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r18697 Thursday 25th October, 2012 at 04:01:46 UTC by Ryan Holtz
01234567890123456789012345678901234567890123456789012345678901234567890123456789 -avr8: Implemented MULS, ANDI, STD Z+, LD -Z, LD Y+, LD -Y, LD -X, SWAP, ASR, ROR, and SBIS opcodes. [MooglyGuy] -avr8: Moved Timer 0-2 into the CPU core itself, 30x driver speedup [MooglyGuy] -cratft.c: Fixed DAC bit order, audio now plays but is 40% too slow [Mooglyguy]

[src/emu/cpu/avr8]	avr8.c avr8.h
[src/mess/drivers]	craft.c uzebox.c
[src/mess/machine]	avr8.h

trunk/src/emu/cpu/avr8/avr8.c

r18696	r18697
21	21	#include "debugger.h"
22	22	#include "avr8.h"
23	23
24		struct avr8_state
	24	#define VERBOSE_LEVEL   (0)
	25
	26	#define ENABLE_VERBOSE_LOG (1)
	27
	28	#if ENABLE_VERBOSE_LOG
	29	INLINE void verboselog(UINT16 pc, int n_level, const char *s_fmt, ...)
25	30	{
26		UINT32 pc;
	31	if( VERBOSE_LEVEL >= n_level )
	32	{
	33	va_list v;
	34	char buf[ 32768 ];
	35	va_start( v, s_fmt );
	36	vsprintf( buf, s_fmt, v );
	37	va_end( v );
	38	logerror( "%05x: %s", pc << 1, buf );
	39	}
	40	}
	41	#else
	42	#define verboselog(x,y,z,...)
	43	#endif
27	44
28		legacy_cpu_device *device;
29		address_space *program;
30		address_space *io;
31		int icount;
32		UINT32 addr_mask;
33		};
34
35	45	enum
36	46	{
37	47	AVR8_SREG_C = 0,
r18696	r18697
44	54	AVR8_SREG_I,
45	55	};
46	56
	57	// I/O Enums
47	58	enum
48	59	{
49		AVR8_IO_SPL = 0x5d,
50		AVR8_IO_SPH = 0x5e,
51		AVR8_IO_SREG = 0x5f,
	60	WGM1_NORMAL = 0,
	61	WGM1_PWM_8_PC,
	62	WGM1_PWM_9_PC,
	63	WGM1_PWM_10_PC,
	64	WGM1_CTC_OCR,
	65	WGM1_FAST_PWM_8,
	66	WGM1_FAST_PWM_9,
	67	WGM1_FAST_PWM_10,
	68	WGM1_PWM_PFC_ICR,
	69	WGM1_PWM_PFC_OCR,
	70	WGM1_PWM_PC_ICR,
	71	WGM1_PWM_PC_OCR,
	72	WGM1_CTC_ICR,
	73	WGM1_RESERVED,
	74	WGM1_FAST_PWM_ICR,
	75	WGM1_FAST_PWM_OCR
52	76	};
53	77
54		#define SREG_R(b) ((READ_IO_8(cpustate, AVR8_IO_SREG) & (1 << (b))) >> (b))
55		#define SREG_W(b,v) WRITE_IO_8(cpustate, AVR8_IO_SREG, (READ_IO_8(cpustate, AVR8_IO_SREG) &~ (1 << (b))) | (((v) ? 1 : 0) << (b)))
	78	enum
	79	{
	80	WGM2_NORMAL = 0,
	81	WGM2_PWM_PC,
	82	WGM2_CTC_CMP,
	83	WGM2_FAST_PWM,
	84	WGM2_RESERVED0,
	85	WGM2_PWM_PC_CMP,
	86	WGM2_RESERVED1,
	87	WGM2_FAST_PWM_CMP
	88	};
	89
	90	static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' };
	91
	92	#define SREG_R(b) ((cpustate->status & (1 << (b))) >> (b))
	93	#define SREG_W(b,v) cpustate->status = (cpustate->status & ~(1 << (b))) | ((v) << (b))
56	94	#define NOT(x) (1 - (x))
57	95
	96	// Opcode-Parsing Defines
58	97	#define RD2(op)         (((op) >> 4) & 0x0003)
59	98	#define RD3(op)         (((op) >> 4) & 0x0007)
60	99	#define RD4(op)         (((op) >> 4) & 0x000f)
r18696	r18697
71	110	#define ACONST5(op)     (((op) >> 3) & 0x001f)
72	111	#define ACONST6(op)     ((((op) >> 5) & 0x0030) | ((op) & 0x000f))
73	112
74		#define XREG            ((READ_IO_8(cpustate, 27) << 8) | READ_IO_8(cpustate, 26))
75		#define YREG            ((READ_IO_8(cpustate, 29) << 8) | READ_IO_8(cpustate, 28))
76		#define ZREG            ((READ_IO_8(cpustate, 31) << 8) | READ_IO_8(cpustate, 30))
77		#define SPREG           ((READ_IO_8(cpustate, AVR8_IO_SPH) << 8) | READ_IO_8(cpustate, AVR8_IO_SPL))
	113	// Register Defines
	114	#define XREG            ((cpustate->r[27] << 8) | cpustate->r[26])
	115	#define YREG            ((cpustate->r[29] << 8) | cpustate->r[28])
	116	#define ZREG            ((cpustate->r[31] << 8) | cpustate->r[30])
	117	#define SPREG         ((cpustate->r[AVR8_REGIDX_SPH] << 8) | cpustate->r[AVR8_REGIDX_SPL])
78	118
	119	// I/O Defines
	120	#define AVR8_OCR1BH            (cpustate->r[AVR8_REGIDX_OCR1BH])
	121	#define AVR8_OCR1BL            (cpustate->r[AVR8_REGIDX_OCR1BL])
	122	#define AVR8_OCR1AH            (cpustate->r[AVR8_REGIDX_OCR1AH])
	123	#define AVR8_OCR1AL            (cpustate->r[AVR8_REGIDX_OCR1AL])
	124	#define AVR8_ICR1H            (cpustate->r[AVR8_REGIDX_ICR1H])
	125	#define AVR8_ICR1L            (cpustate->r[AVR8_REGIDX_ICR1L])
	126	#define AVR8_TCNT1H            (cpustate->r[AVR8_REGIDX_TCNT1H])
	127	#define AVR8_TCNT1L            (cpustate->r[AVR8_REGIDX_TCNT1L])
	128
	129	#define AVR8_TCCR1B               (cpustate->r[AVR8_REGIDX_TCCR1B])
	130	#define AVR8_TCCR1B_ICNC1_MASK      0x80
	131	#define AVR8_TCCR1B_ICNC1_SHIFT      7
	132	#define AVR8_TCCR1B_ICES1_MASK      0x40
	133	#define AVR8_TCCR1B_ICES1_SHIFT      6
	134	#define AVR8_TCCR1B_WGM1_32_MASK   0x18
	135	#define AVR8_TCCR1B_WGM1_32_SHIFT   3
	136	#define AVR8_TCCR1B_CS_MASK         0x07
	137	#define AVR8_TCCR1B_CS_SHIFT      0
	138	#define AVR8_TIMER1_CLOCK_SELECT   (AVR8_TCCR1B & AVR8_TCCR1B_CS_MASK)
	139
	140	#define AVR8_TCCR1A               (cpustate->r[AVR8_REGIDX_TCCR1A])
	141	#define AVR8_TCCR1A_COM1A_MASK      0xc0
	142	#define AVR8_TCCR1A_COM1A_SHIFT      6
	143	#define AVR8_TCCR1A_COM1B_MASK      0x30
	144	#define AVR8_TCCR1A_COM1B_SHIFT      4
	145	#define AVR8_TCCR1A_WGM1_10_MASK   0x03
	146	#define AVR8_TCCR1A_WGM1_10_SHIFT   0
	147	#define AVR8_TCCR1A_COM1A         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT)
	148	#define AVR8_TCCR1A_COM1B         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT)
	149	#define AVR8_TCCR1A_WGM1_10         (AVR8_TCCR1A & AVR8_TCCR1A_WGM1_10_MASK)
	150
	151	#define AVR8_TIMSK1            (cpustate->r[AVR8_REGIDX_TIMSK1])
	152	#define AVR8_TIMSK1_ICIE1_MASK   0x20
	153	#define AVR8_TIMSK1_OCIE1B_MASK   0x04
	154	#define AVR8_TIMSK1_OCIE1A_MASK   0x02
	155	#define AVR8_TIMSK1_TOIE1_MASK   0x01
	156	#define AVR8_TIMSK1_ICIE1      ((AVR8_TIMSK1 & AVR8_TIMSK1_ICIE1_MASK) >> 5)
	157	#define AVR8_TIMSK1_OCIE1B      ((AVR8_TIMSK1 & AVR8_TIMSK1_OCIE1B_MASK) >> 2)
	158	#define AVR8_TIMSK1_OCIE1A      ((AVR8_TIMSK1 & AVR8_TIMSK1_OCIE1A_MASK) >> 1)
	159	#define AVR8_TIMSK1_TOIE1      (AVR8_TIMSK1 & AVR8_TIMSK1_TOIE1_MASK)
	160
	161	#define AVR8_TIFR1            (cpustate->r[AVR8_REGIDX_TIFR1])
	162	#define AVR8_TIFR1_ICF1_MASK   0x20
	163	#define AVR8_TIFR1_ICF1_SHIFT   5
	164	#define AVR8_TIFR1_OCF1B_MASK   0x04
	165	#define AVR8_TIFR1_OCF1B_SHIFT   2
	166	#define AVR8_TIFR1_OCF1A_MASK   0x02
	167	#define AVR8_TIFR1_OCF1A_SHIFT   1
	168	#define AVR8_TIFR1_TOV1_MASK   0x01
	169	#define AVR8_TIFR1_TOV1_SHIFT   0
	170	#define AVR8_TIFR1_MASK         (AVR8_TIFR1_ICF1_MASK | AVR8_TIFR1_TOV1_MASK | \
	171	AVR8_TIFR1_OCF1B_MASK | AVR8_TIFR1_OCF1A_MASK)
	172
	173	#define AVR8_TCCR2B               (cpustate->r[AVR8_REGIDX_TCCR1B])
	174	#define AVR8_TCCR2B_FOC2A_MASK      0x80
	175	#define AVR8_TCCR2B_FOC2A_SHIFT      7
	176	#define AVR8_TCCR2B_FOC2B_MASK      0x40
	177	#define AVR8_TCCR2B_FOC2B_SHIFT      6
	178	#define AVR8_TCCR2B_WGM2_2_MASK      0x08
	179	#define AVR8_TCCR2B_WGM2_2_SHIFT   3
	180	#define AVR8_TCCR2B_CS_MASK         0x07
	181	#define AVR8_TCCR2B_CS_SHIFT      0
	182	#define AVR8_TIMER2_CLOCK_SELECT   (AVR8_TCCR2B & AVR8_TCCR2B_CS_MASK)
	183
	184	#define AVR8_TCCR2A               (cpustate->r[AVR8_REGIDX_TCCR1A])
	185	#define AVR8_TCCR2A_COM2A_MASK      0xc0
	186	#define AVR8_TCCR2A_COM2A_SHIFT      6
	187	#define AVR8_TCCR2A_COM2B_MASK      0x30
	188	#define AVR8_TCCR2A_COM2B_SHIFT      4
	189	#define AVR8_TCCR2A_WGM2_10_MASK   0x03
	190	#define AVR8_TCCR2A_WGM2_10_SHIFT   0
	191	#define AVR8_TCCR2A_COM2A         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2A_MASK) >> AVR8_TCCR2A_COM2A_SHIFT)
	192	#define AVR8_TCCR2A_COM2B         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2B_MASK) >> AVR8_TCCR2A_COM2B_SHIFT)
	193	#define AVR8_TCCR2A_WGM2_10         (AVR8_TCCR2A & AVR8_TCCR1A_WGM2_10_MASK)
	194
	195	#define AVR8_TIMSK2            (cpustate->r[AVR8_REGIDX_TIMSK2])
	196	#define AVR8_TIMSK2_OCIE2B_MASK   0x04
	197	#define AVR8_TIMSK2_OCIE2A_MASK   0x02
	198	#define AVR8_TIMSK2_TOIE2_MASK   0x01
	199	#define AVR8_TIMSK2_OCIE2B      ((AVR8_TIMSK2 & AVR8_TIMSK1_OCIE2B_MASK) >> 2)
	200	#define AVR8_TIMSK2_OCIE2A      ((AVR8_TIMSK2 & AVR8_TIMSK1_OCIE2A_MASK) >> 1)
	201	#define AVR8_TIMSK2_TOIE2      (AVR8_TIMSK2 & AVR8_TIMSK1_TOIE2_MASK)
	202
	203	#define AVR8_TIFR2            (cpustate->r[AVR8_REGIDX_TIFR2])
	204	#define AVR8_TIFR2_OCF2B_MASK   0x04
	205	#define AVR8_TIFR2_OCF2B_SHIFT   2
	206	#define AVR8_TIFR2_OCF2A_MASK   0x02
	207	#define AVR8_TIFR2_OCF2A_SHIFT   1
	208	#define AVR8_TIFR2_TOV2_MASK   0x01
	209	#define AVR8_TIFR2_TOV2_SHIFT   0
	210	#define AVR8_TIFR2_MASK         (AVR8_TIFR2_TOV2_MASK | AVR8_TIFR2_OCF2B_MASK | AVR8_TIFR2_OCF2A_MASK)
	211
	212	#define AVR8_OCR1A            ((AVR8_OCR1AH << 8) | AVR8_OCR1AL)
	213	#define AVR8_OCR1B            ((AVR8_OCR1BH << 8) | AVR8_OCR1BL)
	214	#define AVR8_ICR1            ((AVR8_ICR1H  << 8) | AVR8_ICR1L)
	215	#define AVR8_TCNT1            ((AVR8_TCNT1H << 8) | AVR8_TCNT1L)
	216	#define AVR8_WGM1            (((AVR8_TCCR1B & 0x18) >> 1) | (AVR8_TCCR1A & 0x03))
	217	#define AVR8_TCNT1_DIR         (state->m_tcnt1_direction)
	218
	219	#define AVR8_OCR2B            cpustate->r[AVR8_REGIDX_OCR2B]
	220	#define AVR8_OCR2A            cpustate->r[AVR8_REGIDX_OCR2A]
	221	#define AVR8_TCNT2            cpustate->r[AVR8_REGIDX_TCNT2]
	222	#define AVR8_WGM2            (((AVR8_TCCR2B & 0x08) >> 1) | (AVR8_TCCR2A & 0x03))
	223
	224	#define AVR8_GTCCR_PSRASY_MASK   0x02
	225	#define AVR8_GTCCR_PSRASY_SHIFT   1
	226
79	227	INLINE avr8_state *get_safe_token(device_t *device)
80	228	{
81	229	assert(device != NULL);
r18696	r18697
84	232	}
85	233
86	234	/*****************************************************************************/
	235	// Prototypes
87	236
	237	// - Utility
	238	static void unimplemented_opcode(avr8_state *cpustate, UINT32 op);
	239
	240	// - Interrupts
	241	static void avr8_set_irq_line(avr8_state *cpustate, UINT16 vector, int state);
	242	static void avr8_update_interrupt_internal(avr8_state *cpustate, int source);
	243	static void avr8_poll_interrupt(avr8_state *cpustate);
	244
	245	// - Timers
	246	static void avr8_timer_tick(avr8_state *cpustate, int cycles);
	247
	248	// - Timer 0
	249	static void avr8_timer0_tick(avr8_state *cpustate);
	250
	251	// - Timer 1
	252	static void avr8_timer1_tick(avr8_state *cpustate);
	253	static void avr8_change_timsk1(avr8_state *cpustate, UINT8 data);
	254	static void avr8_update_timer1_waveform_gen_mode(avr8_state *cpustate);
	255	static void avr8_changed_tccr1a(avr8_state *cpustate, UINT8 data);
	256	static void avr8_update_timer1_input_noise_canceler(avr8_state *cpustate);
	257	static void avr8_update_timer1_input_edge_select(avr8_state *cpustate);
	258	static void avr8_update_timer1_clock_source(avr8_state *cpustate);
	259	static void avr8_changed_tccr1b(avr8_state *cpustate, UINT8 data);
	260	static void avr8_update_ocr1(avr8_state *cpustate, UINT16 newval, UINT8 reg);
	261
	262	// - Timer 2
	263	static void avr8_timer2_tick(avr8_state *cpustate);
	264	static void avr8_update_timer2_waveform_gen_mode(avr8_state *cpustate);
	265	static void avr8_changed_tccr2a(avr8_state *cpustate, UINT8 data);
	266	static void avr8_update_timer2_clock_source(avr8_state *cpustate);
	267	static void avr8_timer2_force_output_compare(avr8_state *cpustate, int reg);
	268	static void avr8_changed_tccr2b(avr8_state *cpustate, UINT8 data);
	269	static void avr8_update_ocr2(avr8_state *cpustate, UINT8 newval, UINT8 reg);
	270
	271	// - Register Handling
	272	static bool avr8_io_reg_write(avr8_state *cpustate, UINT16 offset, UINT8 data);
	273	static bool avr8_io_reg_read(avr8_state *cpustate, UINT16 offset, UINT8 *data);
	274
	275	/*****************************************************************************/
	276	// Utility Functions
	277
88	278	static void unimplemented_opcode(avr8_state *cpustate, UINT32 op)
89	279	{
90	280	fatalerror("AVR8: unknown opcode (%08x) at %08x\n", op, cpustate->pc);
91	281	}
92	282
93		/*****************************************************************************/
94
95	283	INLINE bool avr8_is_long_opcode(UINT16 op)
96	284	{
97	285	if((op & 0xf000) == 0x9000)
r18696	r18697
136	324
137	325	INLINE UINT8 READ_IO_8(avr8_state *cpustate, UINT16 address)
138	326	{
	327	if (address < 0x100)
	328	{
	329	// Allow unhandled internal registers to be handled by external driver
	330	UINT8 data;
	331	if (avr8_io_reg_read(cpustate, address, &data))
	332	{
	333	return data;
	334	}
	335	}
139	336	return cpustate->io->read_byte(address);
140	337	}
141	338
142	339	INLINE void WRITE_IO_8(avr8_state *cpustate, UINT16 address, UINT8 data)
143	340	{
	341	if (address < 0x100)
	342	{
	343	// Allow unhandled internal registers to be handled by external driver
	344	if (avr8_io_reg_write(cpustate, address, data))
	345	{
	346	return;
	347	}
	348	}
144	349	cpustate->io->write_byte(address, data);
145	350	}
146	351
147	352	INLINE void PUSH(avr8_state *cpustate, UINT8 val)
148	353	{
149		UINT16 sp = SPREG;
	354	UINT16 sp = SPREG;
150	355	WRITE_IO_8(cpustate, sp, val);
151	356	sp--;
152		//printf( "PUSH %02x, new SP = %04x\n", val, sp );
153		WRITE_IO_8(cpustate, AVR8_IO_SPH, (sp >> 8) & 0x00ff);
154		WRITE_IO_8(cpustate, AVR8_IO_SPL, sp & 0x00ff);
	357	WRITE_IO_8(cpustate, AVR8_REGIDX_SPL, sp & 0x00ff);
	358	WRITE_IO_8(cpustate, AVR8_REGIDX_SPH, (sp >> 8) & 0x00ff);
155	359	}
156	360
157	361	INLINE UINT8 POP(avr8_state *cpustate)
158	362	{
159		UINT16 sp = SPREG;
	363	UINT16 sp = SPREG;
160	364	sp++;
161		WRITE_IO_8(cpustate, AVR8_IO_SPH, (sp >> 8) & 0x00ff);
162		WRITE_IO_8(cpustate, AVR8_IO_SPL, sp & 0x00ff);
163		//printf( "POP %02x, new SP = %04x\n", READ_IO_8(cpustate, sp), sp );
	365	WRITE_IO_8(cpustate, AVR8_REGIDX_SPL, sp & 0x00ff);
	366	WRITE_IO_8(cpustate, AVR8_REGIDX_SPH, (sp >> 8) & 0x00ff);
164	367	return READ_IO_8(cpustate, sp);
165	368	}
166	369
	370	/*****************************************************************************/
	371	// Interrupts
	372
167	373	static void avr8_set_irq_line(avr8_state *cpustate, UINT16 vector, int state)
168	374	{
169	375	// Horrible hack, not accurate
r18696	r18697
172	378	if(SREG_R(AVR8_SREG_I))
173	379	{
174	380	SREG_W(AVR8_SREG_I, 0);
	381	//printf("Push: %04x\n", cpustate->pc);
175	382	PUSH(cpustate, (cpustate->pc >> 8) & 0x00ff);
176	383	PUSH(cpustate, cpustate->pc & 0x00ff);
177	384	cpustate->pc = vector;
	385
	386	//avr8_timer_tick(cpustate, 3);
178	387	}
	388	else
	389	{
	390	cpustate->interrupt_pending = true;
	391	}
179	392	}
180	393	}
181	394
	395	class CInterruptCondition
	396	{
	397	public:
	398	UINT8 m_intindex;
	399	UINT8 m_intreg;
	400	UINT8 m_intmask;
	401	UINT8 m_regindex;
	402	UINT8 m_regmask;
	403	};
	404
	405	static const CInterruptCondition s_int_conditions[AVR8_INTIDX_COUNT] =
	406	{
	407	{ AVR8_INT_SPI_STC, AVR8_REGIDX_SPCR,   AVR8_SPCR_SPIE_MASK,     AVR8_REGIDX_SPSR,    AVR8_SPSR_SPIF_MASK },
	408	{ AVR8_INT_T1CAPT,  AVR8_REGIDX_TIMSK1, AVR8_TIMSK1_ICIE1_MASK,  AVR8_REGIDX_TIFR1,   AVR8_TIFR1_ICF1_MASK },
	409	{ AVR8_INT_T1COMPB, AVR8_REGIDX_TIMSK1, AVR8_TIMSK1_OCIE1B_MASK, AVR8_REGIDX_TIFR1,   AVR8_TIFR1_OCF1B_MASK },
	410	{ AVR8_INT_T1COMPA, AVR8_REGIDX_TIMSK1, AVR8_TIMSK1_OCIE1A_MASK, AVR8_REGIDX_TIFR1,   AVR8_TIFR1_OCF1A_MASK },
	411	{ AVR8_INT_T1OVF,   AVR8_REGIDX_TIMSK1, AVR8_TIMSK1_TOIE1_MASK,  AVR8_REGIDX_TIFR1,   AVR8_TIFR1_TOV1_MASK },
	412	{ AVR8_INT_T2COMPB, AVR8_REGIDX_TIMSK2, AVR8_TIMSK2_OCIE2B_MASK, AVR8_REGIDX_TIFR2,   AVR8_TIFR2_OCF2B_MASK },
	413	{ AVR8_INT_T2COMPA, AVR8_REGIDX_TIMSK2, AVR8_TIMSK2_OCIE2A_MASK, AVR8_REGIDX_TIFR2,   AVR8_TIFR2_OCF2A_MASK },
	414	{ AVR8_INT_T2OVF,   AVR8_REGIDX_TIMSK2, AVR8_TIMSK2_TOIE2_MASK,  AVR8_REGIDX_TIFR2,   AVR8_TIFR2_TOV2_MASK }
	415	};
	416
	417	static void avr8_update_interrupt_internal(avr8_state *cpustate, int source)
	418	{
	419	CInterruptCondition condition = s_int_conditions[source];
	420
	421	int intstate = (cpustate->r[condition.m_regindex] & condition.m_regmask) ? 1 : 0;
	422	intstate = (cpustate->r[condition.m_intreg] & condition.m_intmask) ? intstate : 0;
	423
	424	avr8_set_irq_line(cpustate, condition.m_intindex, intstate);
	425
	426	if (intstate)
	427	{
	428	cpustate->r[condition.m_regindex] &= ~condition.m_regmask;
	429	}
	430	}
	431
	432	static void avr8_poll_interrupt(avr8_state *cpustate)
	433	{
	434	for (int idx = 0; idx < AVR8_INTIDX_COUNT; idx++)
	435	{
	436	avr8_update_interrupt_internal(cpustate, idx);
	437	}
	438	}
	439
	440	void avr8_update_interrupt(device_t *device, int source)
	441	{
	442	avr8_state *cpustate = get_safe_token(device);
	443	avr8_update_interrupt_internal(cpustate, source);
	444	}
	445
182	446	/*****************************************************************************/
	447	// Timers
183	448
	449	static void avr8_timer_tick(avr8_state *cpustate, int cycles)
	450	{
	451	if (cpustate->timer0_prescale != 0)
	452	{
	453	cpustate->timer0_prescale_count += cycles;
	454	while(cpustate->timer0_prescale_count >= cpustate->timer0_prescale)
	455	{
	456	avr8_timer0_tick(cpustate);
	457	cpustate->timer0_prescale_count -= cpustate->timer0_prescale;
	458	}
	459	}
	460
	461	if (cpustate->timer1_prescale != 0)
	462	{
	463	cpustate->timer1_prescale_count += cycles;
	464	while(cpustate->timer1_prescale_count >= cpustate->timer1_prescale)
	465	{
	466	avr8_timer1_tick(cpustate);
	467	cpustate->timer1_prescale_count -= cpustate->timer1_prescale;
	468	}
	469	}
	470
	471	if (cpustate->timer2_prescale != 0)
	472	{
	473	cpustate->timer2_prescale_count += cycles;
	474	while(cpustate->timer2_prescale_count >= (cpustate->timer2_prescale))
	475	{
	476	avr8_timer2_tick(cpustate);
	477	cpustate->timer2_prescale_count -= (cpustate->timer2_prescale);
	478	}
	479	}
	480	}
	481
	482	// Timer 0 Handling
	483	static void avr8_timer0_tick(avr8_state *cpustate)
	484	{
	485	// TODO
	486	}
	487
	488	// Timer 1 Handling
	489
	490	static void avr8_timer1_tick(avr8_state *cpustate)
	491	{
	492	/* TODO: Handle comparison, setting OC1x pins, detection of BOTTOM and TOP */
	493
	494	UINT16 count = (cpustate->r[AVR8_REGIDX_TCNT1H] << 8) | cpustate->r[AVR8_REGIDX_TCNT1L];
	495	INT32 wgm1 = ((cpustate->r[AVR8_REGIDX_TCCR1B] & AVR8_TCCR1B_WGM1_32_MASK) >> 1) |
	496	(cpustate->r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_WGM1_10_MASK);
	497
	498	// Cache things in array form to avoid a compare+branch inside a potentially high-frequency timer
	499	//UINT8 compare_mode[2] = { (cpustate->r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT,
	500	//(cpustate->r[AVR8_REGIDX_TCCR1A] & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT };
	501	UINT16 ocr1[2] = { (cpustate->r[AVR8_REGIDX_OCR1AH] << 8) | cpustate->r[AVR8_REGIDX_OCR1AL],
	502	(cpustate->r[AVR8_REGIDX_OCR1BH] << 8) | cpustate->r[AVR8_REGIDX_OCR1BL] };
	503	UINT8 ocf1[2] = { (1 << AVR8_TIFR1_OCF1A_SHIFT), (1 << AVR8_TIFR1_OCF1B_SHIFT) };
	504	UINT8 int1[2] = { AVR8_INTIDX_OCF1A, AVR8_INTIDX_OCF1B };
	505	INT32 increment = cpustate->timer1_increment;
	506
	507	for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
	508	{
	509	switch(wgm1)
	510	{
	511	case WGM1_FAST_PWM_OCR:
	512	if(count == ocr1[reg])
	513	{
	514	if (reg == 0)
	515	{
	516	cpustate->r[AVR8_REGIDX_TIFR1] |= AVR8_TIFR1_TOV1_MASK;
	517	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_TOV1);
	518	count = 0;
	519	increment = 0;
	520	}
	521
	522	cpustate->r[AVR8_REGIDX_TIFR1] |= ocf1[reg];
	523	avr8_update_interrupt_internal(cpustate, int1[reg]);
	524	}
	525	else if(count == 0)
	526	{
	527	if (reg == 0)
	528	{
	529	cpustate->r[AVR8_REGIDX_TIFR1] &= ~AVR8_TIFR1_TOV1_MASK;
	530	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_TOV1);
	531	}
	532
	533	cpustate->r[AVR8_REGIDX_TIFR1] &= ~ocf1[reg];
	534	avr8_update_interrupt_internal(cpustate, int1[reg]);
	535	}
	536	break;
	537
	538	default:
	539	// TODO
	540	break;
	541	}
	542	/*
	543	switch(compare_mode[reg])
	544	{
	545	case 0:
	546	//verboselog(cpustate->pc, 0, "avr8_update_timer1_compare_mode: Normal port operation (OC1 disconnected)\n");
	547	break;
	548
	549	case 1:
	550	case 2:
	551	// TODO
	552	break;
	553
	554	case 3:
	555	break;
	556	}
	557	*/
	558	}
	559
	560	count += increment;
	561	cpustate->r[AVR8_REGIDX_TCNT1H] = (count >> 8) & 0xff;
	562	cpustate->r[AVR8_REGIDX_TCNT1L] = count & 0xff;
	563	}
	564
	565	static void avr8_change_timsk1(avr8_state *cpustate, UINT8 data)
	566	{
	567	UINT8 oldtimsk = AVR8_TIMSK1;
	568	UINT8 newtimsk = data;
	569	UINT8 changed = newtimsk ^ oldtimsk;
	570
	571	AVR8_TIMSK1 = newtimsk;
	572
	573	if(changed & AVR8_TIMSK1_ICIE1_MASK)
	574	{
	575	// Check for Input Capture Interrupt interrupt condition
	576	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_ICF1);
	577	}
	578
	579	if(changed & AVR8_TIMSK1_OCIE1B_MASK)
	580	{
	581	// Check for Output Compare B Interrupt interrupt condition
	582	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_OCF1B);
	583	}
	584
	585	if(changed & AVR8_TIMSK1_OCIE1A_MASK)
	586	{
	587	// Check for Output Compare A Interrupt interrupt condition
	588	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_OCF1A);
	589	}
	590
	591	if(changed & AVR8_TIMSK1_TOIE1_MASK)
	592	{
	593	// Check for Output Compare A Interrupt interrupt condition
	594	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_TOV1);
	595	}
	596	}
	597
	598	static void avr8_update_timer1_waveform_gen_mode(avr8_state *cpustate)
	599	{
	600	// TODO
	601	cpustate->timer1_top = 0;
	602	verboselog(cpustate->pc, 0, "avr8_update_timer1_waveform_gen_mode: TODO; WGM1 is %d\n", AVR8_WGM1 );
	603	switch(AVR8_WGM1)
	604	{
	605	case WGM1_NORMAL:
	606	cpustate->timer1_top = 0xffff;
	607	break;
	608
	609	case WGM1_PWM_8_PC:
	610	case WGM1_FAST_PWM_8:
	611	cpustate->timer1_top = 0x00ff;
	612	break;
	613
	614	case WGM1_PWM_9_PC:
	615	case WGM1_FAST_PWM_9:
	616	cpustate->timer1_top = 0x01ff;
	617	break;
	618
	619	case WGM1_PWM_10_PC:
	620	case WGM1_FAST_PWM_10:
	621	cpustate->timer1_top = 0x03ff;
	622	break;
	623
	624	case WGM1_PWM_PFC_ICR:
	625	case WGM1_PWM_PC_ICR:
	626	case WGM1_CTC_ICR:
	627	case WGM1_FAST_PWM_ICR:
	628	cpustate->timer1_top = AVR8_ICR1;
	629	break;
	630
	631	case WGM1_PWM_PFC_OCR:
	632	case WGM1_PWM_PC_OCR:
	633	case WGM1_CTC_OCR:
	634	case WGM1_FAST_PWM_OCR:
	635	cpustate->timer1_top = AVR8_OCR1A;
	636	break;
	637
	638	default:
	639	verboselog(cpustate->pc, 0, "avr8_update_timer1_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM1);
	640	break;
	641	}
	642	}
	643
	644	static void avr8_changed_tccr1a(avr8_state *cpustate, UINT8 data)
	645	{
	646	UINT8 oldtccr = AVR8_TCCR1A;
	647	UINT8 newtccr = data;
	648	UINT8 changed = newtccr ^ oldtccr;
	649
	650	cpustate->r[AVR8_REGIDX_TCCR1A] = newtccr;
	651
	652	if(changed & AVR8_TCCR1A_WGM1_10_MASK)
	653	{
	654	// TODO
	655	avr8_update_timer1_waveform_gen_mode(cpustate);
	656	}
	657	}
	658
	659	static void avr8_update_timer1_input_noise_canceler(avr8_state *cpustate)
	660	{
	661	// TODO
	662	}
	663
	664	static void avr8_update_timer1_input_edge_select(avr8_state *cpustate)
	665	{
	666	// TODO
	667	//verboselog(cpustate->pc, 0, "avr8_update_timer1_input_edge_select: TODO; Clocking edge is %s\n", "test");
	668	}
	669
	670	static void avr8_update_timer1_clock_source(avr8_state *cpustate)
	671	{
	672	switch(AVR8_TIMER1_CLOCK_SELECT)
	673	{
	674	case 0: // Counter stopped
	675	cpustate->timer1_prescale = 0;
	676	break;
	677	case 1: // Clk/1; no prescaling
	678	cpustate->timer1_prescale = 1;
	679	break;
	680	case 2: // Clk/8
	681	cpustate->timer1_prescale = 8;
	682	break;
	683	case 3: // Clk/32
	684	cpustate->timer1_prescale = 32;
	685	break;
	686	case 4: // Clk/64
	687	cpustate->timer1_prescale = 64;
	688	break;
	689	case 5: // Clk/128
	690	cpustate->timer1_prescale = 128;
	691	break;
	692	case 6: // T1 trigger, falling edge
	693	case 7: // T1 trigger, rising edge
	694	cpustate->timer1_prescale = 0;
	695	verboselog(cpustate->pc, 0, "avr8_update_timer1_clock_source: T1 Trigger mode not implemented yet\n");
	696	break;
	697	}
	698
	699	if (cpustate->timer1_prescale_count > cpustate->timer1_prescale)
	700	{
	701	cpustate->timer1_prescale_count = cpustate->timer1_prescale - 1;
	702	}
	703	}
	704
	705	static void avr8_changed_tccr1b(avr8_state *cpustate, UINT8 data)
	706	{
	707	UINT8 oldtccr = AVR8_TCCR1B;
	708	UINT8 newtccr = data;
	709	UINT8 changed = newtccr ^ oldtccr;
	710
	711	cpustate->r[AVR8_REGIDX_TCCR1B] = newtccr;
	712
	713	if(changed & AVR8_TCCR1B_ICNC1_MASK)
	714	{
	715	// TODO
	716	avr8_update_timer1_input_noise_canceler(cpustate);
	717	}
	718
	719	if(changed & AVR8_TCCR1B_ICES1_MASK)
	720	{
	721	// TODO
	722	avr8_update_timer1_input_edge_select(cpustate);
	723	}
	724
	725	if(changed & AVR8_TCCR1B_WGM1_32_MASK)
	726	{
	727	// TODO
	728	avr8_update_timer1_waveform_gen_mode(cpustate);
	729	}
	730
	731	if(changed & AVR8_TCCR1B_CS_MASK)
	732	{
	733	avr8_update_timer1_clock_source(cpustate);
	734	}
	735	}
	736
	737	static void avr8_update_ocr1(avr8_state *cpustate, UINT16 newval, UINT8 reg)
	738	{
	739	UINT8 *p_reg_h = (reg == AVR8_REG_A) ? &cpustate->r[AVR8_REGIDX_OCR1AH] : &cpustate->r[AVR8_REGIDX_OCR1BH];
	740	UINT8 *p_reg_l = (reg == AVR8_REG_A) ? &cpustate->r[AVR8_REGIDX_OCR1AL] : &cpustate->r[AVR8_REGIDX_OCR1BL];
	741	*p_reg_h = (UINT8)(newval >> 8);
	742	*p_reg_l = (UINT8)newval;
	743
	744	// Nothing needs to be done? All handled in timer callback
	745	}
	746
	747	// Timer 2 Handling
	748
	749	static void avr8_timer2_tick(avr8_state *cpustate)
	750	{
	751	UINT16 count = cpustate->r[AVR8_REGIDX_TCNT2];
	752	INT32 wgm2 = ((cpustate->r[AVR8_REGIDX_TCCR2B] & AVR8_TCCR2B_WGM2_2_MASK) >> 1) |
	753	(cpustate->r[AVR8_REGIDX_TCCR2A] & AVR8_TCCR2A_WGM2_10_MASK);
	754
	755	// Cache things in array form to avoid a compare+branch inside a potentially high-frequency timer
	756	//UINT8 compare_mode[2] = { (cpustate->r[AVR8_REGIDX_TCCR2A] & AVR8_TCCR2A_COM2A_MASK) >> AVR8_TCCR2A_COM2A_SHIFT,
	757	//(cpustate->r[AVR8_REGIDX_TCCR2A] & AVR8_TCCR2A_COM2B_MASK) >> AVR8_TCCR2A_COM2B_SHIFT };
	758	UINT8 ocr2[2] = { cpustate->r[AVR8_REGIDX_OCR2A], cpustate->r[AVR8_REGIDX_OCR2B] };
	759	UINT8 ocf2[2] = { (1 << AVR8_TIFR2_OCF2A_SHIFT), (1 << AVR8_TIFR2_OCF2B_SHIFT) };
	760	INT32 increment = cpustate->timer2_increment;
	761
	762	for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
	763	{
	764	switch(wgm2)
	765	{
	766	case WGM2_FAST_PWM_CMP:
	767	if(count == ocr2[reg])
	768	{
	769	if (reg == 0)
	770	{
	771	cpustate->r[AVR8_REGIDX_TIFR2] |= AVR8_TIFR2_TOV2_MASK;
	772	count = 0;
	773	increment = 0;
	774	}
	775
	776	cpustate->r[AVR8_REGIDX_TIFR2] |= ocf2[reg];
	777	}
	778	else if(count == 0)
	779	{
	780	if (reg == 0)
	781	{
	782	cpustate->r[AVR8_REGIDX_TIFR2] &= ~AVR8_TIFR2_TOV2_MASK;
	783	}
	784	}
	785	break;
	786
	787	default:
	788	// TODO
	789	break;
	790	}
	791	/*
	792	switch(compare_mode[reg])
	793	{
	794	case 0:
	795	//verboselog(cpustate->pc, 0, "avr8_update_timer2_compare_mode: Normal port operation (OC2 disconnected)\n");
	796	break;
	797
	798	case 1:
	799	case 2:
	800	// TODO
	801	break;
	802
	803	case 3:
	804	break;
	805	}
	806	*/
	807	}
	808
	809	cpustate->r[AVR8_REGIDX_TCNT2] = count + increment;
	810
	811	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_OCF2A);
	812	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_OCF2B);
	813	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_TOV2);
	814	}
	815
	816	static void avr8_update_timer2_waveform_gen_mode(avr8_state *cpustate)
	817	{
	818	cpustate->timer2_top = 0;
	819	switch(AVR8_WGM2)
	820	{
	821	case WGM2_NORMAL:
	822	case WGM2_PWM_PC:
	823	case WGM2_FAST_PWM:
	824	cpustate->timer2_top = 0x00ff;
	825	break;
	826
	827	case WGM2_CTC_CMP:
	828	case WGM2_PWM_PC_CMP:
	829	case WGM2_FAST_PWM_CMP:
	830	cpustate->timer2_top = AVR8_OCR2A;
	831	break;
	832
	833	default:
	834	verboselog(cpustate->pc, 0, "avr8_update_timer2_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM2);
	835	break;
	836	}
	837	}
	838
	839	static void avr8_changed_tccr2a(avr8_state *cpustate, UINT8 data)
	840	{
	841	UINT8 oldtccr = AVR8_TCCR2A;
	842	UINT8 newtccr = data;
	843	UINT8 changed = newtccr ^ oldtccr;
	844
	845	if(changed & AVR8_TCCR2A_WGM2_10_MASK)
	846	{
	847	// TODO
	848	avr8_update_timer2_waveform_gen_mode(cpustate);
	849	}
	850	}
	851
	852	static void avr8_update_timer2_clock_source(avr8_state *cpustate)
	853	{
	854	switch(AVR8_TIMER2_CLOCK_SELECT)
	855	{
	856	case 0: // Counter stopped
	857	cpustate->timer2_prescale = 0;
	858	break;
	859	case 1: // Clk/1; no prescaling
	860	cpustate->timer2_prescale = 1;
	861	break;
	862	case 2: // Clk/8
	863	cpustate->timer2_prescale = 8;
	864	break;
	865	case 3: // Clk/32
	866	cpustate->timer2_prescale = 32;
	867	break;
	868	case 4: // Clk/64
	869	cpustate->timer2_prescale = 64;
	870	break;
	871	case 5: // Clk/128
	872	cpustate->timer2_prescale = 128;
	873	break;
	874	case 6: // Clk/256
	875	cpustate->timer2_prescale = 256;
	876	break;
	877	case 7: // Clk/1024
	878	cpustate->timer2_prescale = 1024;
	879	break;
	880	}
	881
	882	if (cpustate->timer2_prescale_count > cpustate->timer2_prescale)
	883	{
	884	cpustate->timer2_prescale_count = cpustate->timer2_prescale - 1;
	885	}
	886	}
	887
	888	static void avr8_timer2_force_output_compare(avr8_state *cpustate, int reg)
	889	{
	890	// TODO
	891	verboselog(cpustate->pc, 0, "avr8_force_output_compare: TODO; should be forcing OC2%c\n", avr8_reg_name[reg]);
	892	}
	893
	894	static void avr8_changed_tccr2b(avr8_state *cpustate, UINT8 data)
	895	{
	896	UINT8 oldtccr = AVR8_TCCR2B;
	897	UINT8 newtccr = data;
	898	UINT8 changed = newtccr ^ oldtccr;
	899
	900	if(changed & AVR8_TCCR2B_FOC2A_MASK)
	901	{
	902	// TODO
	903	avr8_timer2_force_output_compare(cpustate, AVR8_REG_A);
	904	}
	905
	906	if(changed & AVR8_TCCR2B_FOC2B_MASK)
	907	{
	908	// TODO
	909	avr8_timer2_force_output_compare(cpustate, AVR8_REG_B);
	910	}
	911
	912	if(changed & AVR8_TCCR2B_WGM2_2_MASK)
	913	{
	914	// TODO
	915	avr8_update_timer2_waveform_gen_mode(cpustate);
	916	}
	917
	918	if(changed & AVR8_TCCR2B_CS_MASK)
	919	{
	920	avr8_update_timer2_clock_source(cpustate);
	921	}
	922	}
	923
	924	static void avr8_update_ocr2(avr8_state *cpustate, UINT8 newval, UINT8 reg)
	925	{
	926	cpustate->r[(reg == AVR8_REG_A) ? AVR8_REGIDX_OCR2A : AVR8_REGIDX_OCR2B] = newval;
	927
	928	// Nothing needs to be done? All handled in timer callback
	929	}
	930
	931	/*****************************************************************************/
	932
	933	static bool avr8_io_reg_write(avr8_state *cpustate, UINT16 offset, UINT8 data)
	934	{
	935	switch( offset )
	936	{
	937	case AVR8_REGIDX_OCR1BH:
	938	verboselog(cpustate->pc, 0, "AVR8: OCR1BH = %02x\n", data );
	939	avr8_update_ocr1(cpustate, (AVR8_OCR1B & 0x00ff) | (data << 8), AVR8_REG_B);
	940	return true;
	941
	942	case AVR8_REGIDX_OCR1BL:
	943	verboselog(cpustate->pc, 0, "AVR8: OCR1BL = %02x\n", data );
	944	avr8_update_ocr1(cpustate, (AVR8_OCR1B & 0xff00) | data, AVR8_REG_B);
	945	return true;
	946
	947	case AVR8_REGIDX_OCR1AH:
	948	verboselog(cpustate->pc, 0, "AVR8: OCR1AH = %02x\n", data );
	949	avr8_update_ocr1(cpustate, (AVR8_OCR1A & 0x00ff) | (data << 8), AVR8_REG_A);
	950	return true;
	951
	952	case AVR8_REGIDX_OCR1AL:
	953	verboselog(cpustate->pc, 0, "AVR8: OCR1AL = %02x\n", data );
	954	avr8_update_ocr1(cpustate, (AVR8_OCR1A & 0xff00) | data, AVR8_REG_A);
	955	return true;
	956
	957	case AVR8_REGIDX_TCCR1B:
	958	verboselog(cpustate->pc, 0, "AVR8: TCCR1B = %02x\n", data );
	959	avr8_changed_tccr1b(cpustate, data);
	960	return true;
	961
	962	case AVR8_REGIDX_TCCR1A:
	963	verboselog(cpustate->pc, 0, "AVR8: TCCR1A = %02x\n", data );
	964	avr8_changed_tccr1a(cpustate, data);
	965	return true;
	966
	967	case AVR8_REGIDX_TIMSK1:
	968	verboselog(cpustate->pc, 0, "AVR8: TIMSK1 = %02x\n", data );
	969	avr8_change_timsk1(cpustate, data);
	970	return true;
	971
	972	case AVR8_REGIDX_TIFR1:
	973	verboselog(cpustate->pc, 0, "AVR8: TIFR1 = %02x\n", data );
	974	cpustate->r[AVR8_REGIDX_TIFR1] &= ~(data & AVR8_TIFR1_MASK);
	975	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_ICF1);
	976	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_OCF1A);
	977	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_OCF1B);
	978	avr8_update_interrupt_internal(cpustate, AVR8_INTIDX_TOV1);
	979	return true;
	980
	981	case AVR8_REGIDX_TCCR2B:
	982	verboselog(cpustate->pc, 0, "AVR8: TCCR2B = %02x\n", data );
	983	avr8_changed_tccr2b(cpustate, data);
	984	return true;
	985
	986	case AVR8_REGIDX_TCCR2A:
	987	verboselog(cpustate->pc, 0, "AVR8: TCCR2A = %02x\n", data );
	988	avr8_changed_tccr2a(cpustate, data);
	989	return true;
	990
	991	case AVR8_REGIDX_OCR2A:
	992	avr8_update_ocr2(cpustate, data, AVR8_REG_A);
	993	return true;
	994
	995	case AVR8_REGIDX_OCR2B:
	996	avr8_update_ocr2(cpustate, data, AVR8_REG_B);
	997	return true;
	998
	999	case AVR8_REGIDX_TCNT2:
	1000	AVR8_TCNT2 = data;
	1001	return true;
	1002
	1003	case AVR8_REGIDX_GTCCR:
	1004	if (data & AVR8_GTCCR_PSRASY_MASK)
	1005	{
	1006	data &= ~AVR8_GTCCR_PSRASY_MASK;
	1007	cpustate->timer2_prescale_count = 0;
	1008	}
	1009	//verboselog(cpustate->pc, 0, "AVR8: GTCCR = %02x\n", data );
	1010	// TODO
	1011	return true;
	1012
	1013	case AVR8_REGIDX_SPL:
	1014	case AVR8_REGIDX_SPH:
	1015	case AVR8_REGIDX_GPIOR0:
	1016	cpustate->r[offset] = data;
	1017	return true;
	1018
	1019	case AVR8_REGIDX_SREG:
	1020	cpustate->status = data;
	1021	return true;
	1022
	1023	default:
	1024	verboselog(cpustate->pc, 0, "AVR8: Unrecognized register write: %02x = %02x\n", offset, data );
	1025	return false;
	1026	}
	1027	return false;
	1028	}
	1029
	1030	static bool avr8_io_reg_read(avr8_state *cpustate, UINT16 offset, UINT8 *data)
	1031	{
	1032	switch( offset )
	1033	{
	1034	case AVR8_REGIDX_SPL:
	1035	case AVR8_REGIDX_SPH:
	1036	case AVR8_REGIDX_TCNT1L:
	1037	case AVR8_REGIDX_TCNT1H:
	1038	case AVR8_REGIDX_GPIOR0:
	1039	*data = cpustate->r[offset];
	1040	return true;
	1041
	1042	case AVR8_REGIDX_SREG:
	1043	*data = cpustate->status;
	1044	return true;
	1045
	1046	default:
	1047	verboselog(cpustate->pc, 0, "AVR8: Unrecognized register read: %02x\n", offset );
	1048	return false;
	1049	}
	1050
	1051	return false;
	1052	}
	1053
	1054	/*****************************************************************************/
	1055
184	1056	static CPU_INIT( avr8 )
185	1057	{
186	1058	avr8_state *cpustate = get_safe_token(device);
r18696	r18697
191	1063	cpustate->program = &device->space(AS_PROGRAM);
192	1064	cpustate->io = &device->space(AS_IO);
193	1065
194		WRITE_IO_8(cpustate, AVR8_IO_SREG, 0);
	1066	cpustate->status = 0;
	1067	WRITE_IO_8(cpustate, AVR8_REGIDX_SPL, 0);
	1068	WRITE_IO_8(cpustate, AVR8_REGIDX_SPH, 0);
195	1069
	1070	for (int i = 0; i < 32; i++)
	1071	{
	1072	cpustate->r[i] = 0;
	1073	}
	1074
	1075	cpustate->timer0_top = 0;
	1076	cpustate->timer0_increment = 1;
	1077	cpustate->timer0_prescale = 0;
	1078	cpustate->timer0_prescale_count = 0;
	1079
	1080	cpustate->timer1_top = 0;
	1081	cpustate->timer1_increment = 1;
	1082	cpustate->timer1_prescale = 0;
	1083	cpustate->timer1_prescale_count = 0;
	1084
	1085	cpustate->timer2_top = 0;
	1086	cpustate->timer2_increment = 1;
	1087	cpustate->timer2_prescale = 0;
	1088	cpustate->timer2_prescale_count = 0;
	1089
	1090	AVR8_TIMSK1 = 0;
	1091	AVR8_OCR1AH = 0;
	1092	AVR8_OCR1AL = 0;
	1093	AVR8_OCR1BH = 0;
	1094	AVR8_OCR1BL = 0;
	1095	AVR8_ICR1H = 0;
	1096	AVR8_ICR1L = 0;
	1097	AVR8_TCNT1H = 0;
	1098	AVR8_TCNT1L = 0;
	1099	AVR8_TCNT2 = 0;
	1100
	1101	cpustate->interrupt_pending = false;
	1102
196	1103	device->save_item(NAME(cpustate->pc));
197	1104	}
198	1105
r18696	r18697
204	1111	{
205	1112	avr8_state *cpustate = get_safe_token(device);
206	1113
207		WRITE_IO_8(cpustate, AVR8_IO_SREG, 0);
	1114	cpustate->status = 0;
208	1115	cpustate->pc = 0;
	1116
	1117	cpustate->interrupt_pending = false;
209	1118	}
210	1119
211	1120	static CPU_EXECUTE( avr8 )
r18696	r18697
237	1146	case 0x0000:    // NOP
238	1147	break;
239	1148	case 0x0100:    // MOVW Rd+1:Rd,Rr+1:Rd
240		WRITE_IO_8(cpustate, (RD4(op) << 1)+1, READ_IO_8(cpustate, (RR4(op) << 1)+1));
241		WRITE_IO_8(cpustate, RD4(op) << 1, READ_IO_8(cpustate, RR4(op) << 1));
	1149	cpustate->r[(RD4(op) << 1) + 1] = cpustate->r[(RR4(op) << 1) + 1];
	1150	cpustate->r[RD4(op) << 1] = cpustate->r[RR4(op) << 1];
242	1151	break;
243	1152	case 0x0200:    // MULS Rd,Rr
244		//output += sprintf( output, "MULS    R%d, R%d", 16+RD4(op), 16+RR4(op) );
245		unimplemented_opcode(cpustate, op);
	1153	sd = (INT8)cpustate->r[16 + RD4(op)] * (INT8)cpustate->r[16 + RR4(op)];
	1154	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1155	cpustate->r[0] = sd & 0x00ff;
	1156	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
	1157	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
	1158	opcycles = 2;
246	1159	break;
247	1160	case 0x0300:    // MULSU Rd,Rr
248		sd = (INT8)READ_IO_8(cpustate, 16+RD4(op)) * (UINT8)READ_IO_8(cpustate, 16+RR4(op));
249		WRITE_IO_8(cpustate, 1, (sd >> 8) & 0x00ff);
250		WRITE_IO_8(cpustate, 0, sd & 0x00ff);
	1161	sd = (INT8)cpustate->r[16 + RD4(op)] * (UINT8)cpustate->r[16 + RR4(op)];
	1162	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1163	cpustate->r[0] = sd & 0x00ff;
251	1164	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
252	1165	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
253	1166	opcycles = 2;
r18696	r18697
256	1169	case 0x0500:
257	1170	case 0x0600:
258	1171	case 0x0700:    // CPC Rd,Rr
259		rd = READ_IO_8(cpustate, RD5(op));
260		rr = READ_IO_8(cpustate, RR5(op));
	1172	rd = cpustate->r[RD5(op)];
	1173	rr = cpustate->r[RR5(op)];
261	1174	res = rd - (rr + SREG_R(AVR8_SREG_C));
262	1175	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
263	1176	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
r18696	r18697
270	1183	case 0x0900:
271	1184	case 0x0a00:
272	1185	case 0x0b00:    // SBC Rd,Rr
273		rd = READ_IO_8(cpustate, RD5(op));
274		rr = READ_IO_8(cpustate, RR5(op));
	1186	rd = cpustate->r[RD5(op)];
	1187	rr = cpustate->r[RR5(op)];
275	1188	res = rd - (rr + SREG_R(AVR8_SREG_C));
276		WRITE_IO_8(cpustate, RD5(op), res);
	1189	cpustate->r[RD5(op)] = res;
277	1190	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
278	1191	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
279	1192	SREG_W(AVR8_SREG_N, BIT(res,7));
r18696	r18697
285	1198	case 0x0d00:
286	1199	case 0x0e00:
287	1200	case 0x0f00:    // ADD Rd,Rr
288		rd = READ_IO_8(cpustate, RD5(op));
289		rr = READ_IO_8(cpustate, RR5(op));
	1201	rd = cpustate->r[RD5(op)];
	1202	rr = cpustate->r[RR5(op)];
290	1203	res = rd + rr;
291		WRITE_IO_8(cpustate, RD5(op), res);
	1204	cpustate->r[RD5(op)] = res;
292	1205	SREG_W(AVR8_SREG_H, (BIT(rd,3) & BIT(rr,3)) | (BIT(rr,3) & NOT(BIT(res,3))) | (NOT(BIT(res,3)) & BIT(rd,3)));
293	1206	SREG_W(AVR8_SREG_V, (BIT(rd,7) & BIT(rr,7) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & NOT(BIT(rr,7)) & BIT(res,7)));
294	1207	SREG_W(AVR8_SREG_N, BIT(res,7));
r18696	r18697
306	1219	unimplemented_opcode(cpustate, op);
307	1220	break;
308	1221	case 0x0400:    // CP Rd,Rr
309		rd = READ_IO_8(cpustate, RD5(op));
310		rr = READ_IO_8(cpustate, RR5(op));
	1222	rd = cpustate->r[RD5(op)];
	1223	rr = cpustate->r[RR5(op)];
311	1224	res = rd - rr;
312	1225	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
313	1226	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
r18696	r18697
317	1230	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
318	1231	break;
319	1232	case 0x0800:    // SUB Rd,Rr
320		rd = READ_IO_8(cpustate, RD5(op));
321		rr = READ_IO_8(cpustate, RR5(op));
	1233	rd = cpustate->r[RD5(op)];
	1234	rr = cpustate->r[RR5(op)];
322	1235	res = rd - rr;
323		WRITE_IO_8(cpustate, RD5(op), res);
	1236	cpustate->r[RD5(op)] = res;
324	1237	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
325	1238	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
326	1239	SREG_W(AVR8_SREG_N, BIT(res,7));
r18696	r18697
329	1242	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
330	1243	break;
331	1244	case 0x0c00:    // ADC Rd,Rr
332		rd = READ_IO_8(cpustate, RD5(op));
333		rr = READ_IO_8(cpustate, RR5(op));
	1245	rd = cpustate->r[RD5(op)];
	1246	rr = cpustate->r[RR5(op)];
334	1247	res = rd + rr + SREG_R(AVR8_SREG_C);
335		WRITE_IO_8(cpustate, RD5(op), res);
	1248	cpustate->r[RD5(op)] = res;
336	1249	SREG_W(AVR8_SREG_H, (BIT(rd,3) & BIT(rr,3)) | (BIT(rr,3) & NOT(BIT(res,3))) | (NOT(BIT(res,3)) & BIT(rd,3)));
337	1250	SREG_W(AVR8_SREG_V, (BIT(rd,7) & BIT(rr,7) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & NOT(BIT(rr,7)) & BIT(res,7)));
338	1251	SREG_W(AVR8_SREG_N, BIT(res,7));
r18696	r18697
346	1259	switch(op & 0x0c00)
347	1260	{
348	1261	case 0x0000:    // AND Rd,Rr
349		//output += sprintf( output, "AND     R%d, R%d", RD5(op), RR5(op) );
350		rd = READ_IO_8(cpustate, RD5(op));
351		rr = READ_IO_8(cpustate, RR5(op));
	1262	rd = cpustate->r[RD5(op)];
	1263	rr = cpustate->r[RR5(op)];
352	1264	rd &= rr;
353	1265	SREG_W(AVR8_SREG_V, 0);
354	1266	SREG_W(AVR8_SREG_N, rd & 0x80);
355	1267	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
356	1268	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
357		WRITE_IO_8(cpustate, RD5(op), rd);
	1269	cpustate->r[RD5(op)] = rd;
358	1270	break;
359	1271	case 0x0400:    // EOR Rd,Rr
360		rd = READ_IO_8(cpustate, RD5(op));
361		rr = READ_IO_8(cpustate, RR5(op));
	1272	rd = cpustate->r[RD5(op)];
	1273	rr = cpustate->r[RR5(op)];
362	1274	rd ^= rr;
363	1275	SREG_W(AVR8_SREG_V, 0);
364	1276	SREG_W(AVR8_SREG_N, rd & 0x80);
365	1277	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
366	1278	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
367		WRITE_IO_8(cpustate, RD5(op), rd);
	1279	cpustate->r[RD5(op)] = rd;
368	1280	break;
369	1281	case 0x0800:    // OR Rd,Rr
370		rd = READ_IO_8(cpustate, RD5(op));
371		rr = READ_IO_8(cpustate, RR5(op));
	1282	rd = cpustate->r[RD5(op)];
	1283	rr = cpustate->r[RR5(op)];
372	1284	rd |= rr;
373	1285	SREG_W(AVR8_SREG_V, 0);
374	1286	SREG_W(AVR8_SREG_N, rd & 0x80);
375	1287	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
376	1288	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
377		WRITE_IO_8(cpustate, RD5(op), rd);
	1289	cpustate->r[RD5(op)] = rd;
378	1290	break;
379	1291	case 0x0c00:    // MOV Rd,Rr
380		WRITE_IO_8(cpustate, RD5(op), READ_IO_8(cpustate, RR5(op)));
	1292	cpustate->r[RD5(op)] = cpustate->r[RR5(op)];
381	1293	break;
382	1294	}
383	1295	break;
384	1296	case 0x3000:    // CPI Rd,K
385		rd = READ_IO_8(cpustate, 16+RD4(op));
	1297	rd = cpustate->r[16 + RD4(op)];
386	1298	rr = KCONST8(op);
387	1299	res = rd - rr;
388	1300	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
r18696	r18697
393	1305	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
394	1306	break;
395	1307	case 0x4000:    // SBCI Rd,K
396		rd = READ_IO_8(cpustate, 16+RD4(op));
	1308	rd = cpustate->r[16 + RD4(op)];
397	1309	rr = KCONST8(op);
398	1310	res = rd - (rr + SREG_R(AVR8_SREG_C));
399		WRITE_IO_8(cpustate, 16+RD4(op), res);
	1311	cpustate->r[16 + RD4(op)] = res;
400	1312	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
401	1313	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
402	1314	SREG_W(AVR8_SREG_N, BIT(res,7));
r18696	r18697
405	1317	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
406	1318	break;
407	1319	case 0x5000:    // SUBI Rd,K
408		rd = READ_IO_8(cpustate, 16+RD4(op));
	1320	rd = cpustate->r[16 + RD4(op)];
409	1321	rr = KCONST8(op);
410	1322	res = rd - rr;
411		WRITE_IO_8(cpustate, 16+RD4(op), res);
	1323	cpustate->r[16 + RD4(op)] = res;
412	1324	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
413	1325	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
414	1326	SREG_W(AVR8_SREG_N, BIT(res,7));
r18696	r18697
417	1329	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
418	1330	break;
419	1331	case 0x6000:    // ORI Rd,K
420		rd = READ_IO_8(cpustate, 16+RD4(op));
	1332	rd = cpustate->r[16 + RD4(op)];
421	1333	rr = KCONST8(op);
422	1334	rd |= rr;
423	1335	SREG_W(AVR8_SREG_V, 0);
424	1336	SREG_W(AVR8_SREG_N, rd & 0x80);
425	1337	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
426	1338	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
427		WRITE_IO_8(cpustate, 16+RD4(op), rd);
	1339	cpustate->r[16 + RD4(op)] = rd;
428	1340	break;
429	1341	case 0x7000:    // ANDI Rd,K
430		//output += sprintf( output, "ANDI    R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
431		unimplemented_opcode(cpustate, op);
	1342	rd = cpustate->r[16 + RD4(op)];
	1343	rr = KCONST8(op);
	1344	rd &= rr;
	1345	SREG_W(AVR8_SREG_V, 0);
	1346	SREG_W(AVR8_SREG_N, rd & 0x80);
	1347	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	1348	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
	1349	cpustate->r[16 + RD4(op)] = rd;
432	1350	break;
433	1351	case 0x8000:
434	1352	case 0xa000:
r18696	r18697
439	1357	unimplemented_opcode(cpustate, op);
440	1358	break;
441	1359	case 0x0008:    // LDD Rd,Y+q
442		WRITE_IO_8(cpustate, RD5(op), YREG + QCONST6(op));
	1360	cpustate->r[RD5(op)] = READ_IO_8(cpustate, YREG + QCONST6(op));
443	1361	opcycles = 2;
444	1362	break;
445	1363	case 0x0200:    // STD Z+q,Rr
446		//output += sprintf( output, "ST(D)   Z+%02x, R%d", QCONST6(op), RD5(op) );
447		unimplemented_opcode(cpustate, op);
	1364	WRITE_IO_8(cpustate, ZREG + QCONST6(op), cpustate->r[RD5(op)]);
	1365	opcycles = 2;
448	1366	break;
449	1367	case 0x0208:    // STD Y+q,Rr
450		WRITE_IO_8(cpustate, YREG + QCONST6(op), READ_IO_8(cpustate, RD5(op)));
	1368	WRITE_IO_8(cpustate, YREG + QCONST6(op), cpustate->r[RD5(op)]);
451	1369	opcycles = 2;
452	1370	break;
453	1371	}
r18696	r18697
463	1381	op <<= 16;
464	1382	cpustate->pc++;
465	1383	op |= READ_PRG_16(cpustate, cpustate->pc);
466		WRITE_IO_8(cpustate, RD5(op >> 16), READ_IO_8(cpustate, op & 0x0000ffff));
	1384	cpustate->r[RD5(op >> 16)] = READ_IO_8(cpustate, op & 0x0000ffff);
467	1385	opcycles = 2;
468	1386	break;
469	1387	case 0x0001:    // LD Rd,Z+
470	1388	unimplemented_opcode(cpustate, op);
471	1389	break;
472	1390	case 0x0002:    // LD Rd,-Z
473		//output += sprintf( output, "LD      R%d,-Z", RD5(op) );
474		unimplemented_opcode(cpustate, op);
	1391	pd = ZREG;
	1392	pd--;
	1393	cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
	1394	cpustate->r[27] = (pd >> 8) & 0x00ff;
	1395	cpustate->r[26] = pd & 0x00ff;
	1396	opcycles = 2;
475	1397	break;
476	1398	case 0x0004:    // LPM Rd,Z
477		WRITE_IO_8(cpustate, RD5(op), READ_PRG_8(cpustate, ZREG));
	1399	cpustate->r[RD5(op)] = READ_PRG_8(cpustate, ZREG);
478	1400	opcycles = 3;
479	1401	break;
480	1402	case 0x0005:    // LPM Rd,Z+
481	1403	pd = ZREG;
482		WRITE_IO_8(cpustate, RD5(op), READ_PRG_8(cpustate, pd));
	1404	cpustate->r[RD5(op)] = READ_PRG_8(cpustate, pd);
483	1405	pd++;
484		WRITE_IO_8(cpustate, 31, (pd >> 8) & 0x00ff);
485		WRITE_IO_8(cpustate, 30, pd & 0x00ff);
	1406	cpustate->r[31] = (pd >> 8) & 0x00ff;
	1407	cpustate->r[30] = pd & 0x00ff;
486	1408	opcycles = 3;
487	1409	break;
488	1410	case 0x0006:    // ELPM Rd,Z
r18696	r18697
494	1416	unimplemented_opcode(cpustate, op);
495	1417	break;
496	1418	case 0x0009:    // LD Rd,Y+
497		//output += sprintf( output, "LD      R%d, Y+", RD5(op) );
498		unimplemented_opcode(cpustate, op);
	1419	pd = YREG;
	1420	cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
	1421	pd++;
	1422	cpustate->r[29] = (pd >> 8) & 0x00ff;
	1423	cpustate->r[28] = pd & 0x00ff;
	1424	opcycles = 2;
499	1425	break;
500	1426	case 0x000a:    // LD Rd,-Y
501		//output += sprintf( output, "LD      R%d,-Y", RD5(op) );
502		unimplemented_opcode(cpustate, op);
	1427	pd = YREG;
	1428	pd--;
	1429	cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
	1430	cpustate->r[27] = (pd >> 8) & 0x00ff;
	1431	cpustate->r[26] = pd & 0x00ff;
	1432	opcycles = 2;
503	1433	break;
504	1434	case 0x000c:    // LD Rd,X
505		//output += sprintf( output, "LD      R%d, X", RD5(op) );
506		unimplemented_opcode(cpustate, op);
	1435	cpustate->r[RD5(op)] = READ_IO_8(cpustate, XREG);
507	1436	break;
508	1437	case 0x000d:    // LD Rd,X+
509	1438	pd = XREG;
510		WRITE_IO_8(cpustate, RD5(op), READ_IO_8(cpustate, pd));
	1439	cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
511	1440	pd++;
512		WRITE_IO_8(cpustate, 27, (pd >> 8) & 0x00ff);
513		WRITE_IO_8(cpustate, 26, pd & 0x00ff);
	1441	cpustate->r[27] = (pd >> 8) & 0x00ff;
	1442	cpustate->r[26] = pd & 0x00ff;
514	1443	opcycles = 2;
515	1444	break;
516	1445	case 0x000e:    // LD Rd,-X
517		//output += sprintf( output, "LD      R%d,-X", RD5(op) );
518		unimplemented_opcode(cpustate, op);
	1446	pd = XREG;
	1447	pd--;
	1448	cpustate->r[RD5(op)] = READ_IO_8(cpustate, pd);
	1449	cpustate->r[27] = (pd >> 8) & 0x00ff;
	1450	cpustate->r[26] = pd & 0x00ff;
	1451	opcycles = 2;
519	1452	break;
520	1453	case 0x000f:    // POP Rd
521		WRITE_IO_8(cpustate, RD5(op), POP(cpustate));
	1454	cpustate->r[RD5(op)] = POP(cpustate);
522	1455	opcycles = 2;
523	1456	break;
524	1457	default:
r18696	r18697
535	1468	op <<= 16;
536	1469	cpustate->pc++;
537	1470	op |= READ_PRG_16(cpustate, cpustate->pc);
538		WRITE_IO_8(cpustate, op & 0x0000ffff, READ_IO_8(cpustate, RD5(op >> 16)));
	1471	WRITE_IO_8(cpustate, op & 0x0000ffff, cpustate->r[RD5(op >> 16)]);
539	1472	opcycles = 2;
540	1473	break;
541	1474	case 0x0001:    // ST Z+,Rd
r18696	r18697
548	1481	break;
549	1482	case 0x0009:    // ST Y+,Rd
550	1483	pd = YREG;
551		WRITE_IO_8(cpustate, pd, READ_IO_8(cpustate, RD5(op)));
	1484	WRITE_IO_8(cpustate, pd, cpustate->r[RD5(op)]);
552	1485	pd++;
553		WRITE_IO_8(cpustate, 29, (pd >> 8) & 0x00ff);
554		WRITE_IO_8(cpustate, 28, pd & 0x00ff);
555		opcycles = 2;
	1486	cpustate->r[29] = (pd >> 8) & 0x00ff;
	1487	cpustate->r[28] = pd & 0x00ff;
556	1488	break;
557	1489	case 0x000a:    // ST -Z,Rd
558	1490	//output += sprintf( output, "ST      -Y , R%d", RD5(op) );
559	1491	unimplemented_opcode(cpustate, op);
560	1492	break;
561	1493	case 0x000c:    // ST X,Rd
562		rd = READ_IO_8(cpustate, RD5(op));
563		WRITE_IO_8(cpustate, XREG, rd);
564		opcycles = 2;
	1494	WRITE_IO_8(cpustate, XREG, cpustate->r[RD5(op)]);
565	1495	break;
566	1496	case 0x000d:    // ST X+,Rd
567	1497	pd = XREG;
568		WRITE_IO_8(cpustate, pd, READ_IO_8(cpustate, RD5(op)));
	1498	WRITE_IO_8(cpustate, pd, cpustate->r[RD5(op)]);
569	1499	pd++;
570		WRITE_IO_8(cpustate, 27, (pd >> 8) & 0x00ff);
571		WRITE_IO_8(cpustate, 26, pd & 0x00ff);
572		opcycles = 2;
	1500	cpustate->r[27] = (pd >> 8) & 0x00ff;
	1501	cpustate->r[26] = pd & 0x00ff;
573	1502	break;
574	1503	case 0x000e:    // ST -X,Rd
575	1504	//output += sprintf( output, "ST      -X , R%d", RD5(op) );
576	1505	unimplemented_opcode(cpustate, op);
577	1506	break;
578	1507	case 0x000f:    // PUSH Rd
579		PUSH(cpustate, READ_IO_8(cpustate, RD5(op)));
	1508	PUSH(cpustate, cpustate->r[RD5(op)]);
580	1509	opcycles = 2;
581	1510	break;
582	1511	default:
r18696	r18697
589	1518	switch(op & 0x000f)
590	1519	{
591	1520	case 0x0000:    // COM Rd
592		rd = READ_IO_8(cpustate, RD5(op));
	1521	rd = cpustate->r[RD5(op)];
593	1522	res = ~rd;
594	1523	SREG_W(AVR8_SREG_C, 1);
595	1524	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
596	1525	SREG_W(AVR8_SREG_N, BIT(res,7));
597	1526	SREG_W(AVR8_SREG_V, 0);
598	1527	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
599		WRITE_IO_8(cpustate, RD5(op), res);
	1528	cpustate->r[RD5(op)] = res;
600	1529	break;
601	1530	case 0x0001:    // NEG Rd
602		rd = READ_IO_8(cpustate, RD5(op));
	1531	rd = cpustate->r[RD5(op)];
603	1532	res = 0 - rd;
604	1533	SREG_W(AVR8_SREG_C, (res == 0) ? 0 : 1);
605	1534	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
r18696	r18697
607	1536	SREG_W(AVR8_SREG_V, (res == 0x80) ? 1 : 0);
608	1537	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
609	1538	SREG_W(AVR8_SREG_H, BIT(res,3) | BIT(rd,3));
610		WRITE_IO_8(cpustate, RD5(op), res);
	1539	cpustate->r[RD5(op)] = res;
611	1540	break;
612	1541	case 0x0002:    // SWAP Rd
613		//output += sprintf( output, "SWAP    R%d", RD5(op) );
614		unimplemented_opcode(cpustate, op);
	1542	rd = cpustate->r[RD5(op)];
	1543	cpustate->r[RD5(op)] = (rd >> 4) | (rd << 4);
615	1544	break;
616	1545	case 0x0003:    // INC Rd
617		rd = READ_IO_8(cpustate, RD5(op));
	1546	rd = cpustate->r[RD5(op)];
618	1547	res = rd + 1;
619	1548	SREG_W(AVR8_SREG_V, (rd == 0x7f) ? 1 : 0);
620	1549	SREG_W(AVR8_SREG_N, BIT(res,7));
621	1550	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
622	1551	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
623		WRITE_IO_8(cpustate, RD5(op), res);
	1552	cpustate->r[RD5(op)] = res;
624	1553	break;
625	1554	case 0x0005:    // ASR Rd
626		//output += sprintf( output, "ASR     R%d", RD5(op) );
627		unimplemented_opcode(cpustate, op);
	1555	rd = cpustate->r[RD5(op)];
	1556	res = (rd & 0x80) | (rd >> 1);
	1557	SREG_W(AVR8_SREG_C, rd & 0x01);
	1558	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
	1559	SREG_W(AVR8_SREG_N, (rd & 0x80) ? 1 : 0);
	1560	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
	1561	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	1562	cpustate->r[RD5(op)] = res;
628	1563	break;
629	1564	case 0x0006:    // LSR Rd
630		rd = READ_IO_8(cpustate, RD5(op));
	1565	rd = cpustate->r[RD5(op)];
631	1566	res = rd >> 1;
632	1567	SREG_W(AVR8_SREG_C, rd & 0x01);
633	1568	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
634	1569	SREG_W(AVR8_SREG_N, 0);
635	1570	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
636	1571	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
637		WRITE_IO_8(cpustate, RD5(op), res);
	1572	cpustate->r[RD5(op)] = res;
638	1573	break;
639	1574	case 0x0007:    // ROR Rd
640		//output += sprintf( output, "ROR     R%d", RD5(op) );
641		unimplemented_opcode(cpustate, op);
	1575	rd = cpustate->r[RD5(op)];
	1576	res = rd >> 1;
	1577	res |= (SREG_R(AVR8_SREG_C) << 7);
	1578	SREG_W(AVR8_SREG_C, rd & 0x01);
	1579	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
	1580	SREG_W(AVR8_SREG_N, res & 7);
	1581	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
	1582	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	1583	cpustate->r[RD5(op)] = res;
642	1584	break;
643	1585	case 0x0008:
644	1586	switch(op & 0x00f0)
r18696	r18697
683	1625	}
684	1626	break;
685	1627	case 0x000a:    // DEC Rd
686		rd = READ_IO_8(cpustate, RD5(op));
	1628	rd = cpustate->r[RD5(op)];
687	1629	res = rd - 1;
688	1630	SREG_W(AVR8_SREG_V, (rd == 0x7f) ? 1 : 0);
689	1631	SREG_W(AVR8_SREG_N, BIT(res,7));
690	1632	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
691	1633	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
692		WRITE_IO_8(cpustate, RD5(op), res);
	1634	cpustate->r[RD5(op)] = res;
693	1635	break;
694	1636	case 0x000c:
695	1637	case 0x000d:    // JMP k
r18696	r18697
698	1640	offs |= READ_PRG_16(cpustate, cpustate->pc);
699	1641	cpustate->pc = offs;
700	1642	cpustate->pc--;
701		opcycles = 4;
	1643	opcycles = 3;
702	1644	break;
703	1645	case 0x000e:    // CALL k
704	1646	case 0x000f:
r18696	r18697
709	1651	offs |= READ_PRG_16(cpustate, cpustate->pc);
710	1652	cpustate->pc = offs;
711	1653	cpustate->pc--;
	1654	opcycles = 4;
712	1655	break;
713	1656	default:
714	1657	unimplemented_opcode(cpustate, op);
r18696	r18697
720	1663	switch(op & 0x000f)
721	1664	{
722	1665	case 0x0000:    // COM Rd
723		rd = READ_IO_8(cpustate, RD5(op));
	1666	rd = cpustate->r[RD5(op)];
724	1667	res = ~rd;
725	1668	SREG_W(AVR8_SREG_C, 1);
726	1669	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
727	1670	SREG_W(AVR8_SREG_N, BIT(res,7));
728	1671	SREG_W(AVR8_SREG_V, 0);
729	1672	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
730		WRITE_IO_8(cpustate, RD5(op), res);
	1673	cpustate->r[RD5(op)] = res;
731	1674	break;
732	1675	case 0x0001:    // NEG Rd
733		rd = READ_IO_8(cpustate, RD5(op));
	1676	rd = cpustate->r[RD5(op)];
734	1677	res = 0 - rd;
735	1678	SREG_W(AVR8_SREG_C, (res == 0) ? 0 : 1);
736	1679	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
r18696	r18697
738	1681	SREG_W(AVR8_SREG_V, (res == 0x80) ? 1 : 0);
739	1682	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
740	1683	SREG_W(AVR8_SREG_H, BIT(res,3) | BIT(rd,3));
741		WRITE_IO_8(cpustate, RD5(op), res);
	1684	cpustate->r[RD5(op)] = res;
742	1685	break;
743	1686	case 0x0002:    // SWAP Rd
744		//output += sprintf( output, "SWAP    R%d", RD5(op) );
745		unimplemented_opcode(cpustate, op);
	1687	rd = cpustate->r[RD5(op)];
	1688	cpustate->r[RD5(op)] = (rd >> 4) | (rd << 4);
746	1689	break;
747	1690	case 0x0003:    // INC Rd
748		rd = READ_IO_8(cpustate, RD5(op));
	1691	rd = cpustate->r[RD5(op)];
749	1692	res = rd + 1;
750	1693	SREG_W(AVR8_SREG_V, (rd == 0x7f) ? 1 : 0);
751	1694	SREG_W(AVR8_SREG_N, BIT(res,7));
752	1695	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
753	1696	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
754		WRITE_IO_8(cpustate, RD5(op), res);
	1697	cpustate->r[RD5(op)] = res;
755	1698	break;
756	1699	case 0x0005:    // ASR Rd
757		//output += sprintf( output, "ASR     R%d", RD5(op) );
758		unimplemented_opcode(cpustate, op);
	1700	rd = cpustate->r[RD5(op)];
	1701	res = (rd & 0x80) | (rd >> 1);
	1702	SREG_W(AVR8_SREG_C, rd & 0x01);
	1703	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
	1704	SREG_W(AVR8_SREG_N, (rd & 0x80) ? 1 : 0);
	1705	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
	1706	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	1707	cpustate->r[RD5(op)] = res;
759	1708	break;
760	1709	case 0x0006:    // LSR Rd
761		rd = READ_IO_8(cpustate, RD5(op));
	1710	rd = cpustate->r[RD5(op)];
762	1711	res = rd >> 1;
763	1712	SREG_W(AVR8_SREG_C, rd & 0x01);
764	1713	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
765	1714	SREG_W(AVR8_SREG_N, 0);
766	1715	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
767	1716	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
768		WRITE_IO_8(cpustate, RD5(op), res);
	1717	cpustate->r[RD5(op)] = res;
769	1718	break;
770	1719	case 0x0007:    // ROR Rd
771		//output += sprintf( output, "ROR     R%d", RD5(op) );
772		unimplemented_opcode(cpustate, op);
	1720	rd = cpustate->r[RD5(op)];
	1721	res = rd >> 1;
	1722	res |= (SREG_R(AVR8_SREG_C) << 7);
	1723	SREG_W(AVR8_SREG_C, rd & 0x01);
	1724	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 :0);
	1725	SREG_W(AVR8_SREG_N, res & 7);
	1726	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
	1727	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	1728	cpustate->r[RD5(op)] = res;
773	1729	break;
774	1730	case 0x0008:
775	1731	switch(op & 0x00f0)
r18696	r18697
783	1739	case 0x0010:    // RETI
784	1740	cpustate->pc = POP(cpustate);
785	1741	cpustate->pc |= POP(cpustate) << 8;
	1742	//printf("Pop: %04x\n", cpustate->pc);
786	1743	cpustate->pc--;
787	1744	SREG_W(AVR8_SREG_I, 1);
	1745	if (cpustate->interrupt_pending)
	1746	{
	1747	avr8_poll_interrupt(cpustate);
	1748	cpustate->interrupt_pending = false;
	1749	}
788	1750	opcycles = 4;
789	1751	break;
790	1752	case 0x0080:    // SLEEP
r18696	r18697
800	1762	unimplemented_opcode(cpustate, op);
801	1763	break;
802	1764	case 0x00c0:    // LPM
803		WRITE_IO_8(cpustate, 0, READ_PRG_8(cpustate, ZREG));
	1765	cpustate->r[0] = READ_PRG_8(cpustate, ZREG);
804	1766	opcycles = 3;
805	1767	break;
806	1768	case 0x00d0:    // ELPM
r18696	r18697
839	1801	}
840	1802	break;
841	1803	case 0x000a:    // DEC Rd
842		rd = READ_IO_8(cpustate, RD5(op));
	1804	rd = cpustate->r[RD5(op)];
843	1805	res = rd - 1;
844	1806	SREG_W(AVR8_SREG_V, (rd == 0x7f) ? 1 : 0);
845	1807	SREG_W(AVR8_SREG_N, BIT(res,7));
846	1808	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
847	1809	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
848		WRITE_IO_8(cpustate, RD5(op), res);
	1810	cpustate->r[RD5(op)] = res;
849	1811	break;
850	1812	case 0x000c:
851	1813	case 0x000d:    // JMP k
r18696	r18697
868	1830	}
869	1831	break;
870	1832	case 0x0600:    // ADIW Rd+1:Rd,K
871		rd = READ_IO_8(cpustate, 24 + (DCONST(op) << 1));
872		rr = READ_IO_8(cpustate, 25 + (DCONST(op) << 1));
	1833	rd = cpustate->r[24 + (DCONST(op) << 1)];
	1834	rr = cpustate->r[25 + (DCONST(op) << 1)];
873	1835	pd = rd;
874	1836	pd |= rr << 8;
875	1837	pd += KCONST6(op);
r18696	r18697
878	1840	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
879	1841	SREG_W(AVR8_SREG_Z, (pd == 0) ? 1 : 0);
880	1842	SREG_W(AVR8_SREG_C, NOT(BIT(pd,15)) & BIT(rr,7));
881		WRITE_IO_8(cpustate, 24 + (DCONST(op) << 1), pd & 0xff);
882		WRITE_IO_8(cpustate, 25 + (DCONST(op) << 1), (pd >> 8) & 0xff);
	1843	cpustate->r[24 + (DCONST(op) << 1)] = pd & 0x00ff;
	1844	cpustate->r[25 + (DCONST(op) << 1)] = (pd >> 8) & 0x00ff;
883	1845	opcycles = 2;
884	1846	break;
885	1847	case 0x0700:    // SBIW Rd+1:Rd,K
r18696	r18697
888	1850	break;
889	1851	case 0x0800:    // CBI A,b
890	1852	//output += sprintf( output, "CBI     0x%02x, %d", ACONST5(op), RR3(op) );
891		WRITE_IO_8(cpustate, ACONST5(op), READ_IO_8(cpustate, ACONST5(op)) &~ (1 << RR3(op)));
	1853	WRITE_IO_8(cpustate, 32 + ACONST5(op), READ_IO_8(cpustate, 32 + ACONST5(op)) &~ (1 << RR3(op)));
892	1854	opcycles = 2;
893	1855	break;
894	1856	case 0x0900:    // SBIC A,b
895		if(!(READ_IO_8(cpustate, ACONST5(op)) & (1 << RR3(op))))
	1857	if(NOT(BIT(READ_IO_8(cpustate, 32 + ACONST5(op)), (1 << RR3(op)))))
896	1858	{
897	1859	opcycles += avr8_is_long_opcode(op) ? 2 : 1;
898	1860	cpustate->pc += avr8_is_long_opcode(op) ? 2 : 1;
899	1861	}
900	1862	break;
901	1863	case 0x0a00:    // SBI A,b
902		//output += sprintf( output, "SBI     0x%02x, %d", ACONST5(op), RR3(op) );
903		WRITE_IO_8(cpustate, ACONST5(op), READ_IO_8(cpustate, ACONST5(op)) | (1 << RR3(op)));
	1864	WRITE_IO_8(cpustate, 32 + ACONST5(op), READ_IO_8(cpustate, 32 + ACONST5(op)) | (1 << RR3(op)));
904	1865	opcycles = 2;
905	1866	break;
906	1867	case 0x0b00:    // SBIS A,b
907		//output += sprintf( output, "SBIS    0x%02x, %d", ACONST5(op), RR3(op) );
908		unimplemented_opcode(cpustate, op);
	1868	if(BIT(READ_IO_8(cpustate, 32 + ACONST5(op)), (1 << RR3(op))))
	1869	{
	1870	opcycles += avr8_is_long_opcode(op) ? 2 : 1;
	1871	cpustate->pc += avr8_is_long_opcode(op) ? 2 : 1;
	1872	}
909	1873	break;
910	1874	case 0x0c00:
911	1875	case 0x0d00:
912	1876	case 0x0e00:
913	1877	case 0x0f00:    // MUL Rd,Rr
914		sd = (UINT8)READ_IO_8(cpustate, RD5(op)) * (UINT8)READ_IO_8(cpustate, RR5(op));
915		WRITE_IO_8(cpustate, 1, (sd >> 8) & 0x00ff);
916		WRITE_IO_8(cpustate, 0, sd & 0x00ff);
	1878	sd = (UINT8)cpustate->r[RD5(op)] * (UINT8)cpustate->r[RR5(op)];
	1879	cpustate->r[1] = (sd >> 8) & 0x00ff;
	1880	cpustate->r[0] = sd & 0x00ff;
917	1881	SREG_W(AVR8_SREG_C, (sd & 0x8000) ? 1 : 0);
918	1882	SREG_W(AVR8_SREG_Z, (sd == 0) ? 1 : 0);
919	1883	opcycles = 2;
920		//output += sprintf( output, "MUL     R%d, R%d", RD5(op), RR5(op) );
921	1884	break;
922	1885	}
923	1886	break;
924	1887	case 0xb000:
925	1888	if(op & 0x0800) // OUT A,Rr
926	1889	{
927		WRITE_IO_8(cpustate, 0x20 + ACONST6(op), READ_IO_8(cpustate, RD5(op)));
	1890	WRITE_IO_8(cpustate, 32 + ACONST6(op), cpustate->r[RD5(op)]);
928	1891	}
929	1892	else            // IN Rd,A
930	1893	{
931		WRITE_IO_8(cpustate, RD5(op), READ_IO_8(cpustate, 0x20 + ACONST6(op)));
	1894	cpustate->r[RD5(op)] = READ_IO_8(cpustate, 0x20 + ACONST6(op));
932	1895	}
933	1896	break;
934	1897	case 0xc000:    // RJMP k
r18696	r18697
944	1907	opcycles = 3;
945	1908	break;
946	1909	case 0xe000:    // LDI Rd,K
947		rd = KCONST8(op);
948		WRITE_IO_8(cpustate, 16 + RD4(op), rd);
	1910	cpustate->r[16 + RD4(op)] = KCONST8(op);
949	1911	break;
950	1912	case 0xf000:
951	1913	switch(op & 0x0c00)
r18696	r18697
977	1939	case 0x0800:
978	1940	if(op & 0x0200) // BST Rd, b
979	1941	{
980		SREG_W(AVR8_SREG_T, (BIT(READ_IO_8(cpustate, RD5(op)),RR3(op))) ? 1 : 0);
	1942	SREG_W(AVR8_SREG_T, (BIT(cpustate->r[RD5(op)], RR3(op))) ? 1 : 0);
981	1943	}
982	1944	else            // BLD Rd, b
983	1945	{
984	1946	if(SREG_R(AVR8_SREG_T))
985	1947	{
986		WRITE_IO_8(cpustate, RD5(op), READ_IO_8(cpustate, RD5(op)) | (1 << RR3(op)));
	1948	cpustate->r[RD5(op)] |= (1 << RR3(op));
987	1949	}
988	1950	else
989	1951	{
990		WRITE_IO_8(cpustate, RD5(op), READ_IO_8(cpustate, RD5(op)) &~ (1 << RR3(op)));
	1952	cpustate->r[RD5(op)] &= ~(1 << RR3(op));
991	1953	}
992	1954	}
993	1955	break;
994	1956	case 0x0c00:
995	1957	if(op & 0x0200) // SBRS Rd, b
996	1958	{
997		if(BIT(READ_IO_8(cpustate, RD5(op)),RR3(op)))
	1959	if(BIT(cpustate->r[RD5(op)], RR3(op)))
998	1960	{
999	1961	op = (UINT32)READ_PRG_16(cpustate, cpustate->pc++);
1000		opcycles = 2;
1001		if((op & 0xfe0c) == 0x940c ||
1002		(op & 0xfe0f) == 0xfe0f)
1003		{
1004		cpustate->pc++;
1005		opcycles = 3;
1006		}
	1962	cpustate->pc += avr8_is_long_opcode(op) ? 1 : 0;
	1963	opcycles = avr8_is_long_opcode(op) ? 3 : 2;
1007	1964	}
1008	1965	}
1009	1966	else            // SBRC Rd, b
1010	1967	{
1011		if(!BIT(READ_IO_8(cpustate, RD5(op)),RR3(op)))
	1968	if(!BIT(cpustate->r[RD5(op)], RR3(op)))
1012	1969	{
1013	1970	op = (UINT32)READ_PRG_16(cpustate, cpustate->pc++);
1014		opcycles = 2;
1015		if((op & 0xfe0c) == 0x940c ||
1016		(op & 0xfc0f) == 0x9000)
1017		{
1018		cpustate->pc++;
1019		opcycles = 3;
1020		}
	1971	cpustate->pc += avr8_is_long_opcode(op) ? 1 : 0;
	1972	opcycles = avr8_is_long_opcode(op) ? 3 : 2;
1021	1973	}
1022	1974	}
1023	1975	break;
r18696	r18697
1028	1980	cpustate->pc++;
1029	1981
1030	1982	cpustate->icount -= opcycles;
	1983
	1984	avr8_timer_tick(cpustate, opcycles);
1031	1985	}
1032	1986	}
1033	1987
r18696	r18697
1069	2023
1070	2024	/* --- the following bits of info are set as 64-bit signed integers --- */
1071	2025	case CPUINFO_INT_PC:    /* intentional fallthrough */
1072		case CPUINFO_INT_REGISTER + AVR8_PC:            cpustate->pc = info->i;                         break;
1073		case CPUINFO_INT_REGISTER + AVR8_SREG:          WRITE_IO_8(cpustate, AVR8_IO_SREG, info->i);    break;
1074		case CPUINFO_INT_REGISTER + AVR8_R0:            WRITE_IO_8(cpustate, 0, info->i);               break;
1075		case CPUINFO_INT_REGISTER + AVR8_R1:            WRITE_IO_8(cpustate, 1, info->i);               break;
1076		case CPUINFO_INT_REGISTER + AVR8_R2:            WRITE_IO_8(cpustate, 2, info->i);               break;
1077		case CPUINFO_INT_REGISTER + AVR8_R3:            WRITE_IO_8(cpustate, 3, info->i);               break;
1078		case CPUINFO_INT_REGISTER + AVR8_R4:            WRITE_IO_8(cpustate, 4, info->i);               break;
1079		case CPUINFO_INT_REGISTER + AVR8_R5:            WRITE_IO_8(cpustate, 5, info->i);               break;
1080		case CPUINFO_INT_REGISTER + AVR8_R6:            WRITE_IO_8(cpustate, 6, info->i);               break;
1081		case CPUINFO_INT_REGISTER + AVR8_R7:            WRITE_IO_8(cpustate, 7, info->i);               break;
1082		case CPUINFO_INT_REGISTER + AVR8_R8:            WRITE_IO_8(cpustate, 8, info->i);               break;
1083		case CPUINFO_INT_REGISTER + AVR8_R9:            WRITE_IO_8(cpustate, 9, info->i);               break;
1084		case CPUINFO_INT_REGISTER + AVR8_R10:           WRITE_IO_8(cpustate, 10, info->i);              break;
1085		case CPUINFO_INT_REGISTER + AVR8_R11:           WRITE_IO_8(cpustate, 11, info->i);              break;
1086		case CPUINFO_INT_REGISTER + AVR8_R12:           WRITE_IO_8(cpustate, 12, info->i);              break;
1087		case CPUINFO_INT_REGISTER + AVR8_R13:           WRITE_IO_8(cpustate, 13, info->i);              break;
1088		case CPUINFO_INT_REGISTER + AVR8_R14:           WRITE_IO_8(cpustate, 14, info->i);              break;
1089		case CPUINFO_INT_REGISTER + AVR8_R15:           WRITE_IO_8(cpustate, 15, info->i);              break;
1090		case CPUINFO_INT_REGISTER + AVR8_R16:           WRITE_IO_8(cpustate, 16, info->i);              break;
1091		case CPUINFO_INT_REGISTER + AVR8_R17:           WRITE_IO_8(cpustate, 17, info->i);              break;
1092		case CPUINFO_INT_REGISTER + AVR8_R18:           WRITE_IO_8(cpustate, 18, info->i);              break;
1093		case CPUINFO_INT_REGISTER + AVR8_R19:           WRITE_IO_8(cpustate, 19, info->i);              break;
1094		case CPUINFO_INT_REGISTER + AVR8_R20:           WRITE_IO_8(cpustate, 20, info->i);              break;
1095		case CPUINFO_INT_REGISTER + AVR8_R21:           WRITE_IO_8(cpustate, 21, info->i);              break;
1096		case CPUINFO_INT_REGISTER + AVR8_R22:           WRITE_IO_8(cpustate, 22, info->i);              break;
1097		case CPUINFO_INT_REGISTER + AVR8_R23:           WRITE_IO_8(cpustate, 23, info->i);              break;
1098		case CPUINFO_INT_REGISTER + AVR8_R24:           WRITE_IO_8(cpustate, 24, info->i);              break;
1099		case CPUINFO_INT_REGISTER + AVR8_R25:           WRITE_IO_8(cpustate, 25, info->i);              break;
1100		case CPUINFO_INT_REGISTER + AVR8_R26:           WRITE_IO_8(cpustate, 26, info->i);              break;
1101		case CPUINFO_INT_REGISTER + AVR8_R27:           WRITE_IO_8(cpustate, 27, info->i);              break;
1102		case CPUINFO_INT_REGISTER + AVR8_R28:           WRITE_IO_8(cpustate, 28, info->i);              break;
1103		case CPUINFO_INT_REGISTER + AVR8_R29:           WRITE_IO_8(cpustate, 29, info->i);              break;
1104		case CPUINFO_INT_REGISTER + AVR8_R30:           WRITE_IO_8(cpustate, 30, info->i);              break;
1105		case CPUINFO_INT_REGISTER + AVR8_R31:           WRITE_IO_8(cpustate, 31, info->i);              break;
	2026	case CPUINFO_INT_REGISTER + AVR8_PC:            cpustate->pc = info->i;                 break;
	2027	case CPUINFO_INT_REGISTER + AVR8_SREG:          cpustate->status = info->i;             break;
	2028	case CPUINFO_INT_REGISTER + AVR8_R0:            cpustate->r[ 0] = info->i;              break;
	2029	case CPUINFO_INT_REGISTER + AVR8_R1:            cpustate->r[ 1] = info->i;              break;
	2030	case CPUINFO_INT_REGISTER + AVR8_R2:            cpustate->r[ 2] = info->i;              break;
	2031	case CPUINFO_INT_REGISTER + AVR8_R3:            cpustate->r[ 3] = info->i;              break;
	2032	case CPUINFO_INT_REGISTER + AVR8_R4:            cpustate->r[ 4] = info->i;              break;
	2033	case CPUINFO_INT_REGISTER + AVR8_R5:            cpustate->r[ 5] = info->i;              break;
	2034	case CPUINFO_INT_REGISTER + AVR8_R6:            cpustate->r[ 6] = info->i;              break;
	2035	case CPUINFO_INT_REGISTER + AVR8_R7:            cpustate->r[ 7] = info->i;              break;
	2036	case CPUINFO_INT_REGISTER + AVR8_R8:            cpustate->r[ 8] = info->i;              break;
	2037	case CPUINFO_INT_REGISTER + AVR8_R9:            cpustate->r[ 9] = info->i;              break;
	2038	case CPUINFO_INT_REGISTER + AVR8_R10:           cpustate->r[10] = info->i;              break;
	2039	case CPUINFO_INT_REGISTER + AVR8_R11:           cpustate->r[11] = info->i;              break;
	2040	case CPUINFO_INT_REGISTER + AVR8_R12:           cpustate->r[12] = info->i;              break;
	2041	case CPUINFO_INT_REGISTER + AVR8_R13:           cpustate->r[13] = info->i;              break;
	2042	case CPUINFO_INT_REGISTER + AVR8_R14:           cpustate->r[14] = info->i;              break;
	2043	case CPUINFO_INT_REGISTER + AVR8_R15:           cpustate->r[15] = info->i;              break;
	2044	case CPUINFO_INT_REGISTER + AVR8_R16:           cpustate->r[16] = info->i;              break;
	2045	case CPUINFO_INT_REGISTER + AVR8_R17:           cpustate->r[17] = info->i;              break;
	2046	case CPUINFO_INT_REGISTER + AVR8_R18:           cpustate->r[18] = info->i;              break;
	2047	case CPUINFO_INT_REGISTER + AVR8_R19:           cpustate->r[19] = info->i;              break;
	2048	case CPUINFO_INT_REGISTER + AVR8_R20:           cpustate->r[20] = info->i;              break;
	2049	case CPUINFO_INT_REGISTER + AVR8_R21:           cpustate->r[21] = info->i;              break;
	2050	case CPUINFO_INT_REGISTER + AVR8_R22:           cpustate->r[22] = info->i;              break;
	2051	case CPUINFO_INT_REGISTER + AVR8_R23:           cpustate->r[23] = info->i;              break;
	2052	case CPUINFO_INT_REGISTER + AVR8_R24:           cpustate->r[24] = info->i;              break;
	2053	case CPUINFO_INT_REGISTER + AVR8_R25:           cpustate->r[25] = info->i;              break;
	2054	case CPUINFO_INT_REGISTER + AVR8_R26:           cpustate->r[26] = info->i;              break;
	2055	case CPUINFO_INT_REGISTER + AVR8_R27:           cpustate->r[27] = info->i;              break;
	2056	case CPUINFO_INT_REGISTER + AVR8_R28:           cpustate->r[28] = info->i;              break;
	2057	case CPUINFO_INT_REGISTER + AVR8_R29:           cpustate->r[29] = info->i;              break;
	2058	case CPUINFO_INT_REGISTER + AVR8_R30:           cpustate->r[30] = info->i;              break;
	2059	case CPUINFO_INT_REGISTER + AVR8_R31:           cpustate->r[31] = info->i;              break;
1106	2060	}
1107	2061	}
1108	2062
r18696	r18697
1135	2089	case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO:      info->i = 0;                    break;
1136	2090
1137	2091	case CPUINFO_INT_PC:    /* intentional fallthrough */
1138		case CPUINFO_INT_REGISTER + AVR8_PC:    info->i = cpustate->pc << 1;                    break;
1139		case CPUINFO_INT_REGISTER + AVR8_SREG:  info->i = READ_IO_8(cpustate, AVR8_IO_SREG);    break;
	2092	case CPUINFO_INT_REGISTER + AVR8_PC:    info->i = cpustate->pc << 1;   break;
	2093	case CPUINFO_INT_REGISTER + AVR8_SREG:  info->i = cpustate->status;       break;
1140	2094
1141	2095	/* --- the following bits of info are returned as pointers to data or functions --- */
1142	2096	case CPUINFO_FCT_SET_INFO:              info->setinfo = CPU_SET_INFO_NAME(avr8);        break;
r18696	r18697
1157	2111
1158	2112	case CPUINFO_STR_FLAGS:                         strcpy(info->s, " ");                   break;
1159	2113
1160		case CPUINFO_STR_REGISTER + AVR8_SREG:          sprintf(info->s, "SREG: %c%c%c%c%c%c%c%c", (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x80) ? 'I' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x40) ? 'T' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x20) ? 'H' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x10) ? 'S' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x08) ? 'V' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x04) ? 'N' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x02) ? 'Z' : '-', (READ_IO_8(cpustate, AVR8_IO_SREG) & 0x01) ? 'C' : '-'); break;
1161		case CPUINFO_STR_REGISTER + AVR8_R0:            sprintf(info->s, "R0:  %02x", READ_IO_8(cpustate, 0) ); break;
1162		case CPUINFO_STR_REGISTER + AVR8_R1:            sprintf(info->s, "R1:  %02x", READ_IO_8(cpustate, 1) ); break;
1163		case CPUINFO_STR_REGISTER + AVR8_R2:            sprintf(info->s, "R2:  %02x", READ_IO_8(cpustate, 2) ); break;
1164		case CPUINFO_STR_REGISTER + AVR8_R3:            sprintf(info->s, "R3:  %02x", READ_IO_8(cpustate, 3) ); break;
1165		case CPUINFO_STR_REGISTER + AVR8_R4:            sprintf(info->s, "R4:  %02x", READ_IO_8(cpustate, 4) ); break;
1166		case CPUINFO_STR_REGISTER + AVR8_R5:            sprintf(info->s, "R5:  %02x", READ_IO_8(cpustate, 5) ); break;
1167		case CPUINFO_STR_REGISTER + AVR8_R6:            sprintf(info->s, "R6:  %02x", READ_IO_8(cpustate, 6) ); break;
1168		case CPUINFO_STR_REGISTER + AVR8_R7:            sprintf(info->s, "R7:  %02x", READ_IO_8(cpustate, 7) ); break;
1169		case CPUINFO_STR_REGISTER + AVR8_R8:            sprintf(info->s, "R8:  %02x", READ_IO_8(cpustate, 8) ); break;
1170		case CPUINFO_STR_REGISTER + AVR8_R9:            sprintf(info->s, "R9:  %02x", READ_IO_8(cpustate, 9) ); break;
1171		case CPUINFO_STR_REGISTER + AVR8_R10:           sprintf(info->s, "R10: %02x", READ_IO_8(cpustate, 10) ); break;
1172		case CPUINFO_STR_REGISTER + AVR8_R11:           sprintf(info->s, "R11: %02x", READ_IO_8(cpustate, 11) ); break;
1173		case CPUINFO_STR_REGISTER + AVR8_R12:           sprintf(info->s, "R12: %02x", READ_IO_8(cpustate, 12) ); break;
1174		case CPUINFO_STR_REGISTER + AVR8_R13:           sprintf(info->s, "R13: %02x", READ_IO_8(cpustate, 13) ); break;
1175		case CPUINFO_STR_REGISTER + AVR8_R14:           sprintf(info->s, "R14: %02x", READ_IO_8(cpustate, 14) ); break;
1176		case CPUINFO_STR_REGISTER + AVR8_R15:           sprintf(info->s, "R15: %02x", READ_IO_8(cpustate, 15) ); break;
1177		case CPUINFO_STR_REGISTER + AVR8_R16:           sprintf(info->s, "R16: %02x", READ_IO_8(cpustate, 16) ); break;
1178		case CPUINFO_STR_REGISTER + AVR8_R17:           sprintf(info->s, "R17: %02x", READ_IO_8(cpustate, 17) ); break;
1179		case CPUINFO_STR_REGISTER + AVR8_R18:           sprintf(info->s, "R18: %02x", READ_IO_8(cpustate, 18) ); break;
1180		case CPUINFO_STR_REGISTER + AVR8_R19:           sprintf(info->s, "R19: %02x", READ_IO_8(cpustate, 19) ); break;
1181		case CPUINFO_STR_REGISTER + AVR8_R20:           sprintf(info->s, "R20: %02x", READ_IO_8(cpustate, 20) ); break;
1182		case CPUINFO_STR_REGISTER + AVR8_R21:           sprintf(info->s, "R21: %02x", READ_IO_8(cpustate, 21) ); break;
1183		case CPUINFO_STR_REGISTER + AVR8_R22:           sprintf(info->s, "R22: %02x", READ_IO_8(cpustate, 22) ); break;
1184		case CPUINFO_STR_REGISTER + AVR8_R23:           sprintf(info->s, "R23: %02x", READ_IO_8(cpustate, 23) ); break;
1185		case CPUINFO_STR_REGISTER + AVR8_R24:           sprintf(info->s, "R24: %02x", READ_IO_8(cpustate, 24) ); break;
1186		case CPUINFO_STR_REGISTER + AVR8_R25:           sprintf(info->s, "R25: %02x", READ_IO_8(cpustate, 25) ); break;
1187		case CPUINFO_STR_REGISTER + AVR8_R26:           sprintf(info->s, "R26: %02x", READ_IO_8(cpustate, 26) ); break;
1188		case CPUINFO_STR_REGISTER + AVR8_R27:           sprintf(info->s, "R27: %02x", READ_IO_8(cpustate, 27) ); break;
1189		case CPUINFO_STR_REGISTER + AVR8_R28:           sprintf(info->s, "R28: %02x", READ_IO_8(cpustate, 28) ); break;
1190		case CPUINFO_STR_REGISTER + AVR8_R29:           sprintf(info->s, "R29: %02x", READ_IO_8(cpustate, 29) ); break;
1191		case CPUINFO_STR_REGISTER + AVR8_R30:           sprintf(info->s, "R30: %02x", READ_IO_8(cpustate, 30) ); break;
1192		case CPUINFO_STR_REGISTER + AVR8_R31:           sprintf(info->s, "R31: %02x", READ_IO_8(cpustate, 31) ); break;
	2114	case CPUINFO_STR_REGISTER + AVR8_SREG:          sprintf(info->s, "SREG: %c%c%c%c%c%c%c%c", (cpustate->status & 0x80) ? 'I' : '-', (cpustate->status & 0x40) ? 'T' : '-', (cpustate->status & 0x20) ? 'H' : '-', (cpustate->status & 0x10) ? 'S' : '-', (cpustate->status & 0x08) ? 'V' : '-', (cpustate->status & 0x04) ? 'N' : '-', (cpustate->status & 0x02) ? 'Z' : '-', (cpustate->status & 0x01) ? 'C' : '-'); break;
	2115	case CPUINFO_STR_REGISTER + AVR8_R0:            sprintf(info->s, "R0:  %02x", cpustate->r[ 0] ); break;
	2116	case CPUINFO_STR_REGISTER + AVR8_R1:            sprintf(info->s, "R1:  %02x", cpustate->r[ 1] ); break;
	2117	case CPUINFO_STR_REGISTER + AVR8_R2:            sprintf(info->s, "R2:  %02x", cpustate->r[ 2] ); break;
	2118	case CPUINFO_STR_REGISTER + AVR8_R3:            sprintf(info->s, "R3:  %02x", cpustate->r[ 3] ); break;
	2119	case CPUINFO_STR_REGISTER + AVR8_R4:            sprintf(info->s, "R4:  %02x", cpustate->r[ 4] ); break;
	2120	case CPUINFO_STR_REGISTER + AVR8_R5:            sprintf(info->s, "R5:  %02x", cpustate->r[ 5] ); break;
	2121	case CPUINFO_STR_REGISTER + AVR8_R6:            sprintf(info->s, "R6:  %02x", cpustate->r[ 6] ); break;
	2122	case CPUINFO_STR_REGISTER + AVR8_R7:            sprintf(info->s, "R7:  %02x", cpustate->r[ 7] ); break;
	2123	case CPUINFO_STR_REGISTER + AVR8_R8:            sprintf(info->s, "R8:  %02x", cpustate->r[ 8] ); break;
	2124	case CPUINFO_STR_REGISTER + AVR8_R9:            sprintf(info->s, "R9:  %02x", cpustate->r[ 9] ); break;
	2125	case CPUINFO_STR_REGISTER + AVR8_R10:           sprintf(info->s, "R10: %02x", cpustate->r[10] ); break;
	2126	case CPUINFO_STR_REGISTER + AVR8_R11:           sprintf(info->s, "R11: %02x", cpustate->r[11] ); break;
	2127	case CPUINFO_STR_REGISTER + AVR8_R12:           sprintf(info->s, "R12: %02x", cpustate->r[12] ); break;
	2128	case CPUINFO_STR_REGISTER + AVR8_R13:           sprintf(info->s, "R13: %02x", cpustate->r[13] ); break;
	2129	case CPUINFO_STR_REGISTER + AVR8_R14:           sprintf(info->s, "R14: %02x", cpustate->r[14] ); break;
	2130	case CPUINFO_STR_REGISTER + AVR8_R15:           sprintf(info->s, "R15: %02x", cpustate->r[15] ); break;
	2131	case CPUINFO_STR_REGISTER + AVR8_R16:           sprintf(info->s, "R16: %02x", cpustate->r[16] ); break;
	2132	case CPUINFO_STR_REGISTER + AVR8_R17:           sprintf(info->s, "R17: %02x", cpustate->r[17] ); break;
	2133	case CPUINFO_STR_REGISTER + AVR8_R18:           sprintf(info->s, "R18: %02x", cpustate->r[18] ); break;
	2134	case CPUINFO_STR_REGISTER + AVR8_R19:           sprintf(info->s, "R19: %02x", cpustate->r[19] ); break;
	2135	case CPUINFO_STR_REGISTER + AVR8_R20:           sprintf(info->s, "R20: %02x", cpustate->r[20] ); break;
	2136	case CPUINFO_STR_REGISTER + AVR8_R21:           sprintf(info->s, "R21: %02x", cpustate->r[21] ); break;
	2137	case CPUINFO_STR_REGISTER + AVR8_R22:           sprintf(info->s, "R22: %02x", cpustate->r[22] ); break;
	2138	case CPUINFO_STR_REGISTER + AVR8_R23:           sprintf(info->s, "R23: %02x", cpustate->r[23] ); break;
	2139	case CPUINFO_STR_REGISTER + AVR8_R24:           sprintf(info->s, "R24: %02x", cpustate->r[24] ); break;
	2140	case CPUINFO_STR_REGISTER + AVR8_R25:           sprintf(info->s, "R25: %02x", cpustate->r[25] ); break;
	2141	case CPUINFO_STR_REGISTER + AVR8_R26:           sprintf(info->s, "R26: %02x", cpustate->r[26] ); break;
	2142	case CPUINFO_STR_REGISTER + AVR8_R27:           sprintf(info->s, "R27: %02x", cpustate->r[27] ); break;
	2143	case CPUINFO_STR_REGISTER + AVR8_R28:           sprintf(info->s, "R28: %02x", cpustate->r[28] ); break;
	2144	case CPUINFO_STR_REGISTER + AVR8_R29:           sprintf(info->s, "R29: %02x", cpustate->r[29] ); break;
	2145	case CPUINFO_STR_REGISTER + AVR8_R30:           sprintf(info->s, "R30: %02x", cpustate->r[30] ); break;
	2146	case CPUINFO_STR_REGISTER + AVR8_R31:           sprintf(info->s, "R31: %02x", cpustate->r[31] ); break;
1193	2147	case CPUINFO_STR_REGISTER + AVR8_X:             sprintf(info->s, "X: %04x", XREG ); break;
1194	2148	case CPUINFO_STR_REGISTER + AVR8_Y:             sprintf(info->s, "Y: %04x", YREG ); break;
1195	2149	case CPUINFO_STR_REGISTER + AVR8_Z:             sprintf(info->s, "Z: %04x", ZREG ); break;

trunk/src/emu/cpu/avr8/avr8.h

r18696	r18697
11	11	#ifndef __AVR8_H__
12	12	#define __AVR8_H__
13	13
	14	// Used by core CPU interface
	15	struct avr8_state
	16	{
	17	UINT32 pc;
	18
	19	legacy_cpu_device *device;
	20	address_space *program;
	21	address_space *io;
	22
	23	int icount;
	24	UINT32 addr_mask;
	25
	26	UINT8 r[256];
	27	UINT8 status;
	28
	29	UINT8 timer0_top;
	30	INT32 timer0_increment;
	31	UINT16 timer0_prescale;
	32	UINT16 timer0_prescale_count;
	33
	34	UINT16 timer1_top;
	35	INT32 timer1_increment;
	36	UINT16 timer1_prescale;
	37	UINT16 timer1_prescale_count;
	38
	39	UINT8 timer2_top;
	40	INT32 timer2_increment;
	41	UINT16 timer2_prescale;
	42	UINT16 timer2_prescale_count;
	43
	44	bool interrupt_pending;
	45	};
	46
14	47	enum
15	48	{
16	49	AVR8_SREG = 1,
r18696	r18697
83	116	AVR8_INT_SPM_RDY,
84	117	};
85	118
	119	// Used by I/O register handling
	120	enum
	121	{
	122	AVR8_REGIDX_R0 = 0,
	123	AVR8_REGIDX_R1,
	124	AVR8_REGIDX_R2,
	125	AVR8_REGIDX_R3,
	126	AVR8_REGIDX_R4,
	127	AVR8_REGIDX_R5,
	128	AVR8_REGIDX_R6,
	129	AVR8_REGIDX_R7,
	130	AVR8_REGIDX_R8,
	131	AVR8_REGIDX_R9,
	132	AVR8_REGIDX_R10,
	133	AVR8_REGIDX_R11,
	134	AVR8_REGIDX_R12,
	135	AVR8_REGIDX_R13,
	136	AVR8_REGIDX_R14,
	137	AVR8_REGIDX_R15,
	138	AVR8_REGIDX_R16,
	139	AVR8_REGIDX_R17,
	140	AVR8_REGIDX_R18,
	141	AVR8_REGIDX_R19,
	142	AVR8_REGIDX_R20,
	143	AVR8_REGIDX_R21,
	144	AVR8_REGIDX_R22,
	145	AVR8_REGIDX_R23,
	146	AVR8_REGIDX_R24,
	147	AVR8_REGIDX_R25,
	148	AVR8_REGIDX_R26,
	149	AVR8_REGIDX_R27,
	150	AVR8_REGIDX_R28,
	151	AVR8_REGIDX_R29,
	152	AVR8_REGIDX_R30,
	153	AVR8_REGIDX_R31,
	154
	155	AVR8_REGIDX_PINB = 0x23,
	156	AVR8_REGIDX_DDRB,
	157	AVR8_REGIDX_PORTB,
	158	AVR8_REGIDX_PINC,
	159	AVR8_REGIDX_DDRC,
	160	AVR8_REGIDX_PORTC,
	161	AVR8_REGIDX_PIND,
	162	AVR8_REGIDX_DDRD,
	163	AVR8_REGIDX_PORTD,
	164
	165	AVR8_REGIDX_TIFR0 = 0x35,
	166	AVR8_REGIDX_TIFR1,
	167	AVR8_REGIDX_TIFR2,
	168
	169	AVR8_REGIDX_PCIFR = 0x3b,
	170	AVR8_REGIDX_EIFR,
	171	AVR8_REGIDX_EIMSK,
	172	AVR8_REGIDX_GPIOR0,
	173	AVR8_REGIDX_EECR,
	174	AVR8_REGIDX_EEDR,
	175	AVR8_REGIDX_EEARL,
	176	AVR8_REGIDX_EEARH,
	177	AVR8_REGIDX_GTCCR,
	178	AVR8_REGIDX_TCCR0A,
	179	AVR8_REGIDX_TCCR0B,
	180	AVR8_REGIDX_TCNT0,
	181	AVR8_REGIDX_OCR0A,
	182	AVR8_REGIDX_OCR0B,
	183
	184	AVR8_REGIDX_GPIOR1 = 0x4a,
	185	AVR8_REGIDX_GPIOR2,
	186	AVR8_REGIDX_SPCR,
	187	AVR8_REGIDX_SPSR,
	188	AVR8_REGIDX_SPDR,
	189
	190	AVR8_REGIDX_ACSR = 0x50,
	191
	192	AVR8_REGIDX_SMCR = 0x53,
	193	AVR8_REGIDX_MCUSR,
	194	AVR8_REGIDX_MCUCR,
	195
	196	AVR8_REGIDX_SPMCSR = 0x57,
	197
	198	AVR8_REGIDX_SPL = 0x5d,
	199	AVR8_REGIDX_SPH,
	200	AVR8_REGIDX_SREG,
	201	AVR8_REGIDX_WDTCSR,
	202	AVR8_REGIDX_CLKPR,
	203
	204	AVR8_REGIDX_PRR = 0x64,
	205
	206	AVR8_REGIDX_OSCCAL = 0x66,
	207
	208	AVR8_REGIDX_PCICR = 0x68,
	209	AVR8_REGIDX_EICRA,
	210
	211	AVR8_REGIDX_PCMSK0 = 0x6B,
	212	AVR8_REGIDX_PCMSK1,
	213	AVR8_REGIDX_PCMSK2,
	214	AVR8_REGIDX_TIMSK0,
	215	AVR8_REGIDX_TIMSK1,
	216	AVR8_REGIDX_TIMSK2,
	217
	218	AVR8_REGIDX_ADCL = 0x78,
	219	AVR8_REGIDX_ADCH,
	220	AVR8_REGIDX_ADCSRA,
	221	AVR8_REGIDX_ADCSRB,
	222	AVR8_REGIDX_ADMUX,
	223
	224	AVR8_REGIDX_DIDR0 = 0x7e,
	225	AVR8_REGIDX_DIDR1,
	226	AVR8_REGIDX_TCCR1A,
	227	AVR8_REGIDX_TCCR1B,
	228	AVR8_REGIDX_TCCR1C,
	229
	230	AVR8_REGIDX_TCNT1L = 0x84,
	231	AVR8_REGIDX_TCNT1H,
	232	AVR8_REGIDX_ICR1L,
	233	AVR8_REGIDX_ICR1H,
	234	AVR8_REGIDX_OCR1AL,
	235	AVR8_REGIDX_OCR1AH,
	236	AVR8_REGIDX_OCR1BL,
	237	AVR8_REGIDX_OCR1BH,
	238
	239	AVR8_REGIDX_TCCR2A = 0xb0,
	240	AVR8_REGIDX_TCCR2B,
	241	AVR8_REGIDX_TCNT2,
	242	AVR8_REGIDX_OCR2A,
	243	AVR8_REGIDX_OCR2B,
	244
	245	AVR8_REGIDX_ASSR = 0xb6,
	246
	247	AVR8_REGIDX_TWBR = 0xb8,
	248	AVR8_REGIDX_TWSR,
	249	AVR8_REGIDX_TWAR,
	250	AVR8_REGIDX_TWDR,
	251	AVR8_REGIDX_TWCR,
	252	AVR8_REGIDX_TWAMR,
	253
	254	AVR8_REGIDX_UCSR0A = 0xc0,
	255	AVR8_REGIDX_UCSR0B,
	256	AVR8_REGIDX_UCSR0C,
	257
	258	AVR8_REGIDX_UBRR0L = 0xc4,
	259	AVR8_REGIDX_UBRR0H,
	260	AVR8_REGIDX_UDR0
	261	};
	262
	263	enum
	264	{
	265	AVR8_REG_A = 0,
	266	AVR8_REG_B,
	267	AVR8_REG_C,
	268	AVR8_REG_D,
	269	};
	270
	271	enum
	272	{
	273	AVR8_INTIDX_SPI,
	274	AVR8_INTIDX_ICF1,
	275	AVR8_INTIDX_OCF1B,
	276	AVR8_INTIDX_OCF1A,
	277	AVR8_INTIDX_TOV1,
	278	AVR8_INTIDX_OCF2B,
	279	AVR8_INTIDX_OCF2A,
	280	AVR8_INTIDX_TOV2,
	281
	282	AVR8_INTIDX_COUNT,
	283	};
	284
	285	#define AVR8_EECR_EERE         0x01
	286	#define AVR8_EEARH_MASK         0x01
	287
	288	#define AVR8_SPSR_SPIF_MASK      0x80
	289	#define AVR8_SPSR_SPIF_SHIFT   7
	290	#define AVR8_SPSR_SPR2X_MASK   0x01
	291
	292	#define AVR8_SPCR_SPIE_MASK      0x80
	293	#define AVR8_SPCR_SPE_MASK      0x40
	294	#define AVR8_SPCR_DORD_MASK      0x20
	295	#define AVR8_SPCR_MSTR_MASK      0x10
	296	#define AVR8_SPCR_CPOL_MASK      0x08
	297	#define AVR8_SPCR_CPHA_MASK      0x04
	298	#define AVR8_SPCR_SPR_MASK      0x03
	299
86	300	DECLARE_LEGACY_CPU_DEVICE(ATMEGA88, atmega88);
87	301	DECLARE_LEGACY_CPU_DEVICE(ATMEGA644, atmega644);
88	302
	303	void avr8_update_interrupt(device_t *device, int source);
	304
89	305	CPU_DISASSEMBLE( avr8 );
90	306
91	307	#endif /* __AVR8_H__ */

trunk/src/mess/machine/avr8.h

r18696	r18697
1		#ifndef __EMU_MACHINE_AVR8_H__
2		#define __EMU_MACHINE_AVR8_H__
3
4		// Helpful enums and defines for the Atmel 8-bit AVR series of microcontrollers
5
6		namespace Avr8
7		{
8
9		enum
10		{
11		REGIDX_R0 = 0,
12		REGIDX_R1,
13		REGIDX_R2,
14		REGIDX_R3,
15		REGIDX_R4,
16		REGIDX_R5,
17		REGIDX_R6,
18		REGIDX_R7,
19		REGIDX_R8,
20		REGIDX_R9,
21		REGIDX_R10,
22		REGIDX_R11,
23		REGIDX_R12,
24		REGIDX_R13,
25		REGIDX_R14,
26		REGIDX_R15,
27		REGIDX_R16,
28		REGIDX_R17,
29		REGIDX_R18,
30		REGIDX_R19,
31		REGIDX_R20,
32		REGIDX_R21,
33		REGIDX_R22,
34		REGIDX_R23,
35		REGIDX_R24,
36		REGIDX_R25,
37		REGIDX_R26,
38		REGIDX_R27,
39		REGIDX_R28,
40		REGIDX_R29,
41		REGIDX_R30,
42		REGIDX_R31,
43
44		REGIDX_PINB = 0x23,
45		REGIDX_DDRB,
46		REGIDX_PORTB,
47		REGIDX_PINC,
48		REGIDX_DDRC,
49		REGIDX_PORTC,
50		REGIDX_PIND,
51		REGIDX_DDRD,
52		REGIDX_PORTD,
53
54		REGIDX_TIFR0 = 0x35,
55		REGIDX_TIFR1,
56		REGIDX_TIFR2,
57
58		REGIDX_PCIFR = 0x3b,
59		REGIDX_EIFR,
60		REGIDX_EIMSK,
61		REGIDX_GPIOR0,
62		REGIDX_EECR,
63		REGIDX_EEDR,
64		REGIDX_EEARL,
65		REGIDX_EEARH,
66		REGIDX_GTCCR,
67		REGIDX_TCCR0A,
68		REGIDX_TCCR0B,
69		REGIDX_TCNT0,
70		REGIDX_OCR0A,
71		REGIDX_OCR0B,
72
73		REGIDX_GPIOR1 = 0x4a,
74		REGIDX_GPIOR2,
75		REGIDX_SPCR,
76		REGIDX_SPSR,
77		REGIDX_SPDR,
78
79		REGIDX_ACSR = 0x50,
80
81		REGIDX_SMCR = 0x53,
82		REGIDX_MCUSR,
83		REGIDX_MCUCR,
84
85		REGIDX_SPMCSR = 0x57,
86
87		REGIDX_SPL = 0x5d,
88		REGIDX_SPH,
89		REGIDX_SREG,
90		REGIDX_WDTCSR,
91		REGIDX_CLKPR,
92
93		REGIDX_PRR = 0x64,
94
95		REGIDX_OSCCAL = 0x66,
96
97		REGIDX_PCICR = 0x68,
98		REGIDX_EICRA,
99
100		REGIDX_PCMSK0 = 0x6B,
101		REGIDX_PCMSK1,
102		REGIDX_PCMSK2,
103		REGIDX_TIMSK0,
104		REGIDX_TIMSK1,
105		REGIDX_TIMSK2,
106
107		REGIDX_ADCL = 0x78,
108		REGIDX_ADCH,
109		REGIDX_ADCSRA,
110		REGIDX_ADCSRB,
111		REGIDX_ADMUX,
112
113		REGIDX_DIDR0 = 0x7e,
114		REGIDX_DIDR1,
115		REGIDX_TCCR1A,
116		REGIDX_TCCR1B,
117		REGIDX_TCCR1C,
118
119		REGIDX_TCNT1L = 0x84,
120		REGIDX_TCNT1H,
121		REGIDX_ICR1L,
122		REGIDX_ICR1H,
123		REGIDX_OCR1AL,
124		REGIDX_OCR1AH,
125		REGIDX_OCR1BL,
126		REGIDX_OCR1BH,
127
128		REGIDX_TCCR2A = 0xb0,
129		REGIDX_TCCR2B,
130		REGIDX_TCNT2,
131		REGIDX_OCR2A,
132		REGIDX_OCR2B,
133
134		REGIDX_ASSR = 0xb6,
135
136		REGIDX_TWBR = 0xb8,
137		REGIDX_TWSR,
138		REGIDX_TWAR,
139		REGIDX_TWDR,
140		REGIDX_TWCR,
141		REGIDX_TWAMR,
142
143		REGIDX_UCSR0A = 0xc0,
144		REGIDX_UCSR0B,
145		REGIDX_UCSR0C,
146
147		REGIDX_UBRR0L = 0xc4,
148		REGIDX_UBRR0H,
149		REGIDX_UDR0
150		};
151
152		enum
153		{
154		WGM1_NORMAL = 0,
155		WGM1_PWM_8_PC,
156		WGM1_PWM_9_PC,
157		WGM1_PWM_10_PC,
158		WGM1_CTC_OCR,
159		WGM1_FAST_PWM_8,
160		WGM1_FAST_PWM_9,
161		WGM1_FAST_PWM_10,
162		WGM1_PWM_PFC_ICR,
163		WGM1_PWM_PFC_OCR,
164		WGM1_PWM_PC_ICR,
165		WGM1_PWM_PC_OCR,
166		WGM1_CTC_ICR,
167		WGM1_RESERVED,
168		WGM1_FAST_PWM_ICR,
169		WGM1_FAST_PWM_OCR
170		};
171
172		enum
173		{
174		WGM2_NORMAL = 0,
175		WGM2_PWM_PC,
176		WGM2_CTC_CMP,
177		WGM2_FAST_PWM,
178		WGM2_RESERVED0,
179		WGM2_PWM_PC_CMP,
180		WGM2_RESERVED1,
181		WGM2_FAST_PWM_CMP
182		};
183
184		} // namespace AVR8
185
186		#define AVR8_OCR1BH            (state->m_regs[Avr8::REGIDX_OCR1BH])
187		#define AVR8_OCR1BL            (state->m_regs[Avr8::REGIDX_OCR1BL])
188		#define AVR8_OCR1AH            (state->m_regs[Avr8::REGIDX_OCR1AH])
189		#define AVR8_OCR1AL            (state->m_regs[Avr8::REGIDX_OCR1AL])
190		#define AVR8_ICR1H            (state->m_regs[Avr8::REGIDX_ICR1H])
191		#define AVR8_ICR1L            (state->m_regs[Avr8::REGIDX_ICR1L])
192		#define AVR8_TCNT1H            (state->m_regs[Avr8::REGIDX_TCNT1H])
193		#define AVR8_TCNT1L            (state->m_regs[Avr8::REGIDX_TCNT1L])
194
195		#define AVR8_SREG_I                 0x80
196
197		#define AVR8_TCCR1B               (state->m_regs[Avr8::REGIDX_TCCR1B])
198		#define AVR8_TCCR1B_ICNC1_MASK      0x80
199		#define AVR8_TCCR1B_ICNC1_SHIFT      7
200		#define AVR8_TCCR1B_ICES1_MASK      0x40
201		#define AVR8_TCCR1B_ICES1_SHIFT      6
202		#define AVR8_TCCR1B_WGM1_32_MASK   0x18
203		#define AVR8_TCCR1B_WGM1_32_SHIFT   3
204		#define AVR8_TCCR1B_CS_MASK         0x03
205		#define AVR8_TCCR1B_CS_SHIFT      0
206
207		#define AVR8_TCCR1A               (state->m_regs[Avr8::REGIDX_TCCR1A])
208		#define AVR8_TCCR1A_COM1A_MASK      0xc0
209		#define AVR8_TCCR1A_COM1A_SHIFT      6
210		#define AVR8_TCCR1A_COM1B_MASK      0x30
211		#define AVR8_TCCR1A_COM1B_SHIFT      4
212		#define AVR8_TCCR1A_WGM1_10_MASK   0x03
213		#define AVR8_TCCR1A_WGM1_10_SHIFT   0
214		#define AVR8_TCCR1A_COM1A         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT)
215		#define AVR8_TCCR1A_COM1B         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT)
216		#define AVR8_TCCR1A_WGM1_10         (AVR8_TCCR1A & AVR8_TCCR1A_WGM1_10_MASK)
217
218		#define AVR8_TIMSK1            (state->m_regs[Avr8::REGIDX_TIMSK1])
219		#define AVR8_TIMSK1_ICIE1_MASK   0x20
220		#define AVR8_TIMSK1_OCIE1B_MASK   0x04
221		#define AVR8_TIMSK1_OCIE1A_MASK   0x02
222		#define AVR8_TIMSK1_TOIE1_MASK   0x01
223		#define AVR8_TIMSK1_ICIE1      ((AVR8_TIMSK1 & AVR8_TIMSK1_ICIE1_MASK) >> 5)
224		#define AVR8_TIMSK1_OCIE1B      ((AVR8_TIMSK1 & AVR8_TIMSK1_OCIE1B_MASK) >> 2)
225		#define AVR8_TIMSK1_OCIE1A      ((AVR8_TIMSK1 & AVR8_TIMSK1_OCIE1A_MASK) >> 1)
226		#define AVR8_TIMSK1_TOIE1      (AVR8_TIMSK1 & AVR8_TIMSK1_TOIE1_MASK)
227
228		#define AVR8_TCCR2B               (state->m_regs[Avr8::REGIDX_TCCR1B])
229		#define AVR8_TCCR2B_FOC2A_MASK      0x80
230		#define AVR8_TCCR2B_FOC2A_SHIFT      7
231		#define AVR8_TCCR2B_FOC2B_MASK      0x40
232		#define AVR8_TCCR2B_FOC2B_SHIFT      6
233		#define AVR8_TCCR2B_WGM2_2_MASK      0x08
234		#define AVR8_TCCR2B_WGM2_2_SHIFT   3
235		#define AVR8_TCCR2B_CS_MASK         0x03
236		#define AVR8_TCCR2B_CS_SHIFT      0
237		#define AVR8_TIMER2_CLOCK_SELECT   ((AVR8_TCCR2B & AVR8_TCCR2B_CS_MASK) >> AVR8_TCCR2B_CS_SHIFT)
238
239		#define AVR8_TCCR2A               (state->m_regs[Avr8::REGIDX_TCCR1A])
240		#define AVR8_TCCR2A_COM2A_MASK      0xc0
241		#define AVR8_TCCR2A_COM2A_SHIFT      6
242		#define AVR8_TCCR2A_COM2B_MASK      0x30
243		#define AVR8_TCCR2A_COM2B_SHIFT      4
244		#define AVR8_TCCR2A_WGM2_10_MASK   0x03
245		#define AVR8_TCCR2A_WGM2_10_SHIFT   0
246		#define AVR8_TCCR2A_COM2A         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2A_MASK) >> AVR8_TCCR2A_COM2A_SHIFT)
247		#define AVR8_TCCR2A_COM2B         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2B_MASK) >> AVR8_TCCR2A_COM2B_SHIFT)
248		#define AVR8_TCCR2A_WGM2_10         (AVR8_TCCR2A & AVR8_TCCR1A_WGM2_10_MASK)
249
250		#define AVR8_SPSR            (state->m_regs[Avr8::REGIDX_SPSR])
251		#define AVR8_SPSR_SPIF_MASK      0x80
252		#define AVR8_SPSR_SPIF_SHIFT   7
253		#define AVR8_SPSR_SPR2X_MASK   0x01
254		#define AVR8_SPSR_SPR2X         (AVR8_SPSR & AVR8_SPSR_SPR2X_MASK)
255
256		#define AVR8_SPCR            (state->m_regs[Avr8::REGIDX_SPCR])
257		#define AVR8_SPCR_SPIE_MASK      0x80
258		#define AVR8_SPCR_SPE_MASK      0x40
259		#define AVR8_SPCR_DORD_MASK      0x20
260		#define AVR8_SPCR_MSTR_MASK      0x10
261		#define AVR8_SPCR_CPOL_MASK      0x08
262		#define AVR8_SPCR_CPHA_MASK      0x04
263		#define AVR8_SPCR_SPR_MASK      0x03
264		#define AVR8_SPCR_SPIE         ((AVR8_SPCR & AVR8_SPCR_SPIE_MASK) >> 7)
265		#define AVR8_SPCR_SPE         ((AVR8_SPCR & AVR8_SPCR_SPE_MASK) >> 6)
266		#define AVR8_SPCR_DORD         ((AVR8_SPCR & AVR8_SPCR_DORD_MASK) >> 5)
267		#define AVR8_SPCR_MSTR         ((AVR8_SPCR & AVR8_SPCR_MSTR_MASK) >> 4)
268		#define AVR8_SPCR_CPOL         ((AVR8_SPCR & AVR8_SPCR_CPOL_MASK) >> 3)
269		#define AVR8_SPCR_CPHA         ((AVR8_SPCR & AVR8_SPCR_CPHA_MASK) >> 2)
270		#define AVR8_SPCR_SPR         (AVR8_SPCR & AVR8_SPCR_SPR_MASK)
271
272		#define AVR8_TIFR1            (state->m_regs[Avr8::REGIDX_TIFR1])
273		#define AVR8_TIFR1_ICF1_MASK   0x20
274		#define AVR8_TIFR1_ICF1_SHIFT   5
275		#define AVR8_TIFR1_OCF1B_MASK   0x04
276		#define AVR8_TIFR1_OCF1B_SHIFT   2
277		#define AVR8_TIFR1_OCF1A_MASK   0x02
278		#define AVR8_TIFR1_OCF1A_SHIFT   1
279		#define AVR8_TIFR1_TOV1_MASK   0x01
280		#define AVR8_TIFR1_TOV1_SHIFT   0
281
282		#define AVR8_DDRD            (state->m_regs[Avr8::REGIDX_DDRD])
283		#define AVR8_DDRC            (state->m_regs[Avr8::REGIDX_DDRC])
284		#define AVR8_PORTB            (state->m_regs[Avr8::REGIDX_PORTB])
285		#define AVR8_DDRB            (state->m_regs[Avr8::REGIDX_DDRB])
286
287		#define AVR8_OCR1A            ((AVR8_OCR1AH << 8) | AVR8_OCR1AL)
288		#define AVR8_OCR1B            ((AVR8_OCR1BH << 8) | AVR8_OCR1BL)
289		#define AVR8_ICR1            ((AVR8_ICR1H  << 8) | AVR8_ICR1L)
290		#define AVR8_TCNT1            ((AVR8_TCNT1H << 8) | AVR8_TCNT1L)
291		#define AVR8_WGM1            (((AVR8_TCCR1B & 0x18) >> 1) | (AVR8_TCCR1A & 0x03))
292		#define AVR8_TCNT1_DIR         (state->m_tcnt1_direction)
293
294		#define AVR8_OCR2B            state->m_regs[Avr8::REGIDX_OCR2B]
295		#define AVR8_OCR2A            state->m_regs[Avr8::REGIDX_OCR2A]
296		#define AVR8_TCNT2            state->m_regs[Avr8::REGIDX_TCNT2]
297		#define AVR8_WGM2            (((AVR8_TCCR2B & 0x08) >> 1) | (AVR8_TCCR2A & 0x03))
298
299		#endif // __EMU_MACHINE_AVR8_H__

trunk/src/mess/drivers/uzebox.c

r18696	r18697
1	1
2	2	#include "emu.h"
3	3	#include "cpu/avr8/avr8.h"
4		#include "machine/avr8.h"
5	4	#include "sound/dac.h"
6	5	#include "imagedev/cartslot.h"
7	6

trunk/src/mess/drivers/craft.c

r18696	r18697
6	6
7	7	#include "emu.h"
8	8	#include "cpu/avr8/avr8.h"
9		#include "machine/avr8.h"
10	9	#include "sound/dac.h"
11	10
12	11	#define VERBOSE_LEVEL   (99)
r18696	r18697
33	32	#define MASTER_CLOCK 20000000
34	33
35	34	/****************************************************\
36		* I/O devices                                        *
	35	* I/O defines                                        *
37	36	\****************************************************/
38	37
	38	#define AVR8_DDRD            (state->m_regs[AVR8_REGIDX_DDRD])
	39	#define AVR8_DDRC            (state->m_regs[AVR8_REGIDX_DDRC])
	40	#define AVR8_PORTB            (state->m_regs[AVR8_REGIDX_PORTB])
	41	#define AVR8_DDRB            (state->m_regs[AVR8_REGIDX_DDRB])
39	42
	43	#define AVR8_SPSR            (state->m_regs[AVR8_REGIDX_SPSR])
	44	#define AVR8_SPSR_SPR2X         (AVR8_SPSR & AVR8_SPSR_SPR2X_MASK)
40	45
	46	#define AVR8_SPCR            (state->m_regs[AVR8_REGIDX_SPCR])
	47	#define AVR8_SPCR_SPIE         ((AVR8_SPCR & AVR8_SPCR_SPIE_MASK) >> 7)
	48	#define AVR8_SPCR_SPE         ((AVR8_SPCR & AVR8_SPCR_SPE_MASK) >> 6)
	49	#define AVR8_SPCR_DORD         ((AVR8_SPCR & AVR8_SPCR_DORD_MASK) >> 5)
	50	#define AVR8_SPCR_MSTR         ((AVR8_SPCR & AVR8_SPCR_MSTR_MASK) >> 4)
	51	#define AVR8_SPCR_CPOL         ((AVR8_SPCR & AVR8_SPCR_CPOL_MASK) >> 3)
	52	#define AVR8_SPCR_CPHA         ((AVR8_SPCR & AVR8_SPCR_CPHA_MASK) >> 2)
	53	#define AVR8_SPCR_SPR         (AVR8_SPCR & AVR8_SPCR_SPR_MASK)
41	54
42	55
	56	/****************************************************\
	57	* I/O devices                                        *
	58	\****************************************************/
	59
43	60	class craft_state : public driver_device
44	61	{
45	62	public:
r18696	r18697
47	64	: driver_device(mconfig, type, tag),
48	65	m_maincpu(*this, "maincpu")
49	66	{
50		m_timer0_increment = 1;
51
52		m_timer1_increment = 1;
53
54		m_timer2_increment = 1;
55	67	}
56	68
57	69	virtual void machine_start();
r18696	r18697
59	71	dac_device* dac;
60	72
61	73	UINT8 m_regs[0x100];
	74	UINT8* m_eeprom;
62	75
63	76	required_device<cpu_device> m_maincpu;
64	77
65		emu_timer* m_timer0_timer;
66		UINT8 m_timer0_top;
67		INT32 m_timer0_increment;
68
69		emu_timer* m_timer1_timer;
70		UINT16 m_timer1_top;
71		INT32 m_timer1_increment;
72
73		emu_timer* m_timer2_timer;
74		UINT8 m_timer2_top;
75		INT32 m_timer2_increment;
76	78	DECLARE_READ8_MEMBER(avr8_read);
77	79	DECLARE_WRITE8_MEMBER(avr8_write);
78	80	DECLARE_DRIVER_INIT(craft);
r18696	r18697
85	87
86	88	void craft_state::machine_start()
87	89	{
88		m_timer0_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(craft_state::avr8_timer0_tick),this));
89		m_timer1_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(craft_state::avr8_timer1_tick),this));
90		m_timer2_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(craft_state::avr8_timer2_tick),this));
91	90	}
92		enum
93		{
94		AVR8_REG_A = 0,
95		AVR8_REG_B,
96		AVR8_REG_C,
97		AVR8_REG_D,
98		};
99	91
100		static const char avr8_reg_name[4] = { 'A', 'B', 'C', 'D' };
101
102		TIMER_CALLBACK_MEMBER(craft_state::avr8_timer0_tick)
103		{
104		// TODO
105		}
106
107		TIMER_CALLBACK_MEMBER(craft_state::avr8_timer1_tick)
108		{
109		/* TODO: Handle comparison, setting OC1x pins, detection of BOTTOM and TOP */
110
111		UINT16 count = (m_regs[Avr8::REGIDX_TCNT1H] << 8) | m_regs[Avr8::REGIDX_TCNT1L];
112		INT32 wgm1 = ((m_regs[Avr8::REGIDX_TCCR1B] & AVR8_TCCR1B_WGM1_32_MASK) >> 1) |
113		(m_regs[Avr8::REGIDX_TCCR1A] & AVR8_TCCR1A_WGM1_10_MASK);
114
115		// Cache things in array form to avoid a compare+branch inside a potentially high-frequency timer
116		//UINT8 compare_mode[2] = { (m_regs[Avr8::REGIDX_TCCR1A] & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT,
117		//(m_regs[Avr8::REGIDX_TCCR1A] & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT };
118		UINT16 ocr1[2] = { (m_regs[Avr8::REGIDX_OCR1AH] << 8) | m_regs[Avr8::REGIDX_OCR1AL],
119		(m_regs[Avr8::REGIDX_OCR1BH] << 8) | m_regs[Avr8::REGIDX_OCR1BL] };
120		INT32 int_lines[2] = { AVR8_INT_T1COMPA, AVR8_INT_T1COMPB };
121		INT32 int_masks[2] = { AVR8_TIMSK1_OCIE1A_MASK, AVR8_TIMSK1_OCIE1B_MASK };
122		INT32 increment = m_timer1_increment;
123
124		for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
125		{
126		switch(wgm1)
127		{
128		case Avr8::WGM1_FAST_PWM_OCR:
129		if(count == ocr1[reg])
130		{
131		if (reg == 0)
132		{
133		m_regs[Avr8::REGIDX_TIFR1] |= (1 << AVR8_TIFR1_TOV1_SHIFT);
134		count = 0;
135		increment = 0;
136		}
137		if (m_regs[Avr8::REGIDX_TIMSK1] & int_masks[reg])
138		{
139		m_maincpu->set_input_line(int_lines[reg], 1);
140		}
141		}
142		else if(count == 0)
143		{
144		if (reg == 0)
145		{
146		m_regs[Avr8::REGIDX_TIFR1] &= ~AVR8_TIFR1_TOV1_MASK;
147		}
148		if (m_regs[Avr8::REGIDX_TIMSK1] & int_masks[reg])
149		{
150		m_maincpu->set_input_line(int_lines[reg], 0);
151		}
152		}
153		break;
154
155		default:
156		// TODO
157		break;
158		}
159		/*
160		switch(compare_mode[reg])
161		{
162		case 0:
163		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Normal port operation (OC1 disconnected)\n");
164		break;
165
166		case 1:
167		case 2:
168		// TODO
169		break;
170
171		case 3:
172		break;
173		}
174		*/
175		}
176
177		count += increment;
178		m_regs[Avr8::REGIDX_TCNT1H] = (count >> 8) & 0xff;
179		m_regs[Avr8::REGIDX_TCNT1L] = count & 0xff;
180		}
181
182	92	READ8_MEMBER(craft_state::avr8_read)
183	93	{
184
185		if(offset <= Avr8::REGIDX_R31)
186		{
187		return m_regs[offset];
188		}
189
190	94	switch( offset )
191	95	{
192		case Avr8::REGIDX_SPL:
193		case Avr8::REGIDX_SPH:
194		case Avr8::REGIDX_SREG:
	96	case AVR8_REGIDX_EEDR:
195	97	return m_regs[offset];
196	98
197	99	default:
r18696	r18697
252	154	{
253	155	// TODO
254	156	//verboselog(machine, 0, "avr8_change_port: PORT%c lines %02x changed\n", avr8_reg_name[reg], changed);
255		if (reg == AVR8_REG_D) {
256		state->dac->write_unsigned8(data & 0x7f);
257		}
258	157	}
259		}
260	158
261		namespace Avr8
262		{
	159	if (reg == AVR8_REG_D) {
	160	UINT8 audio_sample = (data & 0x02) | ((data & 0xf4) >> 2);
263	161
264		enum
265		{
266		INTIDX_SPI,
267		INTIDX_ICF1,
268		INTIDX_OCF1B,
269		INTIDX_OCF1A,
270		INTIDX_TOV1,
271
272		INTIDX_COUNT,
273		};
274
275		class CInterruptCondition
276		{
277		public:
278		UINT8 m_intindex;
279		UINT8 m_regindex;
280		UINT8 m_regmask;
281		UINT8 m_regshift;
282		UINT8* mp_reg;
283		};
284
285		static const CInterruptCondition s_int_conditions[INTIDX_COUNT] =
286		{
287		{ INTIDX_SPI,   REGIDX_SPSR,   AVR8_SPSR_SPIF_MASK,   AVR8_SPSR_SPIF_SHIFT,   NULL },
288		{ INTIDX_ICF1,   REGIDX_TIFR1,   AVR8_TIFR1_ICF1_MASK,   AVR8_TIFR1_ICF1_SHIFT,   NULL },
289		{ INTIDX_OCF1B,   REGIDX_TIFR1,   AVR8_TIFR1_OCF1B_MASK,   AVR8_TIFR1_OCF1B_SHIFT,   NULL },
290		{ INTIDX_OCF1A,   REGIDX_TIFR1,   AVR8_TIFR1_OCF1A_MASK,   AVR8_TIFR1_OCF1A_SHIFT,   NULL },
291		{ INTIDX_TOV1,   REGIDX_TIFR1,   AVR8_TIFR1_TOV1_MASK,   AVR8_TIFR1_TOV1_SHIFT,   NULL }
292		};
293
	162	state->dac->write_unsigned8(audio_sample << 2);
	163	}
294	164	}
295	165
296		static void avr8_interrupt_update(running_machine &machine, int source)
297		{
298		// TODO
299		verboselog(machine, 0, "avr8_interrupt_update: TODO; source interrupt is %d\n", source);
300		}
301
302	166	/****************/
303	167	/* SPI Handling */
304	168	/****************/
r18696	r18697
319	183	{
320	184	// TODO
321	185	//craft_state *state = machine.driver_data<craft_state>();
322		verboselog(machine, 0, "avr8_spi_update_masterslave_select: TODO; AVR is %s\n", AVR8_SPCR_MSTR ? "Master" : "Slave");
	186	//verboselog(machine, 0, "avr8_spi_update_masterslave_select: TODO; AVR is %s\n", AVR8_SPCR_MSTR ? "Master" : "Slave");
323	187	}
324	188
325	189	static void avr8_spi_update_clock_polarity(running_machine &machine)
326	190	{
327	191	// TODO
328	192	//craft_state *state = machine.driver_data<craft_state>();
329		verboselog(machine, 0, "avr8_spi_update_clock_polarity: TODO; SCK is Active-%s\n", AVR8_SPCR_CPOL ? "Low" : "High");
	193	//verboselog(machine, 0, "avr8_spi_update_clock_polarity: TODO; SCK is Active-%s\n", AVR8_SPCR_CPOL ? "Low" : "High");
330	194	}
331	195
332	196	static void avr8_spi_update_clock_phase(running_machine &machine)
333	197	{
334	198	// TODO
335	199	//craft_state *state = machine.driver_data<craft_state>();
336		verboselog(machine, 0, "avr8_spi_update_clock_phase: TODO; Sampling edge is %s\n", AVR8_SPCR_CPHA ? "Trailing" : "Leading");
	200	//verboselog(machine, 0, "avr8_spi_update_clock_phase: TODO; Sampling edge is %s\n", AVR8_SPCR_CPHA ? "Trailing" : "Leading");
337	201	}
338	202
339	203	static const UINT8 avr8_spi_clock_divisor[8] = { 4, 16, 64, 128, 2, 8, 32, 64 };
r18696	r18697
342	206	{
343	207	// TODO
344	208	//craft_state *state = machine.driver_data<craft_state>();
345		verboselog(machine, 0, "avr8_spi_update_clock_rate: TODO; New clock rate should be f/%d\n", avr8_spi_clock_divisor[AVR8_SPCR_SPR] / (AVR8_SPSR_SPR2X ? 2 : 1));
	209	//verboselog(machine, 0, "avr8_spi_update_clock_rate: TODO; New clock rate should be f/%d\n", avr8_spi_clock_divisor[AVR8_SPCR_SPR] / (AVR8_SPSR_SPR2X ? 2 : 1));
346	210	}
347	211
348	212	static void avr8_change_spcr(running_machine &machine, UINT8 data)
r18696	r18697
360	224	if(changed & AVR8_SPCR_SPIE_MASK)
361	225	{
362	226	// Check for SPI interrupt condition
363		avr8_interrupt_update(machine, Avr8::INTIDX_SPI);
	227	avr8_update_interrupt(state->m_maincpu, AVR8_INTIDX_SPI);
364	228	}
365	229
366	230	if(low_to_high & AVR8_SPCR_SPE_MASK)
r18696	r18697
412	276	}
413	277	}
414	278
415		/********************/
416		/* Timer 1 Handling */
417		/********************/
418
419		static void avr8_change_timsk1(running_machine &machine, UINT8 data)
420		{
421		craft_state *state = machine.driver_data<craft_state>();
422
423		UINT8 oldtimsk = AVR8_TIMSK1;
424		UINT8 newtimsk = data;
425		UINT8 changed = newtimsk ^ oldtimsk;
426
427		AVR8_TIMSK1 = newtimsk;
428
429		if(changed & AVR8_TIMSK1_ICIE1_MASK)
430		{
431		// Check for Input Capture Interrupt interrupt condition
432		avr8_interrupt_update(machine, Avr8::INTIDX_ICF1);
433		}
434
435		if(changed & AVR8_TIMSK1_OCIE1B_MASK)
436		{
437		// Check for Output Compare B Interrupt interrupt condition
438		avr8_interrupt_update(machine, Avr8::INTIDX_OCF1B);
439		}
440
441		if(changed & AVR8_TIMSK1_OCIE1A_MASK)
442		{
443		// Check for Output Compare A Interrupt interrupt condition
444		avr8_interrupt_update(machine, Avr8::INTIDX_OCF1A);
445		}
446
447		if(changed & AVR8_TIMSK1_TOIE1_MASK)
448		{
449		// Check for Output Compare A Interrupt interrupt condition
450		avr8_interrupt_update(machine, Avr8::INTIDX_TOV1);
451		}
452		}
453
454		static void avr8_update_timer1_waveform_gen_mode(running_machine &machine)
455		{
456		// TODO
457		craft_state *state = machine.driver_data<craft_state>();
458		state->m_timer1_top = 0;
459		verboselog(machine, 0, "avr8_update_timer1_waveform_gen_mode: TODO; WGM1 is %d\n", AVR8_WGM1 );
460		switch(AVR8_WGM1)
461		{
462		case Avr8::WGM1_NORMAL:
463		state->m_timer1_top = 0xffff;
464		break;
465
466		case Avr8::WGM1_PWM_8_PC:
467		case Avr8::WGM1_FAST_PWM_8:
468		state->m_timer1_top = 0x00ff;
469		break;
470
471		case Avr8::WGM1_PWM_9_PC:
472		case Avr8::WGM1_FAST_PWM_9:
473		state->m_timer1_top = 0x01ff;
474		break;
475
476		case Avr8::WGM1_PWM_10_PC:
477		case Avr8::WGM1_FAST_PWM_10:
478		state->m_timer1_top = 0x03ff;
479		break;
480
481		case Avr8::WGM1_PWM_PFC_ICR:
482		case Avr8::WGM1_PWM_PC_ICR:
483		case Avr8::WGM1_CTC_ICR:
484		case Avr8::WGM1_FAST_PWM_ICR:
485		state->m_timer1_top = AVR8_ICR1;
486		break;
487
488		case Avr8::WGM1_PWM_PFC_OCR:
489		case Avr8::WGM1_PWM_PC_OCR:
490		case Avr8::WGM1_CTC_OCR:
491		case Avr8::WGM1_FAST_PWM_OCR:
492		state->m_timer1_top = AVR8_OCR1A;
493		break;
494
495		default:
496		verboselog(machine, 0, "avr8_update_timer1_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM1);
497		break;
498		}
499		}
500
501		static void avr8_changed_tccr1a(running_machine &machine, UINT8 data)
502		{
503		craft_state *state = machine.driver_data<craft_state>();
504
505		UINT8 oldtccr = AVR8_TCCR1A;
506		UINT8 newtccr = data;
507		UINT8 changed = newtccr ^ oldtccr;
508
509		state->m_regs[Avr8::REGIDX_TCCR1A] = newtccr;
510
511		if(changed & AVR8_TCCR1A_WGM1_10_MASK)
512		{
513		// TODO
514		avr8_update_timer1_waveform_gen_mode(machine);
515		}
516		}
517
518		static void avr8_update_timer1_input_noise_canceler(running_machine &machine)
519		{
520		}
521
522		static void avr8_update_timer1_input_edge_select(running_machine &machine)
523		{
524		// TODO
525		//craft_state *state = machine.driver_data<craft_state>();
526		verboselog(machine, 0, "avr8_update_timer1_input_edge_select: TODO; Clocking edge is %s\n", "test");
527		}
528
529		TIMER_CALLBACK_MEMBER(craft_state::avr8_timer2_tick)
530		{
531		/* TODO: Handle comparison, setting OC2x pins, detection of BOTTOM and TOP
532
533		UINT16 count = AVR8_TCNT2;
534		count += m_timer1_increment;
535		for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
536		{
537		UINT8 mode = (reg == AVR8_REG_A) ? AVR8_TCCR2A_COM2A : AVR8_TCCR2A_COM2B;
538
539		if(!mode)
540		{
541		// Normal port operation, OC2n disconnected
542		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; OC2%c disconnected, normal port operation\n", avr8_reg_name[reg]);
543		return;
544		}
545
546		switch(AVR8_WGM2)
547		{
548		case Avr8::WGM2_NORMAL:
549		case Avr8::WGM2_CTC_CMP:
550		switch(mode)
551		{
552		case 1: // Toggle OC2n on Compare Match
553		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Toggle OC2%c on Compare Match\n", avr8_reg_name[reg]);
554		break;
555		case 2: // Clear OC2n on Compare Match
556		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Clear OC2%c on Compare Match\n", avr8_reg_name[reg]);
557		break;
558		case 3: // Set OC2n on Compare Match
559		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Set OC2%c on Compare Match\n", avr8_reg_name[reg]);
560		break;
561		}
562		break;
563
564		case Avr8::WGM2_PWM_PC:
565		switch(mode)
566		{
567		case 1: // Normal port operation, OC2n disconnected
568		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; OC2%c disconnected, normal port operation\n", avr8_reg_name[reg]);
569		break;
570		case 2: // Clear OC2n on match when up-counting, set when down-counting
571		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Clear OC2%c on match when up-counting, set when down-counting\n", avr8_reg_name[reg]);
572		break;
573		case 3: // Set OC2n on match when up-counting, clear when down-counting
574		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Set OC2%c on match when up-counting, clear when down-counting\n", avr8_reg_name[reg]);
575		break;
576		}
577		break;
578
579		case Avr8::WGM2_PWM_PC_CMP:
580		switch(mode)
581		{
582		case 1: // Toggle OC2n on compare match
583		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Toggle OC2%c on compare match\n", avr8_reg_name[reg]);
584		break;
585		case 2: // Clear OC2n on match when up-counting, set when down-counting
586		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Clear OC2%c on match when up-counting, set when down-counting\n", avr8_reg_name[reg]);
587		break;
588		case 3: // Set OC2n on match when up-counting, clear when down-counting
589		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Set OC2%c on match when up-counting, clear when down-counting\n", avr8_reg_name[reg]);
590		break;
591		}
592		break;
593
594
595		case Avr8::WGM2_FAST_PWM:
596		switch(mode)
597		{
598		case 1: // Normal port operation, OC2n disconnected
599		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; OC2%c disconnected, normal port operation\n", avr8_reg_name[reg]);
600		break;
601		case 2: // Clear OC2n on match, set at BOTTOM
602		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Clear OC2%c on match, set at BOTTOM\n", avr8_reg_name[reg]);
603		break;
604		case 3: // Set OC2n on match, clear at BOTTOM
605		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Set OC2%c on match, clear at BOTTOM\n", avr8_reg_name[reg]);
606		break;
607		}
608		break;
609
610		case Avr8::WGM2_FAST_PWM_CMP:
611		switch(mode)
612		{
613		case 1: // Toggle OC2n on compare match
614		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Toggle OC2%c on compare match\n", avr8_reg_name[reg]);
615		break;
616		case 2: // Clear OC2n on match, set at BOTTOM
617		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Clear OC2%c on match, set at BOTTOM\n", avr8_reg_name[reg]);
618		break;
619		case 3: // Set OC2n on match, clear at BOTTOM
620		//verboselog(machine(), 0, "avr8_update_timer2_compare_mode: TODO; Set OC2%c on match, clear at BOTTOM\n", avr8_reg_name[reg]);
621		break;
622		}
623		break;
624
625		default:
626		break;
627		}
628		}
629		*/
630		}
631
632		static void avr8_update_timer1_clock_source(running_machine &machine)
633		{
634		craft_state *state = machine.driver_data<craft_state>();
635		attotime period;
636		switch(AVR8_TIMER2_CLOCK_SELECT)
637		{
638		case 0: // Counter stopped
639		period = attotime::never;
640		break;
641		case 1: // Clk/1; no prescaling
642		period = attotime::from_hz(MASTER_CLOCK);
643		break;
644		case 2: // Clk/8
645		period = attotime::from_hz(MASTER_CLOCK/8);
646		break;
647		case 3: // Clk/32
648		period = attotime::from_hz(MASTER_CLOCK/32);
649		break;
650		case 4: // Clk/64
651		period = attotime::from_hz(MASTER_CLOCK/64);
652		break;
653		case 5: // Clk/128
654		period = attotime::from_hz(MASTER_CLOCK/128);
655		break;
656		case 6: // T1 trigger, falling edge
657		case 7: // T1 trigger, rising edge
658		period = attotime::never;
659		verboselog(machine, 0, "avr8_update_timer1_clock_source: T1 Trigger mode not implemented yet\n");
660		break;
661		}
662		state->m_timer1_timer->adjust(period, 0, period);
663		}
664
665		static void avr8_changed_tccr1b(running_machine &machine, UINT8 data)
666		{
667		craft_state *state = machine.driver_data<craft_state>();
668
669		UINT8 oldtccr = AVR8_TCCR1B;
670		UINT8 newtccr = data;
671		UINT8 changed = newtccr ^ oldtccr;
672
673		state->m_regs[Avr8::REGIDX_TCCR1B] = newtccr;
674
675		if(changed & AVR8_TCCR1B_ICNC1_MASK)
676		{
677		// TODO
678		avr8_update_timer1_input_noise_canceler(machine);
679		}
680
681		if(changed & AVR8_TCCR1B_ICES1_MASK)
682		{
683		// TODO
684		avr8_update_timer1_input_edge_select(machine);
685		}
686
687		if(changed & AVR8_TCCR1B_WGM1_32_MASK)
688		{
689		// TODO
690		avr8_update_timer1_waveform_gen_mode(machine);
691		}
692
693		if(changed & AVR8_TCCR1B_CS_MASK)
694		{
695		avr8_update_timer1_clock_source(machine);
696		}
697		}
698
699		static void avr8_update_timer2_waveform_gen_mode(running_machine &machine)
700		{
701		craft_state *state = machine.driver_data<craft_state>();
702		state->m_timer2_top = 0;
703		switch(AVR8_WGM2)
704		{
705		case Avr8::WGM2_NORMAL:
706		case Avr8::WGM2_PWM_PC:
707		case Avr8::WGM2_FAST_PWM:
708		state->m_timer2_top = 0x00ff;
709		break;
710
711		case Avr8::WGM2_CTC_CMP:
712		case Avr8::WGM2_PWM_PC_CMP:
713		case Avr8::WGM2_FAST_PWM_CMP:
714		state->m_timer2_top = AVR8_OCR2A;
715		break;
716
717		default:
718		verboselog(machine, 0, "avr8_update_timer2_waveform_gen_mode: Unsupported waveform generation type: %d\n", AVR8_WGM2);
719		break;
720		}
721		}
722
723		static void avr8_changed_tccr2a(running_machine &machine, UINT8 data)
724		{
725		craft_state *state = machine.driver_data<craft_state>();
726
727		UINT8 oldtccr = AVR8_TCCR2A;
728		UINT8 newtccr = data;
729		UINT8 changed = newtccr ^ oldtccr;
730
731		if(changed & AVR8_TCCR2A_WGM2_10_MASK)
732		{
733		// TODO
734		avr8_update_timer2_waveform_gen_mode(machine);
735		}
736		}
737
738		static void avr8_update_timer2_clock_source(running_machine &machine)
739		{
740		craft_state *state = machine.driver_data<craft_state>();
741		attotime period;
742		switch(AVR8_TIMER2_CLOCK_SELECT)
743		{
744		case 0: // Counter stopped
745		period = attotime::never;
746		break;
747		case 1: // Clk/1; no prescaling
748		period = attotime::from_hz(MASTER_CLOCK);
749		break;
750		case 2: // Clk/8
751		period = attotime::from_hz(MASTER_CLOCK/8);
752		break;
753		case 3: // Clk/32
754		period = attotime::from_hz(MASTER_CLOCK/32);
755		break;
756		case 4: // Clk/64
757		period = attotime::from_hz(MASTER_CLOCK/64);
758		break;
759		case 5: // Clk/128
760		period = attotime::from_hz(MASTER_CLOCK/128);
761		break;
762		case 6: // Clk/256
763		period = attotime::from_hz(MASTER_CLOCK/256);
764		break;
765		case 7: // Clk/1024
766		period = attotime::from_hz(MASTER_CLOCK/1024);
767		break;
768		}
769		state->m_timer2_timer->adjust(period, 0, period);
770		}
771
772		static void avr8_timer2_force_output_compare(running_machine &machine, int reg)
773		{
774		// TODO
775		verboselog(machine, 0, "avr8_force_output_compare: TODO; should be forcing OC2%c\n", avr8_reg_name[reg]);
776		}
777
778		static void avr8_changed_tccr2b(running_machine &machine, UINT8 data)
779		{
780		craft_state *state = machine.driver_data<craft_state>();
781
782		UINT8 oldtccr = AVR8_TCCR2B;
783		UINT8 newtccr = data;
784		UINT8 changed = newtccr ^ oldtccr;
785
786		if(changed & AVR8_TCCR2B_FOC2A_MASK)
787		{
788		// TODO
789		avr8_timer2_force_output_compare(machine, AVR8_REG_A);
790		}
791
792		if(changed & AVR8_TCCR2B_FOC2B_MASK)
793		{
794		// TODO
795		avr8_timer2_force_output_compare(machine, AVR8_REG_B);
796		}
797
798		if(changed & AVR8_TCCR2B_WGM2_2_MASK)
799		{
800		// TODO
801		avr8_update_timer2_waveform_gen_mode(machine);
802		}
803
804		if(changed & AVR8_TCCR2B_CS_MASK)
805		{
806		avr8_update_timer2_clock_source(machine);
807		}
808		}
809
810		static void avr8_update_ocr1(running_machine &machine, UINT16 newval, UINT8 reg)
811		{
812		craft_state *state = machine.driver_data<craft_state>();
813		UINT8 *p_reg_h = (reg == AVR8_REG_A) ? &AVR8_OCR1AH : &AVR8_OCR1BH;
814		UINT8 *p_reg_l = (reg == AVR8_REG_A) ? &AVR8_OCR1AL : &AVR8_OCR1BL;
815		*p_reg_h = (UINT8)(newval >> 8);
816		*p_reg_l = (UINT8)newval;
817
818		// TODO
819		verboselog(machine, 0, "avr8_update_ocr1: TODO: new OCR1%c = %04x\n", avr8_reg_name[reg], newval);
820		}
821
822	279	WRITE8_MEMBER(craft_state::avr8_write)
823	280	{
824		craft_state *state = machine().driver_data<craft_state>();
825		if(offset <= Avr8::REGIDX_R31)
826		{
827		m_regs[offset] = data;
828		return;
829		}
830
831	281	switch( offset )
832	282	{
833		case Avr8::REGIDX_OCR1BH:
834		verboselog(machine(), 0, "AVR8: OCR1BH = %02x\n", data );
835		avr8_update_ocr1(machine(), (AVR8_OCR1B & 0x00ff) | (data << 8), AVR8_REG_B);
	283	case AVR8_REGIDX_SPSR:
	284	avr8_change_spsr(machine(), data);
836	285	break;
837	286
838		case Avr8::REGIDX_OCR1BL:
839		verboselog(machine(), 0, "AVR8: OCR1BL = %02x\n", data );
840		avr8_update_ocr1(machine(), (AVR8_OCR1B & 0xff00) | data, AVR8_REG_B);
	287	case AVR8_REGIDX_SPCR:
	288	avr8_change_spcr(machine(), data);
841	289	break;
842	290
843		case Avr8::REGIDX_OCR1AH:
844		verboselog(machine(), 0, "AVR8: OCR1AH = %02x\n", data );
845		avr8_update_ocr1(machine(), (AVR8_OCR1A & 0x00ff) | (data << 8), AVR8_REG_A);
	291	case AVR8_REGIDX_SPDR:
	292	// TODO
846	293	break;
847	294
848		case Avr8::REGIDX_OCR1AL:
849		verboselog(machine(), 0, "AVR8: OCR1AL = %02x\n", data );
850		avr8_update_ocr1(machine(), (AVR8_OCR1A & 0xff00) | data, AVR8_REG_A);
	295	case AVR8_REGIDX_EECR:
	296	if (data & AVR8_EECR_EERE)
	297	{
	298	UINT16 addr = (m_regs[AVR8_REGIDX_EEARH] & AVR8_EEARH_MASK) << 8;
	299	addr |= m_regs[AVR8_REGIDX_EEARL];
	300	m_regs[AVR8_REGIDX_EEDR] = m_eeprom[addr];
	301	}
851	302	break;
852	303
853		case Avr8::REGIDX_TCCR1B:
854		verboselog(machine(), 0, "AVR8: TCCR1B = %02x\n", data );
855		avr8_changed_tccr1b(machine(), data);
856		break;
857
858		case Avr8::REGIDX_TCCR1A:
859		verboselog(machine(), 0, "AVR8: TCCR1A = %02x\n", data );
860		avr8_changed_tccr1a(machine(), data);
861		break;
862
863		case Avr8::REGIDX_TIMSK1:
864		verboselog(machine(), 0, "AVR8: TIMSK1 = %02x\n", data );
865		avr8_change_timsk1(machine(), data);
866		break;
867
868		case Avr8::REGIDX_TCCR2B:
869		verboselog(machine(), 0, "AVR8: TCCR2B = %02x\n", data );
870		avr8_changed_tccr2b(machine(), data);
871		break;
872
873		case Avr8::REGIDX_TCCR2A:
874		verboselog(machine(), 0, "AVR8: TCCR2A = %02x\n", data );
875		avr8_changed_tccr2a(machine(), data);
876		break;
877
878		case Avr8::REGIDX_TCNT2:
879		//verboselog(machine(), 0, "AVR8: TCNT2 = %02x\n", data );
880		AVR8_TCNT2 = data;
881		break;
882
883		case Avr8::REGIDX_GTCCR:
884		//verboselog(machine(), 0, "AVR8: GTCCR = %02x\n", data );
885		// TODO
886		break;
887
888		case Avr8::REGIDX_SPL:
889		case Avr8::REGIDX_SPH:
890		case Avr8::REGIDX_SREG:
	304	case AVR8_REGIDX_EEARL:
	305	case AVR8_REGIDX_EEARH:
891	306	m_regs[offset] = data;
892	307	break;
893	308
894		case Avr8::REGIDX_SPSR:
895		avr8_change_spsr(machine(), data);
896		break;
897
898		case Avr8::REGIDX_SPCR:
899		avr8_change_spcr(machine(), data);
900		break;
901
902		case Avr8::REGIDX_PORTD:
	309	case AVR8_REGIDX_PORTD:
903	310	avr8_change_port(machine(), AVR8_REG_D, data);
904	311	break;
905	312
906		case Avr8::REGIDX_DDRD:
	313	case AVR8_REGIDX_DDRD:
907	314	avr8_change_ddr(machine(), AVR8_REG_D, data);
908	315	break;
909	316
910		case Avr8::REGIDX_DDRC:
	317	case AVR8_REGIDX_PORTC:
	318	avr8_change_port(machine(), AVR8_REG_C, data);
	319	break;
	320
	321	case AVR8_REGIDX_DDRC:
911	322	avr8_change_ddr(machine(), AVR8_REG_C, data);
912	323	break;
913	324
914		case Avr8::REGIDX_PORTB:
	325	case AVR8_REGIDX_PORTB:
915	326	avr8_change_port(machine(), AVR8_REG_B, data);
916	327	break;
917	328
918		case Avr8::REGIDX_DDRB:
	329	case AVR8_REGIDX_DDRB:
919	330	avr8_change_ddr(machine(), AVR8_REG_B, data);
920	331	break;
921	332
r18696	r18697
967	378	{
968	379	craft_state *state = machine().driver_data<craft_state>();
969	380
970		AVR8_TIMSK1 = 0;
971		AVR8_OCR1AH = 0;
972		AVR8_OCR1AL = 0;
973		AVR8_OCR1BH = 0;
974		AVR8_OCR1BL = 0;
975		AVR8_ICR1H = 0;
976		AVR8_ICR1L = 0;
977		AVR8_TCNT1H = 0;
978		AVR8_TCNT1L = 0;
979
980	381	state->dac = machine().device<dac_device>("dac");
981	382
982	383	state->dac->write_unsigned8(0x00);
	384
	385	state->m_eeprom = memregion("eeprom")->base();
983	386	}
984	387
985	388	static MACHINE_CONFIG_START( craft, craft_state )

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