trunk/src/mame/drivers/namcos23.c
| r18689 | r18690 | |
| 1335 | 1335 | |
| 1336 | 1336 | required_device<cpu_device> m_maincpu; |
| 1337 | 1337 | required_device<cpu_device> m_audiocpu; |
| 1338 | | required_device<cpu_device> m_iocpu; |
| 1338 | optional_device<cpu_device> m_iocpu; |
| 1339 | 1339 | required_device<rtc4543_device> m_rtc; |
| 1340 | 1340 | required_shared_ptr<UINT32> m_shared_ram; |
| 1341 | 1341 | required_shared_ptr<UINT32> m_charram; |
| r18689 | r18690 | |
| 1357 | 1357 | bool m_ctl_vbl_active; |
| 1358 | 1358 | UINT8 m_ctl_led; |
| 1359 | 1359 | UINT16 m_ctl_inp_buffer[2]; |
| 1360 | | int m_audiocpu_running; |
| 1360 | bool m_audiocpu_running; |
| 1361 | 1361 | UINT32 m_p3d_address; |
| 1362 | 1362 | UINT32 m_p3d_size; |
| 1363 | 1363 | const UINT32 *m_ptrom; |
| r18689 | r18690 | |
| 1396 | 1396 | UINT8 m_im_rd; |
| 1397 | 1397 | UINT8 m_im_wr; |
| 1398 | 1398 | UINT8 m_s23_tssio_port_4; |
| 1399 | |
| 1399 | 1400 | DECLARE_WRITE32_MEMBER(namcos23_textram_w); |
| 1400 | 1401 | DECLARE_WRITE32_MEMBER(s23_txtchar_w); |
| 1401 | 1402 | DECLARE_WRITE32_MEMBER(namcos23_paletteram_w); |
| r18689 | r18690 | |
| 1415 | 1416 | DECLARE_READ16_MEMBER(s23_c361_r); |
| 1416 | 1417 | DECLARE_READ16_MEMBER(s23_c422_r); |
| 1417 | 1418 | DECLARE_WRITE16_MEMBER(s23_c422_w); |
| 1418 | | DECLARE_WRITE32_MEMBER(s23_mcuen_w); |
| 1419 | DECLARE_WRITE16_MEMBER(s23_mcuen_w); |
| 1419 | 1420 | DECLARE_READ32_MEMBER(s23_unk_status_r); |
| 1420 | 1421 | DECLARE_READ32_MEMBER(p3d_r); |
| 1421 | 1422 | DECLARE_WRITE32_MEMBER(p3d_w); |
| r18689 | r18690 | |
| 1760 | 1761 | return 0xffff; |
| 1761 | 1762 | } |
| 1762 | 1763 | |
| 1763 | | // raster timer. TC2 indicates it's probably one-shot since it resets it each VBL... |
| 1764 | 1764 | TIMER_CALLBACK_MEMBER(namcos23_state::c361_timer_cb) |
| 1765 | 1765 | { |
| 1766 | 1766 | c361_t &c361 = m_c361; |
| 1767 | 1767 | |
| 1768 | | if (c361.scanline != 511) |
| 1768 | if (c361.scanline != 0x1ff) |
| 1769 | 1769 | { |
| 1770 | 1770 | m_maincpu->set_input_line(MIPS3_IRQ1, ASSERT_LINE); |
| 1771 | | c361.timer->adjust(attotime::never); |
| 1771 | |
| 1772 | // TC2 indicates it's probably one-shot since it resets it each VBL... |
| 1773 | //c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline)); |
| 1772 | 1774 | } |
| 1773 | 1775 | } |
| 1774 | 1776 | |
| r18689 | r18690 | |
| 1776 | 1778 | { |
| 1777 | 1779 | c361_t &c361 = m_c361; |
| 1778 | 1780 | |
| 1779 | | switch(offset) { |
| 1781 | switch(offset) |
| 1782 | { |
| 1780 | 1783 | case 0: |
| 1781 | 1784 | m_bgtilemap->set_scrollx(0, data&0xfff); |
| 1782 | 1785 | break; |
| r18689 | r18690 | |
| 1786 | 1789 | break; |
| 1787 | 1790 | |
| 1788 | 1791 | case 4: // interrupt control |
| 1789 | | c361.scanline = data; |
| 1790 | | if (data == 0x1ff) |
| 1791 | | { |
| 1792 | | m_maincpu->set_input_line(MIPS3_IRQ1, CLEAR_LINE); |
| 1793 | | c361.timer->adjust(attotime::never); |
| 1794 | | } |
| 1795 | | else |
| 1796 | | { |
| 1797 | | c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline)); |
| 1798 | | } |
| 1792 | c361.scanline = data & 0x1ff; |
| 1793 | c361.timer->adjust(machine().primary_screen->time_until_pos(c361.scanline)); |
| 1799 | 1794 | break; |
| 1800 | 1795 | |
| 1801 | 1796 | default: |
| r18689 | r18690 | |
| 1805 | 1800 | |
| 1806 | 1801 | READ16_MEMBER(namcos23_state::s23_c361_r) |
| 1807 | 1802 | { |
| 1808 | | switch(offset) { |
| 1809 | | case 5: return machine().primary_screen->vpos()*2 | (machine().primary_screen->vblank() ? 1 : 0); |
| 1803 | switch(offset) |
| 1804 | { |
| 1805 | case 5: m_maincpu->set_input_line(MIPS3_IRQ1, CLEAR_LINE); return machine().primary_screen->vblank() ? 0x1ff : machine().primary_screen->vpos(); |
| 1810 | 1806 | case 6: return machine().primary_screen->vblank(); |
| 1811 | 1807 | } |
| 1812 | 1808 | logerror("c361_r %x @ %04x (%08x, %08x)\n", offset, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31)); |
| r18689 | r18690 | |
| 1846 | 1842 | COMBINE_DATA(&c422.regs[offset]); |
| 1847 | 1843 | } |
| 1848 | 1844 | |
| 1849 | | // as with System 22, we need to halt the MCU while checking shared RAM |
| 1850 | | WRITE32_MEMBER(namcos23_state::s23_mcuen_w) |
| 1845 | |
| 1846 | WRITE16_MEMBER(namcos23_state::s23_mcuen_w) |
| 1851 | 1847 | { |
| 1852 | | logerror("mcuen_w: mask %08x, data %08x\n", mem_mask, data); |
| 1853 | | if (mem_mask == 0x0000ffff) |
| 1848 | switch (offset) |
| 1854 | 1849 | { |
| 1855 | | if (data) |
| 1856 | | { |
| 1857 | | logerror("S23: booting H8/3002\n"); |
| 1850 | case 2: |
| 1851 | // subcpu irq ack |
| 1852 | m_maincpu->set_input_line(MIPS3_IRQ1, CLEAR_LINE); |
| 1853 | break; |
| 1858 | 1854 | |
| 1859 | | // Panic Park: writing 1 when it's already running means reboot? |
| 1860 | | if (m_audiocpu_running) |
| 1855 | case 5: |
| 1856 | // boot/start the audio mcu |
| 1857 | if (data) |
| 1861 | 1858 | { |
| 1859 | logerror("mcuen_w: booting H8/3002\n"); |
| 1860 | |
| 1861 | // Panic Park: writing 1 when it's already running means reboot? |
| 1862 | if (m_audiocpu_running) |
| 1863 | { |
| 1864 | m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); |
| 1865 | } |
| 1866 | |
| 1867 | m_audiocpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE); |
| 1868 | m_audiocpu_running = true; |
| 1869 | } |
| 1870 | else |
| 1871 | { |
| 1872 | logerror("mcuen_w: stopping H8/3002\n"); |
| 1862 | 1873 | m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); |
| 1874 | m_audiocpu_running = false; |
| 1863 | 1875 | } |
| 1876 | break; |
| 1864 | 1877 | |
| 1865 | | m_audiocpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE); |
| 1866 | | m_audiocpu_running = 1; |
| 1867 | | } |
| 1868 | | else |
| 1869 | | { |
| 1870 | | logerror("S23: stopping H8/3002\n"); |
| 1871 | | m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); |
| 1872 | | m_audiocpu_running = 0; |
| 1873 | | } |
| 1878 | default: |
| 1879 | logerror("mcuen_w: mask %04x, data %04x @ %x\n", mem_mask, data, offset); |
| 1880 | break; |
| 1874 | 1881 | } |
| 1875 | 1882 | } |
| 1876 | 1883 | |
| r18689 | r18690 | |
| 2194 | 2201 | if(data & 1) |
| 2195 | 2202 | p3d_dma(space, m_p3d_address, m_p3d_size); |
| 2196 | 2203 | return; |
| 2197 | | case 0x17: |
| 2198 | | m_maincpu->set_input_line(MIPS3_IRQ1, CLEAR_LINE); |
| 2199 | | m_c361.timer->adjust(attotime::never); |
| 2200 | | return; |
| 2201 | 2204 | } |
| 2202 | 2205 | logerror("p3d_w %02x, %08x @ %08x (%08x, %08x)\n", offset, data, mem_mask, space.device().safe_pc(), (unsigned int)space.device().state().state_int(MIPS3_R31)); |
| 2203 | 2206 | } |
| r18689 | r18690 | |
| 2436 | 2439 | static ADDRESS_MAP_START( gorgon_map, AS_PROGRAM, 32, namcos23_state ) |
| 2437 | 2440 | ADDRESS_MAP_GLOBAL_MASK(0xfffffff) |
| 2438 | 2441 | AM_RANGE(0x00000000, 0x003fffff) AM_RAM |
| 2439 | | AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w ) |
| 2440 | | AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16(s23_c417_r, s23_c417_w, 0xffffffff ) |
| 2442 | AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w) |
| 2443 | AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16(s23_c417_r, s23_c417_w, 0xffffffff) |
| 2441 | 2444 | AM_RANGE(0x04400000, 0x0440ffff) AM_RAM AM_SHARE("shared_ram") // Communication RAM (C416) |
| 2442 | 2445 | |
| 2443 | | AM_RANGE(0x04c3ff08, 0x04c3ff0b) AM_WRITE(s23_mcuen_w ) |
| 2444 | | AM_RANGE(0x04c3ff0c, 0x04c3ff0f) AM_RAM |
| 2446 | AM_RANGE(0x04c3ff00, 0x04c3ff0f) AM_WRITE16(s23_mcuen_w, 0xffffffff) |
| 2445 | 2447 | |
| 2446 | 2448 | AM_RANGE(0x06080000, 0x0608000f) AM_RAM AM_SHARE("czattr") |
| 2447 | 2449 | AM_RANGE(0x06080200, 0x060803ff) AM_RAM // PCZ Convert RAM (C406) (should be banked) |
| 2448 | 2450 | |
| 2449 | 2451 | AM_RANGE(0x06108000, 0x061087ff) AM_RAM // Gamma RAM (C404) |
| 2450 | | AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE(namcos23_paletteram_w ) AM_SHARE("paletteram") // Palette RAM (C404) |
| 2451 | | AM_RANGE(0x06400000, 0x0641dfff) AM_RAM_WRITE(s23_txtchar_w ) AM_SHARE("charram") // Text CGRAM (C361) |
| 2452 | | AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE(namcos23_textram_w ) AM_SHARE("textram") // Text VRAM (C361) |
| 2453 | | AM_RANGE(0x06420000, 0x0642000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff ) // C361 |
| 2452 | AM_RANGE(0x06110000, 0x0613ffff) AM_RAM_WRITE(namcos23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404) |
| 2453 | AM_RANGE(0x06400000, 0x0641dfff) AM_RAM_WRITE(s23_txtchar_w) AM_SHARE("charram") // Text CGRAM (C361) |
| 2454 | AM_RANGE(0x0641e000, 0x0641ffff) AM_RAM_WRITE(namcos23_textram_w) AM_SHARE("textram") // Text VRAM (C361) |
| 2455 | AM_RANGE(0x06420000, 0x0642000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff) // C361 |
| 2454 | 2456 | |
| 2455 | | AM_RANGE(0x08000000, 0x087fffff) AM_ROM AM_REGION("data", 0) // data ROMs |
| 2457 | AM_RANGE(0x08000000, 0x087fffff) AM_ROM AM_REGION("data", 0) // data ROMs |
| 2456 | 2458 | |
| 2457 | 2459 | AM_RANGE(0x0c000000, 0x0c00ffff) AM_RAM AM_SHARE("nvram") // Backup RAM |
| 2458 | 2460 | |
| 2459 | | AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff ) // write for LEDs at d000000, watchdog at d000004 |
| 2461 | AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff) // write for LEDs at d000000, watchdog at d000004 |
| 2460 | 2462 | |
| 2461 | 2463 | AM_RANGE(0x0e000000, 0x0e007fff) AM_RAM // C405 RAM - what is this? |
| 2462 | 2464 | |
| 2463 | | AM_RANGE(0x0f000000, 0x0f000003) AM_READ(s23_unk_status_r ) |
| 2465 | AM_RANGE(0x0f000000, 0x0f000003) AM_READ(s23_unk_status_r) |
| 2464 | 2466 | |
| 2465 | 2467 | AM_RANGE(0x0f200000, 0x0f203fff) AM_RAM // C422 RAM (where are the C422 regs?) |
| 2466 | 2468 | |
| r18689 | r18690 | |
| 2470 | 2472 | static ADDRESS_MAP_START( ss23_map, AS_PROGRAM, 32, namcos23_state ) |
| 2471 | 2473 | ADDRESS_MAP_GLOBAL_MASK(0xfffffff) |
| 2472 | 2474 | AM_RANGE(0x00000000, 0x00ffffff) AM_RAM |
| 2473 | | AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w ) |
| 2474 | | AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16(s23_c417_r, s23_c417_w, 0xffffffff ) |
| 2475 | AM_RANGE(0x01000000, 0x010000ff) AM_READWRITE(p3d_r, p3d_w) |
| 2476 | AM_RANGE(0x02000000, 0x0200000f) AM_READWRITE16(s23_c417_r, s23_c417_w, 0xffffffff) |
| 2475 | 2477 | AM_RANGE(0x04400000, 0x0440ffff) AM_RAM AM_SHARE("shared_ram") // Communication RAM (C416) |
| 2476 | | AM_RANGE(0x04c3ff08, 0x04c3ff0b) AM_WRITE(s23_mcuen_w ) |
| 2477 | | AM_RANGE(0x04c3ff0c, 0x04c3ff0f) AM_RAM |
| 2478 | AM_RANGE(0x04c3ff00, 0x04c3ff0f) AM_WRITE16(s23_mcuen_w, 0xffffffff) |
| 2478 | 2479 | AM_RANGE(0x06000000, 0x0600ffff) AM_RAM AM_SHARE("nvram") // Backup RAM |
| 2479 | 2480 | AM_RANGE(0x06200000, 0x06203fff) AM_RAM // C422 RAM |
| 2480 | | AM_RANGE(0x06400000, 0x0640000f) AM_READWRITE16(s23_c422_r, s23_c422_w, 0xffffffff ) // C422 registers |
| 2481 | | AM_RANGE(0x06800000, 0x0681dfff) AM_RAM_WRITE(s23_txtchar_w ) AM_SHARE("charram") // Text CGRAM (C361) |
| 2482 | | AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE(namcos23_textram_w ) AM_SHARE("textram") // Text VRAM (C361) |
| 2483 | | AM_RANGE(0x06820000, 0x0682000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff ) // C361 |
| 2481 | AM_RANGE(0x06400000, 0x0640000f) AM_READWRITE16(s23_c422_r, s23_c422_w, 0xffffffff) // C422 registers |
| 2482 | AM_RANGE(0x06800000, 0x0681dfff) AM_RAM_WRITE(s23_txtchar_w) AM_SHARE("charram") // Text CGRAM (C361) |
| 2483 | AM_RANGE(0x0681e000, 0x0681ffff) AM_RAM_WRITE(namcos23_textram_w) AM_SHARE("textram") // Text VRAM (C361) |
| 2484 | AM_RANGE(0x06820000, 0x0682000f) AM_READWRITE16(s23_c361_r, s23_c361_w, 0xffffffff) // C361 |
| 2484 | 2485 | AM_RANGE(0x06a08000, 0x06a087ff) AM_RAM // Blending control & GAMMA (C404) |
| 2485 | | AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE(namcos23_paletteram_w ) AM_SHARE("paletteram") // Palette RAM (C404) |
| 2486 | AM_RANGE(0x06a10000, 0x06a3ffff) AM_RAM_WRITE(namcos23_paletteram_w) AM_SHARE("paletteram") // Palette RAM (C404) |
| 2486 | 2487 | AM_RANGE(0x08000000, 0x08ffffff) AM_ROM AM_REGION("data", 0x0000000) AM_MIRROR(0x1000000) // data ROMs |
| 2487 | 2488 | AM_RANGE(0x0a000000, 0x0affffff) AM_ROM AM_REGION("data", 0x1000000) AM_MIRROR(0x1000000) |
| 2488 | | AM_RANGE(0x0c000000, 0x0c00001f) AM_READWRITE16(s23_c412_r, s23_c412_w, 0xffffffff ) |
| 2489 | | AM_RANGE(0x0c400000, 0x0c400007) AM_READWRITE16(s23_c421_r, s23_c421_w, 0xffffffff ) |
| 2490 | | AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff ) |
| 2491 | | AM_RANGE(0x0e800000, 0x0e800003) AM_READ(s23_unk_status_r ) |
| 2489 | AM_RANGE(0x0c000000, 0x0c00001f) AM_READWRITE16(s23_c412_r, s23_c412_w, 0xffffffff) |
| 2490 | AM_RANGE(0x0c400000, 0x0c400007) AM_READWRITE16(s23_c421_r, s23_c421_w, 0xffffffff) |
| 2491 | AM_RANGE(0x0d000000, 0x0d00000f) AM_READWRITE16(s23_ctl_r, s23_ctl_w, 0xffffffff) |
| 2492 | AM_RANGE(0x0e800000, 0x0e800003) AM_READ(s23_unk_status_r) |
| 2492 | 2493 | AM_RANGE(0x0fc00000, 0x0fffffff) AM_WRITENOP AM_ROM AM_REGION("user1", 0) |
| 2493 | 2494 | ADDRESS_MAP_END |
| 2494 | 2495 | |
| r18689 | r18690 | |
| 3107 | 3108 | memset(m_s23_settings, 0, sizeof(m_s23_settings)); |
| 3108 | 3109 | m_s23_tssio_port_4 = 0; |
| 3109 | 3110 | m_s23_porta = 0, m_s23_rtcstate = 0; |
| 3110 | | m_audiocpu_running = 0; |
| 3111 | m_audiocpu_running = false; |
| 3111 | 3112 | render.count[0] = render.count[1] = 0; |
| 3112 | 3113 | render.cur = 0; |
| 3113 | 3114 | |