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r18674 Tuesday 23rd October, 2012 at 11:46:32 UTC by Robbbert
Williams s3 : added diagnostic/setup controls and dipswitches

[src/mame/drivers]

s3.c

trunk/src/mame/drivers/s3.c

r18673	r18674
37	37	s3_state(const machine_config &mconfig, device_type type, const char *tag)
38	38	: genpin_class(mconfig, type, tag),
39	39	m_maincpu(*this, "maincpu"),
	40	m_audiocpu(*this, "audiocpu"),
40	41	m_dac(*this, "dac"),
41	42	m_pia0(*this, "pia0"),
42	43	m_pia1(*this, "pia1"),
r18673	r18674
53	54	DECLARE_WRITE8_MEMBER(lamp1_w);
54	55	DECLARE_WRITE8_MEMBER(sol0_w);
55	56	DECLARE_WRITE8_MEMBER(sol1_w);
	57	DECLARE_READ8_MEMBER(dips_r);
56	58	DECLARE_READ8_MEMBER(switch_r);
57	59	DECLARE_WRITE8_MEMBER(switch_w);
58		DECLARE_READ_LINE_MEMBER(cb1_r);
	60	DECLARE_READ_LINE_MEMBER(pia2_ca1_r);
	61	DECLARE_READ_LINE_MEMBER(pia2_cb1_r);
	62	DECLARE_READ_LINE_MEMBER(pia4_cb1_r);
	63	DECLARE_WRITE_LINE_MEMBER(pia0_ca2_w) { }; //ST5
	64	DECLARE_WRITE_LINE_MEMBER(pia0_cb2_w) { }; //ST-solenoids enable
	65	DECLARE_WRITE_LINE_MEMBER(pia1_ca2_w) { }; //ST2
	66	DECLARE_WRITE_LINE_MEMBER(pia1_cb2_w) { }; //ST1
	67	DECLARE_WRITE_LINE_MEMBER(pia2_ca2_w) { }; //diag leds enable
	68	DECLARE_WRITE_LINE_MEMBER(pia2_cb2_w) { }; //ST6
	69	DECLARE_WRITE_LINE_MEMBER(pia3_ca2_w) { }; //ST4
	70	DECLARE_WRITE_LINE_MEMBER(pia3_cb2_w) { }; //ST3
59	71	TIMER_DEVICE_CALLBACK_MEMBER(irq);
60		DECLARE_INPUT_CHANGED_MEMBER(nmi);
	72	DECLARE_INPUT_CHANGED_MEMBER(main_nmi);
	73	DECLARE_INPUT_CHANGED_MEMBER(audio_nmi);
61	74	DECLARE_MACHINE_RESET(s3);
62	75	DECLARE_MACHINE_RESET(s3a);
63	76	protected:
64	77
65	78	// devices
66	79	required_device<cpu_device> m_maincpu;
	80	optional_device<cpu_device> m_audiocpu;
67	81	optional_device<dac_device> m_dac;
68	82	required_device<pia6821_device> m_pia0;
69	83	required_device<pia6821_device> m_pia1;
r18673	r18674
83	97	static ADDRESS_MAP_START( s3_main_map, AS_PROGRAM, 8, s3_state )
84	98	ADDRESS_MAP_GLOBAL_MASK(0x7fff)
85	99	AM_RANGE(0x0000, 0x00ff) AM_RAM
86		AM_RANGE(0x0100, 0x017f) AM_RAM AM_SHARE("nvram")
	100	AM_RANGE(0x0100, 0x01ff) AM_RAM AM_SHARE("nvram")
87	101	AM_RANGE(0x2200, 0x2203) AM_DEVREADWRITE("pia0", pia6821_device, read, write) // solenoids
88	102	AM_RANGE(0x2400, 0x2403) AM_DEVREADWRITE("pia1", pia6821_device, read, write) // lamps
89	103	AM_RANGE(0x2800, 0x2803) AM_DEVREADWRITE("pia2", pia6821_device, read, write) // display
90	104	AM_RANGE(0x3000, 0x3003) AM_DEVREADWRITE("pia3", pia6821_device, read, write) // inputs
91		AM_RANGE(0x6000, 0x67ff) AM_ROM
92		AM_RANGE(0x7000, 0x7fff) AM_ROM
	105	AM_RANGE(0x6000, 0x7fff) AM_ROM
93	106	ADDRESS_MAP_END
94	107
95	108	static ADDRESS_MAP_START( s3_audio_map, AS_PROGRAM, 8, s3_state )
r18673	r18674
145	158	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_SLASH)
146	159	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_COLON)
147	160	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_QUOTE)
148		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Outhole") PORT_CODE(KEYCODE_X)
	161	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X)
149	162	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_MINUS)
150	163	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_EQUALS)
151	164	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_BACKSPACE)
r18673	r18674
171	184
172	185	PORT_START("SND")
173	186	PORT_BIT( 0xbf, IP_ACTIVE_LOW, IPT_UNUSED )
174		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Music") PORT_CODE(KEYCODE_9) PORT_TOGGLE
	187	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Music") PORT_CODE(KEYCODE_4) PORT_TOGGLE
175	188
176	189	PORT_START("DIAGS")
177		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_NAME("Diagnostic") PORT_CODE(KEYCODE_0) PORT_CHANGED_MEMBER(DEVICE_SELF, s3_state, nmi, 1)
	190	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER) PORT_NAME("Audio Diag") PORT_CODE(KEYCODE_F1) PORT_CHANGED_MEMBER(DEVICE_SELF, s3_state, audio_nmi, 1)
	191	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER) PORT_NAME("Main Diag") PORT_CODE(KEYCODE_F2) PORT_CHANGED_MEMBER(DEVICE_SELF, s3_state, main_nmi, 1)
	192	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER) PORT_NAME("Advance") PORT_CODE(KEYCODE_0)
	193	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER) PORT_NAME("Manual/Auto") PORT_CODE(KEYCODE_9)
	194	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Enter") PORT_CODE(KEYCODE_8)
	195
	196	PORT_START("DSW0")
	197	PORT_DIPNAME( 0x01, 0x01, "SW01" )
	198	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	199	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
	200	PORT_DIPNAME( 0x02, 0x02, "SW02" )
	201	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	202	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
	203	PORT_DIPNAME( 0x04, 0x04, "SW03" )
	204	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	205	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
	206	PORT_DIPNAME( 0x08, 0x08, "SW04" )
	207	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	208	PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
	209	PORT_DIPNAME( 0x10, 0x10, "SW05" )
	210	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	211	PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
	212	PORT_DIPNAME( 0x20, 0x20, "SW06" )
	213	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	214	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
	215	PORT_DIPNAME( 0x40, 0x40, "SW07" )
	216	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	217	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
	218	PORT_DIPNAME( 0x80, 0x80, "SW08" )
	219	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	220	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
	221
	222	PORT_START("DSW1")
	223	PORT_DIPNAME( 0x01, 0x01, "SW11" )
	224	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	225	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
	226	PORT_DIPNAME( 0x02, 0x02, "SW12" )
	227	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	228	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
	229	PORT_DIPNAME( 0x04, 0x04, "SW13" )
	230	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	231	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
	232	PORT_DIPNAME( 0x08, 0x08, "SW14" )
	233	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	234	PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
	235	PORT_DIPNAME( 0x10, 0x10, "SW15" )
	236	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	237	PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
	238	PORT_DIPNAME( 0x20, 0x20, "SW16" )
	239	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	240	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
	241	PORT_DIPNAME( 0x40, 0x40, "SW17" )
	242	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	243	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
	244	PORT_DIPNAME( 0x80, 0x80, "SW18" )
	245	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
	246	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
178	247	INPUT_PORTS_END
179	248
180	249	MACHINE_RESET_MEMBER( s3_state, s3 )
r18673	r18674
189	258	m_chimes = 0;
190	259	}
191	260
192		INPUT_CHANGED_MEMBER( s3_state::nmi )
	261	INPUT_CHANGED_MEMBER( s3_state::main_nmi )
193	262	{
194	263	// Diagnostic button sends a pulse to NMI pin
195	264	if (newval==CLEAR_LINE)
196	265	m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
197	266	}
198	267
	268	INPUT_CHANGED_MEMBER( s3_state::audio_nmi )
	269	{
	270	// Diagnostic button sends a pulse to NMI pin
	271	if ((newval==CLEAR_LINE) && !m_chimes)
	272	m_audiocpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
	273	}
	274
199	275	WRITE8_MEMBER( s3_state::sol0_w )
200	276	{
201	277	if (BIT(data, 4))
r18673	r18674
263	339	DEVCB_NULL,      /* line CB2 in */
264	340	DEVCB_DRIVER_MEMBER(s3_state, sol0_w),      /* port A out */
265	341	DEVCB_DRIVER_MEMBER(s3_state, sol1_w),      /* port B out */
266		DEVCB_NULL,      /* line CA2 out */
267		DEVCB_NULL,      /* port CB2 out */
	342	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia0_ca2_w),      /* line CA2 out */
	343	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia0_cb2_w),      /* line CB2 out */
268	344	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE),      /* IRQA */
269	345	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE)      /* IRQB */
270	346	};
r18673	r18674
288	364	DEVCB_NULL,      /* line CB2 in */
289	365	DEVCB_DRIVER_MEMBER(s3_state, lamp0_w),      /* port A out */
290	366	DEVCB_DRIVER_MEMBER(s3_state, lamp1_w),      /* port B out */
291		DEVCB_NULL,      /* line CA2 out */
292		DEVCB_NULL,      /* port CB2 out */
	367	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia1_ca2_w),      /* line CA2 out */
	368	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia1_cb2_w),      /* line CB2 out */
293	369	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE),      /* IRQA */
294	370	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE)      /* IRQB */
295	371	};
296	372
	373	READ_LINE_MEMBER( s3_state::pia2_ca1_r )
	374	{
	375	return BIT(ioport("DIAGS")->read(), 2); // advance button
	376	}
	377
	378	READ_LINE_MEMBER( s3_state::pia2_cb1_r )
	379	{
	380	return BIT(ioport("DIAGS")->read(), 3); // auto/manual switch
	381	}
	382
	383	READ8_MEMBER( s3_state::dips_r )
	384	{
	385	if (BIT(ioport("DIAGS")->read(), 4) )
	386	{
	387	switch (m_strobe)
	388	{
	389	case 0:
	390	return ioport("DSW0")->read() & 15;
	391	break;
	392	case 1:
	393	return ioport("DSW0")->read() << 4;
	394	break;
	395	case 2:
	396	return ioport("DSW1")->read() & 15;
	397	break;
	398	case 3:
	399	return ioport("DSW1")->read() << 4;
	400	break;
	401	}
	402	}
	403	return 0xff;
	404	}
	405
297	406	WRITE8_MEMBER( s3_state::dig0_w )
298	407	{
299		m_strobe = data;
	408	m_strobe = data & 15;
300	409	m_data_ok = true;
	410	output_set_value("led0", BIT(data, 4));
	411	output_set_value("led1", BIT(data, 5));
301	412	}
302	413
303	414	WRITE8_MEMBER( s3_state::dig1_w )
r18673	r18674
313	424
314	425	static const pia6821_interface pia2_intf =
315	426	{
316		DEVCB_NULL,      /* port A in */
	427	DEVCB_DRIVER_MEMBER(s3_state, dips_r),      /* port A in */
317	428	DEVCB_NULL,      /* port B in */
318		DEVCB_NULL,      /* line CA1 in */
319		DEVCB_NULL,      /* line CB1 in */
	429	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia2_ca1_r),      /* line CA1 in */
	430	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia2_cb1_r),      /* line CB1 in */
320	431	DEVCB_NULL,      /* line CA2 in */
321	432	DEVCB_NULL,      /* line CB2 in */
322	433	DEVCB_DRIVER_MEMBER(s3_state, dig0_w),      /* port A out */
323	434	DEVCB_DRIVER_MEMBER(s3_state, dig1_w),      /* port B out */
324		DEVCB_NULL,      /* line CA2 out */
325		DEVCB_NULL,      /* port CB2 out */
	435	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia2_ca2_w),      /* line CA2 out */
	436	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia2_cb2_w),      /* line CB2 out */
326	437	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE),      /* IRQA */
327	438	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE)      /* IRQB */
328	439	};
r18673	r18674
349	460	DEVCB_NULL,      /* line CB2 in */
350	461	DEVCB_NULL,      /* port A out */
351	462	DEVCB_DRIVER_MEMBER(s3_state, switch_w),      /* port B out */
352		DEVCB_NULL,      /* line CA2 out */
353		DEVCB_NULL,      /* port CB2 out */
	463	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia3_ca2_w),      /* line CA2 out */
	464	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia3_cb2_w),      /* line CB2 out */
354	465	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE),      /* IRQA */
355	466	DEVCB_CPU_INPUT_LINE("maincpu", M6800_IRQ_LINE)      /* IRQB */
356	467	};
357	468
358		READ_LINE_MEMBER( s3_state::cb1_r )
	469	READ_LINE_MEMBER( s3_state::pia4_cb1_r )
359	470	{
360	471	return m_cb1;
361	472	}
r18673	r18674
375	486	DEVCB_NULL,      /* port A in */
376	487	DEVCB_DRIVER_MEMBER(s3_state, dac_r),      /* port B in */
377	488	DEVCB_NULL,      /* line CA1 in */
378		DEVCB_DRIVER_LINE_MEMBER(s3_state, cb1_r),      /* line CB1 in */
	489	DEVCB_DRIVER_LINE_MEMBER(s3_state, pia4_cb1_r),      /* line CB1 in */
379	490	DEVCB_NULL,      /* line CA2 in */
380	491	DEVCB_NULL,      /* line CB2 in */
381	492	DEVCB_DRIVER_MEMBER(s3_state, dac_w),      /* port A out */
382	493	DEVCB_NULL,      /* port B out */
383	494	DEVCB_NULL,      /* line CA2 out */
384		DEVCB_NULL,      /* port CB2 out */
	495	DEVCB_NULL,      /* line CB2 out */
385	496	DEVCB_CPU_INPUT_LINE("audiocpu", M6800_IRQ_LINE),      /* IRQA */
386	497	DEVCB_CPU_INPUT_LINE("audiocpu", M6800_IRQ_LINE)      /* IRQB */
387	498	};

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