trunk/src/emu/video/pc_vga.c
| r18666 | r18667 | |
|---|
| 2687 | 2687 | |
| 2688 | 2688 | void s3_vga_device::s3_define_video_mode() |
| 2689 | 2689 | { |
| 2690 | int divisor = 1; |
| 2691 | int xtal = 1000000; |
| 2690 | 2692 | if((s3.ext_misc_ctrl_2) >> 4) |
| 2691 | 2693 | { |
| 2692 | 2694 | svga.rgb8_en = 0; |
| r18666 | r18667 | |
|---|
| 2695 | 2697 | svga.rgb32_en = 0; |
| 2696 | 2698 | switch((s3.ext_misc_ctrl_2) >> 4) |
| 2697 | 2699 | { |
| 2698 | | case 0x03: svga.rgb15_en = 1; break; |
| 2699 | | case 0x05: svga.rgb16_en = 1; break; |
| 2700 | | case 0x0d: svga.rgb32_en = 1; break; |
| 2700 | case 0x03: svga.rgb15_en = 1; divisor = 2; break; |
| 2701 | case 0x05: svga.rgb16_en = 1; divisor = 2; break; |
| 2702 | case 0x0d: svga.rgb32_en = 1; divisor = 2; break; |
| 2701 | 2703 | default: fatalerror("TODO: s3 video mode not implemented %02x\n",((s3.ext_misc_ctrl_2) >> 4)); break; |
| 2702 | 2704 | } |
| 2705 | switch(s3.cr42 & 0x0f) // TODO: confirm clock settings |
| 2706 | { |
| 2707 | case 0: |
| 2708 | xtal = XTAL_25_1748MHz; |
| 2709 | break; |
| 2710 | case 1: |
| 2711 | xtal = XTAL_28_63636MHz; |
| 2712 | break; |
| 2713 | case 2: |
| 2714 | xtal = 40000000; |
| 2715 | break; |
| 2716 | case 3: |
| 2717 | xtal = 3000000; |
| 2718 | break; |
| 2719 | case 4: |
| 2720 | xtal = 50000000; |
| 2721 | break; |
| 2722 | case 5: |
| 2723 | xtal = 77000000; |
| 2724 | break; |
| 2725 | case 6: |
| 2726 | xtal = 36000000; |
| 2727 | break; |
| 2728 | case 7: |
| 2729 | xtal = 45000000; |
| 2730 | break; |
| 2731 | case 8: |
| 2732 | xtal = 1000000; |
| 2733 | break; |
| 2734 | case 9: |
| 2735 | xtal = 1000000; |
| 2736 | break; |
| 2737 | case 10: |
| 2738 | xtal = 79000000; |
| 2739 | break; |
| 2740 | case 11: |
| 2741 | xtal = 31000000; |
| 2742 | break; |
| 2743 | case 12: |
| 2744 | xtal = 94000000; |
| 2745 | break; |
| 2746 | case 13: |
| 2747 | xtal = 65000000; |
| 2748 | break; |
| 2749 | case 14: |
| 2750 | xtal = 75000000; |
| 2751 | break; |
| 2752 | case 15: |
| 2753 | xtal = 71000000; |
| 2754 | break; |
| 2755 | default: |
| 2756 | xtal = 1000000; |
| 2757 | } |
| 2703 | 2758 | } |
| 2704 | 2759 | else |
| 2705 | 2760 | { |
| r18666 | r18667 | |
|---|
| 2708 | 2763 | svga.rgb16_en = 0; |
| 2709 | 2764 | svga.rgb32_en = 0; |
| 2710 | 2765 | } |
| 2766 | recompute_params_clock(divisor, xtal); |
| 2711 | 2767 | } |
| 2712 | 2768 | |
| 2713 | 2769 | void s3_vga_device::s3_crtc_reg_write(UINT8 index, UINT8 data) |
| r18666 | r18667 | |
|---|
| 2742 | 2798 | case 0x40: |
| 2743 | 2799 | s3.enable_8514 = data & 0x01; // enable 8514/A registers (x2e8, x6e8, xae8, xee8) |
| 2744 | 2800 | break; |
| 2801 | case 0x42: |
| 2802 | s3.cr42 = data; // bit 5 = interlace, bits 0-3 = dot clock (seems to be undocumented) |
| 2803 | break; |
| 2745 | 2804 | /* |
| 2746 | 2805 | 3d4h index 45h (R/W): CR45 Hardware Graphics Cursor Mode |
| 2747 | 2806 | bit 0 HWGC ENB. Hardware Graphics Cursor Enable. Set to enable the |