trunk/src/emu/cpu/i386/i386ops.h
| r18650 | r18651 | |
|---|
| 301 | 301 | { 0x20, OP_2BYTE|OP_I386, I386OP(mov_r32_cr), I386OP(mov_r32_cr), }, |
| 302 | 302 | { 0x21, OP_2BYTE|OP_I386, I386OP(mov_r32_dr), I386OP(mov_r32_dr), }, |
| 303 | 303 | { 0x22, OP_2BYTE|OP_I386, I386OP(mov_cr_r32), I386OP(mov_cr_r32), }, |
| 304 | | { 0x22, OP_2BYTE|OP_I486, I486OP(mov_cr_r32), I386OP(mov_cr_r32), }, |
| 304 | { 0x22, OP_2BYTE|OP_I486, I486OP(mov_cr_r32), I486OP(mov_cr_r32), }, |
| 305 | 305 | { 0x23, OP_2BYTE|OP_I386, I386OP(mov_dr_r32), I386OP(mov_dr_r32), }, |
| 306 | 306 | { 0x24, OP_2BYTE|OP_I386, I386OP(mov_r32_tr), I386OP(mov_r32_tr), }, |
| 307 | 307 | { 0x26, OP_2BYTE|OP_I386, I386OP(mov_tr_r32), I386OP(mov_tr_r32), }, |
trunk/src/mess/machine/3c503.c
| r18650 | r18651 | |
|---|
| 121 | 121 | case 2: |
| 122 | 122 | return m_prom[offset + 16]; |
| 123 | 123 | case 3: |
| 124 | | logerror("3c503: invalid low register read, page 3"); |
| 124 | logerror("3c503: invalid low register read, page 3\n"); |
| 125 | 125 | } |
| 126 | 126 | return 0; |
| 127 | 127 | } |
| r18650 | r18651 | |
|---|
| 133 | 133 | return m_dp8390->dp8390_w(space, offset, data, mem_mask); |
| 134 | 134 | case 1: |
| 135 | 135 | case 2: |
| 136 | | logerror("3c503: invalid attempt to write to prom"); |
| 136 | logerror("3c503: invalid attempt to write to prom\n"); |
| 137 | 137 | return; |
| 138 | 138 | case 3: |
| 139 | | logerror("3c503: invalid low register write, page 3"); |
| 139 | logerror("3c503: invalid low register write, page 3\n"); |
| 140 | 140 | return; |
| 141 | 141 | } |
| 142 | 142 | } |
| r18650 | r18651 | |
|---|
| 237 | 237 | m_regs.idcfr = (m_regs.idcfr & 0xf) | (data & 0xf0); |
| 238 | 238 | break; |
| 239 | 239 | default: |
| 240 | | logerror("3c503: trying to set multiple irqs %X", data); |
| 240 | logerror("3c503: trying to set multiple irqs %X\n", data); |
| 241 | 241 | } |
| 242 | 242 | switch(data & 0x0f) { |
| 243 | 243 | case 0x00: |
| r18650 | r18651 | |
|---|
| 249 | 249 | case 0x08: |
| 250 | 250 | break; |
| 251 | 251 | default: |
| 252 | | logerror("3c503: trying to set multiple drqs %X", data); |
| 252 | logerror("3c503: trying to set multiple drqs %X\n", data); |
| 253 | 253 | } |
| 254 | 254 | case 9: |
| 255 | | if(m_regs.ctrl & 0x80) logerror("3c503: changing dma address during dma is undefined"); |
| 255 | if(m_regs.ctrl & 0x80) logerror("3c503: changing dma address during dma is undefined\n"); |
| 256 | 256 | m_regs.da = (data << 8) | (m_regs.da & 0xff); |
| 257 | 257 | return; |
| 258 | 258 | case 10: |
| 259 | | if(m_regs.ctrl & 0x80) logerror("3c503: changing dma address during dma is undefined"); |
| 259 | if(m_regs.ctrl & 0x80) logerror("3c503: changing dma address during dma is undefined\n"); |
| 260 | 260 | m_regs.da = (m_regs.da & 0xff00) | data; |
| 261 | 261 | return; |
| 262 | 262 | case 11: |
| r18650 | r18651 | |
|---|
| 279 | 279 | el2_3c503_mem_write(space, m_regs.da++, data, mem_mask); |
| 280 | 280 | return; |
| 281 | 281 | default: |
| 282 | | logerror("3c503: invalid high register write %02x", offset); |
| 282 | logerror("3c503: invalid high register write %02x\n", offset); |
| 283 | 283 | } |
| 284 | 284 | } |
| 285 | 285 | |