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r18598 Friday 19th October, 2012 at 03:38:51 UTC by Ryan Holtz
- Added opcodes to Atmel AVR core: OR, SBCI, ORI, ST Y+, ADIW [Mooglyguy] - Fixed functional issues in Atmel AVR opcodes: COM, NEG, LSR [Mooglyguy] - Added basic Timer 1 support to Craft driver and hooked up the DAC, currently plays only a buzzing noise due to lacking EEPROM support [MooglyGuy]

[src/emu/cpu/avr8]	avr8.c
[src/mess/drivers]	craft.c
[src/mess/machine]	avr8.h

trunk/src/emu/cpu/avr8/avr8.c

r18597	r18598
62	62	#define RR3(op)         ((op) & 0x0007)
63	63	#define RR4(op)         ((op) & 0x000f)
64	64	#define RR5(op)         ((((op) >> 5) & 0x0010) | ((op) & 0x000f))
	65	#define DCONST(op)      (((op) >> 4) & 0x0003)
65	66	#define KCONST6(op)     ((((op) >> 2) & 0x0030) | ((op) & 0x000f))
66	67	#define KCONST7(op)     (((op) >> 3) & 0x007f)
67	68	#define KCONST8(op)     ((((op) >> 4) & 0x00f0) | ((op) & 0x000f))
r18597	r18598
165	166
166	167	static void avr8_set_irq_line(avr8_state *cpustate, UINT16 vector, int state)
167	168	{
168		//printf( "OMFG SETTING IRQ LINE\n" );
169	169	// Horrible hack, not accurate
170	170	if(state)
171	171	{
r18597	r18598
367	367	WRITE_IO_8(cpustate, RD5(op), rd);
368	368	break;
369	369	case 0x0800:    // OR Rd,Rr
370		//output += sprintf( output, "OR      R%d, R%d", RD5(op), RR5(op) );
371		unimplemented_opcode(cpustate, op);
	370	rd = READ_IO_8(cpustate, RD5(op));
	371	rr = READ_IO_8(cpustate, RR5(op));
	372	rd |= rr;
	373	SREG_W(AVR8_SREG_V, 0);
	374	SREG_W(AVR8_SREG_N, rd & 0x80);
	375	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	376	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
	377	WRITE_IO_8(cpustate, RD5(op), rd);
372	378	break;
373	379	case 0x0c00:    // MOV Rd,Rr
374	380	WRITE_IO_8(cpustate, RD5(op), READ_IO_8(cpustate, RR5(op)));
r18597	r18598
387	393	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
388	394	break;
389	395	case 0x4000:    // SBCI Rd,K
390		//output += sprintf( output, "SBCI    R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
391		unimplemented_opcode(cpustate, op);
	396	rd = READ_IO_8(cpustate, 16+RD4(op));
	397	rr = KCONST8(op);
	398	res = rd - (rr + SREG_R(AVR8_SREG_C));
	399	WRITE_IO_8(cpustate, 16+RD4(op), res);
	400	SREG_W(AVR8_SREG_H, (NOT(BIT(rd,3)) & BIT(rr,3)) | (BIT(rr,3) & BIT(res,3)) | (BIT(res,3) & NOT(BIT(rd,3))));
	401	SREG_W(AVR8_SREG_V, (BIT(rd,7) & NOT(BIT(rr,7)) & NOT(BIT(res,7))) | (NOT(BIT(rd,7)) & BIT(rr,7) & BIT(res,7)));
	402	SREG_W(AVR8_SREG_N, BIT(res,7));
	403	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	404	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
	405	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
392	406	break;
393	407	case 0x5000:    // SUBI Rd,K
394	408	rd = READ_IO_8(cpustate, 16+RD4(op));
r18597	r18598
403	417	SREG_W(AVR8_SREG_C, (NOT(BIT(rd,7)) & BIT(rr,7)) | (BIT(rr,7) & BIT(res,7)) | (BIT(res,7) & NOT(BIT(rd,7))));
404	418	break;
405	419	case 0x6000:    // ORI Rd,K
406		//output += sprintf( output, "ORI     R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
407		unimplemented_opcode(cpustate, op);
	420	rd = READ_IO_8(cpustate, 16+RD4(op));
	421	rr = KCONST8(op);
	422	rd |= rr;
	423	SREG_W(AVR8_SREG_V, 0);
	424	SREG_W(AVR8_SREG_N, rd & 0x80);
	425	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	426	SREG_W(AVR8_SREG_Z, (rd == 0) ? 1 : 0);
	427	WRITE_IO_8(cpustate, 16+RD4(op), rd);
408	428	break;
409	429	case 0x7000:    // ANDI Rd,K
410	430	//output += sprintf( output, "ANDI    R%d, 0x%02x", 16+RD4(op), KCONST8(op) );
r18597	r18598
527	547	unimplemented_opcode(cpustate, op);
528	548	break;
529	549	case 0x0009:    // ST Y+,Rd
530		//output += sprintf( output, "ST       Y+, R%d", RD5(op) );
531		unimplemented_opcode(cpustate, op);
	550	pd = YREG;
	551	WRITE_IO_8(cpustate, pd, READ_IO_8(cpustate, RD5(op)));
	552	pd++;
	553	WRITE_IO_8(cpustate, 29, (pd >> 8) & 0x00ff);
	554	WRITE_IO_8(cpustate, 28, pd & 0x00ff);
	555	opcycles = 2;
532	556	break;
533	557	case 0x000a:    // ST -Z,Rd
534	558	//output += sprintf( output, "ST      -Y , R%d", RD5(op) );
r18597	r18598
566	590	{
567	591	case 0x0000:    // COM Rd
568	592	rd = READ_IO_8(cpustate, RD5(op));
569		rd = ~rd;
	593	res = ~rd;
570	594	SREG_W(AVR8_SREG_C, 1);
571	595	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
572	596	SREG_W(AVR8_SREG_N, BIT(res,7));
573	597	SREG_W(AVR8_SREG_V, 0);
574		SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) | SREG_R(AVR8_SREG_V));
	598	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	599	WRITE_IO_8(cpustate, RD5(op), res);
575	600	break;
576	601	case 0x0001:    // NEG Rd
577	602	rd = READ_IO_8(cpustate, RD5(op));
r18597	r18598
580	605	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
581	606	SREG_W(AVR8_SREG_N, BIT(res,7));
582	607	SREG_W(AVR8_SREG_V, (res == 0x80) ? 1 : 0);
583		SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) | SREG_R(AVR8_SREG_V));
	608	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
584	609	SREG_W(AVR8_SREG_H, BIT(res,3) | BIT(rd,3));
	610	WRITE_IO_8(cpustate, RD5(op), res);
585	611	break;
586	612	case 0x0002:    // SWAP Rd
587	613	//output += sprintf( output, "SWAP    R%d", RD5(op) );
r18597	r18598
608	634	SREG_W(AVR8_SREG_N, 0);
609	635	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
610	636	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	637	WRITE_IO_8(cpustate, RD5(op), res);
611	638	break;
612	639	case 0x0007:    // ROR Rd
613	640	//output += sprintf( output, "ROR     R%d", RD5(op) );
r18597	r18598
694	721	{
695	722	case 0x0000:    // COM Rd
696	723	rd = READ_IO_8(cpustate, RD5(op));
697		rd = ~rd;
	724	res = ~rd;
698	725	SREG_W(AVR8_SREG_C, 1);
699	726	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
700	727	SREG_W(AVR8_SREG_N, BIT(res,7));
701	728	SREG_W(AVR8_SREG_V, 0);
702		SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) | SREG_R(AVR8_SREG_V));
	729	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	730	WRITE_IO_8(cpustate, RD5(op), res);
703	731	break;
704	732	case 0x0001:    // NEG Rd
705	733	rd = READ_IO_8(cpustate, RD5(op));
706	734	res = 0 - rd;
707		WRITE_IO_8(cpustate, RD5(op), res);
708	735	SREG_W(AVR8_SREG_C, (res == 0) ? 0 : 1);
709	736	SREG_W(AVR8_SREG_Z, (res == 0) ? 1 : 0);
710	737	SREG_W(AVR8_SREG_N, BIT(res,7));
711	738	SREG_W(AVR8_SREG_V, (res == 0x80) ? 1 : 0);
712		SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) | SREG_R(AVR8_SREG_V));
	739	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
713	740	SREG_W(AVR8_SREG_H, BIT(res,3) | BIT(rd,3));
	741	WRITE_IO_8(cpustate, RD5(op), res);
714	742	break;
715	743	case 0x0002:    // SWAP Rd
716	744	//output += sprintf( output, "SWAP    R%d", RD5(op) );
r18597	r18598
737	765	SREG_W(AVR8_SREG_N, 0);
738	766	SREG_W(AVR8_SREG_V, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_C));
739	767	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	768	WRITE_IO_8(cpustate, RD5(op), res);
740	769	break;
741	770	case 0x0007:    // ROR Rd
742	771	//output += sprintf( output, "ROR     R%d", RD5(op) );
r18597	r18598
839	868	}
840	869	break;
841	870	case 0x0600:    // ADIW Rd+1:Rd,K
842		//output += sprintf( output, "ADIW    R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op) );
843		unimplemented_opcode(cpustate, op);
	871	rd = READ_IO_8(cpustate, 24 + (DCONST(op) << 1));
	872	rr = READ_IO_8(cpustate, 25 + (DCONST(op) << 1));
	873	pd = rd;
	874	pd |= rr << 8;
	875	pd += KCONST6(op);
	876	SREG_W(AVR8_SREG_V, BIT(pd,15) & NOT(BIT(rr,7)));
	877	SREG_W(AVR8_SREG_N, BIT(pd,15));
	878	SREG_W(AVR8_SREG_S, SREG_R(AVR8_SREG_N) ^ SREG_R(AVR8_SREG_V));
	879	SREG_W(AVR8_SREG_Z, (pd == 0) ? 1 : 0);
	880	SREG_W(AVR8_SREG_C, NOT(BIT(pd,15)) & BIT(rr,7));
	881	WRITE_IO_8(cpustate, 24 + (DCONST(op) << 1), pd & 0xff);
	882	WRITE_IO_8(cpustate, 25 + (DCONST(op) << 1), (pd >> 8) & 0xff);
	883	opcycles = 2;
844	884	break;
845	885	case 0x0700:    // SBIW Rd+1:Rd,K
846	886	//output += sprintf( output, "SBIW    R%d:R%d, 0x%02x", 24+(RD2(op) << 1)+1, 24+(RD2(op) << 1), KCONST6(op) );
r18597	r18598
999	1039
1000	1040	switch (state)
1001	1041	{
1002
1003	1042	/* interrupt lines/exceptions */
1004	1043	case CPUINFO_INT_INPUT_STATE + AVR8_INT_RESET:          avr8_set_irq_line(cpustate, AVR8_INT_RESET, info->i);       break;
1005	1044	case CPUINFO_INT_INPUT_STATE + AVR8_INT_INT0:           avr8_set_irq_line(cpustate, AVR8_INT_INT0, info->i);        break;

trunk/src/mess/machine/avr8.h

r18597	r18598
192	192	#define AVR8_TCNT1H            (state->m_regs[Avr8::REGIDX_TCNT1H])
193	193	#define AVR8_TCNT1L            (state->m_regs[Avr8::REGIDX_TCNT1L])
194	194
	195	#define AVR8_SREG_I                 0x80
	196
195	197	#define AVR8_TCCR1B               (state->m_regs[Avr8::REGIDX_TCCR1B])
196	198	#define AVR8_TCCR1B_ICNC1_MASK      0x80
197	199	#define AVR8_TCCR1B_ICNC1_SHIFT      7
r18597	r18598
210	212	#define AVR8_TCCR1A_WGM1_10_MASK   0x03
211	213	#define AVR8_TCCR1A_WGM1_10_SHIFT   0
212	214	#define AVR8_TCCR1A_COM1A         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT)
213		#define AVR8_TCCR1A_COM1B         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT)
	215	#define AVR8_TCCR1A_COM1B         ((AVR8_TCCR1A & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT)
214	216	#define AVR8_TCCR1A_WGM1_10         (AVR8_TCCR1A & AVR8_TCCR1A_WGM1_10_MASK)
215	217
216	218	#define AVR8_TIMSK1            (state->m_regs[Avr8::REGIDX_TIMSK1])
r18597	r18598
242	244	#define AVR8_TCCR2A_WGM2_10_MASK   0x03
243	245	#define AVR8_TCCR2A_WGM2_10_SHIFT   0
244	246	#define AVR8_TCCR2A_COM2A         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2A_MASK) >> AVR8_TCCR2A_COM2A_SHIFT)
245		#define AVR8_TCCR2A_COM2B         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2A_MASK) >> AVR8_TCCR2A_COM2A_SHIFT)
	247	#define AVR8_TCCR2A_COM2B         ((AVR8_TCCR2A & AVR8_TCCR2A_COM2B_MASK) >> AVR8_TCCR2A_COM2B_SHIFT)
246	248	#define AVR8_TCCR2A_WGM2_10         (AVR8_TCCR2A & AVR8_TCCR1A_WGM2_10_MASK)
247	249
248	250	#define AVR8_SPSR            (state->m_regs[Avr8::REGIDX_SPSR])

trunk/src/mess/drivers/craft.c

r18597	r18598
1	1	/*\
2	2	* * Linus Akesson's "Craft"
3	3	* *
4		* * Skeleton driver by MooglyGuy
5		* * Partial rewrite by Harmony
	4	* * Driver by MooglyGuy
6	5	\*/
7	6
8	7	#include "emu.h"
r18597	r18598
10	9	#include "machine/avr8.h"
11	10	#include "sound/dac.h"
12	11
13		#define VERBOSE_LEVEL   (0)
	12	#define VERBOSE_LEVEL   (99)
14	13
15		#define ENABLE_VERBOSE_LOG (1)
	14	#define ENABLE_VERBOSE_LOG (0)
16	15
17	16	#if ENABLE_VERBOSE_LOG
18	17	INLINE void verboselog(running_machine &machine, int n_level, const char *s_fmt, ...)
r18597	r18598
45	44	{
46	45	public:
47	46	craft_state(const machine_config &mconfig, device_type type, const char *tag)
48		: driver_device(mconfig, type, tag)
	47	: driver_device(mconfig, type, tag),
	48	m_maincpu(*this, "maincpu")
49	49	{
50	50	m_timer0_increment = 1;
51	51
r18597	r18598
56	56
57	57	virtual void machine_start();
58	58
	59	dac_device* dac;
	60
59	61	UINT8 m_regs[0x100];
60	62
	63	required_device<cpu_device> m_maincpu;
	64
61	65	emu_timer* m_timer0_timer;
62		UINT8 m_timer0_top;
	66	UINT8 m_timer0_top;
63	67	INT32 m_timer0_increment;
64	68
65	69	emu_timer* m_timer1_timer;
66		UINT16 m_timer1_top;
	70	UINT16 m_timer1_top;
67	71	INT32 m_timer1_increment;
68	72
69	73	emu_timer* m_timer2_timer;
70		UINT8 m_timer2_top;
	74	UINT8 m_timer2_top;
71	75	INT32 m_timer2_increment;
72	76	DECLARE_READ8_MEMBER(avr8_read);
73	77	DECLARE_WRITE8_MEMBER(avr8_write);
r18597	r18598
102	106
103	107	TIMER_CALLBACK_MEMBER(craft_state::avr8_timer1_tick)
104	108	{
105		/* TODO: Handle comparison, setting OC1x pins, detection of BOTTOM and TOP
	109	/* TODO: Handle comparison, setting OC1x pins, detection of BOTTOM and TOP */
106	110
107		UINT16 count = AVR8_TCNT1;
108		count += m_timer1_increment;
	111	UINT16 count = (m_regs[Avr8::REGIDX_TCNT1H] << 8) | m_regs[Avr8::REGIDX_TCNT1L];
	112	INT32 wgm1 = ((m_regs[Avr8::REGIDX_TCCR1B] & AVR8_TCCR1B_WGM1_32_MASK) >> 1) |
	113	(m_regs[Avr8::REGIDX_TCCR1A] & AVR8_TCCR1A_WGM1_10_MASK);
109	114
	115	// Cache things in array form to avoid a compare+branch inside a potentially high-frequency timer
	116	//UINT8 compare_mode[2] = { (m_regs[Avr8::REGIDX_TCCR1A] & AVR8_TCCR1A_COM1A_MASK) >> AVR8_TCCR1A_COM1A_SHIFT,
	117	//(m_regs[Avr8::REGIDX_TCCR1A] & AVR8_TCCR1A_COM1B_MASK) >> AVR8_TCCR1A_COM1B_SHIFT };
	118	UINT16 ocr1[2] = { (m_regs[Avr8::REGIDX_OCR1AH] << 8) | m_regs[Avr8::REGIDX_OCR1AL],
	119	(m_regs[Avr8::REGIDX_OCR1BH] << 8) | m_regs[Avr8::REGIDX_OCR1BL] };
	120	INT32 int_lines[2] = { AVR8_INT_T1COMPA, AVR8_INT_T1COMPB };
	121	INT32 int_masks[2] = { AVR8_TIMSK1_OCIE1A_MASK, AVR8_TIMSK1_OCIE1B_MASK };
	122	INT32 increment = m_timer1_increment;
	123
110	124	for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++)
111	125	{
112		UINT8 mode = (reg == AVR8_REG_A) ? AVR8_TCCR1A_COM1A : AVR8_TCCR1A_COM1B;
113		switch(mode)
	126	switch(wgm1)
114	127	{
	128	case Avr8::WGM1_FAST_PWM_OCR:
	129	if(count == ocr1[reg])
	130	{
	131	if (reg == 0)
	132	{
	133	m_regs[Avr8::REGIDX_TIFR1] |= (1 << AVR8_TIFR1_TOV1_SHIFT);
	134	count = 0;
	135	increment = 0;
	136	}
	137	if (m_regs[Avr8::REGIDX_TIMSK1] & int_masks[reg])
	138	{
	139	m_maincpu->set_input_line(int_lines[reg], 1);
	140	}
	141	}
	142	else if(count == 0)
	143	{
	144	if (reg == 0)
	145	{
	146	m_regs[Avr8::REGIDX_TIFR1] &= ~AVR8_TIFR1_TOV1_MASK;
	147	}
	148	if (m_regs[Avr8::REGIDX_TIMSK1] & int_masks[reg])
	149	{
	150	m_maincpu->set_input_line(int_lines[reg], 0);
	151	}
	152	}
	153	break;
	154
	155	default:
	156	// TODO
	157	break;
	158	}
	159	/*
	160	switch(compare_mode[reg])
	161	{
115	162	case 0:
116	163	//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Normal port operation (OC1 disconnected)\n");
117	164	break;
118	165
119	166	case 1:
120		switch(AVR8_WGM1)
121		{
122		case Avr8::WGM1_NORMAL:
123		case Avr8::WGM1_CTC_OCR:
124		case Avr8::WGM1_CTC_ICR:
125		case Avr8::WGM1_FAST_PWM_8:
126		case Avr8::WGM1_FAST_PWM_9:
127		case Avr8::WGM1_FAST_PWM_10:
128		case Avr8::WGM1_PWM_8_PC:
129		case Avr8::WGM1_PWM_9_PC:
130		case Avr8::WGM1_PWM_10_PC:
131		case Avr8::WGM1_PWM_PFC_ICR:
132		case Avr8::WGM1_PWM_PC_ICR:
133		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Normal port operation (OC1 disconnected)\n");
134		break;
135
136		case Avr8::WGM1_FAST_PWM_ICR:
137		case Avr8::WGM1_FAST_PWM_OCR:
138		case Avr8::WGM1_PWM_PFC_OCR:
139		case Avr8::WGM1_PWM_PC_OCR:
140		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Toggle OC1A on compare match, OC1B disconnected\n");
141		break;
142		}
143		break;
144
145	167	case 2:
146		switch(AVR8_WGM1)
147		{
148		case Avr8::WGM1_NORMAL:
149		case Avr8::WGM1_CTC_OCR:
150		case Avr8::WGM1_CTC_ICR:
151		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Clear OC1%c on compare match\n", avr8_reg_name[reg]);
152		break;
153
154		case Avr8::WGM1_PWM_8_PC:
155		case Avr8::WGM1_PWM_9_PC:
156		case Avr8::WGM1_PWM_10_PC:
157		case Avr8::WGM1_PWM_PFC_ICR:
158		case Avr8::WGM1_PWM_PC_ICR:
159		case Avr8::WGM1_PWM_PFC_OCR:
160		case Avr8::WGM1_PWM_PC_OCR:
161		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Clear OC1%c on match when up-counting, set when down-counting\n", avr8_reg_name[reg]);
162		break;
163
164		case Avr8::WGM1_FAST_PWM_8:
165		case Avr8::WGM1_FAST_PWM_9:
166		case Avr8::WGM1_FAST_PWM_10:
167		case Avr8::WGM1_FAST_PWM_ICR:
168		case Avr8::WGM1_FAST_PWM_OCR:
169		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Clear OC1%c on compare match, set at BOTTOM\n", avr8_reg_name[reg]);
170		break;
171		}
	168	// TODO
172	169	break;
173	170
174	171	case 3:
175		switch(AVR8_WGM1)
176		{
177		case Avr8::WGM1_NORMAL:
178		case Avr8::WGM1_CTC_OCR:
179		case Avr8::WGM1_CTC_ICR:
180		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Set OC1%c on compare match\n", avr8_reg_name[reg]);
181		break;
182
183		case Avr8::WGM1_PWM_8_PC:
184		case Avr8::WGM1_PWM_9_PC:
185		case Avr8::WGM1_PWM_10_PC:
186		case Avr8::WGM1_PWM_PFC_ICR:
187		case Avr8::WGM1_PWM_PC_ICR:
188		case Avr8::WGM1_PWM_PFC_OCR:
189		case Avr8::WGM1_PWM_PC_OCR:
190		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Set OC1%c on match when up-counting, clear on match when down-counting\n", avr8_reg_name[reg]);
191		break;
192
193		case Avr8::WGM1_FAST_PWM_8:
194		case Avr8::WGM1_FAST_PWM_9:
195		case Avr8::WGM1_FAST_PWM_10:
196		case Avr8::WGM1_FAST_PWM_ICR:
197		case Avr8::WGM1_FAST_PWM_OCR:
198		//verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Set OC1%c on compare match, clear at BOTTOM\n", avr8_reg_name[reg]);
199		break;
200		}
201	172	break;
202		default:
203		verboselog(machine(), 0, "avr8_update_timer1_compare_mode: Unknown COM1%c mode setting (%d)\n", avr8_reg_name[reg], mode);
204		break;
205	173	}
	174	*/
206	175	}
207		*/
	176
	177	count += increment;
	178	m_regs[Avr8::REGIDX_TCNT1H] = (count >> 8) & 0xff;
	179	m_regs[Avr8::REGIDX_TCNT1L] = count & 0xff;
208	180	}
209	181
210	182	READ8_MEMBER(craft_state::avr8_read)
r18597	r18598
263	235	if(changed)
264	236	{
265	237	// TODO
266		verboselog(machine, 0, "avr8_change_port: DDR%c lines %02x changed\n", avr8_reg_name[reg], changed);
	238	verboselog(machine, 0, "avr8_change_ddr: DDR%c lines %02x changed\n", avr8_reg_name[reg], changed);
267	239	}
268	240	}
269	241
270	242	static void avr8_change_port(running_machine &machine, int reg, UINT8 data)
271	243	{
272		//craft_state *state = machine.driver_data<craft_state>();
	244	craft_state *state = machine.driver_data<craft_state>();
273	245
274	246	UINT8 oldport = avr8_get_ddr(machine, reg);
275	247	UINT8 newport = data;
276	248	UINT8 changed = newport ^ oldport;
	249
277	250	// TODO: When AVR8 is converted to emu/machine, this should be factored out to 8 single-bit callbacks per port
278	251	if(changed)
279	252	{
280	253	// TODO
281		verboselog(machine, 0, "avr8_change_port: PORT%c lines %02x changed\n", avr8_reg_name[reg], changed);
	254	//verboselog(machine, 0, "avr8_change_port: PORT%c lines %02x changed\n", avr8_reg_name[reg], changed);
	255	if (reg == AVR8_REG_D) {
	256	state->dac->write_unsigned8(data & 0x7f);
	257	}
282	258	}
283	259	}
284	260
r18597	r18598
342	318	static void avr8_spi_update_masterslave_select(running_machine &machine)
343	319	{
344	320	// TODO
345		craft_state *state = machine.driver_data<craft_state>();
	321	//craft_state *state = machine.driver_data<craft_state>();
346	322	verboselog(machine, 0, "avr8_spi_update_masterslave_select: TODO; AVR is %s\n", AVR8_SPCR_MSTR ? "Master" : "Slave");
347	323	}
348	324
349	325	static void avr8_spi_update_clock_polarity(running_machine &machine)
350	326	{
351	327	// TODO
352		craft_state *state = machine.driver_data<craft_state>();
	328	//craft_state *state = machine.driver_data<craft_state>();
353	329	verboselog(machine, 0, "avr8_spi_update_clock_polarity: TODO; SCK is Active-%s\n", AVR8_SPCR_CPOL ? "Low" : "High");
354	330	}
355	331
356	332	static void avr8_spi_update_clock_phase(running_machine &machine)
357	333	{
358	334	// TODO
359		craft_state *state = machine.driver_data<craft_state>();
	335	//craft_state *state = machine.driver_data<craft_state>();
360	336	verboselog(machine, 0, "avr8_spi_update_clock_phase: TODO; Sampling edge is %s\n", AVR8_SPCR_CPHA ? "Trailing" : "Leading");
361	337	}
362	338
r18597	r18598
365	341	static void avr8_spi_update_clock_rate(running_machine &machine)
366	342	{
367	343	// TODO
368		craft_state *state = machine.driver_data<craft_state>();
	344	//craft_state *state = machine.driver_data<craft_state>();
369	345	verboselog(machine, 0, "avr8_spi_update_clock_rate: TODO; New clock rate should be f/%d\n", avr8_spi_clock_divisor[AVR8_SPCR_SPR] / (AVR8_SPSR_SPR2X ? 2 : 1));
370	346	}
371	347
r18597	r18598
448	424	UINT8 newtimsk = data;
449	425	UINT8 changed = newtimsk ^ oldtimsk;
450	426
	427	AVR8_TIMSK1 = newtimsk;
	428
451	429	if(changed & AVR8_TIMSK1_ICIE1_MASK)
452	430	{
453	431	// Check for Input Capture Interrupt interrupt condition
r18597	r18598
528	506	UINT8 newtccr = data;
529	507	UINT8 changed = newtccr ^ oldtccr;
530	508
531		if(changed & AVR8_TCCR1A_WGM1_10)
	509	state->m_regs[Avr8::REGIDX_TCCR1A] = newtccr;
	510
	511	if(changed & AVR8_TCCR1A_WGM1_10_MASK)
532	512	{
533	513	// TODO
534	514	avr8_update_timer1_waveform_gen_mode(machine);
r18597	r18598
690	670	UINT8 newtccr = data;
691	671	UINT8 changed = newtccr ^ oldtccr;
692	672
	673	state->m_regs[Avr8::REGIDX_TCCR1B] = newtccr;
	674
693	675	if(changed & AVR8_TCCR1B_ICNC1_MASK)
694	676	{
695	677	// TODO
r18597	r18598
832	814	UINT8 *p_reg_l = (reg == AVR8_REG_A) ? &AVR8_OCR1AL : &AVR8_OCR1BL;
833	815	*p_reg_h = (UINT8)(newval >> 8);
834	816	*p_reg_l = (UINT8)newval;
	817
835	818	// TODO
836	819	verboselog(machine, 0, "avr8_update_ocr1: TODO: new OCR1%c = %04x\n", avr8_reg_name[reg], newval);
837	820	}
r18597	r18598
892	875	avr8_changed_tccr2a(machine(), data);
893	876	break;
894	877
	878	case Avr8::REGIDX_TCNT2:
	879	//verboselog(machine(), 0, "AVR8: TCNT2 = %02x\n", data );
	880	AVR8_TCNT2 = data;
	881	break;
	882
	883	case Avr8::REGIDX_GTCCR:
	884	//verboselog(machine(), 0, "AVR8: GTCCR = %02x\n", data );
	885	// TODO
	886	break;
	887
895	888	case Avr8::REGIDX_SPL:
896	889	case Avr8::REGIDX_SPH:
897	890	case Avr8::REGIDX_SREG:
r18597	r18598
906	899	avr8_change_spcr(machine(), data);
907	900	break;
908	901
	902	case Avr8::REGIDX_PORTD:
	903	avr8_change_port(machine(), AVR8_REG_D, data);
	904	break;
	905
909	906	case Avr8::REGIDX_DDRD:
910	907	avr8_change_ddr(machine(), AVR8_REG_D, data);
911	908	break;
r18597	r18598
980	977	AVR8_TCNT1H = 0;
981	978	AVR8_TCNT1L = 0;
982	979
983		machine().device<dac_device>("dac")->write_unsigned8(0x00);
	980	state->dac = machine().device<dac_device>("dac");
	981
	982	state->dac->write_unsigned8(0x00);
984	983	}
985	984
986	985	static MACHINE_CONFIG_START( craft, craft_state )

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