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r18575 Wednesday 17th October, 2012 at 15:45:42 UTC by Angelo Salese
Small changes + promoted to working
[src/mame/drivers]dblcrown.c

trunk/src/mame/drivers/dblcrown.c
r18574r18575
55   driver by Angelo Salese
66
77   TODO:
8   - RAM-based tiles color offset (perhaps there isn't a real palette bank,
9     it's just sloppy code?)
10   - Bogus "Hole" in main screen display
8   - Bogus "Hole" in main screen display;
119   - Is the background pen really black?
12   - Lots of unmapped I/Os (game doesn't make much use of the HW)
10   - Lots of unmapped I/Os (game doesn't make much use of the HW);
11   - outputs / lamps;
12   - video / irq timings;
1313
14   Notes:
15   - at POST the SW tries to write to the palette RAM in a banking fashion.
16     I think it's just an HW left-over.
17   - there are various bogus checks to ROM region throughout the whole SW
18     (0x0030-0x0031? O.o)
19
1420============================================================================
1521   Excellent System
1622   boardlabel: ES-9411B
r18574r18575
5763   UINT8 *m_vram;
5864   UINT8 m_vram_bank[2];
5965   UINT8 m_mux_data;
66   UINT8 m_lamps_data;
6067
6168   DECLARE_READ8_MEMBER(bank_r);
6269   DECLARE_WRITE8_MEMBER(bank_w);
r18574r18575
7279   DECLARE_WRITE8_MEMBER(mux_w);
7380   DECLARE_READ8_MEMBER(in_mux_r);
7481   DECLARE_READ8_MEMBER(in_mux_type_r);
82   DECLARE_WRITE8_MEMBER(output_w);
83   DECLARE_READ8_MEMBER(lamps_r);
84   DECLARE_WRITE8_MEMBER(lamps_w);
7585
7686   TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_irq_scanline);
7787
r18574r18575
106116      for (x=0;x<32;x++)
107117      {
108118         UINT16 tile = ((m_vram[count])|(m_vram[count+1]<<8)) & 0xfff;
109         UINT8 col = (m_vram[count+1] >> 4) + 0x10;
119         UINT8 col = (m_vram[count+1] >> 4);
110120
111121         drawgfx_opaque(bitmap,cliprect,gfx_2,tile,col,0,0,x*16,y*16);
112122
r18574r18575
121131      for (x=0;x<64;x++)
122132      {
123133         UINT16 tile = ((m_vram[count])|(m_vram[count+1]<<8)) & 0xfff;
124         UINT8 col = 0x10; // TODO
134         UINT8 col = (m_vram[count+1] >> 4); // ok?
125135
126136         drawgfx_transpen(bitmap,cliprect,gfx,tile,col,0,0,x*8,y*8,0);
127137
r18574r18575
156166
157167READ8_MEMBER( dblcrown_state::palette_r)
158168{
159   if(m_bank & 8) /* TODO: verify this */
160      offset+=0x200;
169   //if(m_bank & 8) /* TODO: verify this */
170   //   offset+=0x200;
161171
162172   return m_pal_ram[offset];
163173}
r18574r18575
166176{
167177   int r,g,b,datax;
168178
169   if(m_bank & 8) /* TODO: verify this */
170      offset+=0x200;
179   //if(m_bank & 8) /* TODO: verify this */
180   //   offset+=0x200;
171181
172182   m_pal_ram[offset] = data;
173183   offset>>=1;
r18574r18575
264274   return res;
265275}
266276
277WRITE8_MEMBER( dblcrown_state::output_w )
278{
279   // bit 4: coin counter
280
281   //popmessage("%02x",data);
282}
283
284
285READ8_MEMBER( dblcrown_state::lamps_r )
286{
287   return m_lamps_data;
288}
289
290WRITE8_MEMBER( dblcrown_state::lamps_w )
291{
292   //popmessage("%02x",data);
293   m_lamps_data = data;
294}
295
267296static ADDRESS_MAP_START( dblcrown_map, AS_PROGRAM, 8, dblcrown_state )
268297   ADDRESS_MAP_UNMAP_HIGH
269298   AM_RANGE(0x0000, 0x7fff) AM_ROM
r18574r18575
272301   AM_RANGE(0xb800, 0xbfff) AM_RAM AM_SHARE("nvram")
273302   AM_RANGE(0xc000, 0xdfff) AM_READWRITE(vram_r, vram_w)
274303   AM_RANGE(0xf000, 0xf1ff) AM_READWRITE(palette_r, palette_w)
275//   AM_RANGE(0xfe00, 0xfeff) AM_RAM // ???
304   AM_RANGE(0xfe00, 0xfeff) AM_RAM // ???
276305   AM_RANGE(0xff00, 0xff01) AM_READWRITE(vram_bank_r, vram_bank_w)
277306   AM_RANGE(0xff04, 0xff04) AM_READWRITE(irq_source_r,irq_source_w)
278307
279//   AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through
308   AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through
280309ADDRESS_MAP_END
281310
282311static ADDRESS_MAP_START( dblcrown_io, AS_IO, 8, dblcrown_state )
r18574r18575
288317   AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWD")
289318   AM_RANGE(0x04, 0x04) AM_READ(in_mux_r)
290319   AM_RANGE(0x05, 0x05) AM_READ(in_mux_type_r)
320   AM_RANGE(0x10, 0x10) AM_READWRITE(lamps_r,lamps_w)
291321   AM_RANGE(0x11, 0x11) AM_READWRITE(bank_r,bank_w)
292322   AM_RANGE(0x12, 0x12) AM_READWRITE(mux_r,mux_w)
293//   AM_RANGE(0x20, 0x20) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
294323   AM_RANGE(0x20, 0x21) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
324//   AM_RANGE(0x30, 0x30) always 1?
325   AM_RANGE(0x40, 0x40) AM_WRITE(output_w)
295326ADDRESS_MAP_END
296327
297328static INPUT_PORTS_START( dblcrown )
r18574r18575
455486
456487static GFXDECODE_START( dblcrown )
457488#ifdef DEBUG_VRAM
458   GFXDECODE_ENTRY( "vram", 0, char_8x8_layout, 0, 0x20 )
489   GFXDECODE_ENTRY( "vram", 0, char_8x8_layout, 0, 0x10 )
459490#endif
460   GFXDECODE_ENTRY( "gfx1", 0, char_16x16_layout, 0, 0x20 )
491   GFXDECODE_ENTRY( "gfx1", 0, char_16x16_layout, 0, 0x10 )
461492GFXDECODE_END
462493
463494
r18574r18575
538569
539570   MCFG_GFXDECODE(dblcrown)
540571
541   MCFG_PALETTE_LENGTH(0x200)
572   MCFG_PALETTE_LENGTH(0x100)
542573
543574   MCFG_NVRAM_ADD_0FILL("nvram")
544575
r18574r18575
570601   ROM_LOAD("palce16v8h.u39", 0x0000, 0x0bf1, CRC(997b0ba9) SHA1(1c121ab74f33d5162b619740b08cc7bc694c257d) )
571602ROM_END
572603
573GAME( 1997, dblcrown,  0,   dblcrown,  dblcrown,  driver_device, 0,       ROT0, "Cadence Technology",      "Double Crown (v1.0.3)", GAME_NOT_WORKING | GAME_IMPERFECT_GRAPHICS ) // 1997 DYNA copyright in tile GFX
604GAME( 1997, dblcrown,  0,   dblcrown,  dblcrown,  driver_device, 0,       ROT0, "Cadence Technology",      "Double Crown (v1.0.3)", GAME_IMPERFECT_GRAPHICS ) // 1997 DYNA copyright in tile GFX

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