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r18567 Tuesday 16th October, 2012 at 23:23:15 UTC by Angelo Salese
Added most things, game is almost working with small issues
[src/mame/drivers]dblcrown.c

trunk/src/mame/drivers/dblcrown.c
r18566r18567
11/***************************************************************************
2Double Crown
3(C) 1994, or maybe 1995
4cards gambling game
52
6dfinal.c ish, but newer?
3   Double Crown (c) 1997 Cadence Technology / Dyna
74
5   driver by Angelo Salese
86
9Excellent System
10boardlabel: ES-9411B
7   TODO:
8   - RAM-based tiles color offset (perhaps there isn't a real palette bank,
9     it's just sloppy code?)
10   - Bogus "Hole" in main screen display
11   - Is the background pen really black?
1112
1228.6363 xtal
13ES-9409 QFP is 208 pins.. for graphics only?
14Z0840006PSC Zilog z80, is rated 6.17 MHz
15OKI M82C55A-2
1665764H-5 .. 64kbit ram CMOS
172 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8)
184 * dipsw 8pos
19YMZ284-D (ay8910, but without i/o ports)
20MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog? and for keeping nvram stable?
13============================================================================
14   Excellent System
15   boardlabel: ES-9411B
2116
17   28.6363 xtal
18   ES-9409 QFP is 208 pins.. for graphics only?
19   Z0840006PSC Zilog z80, is rated 6.17 MHz
20   OKI M82C55A-2
21   65764H-5 .. 64kbit ram CMOS
22   2 * N341256P-25 - CMOS SRAM 256K-BIT(32KX8)
23   4 * dipsw 8pos
24   YMZ284-D (ay8910, but without i/o ports)
25   MAXIM MAX693ACPE is a "Microprocessor Supervisory Circuit", for watchdog? and for keeping nvram stable?
26
2227***************************************************************************/
2328
2429
r18566r18567
5055   UINT8 *m_pal_ram;
5156   UINT8 *m_vram;
5257   UINT8 m_vram_bank[2];
58   UINT8 m_mux_data;
5359
5460   DECLARE_READ8_MEMBER(bank_r);
5561   DECLARE_WRITE8_MEMBER(bank_w);
r18566r18567
6167   DECLARE_WRITE8_MEMBER(vram_w);
6268   DECLARE_READ8_MEMBER(vram_bank_r);
6369   DECLARE_WRITE8_MEMBER(vram_bank_w);
70   DECLARE_READ8_MEMBER(mux_r);
71   DECLARE_WRITE8_MEMBER(mux_w);
72   DECLARE_READ8_MEMBER(in_mux_r);
73   DECLARE_READ8_MEMBER(in_mux_type_r);
6474
6575   TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_irq_scanline);
6676
r18566r18567
8393
8494UINT32 dblcrown_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
8595{
96   gfx_element *gfx = machine().gfx[0];
97   gfx_element *gfx_2 = machine().gfx[1];
98   int x,y;
99   int count;
100
101   count = 0xa000;
102
103   for (y=0;y<16;y++)
104   {
105      for (x=0;x<32;x++)
106      {
107         UINT16 tile = ((m_vram[count])|(m_vram[count+1]<<8)) & 0xfff;
108         UINT8 col = (m_vram[count+1] >> 4) + 0x10;
109
110         drawgfx_opaque(bitmap,cliprect,gfx_2,tile,col,0,0,x*16,y*16);
111
112         count+=2;
113      }
114   }
115
116   count = 0xb000;
117
118   for (y=0;y<32;y++)
119   {
120      for (x=0;x<64;x++)
121      {
122         UINT16 tile = m_vram[count];
123         UINT8 col = 0x10; // TODO
124
125         drawgfx_transpen(bitmap,cliprect,gfx,tile,col,0,0,x*8,y*8,0);
126
127         count+=2;
128      }
129   }
130
131
86132   return 0;
87133}
88134
r18566r18567
129175   r = ((datax)&0x000f)>>0;
130176   g = ((datax)&0x00f0)>>4;
131177   b = ((datax)&0x0f00)>>8;
178   /* TODO: remaining bits */
132179
133180   palette_set_color_rgb(machine(), offset, pal4bit(r), pal4bit(g), pal4bit(b));
134181}
r18566r18567
137184READ8_MEMBER( dblcrown_state::vram_r)
138185{
139186   UINT32 hi_offs;
140   hi_offs = m_vram_bank[offset & 0x1000 >> 12] << 12;
187   hi_offs = m_vram_bank[(offset & 0x1000) >> 12] << 12;
141188
142189   return m_vram[(offset & 0xfff) | hi_offs];
143190}
r18566r18567
172219      printf("vram bank = %02x\n",data);
173220}
174221
222READ8_MEMBER( dblcrown_state::mux_r)
223{
224   return m_mux_data;
225}
226
227WRITE8_MEMBER( dblcrown_state::mux_w)
228{
229   m_mux_data = data;
230}
231
232READ8_MEMBER( dblcrown_state::in_mux_r )
233{
234   const char *const muxnames[] = { "IN0", "IN1", "IN2", "IN3" };
235   int i;
236   UINT8 res;
237
238   res = 0;
239
240   for(i=0;i<4;i++)
241   {
242      if(m_mux_data & 1 << i)
243         res |= ioport(muxnames[i])->read();
244   }
245
246   return res;
247}
248
249READ8_MEMBER( dblcrown_state::in_mux_type_r )
250{
251   const char *const muxnames[] = { "IN0", "IN1", "IN2", "IN3" };
252   int i;
253   UINT8 res;
254
255   res = 0xff;
256
257   for(i=0;i<4;i++)
258   {
259      if(ioport(muxnames[i])->read() != 0xff)
260         res &= ~(1 << i);
261   }
262
263   return res;
264}
265
175266static ADDRESS_MAP_START( dblcrown_map, AS_PROGRAM, 8, dblcrown_state )
267   ADDRESS_MAP_UNMAP_HIGH
176268   AM_RANGE(0x0000, 0x7fff) AM_ROM
177269   AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("rom_bank")
178270   AM_RANGE(0xa000, 0xb7ff) AM_RAM // work ram
179271   AM_RANGE(0xb800, 0xbfff) AM_RAM AM_SHARE("nvram")
180272   AM_RANGE(0xc000, 0xdfff) AM_READWRITE(vram_r, vram_w)
181   AM_RANGE(0xf000, 0xf1ff) AM_READWRITE(palette_r, palette_w) //AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_byte_le_w) AM_SHARE("paletteram") // TODO: correct bit order
182   AM_RANGE(0xfe00, 0xfeff) AM_RAM // ???
273   AM_RANGE(0xf000, 0xf1ff) AM_READWRITE(palette_r, palette_w)
274//   AM_RANGE(0xfe00, 0xfeff) AM_RAM // ???
183275   AM_RANGE(0xff00, 0xff01) AM_READWRITE(vram_bank_r, vram_bank_w)
184276   AM_RANGE(0xff04, 0xff04) AM_READWRITE(irq_source_r,irq_source_w)
185277
186   AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through
278//   AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through
187279ADDRESS_MAP_END
188280
189281static ADDRESS_MAP_START( dblcrown_io, AS_IO, 8, dblcrown_state )
190   ADDRESS_MAP_GLOBAL_MASK(0xff)
191   AM_RANGE(0x11, 0x11) AM_READWRITE(bank_r,bank_w)
282   ADDRESS_MAP_GLOBAL_MASK(0xff)
283   ADDRESS_MAP_UNMAP_HIGH
284   AM_RANGE(0x00, 0x00) AM_READ_PORT("DSWA")
285   AM_RANGE(0x01, 0x01) AM_READ_PORT("DSWB")
286   AM_RANGE(0x02, 0x02) AM_READ_PORT("DSWC")
287   AM_RANGE(0x03, 0x03) AM_READ_PORT("DSWD")
288   AM_RANGE(0x04, 0x04) AM_READ(in_mux_r)
289   AM_RANGE(0x05, 0x05) AM_READ(in_mux_type_r)
290   AM_RANGE(0x11, 0x11) AM_READWRITE(bank_r,bank_w)
291   AM_RANGE(0x12, 0x12) AM_READWRITE(mux_r,mux_w)
292//   AM_RANGE(0x20, 0x20) AM_DEVREAD_LEGACY("aysnd", ay8910_r)
293   AM_RANGE(0x20, 0x21) AM_DEVWRITE_LEGACY("aysnd", ay8910_address_data_w)
192294ADDRESS_MAP_END
193295
194296static INPUT_PORTS_START( dblcrown )
195   /* dummy active high structure */
196   PORT_START("SYSA")
197   PORT_DIPNAME( 0x01, 0x00, "SYSA" )
198   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
199   PORT_DIPSETTING(    0x01, DEF_STR( On ) )
200   PORT_DIPNAME( 0x02, 0x00, DEF_STR( Unknown ) )
201   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
202   PORT_DIPSETTING(    0x02, DEF_STR( On ) )
203   PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) )
204   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
205   PORT_DIPSETTING(    0x04, DEF_STR( On ) )
206   PORT_DIPNAME( 0x08, 0x00, DEF_STR( Unknown ) )
207   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
208   PORT_DIPSETTING(    0x08, DEF_STR( On ) )
209   PORT_DIPNAME( 0x10, 0x00, DEF_STR( Unknown ) )
210   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
211   PORT_DIPSETTING(    0x10, DEF_STR( On ) )
212   PORT_DIPNAME( 0x20, 0x00, DEF_STR( Unknown ) )
213   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
214   PORT_DIPSETTING(    0x20, DEF_STR( On ) )
215   PORT_DIPNAME( 0x40, 0x00, DEF_STR( Unknown ) )
216   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
217   PORT_DIPSETTING(    0x40, DEF_STR( On ) )
218   PORT_DIPNAME( 0x80, 0x00, DEF_STR( Unknown ) )
219   PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
220   PORT_DIPSETTING(    0x80, DEF_STR( On ) )
297   PORT_START("IN0")
298   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME("Memory Reset")
299   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Credit Reset")
300   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 )
301   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN ) PORT_NAME("Note")
302   PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
221303
222   /* dummy active low structure */
304   PORT_START("IN1")
305   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Big")
306   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Small")
307   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE )
308   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Payout")
309   PORT_BIT( 0xf0, IP_ACTIVE_LOW, IPT_UNUSED )
310
311   PORT_START("IN2")
312   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD1 )
313   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD2 )
314   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_HOLD3 )
315   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_POKER_HOLD4 )
316   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 )
317   PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
318
319   PORT_START("IN3")
320   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME("Cancel / Repeat Bet")
321   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_DEAL ) PORT_NAME("Deal / Draw")
322   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_BET )
323   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_D_UP )
324   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE3 ) PORT_NAME("Analyzer")
325   PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED )
326
223327   PORT_START("DSWA")
224328   PORT_DIPNAME( 0x01, 0x01, "DSWA" )
225329   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
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239343   PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
240344   PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
241345   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
346   PORT_DIPNAME( 0x40, 0x40, "Input Test" )
347   PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
348   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
349   PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
350   PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
351   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
352
353   PORT_START("DSWB")
354   PORT_DIPNAME( 0x01, 0x01, "DSWB" )
355   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
356   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
357   PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
358   PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
359   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
360   PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
361   PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
362   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
363   PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
364   PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
365   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
366   PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
367   PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
368   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
369   PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
370   PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
371   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
242372   PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
243373   PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
244374   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
245375   PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
246376   PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
247377   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
378
379   PORT_START("DSWC")
380   PORT_DIPNAME( 0x01, 0x01, "DSWC" )
381   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
382   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
383   PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
384   PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
385   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
386   PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
387   PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
388   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
389   PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
390   PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
391   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
392   PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
393   PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
394   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
395   PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
396   PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
397   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
398   PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
399   PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
400   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
401   PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
402   PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
403   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
404
405   PORT_START("DSWD")
406   PORT_DIPNAME( 0x01, 0x01, "DSWD" )
407   PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
408   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
409   PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
410   PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
411   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
412   PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
413   PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
414   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
415   PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
416   PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
417   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
418   PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
419   PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
420   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
421   PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
422   PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
423   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
424   PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
425   PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
426   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
427   PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
428   PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
429   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
248430INPUT_PORTS_END
249431
250432static const gfx_layout char_8x8_layout =
r18566r18567
298480{
299481   int scanline = param;
300482
301   if (scanline == 240)
483   if (scanline == 256)
302484   {
303485      m_maincpu->set_input_line(0, HOLD_LINE);
304486      m_irq_src = 2;
305487   }
488   else if ((scanline % 4) == 0) /* TODO: proper timing of this ... */
489   {
490/*
491This is the main loop of this irq source. They hooked a timer irq then polled inputs via this wacky routine.
492It needs at least 64 instances because 0xa05b will be eventually nuked by the vblank irq sub-routine.
306493
307   /* TODO: unknown source */
308   if (scanline == 128)
309   {
494043B: pop  af
495043C: push af
496043D: ld   a,($A05B)
4970440: cp   $00
4980442: jr   z,$0463
4990444: cp   $10
5000446: jr   z,$046D
5010448: cp   $20
502044A: jr   z,$047F
503044C: cp   $30
504044E: jr   z,$0491
5050450: cp   $40
5060452: jr   z,$04AB
5070454: ld   a,($A05B)
5080457: inc  a
5090458: ld   ($A05B),a
510045B: xor  a
511045C: ld   ($FF04),a
512045F: pop  af
5130460: ei
5140461: reti
515*/
310516      m_maincpu->set_input_line(0, HOLD_LINE);
311517      m_irq_src = 4;
312518   }
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326532   MCFG_SCREEN_REFRESH_RATE(60)
327533   MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500))
328534   MCFG_SCREEN_UPDATE_DRIVER(dblcrown_state, screen_update)
329   MCFG_SCREEN_SIZE(32*8, 32*8)
330   MCFG_SCREEN_VISIBLE_AREA(0*8, 32*8-1, 0*8, 32*8-1)
535   MCFG_SCREEN_SIZE(64*8, 64*8)
536   MCFG_SCREEN_VISIBLE_AREA(0*8, 40*8-1, 2*8, 30*8-1)
331537
332538   MCFG_GFXDECODE(dblcrown)
333539
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338544   /* sound hardware */
339545   MCFG_SPEAKER_STANDARD_MONO("mono")
340546   MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/12)
341    MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
547    MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
342548MACHINE_CONFIG_END
343549
344550
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363569   ROM_LOAD("palce16v8h.u39", 0x0000, 0x0bf1, CRC(997b0ba9) SHA1(1c121ab74f33d5162b619740b08cc7bc694c257d) )
364570ROM_END
365571
366GAME( 199?, dblcrown,  0,   dblcrown,  dblcrown,  driver_device, 0,       ROT0, "Excellent System",      "Double Crown", GAME_IS_SKELETON ) // 1997 DYNA copyright in tile GFX
572GAME( 1997, dblcrown,  0,   dblcrown,  dblcrown,  driver_device, 0,       ROT0, "Cadence Technology",      "Double Crown (v1.0.3)", GAME_NOT_WORKING | GAME_IMPERFECT_GRAPHICS ) // 1997 DYNA copyright in tile GFX

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