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r18565 Tuesday 16th October, 2012 at 20:48:52 UTC by Angelo Salese
Hooked up various banks, now we're ready to draw ...
[src/mame/drivers]dblcrown.c

trunk/src/mame/drivers/dblcrown.c
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2929
3030#define MAIN_CLOCK XTAL_28_63636MHz
3131
32#define DEBUG_VRAM
33
3234class dblcrown_state : public driver_device
3335{
3436public:
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4547
4648   UINT8 m_bank;
4749   UINT8 m_irq_src;
50   UINT8 *m_pal_ram;
51   UINT8 *m_vram;
52   UINT8 m_vram_bank[2];
4853
4954   DECLARE_READ8_MEMBER(bank_r);
5055   DECLARE_WRITE8_MEMBER(bank_w);
5156   DECLARE_READ8_MEMBER(irq_source_r);
5257   DECLARE_WRITE8_MEMBER(irq_source_w);
58   DECLARE_READ8_MEMBER(palette_r);
59   DECLARE_WRITE8_MEMBER(palette_w);
60   DECLARE_READ8_MEMBER(vram_r);
61   DECLARE_WRITE8_MEMBER(vram_w);
62   DECLARE_READ8_MEMBER(vram_bank_r);
63   DECLARE_WRITE8_MEMBER(vram_bank_w);
5364
5465   TIMER_DEVICE_CALLBACK_MEMBER(dblcrown_irq_scanline);
5566
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6475
6576void dblcrown_state::video_start()
6677{
78   m_pal_ram = auto_alloc_array(machine(), UINT8, 0x200*2);
79   m_vram = auto_alloc_array(machine(), UINT8, 0x1000*0x10);
6780
81   state_save_register_global_pointer(machine(), m_vram, 0x1000*0x10);
6882}
6983
7084UINT32 dblcrown_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
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93107   m_irq_src = data; // this effectively acks the irq, by writing 0
94108}
95109
110READ8_MEMBER( dblcrown_state::palette_r)
111{
112   if(m_bank & 8) /* TODO: verify this */
113      offset+=0x200;
96114
115   return m_pal_ram[offset];
116}
117
118WRITE8_MEMBER( dblcrown_state::palette_w)
119{
120   int r,g,b,datax;
121
122   if(m_bank & 8) /* TODO: verify this */
123      offset+=0x200;
124
125   m_pal_ram[offset] = data;
126   offset>>=1;
127   datax = m_pal_ram[offset*2] + 256*m_pal_ram[offset*2 + 1];
128
129   r = ((datax)&0x000f)>>0;
130   g = ((datax)&0x00f0)>>4;
131   b = ((datax)&0x0f00)>>8;
132
133   palette_set_color_rgb(machine(), offset, pal4bit(r), pal4bit(g), pal4bit(b));
134}
135
136
137READ8_MEMBER( dblcrown_state::vram_r)
138{
139   UINT32 hi_offs;
140   hi_offs = m_vram_bank[offset & 0x1000 >> 12] << 12;
141
142   return m_vram[(offset & 0xfff) | hi_offs];
143}
144
145WRITE8_MEMBER( dblcrown_state::vram_w)
146{
147   UINT32 hi_offs;
148   hi_offs = m_vram_bank[(offset & 0x1000) >> 12] << 12;
149
150   m_vram[(offset & 0xfff) | hi_offs] = data;
151
152   #ifdef DEBUG_VRAM
153   {
154      UINT8 *VRAM = memregion("vram")->base();
155
156      VRAM[(offset & 0xfff) | hi_offs] = data;
157      machine().gfx[0]->mark_dirty(((offset & 0xfff) | hi_offs) / 32);
158   }
159   #endif
160}
161
162READ8_MEMBER( dblcrown_state::vram_bank_r)
163{
164   return m_vram_bank[offset];
165}
166
167WRITE8_MEMBER( dblcrown_state::vram_bank_w)
168{
169   m_vram_bank[offset] = data & 0xf;
170
171   if(data & 0xf0)
172      printf("vram bank = %02x\n",data);
173}
174
97175static ADDRESS_MAP_START( dblcrown_map, AS_PROGRAM, 8, dblcrown_state )
98176   AM_RANGE(0x0000, 0x7fff) AM_ROM
99177   AM_RANGE(0x8000, 0x9fff) AM_ROMBANK("rom_bank")
100178   AM_RANGE(0xa000, 0xb7ff) AM_RAM // work ram
101179   AM_RANGE(0xb800, 0xbfff) AM_RAM AM_SHARE("nvram")
102   AM_RANGE(0xc000, 0xc3ff) AM_RAM
103   AM_RANGE(0xc400, 0xc7ff) AM_RAM
104   AM_RANGE(0xc800, 0xcfff) AM_RAM
105   AM_RANGE(0xd000, 0xdfff) AM_RAM // vram
106   AM_RANGE(0xf000, 0xf1ff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_byte_le_w) AM_SHARE("paletteram") // TODO: correct bit order
180   AM_RANGE(0xc000, 0xdfff) AM_READWRITE(vram_r, vram_w)
181   AM_RANGE(0xf000, 0xf1ff) AM_READWRITE(palette_r, palette_w) //AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_byte_le_w) AM_SHARE("paletteram") // TODO: correct bit order
107182   AM_RANGE(0xfe00, 0xfeff) AM_RAM // ???
108   // 0xff00 - 0xff01 RAM banks for 0xd000
183   AM_RANGE(0xff00, 0xff01) AM_READWRITE(vram_bank_r, vram_bank_w)
109184   AM_RANGE(0xff04, 0xff04) AM_READWRITE(irq_source_r,irq_source_w)
110185
111186   AM_RANGE(0xff00, 0xffff) AM_RAM // ???, intentional fall-through
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172247   PORT_DIPSETTING(    0x00, DEF_STR( On ) )
173248INPUT_PORTS_END
174249
250static const gfx_layout char_8x8_layout =
251{
252   8,8,
253   RGN_FRAC(1,1),
254   4,
255   { 0,1,2,3 },
256   { 4,0, 12,8, 20,16, 28,24 },
257   { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
258   32*8
259};
175260
176261static const gfx_layout char_16x16_layout =
177262{
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186271
187272
188273static GFXDECODE_START( dblcrown )
189   GFXDECODE_ENTRY( "gfx1", 0, char_16x16_layout, 0, 16*4 )
274#ifdef DEBUG_VRAM
275   GFXDECODE_ENTRY( "vram", 0, char_8x8_layout, 0, 0x20 )
276#endif
277   GFXDECODE_ENTRY( "gfx1", 0, char_16x16_layout, 0, 0x20 )
190278GFXDECODE_END
191279
192280
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217305   }
218306
219307   /* TODO: unknown source */
220   if (scanline == 0)
308   if (scanline == 128)
221309   {
222310      m_maincpu->set_input_line(0, HOLD_LINE);
223311      m_irq_src = 4;
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243331
244332   MCFG_GFXDECODE(dblcrown)
245333
246   MCFG_PALETTE_LENGTH(0x100)
334   MCFG_PALETTE_LENGTH(0x200)
247335
248336   MCFG_NVRAM_ADD_0FILL("nvram")
249337
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267355   ROM_REGION( 0x80000, "gfx1", ROMREGION_ERASE00 )
268356   ROM_LOAD("2.u43", 0x00000, 0x80000, CRC(58200bd4) SHA1(2795cfc41056111f66bfb82916343d1c733baa83) )
269357
358#ifdef DEBUG_VRAM
359   ROM_REGION( 0x1000*0x10, "vram", ROMREGION_ERASE00 )
360#endif
361
270362   ROM_REGION( 0x0bf1, "pals", 0 ) // in Jedec format
271363   ROM_LOAD("palce16v8h.u39", 0x0000, 0x0bf1, CRC(997b0ba9) SHA1(1c121ab74f33d5162b619740b08cc7bc694c257d) )
272364ROM_END

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