trunk/src/emu/cpu/tlcs900/900tbl.c
| r18558 | r18559 | |
| 1590 | 1590 | cpustate->xssp.d -= 4; |
| 1591 | 1591 | WRMEML( cpustate->xssp.d, cpustate->pc.d ); |
| 1592 | 1592 | cpustate->pc.d = cpustate->imm1.d; |
| 1593 | cpustate->prefetch_clear = true; |
| 1593 | 1594 | } |
| 1594 | 1595 | |
| 1595 | 1596 | |
| r18558 | r18559 | |
| 1601 | 1602 | WRMEML( cpustate->xssp.d, cpustate->pc.d ); |
| 1602 | 1603 | cpustate->pc.d = cpustate->ea2.d; |
| 1603 | 1604 | cpustate->cycles += 6; |
| 1605 | cpustate->prefetch_clear = true; |
| 1604 | 1606 | } |
| 1605 | 1607 | } |
| 1606 | 1608 | |
| r18558 | r18559 | |
| 1610 | 1612 | cpustate->xssp.d -= 4; |
| 1611 | 1613 | WRMEML( cpustate->xssp.d, cpustate->pc.d ); |
| 1612 | 1614 | cpustate->pc.d = cpustate->ea1.d; |
| 1615 | cpustate->prefetch_clear = true; |
| 1613 | 1616 | } |
| 1614 | 1617 | |
| 1615 | 1618 | |
| r18558 | r18559 | |
| 1743 | 1746 | { |
| 1744 | 1747 | cpustate->pc.d -= 2; |
| 1745 | 1748 | cpustate->cycles += 4; |
| 1749 | cpustate->prefetch_clear = true; |
| 1746 | 1750 | } |
| 1747 | 1751 | } |
| 1748 | 1752 | |
| r18558 | r18559 | |
| 1768 | 1772 | { |
| 1769 | 1773 | cpustate->pc.d -= 2; |
| 1770 | 1774 | cpustate->cycles += 4; |
| 1775 | cpustate->prefetch_clear = true; |
| 1771 | 1776 | } |
| 1772 | 1777 | } |
| 1773 | 1778 | |
| r18558 | r18559 | |
| 1793 | 1798 | { |
| 1794 | 1799 | cpustate->pc.d -= 2; |
| 1795 | 1800 | cpustate->cycles += 4; |
| 1801 | cpustate->prefetch_clear = true; |
| 1796 | 1802 | } |
| 1797 | 1803 | } |
| 1798 | 1804 | |
| r18558 | r18559 | |
| 1818 | 1824 | { |
| 1819 | 1825 | cpustate->pc.d -= 2; |
| 1820 | 1826 | cpustate->cycles += 4; |
| 1827 | cpustate->prefetch_clear = true; |
| 1821 | 1828 | } |
| 1822 | 1829 | } |
| 1823 | 1830 | |
| r18558 | r18559 | |
| 2030 | 2037 | { |
| 2031 | 2038 | cpustate->pc.d = cpustate->ea2.d; |
| 2032 | 2039 | cpustate->cycles += 4; |
| 2040 | cpustate->prefetch_clear = true; |
| 2033 | 2041 | } |
| 2034 | 2042 | } |
| 2035 | 2043 | |
| r18558 | r18559 | |
| 2041 | 2049 | { |
| 2042 | 2050 | cpustate->pc.d = cpustate->ea2.d; |
| 2043 | 2051 | cpustate->cycles += 4; |
| 2052 | cpustate->prefetch_clear = true; |
| 2044 | 2053 | } |
| 2045 | 2054 | } |
| 2046 | 2055 | |
| r18558 | r18559 | |
| 2174 | 2183 | static void _JPI(tlcs900_state *cpustate) |
| 2175 | 2184 | { |
| 2176 | 2185 | cpustate->pc.d = cpustate->imm1.d; |
| 2186 | cpustate->prefetch_clear = true; |
| 2177 | 2187 | } |
| 2178 | 2188 | |
| 2179 | 2189 | |
| r18558 | r18559 | |
| 2183 | 2193 | { |
| 2184 | 2194 | cpustate->pc.d = cpustate->ea2.d; |
| 2185 | 2195 | cpustate->cycles += 4; |
| 2196 | cpustate->prefetch_clear = true; |
| 2186 | 2197 | } |
| 2187 | 2198 | } |
| 2188 | 2199 | |
| r18558 | r18559 | |
| 2193 | 2204 | { |
| 2194 | 2205 | cpustate->pc.d = cpustate->ea2.d; |
| 2195 | 2206 | cpustate->cycles += 4; |
| 2207 | cpustate->prefetch_clear = true; |
| 2196 | 2208 | } |
| 2197 | 2209 | } |
| 2198 | 2210 | |
| r18558 | r18559 | |
| 2203 | 2215 | { |
| 2204 | 2216 | cpustate->pc.d = cpustate->ea2.d; |
| 2205 | 2217 | cpustate->cycles += 4; |
| 2218 | cpustate->prefetch_clear = true; |
| 2206 | 2219 | } |
| 2207 | 2220 | } |
| 2208 | 2221 | |
| r18558 | r18559 | |
| 2399 | 2412 | cpustate->sr.b.l |= FLAG_VF; |
| 2400 | 2413 | cpustate->pc.d -= 2; |
| 2401 | 2414 | cpustate->cycles += 4; |
| 2415 | cpustate->prefetch_clear = true; |
| 2402 | 2416 | } |
| 2403 | 2417 | } |
| 2404 | 2418 | |
| r18558 | r18559 | |
| 2417 | 2431 | cpustate->sr.b.l |= FLAG_VF; |
| 2418 | 2432 | cpustate->pc.d -= 2; |
| 2419 | 2433 | cpustate->cycles += 4; |
| 2434 | cpustate->prefetch_clear = true; |
| 2420 | 2435 | } |
| 2421 | 2436 | } |
| 2422 | 2437 | |
| r18558 | r18559 | |
| 2474 | 2489 | cpustate->sr.b.l |= FLAG_VF; |
| 2475 | 2490 | cpustate->pc.d -= 2; |
| 2476 | 2491 | cpustate->cycles += 4; |
| 2492 | cpustate->prefetch_clear = true; |
| 2477 | 2493 | } |
| 2478 | 2494 | } |
| 2479 | 2495 | |
| r18558 | r18559 | |
| 2492 | 2508 | cpustate->sr.b.l |= FLAG_VF; |
| 2493 | 2509 | cpustate->pc.d -= 2; |
| 2494 | 2510 | cpustate->cycles += 4; |
| 2511 | cpustate->prefetch_clear = true; |
| 2495 | 2512 | } |
| 2496 | 2513 | } |
| 2497 | 2514 | |
| r18558 | r18559 | |
| 2516 | 2533 | { |
| 2517 | 2534 | UINT8 a, b; |
| 2518 | 2535 | |
| 2519 | | RDOP(); |
| 2520 | | a = RDOP(); |
| 2521 | | RDOP(); |
| 2522 | | b = RDOP(); |
| 2523 | | RDOP(); |
| 2536 | RDOP( cpustate ); |
| 2537 | a = RDOP( cpustate ); |
| 2538 | RDOP( cpustate ); |
| 2539 | b = RDOP( cpustate ); |
| 2540 | RDOP( cpustate ); |
| 2524 | 2541 | WRMEM( a, b ); |
| 2525 | 2542 | } |
| 2526 | 2543 | |
| r18558 | r18559 | |
| 2975 | 2992 | { |
| 2976 | 2993 | cpustate->pc.d = RDMEML( cpustate->xssp.d ); |
| 2977 | 2994 | cpustate->xssp.d += 4; |
| 2995 | cpustate->prefetch_clear = true; |
| 2978 | 2996 | } |
| 2979 | 2997 | |
| 2980 | 2998 | |
| r18558 | r18559 | |
| 2985 | 3003 | cpustate->pc.d = RDMEML( cpustate->xssp.d ); |
| 2986 | 3004 | cpustate->xssp.d += 4; |
| 2987 | 3005 | cpustate->cycles += 6; |
| 3006 | cpustate->prefetch_clear = true; |
| 2988 | 3007 | } |
| 2989 | 3008 | } |
| 2990 | 3009 | |
| r18558 | r18559 | |
| 2993 | 3012 | { |
| 2994 | 3013 | cpustate->pc.d = RDMEML( cpustate->xssp.d ); |
| 2995 | 3014 | cpustate->xssp.d += 4 + cpustate->imm1.sw.l; |
| 3015 | cpustate->prefetch_clear = true; |
| 2996 | 3016 | } |
| 2997 | 3017 | |
| 2998 | 3018 | |
| r18558 | r18559 | |
| 3004 | 3024 | cpustate->xssp.d += 4; |
| 3005 | 3025 | cpustate->regbank = cpustate->sr.b.h & 0x03; |
| 3006 | 3026 | cpustate->check_irqs = 1; |
| 3027 | cpustate->prefetch_clear = true; |
| 3007 | 3028 | } |
| 3008 | 3029 | |
| 3009 | 3030 | |
| r18558 | r18559 | |
| 3683 | 3704 | cpustate->xssp.d -= 2; |
| 3684 | 3705 | WRMEMW( cpustate->xssp.d, cpustate->sr.w.l ); |
| 3685 | 3706 | cpustate->pc.d = RDMEML( 0x00ffff00 + 4 * cpustate->imm1.b.l ); |
| 3707 | cpustate->prefetch_clear = true; |
| 3686 | 3708 | } |
| 3687 | 3709 | |
| 3688 | 3710 | |
| r18558 | r18559 | |
| 3887 | 3909 | cpustate->p1_reg32 = get_reg32_current( cpustate, cpustate->op ); |
| 3888 | 3910 | break; |
| 3889 | 3911 | case _CR8: |
| 3890 | | cpustate->imm1.d = RDOP(); |
| 3912 | cpustate->imm1.d = RDOP( cpustate ); |
| 3891 | 3913 | switch( cpustate->imm1.d ) |
| 3892 | 3914 | { |
| 3893 | 3915 | case 0x22: |
| r18558 | r18559 | |
| 3908 | 3930 | } |
| 3909 | 3931 | break; |
| 3910 | 3932 | case _CR16: |
| 3911 | | cpustate->imm1.d = RDOP(); |
| 3933 | cpustate->imm1.d = RDOP( cpustate ); |
| 3912 | 3934 | switch( cpustate->imm1.d ) |
| 3913 | 3935 | { |
| 3914 | 3936 | case 0x20: |
| r18558 | r18559 | |
| 3929 | 3951 | } |
| 3930 | 3952 | break; |
| 3931 | 3953 | case _CR32: |
| 3932 | | cpustate->imm1.d = RDOP(); |
| 3954 | cpustate->imm1.d = RDOP( cpustate ); |
| 3933 | 3955 | switch( cpustate->imm1.d ) |
| 3934 | 3956 | { |
| 3935 | 3957 | case 0x00: |
| r18558 | r18559 | |
| 3962 | 3984 | } |
| 3963 | 3985 | break; |
| 3964 | 3986 | case _D8: |
| 3965 | | cpustate->ea1.d = RDOP(); |
| 3987 | cpustate->ea1.d = RDOP( cpustate ); |
| 3966 | 3988 | cpustate->ea1.d = cpustate->pc.d + cpustate->ea1.sb.l; |
| 3967 | 3989 | break; |
| 3968 | 3990 | case _D16: |
| 3969 | | cpustate->ea1.d = RDOP(); |
| 3970 | | cpustate->ea1.b.h = RDOP(); |
| 3991 | cpustate->ea1.d = RDOP( cpustate ); |
| 3992 | cpustate->ea1.b.h = RDOP( cpustate ); |
| 3971 | 3993 | cpustate->ea1.d = cpustate->pc.d + cpustate->ea1.sw.l; |
| 3972 | 3994 | break; |
| 3973 | 3995 | case _I3: |
| 3974 | 3996 | cpustate->imm1.d = cpustate->op & 0x07; |
| 3975 | 3997 | break; |
| 3976 | 3998 | case _I8: |
| 3977 | | cpustate->imm1.d = RDOP(); |
| 3999 | cpustate->imm1.d = RDOP( cpustate ); |
| 3978 | 4000 | break; |
| 3979 | 4001 | case _I16: |
| 3980 | | cpustate->imm1.d = RDOP(); |
| 3981 | | cpustate->imm1.b.h = RDOP(); |
| 4002 | cpustate->imm1.d = RDOP( cpustate ); |
| 4003 | cpustate->imm1.b.h = RDOP( cpustate ); |
| 3982 | 4004 | break; |
| 3983 | 4005 | case _I24: |
| 3984 | | cpustate->imm1.d = RDOP(); |
| 3985 | | cpustate->imm1.b.h = RDOP(); |
| 3986 | | cpustate->imm1.b.h2 = RDOP(); |
| 4006 | cpustate->imm1.d = RDOP( cpustate ); |
| 4007 | cpustate->imm1.b.h = RDOP( cpustate ); |
| 4008 | cpustate->imm1.b.h2 = RDOP( cpustate ); |
| 3987 | 4009 | break; |
| 3988 | 4010 | case _I32: |
| 3989 | | cpustate->imm1.d = RDOP(); |
| 3990 | | cpustate->imm1.b.h = RDOP(); |
| 3991 | | cpustate->imm1.b.h2 = RDOP(); |
| 3992 | | cpustate->imm1.b.h3 = RDOP(); |
| 4011 | cpustate->imm1.d = RDOP( cpustate ); |
| 4012 | cpustate->imm1.b.h = RDOP( cpustate ); |
| 4013 | cpustate->imm1.b.h2 = RDOP( cpustate ); |
| 4014 | cpustate->imm1.b.h3 = RDOP( cpustate ); |
| 3993 | 4015 | break; |
| 3994 | 4016 | case _M: |
| 3995 | 4017 | cpustate->ea1.d = cpustate->ea2.d; |
| 3996 | 4018 | break; |
| 3997 | 4019 | case _M8: |
| 3998 | | cpustate->ea1.d = RDOP(); |
| 4020 | cpustate->ea1.d = RDOP( cpustate ); |
| 3999 | 4021 | break; |
| 4000 | 4022 | case _M16: |
| 4001 | | cpustate->ea1.d = RDOP(); |
| 4002 | | cpustate->ea1.b.h = RDOP(); |
| 4023 | cpustate->ea1.d = RDOP( cpustate ); |
| 4024 | cpustate->ea1.b.h = RDOP( cpustate ); |
| 4003 | 4025 | break; |
| 4004 | 4026 | case _R: |
| 4005 | 4027 | cpustate->p1_reg8 = cpustate->p2_reg8; |
| r18558 | r18559 | |
| 4029 | 4051 | cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op ); |
| 4030 | 4052 | break; |
| 4031 | 4053 | case _CR8: |
| 4032 | | cpustate->imm1.d = RDOP(); |
| 4054 | cpustate->imm1.d = RDOP( cpustate ); |
| 4033 | 4055 | switch( cpustate->imm1.d ) |
| 4034 | 4056 | { |
| 4035 | 4057 | case 0x22: |
| r18558 | r18559 | |
| 4050 | 4072 | } |
| 4051 | 4073 | break; |
| 4052 | 4074 | case _CR16: |
| 4053 | | cpustate->imm1.d = RDOP(); |
| 4075 | cpustate->imm1.d = RDOP( cpustate ); |
| 4054 | 4076 | switch( cpustate->imm1.d ) |
| 4055 | 4077 | { |
| 4056 | 4078 | case 0x20: |
| r18558 | r18559 | |
| 4071 | 4093 | } |
| 4072 | 4094 | break; |
| 4073 | 4095 | case _CR32: |
| 4074 | | cpustate->imm1.d = RDOP(); |
| 4096 | cpustate->imm1.d = RDOP( cpustate ); |
| 4075 | 4097 | switch( cpustate->imm1.d ) |
| 4076 | 4098 | { |
| 4077 | 4099 | case 0x00: |
| r18558 | r18559 | |
| 4104 | 4126 | } |
| 4105 | 4127 | break; |
| 4106 | 4128 | case _D8: |
| 4107 | | cpustate->ea2.d = RDOP(); |
| 4129 | cpustate->ea2.d = RDOP( cpustate ); |
| 4108 | 4130 | cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sb.l; |
| 4109 | 4131 | break; |
| 4110 | 4132 | case _D16: |
| 4111 | | cpustate->ea2.d = RDOP(); |
| 4112 | | cpustate->ea2.b.h = RDOP(); |
| 4133 | cpustate->ea2.d = RDOP( cpustate ); |
| 4134 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 4113 | 4135 | cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l; |
| 4114 | 4136 | break; |
| 4115 | 4137 | case _I3: |
| 4116 | 4138 | cpustate->imm2.d = cpustate->op & 0x07; |
| 4117 | 4139 | break; |
| 4118 | 4140 | case _I8: |
| 4119 | | cpustate->imm2.d = RDOP(); |
| 4141 | cpustate->imm2.d = RDOP( cpustate ); |
| 4120 | 4142 | break; |
| 4121 | 4143 | case _I16: |
| 4122 | | cpustate->imm2.d = RDOP(); |
| 4123 | | cpustate->imm2.b.h = RDOP(); |
| 4144 | cpustate->imm2.d = RDOP( cpustate ); |
| 4145 | cpustate->imm2.b.h = RDOP( cpustate ); |
| 4124 | 4146 | break; |
| 4125 | 4147 | case _I32: |
| 4126 | | cpustate->imm2.d = RDOP(); |
| 4127 | | cpustate->imm2.b.h = RDOP(); |
| 4128 | | cpustate->imm2.b.h2 = RDOP(); |
| 4129 | | cpustate->imm2.b.h3 = RDOP(); |
| 4148 | cpustate->imm2.d = RDOP( cpustate ); |
| 4149 | cpustate->imm2.b.h = RDOP( cpustate ); |
| 4150 | cpustate->imm2.b.h2 = RDOP( cpustate ); |
| 4151 | cpustate->imm2.b.h3 = RDOP( cpustate ); |
| 4130 | 4152 | break; |
| 4131 | 4153 | case _M8: |
| 4132 | | cpustate->ea2.d = RDOP(); |
| 4154 | cpustate->ea2.d = RDOP( cpustate ); |
| 4133 | 4155 | break; |
| 4134 | 4156 | case _M16: |
| 4135 | | cpustate->ea2.d = RDOP(); |
| 4136 | | cpustate->ea2.b.h = RDOP(); |
| 4157 | cpustate->ea2.d = RDOP( cpustate ); |
| 4158 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 4137 | 4159 | break; |
| 4138 | 4160 | } |
| 4139 | 4161 | } |
| r18558 | r18559 | |
| 5325 | 5347 | cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op ); |
| 5326 | 5348 | |
| 5327 | 5349 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5328 | | cpustate->op = RDOP(); |
| 5350 | cpustate->op = RDOP( cpustate ); |
| 5329 | 5351 | inst = &mnemonic_80[cpustate->op]; |
| 5330 | 5352 | prepare_operands( cpustate, inst ); |
| 5331 | 5353 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5343 | 5365 | cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op ); |
| 5344 | 5366 | |
| 5345 | 5367 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5346 | | cpustate->op = RDOP(); |
| 5368 | cpustate->op = RDOP( cpustate ); |
| 5347 | 5369 | cpustate->ea2.d += (INT8)cpustate->op; |
| 5348 | 5370 | cpustate->cycles += 2; |
| 5349 | | cpustate->op = RDOP(); |
| 5371 | cpustate->op = RDOP( cpustate ); |
| 5350 | 5372 | inst = &mnemonic_80[cpustate->op]; |
| 5351 | 5373 | prepare_operands( cpustate, inst ); |
| 5352 | 5374 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5364 | 5386 | cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op ); |
| 5365 | 5387 | |
| 5366 | 5388 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5367 | | cpustate->op = RDOP(); |
| 5389 | cpustate->op = RDOP( cpustate ); |
| 5368 | 5390 | inst = &mnemonic_90[cpustate->op]; |
| 5369 | 5391 | prepare_operands( cpustate, inst ); |
| 5370 | 5392 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5378 | 5400 | const tlcs900inst *inst; |
| 5379 | 5401 | |
| 5380 | 5402 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5381 | | cpustate->op = RDOP(); |
| 5403 | cpustate->op = RDOP( cpustate ); |
| 5382 | 5404 | cpustate->ea2.d += (INT8)cpustate->op; |
| 5383 | 5405 | cpustate->cycles += 2; |
| 5384 | | cpustate->op = RDOP(); |
| 5406 | cpustate->op = RDOP( cpustate ); |
| 5385 | 5407 | inst = &mnemonic_98[cpustate->op]; |
| 5386 | 5408 | prepare_operands( cpustate, inst ); |
| 5387 | 5409 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5395 | 5417 | const tlcs900inst *inst; |
| 5396 | 5418 | |
| 5397 | 5419 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5398 | | cpustate->op = RDOP(); |
| 5420 | cpustate->op = RDOP( cpustate ); |
| 5399 | 5421 | inst = &mnemonic_a0[cpustate->op]; |
| 5400 | 5422 | prepare_operands( cpustate, inst ); |
| 5401 | 5423 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5409 | 5431 | const tlcs900inst *inst; |
| 5410 | 5432 | |
| 5411 | 5433 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5412 | | cpustate->op = RDOP(); |
| 5434 | cpustate->op = RDOP( cpustate ); |
| 5413 | 5435 | cpustate->ea2.d += (INT8)cpustate->op; |
| 5414 | 5436 | cpustate->cycles += 2; |
| 5415 | | cpustate->op = RDOP(); |
| 5437 | cpustate->op = RDOP( cpustate ); |
| 5416 | 5438 | inst = &mnemonic_a0[cpustate->op]; |
| 5417 | 5439 | prepare_operands( cpustate, inst ); |
| 5418 | 5440 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5426 | 5448 | const tlcs900inst *inst; |
| 5427 | 5449 | |
| 5428 | 5450 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5429 | | cpustate->op = RDOP(); |
| 5451 | cpustate->op = RDOP( cpustate ); |
| 5430 | 5452 | inst = &mnemonic_b0[cpustate->op]; |
| 5431 | 5453 | prepare_operands( cpustate, inst ); |
| 5432 | 5454 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5440 | 5462 | const tlcs900inst *inst; |
| 5441 | 5463 | |
| 5442 | 5464 | cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op ); |
| 5443 | | cpustate->op = RDOP(); |
| 5465 | cpustate->op = RDOP( cpustate ); |
| 5444 | 5466 | cpustate->ea2.d += (INT8)cpustate->op; |
| 5445 | 5467 | cpustate->cycles += 2; |
| 5446 | | cpustate->op = RDOP(); |
| 5468 | cpustate->op = RDOP( cpustate ); |
| 5447 | 5469 | inst = &mnemonic_b8[cpustate->op]; |
| 5448 | 5470 | prepare_operands( cpustate, inst ); |
| 5449 | 5471 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5460 | 5482 | switch ( cpustate->op & 0x07 ) |
| 5461 | 5483 | { |
| 5462 | 5484 | case 0x00: /* (n) */ |
| 5463 | | cpustate->ea2.d = RDOP(); |
| 5485 | cpustate->ea2.d = RDOP( cpustate ); |
| 5464 | 5486 | cpustate->cycles += 2; |
| 5465 | 5487 | break; |
| 5466 | 5488 | |
| 5467 | 5489 | case 0x01: /* (nn) */ |
| 5468 | | cpustate->ea2.d = RDOP(); |
| 5469 | | cpustate->ea2.b.h = RDOP(); |
| 5490 | cpustate->ea2.d = RDOP( cpustate ); |
| 5491 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5470 | 5492 | cpustate->cycles += 2; |
| 5471 | 5493 | break; |
| 5472 | 5494 | |
| 5473 | 5495 | case 0x02: /* (nnn) */ |
| 5474 | | cpustate->ea2.d = RDOP(); |
| 5475 | | cpustate->ea2.b.h = RDOP(); |
| 5476 | | cpustate->ea2.b.h2 = RDOP(); |
| 5496 | cpustate->ea2.d = RDOP( cpustate ); |
| 5497 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5498 | cpustate->ea2.b.h2 = RDOP( cpustate ); |
| 5477 | 5499 | cpustate->cycles += 3; |
| 5478 | 5500 | break; |
| 5479 | 5501 | |
| 5480 | 5502 | case 0x03: |
| 5481 | | cpustate->op = RDOP(); |
| 5503 | cpustate->op = RDOP( cpustate ); |
| 5482 | 5504 | switch ( cpustate->op & 0x03 ) |
| 5483 | 5505 | { |
| 5484 | 5506 | /* (xrr) */ |
| r18558 | r18559 | |
| 5489 | 5511 | |
| 5490 | 5512 | /* (xrr+d16) */ |
| 5491 | 5513 | case 0x01: |
| 5492 | | cpustate->ea2.b.l = RDOP(); |
| 5493 | | cpustate->ea2.b.h = RDOP(); |
| 5514 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5515 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5494 | 5516 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l; |
| 5495 | 5517 | cpustate->cycles += 5; |
| 5496 | 5518 | break; |
| r18558 | r18559 | |
| 5504 | 5526 | { |
| 5505 | 5527 | /* (xrr+r8) */ |
| 5506 | 5528 | case 0x03: |
| 5507 | | cpustate->op = RDOP(); |
| 5529 | cpustate->op = RDOP( cpustate ); |
| 5508 | 5530 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5509 | | cpustate->op = RDOP(); |
| 5531 | cpustate->op = RDOP( cpustate ); |
| 5510 | 5532 | cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op ); |
| 5511 | 5533 | cpustate->cycles += 8; |
| 5512 | 5534 | break; |
| 5513 | 5535 | |
| 5514 | 5536 | /* (xrr+r16) */ |
| 5515 | 5537 | case 0x07: |
| 5516 | | cpustate->op = RDOP(); |
| 5538 | cpustate->op = RDOP( cpustate ); |
| 5517 | 5539 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5518 | | cpustate->op = RDOP(); |
| 5540 | cpustate->op = RDOP( cpustate ); |
| 5519 | 5541 | cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op ); |
| 5520 | 5542 | cpustate->cycles += 8; |
| 5521 | 5543 | break; |
| 5522 | 5544 | |
| 5523 | 5545 | /* (pc+d16) */ |
| 5524 | 5546 | case 0x13: |
| 5525 | | cpustate->ea2.b.l = RDOP(); |
| 5526 | | cpustate->ea2.b.h = RDOP(); |
| 5547 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5548 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5527 | 5549 | cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l; |
| 5528 | 5550 | cpustate->cycles += 5; |
| 5529 | 5551 | break; |
| r18558 | r18559 | |
| 5532 | 5554 | break; |
| 5533 | 5555 | |
| 5534 | 5556 | case 0x04: /* (-xrr) */ |
| 5535 | | cpustate->op = RDOP(); |
| 5557 | cpustate->op = RDOP( cpustate ); |
| 5536 | 5558 | reg = get_reg32( cpustate, cpustate->op ); |
| 5537 | 5559 | *reg -= ( 1 << ( cpustate->op & 0x03 ) ); |
| 5538 | 5560 | cpustate->ea2.d = *reg; |
| r18558 | r18559 | |
| 5540 | 5562 | break; |
| 5541 | 5563 | |
| 5542 | 5564 | case 0x05: /* (xrr+) */ |
| 5543 | | cpustate->op = RDOP(); |
| 5565 | cpustate->op = RDOP( cpustate ); |
| 5544 | 5566 | reg = get_reg32( cpustate, cpustate->op ); |
| 5545 | 5567 | cpustate->ea2.d = *reg; |
| 5546 | 5568 | *reg += ( 1 << ( cpustate->op & 0x03 ) ); |
| 5547 | 5569 | cpustate->cycles += 3; |
| 5548 | 5570 | break; |
| 5549 | 5571 | } |
| 5550 | | cpustate->op = RDOP(); |
| 5572 | cpustate->op = RDOP( cpustate ); |
| 5551 | 5573 | inst = &mnemonic_c0[cpustate->op]; |
| 5552 | 5574 | prepare_operands( cpustate, inst ); |
| 5553 | 5575 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5567 | 5589 | } |
| 5568 | 5590 | else |
| 5569 | 5591 | { |
| 5570 | | cpustate->op = RDOP(); |
| 5592 | cpustate->op = RDOP( cpustate ); |
| 5571 | 5593 | cpustate->p2_reg8 = get_reg8( cpustate, cpustate->op ); |
| 5572 | 5594 | /* For MUL and DIV operations */ |
| 5573 | 5595 | cpustate->p2_reg16 = get_reg16( cpustate, cpustate->op ); |
| 5574 | 5596 | } |
| 5575 | | cpustate->op = RDOP(); |
| 5597 | cpustate->op = RDOP( cpustate ); |
| 5576 | 5598 | inst = &mnemonic_c8[cpustate->op]; |
| 5577 | 5599 | prepare_operands( cpustate, inst ); |
| 5578 | 5600 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5589 | 5611 | switch ( cpustate->op & 0x07 ) |
| 5590 | 5612 | { |
| 5591 | 5613 | case 0x00: /* (n) */ |
| 5592 | | cpustate->ea2.d = RDOP(); |
| 5614 | cpustate->ea2.d = RDOP( cpustate ); |
| 5593 | 5615 | cpustate->cycles += 2; |
| 5594 | 5616 | break; |
| 5595 | 5617 | |
| 5596 | 5618 | case 0x01: /* (nn) */ |
| 5597 | | cpustate->ea2.d = RDOP(); |
| 5598 | | cpustate->ea2.b.h = RDOP(); |
| 5619 | cpustate->ea2.d = RDOP( cpustate ); |
| 5620 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5599 | 5621 | cpustate->cycles += 2; |
| 5600 | 5622 | break; |
| 5601 | 5623 | |
| 5602 | 5624 | case 0x02: /* (nnn) */ |
| 5603 | | cpustate->ea2.d = RDOP(); |
| 5604 | | cpustate->ea2.b.h = RDOP(); |
| 5605 | | cpustate->ea2.b.h2 = RDOP(); |
| 5625 | cpustate->ea2.d = RDOP( cpustate ); |
| 5626 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5627 | cpustate->ea2.b.h2 = RDOP( cpustate ); |
| 5606 | 5628 | cpustate->cycles += 3; |
| 5607 | 5629 | break; |
| 5608 | 5630 | |
| 5609 | 5631 | case 0x03: |
| 5610 | | cpustate->op = RDOP(); |
| 5632 | cpustate->op = RDOP( cpustate ); |
| 5611 | 5633 | switch ( cpustate->op & 0x03 ) |
| 5612 | 5634 | { |
| 5613 | 5635 | /* (xrr) */ |
| r18558 | r18559 | |
| 5618 | 5640 | |
| 5619 | 5641 | /* (xrr+d16) */ |
| 5620 | 5642 | case 0x01: |
| 5621 | | cpustate->ea2.b.l = RDOP(); |
| 5622 | | cpustate->ea2.b.h = RDOP(); |
| 5643 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5644 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5623 | 5645 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l; |
| 5624 | 5646 | cpustate->cycles += 5; |
| 5625 | 5647 | break; |
| r18558 | r18559 | |
| 5633 | 5655 | { |
| 5634 | 5656 | /* (xrr+r8) */ |
| 5635 | 5657 | case 0x03: |
| 5636 | | cpustate->op = RDOP(); |
| 5658 | cpustate->op = RDOP( cpustate ); |
| 5637 | 5659 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5638 | | cpustate->op = RDOP(); |
| 5660 | cpustate->op = RDOP( cpustate ); |
| 5639 | 5661 | cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op ); |
| 5640 | 5662 | cpustate->cycles += 8; |
| 5641 | 5663 | break; |
| 5642 | 5664 | |
| 5643 | 5665 | /* (xrr+r16) */ |
| 5644 | 5666 | case 0x07: |
| 5645 | | cpustate->op = RDOP(); |
| 5667 | cpustate->op = RDOP( cpustate ); |
| 5646 | 5668 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5647 | | cpustate->op = RDOP(); |
| 5669 | cpustate->op = RDOP( cpustate ); |
| 5648 | 5670 | cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op ); |
| 5649 | 5671 | cpustate->cycles += 8; |
| 5650 | 5672 | break; |
| 5651 | 5673 | |
| 5652 | 5674 | /* (pc+d16) */ |
| 5653 | 5675 | case 0x13: |
| 5654 | | cpustate->ea2.b.l = RDOP(); |
| 5655 | | cpustate->ea2.b.h = RDOP(); |
| 5676 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5677 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5656 | 5678 | cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l; |
| 5657 | 5679 | cpustate->cycles += 5; |
| 5658 | 5680 | break; |
| r18558 | r18559 | |
| 5661 | 5683 | break; |
| 5662 | 5684 | |
| 5663 | 5685 | case 0x04: /* (-xrr) */ |
| 5664 | | cpustate->op = RDOP(); |
| 5686 | cpustate->op = RDOP( cpustate ); |
| 5665 | 5687 | reg = get_reg32( cpustate, cpustate->op ); |
| 5666 | 5688 | *reg -= ( 1 << ( cpustate->op & 0x03 ) ); |
| 5667 | 5689 | cpustate->ea2.d = *reg; |
| r18558 | r18559 | |
| 5669 | 5691 | break; |
| 5670 | 5692 | |
| 5671 | 5693 | case 0x05: /* (xrr+) */ |
| 5672 | | cpustate->op = RDOP(); |
| 5694 | cpustate->op = RDOP( cpustate ); |
| 5673 | 5695 | reg = get_reg32( cpustate, cpustate->op ); |
| 5674 | 5696 | cpustate->ea2.d = *reg; |
| 5675 | 5697 | *reg += ( 1 << ( cpustate->op & 0x03 ) ); |
| 5676 | 5698 | cpustate->cycles += 3; |
| 5677 | 5699 | break; |
| 5678 | 5700 | } |
| 5679 | | cpustate->op = RDOP(); |
| 5701 | cpustate->op = RDOP( cpustate ); |
| 5680 | 5702 | inst = &mnemonic_d0[cpustate->op]; |
| 5681 | 5703 | prepare_operands( cpustate, inst ); |
| 5682 | 5704 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5695 | 5717 | } |
| 5696 | 5718 | else |
| 5697 | 5719 | { |
| 5698 | | cpustate->op = RDOP(); |
| 5720 | cpustate->op = RDOP( cpustate ); |
| 5699 | 5721 | cpustate->p2_reg16 = get_reg16( cpustate, cpustate->op ); |
| 5700 | 5722 | cpustate->p2_reg32 = get_reg32( cpustate, cpustate->op ); |
| 5701 | 5723 | } |
| 5702 | | cpustate->op = RDOP(); |
| 5724 | cpustate->op = RDOP( cpustate ); |
| 5703 | 5725 | inst = &mnemonic_d8[cpustate->op]; |
| 5704 | 5726 | prepare_operands( cpustate, inst ); |
| 5705 | 5727 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5716 | 5738 | switch ( cpustate->op & 0x07 ) |
| 5717 | 5739 | { |
| 5718 | 5740 | case 0x00: /* (n) */ |
| 5719 | | cpustate->ea2.d = RDOP(); |
| 5741 | cpustate->ea2.d = RDOP( cpustate ); |
| 5720 | 5742 | cpustate->cycles += 2; |
| 5721 | 5743 | break; |
| 5722 | 5744 | |
| 5723 | 5745 | case 0x01: /* (nn) */ |
| 5724 | | cpustate->ea2.d = RDOP(); |
| 5725 | | cpustate->ea2.b.h = RDOP(); |
| 5746 | cpustate->ea2.d = RDOP( cpustate ); |
| 5747 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5726 | 5748 | cpustate->cycles += 2; |
| 5727 | 5749 | break; |
| 5728 | 5750 | |
| 5729 | 5751 | case 0x02: /* (nnn) */ |
| 5730 | | cpustate->ea2.d = RDOP(); |
| 5731 | | cpustate->ea2.b.h = RDOP(); |
| 5732 | | cpustate->ea2.b.h2 = RDOP(); |
| 5752 | cpustate->ea2.d = RDOP( cpustate ); |
| 5753 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5754 | cpustate->ea2.b.h2 = RDOP( cpustate ); |
| 5733 | 5755 | cpustate->cycles += 3; |
| 5734 | 5756 | break; |
| 5735 | 5757 | |
| 5736 | 5758 | case 0x03: |
| 5737 | | cpustate->op = RDOP(); |
| 5759 | cpustate->op = RDOP( cpustate ); |
| 5738 | 5760 | switch ( cpustate->op & 0x03 ) |
| 5739 | 5761 | { |
| 5740 | 5762 | /* (xrr) */ |
| r18558 | r18559 | |
| 5745 | 5767 | |
| 5746 | 5768 | /* (xrr+d16) */ |
| 5747 | 5769 | case 0x01: |
| 5748 | | cpustate->ea2.b.l = RDOP(); |
| 5749 | | cpustate->ea2.b.h = RDOP(); |
| 5770 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5771 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5750 | 5772 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l; |
| 5751 | 5773 | cpustate->cycles += 5; |
| 5752 | 5774 | break; |
| r18558 | r18559 | |
| 5760 | 5782 | { |
| 5761 | 5783 | /* (xrr+r8) */ |
| 5762 | 5784 | case 0x03: |
| 5763 | | cpustate->op = RDOP(); |
| 5785 | cpustate->op = RDOP( cpustate ); |
| 5764 | 5786 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5765 | | cpustate->op = RDOP(); |
| 5787 | cpustate->op = RDOP( cpustate ); |
| 5766 | 5788 | cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op ); |
| 5767 | 5789 | cpustate->cycles += 8; |
| 5768 | 5790 | break; |
| 5769 | 5791 | |
| 5770 | 5792 | /* (xrr+r16) */ |
| 5771 | 5793 | case 0x07: |
| 5772 | | cpustate->op = RDOP(); |
| 5794 | cpustate->op = RDOP( cpustate ); |
| 5773 | 5795 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5774 | | cpustate->op = RDOP(); |
| 5796 | cpustate->op = RDOP( cpustate ); |
| 5775 | 5797 | cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op ); |
| 5776 | 5798 | cpustate->cycles += 8; |
| 5777 | 5799 | break; |
| 5778 | 5800 | |
| 5779 | 5801 | /* (pc+d16) */ |
| 5780 | 5802 | case 0x13: |
| 5781 | | cpustate->ea2.b.l = RDOP(); |
| 5782 | | cpustate->ea2.b.h = RDOP(); |
| 5803 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5804 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5783 | 5805 | cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l; |
| 5784 | 5806 | cpustate->cycles += 5; |
| 5785 | 5807 | break; |
| r18558 | r18559 | |
| 5788 | 5810 | break; |
| 5789 | 5811 | |
| 5790 | 5812 | case 0x04: /* (-xrr) */ |
| 5791 | | cpustate->op = RDOP(); |
| 5813 | cpustate->op = RDOP( cpustate ); |
| 5792 | 5814 | reg = get_reg32( cpustate, cpustate->op ); |
| 5793 | 5815 | *reg -= ( 1 << ( cpustate->op & 0x03 ) ); |
| 5794 | 5816 | cpustate->ea2.d = *reg; |
| r18558 | r18559 | |
| 5796 | 5818 | break; |
| 5797 | 5819 | |
| 5798 | 5820 | case 0x05: /* (xrr+) */ |
| 5799 | | cpustate->op = RDOP(); |
| 5821 | cpustate->op = RDOP( cpustate ); |
| 5800 | 5822 | reg = get_reg32( cpustate, cpustate->op ); |
| 5801 | 5823 | cpustate->ea2.d = *reg; |
| 5802 | 5824 | *reg += ( 1 << ( cpustate->op & 0x03 ) ); |
| 5803 | 5825 | cpustate->cycles += 3; |
| 5804 | 5826 | break; |
| 5805 | 5827 | } |
| 5806 | | cpustate->op = RDOP(); |
| 5828 | cpustate->op = RDOP( cpustate ); |
| 5807 | 5829 | inst = &mnemonic_e0[cpustate->op]; |
| 5808 | 5830 | prepare_operands( cpustate, inst ); |
| 5809 | 5831 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5821 | 5843 | } |
| 5822 | 5844 | else |
| 5823 | 5845 | { |
| 5824 | | cpustate->op = RDOP(); |
| 5846 | cpustate->op = RDOP( cpustate ); |
| 5825 | 5847 | cpustate->p2_reg32 = get_reg32( cpustate, cpustate->op ); |
| 5826 | 5848 | } |
| 5827 | | cpustate->op = RDOP(); |
| 5849 | cpustate->op = RDOP( cpustate ); |
| 5828 | 5850 | inst = &mnemonic_e8[cpustate->op]; |
| 5829 | 5851 | prepare_operands( cpustate, inst ); |
| 5830 | 5852 | inst->opfunc( cpustate ); |
| r18558 | r18559 | |
| 5841 | 5863 | switch ( cpustate->op & 0x07 ) |
| 5842 | 5864 | { |
| 5843 | 5865 | case 0x00: /* (n) */ |
| 5844 | | cpustate->ea2.d = RDOP(); |
| 5866 | cpustate->ea2.d = RDOP( cpustate ); |
| 5845 | 5867 | cpustate->cycles += 2; |
| 5846 | 5868 | break; |
| 5847 | 5869 | |
| 5848 | 5870 | case 0x01: /* (nn) */ |
| 5849 | | cpustate->ea2.d = RDOP(); |
| 5850 | | cpustate->ea2.b.h = RDOP(); |
| 5871 | cpustate->ea2.d = RDOP( cpustate ); |
| 5872 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5851 | 5873 | cpustate->cycles += 2; |
| 5852 | 5874 | break; |
| 5853 | 5875 | |
| 5854 | 5876 | case 0x02: /* (nnn) */ |
| 5855 | | cpustate->ea2.d = RDOP(); |
| 5856 | | cpustate->ea2.b.h = RDOP(); |
| 5857 | | cpustate->ea2.b.h2 = RDOP(); |
| 5877 | cpustate->ea2.d = RDOP( cpustate ); |
| 5878 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5879 | cpustate->ea2.b.h2 = RDOP( cpustate ); |
| 5858 | 5880 | cpustate->cycles += 3; |
| 5859 | 5881 | break; |
| 5860 | 5882 | |
| 5861 | 5883 | case 0x03: |
| 5862 | | cpustate->op = RDOP(); |
| 5884 | cpustate->op = RDOP( cpustate ); |
| 5863 | 5885 | switch ( cpustate->op & 0x03 ) |
| 5864 | 5886 | { |
| 5865 | 5887 | /* (xrr) */ |
| r18558 | r18559 | |
| 5870 | 5892 | |
| 5871 | 5893 | /* (xrr+d16) */ |
| 5872 | 5894 | case 0x01: |
| 5873 | | cpustate->ea2.b.l = RDOP(); |
| 5874 | | cpustate->ea2.b.h = RDOP(); |
| 5895 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5896 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5875 | 5897 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l; |
| 5876 | 5898 | cpustate->cycles += 5; |
| 5877 | 5899 | break; |
| r18558 | r18559 | |
| 5885 | 5907 | { |
| 5886 | 5908 | /* (xrr+r8) */ |
| 5887 | 5909 | case 0x03: |
| 5888 | | cpustate->op = RDOP(); |
| 5910 | cpustate->op = RDOP( cpustate ); |
| 5889 | 5911 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5890 | | cpustate->op = RDOP(); |
| 5912 | cpustate->op = RDOP( cpustate ); |
| 5891 | 5913 | cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op ); |
| 5892 | 5914 | cpustate->cycles += 8; |
| 5893 | 5915 | break; |
| 5894 | 5916 | |
| 5895 | 5917 | /* (xrr+r16) */ |
| 5896 | 5918 | case 0x07: |
| 5897 | | cpustate->op = RDOP(); |
| 5919 | cpustate->op = RDOP( cpustate ); |
| 5898 | 5920 | cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ); |
| 5899 | | cpustate->op = RDOP(); |
| 5921 | cpustate->op = RDOP( cpustate ); |
| 5900 | 5922 | cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op ); |
| 5901 | 5923 | cpustate->cycles += 8; |
| 5902 | 5924 | break; |
| 5903 | 5925 | |
| 5904 | 5926 | /* (pc+d16) */ |
| 5905 | 5927 | case 0x13: |
| 5906 | | cpustate->ea2.b.l = RDOP(); |
| 5907 | | cpustate->ea2.b.h = RDOP(); |
| 5928 | cpustate->ea2.b.l = RDOP( cpustate ); |
| 5929 | cpustate->ea2.b.h = RDOP( cpustate ); |
| 5908 | 5930 | cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l; |
| 5909 | 5931 | cpustate->cycles += 5; |
| 5910 | 5932 | break; |
| r18558 | r18559 | |
| 5913 | 5935 | break; |
| 5914 | 5936 | |
| 5915 | 5937 | case 0x04: /* (-xrr) */ |
| 5916 | | cpustate->op = RDOP(); |
| 5938 | cpustate->op = RDOP( cpustate ); |
| 5917 | 5939 | reg = get_reg32( cpustate, cpustate->op ); |
| 5918 | 5940 | *reg -= ( 1 << ( cpustate->op & 0x03 ) ); |
| 5919 | 5941 | cpustate->ea2.d = *reg; |
| r18558 | r18559 | |
| 5921 | 5943 | break; |
| 5922 | 5944 | |
| 5923 | 5945 | case 0x05: /* (xrr+) */ |
| 5924 | | cpustate->op = RDOP(); |
| 5946 | cpustate->op = RDOP( cpustate ); |
| 5925 | 5947 | reg = get_reg32( cpustate, cpustate->op ); |
| 5926 | 5948 | cpustate->ea2.d = *reg; |
| 5927 | 5949 | *reg += ( 1 << ( cpustate->op & 0x03 ) ); |
| r18558 | r18559 | |
| 5929 | 5951 | break; |
| 5930 | 5952 | } |
| 5931 | 5953 | |
| 5932 | | cpustate->op = RDOP(); |
| 5954 | cpustate->op = RDOP( cpustate ); |
| 5933 | 5955 | inst = &mnemonic_f0[cpustate->op]; |
| 5934 | 5956 | prepare_operands( cpustate, inst ); |
| 5935 | 5957 | inst->opfunc( cpustate ); |