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r18553 Tuesday 16th October, 2012 at 07:51:10 UTC by Miodrag Milanović
updated i8243 to use devcb2 and remove trampolines (no whatsnew)

[src/emu/machine]	i8243.c i8243.h
[src/mame/audio]	segag80r.c
[src/mame/drivers]	othello.c segas16a.c
[src/mame/includes]	segas16a.h
[src/mess/drivers]	fidelz80.c
[src/mess/includes]	fidelz80.h

trunk/src/mame/includes/segas16a.h

r18552	r18553
91	91	DECLARE_WRITE8_MEMBER( n7751_command_w );
92	92	DECLARE_WRITE8_MEMBER( n7751_control_w );
93	93	DECLARE_WRITE8_MEMBER( n7751_rom_offset_w );
94		static DECLARE_WRITE8_DEVICE_HANDLER( static_n7751_rom_offset_w );
95	94
96	95	// N7751 sound generator CPU read/write handlers
97	96	DECLARE_READ8_MEMBER( n7751_rom_r );

trunk/src/mame/drivers/othello.c

r18552	r18553
90	90	DECLARE_READ8_MEMBER(n7751_command_r);
91	91	DECLARE_READ8_MEMBER(n7751_t1_r);
92	92	DECLARE_WRITE8_MEMBER(n7751_p2_w);
	93	DECLARE_WRITE8_MEMBER(n7751_rom_control_w);
93	94	virtual void machine_start();
94	95	virtual void machine_reset();
95	96	virtual void palette_init();
r18552	r18553
250	251	AM_RANGE(0x08, 0x08) AM_WRITE(ay_select_w)
251	252	ADDRESS_MAP_END
252	253
253		static WRITE8_DEVICE_HANDLER( n7751_rom_control_w )
	254	WRITE8_MEMBER(othello_state::n7751_rom_control_w)
254	255	{
255		othello_state *state = space.machine().driver_data<othello_state>();
256
257	256	/* P4 - address lines 0-3 */
258	257	/* P5 - address lines 4-7 */
259	258	/* P6 - address lines 8-11 */
r18552	r18553
261	260	switch (offset)
262	261	{
263	262	case 0:
264		state->m_sound_addr = (state->m_sound_addr & ~0x00f) | ((data & 0x0f) << 0);
	263	m_sound_addr = (m_sound_addr & ~0x00f) | ((data & 0x0f) << 0);
265	264	break;
266	265
267	266	case 1:
268		state->m_sound_addr = (state->m_sound_addr & ~0x0f0) | ((data & 0x0f) << 4);
	267	m_sound_addr = (m_sound_addr & ~0x0f0) | ((data & 0x0f) << 4);
269	268	break;
270	269
271	270	case 2:
272		state->m_sound_addr = (state->m_sound_addr & ~0xf00) | ((data & 0x0f) << 8);
	271	m_sound_addr = (m_sound_addr & ~0xf00) | ((data & 0x0f) << 8);
273	272	break;
274	273
275	274	case 3:
276		state->m_sound_addr &= 0xfff;
	275	m_sound_addr &= 0xfff;
277	276	{
278	277
279		if (!BIT(data, 0)) state->m_sound_addr |= 0x0000;
280		if (!BIT(data, 1)) state->m_sound_addr |= 0x1000;
281		if (!BIT(data, 2)) state->m_sound_addr |= 0x2000;
282		if (!BIT(data, 3)) state->m_sound_addr |= 0x3000;
	278	if (!BIT(data, 0)) m_sound_addr |= 0x0000;
	279	if (!BIT(data, 1)) m_sound_addr |= 0x1000;
	280	if (!BIT(data, 2)) m_sound_addr |= 0x2000;
	281	if (!BIT(data, 3)) m_sound_addr |= 0x3000;
283	282	}
284	283	break;
285	284	}
r18552	r18553
297	296
298	297	WRITE8_MEMBER(othello_state::n7751_p2_w)
299	298	{
300		device_t *device = machine().device("n7751_8243");
	299	i8243_device *device = machine().device<i8243_device>("n7751_8243");
301	300
302	301	/* write to P2; low 4 bits go to 8243 */
303		i8243_p2_w(device, space, offset, data & 0x0f);
	302	device->i8243_p2_w(space, offset, data & 0x0f);
304	303
305	304	/* output of bit $80 indicates we are ready (1) or busy (0) */
306	305	/* no other outputs are used */
r18552	r18553
319	318	AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READ(n7751_rom_r)
320	319	AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1) AM_DEVWRITE("dac", dac_device, write_unsigned8)
321	320	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_WRITE(n7751_p2_w)
322		AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE_LEGACY("n7751_8243", i8243_prog_w)
	321	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("n7751_8243", i8243_device, i8243_prog_w)
323	322	ADDRESS_MAP_END
324	323
325	324	static INPUT_PORTS_START( othello )
r18552	r18553
426	425	MCFG_CPU_ADD("n7751", N7751, XTAL_6MHz)
427	426	MCFG_CPU_IO_MAP(n7751_portmap)
428	427
429		MCFG_I8243_ADD("n7751_8243", NULL, n7751_rom_control_w)
	428	MCFG_I8243_ADD("n7751_8243", NOOP, WRITE8(othello_state,n7751_rom_control_w))
430	429
431	430
432	431	/* video hardware */

trunk/src/mame/drivers/segas16a.c

r18552	r18553
424	424	m_n7751_rom_address = (m_n7751_rom_address & ~mask) | newdata;
425	425	}
426	426
427		WRITE8_DEVICE_HANDLER( segas16a_state::static_n7751_rom_offset_w )
428		{
429		segas16a_state *state = space.machine().driver_data<segas16a_state>();
430		state->n7751_rom_offset_w(state->m_maincpu->space(AS_PROGRAM), offset, data);
431		}
432
433
434
435	427	//**************************************************************************
436	428	//  N7751 SOUND GENERATOR CPU READ/WRITE HANDLERS
437	429	//**************************************************************************
r18552	r18553
455	447	{
456	448	// read from P2 - 8255's PC0-2 connects to 7751's S0-2 (P24-P26 on an 8048)
457	449	// bit 0x80 is an alternate way to control the sample on/off; doesn't appear to be used
458		return 0x80 | ((m_n7751_command & 0x07) << 4) | (i8243_p2_r(m_n7751_i8243, space, offset) & 0x0f);
	450	return 0x80 | ((m_n7751_command & 0x07) << 4) | (m_n7751_i8243->i8243_p2_r(space, offset) & 0x0f);
459	451	}
460	452
461	453
r18552	r18553
466	458	WRITE8_MEMBER( segas16a_state::n7751_p2_w )
467	459	{
468	460	// write to P2; low 4 bits go to 8243
469		i8243_p2_w(m_n7751_i8243, space, offset, data & 0x0f);
	461	m_n7751_i8243->i8243_p2_w(space, offset, data & 0x0f);
470	462
471	463	// output of bit $80 indicates we are ready (1) or busy (0)
472	464	// no other outputs are used
r18552	r18553
1046	1038	AM_RANGE(MCS48_PORT_T1,   MCS48_PORT_T1)   AM_READ(n7751_t1_r)
1047	1039	AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1)   AM_DEVWRITE("dac", dac_device, write_unsigned8)
1048	1040	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2)   AM_READWRITE(n7751_p2_r, n7751_p2_w)
1049		AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE_LEGACY("n7751_8243", i8243_prog_w)
	1041	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("n7751_8243", i8243_device, i8243_prog_w)
1050	1042	ADDRESS_MAP_END
1051	1043
1052	1044
r18552	r18553
1944	1936	MCFG_CPU_ADD("n7751", N7751, 6000000)
1945	1937	MCFG_CPU_IO_MAP(n7751_portmap)
1946	1938
1947		MCFG_I8243_ADD("n7751_8243", NULL, segas16a_state::static_n7751_rom_offset_w)
	1939	MCFG_I8243_ADD("n7751_8243", NOOP, WRITE8(segas16a_state,n7751_rom_offset_w))
1948	1940
1949	1941	MCFG_NVRAM_ADD_0FILL("nvram")
1950	1942

trunk/src/mame/audio/segag80r.c

r18552	r18553
780	780
781	781	static SOUND_START( monsterb );
782	782
783		static DECLARE_WRITE8_DEVICE_HANDLER( n7751_rom_control_w );
784
785	783	/*
786	784	Monster Bash
787	785
r18552	r18553
829	827	AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READ(n7751_rom_r)
830	828	AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1) AM_DEVWRITE("dac", dac_device, write_unsigned8)
831	829	AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_WRITE(n7751_p2_w)
832		AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE_LEGACY("audio_8243", i8243_prog_w)
	830	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("audio_8243", i8243_device, i8243_prog_w)
833	831	ADDRESS_MAP_END
834	832
835	833
r18552	r18553
859	857	MCFG_CPU_ADD("audiocpu", N7751, 6000000)
860	858	MCFG_CPU_IO_MAP(monsterb_7751_portmap)
861	859
862		MCFG_I8243_ADD("audio_8243", NULL, n7751_rom_control_w)
	860	MCFG_I8243_ADD("audio_8243", NOOP, WRITE8(segag80r_state,n7751_rom_control_w))
863	861
864	862	/* sound hardware */
865	863	MCFG_SOUND_START(monsterb)
r18552	r18553
964	962	}
965	963
966	964
967		static WRITE8_DEVICE_HANDLER( n7751_rom_control_w )
	965	WRITE8_MEMBER(segag80r_state::n7751_rom_control_w)
968	966	{
969		segag80r_state *state = space.machine().driver_data<segag80r_state>();
970	967	/* P4 - address lines 0-3 */
971	968	/* P5 - address lines 4-7 */
972	969	/* P6 - address lines 8-11 */
r18552	r18553
974	971	switch (offset)
975	972	{
976	973	case 0:
977		state->m_sound_addr = (state->m_sound_addr & ~0x00f) | ((data & 0x0f) << 0);
	974	m_sound_addr = (m_sound_addr & ~0x00f) | ((data & 0x0f) << 0);
978	975	break;
979	976
980	977	case 1:
981		state->m_sound_addr = (state->m_sound_addr & ~0x0f0) | ((data & 0x0f) << 4);
	978	m_sound_addr = (m_sound_addr & ~0x0f0) | ((data & 0x0f) << 4);
982	979	break;
983	980
984	981	case 2:
985		state->m_sound_addr = (state->m_sound_addr & ~0xf00) | ((data & 0x0f) << 8);
	982	m_sound_addr = (m_sound_addr & ~0xf00) | ((data & 0x0f) << 8);
986	983	break;
987	984
988	985	case 3:
989		state->m_sound_addr &= 0xfff;
	986	m_sound_addr &= 0xfff;
990	987	{
991		int numroms = state->memregion("n7751")->bytes() / 0x1000;
992		if (!(data & 0x01) && numroms >= 1) state->m_sound_addr |= 0x0000;
993		if (!(data & 0x02) && numroms >= 2) state->m_sound_addr |= 0x1000;
994		if (!(data & 0x04) && numroms >= 3) state->m_sound_addr |= 0x2000;
995		if (!(data & 0x08) && numroms >= 4) state->m_sound_addr |= 0x3000;
	988	int numroms = memregion("n7751")->bytes() / 0x1000;
	989	if (!(data & 0x01) && numroms >= 1) m_sound_addr |= 0x0000;
	990	if (!(data & 0x02) && numroms >= 2) m_sound_addr |= 0x1000;
	991	if (!(data & 0x04) && numroms >= 3) m_sound_addr |= 0x2000;
	992	if (!(data & 0x08) && numroms >= 4) m_sound_addr |= 0x3000;
996	993	}
997	994	break;
998	995	}
r18552	r18553
1016	1013
1017	1014	WRITE8_MEMBER(segag80r_state::n7751_p2_w)
1018	1015	{
1019		device_t *device = machine().device("audio_8243");
	1016	i8243_device *device = machine().device<i8243_device>("audio_8243");
1020	1017	/* write to P2; low 4 bits go to 8243 */
1021		i8243_p2_w(device, space, offset, data & 0x0f);
	1018	device->i8243_p2_w(space, offset, data & 0x0f);
1022	1019
1023	1020	/* output of bit $80 indicates we are ready (1) or busy (0) */
1024	1021	/* no other outputs are used */

trunk/src/emu/machine/i8243.c

r18552	r18553
24	24	//-------------------------------------------------
25	25
26	26	i8243_device::i8243_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
27		: device_t(mconfig, I8243, "I8243", tag, owner, clock)
	27	: device_t(mconfig, I8243, "I8243", tag, owner, clock),
	28	m_readhandler(*this),
	29	m_writehandler(*this)
28	30	{
29
30	31	}
31	32
32
33	33	//-------------------------------------------------
34		//  static_set_read_handler - configuration helper
35		//  to set the read handler
36		//-------------------------------------------------
37
38		void i8243_device::static_set_read_handler(device_t &device, read8_device_func callback)
39		{
40		i8243_device &i8243 = downcast<i8243_device &>(device);
41		if(callback != NULL)
42		{
43		i8243.m_readhandler_cb.type = DEVCB_TYPE_DEVICE;
44		i8243.m_readhandler_cb.index = 0;
45		i8243.m_readhandler_cb.tag = "";
46		i8243.m_readhandler_cb.readdevice = callback;
47		}
48		else
49		{
50		i8243.m_readhandler_cb.type = DEVCB_TYPE_NULL;
51		}
52		}
53
54
55		//-------------------------------------------------
56		//  static_set_write_handler - configuration helper
57		//  to set the write handler
58		//-------------------------------------------------
59
60		void i8243_device::static_set_write_handler(device_t &device, write8_device_func callback)
61		{
62		i8243_device &i8243 = downcast<i8243_device &>(device);
63		if(callback != NULL)
64		{
65		i8243.m_writehandler_cb.type = DEVCB_TYPE_DEVICE;
66		i8243.m_writehandler_cb.index = 0;
67		i8243.m_writehandler_cb.tag = "";
68		i8243.m_writehandler_cb.writedevice = callback;
69		}
70		else
71		{
72		i8243.m_writehandler_cb.type = DEVCB_TYPE_NULL;
73		}
74		}
75
76
77		//-------------------------------------------------
78	34	//  device_start - device-specific startup
79	35	//-------------------------------------------------
80	36
81	37	void i8243_device::device_start()
82	38	{
83		m_readhandler.resolve(m_readhandler_cb, *this);
84		m_writehandler.resolve(m_writehandler_cb, *this);
	39	m_readhandler.resolve_safe(0);
	40	m_writehandler.resolve_safe();
85	41	}
86	42
87	43
r18552	r18553
101	57	i8243_p2_r - handle a read from port 2
102	58	-------------------------------------------------*/
103	59
104		READ8_DEVICE_HANDLER_TRAMPOLINE(i8243, i8243_p2_r)
	60	READ8_MEMBER(i8243_device::i8243_p2_r)
105	61	{
106	62	return m_p2out;
107	63	}
r18552	r18553
111	67	i8243_p2_r - handle a write to port 2
112	68	-------------------------------------------------*/
113	69
114		WRITE8_DEVICE_HANDLER_TRAMPOLINE(i8243, i8243_p2_w)
	70	WRITE8_MEMBER(i8243_device::i8243_p2_w)
115	71	{
116	72	m_p2 = data & 0x0f;
117	73	}
r18552	r18553
122	78	line state
123	79	-------------------------------------------------*/
124	80
125		WRITE8_DEVICE_HANDLER_TRAMPOLINE(i8243, i8243_prog_w)
	81	WRITE8_MEMBER(i8243_device::i8243_prog_w)
126	82	{
127	83	/* only care about low bit */
128	84	data &= 1;
r18552	r18553
150	106	{
151	107	case MCS48_EXPANDER_OP_WRITE:
152	108	m_p[m_opcode & 3] = m_p2 & 0x0f;
153		m_writehandler(m_opcode & 3, m_p[m_opcode & 3]);
	109	m_writehandler((UINT8)(m_opcode & 3), (UINT8)(m_p[m_opcode & 3]));
154	110	break;
155	111
156	112	case MCS48_EXPANDER_OP_OR:
157	113	m_p[m_opcode & 3] |= m_p2 & 0x0f;
158		m_writehandler(m_opcode & 3, m_p[m_opcode & 3]);
	114	m_writehandler((UINT8)(m_opcode & 3), (UINT8)(m_p[m_opcode & 3]));
159	115	break;
160	116
161	117	case MCS48_EXPANDER_OP_AND:
162	118	m_p[m_opcode & 3] &= m_p2 & 0x0f;
163		m_writehandler(m_opcode & 3, m_p[m_opcode & 3]);
	119	m_writehandler((UINT8)(m_opcode & 3), (UINT8)(m_p[m_opcode & 3]));
164	120	break;
165	121	}
166	122	}

trunk/src/emu/machine/i8243.h

r18552	r18553
27	27	MCFG_I8243_READHANDLER(_read) \
28	28	MCFG_I8243_WRITEHANDLER(_write) \
29	29
30		#define MCFG_I8243_READHANDLER(_read) \
31		i8243_device::static_set_read_handler(*device, _read); \
	30	#define MCFG_I8243_READHANDLER(_devcb) \
	31	devcb = &i8243_device::set_read_handler(*device, DEVCB2_##_devcb); \
32	32
33		#define MCFG_I8243_WRITEHANDLER(_write) \
34		i8243_device::static_set_write_handler(*device, _write); \
	33	#define MCFG_I8243_WRITEHANDLER(_devcb) \
	34	devcb = &i8243_device::set_write_handler(*device, DEVCB2_##_devcb); \
35	35
36	36	/***************************************************************************
37	37	TYPE DEFINITIONS
r18552	r18553
46	46	// construction/destruction
47	47	i8243_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
48	48
49		// inline configuration helpers
50		static void static_set_read_handler(device_t &device, read8_device_func callback);
51		static void static_set_write_handler(device_t &device, write8_device_func callback);
	49	// static configuration helpers
	50	template<class _Object> static devcb2_base &set_read_handler(device_t &device, _Object object) { return downcast<i8243_device &>(device).m_readhandler.set_callback(object); }
	51	template<class _Object> static devcb2_base &set_write_handler(device_t &device, _Object object) { return downcast<i8243_device &>(device).m_writehandler.set_callback(object); }
	52
	53	DECLARE_READ8_MEMBER(i8243_p2_r);
	54	DECLARE_WRITE8_MEMBER(i8243_p2_w);
52	55
	56	DECLARE_WRITE8_MEMBER(i8243_prog_w);
53	57
54		UINT8 i8243_p2_r(UINT32 offset);
55		void i8243_p2_w(UINT32 offset, UINT8 data);
56
57		void i8243_prog_w(UINT32 offset, UINT8 data);
58
59	58	protected:
60	59	// device-level overrides
61	60	virtual void device_start();
r18552	r18553
71	70	UINT8      m_opcode;         /* latched opcode */
72	71	UINT8      m_prog;            /* previous PROG state */
73	72
74		devcb_read8      m_readhandler_cb;
75		devcb_write8   m_writehandler_cb;
76
77		devcb_resolved_read8   m_readhandler;
78		devcb_resolved_write8   m_writehandler;
	73	devcb2_read8   m_readhandler;
	74	devcb2_write8   m_writehandler;
79	75	};
80	76
81	77
82	78	// device type definition
83	79	extern const device_type I8243;
84	80
85
86
87		/***************************************************************************
88		PROTOTYPES
89		***************************************************************************/
90
91		DECLARE_READ8_DEVICE_HANDLER( i8243_p2_r );
92		DECLARE_WRITE8_DEVICE_HANDLER( i8243_p2_w );
93
94		DECLARE_WRITE8_DEVICE_HANDLER( i8243_prog_w );
95
96
97	81	#endif  /* __I8243_H__ */

trunk/src/mess/includes/fidelz80.h

r18552	r18553
66	66	DECLARE_INPUT_CHANGED_MEMBER(fidelz80_trigger_reset);
67	67	DECLARE_INPUT_CHANGED_MEMBER(abc_trigger_reset);
68	68	TIMER_DEVICE_CALLBACK_MEMBER(nmi_timer);
	69
	70	DECLARE_WRITE8_MEMBER(digit_w);
69	71	};
70	72
71	73

trunk/src/mess/drivers/fidelz80.c

r18552	r18553
918	918	if (m_kp_matrix & 0x80)
919	919	data &= ioport("LINE8")->read();
920	920
921		return (m_i8243->i8243_p2_r(offset)&0x0f) | (data&0xf0);
	921	return (m_i8243->i8243_p2_r(space, offset)&0x0f) | (data&0xf0);
922	922	}
923	923
924	924	WRITE8_MEMBER(fidelz80_state::exp_i8243_p2_w)
925	925	{
926		m_i8243->i8243_p2_w(offset, data&0x0f);
	926	m_i8243->i8243_p2_w(space, offset, data&0x0f);
927	927	}
928	928
929	929	// probably related to the card scanner
r18552	r18553
941	941	I8243 expander
942	942	******************************************************************************/
943	943
944		static WRITE8_DEVICE_HANDLER( digit_w )
	944	WRITE8_MEMBER(fidelz80_state::digit_w)
945	945	{
946		fidelz80_state *state = space.machine().driver_data<fidelz80_state>();
947
948		if (state->m_digit_line_status[offset])
	946	if (m_digit_line_status[offset])
949	947	return;
950	948
951		state->m_digit_line_status[offset&3] = 1;
	949	m_digit_line_status[offset&3] = 1;
952	950
953	951	switch (offset)
954	952	{
955	953	case 0:
956		state->m_digit_data = (state->m_digit_data&(~0x000f)) | ((data<<0)&0x000f);
	954	m_digit_data = (m_digit_data&(~0x000f)) | ((data<<0)&0x000f);
957	955	break;
958	956	case 1:
959		state->m_digit_data = (state->m_digit_data&(~0x00f0)) | ((data<<4)&0x00f0);
	957	m_digit_data = (m_digit_data&(~0x00f0)) | ((data<<4)&0x00f0);
960	958	break;
961	959	case 2:
962		state->m_digit_data = (state->m_digit_data&(~0x0f00)) | ((data<<8)&0x0f00);
	960	m_digit_data = (m_digit_data&(~0x0f00)) | ((data<<8)&0x0f00);
963	961	break;
964	962	case 3:
965		state->m_digit_data = (state->m_digit_data&(~0xf000)) | ((data<<12)&0xf000);
	963	m_digit_data = (m_digit_data&(~0xf000)) | ((data<<12)&0xf000);
966	964	break;
967	965	}
968	966	}
r18552	r18553
1072	1070	ADDRESS_MAP_UNMAP_LOW
1073	1071	AM_RANGE(MCS48_PORT_P1, MCS48_PORT_P1) AM_WRITE(kp_matrix_w)
1074	1072	AM_RANGE(MCS48_PORT_P2, MCS48_PORT_P2) AM_READWRITE(exp_i8243_p2_r, exp_i8243_p2_w)
1075		AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE_LEGACY("i8243", i8243_prog_w)
	1073	AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_DEVWRITE("i8243", i8243_device, i8243_prog_w)
1076	1074
1077	1075	// related to the card scanner, probably clock and data optical
1078	1076	AM_RANGE(MCS48_PORT_T0, MCS48_PORT_T0) AM_READ(unknown_r)
r18552	r18553
1358	1356	MCFG_CPU_ADD("mcu", I8041, XTAL_5MHz) // 5MHz
1359	1357	MCFG_CPU_IO_MAP(abc_mcu_io)
1360	1358
1361		MCFG_I8243_ADD("i8243", NULL, digit_w)
	1359	MCFG_I8243_ADD("i8243", NOOP, WRITE8(fidelz80_state,digit_w))
1362	1360
1363	1361	/* sound hardware */
1364	1362	MCFG_SPEAKER_STANDARD_MONO( "mono" )

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