MAME SVN History

199869 Revisions

r18538 Monday 15th October, 2012 at 14:26:38 UTC by Curt Coder
(MESS) c128: Rewrote the driver using the PLA for address decoding. [Curt Coder]

[src/mess]	mess.lst mess.mak
[src/mess/drivers]	c128.c
[src/mess/includes]	c128.h
[src/mess/machine]	~~c128.c~~

trunk/src/mess/mess.lst
r18537	r18538
636	636	c128 // Commodore 128 - NTSC
637	637	c128cr // Commodore 128CR - NTSC (proto?)
638	638	c128sfi // Commodore 128 - PAL (Swedish / Finnish)
639		c128fra // Commodore 128 - PAL (French)
	639	//c128fra // Commodore 128 - PAL (French)
640	640	c128ger // Commodore 128 - PAL (German)
641		c128nor // Commodore 128 - PAL (Norwegian)
	641	//c128nor // Commodore 128 - PAL (Norwegian)
642	642	c128d // Commodore 128D - PAL
643	643	c128dpr // Commodore 128D - NTSC (proto)
644	644	c128dcr // Commodore 128DCR - NTSC
645	645	c128drde // Commodore 128DCR - PAL (German)
646		c128drit // Commodore 128DCR - PAL (Italian)
	646	//c128drit // Commodore 128DCR - PAL (Italian)
647	647	c128drsw // Commodore 128DCR - PAL (Swedish)
648	648	c128d81 // Commodore 128D/81
649	649

trunk/src/mess/drivers/c128.c
r18537	r18538
1		/***************************************************************************
2		commodore c128 home computer
3
4		PeT mess@utanet.at
5
6		documentation:
7		iDOC (http://www.softwolves.pp.se/idoc)
8		Christian Janoff mepk@c64.org
9		***************************************************************************/
10
11	1	/*
12	2
13		2008 - Driver Updates
14		---------------------
15
16		(most of the informations are taken from http://www.zimmers.net/cbmpics/ )
17
18
19		[CBM systems which belong to this driver]
20
21		* Commodore 128 (1985)
22
23		CPU: CSG 8502 (1 or 2 MHz), Z80 (~3 MHz)
24		RAM: 128 kilobytes
25		ROM: 72 kilobytes expandable
26		Video: MOS 8564 "VIC-IIE", MOS 8563 "VDC" CTRC (40/80 columns text; Palette of 16
27		colors; Hires modes 320 x 200, 640 x 200, 16k of dedicated VDC RAM)
28		Sound: MOS 8580 "SID" (3 voice stereo synthesizer/digital sound
29		capabilities)
30		Ports: MOS 6526 CIA x2 (2 Joystick/Mouse ports; CBM Serial port; CBM
31		Datasette port; parallel programmable "User" port; CBM Monitor port;
32		C64 expansion port; Warm reset switch; Keyboard port; Power switch)
33		Keyboard: Full-sized 93 key QWERTY (14 key numeric keypad; 8 programmable
34		function keys + HELP; 4 direction 4-key cursor-pad)
35
36		Upgrade kits were sold to upgrade the VDC RAM to 64k using a passthrough board
37		that the VDC sat in.
38
39
40		* Commodore 128CR (prototype from June, 1986)
41
42		Basically, a C128 in a redesigned board to reduce production costs. It's
43		not clear when it's been produced, nor if it has ever been produced on
44		large scale. Its BIOS is an intermediate revision between rev. 0 and rev. 1
45		in the main C128.
46		A picture of the PCB can be found here:
47		http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/c128/c128cr.jpg
48
49		Appears to be functionally identical to the original c128, has 16k VDC ram, and a
50		?prototype? VDC labeled 2568R1X. Has 6526A-1 CIAs, 8721R3 and 8722R2 gate
51		arrays, 8580R5 sid, and 8502R0 processor.
52
53
54		* Commodore 128D (1985)
55
56		Designed in the US, but only sold in Europe, it is a C128 in a desktop
57		case, with built-in 1571 disk drive (upgraded with a special software to
58		discourage pirating software). Some NTSC prototypes exist.
59
60		CPU: CSG 8502 (1 or 2 MHz), Z80 (~3 MHz), 6502 (co-processor for disk
61		drive)
62		RAM: 128 kilobytes
63		ROM: 72 kilobytes expandable
64		Video: MOS 8564 "VIC-IIE", MOS 8563 "VDC" CTRC (40/80 columns text; Palette of 16
65		colors; Hires modes 320 x 200, 640 x 200, 64k of dedicated VDC RAM)
66		Sound: MOS 8580 "SID" (3 voice stereo synthesizer/digital sound
67		capabilities)
68		Ports: MOS 6526 CIA x2 (2 Joystick/Mouse ports; CBM Serial port; CBM
69		Datasette port; parallel programmable "User" port; CBM Monitor port;
70		C64 expansion port; Warm reset switch; Keyboard port; Power switch)
71		Keyboard: Full-sized 93 key QWERTY (14 key numeric keypad; 8 programmable
72		function keys + HELP; 4 direction 4-key cursor-pad)
73		Additional Hardware: Internal 1571 disk drive (Double sided/Double Density
74		360k; capable of reading GCR and MFM formats)
75
76
77		* Commodore 128DCR (1986)
78
79		Basically, a C128D in a redesigned board to reduce production costs. It's
80		the only model sold in the US, but it's quite possible that it came later
81		in Europe as well (being cheaper to produce).
82
83
84		* Commodore "128D/81" (198?)
85
86		NTSC prototype for an improved version of C128D, featuring a built-in 1581
87		disk drive in place of the 1571 used in C128D / C128DCR. The prototype has no
88		given name, so C128D/81 is just a reasonable way to indicate it. The case is
89		from a PAL C128D and the board is a heavily modified PAL board with hand
90		soldered connections to make it NTSC.
91
92
93		[TO DO]
94
95		* C64 Mode
96
97		See [TO DO] in drivers/c64.c for the missing features.
98
99
100		* C/PM Mode
101
102		It should work if you put the CP/M disk in drive 8 and enter BOOT. Better
103		disk emulation would be of help, anyway.
104
105		* C128 Mode
106
107		Various missing features (e.g. no cpu clock doubling; no internal function
108		rom; serial bus doesn't support printer or other devices; no C128 cart
109		expansions are supported; no userport; no rs232/v.24 interface)
110
111		* Informations / BIOS / Supported Sets:
112
113		- Was C128D using rev. 1 BIOS in 4 ROMs? I guessed so because the board has the
114		same desing as a C128, and later C128DCR still used rev. 1 BIOS (only contained
115		in two ROMs)
116
117		- Is it possible to track down and dump properly C128 PAL BIOSes? Current sets
118		are mostly tagged as bad dumps because obtained by extracting the content in
119		pieces. I'd like to have confirmation that the common parts are really the same
120		before removing the flag.
121
122		- PAL BIOSes are from C128? C128D? or C128DCR? Were there differences in the
123		contents between them, except for being splitted in 2 or 4 parts? Were all
124		versions sold in each country? Right now we choose to support the following sets
125		(more to be added if BIOS content confirmed):
126
127		+ German, Italian and Swedish dumps are known to come from a C128DCR. Therefore,
128		we support c128drde, c128drit and c128drsw.
129
130		+ We also have a dump of the German C128, therefore we support the c128ger, even
131		if it's not clear which BASIC version it was shipped with. We assumed the older
132		kernal to be shipped with rev. 0 and the newer with rev. 1.
133
134		+ The Finnish, French and Norwegian dumps came with no notes (or these have been
135		lost). Therefore we support only the c128 for these, i.e. c128fin, c128fre and
136		c128nor.
137
138		+ Character ROM for Belgium, Italy and French was the same (I/F/B on the label,
139		and indeed it turned out to be the same on both the Italian and French C128)
140
141		- Also, the italian C128DCR was found with a rev. 0 BASIC on it. Were both rev. 0
142		and rev. 1 used in the CR version? When did Commodore switch between the two?
143
144		[Notes about dumping BIOS]
145
146		Dumping roms with eeprom reader
147		-------------------------------
148
149		c128 / c128d
150
151		U18 (read compatible 2764?) 8kB c64 character rom, c128 character rom
152		U32 23128 (read compatible 27128?) 16kB c64 Basic, c64 Kernel
153		U33 23128 (read compatible 27128?) 16kB c128 Basic at 0x4000
154		U34 23128 (read compatible 27128?) 16kB c128 Basic at 0x8000
155		U35 23128 (read compatible 27128?) 16kB c128 Editor, Z80BIOS, c128 Kernel
156
157		c128cr / c128dcr
158
159		U18 (read compatible 2764?) 8kB c64 character rom, c128 character rom
160		U32 23256 (read compatible 27256?) 32kB c64 Basic + Kernel, c128 Editor, Z80BIOS, c128 Kernel
161		U34 23256 (read compatible 27256?) 32kB c128 Basic
162
163		c128d / c128dcr also need:
164
165		U102 23256 (read compatible 27256?) 32kB 1571 system rom
166
167
168		It would be also possible to dump the BIOS in monitor, but it would be preferable
169		to use an EEPROM reader, in order to obtain a dump of the whole content.
170		*/
171
172		/*
173
174	3	TODO:
175	4
176		- connect to PLA
177		- clean up ROMs
178		- wire up function ROM softlist
179		- remove banking code from machine/c128.h
	5	- C64 mode charrom read
	6	- fix fast serial
	7	- K0-K2 key line read
	8	- clean up inputs
	9	- expansion DMA
180	10	- inherit from c64_state and use common members from there
181		- clean up inputs
182		- fix fast serial
183	11
184	12	*/
185	13
186		#include "emu.h"
187		#include "cpu/z80/z80.h"
188		#include "cpu/m6502/m6502.h"
189		#include "sound/sid6581.h"
190		#include "sound/dac.h"
191		#include "machine/6526cia.h"
192
193		#include "machine/cbmipt.h"
194		#include "video/mos6566.h"
195		#include "video/mc6845.h"
196
197
198		/* devices config */
199		#include "includes/cbm.h"
200		#include "formats/cbm_snqk.h"
201		#include "machine/cbmiec.h"
202
203	14	#include "includes/c128.h"
204		#include "includes/c64_legacy.h"
205	15
206	16
207	17
r18537	r18538
209	19	// MACROS / CONSTANTS
210	20	//**************************************************************************
211	21
	22	#define LOG 0
	23
212	24	#define A15 BIT(offset, 15)
213	25	#define A14 BIT(offset, 14)
214	26	#define A13 BIT(offset, 13)
r18537	r18538
219	31	#define VMA4 BIT(vma, 12)
220	32
221	33
222		/*************************************
223		*
224		* Main CPU memory handlers
225		*
226		*************************************/
227	34
	35	//**************************************************************************
	36	// INTERRUPTS
	37	//**************************************************************************
228	38
229		/* shares ram with m8502
230		* how to bankswitch ?
231		* bank 0
232		* 0x0000, 0x03ff bios rom
233		* 0x1400, 0x1bff vdc videoram
234		* 0x1c00, 0x23ff vdc colorram
235		* 0x2c00, 0x2fff vic2e videoram
236		* 0xff00, 0xff04 mmu registers
237		* else ram (dram bank 0?)
238		* bank 1
239		* 0x0000-0xedff ram (dram bank 1?)
240		* 0xe000-0xffff ram as bank 0
241		*/
	39	//-------------------------------------------------
	40	// check_interrupts -
	41	//-------------------------------------------------
242	42
243		void c128_state::bankswitch_pla(offs_t offset, offs_t ta, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
	43	inline void c128_state::check_interrupts()
	44	{
	45	int restore = BIT(ioport("SPECIAL")->read(), 7);
	46
	47	int irq = m_cia1_irq \|\| m_vic_irq \|\| m_exp_irq;
	48	int nmi = m_cia2_irq \|\| restore \|\| m_exp_nmi;
	49
	50	m_maincpu->set_input_line(INPUT_LINE_IRQ0, irq);
	51
	52	m_subcpu->set_input_line(M8502_IRQ_LINE, irq);
	53	m_subcpu->set_input_line(INPUT_LINE_NMI, nmi);
	54
	55	int flag = m_cass_rd && m_iec_srq;
	56
	57	m_cia1->flag_w(flag);
	58	}
	59
	60
	61
	62	//**************************************************************************
	63	// ADDRESS DECODING
	64	//**************************************************************************
	65
	66	//-------------------------------------------------
	67	// read_pla -
	68	//-------------------------------------------------
	69
	70	void c128_state::read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
244	71	int sden, int dir, int gwe, int rom1, int rom2, int rom3, int rom4, int charom, int colorram, int vic,
245	72	int from1, int romh, int roml, int dwe, int ioacc, int clrbank, int iocs, int casenb)
246	73	{
247	74	int _128_256 = 1;
248	75	int dmaack = 1;
249		int vicfix = 0;
250		int game = m_exp->game_r(ta, ba, rw, m_hiram);
251		int exrom = m_exp->exrom_r(ta, ba, rw, m_hiram);
	76	int vicfix = 1;
252	77	int clk = 1;
253	78
254		UINT32 input = clk << 26 \| m_va14 << 25 \| m_charen << 24 \|
	79	m_game = m_exp->game_r(ca, ba, rw, m_hiram);
	80	m_exrom = m_exp->exrom_r(ca, ba, rw, m_hiram);
	81
	82	UINT32 input = clk << 26 \| !m_va14 << 25 \| m_charen << 24 \|
255	83	m_hiram << 23 \| m_loram << 22 \| ba << 21 \| VMA5 << 20 \| VMA4 << 19 \| ms0 << 18 \| ms1 << 17 \| ms2 << 16 \|
256		exrom << 15 \| game << 14 \| rw << 13 \| aec << 12 \| A10 << 11 \| A11 << 10 \| A12 << 9 \| A13 << 8 \|
	84	m_exrom << 15 \| m_game << 14 \| rw << 13 \| aec << 12 \| A10 << 11 \| A11 << 10 \| A12 << 9 \| A13 << 8 \|
257	85	A14 << 7 \| A15 << 6 \| z80io << 5 \| m_z80en << 4 \| ms3 << 3 \| vicfix << 2 \| dmaack << 1 \| _128_256;
258	86
	87	/*
	88	000000000001111111112222222
	89	012345678901234567890123456
	90	--11--------0------10---0-- 000000000000000001
	91	---0--------0-1----10----1- 000000000000000001
	92	---0--------0--0---10----1- 000000000000000001
	93	---0--1101--111-------1-0-- 000000000000000001
	94	---0--1101--111--------10-- 000000000000000001
	95	---0--1101--11-0-------10-- 000000000000000001
	96	---11-1101--11--100-------- 000000000000000001
	97	*/
	98
259	99	UINT32 data = m_pla->read(input);
260	100
261	101	*sden = BIT(data, 0);
r18537	r18538
276	116	*gwe = BIT(data, 15);
277	117	*colorram = BIT(data, 16);
278	118	*charom = BIT(data, 17);
	119
	120	m_clrbank = *clrbank;
279	121	}
280	122
	123
	124	//-------------------------------------------------
	125	// read_memory -
	126	//-------------------------------------------------
	127
281	128	UINT8 c128_state::read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io)
282	129	{
283	130	int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1;
r18537	r18538
285	132	from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1;
286	133	int io1 = 1, io2 = 1;
287	134
	135	UINT8 data = 0xff;
	136
288	137	offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3, &cas0, &cas1);
	138	offs_t ma = 0;
	139	offs_t sa = 0;
289	140
290		bankswitch_pla(offset, ta, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
291		&sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
292		&from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
293
294		UINT8 data = 0xff;
295
296		if (ba)
	141	if (aec)
297	142	{
298	143	data = m_vic->bus_r();
	144	ma = ta \| (offset & 0xff);
	145	sa = offset & 0xff;
299	146	}
	147	else
	148	{
	149	ta \|= (vma & 0xf00);
	150	ma = (!m_va15 << 15) \| (!m_va14 << 14) \| vma;
	151	sa = vma & 0xff;
	152	}
300	153
	154	offs_t ca = ta \| (offset & 0xff);
	155
	156	read_pla(offset, ca, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
	157	&sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
	158	&from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
	159	/*
	160	if (!space.debugger_access() && !ba)
	161	logerror("read %04x %04x %04x - %u %u %u %u %u %u %u %u %u %u - %u %u %u %u %u %u %u %u %u %u - %u %u %u %u %u %u %u %u\n",
	162	offset, ta, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0, cas1, cas0,
	163	sden, dir, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic,
	164	from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb);
	165	*/
301	166	if (!casenb)
302	167	{
303	168	if (!cas0)
304	169	{
305		data = m_ram->pointer()[(ta ~~& 0xff00) \| (offset & 0xff)~~];
	170	data = m_ram->pointer()[ma];
306	171	}
307	172	else if (!cas1)
308	173	{
309		data = m_ram->pointer()[0x10000 \| (ta ~~& 0xff00) \| (offset & 0xff)~~];
	174	data = m_ram->pointer()[0x10000 \| ma];
310	175	}
311	176	}
312	177	else if (!rom1)
313	178	{
314		if (m_rom3)
315		{
316		data = m_rom1[((BIT(ta, 14) && BIT(offset, 13)) << 13) \| (ta & 0x1000) \| (offset & 0xfff)];
317		}
318		else
319		{
320		data = m_rom1[(ms3 << 14) \| ((BIT(ta, 14) && BIT(offset, 13)) << 13) \| (ta & 0x1000) \| (offset & 0xfff)];
321		}
	179	// CR: data = m_rom1[(ms3 << 14) \| ((BIT(ta, 14) && BIT(offset, 13)) << 13) \| (ta & 0x1000) \| (offset & 0xfff)];
	180	data = m_rom1[((BIT(ta, 14) && BIT(offset, 13)) << 13) \| (ta & 0x1000) \| (offset & 0xfff)];
322	181	}
323		else if (!rom2 ~~&& m_rom3~~)
	182	else if (!rom2)
324	183	{
325	184	data = m_rom2[offset & 0x3fff];
326	185	}
327	186	else if (!rom3)
328	187	{
329		if (m_rom3)
330		{
331		data = m_rom3[offset & 0x3fff];
332		}
333		else
334		{
335		data = m_rom2[(BIT(offset, 15) << 14) \| (offset & 0x3fff)];
336		}
	188	// CR: data = m_rom3[(BIT(offset, 15) << 14) \| (offset & 0x3fff)];
	189	data = m_rom3[offset & 0x3fff];
337	190	}
338		else if (!rom4 ~~&& m_rom3~~)
	191	else if (!rom4)
339	192	{
340	193	data = m_rom4[(ta & 0x1000) \| (offset & 0x2fff)];
341	194	}
342	195	else if (!charom)
343	196	{
344		data = m_charom[(ms3 << 12) \| (ta & 0xf00) \| ~~(off~~s~~et & 0xff)~~];
	197	data = m_charom[(ms3 << 12) \| (ta & 0xf00) \| sa];
345	198	}
346	199	else if (!colorram)
347	200	{
348		data = m_color_ram[(clrbank << 10) \| (ta & 0x300) \| ~~(off~~s~~et & 0xff)~~] & 0x0f;
	201	data = m_color_ram[(clrbank << 10) \| (ta & 0x300) \| sa] & 0x0f;
349	202	}
350	203	else if (!vic)
351	204	{
r18537	r18538
392	245	}
393	246	}
394	247
395		data = m_exp->cd_r(space, ta, data, ba, roml, romh, io1, io2);
	248	data = m_exp->cd_r(space, ca, data, ba, roml, romh, io1, io2);
396	249
397	250	return m_mmu->read(offset, data);
398	251	}
399	252
	253
	254	//-------------------------------------------------
	255	// write_memory -
	256	//-------------------------------------------------
	257
400	258	void c128_state::write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io)
401	259	{
402	260	int rw = 0, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1;
r18537	r18538
405	263	int io1 = 1, io2 = 1;
406	264
407	265	offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3, &cas0, &cas1);
	266	offs_t ca = ta \| (offset & 0xff);
	267	offs_t ma = ta \| (offset & 0xff);
	268	offs_t sa = offset & 0xff;
408	269
409		ba~~nkswitch~~_pla(offset, ta, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
	270	read_pla(offset, ca, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
410	271	&sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
411	272	&from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
412	273
r18537	r18538
414	275	{
415	276	if (!cas0)
416	277	{
417		m_ram->pointer()[(ta ~~& 0xff00) \| (offset & 0xff)~~] = data;
	278	m_ram->pointer()[ma] = data;
418	279	}
419	280	else if (!cas1)
420	281	{
421		m_ram->pointer()[0x10000 \| (ta ~~& 0xff00) \| (offset & 0xff)~~] = data;
	282	m_ram->pointer()[0x10000 \| ma] = data;
422	283	}
423	284	}
424	285	else if (!colorram && !gwe)
425	286	{
426		m_color_ram[(clrbank << 10) \| (ta & 0x300) \| ~~(off~~s~~et & 0xff)~~] = data \| 0xf0;
	287	m_color_ram[(clrbank << 10) \| (ta & 0x300) \| sa] = data \| 0xf0;
427	288	}
428	289	else if (!vic)
429	290	{
r18537	r18538
466	327	}
467	328	}
468	329
469		m_exp->cd_w(space, ta, data, ba, roml, romh, io1, io2);
	330	m_exp->cd_w(space, ca, data, ba, roml, romh, io1, io2);
470	331
471	332	m_mmu->write(space, offset, data);
472	333	}
473	334
	335
	336	//-------------------------------------------------
	337	// z80_r -
	338	//-------------------------------------------------
	339
474	340	READ8_MEMBER( c128_state::z80_r )
475	341	{
476	342	int ba = 1, aec = 1, z80io = 1;
r18537	r18538
479	345	return read_memory(space, offset, vma, ba, aec, z80io);
480	346	}
481	347
	348
	349	//-------------------------------------------------
	350	// z80_w -
	351	//-------------------------------------------------
	352
482	353	WRITE8_MEMBER( c128_state::z80_w )
483	354	{
484	355	int ba = 1, aec = 1, z80io = 1;
r18537	r18538
487	358	write_memory(space, offset, vma, data, ba, aec, z80io);
488	359	}
489	360
	361
	362	//-------------------------------------------------
	363	// z80_io_r -
	364	//-------------------------------------------------
	365
490	366	READ8_MEMBER( c128_state::z80_io_r )
491	367	{
492	368	int ba = 1, aec = 1, z80io = 0;
r18537	r18538
495	371	return read_memory(space, offset, vma, ba, aec, z80io);
496	372	}
497	373
	374
	375	//-------------------------------------------------
	376	// z80_io_w -
	377	//-------------------------------------------------
	378
498	379	WRITE8_MEMBER( c128_state::z80_io_w )
499	380	{
500	381	int ba = 1, aec = 1, z80io = 0;
r18537	r18538
503	384	write_memory(space, offset, vma, data, ba, aec, z80io);
504	385	}
505	386
	387
	388	//-------------------------------------------------
	389	// read -
	390	//-------------------------------------------------
	391
506	392	READ8_MEMBER( c128_state::read )
507	393	{
508	394	int ba = 1, aec = 1, z80io = 1;
509	395	offs_t vma = 0;
510	396
511		return read_memory(space, ~~vma,~~ offset, ba, aec, z80io);
	397	return read_memory(space, offset, vma, ba, aec, z80io);
512	398	}
513	399
	400
	401	//-------------------------------------------------
	402	// write -
	403	//-------------------------------------------------
	404
514	405	WRITE8_MEMBER( c128_state::write )
515	406	{
516	407	int ba = 1, aec = 1, z80io = 1;
r18537	r18538
519	410	write_memory(space, offset, vma, data, ba, aec, z80io);
520	411	}
521	412
	413
	414	//-------------------------------------------------
	415	// vic_videoram_r -
	416	//-------------------------------------------------
	417
522	418	READ8_MEMBER( c128_state::vic_videoram_r )
523	419	{
524	420	int ba = 0, aec = 0, z80io = 1;
525		offs_t vma = 0;
526	421
527		return read_memory(space, offset~~, vma~~, ba, aec, z80io);
	422	return read_memory(space, 0, offset, ba, aec, z80io);
528	423	}
529	424
530	425
	426	//-------------------------------------------------
	427	// vic_colorram_r -
	428	//-------------------------------------------------
531	429
	430	READ8_MEMBER( c128_state::vic_colorram_r )
	431	{
	432	return m_color_ram[(m_clrbank << 10) \| offset];
	433	}
	434
	435
	436
532	437	//**************************************************************************
533	438	// ADDRESS MAPS
534	439	//**************************************************************************
r18537	r18538
538	443	//-------------------------------------------------
539	444
540	445	static ADDRESS_MAP_START( z80_mem, AS_PROGRAM, 8, c128_state )
541		AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bank10") AM_WRITE(write_0000)
542		AM_RANGE(0x1000, 0xbfff) AM_READ_BANK("bank11") AM_WRITE(write_1000)
543		AM_RANGE(0xc000, 0xffff) AM_RAM
	446	AM_RANGE(0x0000, 0xffff) AM_READWRITE(z80_r, z80_w)
544	447	ADDRESS_MAP_END
545	448
546	449
r18537	r18538
549	452	//-------------------------------------------------
550	453
551	454	static ADDRESS_MAP_START( z80_io, AS_IO, 8, c128_state )
552		AM_RANGE(0x1000, 0x13ff) AM_READWRITE_LEGACY(c64_colorram_read, c64_colorram_write)
553		AM_RANGE(0xd000, 0xd3ff) AM_DEVREADWRITE(MOS8564_TAG, mos6566_device, read, write)
554		AM_RANGE(0xd400, 0xd4ff) AM_DEVREADWRITE(MOS6581_TAG, sid6581_device, read, write)
555		AM_RANGE(0xd500, 0xd5ff) AM_READWRITE(mmu8722_port_r, mmu8722_port_w)
556		AM_RANGE(0xd600, 0xd600) AM_MIRROR(0x1fe) AM_DEVREADWRITE(MOS8563_TAG, mos8563_device, status_r, address_w)
557		AM_RANGE(0xd601, 0xd601) AM_MIRROR(0x1fe) AM_DEVREADWRITE(MOS8563_TAG, mos8563_device, register_r, register_w)
558		AM_RANGE(0xdc00, 0xdc0f) AM_MIRROR(0xf0) AM_DEVREADWRITE(MOS6526_1_TAG, mos6526_device, read, write)
559		AM_RANGE(0xdd00, 0xdd0f) AM_MIRROR(0xf0) AM_DEVREADWRITE(MOS6526_2_TAG, mos6526_device, read, write)
560		/* AM_RANGE(0xdf00, 0xdfff) AM_READWRITE_LEGACY(dma_port_r, dma_port_w) */
	455	AM_RANGE(0x0000, 0xffff) AM_READWRITE(z80_io_r, z80_io_w)
561	456	ADDRESS_MAP_END
562	457
563	458
r18537	r18538
566	461	//-------------------------------------------------
567	462
568	463	static ADDRESS_MAP_START( m8502_mem, AS_PROGRAM, 8, c128_state )
569		AM_RANGE(0x0000, 0x00ff) AM_RAMBANK("bank1")
570		AM_RANGE(0x0100, 0x01ff) AM_RAMBANK("bank2")
571		AM_RANGE(0x0200, 0x03ff) AM_RAMBANK("bank3")
572		AM_RANGE(0x0400, 0x0fff) AM_RAMBANK("bank4")
573		AM_RANGE(0x1000, 0x1fff) AM_RAMBANK("bank5")
574		AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank6")
575
576		AM_RANGE(0x4000, 0x7fff) AM_READ_BANK( "bank7") AM_WRITE(write_4000 )
577		AM_RANGE(0x8000, 0x9fff) AM_READ_BANK( "bank8") AM_WRITE(write_8000 )
578		AM_RANGE(0xa000, 0xbfff) AM_READ_BANK( "bank9") AM_WRITE(write_a000 )
579
580		AM_RANGE(0xc000, 0xcfff) AM_READ_BANK( "bank12") AM_WRITE(write_c000 )
581		AM_RANGE(0xd000, 0xdfff) AM_READ_BANK( "bank13") AM_WRITE(write_d000)
582		AM_RANGE(0xe000, 0xfeff) AM_READ_BANK( "bank14") AM_WRITE(write_e000 )
583		AM_RANGE(0xff00, 0xff04) AM_READ_BANK( "bank15") AM_WRITE(write_ff00 ) /* mmu c128 modus */
584		AM_RANGE(0xff05, 0xffff) AM_READ_BANK( "bank16") AM_WRITE(write_ff05 )
	464	AM_RANGE(0x0000, 0xffff) AM_READWRITE(read, write)
585	465	ADDRESS_MAP_END
586	466
587	467
r18537	r18538
590	470	//-------------------------------------------------
591	471
592	472	static ADDRESS_MAP_START( vic_videoram_map, AS_0, 8, c128_state )
593		AM_RANGE(0x0000, 0x3fff) AM_READ(vic_dma_r~~ead~~)
	473	AM_RANGE(0x0000, 0x3fff) AM_READ(vic_videoram_r)
594	474	ADDRESS_MAP_END
595	475
596	476
r18537	r18538
599	479	//-------------------------------------------------
600	480
601	481	static ADDRESS_MAP_START( vic_colorram_map, AS_1, 8, c128_state )
602		AM_RANGE(0x000, 0x3ff) AM_READ(vic_~~dma_read_~~color)
	482	AM_RANGE(0x000, 0x3ff) AM_READ(vic_colorram_r)
603	483	ADDRESS_MAP_END
604	484
605	485
r18537	r18538
709	589	//-------------------------------------------------
710	590	// INPUT_PORTS( c128fra )
711	591	//-------------------------------------------------
712
	592	#ifdef UNUSED_CODE
713	593	static INPUT_PORTS_START( c128fra )
714	594	PORT_INCLUDE( c128 )
715	595
r18537	r18538
761	641	PORT_CONFSETTING( 0x00, "ASCII" )
762	642	PORT_CONFSETTING( 0x20, "?French?" )
763	643	INPUT_PORTS_END
	644	#endif
764	645
765
766	646	//-------------------------------------------------
767	647	// INPUT_PORTS( c128ita )
768	648	//-------------------------------------------------
769
	649	#ifdef UNUSED_CODE
770	650	static INPUT_PORTS_START( c128ita )
771	651	PORT_INCLUDE( c128 )
772	652
r18537	r18538
815	695	PORT_CONFSETTING( 0x00, "ASCII" )
816	696	PORT_CONFSETTING( 0x20, DEF_STR( Italian ) )
817	697	INPUT_PORTS_END
	698	#endif
818	699
819
820	700	//-------------------------------------------------
821	701	// INPUT_PORTS( c128swe )
822	702	//-------------------------------------------------
r18537	r18538
865	745	{
866	746	if (state)
867	747	{
868		m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
869		m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	748	m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	749	m_subcpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	750
	751	if (m_reset)
	752	{
	753	m_subcpu->reset();
	754	//m_subcpu->set_state_int(M8502_PC, 0xff3d);
	755	m_reset = 0;
	756	}
870	757	}
871	758	else
872	759	{
873		m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
874		m_subcpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	760	m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	761	m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
875	762	}
876	763
877	764	m_z80en = state;
r18537	r18538
879	766
880	767	WRITE_LINE_MEMBER( c128_state::mmu_fsdir_w )
881	768	{
	769	update_iec();
882	770	}
883	771
884	772	READ_LINE_MEMBER( c128_state::mmu_game_r )
885	773	{
886		return 1;
	774	return m_game;
887	775	}
888	776
889	777	READ_LINE_MEMBER( c128_state::mmu_exrom_r )
890	778	{
891		return 1;
	779	return m_exrom;
892	780	}
893	781
894	782	READ_LINE_MEMBER( c128_state::mmu_sense40_r )
895	783	{
896		return 1;
	784	return !BIT(ioport("SPECIAL")->read(), 4);
897	785	}
898	786
899	787	static MOS8722_INTERFACE( mmu_intf )
r18537	r18538
910	798	// MOS8564_INTERFACE( vic_intf )
911	799	//-------------------------------------------------
912	800
913		RE~~AD8~~_MEMBER( c128_state::~~vic~~_lightpe~~n_x_cb~~ )
	801	INTERRUPT_GEN_MEMBER( c128_state::frame_interrupt )
914	802	{
915		return ioport("LIGHTX")->read() & ~0x01;
916		}
	803	static const char *const c128ports[] = { "KP0", "KP1", "KP2" };
917	804
918		READ8_MEMBER( c128_state::vic_lightpen_y_cb )
919		{
920		return ioport("LIGHTY")->read() & ~0x01;
	805	check_interrupts();
	806
	807	/* common keys input ports */
	808	cbm_common_interrupt(&device);
	809
	810	/* Fix Me! Currently, neither left Shift nor Shift Lock work in c128, but reading the correspondent input produces a bug!
	811	Hence, we overwrite the actual reading as it never happens */
	812	if ((ioport("SPECIAL")->read() & 0x40)) //
	813	c64_keyline[1] \|= 0x80;
	814
	815	/* c128 specific: keypad input ports */
	816	for (int i = 0; i < 3; i++)
	817	{
	818	UINT8 value = 0xff;
	819	value &= ~ioport(c128ports[i])->read();
	820	m_keyline[i] = value;
	821	}
921	822	}
922	823
923		RE~~AD8~~_MEMBER( c128_state::vic_li~~ghtpen~~_~~button_cb~~ )
	824	WRITE_LINE_MEMBER( c128_state::vic_irq_w )
924	825	{
925		return ioport("OTHER")->read() & 0x04;
926		}
	826	m_vic_irq = state;
927	827
928		READ8_MEMBER( c128_state::vic_rdy_cb )
929		{
930		return ioport("CTRLSEL")->read() & 0x08;
	828	check_interrupts();
931	829	}
932	830
933	831	static MOS8564_INTERFACE( vic_intf )
934	832	{
935	833	SCREEN_VIC_TAG,
936	834	Z80A_TAG,
937		DEVCB_DRIVER_LINE_MEMBER(c128_state, vic_i~~nte~~r~~rupt~~),
	835	DEVCB_DRIVER_LINE_MEMBER(c128_state, vic_irq_w),
938	836	DEVCB_NULL,
939		DEVCB_DRIVER_MEMBER(c128_state, vic_lightpen_x_cb),
940		DEVCB_DRIVER_MEMBER(c128_state, vic_lightpen_y_cb),
941		DEVCB_DRIVER_MEMBER(c128_state, vic_lightpen_button_cb),
942		DEVCB_DRIVER_MEMBER(c128_state, vic_rdy_cb)
	837	DEVCB_NULL,
	838	DEVCB_NULL,
	839	DEVCB_NULL,
	840	DEVCB_NULL
943	841	};
944	842
945	843
r18537	r18538
1004	902
1005	903
1006	904	//-------------------------------------------------
	905	// MOS6526_INTERFACE( cia1_intf )
	906	//-------------------------------------------------
	907
	908	WRITE_LINE_MEMBER( c128_state::cia1_irq_w )
	909	{
	910	m_cia1_irq = state;
	911
	912	check_interrupts();
	913	}
	914
	915	READ8_MEMBER( c128_state::cia1_pa_r )
	916	{
	917	/*
	918
	919	bit description
	920
	921	PA0 COL0, JOY B0
	922	PA1 COL1, JOY B1
	923	PA2 COL2, JOY B2
	924	PA3 COL3, JOY B3
	925	PA4 COL4, BTNB
	926	PA5 COL5
	927	PA6 COL6
	928	PA7 COL7
	929
	930	*/
	931
	932	UINT8 cia0portb = m_cia1->pb_r();
	933
	934	return cbm_common_cia0_port_a_r(m_cia1, cia0portb);
	935	}
	936
	937	READ8_MEMBER( c128_state::cia1_pb_r )
	938	{
	939	/*
	940
	941	bit description
	942
	943	PB0 JOY A0
	944	PB1 JOY A1
	945	PB2 JOY A2
	946	PB3 JOY A3
	947	PB4 BTNA/_LP
	948	PB5
	949	PB6
	950	PB7
	951
	952	*/
	953
	954	UINT8 data = 0xff;
	955	UINT8 cia0porta = m_cia1->pa_r();
	956	//vic2e_device_interface intf = dynamic_cast<vic2e_device_interface>(&m_vic);
	957
	958	data &= cbm_common_cia0_port_b_r(m_cia1, cia0porta);
	959	/*
	960	if (!intf->k0_r()) data &= m_keyline[0];
	961	if (!intf->k1_r()) data &= m_keyline[1];
	962	if (!intf->k2_r()) data &= m_keyline[2];
	963	*/
	964	return data;
	965	}
	966
	967	WRITE8_MEMBER( c128_state::cia1_pb_w )
	968	{
	969	/*
	970
	971	bit description
	972
	973	PB0 ROW0
	974	PB1 ROW1
	975	PB2 ROW2
	976	PB3 ROW3
	977	PB4 ROW4
	978	PB5 ROW5
	979	PB6 ROW6
	980	PB7 ROW7
	981
	982	*/
	983
	984	m_vic->lp_w(BIT(data, 4));
	985	}
	986
	987	WRITE_LINE_MEMBER( c128_state::cia1_cnt_w )
	988	{
	989	m_cnt1 = state;
	990
	991	update_iec();
	992	}
	993
	994	WRITE_LINE_MEMBER( c128_state::cia1_sp_w )
	995	{
	996	m_sp1 = state;
	997
	998	update_iec();
	999	}
	1000
	1001	static MOS6526_INTERFACE( cia1_intf )
	1002	{
	1003	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_irq_w),
	1004	DEVCB_NULL,
	1005	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_cnt_w),
	1006	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_sp_w),
	1007	DEVCB_DRIVER_MEMBER(c128_state, cia1_pa_r),
	1008	DEVCB_NULL,
	1009	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_r),
	1010	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_w)
	1011	};
	1012
	1013
	1014	//-------------------------------------------------
	1015	// MOS6526_INTERFACE( cia2_intf )
	1016	//-------------------------------------------------
	1017
	1018	WRITE_LINE_MEMBER( c128_state::cia2_irq_w )
	1019	{
	1020	m_cia2_irq = state;
	1021
	1022	check_interrupts();
	1023	}
	1024
	1025	READ8_MEMBER( c128_state::cia2_pa_r )
	1026	{
	1027	/*
	1028
	1029	bit description
	1030
	1031	PA0
	1032	PA1
	1033	PA2 USER PORT
	1034	PA3
	1035	PA4
	1036	PA5
	1037	PA6 CLK
	1038	PA7 DATA
	1039
	1040	*/
	1041
	1042	UINT8 data = 0;
	1043
	1044	// user port
	1045	data \|= m_user->pa2_r() << 2;
	1046
	1047	// IEC bus
	1048	data \|= m_iec->clk_r() << 6;
	1049	data \|= m_iec->data_r() << 7;
	1050
	1051	return data;
	1052	}
	1053
	1054	WRITE8_MEMBER( c128_state::cia2_pa_w )
	1055	{
	1056	/*
	1057
	1058	bit description
	1059
	1060	PA0 _VA14
	1061	PA1 _VA15
	1062	PA2 USER PORT
	1063	PA3 ATN OUT
	1064	PA4 CLK OUT
	1065	PA5 DATA OUT
	1066	PA6
	1067	PA7
	1068
	1069	*/
	1070
	1071	// VIC banking
	1072	m_va14 = BIT(data, 0);
	1073	m_va15 = BIT(data, 1);
	1074
	1075	// user port
	1076	m_user->pa2_w(BIT(data, 2));
	1077
	1078	// IEC bus
	1079	m_iec->atn_w(!BIT(data, 3));
	1080	m_iec->clk_w(!BIT(data, 4));
	1081	m_iec_data_out = BIT(data, 5);
	1082
	1083	update_iec();
	1084	}
	1085
	1086	static MOS6526_INTERFACE( cia2_intf )
	1087	{
	1088	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia2_irq_w),
	1089	DEVCB_DEVICE_LINE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, pc2_w),
	1090	DEVCB_DEVICE_LINE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, sp2_w),
	1091	DEVCB_DEVICE_LINE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, cnt2_w),
	1092	DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_r),
	1093	DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_w),
	1094	DEVCB_DEVICE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, pb_r),
	1095	DEVCB_DEVICE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, pb_w)
	1096	};
	1097
	1098
	1099	//-------------------------------------------------
1007	1100	// M6510_INTERFACE( cpu_intf )
1008	1101	//-------------------------------------------------
1009	1102
	1103	READ8_MEMBER( c128_state::cpu_r)
	1104	{
	1105	/*
	1106
	1107	bit description
	1108
	1109	P0 1
	1110	P1 1
	1111	P2 1
	1112	P3
	1113	P4 CASS SENSE
	1114	P5
	1115	P6 CAPS LOCK
	1116
	1117	*/
	1118
	1119	UINT8 data = 0x07;
	1120
	1121	// cassette sense
	1122	data \|= m_cassette->sense_r() << 4;
	1123
	1124	// CAPS LOCK
	1125	data \|= !BIT(ioport("SPECIAL")->read(), 5) << 6;
	1126
	1127	return data;
	1128	}
	1129
	1130	WRITE8_MEMBER( c128_state::cpu_w )
	1131	{
	1132	/*
	1133
	1134	bit description
	1135
	1136	P0 LORAM
	1137	P1 HIRAM
	1138	P2 CHAREN
	1139	P3 CASS WRT
	1140	P4
	1141	P5 CASS MOTOR
	1142	P6
	1143
	1144	*/
	1145
	1146	// memory banking
	1147	m_loram = BIT(data, 0);
	1148	m_hiram = BIT(data, 1);
	1149	m_charen = BIT(data, 2);
	1150
	1151	// cassette write
	1152	m_cassette->write(BIT(data, 3));
	1153
	1154	// cassette motor
	1155	m_cassette->motor_w(BIT(data, 5));
	1156	}
	1157
1010	1158	static M6510_INTERFACE( cpu_intf )
1011	1159	{
1012		DEVCB_NULL, /* read_indexed_func */
1013		DEVCB_NULL, /* write_indexed_func */
1014		DEVCB_DRIVER_MEMBER(c128_state, cpu_r), /* port_read_func */
1015		DEVCB_DRIVER_MEMBER(c128_state, cpu_w), /* port_write_func */
	1160	DEVCB_NULL,
	1161	DEVCB_NULL,
	1162	DEVCB_DRIVER_MEMBER(c128_state, cpu_r),
	1163	DEVCB_DRIVER_MEMBER(c128_state, cpu_w),
1016	1164	0x07,
1017	1165	0x20
1018	1166	};
r18537	r18538
1022	1170	// CBM_IEC_INTERFACE( cbm_iec_intf )
1023	1171	//-------------------------------------------------
1024	1172
	1173	inline void c128_state::update_iec()
	1174	{
	1175	int fsdir = m_mmu->fsdir_r();
	1176
	1177	// fast serial data in
	1178	int data_in = m_iec->data_r();
	1179
	1180	m_cia1->sp_w(fsdir \|\| data_in);
	1181
	1182	// fast serial data out
	1183	int data_out = !m_iec_data_out;
	1184
	1185	if (fsdir) data_out &= m_sp1;
	1186
	1187	m_iec->data_w(data_out);
	1188
	1189	// fast serial clock in
	1190	int srq_in = m_iec->srq_r();
	1191
	1192	m_cia1->cnt_w(fsdir \|\| srq_in);
	1193
	1194	// fast serial clock out
	1195	int srq_out = 1;
	1196
	1197	if (fsdir) srq_out &= m_cnt1;
	1198
	1199	m_iec->srq_w(srq_out);
	1200	}
	1201
	1202	WRITE_LINE_MEMBER( c128_state::iec_srq_w )
	1203	{
	1204	update_iec();
	1205	}
	1206
	1207	WRITE_LINE_MEMBER( c128_state::iec_data_w )
	1208	{
	1209	update_iec();
	1210	}
	1211
1025	1212	static CBM_IEC_INTERFACE( cbm_iec_intf )
1026	1213	{
1027	1214	DEVCB_DRIVER_LINE_MEMBER(c128_state, iec_srq_w),
r18537	r18538
1036	1223	// PET_DATASSETTE_PORT_INTERFACE( datassette_intf )
1037	1224	//-------------------------------------------------
1038	1225
	1226	WRITE_LINE_MEMBER( c128_state::tape_read_w )
	1227	{
	1228	m_cass_rd = state;
	1229
	1230	check_interrupts();
	1231	}
	1232
1039	1233	static PET_DATASSETTE_PORT_INTERFACE( datassette_intf )
1040	1234	{
1041		DEVCB_DEVICE_LINE_MEMBER(~~MOS6526_~~1~~_TAG, mos65~~26_de~~vice~~, flag_w)
	1235	DEVCB_DRIVER_LINE_MEMBER(c128_state, tape_read_w),
1042	1236	};
1043	1237
1044	1238
r18537	r18538
1046	1240	// C64_EXPANSION_INTERFACE( expansion_intf )
1047	1241	//-------------------------------------------------
1048	1242
	1243	READ8_MEMBER( c128_state::exp_dma_r )
	1244	{
	1245	return m_subcpu->space(AS_PROGRAM).read_byte(offset);
	1246	}
	1247
	1248	WRITE8_MEMBER( c128_state::exp_dma_w )
	1249	{
	1250	m_subcpu->space(AS_PROGRAM).write_byte(offset, data);
	1251	}
	1252
	1253	WRITE_LINE_MEMBER( c128_state::exp_irq_w )
	1254	{
	1255	m_exp_irq = state;
	1256
	1257	check_interrupts();
	1258	}
	1259
	1260	WRITE_LINE_MEMBER( c128_state::exp_nmi_w )
	1261	{
	1262	m_exp_nmi = state;
	1263
	1264	check_interrupts();
	1265	}
	1266
	1267	WRITE_LINE_MEMBER( c128_state::exp_dma_w )
	1268	{
	1269	// TODO
	1270	}
	1271
	1272	WRITE_LINE_MEMBER( c128_state::exp_reset_w )
	1273	{
	1274	if (state == ASSERT_LINE)
	1275	{
	1276	machine_reset();
	1277	}
	1278	}
	1279
1049	1280	static C64_EXPANSION_INTERFACE( expansion_intf )
1050	1281	{
1051		DEVCB_NULL,
1052		DEVCB_NULL,
1053		DEVCB_NULL,
1054		DEVCB_NULL,
1055		DEVCB_NULL,
1056		DEVCB_NULL
	1282	DEVCB_DRIVER_MEMBER(c128_state, exp_dma_r),
	1283	DEVCB_DRIVER_MEMBER(c128_state, exp_dma_w),
	1284	DEVCB_DRIVER_LINE_MEMBER(c128_state, exp_irq_w),
	1285	DEVCB_DRIVER_LINE_MEMBER(c128_state, exp_nmi_w),
	1286	DEVCB_DRIVER_LINE_MEMBER(c128_state, exp_dma_w),
	1287	DEVCB_DRIVER_LINE_MEMBER(c128_state, exp_reset_w)
1057	1288	};
1058	1289
1059	1290
r18537	r18538
1063	1294
1064	1295	static C64_USER_PORT_INTERFACE( user_intf )
1065	1296	{
1066		DEVCB_NULL,
1067		DEVCB_NULL,
1068		DEVCB_NULL,
1069		DEVCB_NULL,
1070		DEVCB_NULL,
1071		DEVCB_NULL
	1297	DEVCB_DEVICE_LINE_MEMBER(MOS6526_1_TAG, mos6526_device, sp_w),
	1298	DEVCB_DEVICE_LINE_MEMBER(MOS6526_1_TAG, mos6526_device, cnt_w),
	1299	DEVCB_DEVICE_LINE_MEMBER(MOS6526_2_TAG, mos6526_device, sp_w),
	1300	DEVCB_DEVICE_LINE_MEMBER(MOS6526_2_TAG, mos6526_device, cnt_w),
	1301	DEVCB_DEVICE_LINE_MEMBER(MOS6526_2_TAG, mos6526_device, flag_w),
	1302	DEVCB_DRIVER_LINE_MEMBER(c128_state, exp_reset_w)
1072	1303	};
1073	1304
1074	1305
1075	1306	//**************************************************************************
	1307	// MACHINE INITIALIZATION
	1308	//**************************************************************************
	1309
	1310	//-------------------------------------------------
	1311	// MACHINE_START( c64 )
	1312	//-------------------------------------------------
	1313
	1314	void c128_state::machine_start()
	1315	{
	1316	cbm_common_init();
	1317	m_keyline[0] = m_keyline[1] = m_keyline[2] = 0xff;
	1318
	1319	// find memory regions
	1320	m_rom1 = memregion(M8502_TAG)->base();
	1321	m_rom2 = m_rom1 + 0x4000;
	1322	m_rom3 = m_rom1 + 0x8000;
	1323	m_rom4 = m_rom1 + 0xc000;
	1324	m_from = memregion("from")->base();
	1325	m_charom = memregion("charom")->base();
	1326
	1327	// allocate memory
	1328	m_color_ram.allocate(0x800);
	1329	}
	1330
	1331
	1332	//-------------------------------------------------
	1333	// MACHINE_RESET( c64 )
	1334	//-------------------------------------------------
	1335
	1336	void c128_state::machine_reset()
	1337	{
	1338	m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	1339	m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	1340
	1341	m_maincpu->reset();
	1342	m_reset = 1;
	1343
	1344	m_mmu->reset();
	1345	m_cia1->reset();
	1346	m_cia2->reset();
	1347	m_iec->reset();
	1348	m_exp->reset();
	1349	m_user->reset();
	1350	}
	1351
	1352
	1353
	1354	//**************************************************************************
1076	1355	// MACHINE DRIVERS
1077	1356	//**************************************************************************
1078	1357
r18537	r18538
1085	1364	MCFG_CPU_ADD(Z80A_TAG, Z80, VIC6567_CLOCK)
1086	1365	MCFG_CPU_PROGRAM_MAP( z80_mem)
1087	1366	MCFG_CPU_IO_MAP( z80_io)
1088		MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, ~~c128_~~frame_interrupt)
	1367	MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, frame_interrupt)
1089	1368	MCFG_QUANTUM_PERFECT_CPU(Z80A_TAG)
1090	1369
1091	1370	MCFG_CPU_ADD(M8502_TAG, M8502, VIC6567_CLOCK)
1092	1371	MCFG_CPU_PROGRAM_MAP( m8502_mem)
1093	1372	MCFG_CPU_CONFIG( cpu_intf )
1094		MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, ~~c128_~~frame_interrupt)
	1373	MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, frame_interrupt)
1095	1374	MCFG_QUANTUM_PERFECT_CPU(M8502_TAG)
1096	1375
1097	1376	// video hardware
r18537	r18538
1109	1388	// devices
1110	1389	MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
1111	1390	MCFG_MOS8721_ADD(MOS8721_TAG)
1112		MCFG_MOS6526_ADD(MOS6526_1_TAG, VIC6567_CLOCK, 60, c128_cia1_intf)
1113		MCFG_MOS6526_ADD(MOS6526_2_TAG, VIC6567_CLOCK, 60, c128_cia2_intf)
	1391	MCFG_MOS6526_ADD(MOS6526_1_TAG, VIC6567_CLOCK, 60, cia1_intf)
	1392	MCFG_MOS6526_ADD(MOS6526_2_TAG, VIC6567_CLOCK, 60, cia2_intf)
1114	1393	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
1115	1394	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
1116	1395	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
r18537	r18538
1132	1411	MCFG_SOFTWARE_LIST_ADD("from_list", "c128_rom")
1133	1412	MCFG_SOFTWARE_LIST_FILTER("from_list", "NTSC")
1134	1413
	1414	// function ROM
	1415	MCFG_CARTSLOT_ADD("from")
	1416	MCFG_CARTSLOT_EXTENSION_LIST("bin,rom")
	1417	MCFG_CARTSLOT_INTERFACE("c128_rom")
	1418
1135	1419	// internal ram
1136	1420	MCFG_RAM_ADD(RAM_TAG)
1137	1421	MCFG_RAM_DEFAULT_SIZE("128K")
r18537	r18538
1150	1434	//-------------------------------------------------
1151	1435	// MACHINE_CONFIG( c128d )
1152	1436	//-------------------------------------------------
	1437
1153	1438	static MACHINE_CONFIG_DERIVED( c128d, ntsc )
1154	1439	MCFG_CBM_IEC_ADD(cbm_iec_intf, "c1571")
1155	1440	MACHINE_CONFIG_END
r18537	r18538
1192	1477	MCFG_CPU_ADD(Z80A_TAG, Z80, VIC6569_CLOCK)
1193	1478	MCFG_CPU_PROGRAM_MAP( z80_mem)
1194	1479	MCFG_CPU_IO_MAP(z80_io)
1195		MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, ~~c128_~~frame_interrupt)
	1480	MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, frame_interrupt)
1196	1481	MCFG_QUANTUM_PERFECT_CPU(Z80A_TAG)
1197	1482
1198	1483	MCFG_CPU_ADD(M8502_TAG, M8502, VIC6569_CLOCK)
1199	1484	MCFG_CPU_PROGRAM_MAP( m8502_mem)
1200	1485	MCFG_CPU_CONFIG( cpu_intf )
1201		MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, ~~c128_~~frame_interrupt)
	1486	MCFG_CPU_VBLANK_INT_DRIVER(SCREEN_VIC_TAG, c128_state, frame_interrupt)
1202	1487	MCFG_QUANTUM_PERFECT_CPU(M8502_TAG)
1203	1488
1204	1489	// video hardware
r18537	r18538
1216	1501	// devices
1217	1502	MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
1218	1503	MCFG_MOS8721_ADD(MOS8721_TAG)
1219		MCFG_MOS6526_ADD(MOS6526_1_TAG, VIC6569_CLOCK, 50, c128_cia1_intf)
1220		MCFG_MOS6526_ADD(MOS6526_2_TAG, VIC6569_CLOCK, 50, c128_cia2_intf)
	1504	MCFG_MOS6526_ADD(MOS6526_1_TAG, VIC6569_CLOCK, 50, cia1_intf)
	1505	MCFG_MOS6526_ADD(MOS6526_2_TAG, VIC6569_CLOCK, 50, cia2_intf)
1221	1506	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
1222	1507	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
1223	1508	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
r18537	r18538
1239	1524	MCFG_SOFTWARE_LIST_ADD("from_list", "c128_rom")
1240	1525	MCFG_SOFTWARE_LIST_FILTER("from_list", "PAL")
1241	1526
	1527	// function ROM
	1528	MCFG_CARTSLOT_ADD("from")
	1529	MCFG_CARTSLOT_EXTENSION_LIST("bin,rom")
	1530	MCFG_CARTSLOT_INTERFACE("c128_rom")
	1531
1242	1532	// internal ram
1243	1533	MCFG_RAM_ADD(RAM_TAG)
1244	1534	MCFG_RAM_DEFAULT_SIZE("128K")
r18537	r18538
1287	1577	//-------------------------------------------------
1288	1578
1289	1579	ROM_START( c128 )
1290		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1291		ROM_DEFAULT_BIOS("r1")
1292		ROM_SYSTEM_BIOS( 0, "r0", "rev. 0" )
1293		ROMX_LOAD( "318018-02.bin", 0x100000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6), ROM_BIOS(1) ) // BASIC lo
1294		ROMX_LOAD( "318019-02.bin", 0x104000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f), ROM_BIOS(1) ) // BASIC hi
1295		ROMX_LOAD( "318020-03.bin", 0x10c000, 0x4000, CRC(1e94bb02) SHA1(e80ffbafae068cc0e42698ec5c5c39af46ac612a), ROM_BIOS(1) ) // Kernal
1296		ROM_SYSTEM_BIOS( 1, "r1", "rev. 1" )
1297		ROMX_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(2) ) // BASIC lo
1298		ROMX_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(2) ) // BASIC hi
1299		ROMX_LOAD( "318020-05.bin", 0x10c000, 0x4000, CRC(ba456b8e) SHA1(ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab), ROM_BIOS(2) ) // Kernal
	1580	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1581	ROM_DEFAULT_BIOS("r4")
	1582	ROM_LOAD( "251913-01.u32", 0x0000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )
	1583	ROM_SYSTEM_BIOS( 0, "r2", "Revision 2" )
	1584	ROMX_LOAD( "318018-02.u33", 0x4000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6), ROM_BIOS(1) )
	1585	ROMX_LOAD( "318019-02.u34", 0x8000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f), ROM_BIOS(1) )
	1586	ROMX_LOAD( "318020-03.u35", 0xc000, 0x4000, CRC(1e94bb02) SHA1(e80ffbafae068cc0e42698ec5c5c39af46ac612a), ROM_BIOS(1) )
	1587	ROM_SYSTEM_BIOS( 1, "r4", "Revision 4" )
	1588	ROMX_LOAD( "318018-04.u33", 0x4000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(2) )
	1589	ROMX_LOAD( "318019-04.u34", 0x8000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(2) )
	1590	ROMX_LOAD( "318020-05.u35", 0xc000, 0x4000, CRC(ba456b8e) SHA1(ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab), ROM_BIOS(2) )
1300	1591	ROM_SYSTEM_BIOS( 2, "jiffydos", "JiffyDOS v6.01" )
1301		ROMX_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(3) ) // BASIC lo
1302		ROMX_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(3) ) // BASIC hi
1303		ROMX_LOAD( "jiffydos c128.bin", 0x10c000, 0x4000, CRC(4b7964de) SHA1(7d1898f32beae4b2ae610d469ce578a588efaa7c), ROM_BIOS(3) ) // Kernal
	1592	ROMX_LOAD( "318018-04.u33", 0x4000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(3) )
	1593	ROMX_LOAD( "318019-04.u34", 0x8000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(3) )
	1594	ROMX_LOAD( "jiffydos c128.u35", 0xc000, 0x4000, CRC(4b7964de) SHA1(7d1898f32beae4b2ae610d469ce578a588efaa7c), ROM_BIOS(3) )
1304	1595
1305		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1306		ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) ) // Character
	1596	ROM_REGION( 0x8000, "from", 0 )
	1597	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1307	1598
1308		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1599	ROM_REGION( 0x2000, "charom", 0 )
	1600	ROM_LOAD( "390059-01.u18", 0x0000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
1309	1601
1310		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1311		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1602	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1603	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1604	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1312	1605	ROM_END
1313	1606
1314	1607
1315	1608	//-------------------------------------------------
1316		// ROM( c128cr )
1317		//-------------------------------------------------
1318
1319		ROM_START( c128cr )
1320		/* C128CR prototype, owned by Bo Zimmers
1321		PCB markings: "COMMODORE 128CR REV.3 // PCB NO.252270" and "PCB ASSY NO.250783"
1322		Sticker on rom cart shield: "C128CR No.2 // ENG. SAMPLE // Jun/9/'86 KNT"
1323		3 ROMs (combined basic, combined c64/kernal, plain character rom)
1324		6526A-1 CIAs
1325		?prototype? 2568R1X VDC w/ 1186 datecode
1326		*/
1327		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1328		ROM_LOAD( "252343-03.u34", 0x100000, 0x8000, CRC(bc07ed87) SHA1(0eec437994a3f2212343a712847213a8a39f4a7b) ) // BASIC lo + hi, "252343-03 // U34"
1329		ROM_LOAD( "252343-04.u32", 0x108000, 0x8000, CRC(cc6bdb69) SHA1(36286b2e8bea79f7767639fd85e12c5447c7041b) ) // C64 OS ROM + Kernal, "252343-04 // US // U32"
1330		ROM_LOAD( "390059-01.u18", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) ) // Character, "MOS // (C)1985 CBM // 390059-01 // M468613 8547H"
1331
1332		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
1333
1334		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1335		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
1336		ROM_END
1337
1338
1339		//-------------------------------------------------
1340	1609	// ROM( c128ger )
1341	1610	//-------------------------------------------------
1342	1611
1343	1612	ROM_START( c128ger )
1344		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1345		ROM_SYSTEM_BIOS( 0, "default", "rev. 1" )
1346		ROMX_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(1) ) // BASIC lo
1347		ROMX_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(1) ) // BASIC hi
1348		ROMX_LOAD( "315078-02.bin", 0x10c000, 0x4000, CRC(b275bb2e) SHA1(78ac5dcdd840b092ba1ee6d19b33af079613291f), ROM_BIOS(1) ) // Kernal
1349		ROM_SYSTEM_BIOS( 1, "rev0", "rev. 0" )
1350		ROMX_LOAD( "318018-02.bin", 0x100000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6), ROM_BIOS(2) ) // BASIC lo
1351		ROMX_LOAD( "318019-02.bin", 0x104000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f), ROM_BIOS(2) ) // BASIC hi
1352		ROMX_LOAD( "315078-01.bin", 0x10c000, 0x4000, CRC(a51e2168) SHA1(bcf82a89a8fc5d086bec2ff3bcbdecc8af2be3af), ROM_BIOS(2) ) // Kernal
	1613	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1614	ROM_DEFAULT_BIOS("r4")
	1615	ROM_LOAD( "251913-01.u32", 0x0000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) )
	1616	ROM_SYSTEM_BIOS( 0, "r2", "Revision 2" )
	1617	ROMX_LOAD( "318018-02.u33", 0x4000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6), ROM_BIOS(1) )
	1618	ROMX_LOAD( "318019-02.u34", 0x8000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f), ROM_BIOS(1) )
	1619	ROMX_LOAD( "315078-01.u35", 0xc000, 0x4000, CRC(a51e2168) SHA1(bcf82a89a8fc5d086bec2ff3bcbdecc8af2be3af), ROM_BIOS(1) )
	1620	ROM_SYSTEM_BIOS( 1, "r4", "Revision 4" )
	1621	ROMX_LOAD( "318018-04.u33", 0x4000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441), ROM_BIOS(2) )
	1622	ROMX_LOAD( "318019-04.u34", 0x8000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0), ROM_BIOS(2) )
	1623	ROMX_LOAD( "315078-02.u35", 0xc000, 0x4000, CRC(b275bb2e) SHA1(78ac5dcdd840b092ba1ee6d19b33af079613291f), ROM_BIOS(2) )
1353	1624
1354		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1355		ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) ) // Character
	1625	ROM_REGION( 0x8000, "from", 0 )
	1626	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1356	1627
1357		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1628	ROM_REGION( 0x2000, "charom", 0 )
	1629	ROM_LOAD( "390059-01.u18", 0x00000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
1358	1630
1359		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1360		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1631	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1632	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1633	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1361	1634	ROM_END
1362	1635
1363	1636
r18537	r18538
1366	1639	//-------------------------------------------------
1367	1640
1368	1641	ROM_START( c128sfi )
1369		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1370		ROM_LOAD( "318018-02.u33", 0x100000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6) )
1371		ROM_LOAD( "318019-02.u34", 0x104000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f) )
1372		ROM_LOAD( "325182-01.u32", 0x108000, 0x4000, CRC(2aff27d3) SHA1(267654823c4fdf2167050f41faa118218d2569ce) ) // C128 64 Sw/Fi
1373		ROM_LOAD( "325189-01.u35", 0x10c000, 0x4000, CRC(9526fac4) SHA1(a01dd871241c801db51e8ebc30fedfafd8cc506b) ) // C128 Ker Sw/Fi
	1642	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1643	ROM_LOAD( "325182-01.u32", 0x0000, 0x4000, CRC(2aff27d3) SHA1(267654823c4fdf2167050f41faa118218d2569ce) ) // "C128 64 Sw/Fi"
	1644	ROM_LOAD( "318018-02.u33", 0x4000, 0x4000, CRC(2ee6e2fa) SHA1(60e1491e1d5782e3cf109f518eb73427609badc6) )
	1645	ROM_LOAD( "318019-02.u34", 0x8000, 0x4000, CRC(d551fce0) SHA1(4d223883e866645328f86a904b221464682edc4f) )
	1646	ROM_LOAD( "325189-01.u35", 0xc000, 0x4000, CRC(9526fac4) SHA1(a01dd871241c801db51e8ebc30fedfafd8cc506b) ) // "C128 Ker Sw/Fi"
1374	1647
1375		/* This was not included in the submission, unfortunately */
1376		ROM_LOAD( "325181-02.u18", 0x120000, 0x2000, BAD_DUMP CRC(7a70d9b8) SHA1(aca3f7321ee7e6152f1f0afad646ae41964de4fb) ) // C128 Char Sw/Fi
	1648	ROM_REGION( 0x8000, "from", 0 )
	1649	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1377	1650
1378		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1651	ROM_REGION( 0x2000, "charom", 0 )
	1652	ROM_LOAD( "325181-01.bin", 0x0000, 0x2000, CRC(7a70d9b8) SHA1(aca3f7321ee7e6152f1f0afad646ae41964de4fb) ) // "C128 Char Sw/Fi"
1379	1653
1380		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1381		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1654	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1655	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1656	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1382	1657	ROM_END
1383	1658
1384	1659
1385	1660	//-------------------------------------------------
1386		// ROM( c128~~fra~~ )
	1661	// ROM( c128d )
1387	1662	//-------------------------------------------------
1388	1663
1389		ROM_START( c128fra )
1390		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1391		ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, BAD_DUMP CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) ) // BASIC lo
1392		ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, BAD_DUMP CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) ) // BASIC hi
1393		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, BAD_DUMP CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1394		ROM_LOAD( "editor.french.bin", 0x10c000, 0x1000, BAD_DUMP CRC(3e086a24) SHA1(0a2f67455166f8dac101f8f8564a1c0364cb456a) )
1395		ROM_LOAD( "z80bios.bin", 0x10d000, 0x1000, BAD_DUMP CRC(c38d83c6) SHA1(38662a024f1de2f4417a5f9df4898a9985503e06) )
1396		ROM_LOAD( "kernalpart.french.bin", 0x10e000, 0x2000, BAD_DUMP CRC(ca5e1179) SHA1(d234a031caf59a0f66871f2babe1644783e66cf7) )
1397		ROM_LOAD( "325167-01.bin", 0x120000, 0x2000, BAD_DUMP CRC(bad36b88) SHA1(9119b27a1bf885fa4c76fff5d858c74c194dd2b8) )
	1664	#define rom_c128d rom_c128
1398	1665
1399		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
1400	1666
1401		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1402		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
1403		ROM_END
1404
1405
1406	1667	//-------------------------------------------------
1407		// ROM( c128nor )
	1668	// ROM( c128dpr )
1408	1669	//-------------------------------------------------
1409	1670
1410		ROM_START( c128nor )
1411		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1412		ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, BAD_DUMP CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) ) // BASIC lo
1413		ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, BAD_DUMP CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) ) // BASIC hi
1414		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, BAD_DUMP CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1415		ROM_LOAD( "editor.norwegian.bin", 0x10c000, 0x1000, BAD_DUMP CRC(84c55911) SHA1(22f6c5f40d4e895ea51e8432b30c219eacb75778) )
1416		ROM_LOAD( "z80bios.bin", 0x10d000, 0x1000, BAD_DUMP CRC(c38d83c6) SHA1(38662a024f1de2f4417a5f9df4898a9985503e06) )
1417		ROM_LOAD( "kernalpart.norwegian.bin", 0x10e000, 0x2000, BAD_DUMP CRC(3ba48012) SHA1(21a90256a3572a890f8027a085d851bf818b0dda) )
1418		/* standard vic20 based norwegian */
1419		ROM_LOAD( "char.nor", 0x120000, 0x2000, BAD_DUMP CRC(ba95c625) SHA1(5a87faa457979e7b6f434251a9e32f4483b337b3) )
	1671	#define rom_c128dpr rom_c128d
1420	1672
1421		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
1422	1673
1423		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1424		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
1425		ROM_END
1426
1427
1428	1674	//-------------------------------------------------
1429		// ROM( c128d )
	1675	// ROM( c128cr )
1430	1676	//-------------------------------------------------
1431	1677
1432		/* C128D Board is basically the same as C128 + a second board for the disk drive */
1433		ROM_START( c128d )
1434		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1435		ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) ) // BASIC lo
1436		ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) ) // BASIC hi
1437		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1438		ROM_LOAD( "318020-05.bin", 0x10c000, 0x4000, CRC(ba456b8e) SHA1(ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab) ) // Kernal
1439		ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
	1678	ROM_START( c128cr )
	1679	/* C128CR prototype, owned by Bo Zimmers
	1680	PCB markings: "COMMODORE 128CR REV.3 // PCB NO.252270" and "PCB ASSY NO.250783"
	1681	Sticker on rom cart shield: "C128CR No.2 // ENG. SAMPLE // Jun/9/'86 KNT"
	1682	3 ROMs (combined basic, combined c64/kernal, plain character rom)
	1683	6526A-1 CIAs
	1684	?prototype? 2568R1X VDC w/ 1186 datecode
	1685	*/
	1686	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1687	ROM_LOAD( "252343-03.u34", 0x4000, 0x8000, CRC(bc07ed87) SHA1(0eec437994a3f2212343a712847213a8a39f4a7b) ) // "252343-03 // U34"
	1688	ROM_LOAD( "252343-04.u32", 0x0000, 0x4000, CRC(cc6bdb69) SHA1(36286b2e8bea79f7767639fd85e12c5447c7041b) ) // "252343-04 // US // U32"
	1689	ROM_CONTINUE( 0xc000, 0x4000 )
1440	1690
1441		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1691	ROM_REGION( 0x8000, "from", 0 )
	1692	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1442	1693
1443		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1444		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1694	ROM_REGION( 0x2000, "charom", 0 )
	1695	ROM_LOAD( "390059-01.u18", 0x0000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) ) // "MOS // (C)1985 CBM // 390059-01 // M468613 8547H"
	1696
	1697	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1698	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1699	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1445	1700	ROM_END
1446	1701
1447	1702
1448	1703	//-------------------------------------------------
1449		// ROM( c128dpr )
1450		//-------------------------------------------------
1451
1452		#define rom_c128dpr rom_c128d
1453
1454
1455		//-------------------------------------------------
1456	1704	// ROM( c128dcr )
1457	1705	//-------------------------------------------------
1458	1706
1459		/* This BIOS is exactly the same as C128 rev. 1, but on two ROMs only */
1460	1707	ROM_START( c128dcr )
1461		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1462		ROM_LOAD( "318022-02.bin", 0x100000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) ) // BASIC lo + hi
1463		ROM_LOAD( "318023-02.bin", 0x108000, 0x8000, CRC(eedc120a) SHA1(f98c5a986b532c78bb68df9ec6dbcf876913b99f) ) // C64 OS ROM + Kernal
1464		ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) ) // Character
	1708	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1709	ROM_LOAD( "318022-02.u34", 0x4000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) )
	1710	ROM_LOAD( "318023-02.u32", 0x0000, 0x4000, CRC(eedc120a) SHA1(f98c5a986b532c78bb68df9ec6dbcf876913b99f) )
	1711	ROM_CONTINUE( 0xc000, 0x4000 )
1465	1712
1466		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1713	ROM_REGION( 0x8000, "from", 0 )
	1714	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1467	1715
1468		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1469		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1716	ROM_REGION( 0x2000, "charom", 0 )
	1717	ROM_LOAD( "390059-01.u18", 0x0000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
	1718
	1719	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1720	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1721	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1470	1722	ROM_END
1471	1723
1472	1724
r18537	r18538
1475	1727	//-------------------------------------------------
1476	1728
1477	1729	ROM_START( c128drde )
1478		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1479		ROM_LOAD( "318022-02.bin", 0x100000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) ) // BASIC lo + hi
1480		ROM_LOAD( "318077-01.bin", 0x108000, 0x8000, CRC(eb6e2c8f) SHA1(6b3d891fedabb5335f388a5d2a71378472ea60f4) ) // C64 OS ROM + Kernal Ger
1481		ROM_LOAD( "315079-01.bin", 0x120000, 0x2000, CRC(fe5a2db1) SHA1(638f8aff51c2ac4f99a55b12c4f8c985ef4bebd3) )
	1730	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1731	ROM_LOAD( "318022-02.u34", 0x4000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) )
	1732	ROM_LOAD( "318077-01.u32", 0x0000, 0x4000, CRC(eb6e2c8f) SHA1(6b3d891fedabb5335f388a5d2a71378472ea60f4) )
	1733	ROM_CONTINUE( 0xc000, 0x4000 )
1482	1734
1483		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1735	ROM_REGION( 0x8000, "from", 0 )
	1736	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1484	1737
1485		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1486		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1738	ROM_REGION( 0x2000, "charom", 0 )
	1739	ROM_LOAD( "315079-01.u18", 0x0000, 0x2000, CRC(fe5a2db1) SHA1(638f8aff51c2ac4f99a55b12c4f8c985ef4bebd3) )
	1740
	1741	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1742	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1743	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1487	1744	ROM_END
1488	1745
1489	1746
r18537	r18538
1492	1749	//-------------------------------------------------
1493	1750
1494	1751	ROM_START( c128drsw )
1495		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1496		ROM_LOAD( "318022-02.bin", 0x100000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) ) // BASIC lo + hi
1497		ROM_LOAD( "318034-01.bin", 0x108000, 0x8000, CRC(cb4e1719) SHA1(9b0a0cef56d00035c611e07170f051ee5e63aa3a) ) // C64 OS ROM + Kernal Sw/Fi
1498		ROM_LOAD( "325181-01.bin", 0x120000, 0x2000, CRC(7a70d9b8) SHA1(aca3f7321ee7e6152f1f0afad646ae41964de4fb) )
	1752	ROM_REGION( 0x10000, M8502_TAG, 0 )
	1753	ROM_LOAD( "318022-02.u34", 0x4000, 0x8000, CRC(af1ae1e8) SHA1(953dcdf5784a6b39ef84dd6fd968c7a03d8d6816) )
	1754	ROM_LOAD( "318034-01.u32", 0x0000, 0x4000, CRC(cb4e1719) SHA1(9b0a0cef56d00035c611e07170f051ee5e63aa3a) )
	1755	ROM_CONTINUE( 0xc000, 0x4000 )
1499	1756
1500		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
	1757	ROM_REGION( 0x8000, "from", 0 )
	1758	ROM_CART_LOAD( "from", 0x0000, 0x8000, ROM_NOMIRROR )
1501	1759
1502		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1503		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
1504		ROM_END
	1760	ROM_REGION( 0x2000, "charom", 0 )
	1761	ROM_LOAD( "325181-01.u18", 0x0000, 0x2000, CRC(7a70d9b8) SHA1(aca3f7321ee7e6152f1f0afad646ae41964de4fb) )
1505	1762
1506
1507		//-------------------------------------------------
1508		// ROM( c128drit )
1509		//-------------------------------------------------
1510
1511		ROM_START( c128drit )
1512		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1513		ROM_LOAD( "318022-01.bin", 0x100000, 0x8000, CRC(e857df90) SHA1(5c2d7bbda2c3f9a926bd76ad19dc0c8c733c41cd) ) // BASIC lo + hi - based on BASIC rev.0
1514		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, BAD_DUMP CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1515		ROM_LOAD( "editor.italian.bin", 0x10c000, 0x1000, BAD_DUMP CRC(8df58148) SHA1(39add4c0adda7a64f68a09ae8742599091228017) )
1516		ROM_LOAD( "z80bios.bin", 0x10d000, 0x1000, BAD_DUMP CRC(c38d83c6) SHA1(38662a024f1de2f4417a5f9df4898a9985503e06) )
1517		ROM_LOAD( "kernalpart.italian.bin", 0x10e000, 0x2000, BAD_DUMP CRC(7b0d2140) SHA1(f5d604d89daedb47a1abe4b0aa41ea762829e71e) )
1518		ROM_LOAD( "325167-01.bin", 0x120000, 0x2000, BAD_DUMP CRC(bad36b88) SHA1(9119b27a1bf885fa4c76fff5d858c74c194dd2b8) )
1519
1520		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
1521
1522		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1523		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
	1763	ROM_REGION( 0xc88, MOS8721_TAG, 0 )
	1764	// converted from http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c128/8721-reduced.zip/8721-reduced.txt
	1765	ROM_LOAD( "8721r3.u11", 0x000, 0xc88, BAD_DUMP CRC(154db186) SHA1(ccadcdb1db3b62c51dc4ce60fe6f96831586d297) )
1524	1766	ROM_END
1525	1767
1526	1768
r18537	r18538
1528	1770	// ROM( c128d81 )
1529	1771	//-------------------------------------------------
1530	1772
1531		ROM_START( c128d81 )
1532		ROM_REGION( 0x132800, Z80A_TAG, 0 )
1533		ROM_LOAD( "318018-04.bin", 0x100000, 0x4000, CRC(9f9c355b) SHA1(d53a7884404f7d18ebd60dd3080c8f8d71067441) ) // BASIC lo
1534		ROM_LOAD( "318019-04.bin", 0x104000, 0x4000, CRC(6e2c91a7) SHA1(c4fb4a714e48a7bf6c28659de0302183a0e0d6c0) ) // BASIC hi
1535		ROM_LOAD( "251913-01.bin", 0x108000, 0x4000, CRC(0010ec31) SHA1(765372a0e16cbb0adf23a07b80f6b682b39fbf88) ) // C64 OS ROM
1536		ROM_LOAD( "318020-05.bin", 0x10c000, 0x4000, CRC(ba456b8e) SHA1(ceb6e1a1bf7e08eb9cbc651afa29e26adccf38ab) ) // Kernal
1537		ROM_LOAD( "390059-01.bin", 0x120000, 0x2000, CRC(6aaaafe6) SHA1(29ed066d513f2d5c09ff26d9166ba23c2afb2b3f) )
	1773	#define rom_c128d81 rom_c128d
1538	1774
1539		ROM_REGION( 0x10000, M8502_TAG, ROMREGION_ERASEFF )
1540	1775
1541		ROM_REGION( 0x100, MOS8721_TAG, 0 )
1542		ROM_LOAD( "8721r3.u11", 0x000, 0x100, NO_DUMP )
1543		ROM_END
1544	1776
1545
1546
1547	1777	//**************************************************************************
1548	1778	// SYSTEM DRIVERS
1549	1779	//**************************************************************************
1550	1780
1551	1781	// YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS
1552		COMP( 1985, c128, 0, 0, c128, c128, c128_state, c128, "Commodore Business Machines", "Commodore 128 (NTSC)", 0)
1553		COMP( 1985, c128cr, c128, 0, c128, c128, c128_state, c128, "Commodore Business Machines", "Commodore 128CR (NTSC, prototype?)", 0)
	1782	COMP( 1985, c128, 0, 0, c128, c128, driver_device, 0, "Commodore Business Machines", "Commodore 128 (NTSC)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1783	COMP( 1985, c128sfi, c128, 0, c128pal, c128swe, driver_device, 0, "Commodore Business Machines", "Commodore 128 (Sweden/Finland)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1784	//COMP( 1985, c128fra, c128, 0, c128pal, c128fra, driver_device, 0, "Commodore Business Machines", "Commodore 128 (France)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1785	COMP( 1985, c128ger, c128, 0, c128pal, c128ger, driver_device, 0, "Commodore Business Machines", "Commodore 128 (Germany)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1786	//COMP( 1985, c128nor, c128, 0, c128pal, c128ita, driver_device, 0, "Commodore Business Machines", "Commodore 128 (Norway)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1787	COMP( 1985, c128dpr, c128, 0, c128d, c128, driver_device, 0, "Commodore Business Machines", "Commodore 128D (NTSC, prototype)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1788	COMP( 1985, c128d, c128, 0, c128dpal, c128, driver_device, 0,"Commodore Business Machines", "Commodore 128D (PAL)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
1554	1789
1555		COMP( 1985, c128sfi, c128, 0, c128pal, c128swe, c128_state, c128pal, "Commodore Business Machines", "Commodore 128 (Sweden/Finland)", 0)
1556		COMP( 1985, c128fra, c128, 0, c128pal, c128fra, c128_state, c128pal, "Commodore Business Machines", "Commodore 128 (France)", 0)
1557		COMP( 1985, c128ger, c128, 0, c128pal, c128ger, c128_state, c128pal, "Commodore Business Machines", "Commodore 128 (Germany)", 0)
1558		COMP( 1985, c128nor, c128, 0, c128pal, c128ita, c128_state, c128pal, "Commodore Business Machines", "Commodore 128 (Norway)", 0)
1559		// we miss other countries: Spain, Belgium, etc.
1560
1561		// the following drivers use a 1571 floppy drive
1562		COMP( 1985, c128dpr, c128, 0, c128d, c128, c128_state, c128d, "Commodore Business Machines", "Commodore 128D (NTSC, prototype)", GAME_NOT_WORKING )
1563		COMP( 1985, c128d, c128, 0, c128dpal, c128, c128_state, c128dpal,"Commodore Business Machines", "Commodore 128D (PAL)", GAME_NOT_WORKING )
1564
1565		// the following drivers use a 1571CR floppy drive
1566		COMP( 1986, c128dcr, c128, 0, c128dcr, c128, c128_state, c128dcr, "Commodore Business Machines", "Commodore 128DCR (NTSC)", GAME_NOT_WORKING)
1567		COMP( 1986, c128drde, c128, 0, c128dcrp, c128ger, c128_state, c128dcrp,"Commodore Business Machines", "Commodore 128DCR (Germany)", GAME_NOT_WORKING)
1568		COMP( 1986, c128drit, c128, 0, c128dcrp, c128ita, c128_state, c128dcrp,"Commodore Business Machines", "Commodore 128DCR (Italy)", GAME_NOT_WORKING)
1569		COMP( 1986, c128drsw, c128, 0, c128dcrp, c128swe, c128_state, c128dcrp,"Commodore Business Machines", "Commodore 128DCR (Sweden/Finland)", GAME_NOT_WORKING)
1570
1571		// the following driver is a c128 with 1581 floppy drive. it allows us to document 1581 firmware dumps, but it does not do much more
1572		COMP( 1986, c128d81, c128, 0, c128d81, c128, c128_state, c128d81, "Commodore Business Machines", "Commodore 128D/81 (NTSC, prototype)", GAME_NOT_WORKING)
	1790	COMP( 1985, c128cr, c128, 0, c128, c128, driver_device, 0, "Commodore Business Machines", "Commodore 128CR (NTSC, prototype?)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1791	COMP( 1986, c128dcr, c128, 0, c128dcr, c128, driver_device, 0, "Commodore Business Machines", "Commodore 128DCR (NTSC)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1792	COMP( 1986, c128drde, c128, 0, c128dcrp, c128ger, driver_device, 0,"Commodore Business Machines", "Commodore 128DCR (Germany)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1793	//COMP( 1986, c128drit, c128, 0, c128dcrp, c128ita, driver_device, 0,"Commodore Business Machines", "Commodore 128DCR (Italy)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1794	COMP( 1986, c128drsw, c128, 0, c128dcrp, c128swe, driver_device, 0,"Commodore Business Machines", "Commodore 128DCR (Sweden/Finland)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )
	1795	COMP( 1986, c128d81, c128, 0, c128d81, c128, driver_device, 0, "Commodore Business Machines", "Commodore 128D/81 (NTSC, prototype)", GAME_NOT_WORKING \| GAME_SUPPORTS_SAVE )

trunk/src/mess/mess.mak
r18537	r18538
893	893	$(MESS_DRIVERS)/c65.o \
894	894	$(MESS_MACHINE)/c65.o \
895	895	$(MESS_DRIVERS)/c128.o \
896		$(MESS_MACHINE)/c128.o \
897	896	$(MESS_MACHINE)/c128_comal80.o \
898	897	$(MESS_MACHINE)/cbmiec.o \
899	898	$(MESS_MACHINE)/c1541.o \

trunk/src/mess/machine/c128.c
r18537	r18538
1		/***************************************************************************
2
3		commodore c128 home computer
4
5		peter.trauner@jk.uni-linz.ac.at
6		documentation:
7		iDOC (http://www.softwolves.pp.se/idoc)
8		Christian Janoff mepk@c64.org
9
10		***************************************************************************/
11
12		#include "emu.h"
13		#include "includes/c128.h"
14		#include "includes/c64_legacy.h"
15		#include "includes/cbm.h"
16		#include "machine/cbmiec.h"
17		#include "cpu/m6502/m6502.h"
18		#include "imagedev/cassette.h"
19		#include "machine/6526cia.h"
20		#include "sound/sid6581.h"
21		#include "video/mos6566.h"
22		#include "video/mc6845.h"
23
24		#define MMU_PAGE1 ((((m_mmu_reg[10]&0xf)<<8)\|m_mmu_reg[9])<<8)
25		#define MMU_PAGE0 ((((m_mmu_reg[8]&0xf)<<8)\|m_mmu_reg[7])<<8)
26		#define MMU_VIC_ADDR ((m_mmu_reg[6]&0xc0)<<10)
27		#define MMU_RAM_RCR_ADDR ((m_mmu_reg[6]&0x30)<<14)
28		#define MMU_SIZE (c128_mmu_helper[m_mmu_reg[6]&3])
29		#define MMU_BOTTOM (m_mmu_reg[6]&4)
30		#define MMU_TOP (m_mmu_reg[6]&8)
31		#define MMU_CPU8502 (m_mmu_reg[5]&1) /* else z80 */
32		/* fastio output (c128_mmu[5]&8) else input */
33		#define MMU_FSDIR (m_mmu_reg[5]&0x08)
34		#define MMU_GAME_IN (m_mmu_reg[5]&0x10)
35		#define MMU_EXROM_IN (m_mmu_reg[5]&0x20)
36		#define MMU_64MODE (m_mmu_reg[5]&0x40)
37		#define MMU_40_IN (m_mmu_reg[5]&0x80)
38
39		#define MMU_RAM_CR_ADDR ((m_mmu_reg[0]&0xc0)<<10)
40		#define MMU_RAM_LO (m_mmu_reg[0]&2) /* else rom at 0x4000 */
41		#define MMU_RAM_MID ((m_mmu_reg[0]&0xc)==0xc) /* 0x8000 - 0xbfff */
42		#define MMU_ROM_MID ((m_mmu_reg[0]&0xc)==0)
43		#define MMU_EXTERNAL_ROM_MID ((m_mmu_reg[0]&0xc)==8)
44		#define MMU_INTERNAL_ROM_MID ((m_mmu_reg[0]&0xc)==4)
45
46		#define MMU_IO_ON (!(m_mmu_reg[0]&1)) /* io window at 0xd000 */
47		#define MMU_ROM_HI ((m_mmu_reg[0]&0x30)==0) /* rom at 0xc000 */
48		#define MMU_EXTERNAL_ROM_HI ((m_mmu_reg[0]&0x30)==0x20)
49		#define MMU_INTERNAL_ROM_HI ((m_mmu_reg[0]&0x30)==0x10)
50		#define MMU_RAM_HI ((m_mmu_reg[0]&0x30)==0x30)
51
52		#define MMU_RAM_ADDR (MMU_RAM_RCR_ADDR\|MMU_RAM_CR_ADDR)
53
54		static const int c128_mmu_helper[4] =
55		{0x400, 0x1000, 0x2000, 0x4000};
56
57		#define VERBOSE_LEVEL 0
58		#define DBG_LOG( MACHINE, N, M, A ) \
59		do { \
60		if(VERBOSE_LEVEL >= N) \
61		{ \
62		if( M ) \
63		logerror("%11.6f: %-24s", MACHINE.time().as_double(), (char*) M ); \
64		logerror A; \
65		} \
66		} while (0)
67
68		/*
69		two cpus share 1 memory system, only 1 cpu can run
70		controller is the mmu
71
72		mame has different memory subsystems for each cpu
73		*/
74
75
76		/* m8502 port
77		in c128 mode
78		bit 0 color
79		bit 1 lores
80		bit 2 hires
81		3 textmode
82		5 graphics (turned on ram at 0x1000 for video chip
83		*/
84
85
86
87
88
89
90
91		void c128_state::nmi()
92		{
93		if (m_nmilevel != (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq) /* KEY_RESTORE */
94		{
95		if (1) // this was never valid, there is no active CPU during a timer firing! cpu_getactivecpu() == 0)
96		{
97		/* z80 */
98		m_maincpu->set_input_line(INPUT_LINE_NMI, (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq);
99		}
100		else
101		{
102		m_subcpu->set_input_line(INPUT_LINE_NMI, (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq);
103		}
104
105		m_nmilevel = (ioport("SPECIAL")->read() & 0x80) \|\| m_cia1_irq;
106		}
107		}
108
109		/***********************************************
110
111		CIA Interfaces
112
113		***********************************************/
114
115		/*
116		* CIA 0 - Port A keyboard line select
117		* CIA 0 - Port B keyboard line read
118		*
119		* flag cassette read input, serial request in
120		* irq to irq connected
121		*
122		* see machine/cbm.c
123		*/
124
125		READ8_MEMBER( c128_state::cia1_pa_r )
126		{
127		UINT8 cia0portb = m_cia1->pb_r();
128
129		return cbm_common_cia0_port_a_r(m_cia1, cia0portb);
130		}
131
132		READ8_MEMBER( c128_state::cia1_pb_r )
133		{
134		UINT8 value = 0xff;
135		UINT8 cia0porta = m_cia1->pa_r();
136		//vic2e_device_interface intf = dynamic_cast<vic2e_device_interface>(&m_vic);
137
138		value &= cbm_common_cia0_port_b_r(m_cia1, cia0porta);
139		/*
140		if (!intf->k0_r())
141		value &= m_keyline[0];
142		if (!intf->k1_r())
143		value &= m_keyline[1];
144		if (!intf->k2_r())
145		value &= m_keyline[2];
146		*/
147		return value;
148		}
149
150		WRITE8_MEMBER( c128_state::cia1_pb_w )
151		{
152		m_vic->lp_w(BIT(data, 4));
153		}
154
155		void c128_state::irq(int level)
156		{
157		if (level != m_old_level)
158		{
159		DBG_LOG(machine(), 3, "mos6510", ("irq %s\n", level ? "start" : "end"));
160
161		if (0) // && (cpu_getactivecpu() == 0))
162		{
163		m_maincpu->set_input_line(0, level);
164		}
165		else
166		{
167		m_subcpu->set_input_line(M6510_IRQ_LINE, level);
168		}
169
170		m_old_level = level;
171		}
172		}
173
174		WRITE_LINE_MEMBER( c128_state::cia1_irq_w )
175		{
176		m_cia1_irq = state;
177
178		irq(state \|\| m_vicirq);
179		}
180
181		WRITE_LINE_MEMBER( c128_state::vic_interrupt )
182		{
183		if (state != m_vicirq)
184		{
185		irq(state \|\| m_cia1_irq);
186		m_vicirq = state;
187		}
188		}
189
190		void c128_state::iec_data_out_w()
191		{
192		int data = !m_data_out;
193
194		/* fast serial data */
195		if (MMU_FSDIR) data &= m_sp1;
196
197		m_iec->data_w(data);
198		}
199
200		void c128_state::iec_srq_out_w()
201		{
202		int srq = 1;
203
204		/* fast serial clock */
205		if (MMU_FSDIR) srq &= m_cnt1;
206
207		m_iec->srq_w(srq);
208		}
209
210		WRITE_LINE_MEMBER( c128_state::cia1_cnt_w )
211		{
212		/* fast clock out */
213		m_cnt1 = state;
214
215		iec_srq_out_w();
216		}
217
218		WRITE_LINE_MEMBER( c128_state::cia1_sp_w )
219		{
220		/* fast data out */
221		m_sp1 = state;
222
223		iec_data_out_w();
224		}
225
226		const mos6526_interface c128_cia1_intf =
227		{
228		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_irq_w),
229		DEVCB_NULL, /* pc_func */
230		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_cnt_w),
231		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_sp_w),
232		DEVCB_DRIVER_MEMBER(c128_state, cia1_pa_r),
233		DEVCB_NULL,
234		DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_r),
235		DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_w)
236		};
237
238		WRITE_LINE_MEMBER( c128_state::iec_srq_w )
239		{
240		m_cia1->cnt_w(MMU_FSDIR \|\| state);
241		}
242
243		WRITE_LINE_MEMBER( c128_state::iec_data_w )
244		{
245		m_cia1->sp_w(MMU_FSDIR \|\| state);
246		}
247
248		/*
249		* CIA 1 - Port A
250		* bit 7 serial bus data input
251		* bit 6 serial bus clock input
252		* bit 5 serial bus data output
253		* bit 4 serial bus clock output
254		* bit 3 serial bus atn output
255		* bit 2 rs232 data output
256		* bits 1-0 vic-chip system memory bank select
257		*
258		* CIA 1 - Port B
259		* bit 7 user rs232 data set ready
260		* bit 6 user rs232 clear to send
261		* bit 5 user
262		* bit 4 user rs232 carrier detect
263		* bit 3 user rs232 ring indicator
264		* bit 2 user rs232 data terminal ready
265		* bit 1 user rs232 request to send
266		* bit 0 user rs232 received data
267		*
268		* flag restore key or rs232 received data input
269		* irq to nmi connected ?
270		*/
271		READ8_MEMBER( c128_state::cia2_pa_r )
272		{
273		UINT8 value = 0xff;
274
275		if (!m_iec->clk_r())
276		value &= ~0x40;
277
278		if (!m_iec->data_r())
279		value &= ~0x80;
280
281		return value;
282		}
283
284		WRITE8_MEMBER( c128_state::cia2_pa_w )
285		{
286		static const int helper[4] = {0xc000, 0x8000, 0x4000, 0x0000};
287
288		m_data_out = BIT(data, 5);
289		iec_data_out_w();
290
291		m_iec->clk_w(!BIT(data, 4));
292
293		m_iec->atn_w(!BIT(data, 3));
294
295		m_vicaddr = m_memory + helper[data & 0x03];
296		m_c128_vicaddr = m_memory + helper[data & 0x03] + m_va1617;
297
298		// VIC banking
299		m_va14 = BIT(data, 0);
300		m_va15 = BIT(data, 1);
301		}
302
303		WRITE_LINE_MEMBER( c128_state::cia2_irq_w )
304		{
305		nmi();
306		}
307
308		const mos6526_interface c128_cia2_intf =
309		{
310		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia2_irq_w),
311		DEVCB_NULL, /* pc_func */
312		DEVCB_NULL,
313		DEVCB_NULL,
314		DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_r),
315		DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_w),
316		DEVCB_NULL,
317		DEVCB_NULL
318		};
319
320		/***********************************************
321
322		Memory Handlers
323
324		***********************************************/
325		WRITE8_MEMBER( c128_state::dma8726_port_w )
326		{
327		DBG_LOG(machine(), 1, "dma write", ("%.3x %.2x\n",offset,data));
328		}
329
330		READ8_MEMBER( c128_state::dma8726_port_r )
331		{
332		DBG_LOG(machine(), 1, "dma read", ("%.3x\n",offset));
333		return 0xff;
334		}
335
336		WRITE8_MEMBER( c128_state::write_d000 )
337		{
338		UINT8 c64_port6510 = m6510_get_port(m_subcpu);
339
340		if (!m_write_io)
341		{
342		if (offset + 0xd000 >= m_ram_top)
343		m_memory[0xd000 + offset] = data;
344		else
345		m_ram_ptr[0xd000 + offset] = data;
346		}
347		else
348		{
349		switch ((offset&0xf00)>>8)
350		{
351		case 0:case 1: case 2: case 3:
352		m_vic->write(space, offset & 0x3f, data);
353		break;
354		case 4:
355		m_sid->write(space, offset & 0x3f, data);
356		break;
357		case 5:
358		mmu8722_port_w(space, offset & 0xff, data);
359		break;
360		case 6: case 7:
361		if (offset & 0x01)
362		m_vdc->register_w(space, 0, data);
363		else
364		m_vdc->address_w(space, 0, data);
365		break;
366		case 8: case 9: case 0xa: case 0xb:
367		if (m_c64mode)
368		m_colorram[(offset & 0x3ff)] = data \| 0xf0;
369		else
370		m_colorram[(offset & 0x3ff)\|((c64_port6510&3)<<10)] = data \| 0xf0; // maybe all 8 bit connected!
371		break;
372		case 0xc:
373		m_cia1->write(space, offset & 0x0f, data);
374		break;
375		case 0xd:
376		m_cia2->write(space, offset & 0x0f, data);
377		break;
378		case 0xf:
379		dma8726_port_w(space, offset&0xff,data);
380		break;
381		case 0xe:
382		DBG_LOG(machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
383		break;
384		}
385		}
386		}
387
388
389
390		READ8_MEMBER( c128_state::read_io )
391		{
392		if (offset < 0x400)
393		return m_vic->read(space, offset & 0x3f);
394		else if (offset < 0x500)
395		return m_sid->read(space, offset & 0xff);
396		else if (offset < 0x600)
397		return mmu8722_port_r(space, offset & 0xff);
398		else if (offset < 0x800)
399		if (offset & 0x01)
400		return m_vdc->register_r(space, 0);
401		else
402		return m_vdc->status_r(space, 0);
403		else if (offset < 0xc00)
404		return m_colorram[offset & 0x3ff];
405		else if (offset == 0xc00)
406		{
407		//cia_set_port_mask_value(m_cia1, 0, ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[8] : c64_keyline[9] );
408		return m_cia1->read(space, offset & 0x0f);
409		}
410		else if (offset == 0xc01)
411		{
412		//cia_set_port_mask_value(m_cia1, 1, ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[9] : c64_keyline[8] );
413		return m_cia1->read(space, offset & 0x0f);
414		}
415		else if (offset < 0xd00)
416		return m_cia1->read(space, offset & 0x0f);
417		else if (offset < 0xe00)
418		return m_cia2->read(space, offset & 0x0f);
419		else if ((offset >= 0xf00) & (offset <= 0xfff))
420		return dma8726_port_r(space, offset&0xff);
421		DBG_LOG(machine(), 1, "io read", ("%.3x\n", offset));
422		return 0xff;
423		}
424
425		void c128_state::bankswitch_64(int reset)
426		{
427		int data, loram, hiram, charen;
428
429		if (!m_c64mode)
430		return;
431
432		data = m6510_get_port(m_subcpu) & 0x07;
433		if ((m_old_data == data) && (m_old_exrom == m_exrom) && (m_old_game == m_game) && !reset)
434		return;
435
436		DBG_LOG(machine(), 1, "bankswitch", ("%d\n", data & 7));
437		loram = (data & 1) ? 1 : 0;
438		hiram = (data & 2) ? 1 : 0;
439		charen = (data & 4) ? 1 : 0;
440
441		if ((!m_game && m_exrom) \|\| (loram && hiram && !m_exrom))
442		membank("bank8")->set_base(m_roml);
443		else
444		membank("bank8")->set_base(m_memory + 0x8000);
445
446		if ((!m_game && m_exrom && hiram) \|\| (!m_exrom))
447		membank("bank9")->set_base(m_romh);
448		else if (loram && hiram)
449		membank("bank9")->set_base(m_basic);
450		else
451		membank("bank9")->set_base(m_memory + 0xa000);
452
453		if ((!m_game && m_exrom) \|\| (charen && (loram \|\| hiram)))
454		{
455		m_subcpu->space(AS_PROGRAM).install_read_handler(0xd000, 0xdfff, read8_delegate(FUNC(c128_state::read_io), this));
456		m_write_io = 1;
457		}
458		else
459		{
460		m_subcpu->space(AS_PROGRAM).install_read_bank(0xd000, 0xdfff, "bank5");
461		m_write_io = 0;
462		if ((!charen && (loram \|\| hiram)))
463		membank("bank13")->set_base(m_chargen);
464		else
465		membank("bank13")->set_base(m_memory + 0xd000);
466		}
467
468		if (!m_game && m_exrom)
469		{
470		membank("bank14")->set_base(m_romh);
471		membank("bank15")->set_base(m_romh+0x1f00);
472		membank("bank16")->set_base(m_romh+0x1f05);
473		}
474		else
475		{
476		if (hiram)
477		{
478		membank("bank14")->set_base(m_kernal);
479		membank("bank15")->set_base(m_kernal+0x1f00);
480		membank("bank16")->set_base(m_kernal+0x1f05);
481		}
482		else
483		{
484		membank("bank14")->set_base(m_memory + 0xe000);
485		membank("bank15")->set_base(m_memory + 0xff00);
486		membank("bank16")->set_base(m_memory + 0xff05);
487		}
488		}
489		m_old_data = data;
490		m_old_exrom = m_exrom;
491		m_old_game =m_game;
492		}
493
494		/* typical z80 configuration
495		0x3f 0x3f 0x7f 0x3e 0x7e 0xb0 0x0b 0x00 0x00 0x01 0x00 */
496		void c128_state::bankswitch_z80()
497		{
498		m_ram_ptr = m_memory + MMU_RAM_ADDR;
499		m_va1617 = MMU_VIC_ADDR;
500		#if 1
501		membank("bank10")->set_base(m_z80);
502		membank("bank11")->set_base(m_ram_ptr + 0x1000);
503		if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
504		\|\| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
505		m_ram_ptr = NULL;
506		#else
507		if (MMU_BOTTOM)
508		m_ram_bottom = MMU_SIZE;
509		else
510		m_ram_bottom = 0;
511
512		if (MMU_RAM_ADDR==0) { /* this is used in z80 mode for rom on/off switching !*/
513		membank("bank10")->set_base(m_z80);
514		membank("bank11")->set_base(m_z80 + 0x400);
515		}
516		else
517		{
518		membank("bank10")->set_base((m_ram_bottom > 0 ? m_memory : m_ram));
519		membank("bank11")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram) + 0x400);
520		}
521
522		membank("bank1")->set_base((m_ram_bottom > 0 ? m_memory : m_ram));
523		membank("bank2")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram) + 0x400);
524
525		membank("bank3")->set_base((m_ram_bottom > 0x1000 ? m_memory : m_ram) + 0x1000);
526		membank("bank4")->set_base((m_ram_bottom > 0x2000 ? m_memory : m_ram) + 0x2000);
527		membank("bank5")->set_base(m_ram + 0x4000);
528
529		if (MMU_TOP)
530		m_ram_top = 0x10000 - MMU_SIZE;
531		else
532		m_ram_top = 0x10000;
533
534		if (m_ram_top > 0xc000)
535		membank("bank6")->set_base(m_ram + 0xc000);
536		else
537		membank("bank6")->set_base(m_memory + 0xc000);
538
539		if (m_ram_top > 0xe000)
540		membank("bank7")->set_base(m_ram + 0xe000);
541		else
542		membank("bank7")->set_base(m_memory + 0xd000);
543
544		if (m_ram_top > 0xf000)
545		membank("bank8")->set_base(m_ram + 0xf000);
546		else
547		membank("bank8")->set_base(m_memory + 0xe000);
548
549		if (m_ram_top > 0xff05)
550		membank("bank9")->set_base(m_ram + 0xff05);
551		else
552		membank("bank9")->set_base(m_memory + 0xff05);
553
554		if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
555		\|\| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
556		m_ram = NULL;
557		#endif
558		}
559
560		void c128_state::bankswitch_128(int reset)
561		{
562		m_c64mode = MMU_64MODE;
563		if (m_c64mode)
564		{
565		/* mmu works also in c64 mode, but this can wait */
566		m_ram_ptr = m_memory;
567		m_va1617 = 0;
568		m_ram_bottom = 0;
569		m_ram_top = 0x10000;
570
571		membank("bank1")->set_base(m_memory);
572		membank("bank2")->set_base(m_memory + 0x100);
573
574		membank("bank3")->set_base(m_memory + 0x200);
575		membank("bank4")->set_base(m_memory + 0x400);
576		membank("bank5")->set_base(m_memory + 0x1000);
577		membank("bank6")->set_base(m_memory + 0x2000);
578
579		membank("bank7")->set_base(m_memory + 0x4000);
580
581		membank("bank12")->set_base(m_memory + 0xc000);
582
583		bankswitch_64(reset);
584		}
585		else
586		{
587		m_ram_ptr = m_memory + MMU_RAM_ADDR;
588		m_va1617 = MMU_VIC_ADDR;
589		membank("bank1")->set_base(m_memory + m_mmu_page0);
590		membank("bank2")->set_base(m_memory + m_mmu_page1);
591		if (MMU_BOTTOM)
592		{
593		m_ram_bottom = MMU_SIZE;
594		}
595		else
596		m_ram_bottom = 0;
597		membank("bank3")->set_base((m_ram_bottom > 0x200 ? m_memory : m_ram_ptr) + 0x200);
598		membank("bank4")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram_ptr) + 0x400);
599		membank("bank5")->set_base((m_ram_bottom > 0x1000 ? m_memory : m_ram_ptr) + 0x1000);
600		membank("bank6")->set_base((m_ram_bottom > 0x2000 ? m_memory : m_ram_ptr) + 0x2000);
601
602		if (MMU_RAM_LO)
603		{
604		membank("bank7")->set_base(m_ram_ptr + 0x4000);
605		}
606		else
607		{
608		membank("bank7")->set_base(m_c128_basic);
609		}
610
611		if (MMU_RAM_MID)
612		{
613		membank("bank8")->set_base(m_ram_ptr + 0x8000);
614		membank("bank9")->set_base(m_ram_ptr + 0xa000);
615		}
616		else if (MMU_ROM_MID)
617		{
618		membank("bank8")->set_base(m_c128_basic + 0x4000);
619		membank("bank9")->set_base(m_c128_basic + 0x6000);
620		}
621		else if (MMU_INTERNAL_ROM_MID)
622		{
623		membank("bank8")->set_base(m_internal_function);
624		membank("bank9")->set_base(m_internal_function + 0x2000);
625		}
626		else
627		{
628		membank("bank8")->set_base(m_external_function);
629		membank("bank9")->set_base(m_external_function + 0x2000);
630		}
631
632		if (MMU_TOP)
633		{
634		m_ram_top = 0x10000 - MMU_SIZE;
635		}
636		else
637		m_ram_top = 0x10000;
638
639		m_subcpu->space(AS_PROGRAM).install_read_handler(0xff00, 0xff04, read8_delegate(FUNC(c128_state::mmu8722_ff00_r), this));
640
641		if (MMU_IO_ON)
642		{
643		m_write_io = 1;
644		m_subcpu->space(AS_PROGRAM).install_read_handler(0xd000, 0xdfff, read8_delegate(FUNC(c128_state::read_io), this));
645		}
646		else
647		{
648		m_write_io = 0;
649		m_subcpu->space(AS_PROGRAM).install_read_bank(0xd000, 0xdfff, "bank13");
650		}
651
652
653		if (MMU_RAM_HI)
654		{
655		if (m_ram_top > 0xc000)
656		{
657		membank("bank12")->set_base(m_ram_ptr + 0xc000);
658		}
659		else
660		{
661		membank("bank12")->set_base(m_memory + 0xc000);
662		}
663		if (!MMU_IO_ON)
664		{
665		if (m_ram_top > 0xd000)
666		{
667		membank("bank13")->set_base(m_ram_ptr + 0xd000);
668		}
669		else
670		{
671		membank("bank13")->set_base(m_memory + 0xd000);
672		}
673		}
674		if (m_ram_top > 0xe000)
675		{
676		membank("bank14")->set_base(m_ram_ptr + 0xe000);
677		}
678		else
679		{
680		membank("bank14")->set_base(m_memory + 0xe000);
681		}
682		if (m_ram_top > 0xff05)
683		{
684		membank("bank16")->set_base(m_ram_ptr + 0xff05);
685		}
686		else
687		{
688		membank("bank16")->set_base(m_memory + 0xff05);
689		}
690		}
691		else if (MMU_ROM_HI)
692		{
693		membank("bank12")->set_base(m_editor);
694		if (!MMU_IO_ON) {
695		membank("bank13")->set_base(m_c128_chargen);
696		}
697		membank("bank14")->set_base(m_c128_kernal);
698		membank("bank16")->set_base(m_c128_kernal + 0x1f05);
699		}
700		else if (MMU_INTERNAL_ROM_HI)
701		{
702		membank("bank12")->set_base(m_internal_function);
703		if (!MMU_IO_ON) {
704		membank("bank13")->set_base(m_internal_function + 0x1000);
705		}
706		membank("bank14")->set_base(m_internal_function + 0x2000);
707		membank("bank16")->set_base(m_internal_function + 0x3f05);
708		}
709		else /if (MMU_EXTERNAL_ROM_HI) /
710		{
711		membank("bank12")->set_base(m_external_function);
712		if (!MMU_IO_ON) {
713		membank("bank13")->set_base(m_external_function + 0x1000);
714		}
715		membank("bank14")->set_base(m_external_function + 0x2000);
716		membank("bank16")->set_base(m_external_function + 0x3f05);
717		}
718
719		if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
720		\|\| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
721		m_ram_ptr = NULL;
722		}
723		}
724
725		// 128u4
726		// FIX-ME: are the bankswitch functions working in the expected way without the memory_set_context?
727		void c128_state::bankswitch(int reset)
728		{
729		if (m_mmu_cpu != MMU_CPU8502)
730		{
731		if (!MMU_CPU8502)
732		{
733		// DBG_LOG(machine, 1, "switching to z80", ("active %d\n",cpu_getactivecpu()) );
734		// memory_set_context(machine, 0);
735		bankswitch_z80();
736		// memory_set_context(machine, 1);
737		m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
738		m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
739		}
740		else
741		{
742		// DBG_LOG(machine, 1, "switching to m6502", ("active %d\n",cpu_getactivecpu()) );
743		// memory_set_context(machine, 1);
744		bankswitch_128(reset);
745		// memory_set_context(machine, 0);
746		m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
747		m_subcpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
748
749		/* NPW 19-Nov-2005 - In the C128, CPU #0 starts out and hands over
750		* control to CPU #1. CPU #1 seems to execute garbage from 0x0000
751		* up to 0x1100, at which point it finally hits some code
752		* (presumably set up by CPU #1.) This always worked, but when I
753		* changed the m8502 CPU core to use an internal memory map, it
754		* started BRK-ing forever when trying to execute 0x0000.
755		*
756		* I am not sure whether the C128 actually executes this invalid
757		* memory or if this is a bug in the C128 driver. In any case, the
758		* driver used to work with this behavior, so I am doing this hack
759		* where I set CPU #1's PC to 0x1100 on reset.
760		*/
761		if (m_subcpu->pc() == 0x0000)
762		m_subcpu->set_pc(0x1100);
763		}
764		m_mmu_cpu = MMU_CPU8502;
765		return;
766		}
767		if (!MMU_CPU8502)
768		bankswitch_z80();
769		else
770		bankswitch_128(reset);
771		}
772
773		void c128_state::mmu8722_reset()
774		{
775		memset(m_mmu_reg, 0, sizeof (m_mmu_reg));
776		m_mmu_reg[5] \|= 0x38;
777		m_mmu_reg[10] = 1;
778		m_mmu_cpu = 0;
779		m_mmu_page0 = 0;
780		m_mmu_page1 = 0x0100;
781		bankswitch(1);
782		}
783
784		WRITE8_MEMBER( c128_state::mmu8722_port_w )
785		{
786		offset &= 0xf;
787		switch (offset)
788		{
789		case 1:
790		case 2:
791		case 3:
792		case 4:
793		case 8:
794		case 10:
795		m_mmu_reg[offset] = data;
796		break;
797		case 5:
798		m_mmu_reg[offset] = data;
799		bankswitch(0);
800		iec_srq_out_w();
801		iec_data_out_w();
802		m_cia1->cnt_w(MMU_FSDIR \|\| m_iec->srq_r());
803		m_cia1->sp_w(MMU_FSDIR \|\| m_iec->data_r());
804		break;
805		case 0:
806		case 6:
807		m_mmu_reg[offset] = data;
808		bankswitch(0);
809		break;
810		case 7:
811		m_mmu_reg[offset] = data;
812		m_mmu_page0=MMU_PAGE0;
813		break;
814		case 9:
815		m_mmu_reg[offset] = data;
816		m_mmu_page1=MMU_PAGE1;
817		bankswitch(0);
818		break;
819		case 0xb:
820		break;
821		case 0xc:
822		case 0xd:
823		case 0xe:
824		case 0xf:
825		break;
826		}
827		}
828
829		READ8_MEMBER( c128_state::mmu8722_port_r )
830		{
831		int data;
832
833		offset &= 0x0f;
834		switch (offset)
835		{
836		case 5:
837		data = m_mmu_reg[offset] \| 6;
838		if ( /disk enable signal / 0)
839		data &= ~8;
840		if (!m_game)
841		data &= ~0x10;
842		if (!m_exrom)
843		data &= ~0x20;
844		if (ioport("SPECIAL")->read() & 0x10)
845		data &= ~0x80;
846		break;
847		case 0xb:
848		/* hinybble number of 64 kb memory blocks */
849		if ((ioport("SPECIAL")->read() & 0x06) == 0x02) // 256KB RAM
850		data = 0x4f;
851		else if ((ioport("SPECIAL")->read() & 0x06) == 0x04) // 1MB
852		data = 0xf;
853		else
854		data = 0x2f;
855		break;
856		case 0xc:
857		case 0xd:
858		case 0xe:
859		case 0xf:
860		data=0xff;
861		break;
862		default:
863		data=m_mmu_reg[offset];
864		}
865		return data;
866		}
867
868		WRITE8_MEMBER( c128_state::mmu8722_ff00_w )
869		{
870		switch (offset)
871		{
872		case 0:
873		m_mmu_reg[offset] = data;
874		bankswitch(0);
875		break;
876		case 1:
877		case 2:
878		case 3:
879		case 4:
880		#if 1
881		m_mmu_reg[0]= m_mmu_reg[offset];
882		#else
883		m_mmu_reg[0]\|= m_mmu_reg[offset];
884		#endif
885		bankswitch(0);
886		break;
887		}
888		}
889
890		READ8_MEMBER( c128_state::mmu8722_ff00_r )
891		{
892		return m_mmu_reg[offset];
893		}
894
895		WRITE8_MEMBER( c128_state::write_0000 )
896		{
897		if (m_ram_ptr != NULL)
898		m_ram_ptr[0x0000 + offset] = data;
899		}
900
901		WRITE8_MEMBER( c128_state::write_1000 )
902		{
903		if (m_ram_ptr != NULL)
904		m_ram_ptr[0x1000 + offset] = data;
905		}
906
907		WRITE8_MEMBER( c128_state::write_4000 )
908		{
909		if (m_ram_ptr != NULL)
910		m_ram_ptr[0x4000 + offset] = data;
911		}
912
913		WRITE8_MEMBER( c128_state::write_8000 )
914		{
915		if (m_ram_ptr != NULL)
916		m_ram_ptr[0x8000 + offset] = data;
917		}
918
919		WRITE8_MEMBER( c128_state::write_a000 )
920		{
921		if (m_ram_ptr != NULL)
922		m_ram_ptr[0xa000 + offset] = data;
923		}
924
925		WRITE8_MEMBER( c128_state::write_c000 )
926		{
927		if (m_ram_ptr != NULL)
928		m_ram_ptr[0xc000 + offset] = data;
929		}
930
931		WRITE8_MEMBER( c128_state::write_e000 )
932		{
933		if (offset + 0xe000 >= m_ram_top)
934		m_memory[0xe000 + offset] = data;
935		else if (m_ram_ptr != NULL)
936		m_ram_ptr[0xe000 + offset] = data;
937		}
938
939		WRITE8_MEMBER( c128_state::write_ff00 )
940		{
941		if (!m_c64mode)
942		mmu8722_ff00_w(space, offset, data);
943		else if (m_ram_ptr!=NULL)
944		m_memory[0xff00 + offset] = data;
945		}
946
947		WRITE8_MEMBER( c128_state::write_ff05 )
948		{
949		if (offset + 0xff05 >= m_ram_top)
950		m_memory[0xff05 + offset] = data;
951		else if (m_ram_ptr!=NULL)
952		m_ram_ptr[0xff05 + offset] = data;
953		}
954
955		/*
956		* only 14 address lines
957		* a15 and a14 portlines
958		* 0x1000-0x1fff, 0x9000-0x9fff char rom
959		*/
960		READ8_MEMBER( c128_state::vic_dma_read )
961		{
962		UINT8 c64_port6510 = m6510_get_port(m_subcpu);
963
964		/* main memory configuration to include */
965		if (m_c64mode)
966		{
967		if (!m_game && m_exrom)
968		{
969		if (offset < 0x3000)
970		return m_memory[offset];
971		return m_romh[offset & 0x1fff];
972		}
973		if (((m_vicaddr - m_memory + offset) & 0x7000) == 0x1000)
974		return m_chargen[offset & 0xfff];
975		return m_vicaddr[offset];
976		}
977		if (!(c64_port6510 & 4) && (((m_c128_vicaddr - m_memory + offset) & 0x7000) == 0x1000))
978		return m_c128_chargen[offset & 0xfff];
979		return m_c128_vicaddr[offset];
980		}
981
982		READ8_MEMBER( c128_state::vic_dma_read_color )
983		{
984		UINT8 c64_port6510 = m6510_get_port(m_subcpu);
985
986		if (m_c64mode)
987		return m_colorram[offset & 0x3ff] & 0xf;
988		else
989		return m_colorram[(offset & 0x3ff)\|((c64_port6510 & 0x3) << 10)] & 0xf;
990		}
991
992		/* 2008-09-01
993		We need here the m6510 port handlers from c64, otherwise c128_common_driver_init
994		seems unable to use correctly the timer.
995		This will be probably fixed in a future clean up.
996		*/
997
998
999		WRITE8_MEMBER( c128_state::cpu_w )
1000		{
1001		/*
1002
1003		bit description
1004
1005		P0 LORAM
1006		P1 HIRAM
1007		P2 CHAREN
1008		P3 CASS WRT
1009		P4
1010		P5 CASS MOTOR
1011		P6
1012
1013		*/
1014
1015		// memory banking
1016		m_loram = BIT(data, 0);
1017		m_hiram = BIT(data, 1);
1018		m_charen = BIT(data, 2);
1019
1020		// cassette write
1021		m_cassette->write(BIT(data, 3));
1022
1023		// cassette motor
1024		m_cassette->motor_w(BIT(data, 5));
1025
1026		bankswitch_64(0);
1027
1028		m_memory[0x000] = m_subcpu->space(AS_PROGRAM).read_byte(0);
1029		m_memory[0x001] = m_subcpu->space(AS_PROGRAM).read_byte(1);
1030		}
1031
1032		READ8_MEMBER( c128_state::cpu_r)
1033		{
1034		UINT8 data = 0x07;
1035
1036		if (m_cassette->sense_r())
1037		data &= ~0x10;
1038		else
1039		data \|= 0x10;
1040
1041		if (ioport("SPECIAL")->read() & 0x20) /* Check Caps Lock */
1042		data &= ~0x40;
1043		else
1044		data \|= 0x40;
1045
1046		return data;
1047		}
1048
1049		DRIVER_INIT_MEMBER(c128_state,c128)
1050		{
1051		UINT8 *ram = memregion(Z80A_TAG)->base();
1052
1053		m_memory = ram;
1054
1055		m_c128_basic = ram + 0x100000;
1056		m_basic = ram + 0x108000;
1057		m_kernal = ram + 0x10a000;
1058		m_editor = ram + 0x10c000;
1059		m_z80 = ram + 0x10d000;
1060		m_c128_kernal = ram + 0x10e000;
1061		m_internal_function = ram + 0x110000;
1062		m_external_function = ram + 0x118000;
1063		m_chargen = ram + 0x120000;
1064		m_c128_chargen = ram + 0x121000;
1065		m_colorram = ram + 0x122000;
1066		m_vdcram = ram + 0x122800;
1067		m_c64_roml = auto_alloc_array(machine(), UINT8, 0x2000);
1068		m_c64_romh = auto_alloc_array(machine(), UINT8, 0x2000);
1069
1070		m_game = 1;
1071		m_exrom = 1;
1072		m_pal = 0;
1073		m_c64mode = 0;
1074		m_vicirq = 0;
1075
1076		m_cnt1 = 1;
1077		m_sp1 = 1;
1078		cbm_common_init();
1079		m_keyline[0] = m_keyline[1] = m_keyline[2] = 0xff;
1080		}
1081
1082		DRIVER_INIT_MEMBER(c128_state,c128pal)
1083		{
1084		DRIVER_INIT_CALL( c128 );
1085
1086		m_pal = 1;
1087		}
1088
1089		DRIVER_INIT_MEMBER(c128_state,c128d)
1090		{
1091		DRIVER_INIT_CALL( c128 );
1092		}
1093
1094		DRIVER_INIT_MEMBER(c128_state,c128dpal)
1095		{
1096		DRIVER_INIT_CALL( c128pal );
1097		}
1098
1099		DRIVER_INIT_MEMBER(c128_state,c128dcr)
1100		{
1101		DRIVER_INIT_CALL( c128 );
1102		}
1103
1104		DRIVER_INIT_MEMBER(c128_state,c128dcrp)
1105		{
1106		DRIVER_INIT_CALL( c128pal );
1107		}
1108
1109		DRIVER_INIT_MEMBER(c128_state,c128d81)
1110		{
1111		DRIVER_INIT_CALL( c128 );
1112		}
1113
1114		void c128_state::machine_start()
1115		{
1116		// This was in MACHINE_START( c64 ), but never called
1117		// TO DO: find its correct use, when fixing c64 mode
1118		if (m_c64mode)
1119		bankswitch_64(1);
1120		}
1121
1122		void c128_state::machine_reset()
1123		{
1124		m_c128_vicaddr = m_vicaddr = m_memory;
1125		m_c64mode = 0;
1126		mmu8722_reset();
1127		m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
1128		m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
1129		}
1130
1131
1132		INTERRUPT_GEN_MEMBER(c128_state::c128_frame_interrupt)
1133		{
1134		static const char *const c128ports[] = { "KP0", "KP1", "KP2" };
1135		int i, value;
1136		//device_t *vic2e = machine().device("vic2e");
1137		//device_t *vdc8563 = machine().device("vdc8563");
1138
1139		nmi();
1140
1141		/* common keys input ports */
1142		cbm_common_interrupt(&device);
1143
1144		/* Fix Me! Currently, neither left Shift nor Shift Lock work in c128, but reading the correspondent input produces a bug!
1145		Hence, we overwrite the actual reading as it never happens */
1146		if ((machine().root_device().ioport("SPECIAL")->read() & 0x40)) //
1147		c64_keyline[1] \|= 0x80;
1148
1149		/* c128 specific: keypad input ports */
1150		for (i = 0; i < 3; i++)
1151		{
1152		value = 0xff;
1153		value &= ~machine().root_device().ioport(c128ports[i])->read();
1154		m_keyline[i] = value;
1155		}
1156		}

trunk/src/mess/includes/c128.h
r18537	r18538
1		/*****************************************************************************
2		*
3		* includes/c128.h
4		*
5		* Commodore C128 Home Computer
6		*
7		* peter.trauner@jk.uni-linz.ac.at
8		*
9		* Documentation: iDOC (http://www.softwolves.pp.se/idoc)
10		* Christian Janoff <mepk@c64.org>
11		*
12		****************************************************************************/
	1	#pragma once
13	2
14		#ifndef __C128_H__
15		#define __C128_H__
	3	#ifndef __C128__
	4	#define __C128__
16	5
17	6	#include "emu.h"
18	7	#include "formats/cbm_snqk.h"
r18537	r18538
32	21	#include "video/mos6566.h"
33	22	#include "video/vdc8563.h"
34	23
35		// TODO remove
36		#include "includes/c64_legacy.h"
37
38	24	#define Z80A_TAG "u10"
39	25	#define M8502_TAG "u6"
40	26	#define MOS8563_TAG "u22"
r18537	r18538
50	36	#define CONTROL1_TAG "joy1"
51	37	#define CONTROL2_TAG "joy2"
52	38
53		class c128_state : public le~~gacy~~_c~~64_stat~~e
	39	class c128_state : public driver_device
54	40	{
55	41	public:
56	42	c128_state(const machine_config &mconfig, device_type type, const char *tag)
57		: le~~gacy~~_c~~64_stat~~e(mconfig, type, tag),
	43	: driver_device(mconfig, type, tag),
58	44	m_maincpu(*this, Z80A_TAG),
59	45	m_subcpu(*this, M8502_TAG),
60	46	m_mmu(*this, MOS8722_TAG),
r18537	r18538
64	50	m_sid(*this, MOS6581_TAG),
65	51	m_cia1(*this, MOS6526_1_TAG),
66	52	m_cia2(*this, MOS6526_2_TAG),
67		//m_iec(*this, CBM_IEC_TAG),
	53	m_iec(*this, CBM_IEC_TAG),
68	54	m_joy1(*this, CONTROL1_TAG),
69	55	m_joy2(*this, CONTROL2_TAG),
70	56	m_exp(*this, C64_EXPANSION_SLOT_TAG),
71	57	m_user(*this, C64_USER_PORT_TAG),
72	58	m_ram(*this, RAM_TAG),
73	59	m_cassette(*this, PET_DATASSETTE_PORT_TAG),
	60	m_z80en(0),
	61	m_loram(1),
	62	m_hiram(1),
	63	m_charen(1),
	64	m_game(1),
	65	m_exrom(1),
74	66	m_rom1(NULL),
75	67	m_rom2(NULL),
76	68	m_rom3(NULL),
77	69	m_rom4(NULL),
78	70	m_from(NULL),
79		m_charom(NULL)
	71	m_charom(NULL),
	72	m_color_ram(*this, "color_ram"),
	73	m_va14(1),
	74	m_va15(1),
	75	m_clrbank(0),
	76	m_cnt1(1),
	77	m_sp1(1),
	78	m_iec_data_out(1),
	79	m_cia1_irq(CLEAR_LINE),
	80	m_cia2_irq(CLEAR_LINE),
	81	m_vic_irq(CLEAR_LINE),
	82	m_exp_irq(CLEAR_LINE),
	83	m_exp_nmi(CLEAR_LINE),
	84	m_cass_rd(1),
	85	m_iec_srq(1)
80	86	{ }
81	87
82	88	required_device<legacy_cpu_device> m_maincpu;
r18537	r18538
88	94	required_device<sid6581_device> m_sid;
89	95	required_device<mos6526_device> m_cia1;
90	96	required_device<mos6526_device> m_cia2;
91		//required_device<cbm_iec_device> m_iec;
	97	required_device<cbm_iec_device> m_iec;
92	98	required_device<vcs_control_port_device> m_joy1;
93	99	required_device<vcs_control_port_device> m_joy2;
94	100	required_device<c64_expansion_slot_device> m_exp;
r18537	r18538
99	105	virtual void machine_start();
100	106	virtual void machine_reset();
101	107
102		void bankswitch_pla(offs_t offset, offs_t ta, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
103		int sden, int dir, int gwe, int rom1, int rom2, int rom3, int rom4, int charom, int colorram, int vic, int from1, int romh, int roml, int dwe, int ioacc, int clrbank, int iocs, int casenb);
	108	inline void check_interrupts();
	109	void read_pla(offs_t offset, offs_t ca, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
	110	int sden, int dir, int gwe, int rom1, int rom2, int rom3, int rom4, int charom, int colorram, int vic,
	111	int from1, int romh, int roml, int dwe, int ioacc, int clrbank, int iocs, int casenb);
104	112	UINT8 read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io);
105	113	void write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io);
	114	inline void update_iec();
106	115
107	116	DECLARE_READ8_MEMBER( z80_r );
108	117	DECLARE_WRITE8_MEMBER( z80_w );
r18537	r18538
111	120	DECLARE_READ8_MEMBER( read );
112	121	DECLARE_WRITE8_MEMBER( write );
113	122	DECLARE_READ8_MEMBER( vic_videoram_r );
	123	DECLARE_READ8_MEMBER( vic_colorram_r );
114	124
115		DECLARE_READ8_MEMBER( read_io );
116		DECLARE_READ8_MEMBER( mmu8722_port_r );
117		DECLARE_WRITE8_MEMBER( mmu8722_port_w );
118		DECLARE_READ8_MEMBER( mmu8722_ff00_r );
119		DECLARE_WRITE8_MEMBER( mmu8722_ff00_w );
120		DECLARE_READ8_MEMBER( dma8726_port_r );
121		DECLARE_WRITE8_MEMBER( dma8726_port_w );
122		DECLARE_WRITE8_MEMBER( write_0000 );
123		DECLARE_WRITE8_MEMBER( write_1000 );
124		DECLARE_WRITE8_MEMBER( write_4000 );
125		DECLARE_WRITE8_MEMBER( write_8000 );
126		DECLARE_WRITE8_MEMBER( write_a000 );
127		DECLARE_WRITE8_MEMBER( write_c000 );
128		DECLARE_WRITE8_MEMBER( write_d000 );
129		DECLARE_WRITE8_MEMBER( write_e000 );
130		DECLARE_WRITE8_MEMBER( write_ff00 );
131		DECLARE_WRITE8_MEMBER( write_ff05 );
132
133	125	DECLARE_WRITE_LINE_MEMBER( mmu_z80en_w );
134	126	DECLARE_WRITE_LINE_MEMBER( mmu_fsdir_w );
135	127	DECLARE_READ_LINE_MEMBER( mmu_game_r );
136	128	DECLARE_READ_LINE_MEMBER( mmu_exrom_r );
137	129	DECLARE_READ_LINE_MEMBER( mmu_sense40_r );
138	130
139		DECLARE_READ8_MEMBER( vic_lightpen_x_cb );
140		DECLARE_READ8_MEMBER( vic_lightpen_y_cb );
141		DECLARE_READ8_MEMBER( vic_lightpen_button_cb );
	131	INTERRUPT_GEN_MEMBER( frame_interrupt );
142	132	DECLARE_READ8_MEMBER( vic_dma_read );
143	133	DECLARE_READ8_MEMBER( vic_dma_read_color );
144		DECLARE_WRITE_LINE_MEMBER( vic_interrupt );
145		DECLARE_READ8_MEMBER( vic_rdy_cb );
146
	134	DECLARE_WRITE_LINE_MEMBER( vic_irq_w );
	135
147	136	DECLARE_READ8_MEMBER( sid_potx_r );
148	137	DECLARE_READ8_MEMBER( sid_poty_r );
149	138
r18537	r18538
158	147	DECLARE_READ8_MEMBER( cia2_pa_r );
159	148	DECLARE_WRITE8_MEMBER( cia2_pa_w );
160	149
161		DECLARE_WRITE_LINE_MEMBER( iec_srq_w );
162		DECLARE_WRITE_LINE_MEMBER( iec_data_w );
163
164	150	DECLARE_READ8_MEMBER( cpu_r );
165	151	DECLARE_WRITE8_MEMBER( cpu_w );
166	152
167		void nmi();
168		void irq(int level);
169		void iec_data_out_w();
170		void iec_srq_out_w();
171		void bankswitch_64(int reset);
172		void bankswitch_z80();
173		void bankswitch_128(int reset);
174		void bankswitch(int reset);
175		void mmu8722_reset();
	153	DECLARE_WRITE_LINE_MEMBER( tape_read_w );
176	154
	155	DECLARE_WRITE_LINE_MEMBER( iec_srq_w );
	156	DECLARE_WRITE_LINE_MEMBER( iec_data_w );
	157
	158	DECLARE_READ8_MEMBER( exp_dma_r );
	159	DECLARE_WRITE8_MEMBER( exp_dma_w );
	160	DECLARE_WRITE_LINE_MEMBER( exp_irq_w );
	161	DECLARE_WRITE_LINE_MEMBER( exp_nmi_w );
	162	DECLARE_WRITE_LINE_MEMBER( exp_dma_w );
	163	DECLARE_WRITE_LINE_MEMBER( exp_reset_w );
	164
177	165	// memory state
	166	int m_z80en;
178	167	int m_loram;
179	168	int m_hiram;
180	169	int m_charen;
181		int m_va14;
182		int m_va15;
	170	int m_game;
	171	int m_exrom;
	172	int m_reset;
183	173	const UINT8 *m_rom1;
184	174	const UINT8 *m_rom2;
185	175	const UINT8 *m_rom3;
186	176	const UINT8 *m_rom4;
187	177	const UINT8 *m_from;
188	178	const UINT8 *m_charom;
189		UINT8 *m_color_ram;
190	179
191		UINT8 *m_c128_basic;
192		UINT8 *m_c128_kernal;
193		UINT8 *m_c128_chargen;
194		UINT8 *m_z80;
195		UINT8 *m_editor;
196		UINT8 *m_internal_function;
197		UINT8 *m_external_function;
198		UINT8 *m_vdcram;
199		UINT8 m_mmu_reg[0x0b];
200		int m_mmu_cpu;
201		int m_mmu_page0;
202		int m_mmu_page1;
203		int m_c64mode;
204		int m_write_io;
205		int m_ram_bottom;
206		int m_ram_top;
207		UINT8 *m_ram_ptr;
208		UINT8 m_c64_port_data;
209		UINT8 m_keyline[3];
	180	// video state
	181	optional_shared_ptr<UINT8> m_color_ram;
	182	int m_va14;
	183	int m_va15;
	184	int m_clrbank;
	185
	186	// fast serial state
210	187	int m_cnt1;
211	188	int m_sp1;
212		int m_data_out;
213		int m_va1617;
214		int m_nmilevel;
215		int m_z80en;
	189	int m_iec_data_out;
	190
	191	// interrupt state
216	192	int m_cia1_irq;
217		DECLARE_DRIVER_INIT(c128pal);
218		DECLARE_DRIVER_INIT(c128dcrp);
219		DECLARE_DRIVER_INIT(c128dcr);
220		DECLARE_DRIVER_INIT(c128dpal);
221		DECLARE_DRIVER_INIT(c128d);
222		DECLARE_DRIVER_INIT(c128);
223		DECLARE_DRIVER_INIT(c128d81);
224		INTERRUPT_GEN_MEMBER(c128_frame_interrupt);
	193	int m_cia2_irq;
	194	int m_vic_irq;
	195	int m_exp_irq;
	196	int m_exp_nmi;
	197	int m_cass_rd;
	198	int m_iec_srq;
	199
	200	// keyboard state
	201	UINT8 m_keyline[3];
225	202	};
226	203
227	204
228		/----------- defined in machine/c128.c -----------/
229	205
230		extern const mos6526_interface c128_cia1_intf, c128_cia2_intf;
231
232		#endif /* __C128_H__ */
	206	#endif

199869 Revisions