MAME SVN History

199869 Revisions

r18356 Monday 8th October, 2012 at 12:11:39 UTC by smf
(MESS) ran the new srcclean on these, as an example (nw)

[src/mess/drivers]	rmnimbus.c
[src/mess/includes]	rmnimbus.h
[src/mess/machine]	rmnimbus.c

trunk/src/mess/machine/rmnimbus.c
r18355	r18356
82	82	#define LOG_TIMER 0
83	83	#define LOG_OPTIMIZATION 0
84	84	#define LOG_DMA 0
85		#define CPU_RESUME_TRIGGER 7123
	85	#define CPU_RESUME_TRIGGER 7123
86	86	#define LOG_KEYBOARD 0
87	87	#define LOG_SIO 0
88	88	#define LOG_DISK_FDD 0
r18355	r18356
99	99
100	100	#define DEBUG_SET(flags) ((state->m_debug_machine & (flags))==(flags))
101	101
102		#define DEBUG_NONE 0x0000000
	102	#define DEBUG_NONE 0x0000000
103	103	#define DMA_BREAK 0x0000001
104	104	#define DECODE_BIOS 0x0000002
105	105	#define DECODE_BIOS_RAW 0x0000004
106		#define DECODE_DOS21 0x0000008
	106	#define DECODE_DOS21 0x0000008
107	107
108	108
109	109	/* Z80 SIO */
110	110
111	111	const z80sio_interface nimbus_sio_intf =
112	112	{
113		DEVCB_DRIVER_LINE_MEMBER(rmnimbus_state,sio_interrupt), /* interrupt handler */
	113	DEVCB_DRIVER_LINE_MEMBER(rmnimbus_state,sio_interrupt), /* interrupt handler */
114	114	DEVCB_NULL, //sio_dtr_w, /* DTR changed handler */
115		DEVCB_NULL, /* RTS changed handler */
116		DEVCB_NULL, /* BREAK changed handler */
117		DEVCB_DRIVER_MEMBER16(rmnimbus_state,sio_serial_transmit), /* transmit handler */
118		DEVCB_DRIVER_MEMBER16(rmnimbus_state,sio_serial_receive) /* receive handler */
	115	DEVCB_NULL, /* RTS changed handler */
	116	DEVCB_NULL, /* BREAK changed handler */
	117	DEVCB_DRIVER_MEMBER16(rmnimbus_state,sio_serial_transmit), /* transmit handler */
	118	DEVCB_DRIVER_MEMBER16(rmnimbus_state,sio_serial_receive) /* receive handler */
119	119	};
120	120
121	121	/* Floppy drives WD2793 */
r18355	r18356
134	134
135	135	static const UINT16 def_config[16] =
136	136	{
137		0x0280, 0x017F, 0xE822, 0x8129,
138		0x0329, 0x0000, 0x0000, 0x0000,
139		0x0000, 0x0000, 0x0000, 0x0000,
140		0x0000, 0x8796, 0x2025, 0xB9E6
	137	0x0280, 0x017F, 0xE822, 0x8129,
	138	0x0329, 0x0000, 0x0000, 0x0000,
	139	0x0000, 0x0000, 0x0000, 0x0000,
	140	0x0000, 0x8796, 0x2025, 0xB9E6
141	141	};
142	142
143	143	/* Memory controler */
r18355	r18356
192	192	static IRQ_CALLBACK(int_callback)
193	193	{
194	194	rmnimbus_state *state = device->machine().driver_data<rmnimbus_state>();
195		UINT8 vector;
196		UINT16 old;
197		UINT16 oldreq;
	195	UINT8 vector;
	196	UINT16 old;
	197	UINT16 oldreq;
198	198
199	199	if (LOG_INTERRUPTS)
200	200	logerror("(%f) **** Acknowledged interrupt vector %02X\n", device->machine().time().as_double(), state->m_i186.intr.poll_status & 0x1f);
r18355	r18356
226	226	{
227	227	switch (state->m_i186.intr.poll_status & 0x1f)
228	228	{
229		case 0x08: state->m_i186.intr.status &= ~0x01; break;
230		case 0x12: state->m_i186.intr.status &= ~0x02; break;
231		case 0x13: state->m_i186.intr.status &= ~0x04; break;
	229	case 0x08: state->m_i186.intr.status &= ~0x01; break;
	230	case 0x12: state->m_i186.intr.status &= ~0x02; break;
	231	case 0x13: state->m_i186.intr.status &= ~0x04; break;
232	232	}
233	233	}
234	234	state->m_i186.intr.ack_mask = 0;
r18355	r18356
237	237	state->m_i186.intr.poll_status &= ~0x8000;
238	238
239	239	/* return the vector */
240		switch(state->m_i186.intr.poll_status & 0x1F)
241		{
242		case 0x0C : vector=(state->m_i186.intr.ext[0] & EXTINT_CTRL_CASCADE) ? state->m_i186.intr.ext_vector[0] : (state->m_i186.intr.poll_status & 0x1f); break;
243		case 0x0D : vector=(state->m_i186.intr.ext[1] & EXTINT_CTRL_CASCADE) ? state->m_i186.intr.ext_vector[1] : (state->m_i186.intr.poll_status & 0x1f); break;
244		default :
245		vector=state->m_i186.intr.poll_status & 0x1f; break;
246		}
	240	switch(state->m_i186.intr.poll_status & 0x1F)
	241	{
	242	case 0x0C : vector=(state->m_i186.intr.ext[0] & EXTINT_CTRL_CASCADE) ? state->m_i186.intr.ext_vector[0] : (state->m_i186.intr.poll_status & 0x1f); break;
	243	case 0x0D : vector=(state->m_i186.intr.ext[1] & EXTINT_CTRL_CASCADE) ? state->m_i186.intr.ext_vector[1] : (state->m_i186.intr.poll_status & 0x1f); break;
	244	default :
	245	vector=state->m_i186.intr.poll_status & 0x1f; break;
	246	}
247	247
248		if (LOG_INTERRUPTS)
249		{
250		logerror("i186.intr.ext[0]=%04X i186.intr.ext[1]=%04X\n",state->m_i186.intr.ext[0],state->m_i186.intr.ext[1]);
251		logerror("Ext vectors : %02X %02X\n",state->m_i186.intr.ext_vector[0],state->m_i186.intr.ext_vector[1]);
252		logerror("Int %02X Calling vector %02X\n",state->m_i186.intr.poll_status,vector);
253		}
	248	if (LOG_INTERRUPTS)
	249	{
	250	logerror("i186.intr.ext[0]=%04X i186.intr.ext[1]=%04X\n",state->m_i186.intr.ext[0],state->m_i186.intr.ext[1]);
	251	logerror("Ext vectors : %02X %02X\n",state->m_i186.intr.ext_vector[0],state->m_i186.intr.ext_vector[1]);
	252	logerror("Int %02X Calling vector %02X\n",state->m_i186.intr.poll_status,vector);
	253	}
254	254
255		return vector;
	255	return vector;
256	256	}
257	257
258	258
r18355	r18356
363	363	/* turn off the appropriate in-service bit */
364	364	switch (data & 0x1f)
365	365	{
366		case 0x08: state->m_i186.intr.in_service &= ~0x01; break;
367		case 0x12: state->m_i186.intr.in_service &= ~0x01; break;
368		case 0x13: state->m_i186.intr.in_service &= ~0x01; break;
369		case 0x0a: state->m_i186.intr.in_service &= ~0x04; break;
370		case 0x0b: state->m_i186.intr.in_service &= ~0x08; break;
371		case 0x0c: state->m_i186.intr.in_service &= ~0x10; break;
372		case 0x0d: state->m_i186.intr.in_service &= ~0x20; break;
373		case 0x0e: state->m_i186.intr.in_service &= ~0x40; break;
374		case 0x0f: state->m_i186.intr.in_service &= ~0x80; break;
375		default: logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", machine.device(MAINCPU_TAG)->safe_pc(), data & 0x1f);
	366	case 0x08: state->m_i186.intr.in_service &= ~0x01; break;
	367	case 0x12: state->m_i186.intr.in_service &= ~0x01; break;
	368	case 0x13: state->m_i186.intr.in_service &= ~0x01; break;
	369	case 0x0a: state->m_i186.intr.in_service &= ~0x04; break;
	370	case 0x0b: state->m_i186.intr.in_service &= ~0x08; break;
	371	case 0x0c: state->m_i186.intr.in_service &= ~0x10; break;
	372	case 0x0d: state->m_i186.intr.in_service &= ~0x20; break;
	373	case 0x0e: state->m_i186.intr.in_service &= ~0x40; break;
	374	case 0x0f: state->m_i186.intr.in_service &= ~0x80; break;
	375	default: logerror("%05X:ERROR - 80186 EOI with unknown vector %02X\n", machine.device(MAINCPU_TAG)->safe_pc(), data & 0x1f);
376	376	}
377	377	if (LOG_INTERRUPTS) logerror("(%f) **** Got EOI for vector %02X\n", machine.time().as_double(), data & 0x1f);
378	378	}
r18355	r18356
419	419	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
420	420	if (LOG_INTERRUPTS_EXT) logerror("generating external int %02X, vector %02X\n",intno,vector);
421	421
422		// Only 4 external ints
423		if(intno>3)
424		{
425		logerror("external_int() invalid external interupt no : 0x%02X (can only be 0..3)\n",intno);
426		return;
427		}
	422	// Only 4 external ints
	423	if(intno>3)
	424	{
	425	logerror("external_int() invalid external interupt no : 0x%02X (can only be 0..3)\n",intno);
	426	return;
	427	}
428	428
429		// Only set external vector if cascade mode enabled, only valid for
430		// int 0 & int 1
431		if (intno<2)
432		{
433		if(state->m_i186.intr.ext[intno] & EXTINT_CTRL_CASCADE)
434		state->m_i186.intr.ext_vector[intno]=vector;
435		}
	429	// Only set external vector if cascade mode enabled, only valid for
	430	// int 0 & int 1
	431	if (intno<2)
	432	{
	433	if(state->m_i186.intr.ext[intno] & EXTINT_CTRL_CASCADE)
	434	state->m_i186.intr.ext_vector[intno]=vector;
	435	}
436	436
437		// Turn on the requested request bit and handle interrupt
438		state->m_i186.intr.request \|= (0x010 << intno);
439		update_interrupt_state(machine);
	437	// Turn on the requested request bit and handle interrupt
	438	state->m_i186.intr.request \|= (0x010 << intno);
	439	update_interrupt_state(machine);
440	440	}
441	441
442	442	static void nimbus_recalculate_ints(running_machine &machine)
443	443	{
444	444	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
445		if((state->m_iou_reg092 & DISK_INT_ENABLE) && state->m_nimbus_drives.int_ff)
446		{
447		state->m_nimbus_drives.int_ff=0;
448		external_int(machine,0,EXTERNAL_INT_DISK);
449		}
	445	if((state->m_iou_reg092 & DISK_INT_ENABLE) && state->m_nimbus_drives.int_ff)
	446	{
	447	state->m_nimbus_drives.int_ff=0;
	448	external_int(machine,0,EXTERNAL_INT_DISK);
	449	}
450	450	}
451	451
452	452	/*************************************
r18355	r18356
511	511
512	512
513	513	static void internal_timer_update(running_machine &machine,
514		int which,
515		int new_count,
516		int new_maxA,
517		int new_maxB,
518		int new_control)
	514	int which,
	515	int new_count,
	516	int new_maxA,
	517	int new_maxB,
	518	int new_control)
519	519	{
520	520	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
521	521	struct timer_state *t = &state->m_i186.timer[which];
r18355	r18356
546	546	t->maxA = new_maxA;
547	547	if (new_maxA == 0)
548	548	{
549		new_maxA = 0x10000;
	549	new_maxA = 0x10000;
550	550	}
551	551	}
552	552
r18355	r18356
563	563
564	564	if (new_maxB == 0)
565	565	{
566		new_maxB = 0x10000;
	566	new_maxB = 0x10000;
567	567	}
568	568	}
569	569
r18355	r18356
585	585	diff = new_control ^ t->control;
586	586	if (diff & 0x001c)
587	587	logerror("%05X:ERROR! -unsupported timer mode %04X\n",
588		machine.device(MAINCPU_TAG)->safe_pc(), new_control);
	588	machine.device(MAINCPU_TAG)->safe_pc(), new_control);
589	589
590	590	/* if we have real changes, update things */
591	591	if (diff != 0)
r18355	r18356
727	727	address_space &memory_space = machine.device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
728	728	address_space &io_space = machine.device(MAINCPU_TAG)->memory().space(AS_IO);
729	729
730		UINT16 dma_word;
731		UINT8 dma_byte;
732		UINT8 incdec_size;
	730	UINT16 dma_word;
	731	UINT8 dma_byte;
	732	UINT8 incdec_size;
733	733
734		if (LOG_DMA>1)
735		logerror("Control=%04X, src=%05X, dest=%05X, count=%04X\n",dma->control,dma->source,dma->dest,dma->count);
	734	if (LOG_DMA>1)
	735	logerror("Control=%04X, src=%05X, dest=%05X, count=%04X\n",dma->control,dma->source,dma->dest,dma->count);
736	736
737		if(!(dma->control & ST_STOP))
738		{
739		logerror("%05X:ERROR! - drq%d with dma channel stopped\n",
	737	if(!(dma->control & ST_STOP))
	738	{
	739	logerror("%05X:ERROR! - drq%d with dma channel stopped\n",
740	740	machine.device(MAINCPU_TAG)->safe_pc(), which);
741	741
742		return;
743		}
	742	return;
	743	}
744	744
745	745	address_space &dest_space = (dma->control & DEST_MIO) ? memory_space : io_space;
746		address_space &src_space = (dma->control & SRC_MIO) ? memory_space : io_space;
	746	address_space &src_space = (dma->control & SRC_MIO) ? memory_space : io_space;
747	747
748		// Do the transfer
749		if(dma->control & BYTE_WORD)
750		{
751		dma_word=src_space.read_word(dma->source);
752		dest_space.write_word(dma->dest,dma_word);
753		incdec_size=2;
754		}
755		else
756		{
757		dma_byte=src_space.read_byte(dma->source);
758		dest_space.write_byte(dma->dest,dma_byte);
759		incdec_size=1;
760		}
	748	// Do the transfer
	749	if(dma->control & BYTE_WORD)
	750	{
	751	dma_word=src_space.read_word(dma->source);
	752	dest_space.write_word(dma->dest,dma_word);
	753	incdec_size=2;
	754	}
	755	else
	756	{
	757	dma_byte=src_space.read_byte(dma->source);
	758	dest_space.write_byte(dma->dest,dma_byte);
	759	incdec_size=1;
	760	}
761	761
762		// Increment or Decrement destination ans source pointers as needed
763		switch (dma->control & DEST_INCDEC_MASK)
764		{
765		case DEST_DECREMENT : dma->dest -= incdec_size;
766		case DEST_INCREMENT : dma->dest += incdec_size;
767		}
	762	// Increment or Decrement destination ans source pointers as needed
	763	switch (dma->control & DEST_INCDEC_MASK)
	764	{
	765	case DEST_DECREMENT : dma->dest -= incdec_size;
	766	case DEST_INCREMENT : dma->dest += incdec_size;
	767	}
768	768
769		switch (dma->control & SRC_INCDEC_MASK)
770		{
771		case SRC_DECREMENT : dma->source -= incdec_size;
772		case SRC_INCREMENT : dma->source += incdec_size;
773		}
	769	switch (dma->control & SRC_INCDEC_MASK)
	770	{
	771	case SRC_DECREMENT : dma->source -= incdec_size;
	772	case SRC_INCREMENT : dma->source += incdec_size;
	773	}
774	774
775		// decrement count
776		dma->count -= 1;
	775	// decrement count
	776	dma->count -= 1;
777	777
778		// Terminate if count is zero, and terminate flag set
779		if((dma->control & TERMINATE_ON_ZERO) && (dma->count==0))
780		{
781		dma->control &= ~ST_STOP;
782		if (LOG_DMA) logerror("DMA terminated\n");
783		}
	778	// Terminate if count is zero, and terminate flag set
	779	if((dma->control & TERMINATE_ON_ZERO) && (dma->count==0))
	780	{
	781	dma->control &= ~ST_STOP;
	782	if (LOG_DMA) logerror("DMA terminated\n");
	783	}
784	784
785		// Interrupt if count is zero, and interrupt flag set
786		if((dma->control & INTERRUPT_ON_ZERO) && (dma->count==0))
787		{
	785	// Interrupt if count is zero, and interrupt flag set
	786	if((dma->control & INTERRUPT_ON_ZERO) && (dma->count==0))
	787	{
788	788	if (LOG_DMA>1) logerror("DMA%d - requesting interrupt: count = %04X, source = %04X\n", which, dma->count, dma->source);
789	789	state->m_i186.intr.request \|= 0x04 << which;
790	790	update_interrupt_state(machine);
791		}
	791	}
792	792	}
793	793
794	794	/-------------------------------------------------------------------------/
r18355	r18356
815	815	{
816	816	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
817	817	/* reset the interrupt state */
818		state->m_i186.intr.priority_mask = 0x0007;
819		state->m_i186.intr.timer = 0x000f;
820		state->m_i186.intr.dma[0] = 0x000f;
821		state->m_i186.intr.dma[1] = 0x000f;
822		state->m_i186.intr.ext[0] = 0x000f;
823		state->m_i186.intr.ext[1] = 0x000f;
824		state->m_i186.intr.ext[2] = 0x000f;
825		state->m_i186.intr.ext[3] = 0x000f;
826		state->m_i186.intr.in_service = 0x0000;
	818	state->m_i186.intr.priority_mask = 0x0007;
	819	state->m_i186.intr.timer = 0x000f;
	820	state->m_i186.intr.dma[0] = 0x000f;
	821	state->m_i186.intr.dma[1] = 0x000f;
	822	state->m_i186.intr.ext[0] = 0x000f;
	823	state->m_i186.intr.ext[1] = 0x000f;
	824	state->m_i186.intr.ext[2] = 0x000f;
	825	state->m_i186.intr.ext[3] = 0x000f;
	826	state->m_i186.intr.in_service = 0x0000;
827	827
828	828	/* External vectors by default to internal int 0/1 vectors */
829		state->m_i186.intr.ext_vector[0] = 0x000C;
830		state->m_i186.intr.ext_vector[1] = 0x000D;
	829	state->m_i186.intr.ext_vector[0] = 0x000C;
	830	state->m_i186.intr.ext_vector[1] = 0x000D;
831	831
832	832	state->m_i186.intr.pending = 0x0000;
833	833	state->m_i186.intr.ack_mask = 0x0000;
r18355	r18356
1276	1276
1277	1277	static void execute_debug_irq(running_machine &machine, int ref, int params, const char *param[])
1278	1278	{
1279		int IntNo;
1280		int Vector;
	1279	int IntNo;
	1280	int Vector;
1281	1281
1282		if(params>1)
1283		{
1284		sscanf(param[0],"%X",&IntNo);
1285		sscanf(param[1],"%X",&Vector);
	1282	if(params>1)
	1283	{
	1284	sscanf(param[0],"%X",&IntNo);
	1285	sscanf(param[1],"%X",&Vector);
1286	1286
1287		debug_console_printf(machine,"triggering IRQ%d, Vector=%02X\n",IntNo,Vector);
1288		external_int(machine,IntNo,Vector);
1289		}
1290		else
1291		{
1292		debug_console_printf(machine,"Error, you must supply an intno and vector to trigger\n");
1293		}
	1287	debug_console_printf(machine,"triggering IRQ%d, Vector=%02X\n",IntNo,Vector);
	1288	external_int(machine,IntNo,Vector);
	1289	}
	1290	else
	1291	{
	1292	debug_console_printf(machine,"Error, you must supply an intno and vector to trigger\n");
	1293	}
1294	1294	}
1295	1295
1296	1296
1297	1297	static void execute_debug_intmasks(running_machine &machine, int ref, int params, const char *param[])
1298	1298	{
1299	1299	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
1300		int IntNo;
	1300	int IntNo;
1301	1301
1302		debug_console_printf(machine,"i186.intr.priority_mask=%4X\n",state->m_i186.intr.priority_mask);
1303		for(IntNo=0; IntNo<4; IntNo++)
1304		{
1305		debug_console_printf(machine,"extInt%d mask=%4X\n",IntNo,state->m_i186.intr.ext[IntNo]);
1306		}
	1302	debug_console_printf(machine,"i186.intr.priority_mask=%4X\n",state->m_i186.intr.priority_mask);
	1303	for(IntNo=0; IntNo<4; IntNo++)
	1304	{
	1305	debug_console_printf(machine,"extInt%d mask=%4X\n",IntNo,state->m_i186.intr.ext[IntNo]);
	1306	}
1307	1307
1308		debug_console_printf(machine,"i186.intr.request = %04X\n",state->m_i186.intr.request);
1309		debug_console_printf(machine,"i186.intr.ack_mask = %04X\n",state->m_i186.intr.ack_mask);
1310		debug_console_printf(machine,"i186.intr.in_service= %04X\n",state->m_i186.intr.in_service);
	1308	debug_console_printf(machine,"i186.intr.request = %04X\n",state->m_i186.intr.request);
	1309	debug_console_printf(machine,"i186.intr.ack_mask = %04X\n",state->m_i186.intr.ack_mask);
	1310	debug_console_printf(machine,"i186.intr.in_service= %04X\n",state->m_i186.intr.in_service);
1311	1311	}
1312	1312
1313	1313	static void nimbus_debug(running_machine &machine, int ref, int params, const char *param[])
1314	1314	{
1315	1315	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
1316		if(params>0)
1317		{
1318		sscanf(param[0],"%d",&state->m_debug_machine);
1319		}
1320		else
1321		{
1322		debug_console_printf(machine,"Error usage : nimbus_debug <debuglevel>\n");
1323		debug_console_printf(machine,"Current debuglevel=%02X\n",state->m_debug_machine);
1324		}
	1316	if(params>0)
	1317	{
	1318	sscanf(param[0],"%d",&state->m_debug_machine);
	1319	}
	1320	else
	1321	{
	1322	debug_console_printf(machine,"Error usage : nimbus_debug <debuglevel>\n");
	1323	debug_console_printf(machine,"Current debuglevel=%02X\n",state->m_debug_machine);
	1324	}
1325	1325	}
1326	1326
1327	1327	/*-----------------------------------------------
r18355	r18356
1330	1330
1331	1331	static int instruction_hook(device_t &device, offs_t curpc)
1332	1332	{
1333		rmnimbus_state *state = device.machine().driver_data<rmnimbus_state>();
1334		address_space &space = device.memory().space(AS_PROGRAM);
1335		UINT8 *addr_ptr;
	1333	rmnimbus_state *state = device.machine().driver_data<rmnimbus_state>();
	1334	address_space &space = device.memory().space(AS_PROGRAM);
	1335	UINT8 *addr_ptr;
1336	1336
1337		addr_ptr = (UINT8*)space.get_read_ptr(curpc);
	1337	addr_ptr = (UINT8*)space.get_read_ptr(curpc);
1338	1338
1339	1339	if ((addr_ptr !=NULL) && (addr_ptr[0]==0xCD))
1340	1340	{
r18355	r18356
1347	1347	}
1348	1348
1349	1349	if(DEBUG_SET(DECODE_DOS21) && (addr_ptr[1]==0x21))
1350		decode_dos21(&device,curpc);
	1350	decode_dos21(&device,curpc);
1351	1351	}
1352	1352
1353		return 0;
	1353	return 0;
1354	1354	}
1355	1355
1356	1356	#define set_type(type_name) sprintf(type_str,type_name)
r18355	r18356
1359	1359
1360	1360	static void decode_subbios(device_t *device,offs_t pc, UINT8 raw_flag)
1361	1361	{
1362		char type_str[80];
1363		char drv_str[80];
1364		char func_str[80];
	1362	char type_str[80];
	1363	char drv_str[80];
	1364	char func_str[80];
1365	1365
1366		void (dump_dssi)(device_t ,UINT16, UINT16 ,UINT8) = NULL;
	1366	void (dump_dssi)(device_t ,UINT16, UINT16 ,UINT8) = NULL;
1367	1367
1368		device_t *cpu = device->machine().device(MAINCPU_TAG);
	1368	device_t *cpu = device->machine().device(MAINCPU_TAG);
1369	1369
1370		UINT16 ax = cpu->state().state_int(I8086_AX);
1371		UINT16 bx = cpu->state().state_int(I8086_BX);
1372		UINT16 cx = cpu->state().state_int(I8086_CX);
1373		UINT16 ds = cpu->state().state_int(I8086_DS);
1374		UINT16 si = cpu->state().state_int(I8086_SI);
	1370	UINT16 ax = cpu->state().state_int(I8086_AX);
	1371	UINT16 bx = cpu->state().state_int(I8086_BX);
	1372	UINT16 cx = cpu->state().state_int(I8086_CX);
	1373	UINT16 ds = cpu->state().state_int(I8086_DS);
	1374	UINT16 si = cpu->state().state_int(I8086_SI);
1375	1375
1376	1376	// *** TEMP Don't show f_enquire_display_line calls !
1377	1377	if((cx==6) && (ax==43))
r18355	r18356
1384	1384	logerror("Sub-bios call at %08X, AX=%04X, BX=%04X, CX=%04X, DS:SI=%04X:%04X\n",pc,ax,bx,cx,ds,si);
1385	1385	}
1386	1386
1387		set_type("invalid");
1388		set_drv("invalid");
1389		set_func("invalid");
	1387	set_type("invalid");
	1388	set_drv("invalid");
	1389	set_func("invalid");
1390	1390
1391		switch (cx)
1392		{
1393		case 0 :
1394		{
1395		set_type("t_mummu");
1396		set_drv("d_mummu");
	1391	switch (cx)
	1392	{
	1393	case 0 :
	1394	{
	1395	set_type("t_mummu");
	1396	set_drv("d_mummu");
1397	1397
1398		switch (ax)
1399		{
1400		case 0 : set_func("f_get_version_number"); break;
1401		case 1 : set_func("f_add_type_code"); break;
1402		case 2 : set_func("f_del_typc_code"); break;
1403		case 3 : set_func("f_get_TCB"); break;
1404		case 4 : set_func("f_add_driver_code"); break;
1405		case 5 : set_func("f_del_driver_code"); break;
1406		case 6 : set_func("f_get_DCB"); break;
1407		case 7 : set_func("f_get_copyright"); break;
1408		}
1409		}; break;
	1398	switch (ax)
	1399	{
	1400	case 0 : set_func("f_get_version_number"); break;
	1401	case 1 : set_func("f_add_type_code"); break;
	1402	case 2 : set_func("f_del_typc_code"); break;
	1403	case 3 : set_func("f_get_TCB"); break;
	1404	case 4 : set_func("f_add_driver_code"); break;
	1405	case 5 : set_func("f_del_driver_code"); break;
	1406	case 6 : set_func("f_get_DCB"); break;
	1407	case 7 : set_func("f_get_copyright"); break;
	1408	}
	1409	}; break;
1410	1410
1411		case 1 :
1412		{
1413		set_type("t_character");
1414		set_drv("d_printer");
	1411	case 1 :
	1412	{
	1413	set_type("t_character");
	1414	set_drv("d_printer");
1415	1415
1416		switch(ax)
1417		{
1418		case 0 : set_func("f_get_version_number"); break;
1419		case 1 : set_func("f_get_output_status"); break;
1420		case 2 : set_func("f_output_character"); break;
1421		case 3 : set_func("f_get_input_status"); break;
1422		case 4 : set_func("f_get_and_remove"); break;
1423		case 5 : set_func("f_get_no_remove"); break;
1424		case 6 : set_func("f_get_last_and_remove"); break;
1425		case 7 : set_func("f_get_last_no_remove"); break;
1426		case 8 : set_func("f_set_IO_parameters"); break;
1427		}
1428		}; break;
	1416	switch(ax)
	1417	{
	1418	case 0 : set_func("f_get_version_number"); break;
	1419	case 1 : set_func("f_get_output_status"); break;
	1420	case 2 : set_func("f_output_character"); break;
	1421	case 3 : set_func("f_get_input_status"); break;
	1422	case 4 : set_func("f_get_and_remove"); break;
	1423	case 5 : set_func("f_get_no_remove"); break;
	1424	case 6 : set_func("f_get_last_and_remove"); break;
	1425	case 7 : set_func("f_get_last_no_remove"); break;
	1426	case 8 : set_func("f_set_IO_parameters"); break;
	1427	}
	1428	}; break;
1429	1429
1430		case 2 :
1431		{
1432		set_type("t_disk");
	1430	case 2 :
	1431	{
	1432	set_type("t_disk");
1433	1433
1434		switch(bx)
1435		{
1436		case 0 : set_drv("d_floppy"); break;
1437		case 1 : set_drv("d_winchester"); break;
1438		case 2 : set_drv("d_tape"); break;
1439		case 3 : set_drv("d_rompack"); break;
1440		case 4 : set_drv("d_eeprom"); break;
1441		}
	1434	switch(bx)
	1435	{
	1436	case 0 : set_drv("d_floppy"); break;
	1437	case 1 : set_drv("d_winchester"); break;
	1438	case 2 : set_drv("d_tape"); break;
	1439	case 3 : set_drv("d_rompack"); break;
	1440	case 4 : set_drv("d_eeprom"); break;
	1441	}
1442	1442
1443		switch(ax)
1444		{
1445		case 0 : set_func("f_get_version_number"); break;
1446		case 1 : set_func("f_initialise_unit"); break;
1447		case 2 : set_func("f_pseudo_init_unit"); break;
1448		case 3 : set_func("f_get_device_status"); break;
1449		case 4 : set_func("f_read_n_sectors"); dump_dssi=&decode_dssi_f_rw_sectors; break;
1450		case 5 : set_func("f_write_n_sectors"); dump_dssi=&decode_dssi_f_rw_sectors; break;
1451		case 6 : set_func("f_verify_n_sectors"); break;
1452		case 7 : set_func("f_media_check"); break;
1453		case 8 : set_func("f_recalibrate"); break;
1454		case 9 : set_func("f_motors_off"); break;
1455		}
	1443	switch(ax)
	1444	{
	1445	case 0 : set_func("f_get_version_number"); break;
	1446	case 1 : set_func("f_initialise_unit"); break;
	1447	case 2 : set_func("f_pseudo_init_unit"); break;
	1448	case 3 : set_func("f_get_device_status"); break;
	1449	case 4 : set_func("f_read_n_sectors"); dump_dssi=&decode_dssi_f_rw_sectors; break;
	1450	case 5 : set_func("f_write_n_sectors"); dump_dssi=&decode_dssi_f_rw_sectors; break;
	1451	case 6 : set_func("f_verify_n_sectors"); break;
	1452	case 7 : set_func("f_media_check"); break;
	1453	case 8 : set_func("f_recalibrate"); break;
	1454	case 9 : set_func("f_motors_off"); break;
	1455	}
1456	1456	dump_dssi=&decode_dssi_f_rw_sectors;
1457	1457
1458		}; break;
	1458	}; break;
1459	1459
1460		case 3 :
1461		{
1462		set_type("t_piconet");
1463		set_drv("d_piconet");
	1460	case 3 :
	1461	{
	1462	set_type("t_piconet");
	1463	set_drv("d_piconet");
1464	1464
1465		switch(ax)
1466		{
1467		case 0 : set_func("f_get_version_number"); break;
1468		case 1 : set_func("f_get_slave_status"); break;
1469		case 2 : set_func("f_get_slave_map"); break;
1470		case 3 : set_func("f_change_slave_addr"); break;
1471		case 4 : set_func("f_read_slave_control"); break;
1472		case 5 : set_func("f_write_slave_control"); break;
1473		case 6 : set_func("f_send_data_byte"); break;
1474		case 7 : set_func("f_request_data_byte"); break;
1475		case 8 : set_func("f_send_data_block"); break;
1476		case 9 : set_func("f_request_data_block"); break;
1477		case 10 : set_func("f_reset_slave"); break;
	1465	switch(ax)
	1466	{
	1467	case 0 : set_func("f_get_version_number"); break;
	1468	case 1 : set_func("f_get_slave_status"); break;
	1469	case 2 : set_func("f_get_slave_map"); break;
	1470	case 3 : set_func("f_change_slave_addr"); break;
	1471	case 4 : set_func("f_read_slave_control"); break;
	1472	case 5 : set_func("f_write_slave_control"); break;
	1473	case 6 : set_func("f_send_data_byte"); break;
	1474	case 7 : set_func("f_request_data_byte"); break;
	1475	case 8 : set_func("f_send_data_block"); break;
	1476	case 9 : set_func("f_request_data_block"); break;
	1477	case 10 : set_func("f_reset_slave"); break;
1478	1478
1479		}
1480		}; break;
	1479	}
	1480	}; break;
1481	1481
1482		case 4 :
1483		{
1484		set_type("t_tick");
1485		set_drv("d_tick");
	1482	case 4 :
	1483	{
	1484	set_type("t_tick");
	1485	set_drv("d_tick");
1486	1486
1487		switch(ax)
1488		{
1489		case 0 : set_func("f_get_version_number"); break;
1490		case 1 : set_func("f_ticks_per_second"); break;
1491		case 2 : set_func("f_link_tick_routine"); break;
1492		case 3 : set_func("f_unlink_tick_routine"); break;
1493		}
1494		}; break;
	1487	switch(ax)
	1488	{
	1489	case 0 : set_func("f_get_version_number"); break;
	1490	case 1 : set_func("f_ticks_per_second"); break;
	1491	case 2 : set_func("f_link_tick_routine"); break;
	1492	case 3 : set_func("f_unlink_tick_routine"); break;
	1493	}
	1494	}; break;
1495	1495
1496		case 5 :
1497		{
1498		set_type("t_graphics_input");
	1496	case 5 :
	1497	{
	1498	set_type("t_graphics_input");
1499	1499
1500		switch(bx)
1501		{
1502		case 0 : set_drv("d_mouse"); break;
1503		case 1 : set_drv("d_joystick_1"); break;
1504		case 2 : set_drv("d_joystick_2"); break;
1505		}
	1500	switch(bx)
	1501	{
	1502	case 0 : set_drv("d_mouse"); break;
	1503	case 1 : set_drv("d_joystick_1"); break;
	1504	case 2 : set_drv("d_joystick_2"); break;
	1505	}
1506	1506
1507	1507
1508		switch(ax)
1509		{
1510		case 0 : set_func("f_get_version_number"); break;
1511		case 1 : set_func("f_graphics_input_cold_start"); break;
1512		case 2 : set_func("f_graphics_input_device_off"); break;
1513		case 3 : set_func("f_return_button_status"); break;
1514		case 4 : set_func("f_return_switch_and_button_stat"); break;
1515		case 5 : set_func("f_start_tracking"); break;
1516		case 6 : set_func("f_stop_tracking"); break;
1517		case 7 : set_func("f_enquire_position"); break;
1518		case 8 : set_func("f_set_position"); break;
	1508	switch(ax)
	1509	{
	1510	case 0 : set_func("f_get_version_number"); break;
	1511	case 1 : set_func("f_graphics_input_cold_start"); break;
	1512	case 2 : set_func("f_graphics_input_device_off"); break;
	1513	case 3 : set_func("f_return_button_status"); break;
	1514	case 4 : set_func("f_return_switch_and_button_stat"); break;
	1515	case 5 : set_func("f_start_tracking"); break;
	1516	case 6 : set_func("f_stop_tracking"); break;
	1517	case 7 : set_func("f_enquire_position"); break;
	1518	case 8 : set_func("f_set_position"); break;
1519	1519
1520		case 10 : set_func("f_return_button_press_info"); break;
1521		case 11 : set_func("f_return_button_release_info"); break;
1522		case 12 : set_func("f_set_gain/f_set_squeaks_per_pixel_ratio"); break;
1523		case 13 : set_func("f_enquire_graphics_in_misc_data"); break;
1524		}
1525		}; break;
	1520	case 10 : set_func("f_return_button_press_info"); break;
	1521	case 11 : set_func("f_return_button_release_info"); break;
	1522	case 12 : set_func("f_set_gain/f_set_squeaks_per_pixel_ratio"); break;
	1523	case 13 : set_func("f_enquire_graphics_in_misc_data"); break;
	1524	}
	1525	}; break;
1526	1526
1527		case 6 :
1528		{
1529		set_type("t_graphics_output");
1530		set_drv("d_ngc_screen");
	1527	case 6 :
	1528	{
	1529	set_type("t_graphics_output");
	1530	set_drv("d_ngc_screen");
1531	1531
1532		switch(ax)
1533		{
1534		case 0 : set_func("f_get_version_number"); break;
1535		case 1 : set_func("f_graphics_output_cold_start"); break;
1536		case 2 : set_func("f_graphics_output_warm_start"); break;
1537		case 3 : set_func("f_graphics_output_off"); break;
1538		case 4 : set_func("f_reinit_graphics_output"); break;
1539		case 5 : set_func("f_polymarker"); break;
1540		case 6 : set_func("f_polyline"); dump_dssi=&decode_dssi_f_fill_area; break;
1541		case 7 : set_func("f_fill_area"); dump_dssi=&decode_dssi_f_fill_area; break;
1542		case 8 : set_func("f_flood_fill_area"); break;
1543		case 9 : set_func("f_plot_character_string"); dump_dssi=&decode_dssi_f_plot_character_string; break;
1544		case 10 : set_func("f_define_graphics_clipping_area"); break;
1545		case 11 : set_func("f_enquire_clipping_area_limits"); break;
1546		case 12 : set_func("f_select_graphics_clipping_area"); break;
1547		case 13 : set_func("f_enq_selctd_graphics_clip_area"); break;
1548		case 14 : set_func("f_set_clt_element"); break;
1549		case 15 : set_func("f_enquire_clt_element"); break;
1550		case 16 : set_func("f_set_new_clt"); dump_dssi=&decode_dssi_f_set_new_clt; break;
1551		case 17 : set_func("f_enquire_clt_contents"); break;
1552		case 18 : set_func("f_define_dithering_pattern"); break;
1553		case 19 : set_func("f_enquire_dithering_pattern"); break;
1554		case 20 : set_func("f_draw_sprite"); break;
1555		case 21 : set_func("f_move_sprite"); break;
1556		case 22 : set_func("f_erase_sprite"); break;
1557		case 23 : set_func("f_read_pixel"); break;
1558		case 24 : set_func("f_read_to_limit"); break;
1559		case 25 : set_func("f_read_area_pixel"); break;
1560		case 26 : set_func("f_write_area_pixel"); break;
1561		case 27 : set_func("f_copy_area_pixel"); break;
	1532	switch(ax)
	1533	{
	1534	case 0 : set_func("f_get_version_number"); break;
	1535	case 1 : set_func("f_graphics_output_cold_start"); break;
	1536	case 2 : set_func("f_graphics_output_warm_start"); break;
	1537	case 3 : set_func("f_graphics_output_off"); break;
	1538	case 4 : set_func("f_reinit_graphics_output"); break;
	1539	case 5 : set_func("f_polymarker"); break;
	1540	case 6 : set_func("f_polyline"); dump_dssi=&decode_dssi_f_fill_area; break;
	1541	case 7 : set_func("f_fill_area"); dump_dssi=&decode_dssi_f_fill_area; break;
	1542	case 8 : set_func("f_flood_fill_area"); break;
	1543	case 9 : set_func("f_plot_character_string"); dump_dssi=&decode_dssi_f_plot_character_string; break;
	1544	case 10 : set_func("f_define_graphics_clipping_area"); break;
	1545	case 11 : set_func("f_enquire_clipping_area_limits"); break;
	1546	case 12 : set_func("f_select_graphics_clipping_area"); break;
	1547	case 13 : set_func("f_enq_selctd_graphics_clip_area"); break;
	1548	case 14 : set_func("f_set_clt_element"); break;
	1549	case 15 : set_func("f_enquire_clt_element"); break;
	1550	case 16 : set_func("f_set_new_clt"); dump_dssi=&decode_dssi_f_set_new_clt; break;
	1551	case 17 : set_func("f_enquire_clt_contents"); break;
	1552	case 18 : set_func("f_define_dithering_pattern"); break;
	1553	case 19 : set_func("f_enquire_dithering_pattern"); break;
	1554	case 20 : set_func("f_draw_sprite"); break;
	1555	case 21 : set_func("f_move_sprite"); break;
	1556	case 22 : set_func("f_erase_sprite"); break;
	1557	case 23 : set_func("f_read_pixel"); break;
	1558	case 24 : set_func("f_read_to_limit"); break;
	1559	case 25 : set_func("f_read_area_pixel"); break;
	1560	case 26 : set_func("f_write_area_pixel"); break;
	1561	case 27 : set_func("f_copy_area_pixel"); break;
1562	1562
1563		case 29 : set_func("f_read_area_word"); break;
1564		case 30 : set_func("f_write_area_word"); break;
1565		case 31 : set_func("f_copy_area_word"); break;
1566		case 32 : set_func("f_swap_area_word"); break;
1567		case 33 : set_func("f_set_border_colour"); break;
1568		case 34 : set_func("f_enquire_border_colour"); break;
1569		case 35 : set_func("f_enquire_miscellaneous_data"); break;
1570		case 36 : set_func("f_circle"); break;
	1563	case 29 : set_func("f_read_area_word"); break;
	1564	case 30 : set_func("f_write_area_word"); break;
	1565	case 31 : set_func("f_copy_area_word"); break;
	1566	case 32 : set_func("f_swap_area_word"); break;
	1567	case 33 : set_func("f_set_border_colour"); break;
	1568	case 34 : set_func("f_enquire_border_colour"); break;
	1569	case 35 : set_func("f_enquire_miscellaneous_data"); break;
	1570	case 36 : set_func("f_circle"); break;
1571	1571
1572		case 38 : set_func("f_arc_of_ellipse"); break;
1573		case 39 : set_func("f_isin"); break;
1574		case 40 : set_func("f_icos"); break;
1575		case 41 : set_func("f_define_hatching_pattern"); break;
1576		case 42 : set_func("f_enquire_hatching_pattern"); break;
1577		case 43 : set_func("f_enquire_display_line"); break;
1578		case 44 : set_func("f_plonk_logo"); break;
1579		}
1580		}; break;
	1572	case 38 : set_func("f_arc_of_ellipse"); break;
	1573	case 39 : set_func("f_isin"); break;
	1574	case 40 : set_func("f_icos"); break;
	1575	case 41 : set_func("f_define_hatching_pattern"); break;
	1576	case 42 : set_func("f_enquire_hatching_pattern"); break;
	1577	case 43 : set_func("f_enquire_display_line"); break;
	1578	case 44 : set_func("f_plonk_logo"); break;
	1579	}
	1580	}; break;
1581	1581
1582		case 7 :
1583		{
1584		set_type("t_zend");
1585		switch(ax)
1586		{
1587		case 0 : set_func("f_get_version_number"); break;
1588		}
1589		}; break;
	1582	case 7 :
	1583	{
	1584	set_type("t_zend");
	1585	switch(ax)
	1586	{
	1587	case 0 : set_func("f_get_version_number"); break;
	1588	}
	1589	}; break;
1590	1590
1591		case 8 :
1592		{
1593		set_type("t_zep");
1594		switch(ax)
1595		{
1596		case 0 : set_func("f_get_version_number"); break;
1597		}
1598		}; break;
	1591	case 8 :
	1592	{
	1593	set_type("t_zep");
	1594	switch(ax)
	1595	{
	1596	case 0 : set_func("f_get_version_number"); break;
	1597	}
	1598	}; break;
1599	1599
1600		case 9 :
1601		{
1602		set_type("t_raw_console");
	1600	case 9 :
	1601	{
	1602	set_type("t_raw_console");
1603	1603
1604		switch(bx)
1605		{
1606		case 0 :
1607		{
1608		set_drv("d_screen");
	1604	switch(bx)
	1605	{
	1606	case 0 :
	1607	{
	1608	set_drv("d_screen");
1609	1609
1610		switch(ax)
1611		{
1612		case 0 : set_func("f_get_version_number"); break;
1613		case 1 : set_func("f_plonk_char"); dump_dssi=decode_dssi_f_plonk_char; break;
1614		case 2 : set_func("f_plonk_cursor"); break;
1615		case 3 : set_func("f_kill_cursor"); break;
1616		case 4 : set_func("f_scroll"); break;
1617		case 5 : set_func("f_width"); dump_dssi=decode_dssi_generic;break;
1618		case 6 : set_func("f_get_char_set"); break;
1619		case 7 : set_func("f_set_char_set"); break;
1620		case 8 : set_func("f_reset_char_set"); break;
1621		case 9 : set_func("f_set_plonk_parameters"); break;
1622		case 10 : set_func("f_set_cursor_flash_rate"); break;
1623		}
1624		}; break;
	1610	switch(ax)
	1611	{
	1612	case 0 : set_func("f_get_version_number"); break;
	1613	case 1 : set_func("f_plonk_char"); dump_dssi=decode_dssi_f_plonk_char; break;
	1614	case 2 : set_func("f_plonk_cursor"); break;
	1615	case 3 : set_func("f_kill_cursor"); break;
	1616	case 4 : set_func("f_scroll"); break;
	1617	case 5 : set_func("f_width"); dump_dssi=decode_dssi_generic;break;
	1618	case 6 : set_func("f_get_char_set"); break;
	1619	case 7 : set_func("f_set_char_set"); break;
	1620	case 8 : set_func("f_reset_char_set"); break;
	1621	case 9 : set_func("f_set_plonk_parameters"); break;
	1622	case 10 : set_func("f_set_cursor_flash_rate"); break;
	1623	}
	1624	}; break;
1625	1625
1626		case 1 :
1627		{
1628		set_drv("d_keyboard");
	1626	case 1 :
	1627	{
	1628	set_drv("d_keyboard");
1629	1629
1630		switch(ax)
1631		{
1632		case 0 : set_func("f_get_version_number"); break;
1633		case 1 : set_func("f_init_keyboard"); break;
1634		case 2 : set_func("f_get_last_key_code"); break;
1635		case 3 : set_func("f_get_bitmap"); break;
1636		}
1637		}; break;
1638		}
1639		}; break;
	1630	switch(ax)
	1631	{
	1632	case 0 : set_func("f_get_version_number"); break;
	1633	case 1 : set_func("f_init_keyboard"); break;
	1634	case 2 : set_func("f_get_last_key_code"); break;
	1635	case 3 : set_func("f_get_bitmap"); break;
	1636	}
	1637	}; break;
	1638	}
	1639	}; break;
1640	1640
1641		case 10 :
1642		{
	1641	case 10 :
	1642	{
1643	1643
1644		set_type("t_acoustics");
	1644	set_type("t_acoustics");
1645	1645
1646		switch(bx)
1647		{
1648		case 0 :
1649		{
1650		set_drv("d_sound");
	1646	switch(bx)
	1647	{
	1648	case 0 :
	1649	{
	1650	set_drv("d_sound");
1651	1651
1652		switch(ax)
1653		{
1654		case 0 : set_func("f_get_version_number"); break;
1655		case 1 : set_func("f_sound_enable"); break;
1656		case 2 : set_func("f_play_note"); break;
1657		case 3 : set_func("f_get_queue_status"); break;
1658		}
1659		}; break;
	1652	switch(ax)
	1653	{
	1654	case 0 : set_func("f_get_version_number"); break;
	1655	case 1 : set_func("f_sound_enable"); break;
	1656	case 2 : set_func("f_play_note"); break;
	1657	case 3 : set_func("f_get_queue_status"); break;
	1658	}
	1659	}; break;
1660	1660
1661		case 1 :
1662		{
1663		set_drv("d_voice");
	1661	case 1 :
	1662	{
	1663	set_drv("d_voice");
1664	1664
1665		switch(ax)
1666		{
1667		case 0 : set_func("f_get_version_number"); break;
1668		case 1 : set_func("f_talk"); break;
1669		case 2 : set_func("f_wait_and_talk"); break;
1670		case 3 : set_func("f_test_talking"); break;
1671		}
1672		}
1673		}
1674		}; break;
	1665	switch(ax)
	1666	{
	1667	case 0 : set_func("f_get_version_number"); break;
	1668	case 1 : set_func("f_talk"); break;
	1669	case 2 : set_func("f_wait_and_talk"); break;
	1670	case 3 : set_func("f_test_talking"); break;
	1671	}
	1672	}
	1673	}
	1674	}; break;
1675	1675
1676		case 11 :
1677		{
1678		set_type("t_hard_sums");
1679		switch(ax)
1680		{
1681		case 0 : set_func("f_get_version_number"); break;
1682		}
1683		}; break;
1684		}
	1676	case 11 :
	1677	{
	1678	set_type("t_hard_sums");
	1679	switch(ax)
	1680	{
	1681	case 0 : set_func("f_get_version_number"); break;
	1682	}
	1683	}; break;
	1684	}
1685	1685
1686	1686	if(raw_flag)
1687	1687	{
r18355	r18356
1700	1700
1701	1701	static void *get_dssi_ptr(address_space &space, UINT16 ds, UINT16 si)
1702	1702	{
1703		int addr;
	1703	int addr;
1704	1704
1705		addr=((ds<<4)+si);
	1705	addr=((ds<<4)+si);
1706	1706	// OUTPUT_SEGOFS("DS:SI",ds,si);
1707	1707
1708		return space.get_read_ptr(addr);
	1708	return space.get_read_ptr(addr);
1709	1709	}
1710	1710
1711	1711	static void decode_dssi_generic(device_t *device,UINT16 ds, UINT16 si, UINT8 raw_flag)
1712	1712	{
1713	1713	address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1714		UINT16 *params;
1715		int count;
	1714	UINT16 *params;
	1715	int count;
1716	1716
1717		if(raw_flag)
	1717	if(raw_flag)
1718	1718	return;
1719	1719
1720		params=(UINT16 *)get_dssi_ptr(space,ds,si);
	1720	params=(UINT16 *)get_dssi_ptr(space,ds,si);
1721	1721
1722	1722	for(count=0; count<10; count++)
1723	1723	logerror("%04X ",params[count]);
r18355	r18356
1728	1728
1729	1729	static void decode_dssi_f_fill_area(device_t *device,UINT16 ds, UINT16 si, UINT8 raw_flag)
1730	1730	{
1731		address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
	1731	address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1732	1732
1733		UINT16 *addr_ptr;
1734		t_area_params *area_params;
1735		t_nimbus_brush *brush;
1736		int cocount;
	1733	UINT16 *addr_ptr;
	1734	t_area_params *area_params;
	1735	t_nimbus_brush *brush;
	1736	int cocount;
1737	1737
1738		area_params = (t_area_params *)get_dssi_ptr(space,ds,si);
	1738	area_params = (t_area_params *)get_dssi_ptr(space,ds,si);
1739	1739
1740		if (!raw_flag)
	1740	if (!raw_flag)
1741	1741	OUTPUT_SEGOFS("SegBrush:OfsBrush",area_params->seg_brush,area_params->ofs_brush);
1742	1742
1743	1743	brush=(t_nimbus_brush *)space.get_read_ptr(LINEAR_ADDR(area_params->seg_brush,area_params->ofs_brush));
1744	1744
1745		if(raw_flag)
	1745	if(raw_flag)
1746	1746	{
1747	1747	logerror("\tdw\t%04X, %04X, %04X, %04X, %04X, %04X, %04X, %04X, %04X, ",
1748		brush->style,brush->style_index,brush->colour1,brush->colour2,
1749		brush->transparency,brush->boundary_spec,brush->boundary_colour,brush->save_colour,
1750		area_params->count);
	1748	brush->style,brush->style_index,brush->colour1,brush->colour2,
	1749	brush->transparency,brush->boundary_spec,brush->boundary_colour,brush->save_colour,
	1750	area_params->count);
1751	1751	}
1752	1752	else
1753	1753	{
r18355	r18356
1761	1761	OUTPUT_SEGOFS("SegData:OfsData",area_params->seg_data,area_params->ofs_data);
1762	1762	}
1763	1763
1764		addr_ptr = (UINT16 *)space.get_read_ptr(LINEAR_ADDR(area_params->seg_data,area_params->ofs_data));
1765		for(cocount=0; cocount < area_params->count; cocount++)
1766		{
	1764	addr_ptr = (UINT16 *)space.get_read_ptr(LINEAR_ADDR(area_params->seg_data,area_params->ofs_data));
	1765	for(cocount=0; cocount < area_params->count; cocount++)
	1766	{
1767	1767	if(raw_flag)
1768	1768	{
1769	1769	if(cocount!=(area_params->count-1))
r18355	r18356
1773	1773	}
1774	1774	else
1775	1775	logerror("x=%d y=%d\n",addr_ptr[cocount2],addr_ptr[(cocount2)+1]);
1776		}
	1776	}
1777	1777
1778	1778	if(raw_flag)
1779	1779	logerror("\n");
r18355	r18356
1781	1781
1782	1782	static void decode_dssi_f_plot_character_string(device_t *device,UINT16 ds, UINT16 si, UINT8 raw_flag)
1783	1783	{
1784		address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
	1784	address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1785	1785
1786		UINT8 *char_ptr;
1787		t_plot_string_params *plot_string_params;
1788		int charno;
	1786	UINT8 *char_ptr;
	1787	t_plot_string_params *plot_string_params;
	1788	int charno;
1789	1789
1790		if(raw_flag)
	1790	if(raw_flag)
1791	1791	return;
1792	1792
1793		plot_string_params=(t_plot_string_params *)get_dssi_ptr(space,ds,si);
	1793	plot_string_params=(t_plot_string_params *)get_dssi_ptr(space,ds,si);
1794	1794
1795		OUTPUT_SEGOFS("SegFont:OfsFont",plot_string_params->seg_font,plot_string_params->ofs_font);
1796		OUTPUT_SEGOFS("SegData:OfsData",plot_string_params->seg_data,plot_string_params->ofs_data);
	1795	OUTPUT_SEGOFS("SegFont:OfsFont",plot_string_params->seg_font,plot_string_params->ofs_font);
	1796	OUTPUT_SEGOFS("SegData:OfsData",plot_string_params->seg_data,plot_string_params->ofs_data);
1797	1797
1798		logerror("x=%d, y=%d, length=%d\n",plot_string_params->x,plot_string_params->y,plot_string_params->length);
	1798	logerror("x=%d, y=%d, length=%d\n",plot_string_params->x,plot_string_params->y,plot_string_params->length);
1799	1799
1800		char_ptr=(UINT8*)space.get_read_ptr(LINEAR_ADDR(plot_string_params->seg_data,plot_string_params->ofs_data));
	1800	char_ptr=(UINT8*)space.get_read_ptr(LINEAR_ADDR(plot_string_params->seg_data,plot_string_params->ofs_data));
1801	1801
1802		if (plot_string_params->length==0xFFFF)
1803		logerror("%s",char_ptr);
1804		else
1805		for(charno=0;charno<plot_string_params->length;charno++)
1806		logerror("%c",char_ptr[charno]);
	1802	if (plot_string_params->length==0xFFFF)
	1803	logerror("%s",char_ptr);
	1804	else
	1805	for(charno=0;charno<plot_string_params->length;charno++)
	1806	logerror("%c",char_ptr[charno]);
1807	1807
1808		logerror("\n");
	1808	logerror("\n");
1809	1809	}
1810	1810
1811	1811	static void decode_dssi_f_set_new_clt(device_t *device,UINT16 ds, UINT16 si, UINT8 raw_flag)
1812	1812	{
1813		address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1814		UINT16 *new_colours;
1815		int colour;
1816		new_colours=(UINT16 *)get_dssi_ptr(space,ds,si);
	1813	address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
	1814	UINT16 *new_colours;
	1815	int colour;
	1816	new_colours=(UINT16 *)get_dssi_ptr(space,ds,si);
1817	1817
1818		if(raw_flag)
	1818	if(raw_flag)
1819	1819	return;
1820	1820
1821		OUTPUT_SEGOFS("SegColours:OfsColours",ds,si);
	1821	OUTPUT_SEGOFS("SegColours:OfsColours",ds,si);
1822	1822
1823		for(colour=0;colour<16;colour++)
1824		logerror("colour #%02X=%04X\n",colour,new_colours[colour]);
	1823	for(colour=0;colour<16;colour++)
	1824	logerror("colour #%02X=%04X\n",colour,new_colours[colour]);
1825	1825
1826	1826	}
1827	1827
1828	1828	static void decode_dssi_f_plonk_char(device_t *device,UINT16 ds, UINT16 si, UINT8 raw_flag)
1829	1829	{
1830		address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1831		UINT16 *params;
1832		params=(UINT16 *)get_dssi_ptr(space,ds,si);
	1830	address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
	1831	UINT16 *params;
	1832	params=(UINT16 *)get_dssi_ptr(space,ds,si);
1833	1833
1834		if(raw_flag)
	1834	if(raw_flag)
1835	1835	return;
1836	1836
1837		OUTPUT_SEGOFS("SegParams:OfsParams",ds,si);
	1837	OUTPUT_SEGOFS("SegParams:OfsParams",ds,si);
1838	1838
1839		logerror("plonked_char=%c\n",params[0]);
	1839	logerror("plonked_char=%c\n",params[0]);
1840	1840	}
1841	1841
1842	1842	static void decode_dssi_f_rw_sectors(device_t *device,UINT16 ds, UINT16 si, UINT8 raw_flag)
1843	1843	{
1844		address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
1845		UINT16 *params;
1846		int param_no;
	1844	address_space &space = device->machine().device(MAINCPU_TAG)->memory().space(AS_PROGRAM);
	1845	UINT16 *params;
	1846	int param_no;
1847	1847
1848		if(raw_flag)
	1848	if(raw_flag)
1849	1849	return;
1850	1850
1851		params=(UINT16 *)get_dssi_ptr(space,ds,si);
	1851	params=(UINT16 *)get_dssi_ptr(space,ds,si);
1852	1852
1853		for(param_no=0;param_no<16;param_no++)
1854		logerror("%04X ",params[param_no]);
	1853	for(param_no=0;param_no<16;param_no++)
	1854	logerror("%04X ",params[param_no]);
1855	1855
1856		logerror("\n");
	1856	logerror("\n");
1857	1857	}
1858	1858
1859	1859	static void decode_dos21(device_t *device,offs_t pc)
1860	1860	{
1861		device_t *cpu = device->machine().device(MAINCPU_TAG);
	1861	device_t *cpu = device->machine().device(MAINCPU_TAG);
1862	1862
1863		UINT16 ax = cpu->state().state_int(I8086_AX);
1864		UINT16 bx = cpu->state().state_int(I8086_BX);
1865		UINT16 cx = cpu->state().state_int(I8086_CX);
	1863	UINT16 ax = cpu->state().state_int(I8086_AX);
	1864	UINT16 bx = cpu->state().state_int(I8086_BX);
	1865	UINT16 cx = cpu->state().state_int(I8086_CX);
1866	1866	UINT16 dx = cpu->state().state_int(I8086_DX);
1867		UINT16 cs = cpu->state().state_int(I8086_CS);
	1867	UINT16 cs = cpu->state().state_int(I8086_CS);
1868	1868	UINT16 ds = cpu->state().state_int(I8086_DS);
1869	1869	UINT16 es = cpu->state().state_int(I8086_ES);
1870	1870	UINT16 ss = cpu->state().state_int(I8086_SS);
1871	1871
1872		UINT16 si = cpu->state().state_int(I8086_SI);
1873		UINT16 di = cpu->state().state_int(I8086_DI);
	1872	UINT16 si = cpu->state().state_int(I8086_SI);
	1873	UINT16 di = cpu->state().state_int(I8086_DI);
1874	1874	UINT16 bp = cpu->state().state_int(I8086_BP);
1875	1875
1876		logerror("=======================================================================\n");
1877		logerror("DOS Int 0x21 call at %05X\n",pc);
	1876	logerror("=======================================================================\n");
	1877	logerror("DOS Int 0x21 call at %05X\n",pc);
1878	1878	logerror("AX=%04X, BX=%04X, CX=%04X, DX=%04X\n",ax,bx,cx,dx);
1879	1879	logerror("CS=%04X, DS=%04X, ES=%04X, SS=%04X\n",cs,ds,es,ss);
1880	1880	logerror("SI=%04X, DI=%04X, BP=%04X\n",si,di,bp);
1881		logerror("=======================================================================\n");
	1881	logerror("=======================================================================\n");
1882	1882
1883	1883	if((ax & 0xff00)==0x0900)
1884	1884	debugger_break(device->machine());
r18355	r18356
1939	1939
1940	1940	struct nimbus_meminfo
1941	1941	{
1942		offs_t start; /* start address of bank */
1943		offs_t end; /* End address of bank */
	1942	offs_t start; /* start address of bank */
	1943	offs_t end; /* End address of bank */
1944	1944	};
1945	1945
1946	1946	static const struct nimbus_meminfo memmap[] =
1947	1947	{
1948		{ 0x00000, 0x1FFFF },
1949		{ 0x20000, 0x3FFFF },
1950		{ 0x40000, 0x5FFFF },
1951		{ 0x60000, 0x7FFFF },
1952		{ 0x80000, 0x9FFFF },
1953		{ 0xA0000, 0xBFFFF },
1954		{ 0xC0000, 0xDFFFF },
1955		{ 0xE0000, 0xEFFFF }
	1948	{ 0x00000, 0x1FFFF },
	1949	{ 0x20000, 0x3FFFF },
	1950	{ 0x40000, 0x5FFFF },
	1951	{ 0x60000, 0x7FFFF },
	1952	{ 0x80000, 0x9FFFF },
	1953	{ 0xA0000, 0xBFFFF },
	1954	{ 0xC0000, 0xDFFFF },
	1955	{ 0xE0000, 0xEFFFF }
1956	1956	};
1957	1957
1958	1958	struct nimbus_block
1959	1959	{
1960		int blockbase;
1961		int blocksize;
	1960	int blockbase;
	1961	int blocksize;
1962	1962	};
1963	1963
1964	1964	typedef nimbus_block nimbus_blocks[3];
1965	1965
1966	1966	static const nimbus_blocks ramblocks[] =
1967	1967	{
1968		{{ 0, 128 }, { 000, 000 }, { 000, 000 }} ,
1969		{{ 0, 128 }, { 128, 128 }, { 000, 000 }} ,
1970		{{ 0, 128 }, { 128, 128 }, { 256, 128 }} ,
1971		{{ 0, 512 }, { 000, 000 }, { 000, 000 }} ,
1972		{{ 0, 512 }, { 512, 128 }, { 000, 000 }} ,
1973		{{ 0, 512 }, { 512, 512 }, { 000, 000 }} ,
1974		{{ 0, 512 }, { 512, 512 }, { 1024, 512 } }
	1968	{{ 0, 128 }, { 000, 000 }, { 000, 000 }} ,
	1969	{{ 0, 128 }, { 128, 128 }, { 000, 000 }} ,
	1970	{{ 0, 128 }, { 128, 128 }, { 256, 128 }} ,
	1971	{{ 0, 512 }, { 000, 000 }, { 000, 000 }} ,
	1972	{{ 0, 512 }, { 512, 128 }, { 000, 000 }} ,
	1973	{{ 0, 512 }, { 512, 512 }, { 000, 000 }} ,
	1974	{{ 0, 512 }, { 512, 512 }, { 1024, 512 } }
1975	1975	};
1976	1976
1977	1977	static void nimbus_bank_memory(running_machine &machine)
1978	1978	{
1979	1979	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
1980		address_space &space = machine.device( MAINCPU_TAG)->memory().space( AS_PROGRAM );
1981		int ramsize = machine.device<ram_device>(RAM_TAG)->size();
1982		int ramblock = 0;
1983		int blockno;
1984		char bank[10];
1985		UINT8 *ram = &machine.device<ram_device>(RAM_TAG)->pointer()[0];
1986		UINT8 *map_blocks[3];
1987		UINT8 *map_base;
1988		int map_blockno;
1989		int block_ofs;
	1980	address_space &space = machine.device( MAINCPU_TAG)->memory().space( AS_PROGRAM );
	1981	int ramsize = machine.device<ram_device>(RAM_TAG)->size();
	1982	int ramblock = 0;
	1983	int blockno;
	1984	char bank[10];
	1985	UINT8 *ram = &machine.device<ram_device>(RAM_TAG)->pointer()[0];
	1986	UINT8 *map_blocks[3];
	1987	UINT8 *map_base;
	1988	int map_blockno;
	1989	int block_ofs;
1990	1990
1991		UINT8 ramsel = (state->m_mcu_reg080 & 0x1F);
	1991	UINT8 ramsel = (state->m_mcu_reg080 & 0x1F);
1992	1992
1993		// Invalid ramsel, return.
1994		if((ramsel & 0x07)!=0x07)
1995		return;
	1993	// Invalid ramsel, return.
	1994	if((ramsel & 0x07)!=0x07)
	1995	return;
1996	1996
1997		switch (ramsize / 1024)
1998		{
1999		case 128 : ramblock=0; break;
2000		case 256 : ramblock=1; break;
2001		case 384 : ramblock=2; break;
2002		case 512 : ramblock=3; break;
2003		case 640 : ramblock=4; break;
2004		case 1024 : ramblock=5; break;
2005		case 1536 : ramblock=6; break;
2006		}
	1997	switch (ramsize / 1024)
	1998	{
	1999	case 128 : ramblock=0; break;
	2000	case 256 : ramblock=1; break;
	2001	case 384 : ramblock=2; break;
	2002	case 512 : ramblock=3; break;
	2003	case 640 : ramblock=4; break;
	2004	case 1024 : ramblock=5; break;
	2005	case 1536 : ramblock=6; break;
	2006	}
2007	2007
2008		map_blocks[0] = ram;
2009		map_blocks[1] = (ramblocks[ramblock][1].blocksize==0) ? NULL : &ram[ramblocks[ramblock][1].blockbase*1024];
2010		map_blocks[2] = (ramblocks[ramblock][2].blocksize==0) ? NULL : &ram[ramblocks[ramblock][2].blockbase*1024];
	2008	map_blocks[0] = ram;
	2009	map_blocks[1] = (ramblocks[ramblock][1].blocksize==0) ? NULL : &ram[ramblocks[ramblock][1].blockbase*1024];
	2010	map_blocks[2] = (ramblocks[ramblock][2].blocksize==0) ? NULL : &ram[ramblocks[ramblock][2].blockbase*1024];
2011	2011
2012		//if(LOG_RAM) logerror("\n\nmcu_reg080=%02X, ramblock=%d, map_blocks[0]=%X, map_blocks[1]=%X, map_blocks[2]=%X\n",state->m_mcu_reg080,ramblock,(int)map_blocks[0],(int)map_blocks[1],(int)map_blocks[2]);
	2012	//if(LOG_RAM) logerror("\n\nmcu_reg080=%02X, ramblock=%d, map_blocks[0]=%X, map_blocks[1]=%X, map_blocks[2]=%X\n",state->m_mcu_reg080,ramblock,(int)map_blocks[0],(int)map_blocks[1],(int)map_blocks[2]);
2013	2013
2014		for(blockno=0;blockno<8;blockno++)
2015		{
2016		sprintf(bank,"bank%d",blockno);
	2014	for(blockno=0;blockno<8;blockno++)
	2015	{
	2016	sprintf(bank,"bank%d",blockno);
2017	2017
2018		switch (ramsel)
2019		{
2020		case 0x07 : (blockno<3) ? map_blockno=blockno : map_blockno=-1; break;
2021		case 0x1F : (blockno<4) ? map_blockno=0 : map_blockno=1; break;
2022		case 0x0F : (blockno<4) ? map_blockno=1 : map_blockno=0; break;
2023		case 0x17 : (blockno<4) ? map_blockno=1 : map_blockno=2; break;
2024		default : map_blockno=-1;
2025		}
2026		block_ofs=(ramsel==0x07) ? 0 : ((blockno % 4)*128);
	2018	switch (ramsel)
	2019	{
	2020	case 0x07 : (blockno<3) ? map_blockno=blockno : map_blockno=-1; break;
	2021	case 0x1F : (blockno<4) ? map_blockno=0 : map_blockno=1; break;
	2022	case 0x0F : (blockno<4) ? map_blockno=1 : map_blockno=0; break;
	2023	case 0x17 : (blockno<4) ? map_blockno=1 : map_blockno=2; break;
	2024	default : map_blockno=-1;
	2025	}
	2026	block_ofs=(ramsel==0x07) ? 0 : ((blockno % 4)*128);
2027	2027
2028	2028
2029		if(LOG_RAM) logerror("mapped %s",bank);
	2029	if(LOG_RAM) logerror("mapped %s",bank);
2030	2030
2031		if((block_ofs < ramblocks[ramblock][map_blockno].blocksize) &&
2032		(map_blocks[map_blockno]!=NULL) && (map_blockno>-1))
2033		{
2034		map_base=(ramsel==0x07) ? map_blocks[map_blockno] : &map_blocks[map_blockno][block_ofs*1024];
	2031	if((block_ofs < ramblocks[ramblock][map_blockno].blocksize) &&
	2032	(map_blocks[map_blockno]!=NULL) && (map_blockno>-1))
	2033	{
	2034	map_base=(ramsel==0x07) ? map_blocks[map_blockno] : &map_blocks[map_blockno][block_ofs*1024];
2035	2035
2036		state->membank(bank)->set_base(map_base);
2037		space.install_readwrite_bank(memmap[blockno].start, memmap[blockno].end, bank);
2038		//if(LOG_RAM) logerror(", base=%X\n",(int)map_base);
2039		}
2040		else
2041		{
2042		space.nop_readwrite(memmap[blockno].start, memmap[blockno].end);
2043		if(LOG_RAM) logerror("NOP\n");
2044		}
2045		}
	2036	state->membank(bank)->set_base(map_base);
	2037	space.install_readwrite_bank(memmap[blockno].start, memmap[blockno].end, bank);
	2038	//if(LOG_RAM) logerror(", base=%X\n",(int)map_base);
	2039	}
	2040	else
	2041	{
	2042	space.nop_readwrite(memmap[blockno].start, memmap[blockno].end);
	2043	if(LOG_RAM) logerror("NOP\n");
	2044	}
	2045	}
2046	2046	}
2047	2047
2048	2048	READ8_MEMBER(rmnimbus_state::nimbus_mcu_r)
2049	2049	{
2050		return m_mcu_reg080;
	2050	return m_mcu_reg080;
2051	2051	}
2052	2052
2053	2053	WRITE8_MEMBER(rmnimbus_state::nimbus_mcu_w)
2054	2054	{
2055		m_mcu_reg080=data;
	2055	m_mcu_reg080=data;
2056	2056
2057		nimbus_bank_memory(machine());
	2057	nimbus_bank_memory(machine());
2058	2058	}
2059	2059
2060	2060	static void memory_reset(running_machine &machine)
2061	2061	{
2062	2062	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2063		state->m_mcu_reg080=0x07;
2064		nimbus_bank_memory(machine);
	2063	state->m_mcu_reg080=0x07;
	2064	nimbus_bank_memory(machine);
2065	2065	}
2066	2066
2067	2067	READ16_MEMBER(rmnimbus_state::nimbus_io_r)
2068	2068	{
2069		int pc=space.device().safe_pc();
	2069	int pc=space.device().safe_pc();
2070	2070
2071		logerror("Nimbus IOR at pc=%08X from %04X mask=%04X, data=%04X\n",pc,(offset*2)+0x30,mem_mask,m_IOPorts[offset]);
	2071	logerror("Nimbus IOR at pc=%08X from %04X mask=%04X, data=%04X\n",pc,(offset*2)+0x30,mem_mask,m_IOPorts[offset]);
2072	2072
2073		switch (offset*2)
2074		{
2075		default : return m_IOPorts[offset];
2076		}
2077		return 0;
	2073	switch (offset*2)
	2074	{
	2075	default : return m_IOPorts[offset];
	2076	}
	2077	return 0;
2078	2078	}
2079	2079
2080	2080	WRITE16_MEMBER(rmnimbus_state::nimbus_io_w)
2081	2081	{
2082		int pc=space.device().safe_pc();
	2082	int pc=space.device().safe_pc();
2083	2083
2084		logerror("Nimbus IOW at %08X write of %04X to %04X mask=%04X\n",pc,data,(offset*2)+0x30,mem_mask);
	2084	logerror("Nimbus IOW at %08X write of %04X to %04X mask=%04X\n",pc,data,(offset*2)+0x30,mem_mask);
2085	2085
2086		switch (offset*2)
2087		{
2088		default : COMBINE_DATA(&m_IOPorts[offset]); break;
2089		}
	2086	switch (offset*2)
	2087	{
	2088	default : COMBINE_DATA(&m_IOPorts[offset]); break;
	2089	}
2090	2090	}
2091	2091
2092	2092
r18355	r18356
2098	2098	static void keyboard_reset(running_machine &machine)
2099	2099	{
2100	2100	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2101		memset(state->m_keyboard.keyrows,0xFF,NIMBUS_KEYROWS);
	2101	memset(state->m_keyboard.keyrows,0xFF,NIMBUS_KEYROWS);
2102	2102
2103		// Setup timer to scan state->m_keyboard.
2104		state->m_keyboard.keyscan_timer->adjust(attotime::zero, 0, attotime::from_hz(50));
	2103	// Setup timer to scan state->m_keyboard.
	2104	state->m_keyboard.keyscan_timer->adjust(attotime::zero, 0, attotime::from_hz(50));
2105	2105	}
2106	2106
2107	2107	static void queue_scancode(running_machine &machine, UINT8 scancode)
r18355	r18356
2133	2133
2134	2134	{
2135	2135	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2136		UINT8 keyrow;
2137		UINT8 row;
2138		UINT8 bitno;
2139		UINT8 mask;
2140		static const char *const keynames[] = {
2141		"KEY0", "KEY1", "KEY2", "KEY3", "KEY4",
2142		"KEY5", "KEY6", "KEY7", "KEY8", "KEY9",
2143		"KEY10"
2144		};
	2136	UINT8 keyrow;
	2137	UINT8 row;
	2138	UINT8 bitno;
	2139	UINT8 mask;
	2140	static const char *const keynames[] = {
	2141	"KEY0", "KEY1", "KEY2", "KEY3", "KEY4",
	2142	"KEY5", "KEY6", "KEY7", "KEY8", "KEY9",
	2143	"KEY10"
	2144	};
2145	2145
2146		for(row=0;row<NIMBUS_KEYROWS;row++)
2147		{
2148		keyrow=machine.root_device().ioport(keynames[row])->read();
	2146	for(row=0;row<NIMBUS_KEYROWS;row++)
	2147	{
	2148	keyrow=machine.root_device().ioport(keynames[row])->read();
2149	2149
2150		for(mask=0x80, bitno=7;mask>0;mask=mask>>1, bitno-=1)
2151		{
2152		if(!(keyrow & mask) && (state->m_keyboard.keyrows[row] & mask))
2153		{
2154		if (LOG_KEYBOARD) logerror("keypress %02X\n",(row<<3)+bitno);
2155		queue_scancode(machine, (row<<3)+bitno);
2156		}
	2150	for(mask=0x80, bitno=7;mask>0;mask=mask>>1, bitno-=1)
	2151	{
	2152	if(!(keyrow & mask) && (state->m_keyboard.keyrows[row] & mask))
	2153	{
	2154	if (LOG_KEYBOARD) logerror("keypress %02X\n",(row<<3)+bitno);
	2155	queue_scancode(machine, (row<<3)+bitno);
	2156	}
2157	2157
2158		if((keyrow & mask) && !(state->m_keyboard.keyrows[row] & mask))
2159		{
2160		if (LOG_KEYBOARD) logerror("keyrelease %02X\n",0x80+(row<<3)+bitno);
2161		queue_scancode(machine, 0x80+(row<<3)+bitno);
2162		}
2163		}
	2158	if((keyrow & mask) && !(state->m_keyboard.keyrows[row] & mask))
	2159	{
	2160	if (LOG_KEYBOARD) logerror("keyrelease %02X\n",0x80+(row<<3)+bitno);
	2161	queue_scancode(machine, 0x80+(row<<3)+bitno);
	2162	}
	2163	}
2164	2164
2165		state->m_keyboard.keyrows[row]=keyrow;
2166		}
	2165	state->m_keyboard.keyrows[row]=keyrow;
	2166	}
2167	2167	}
2168	2168
2169	2169	TIMER_CALLBACK_MEMBER(rmnimbus_state::keyscan_callback)
2170	2170	{
2171		scan_keyboard(machine());
	2171	scan_keyboard(machine());
2172	2172	}
2173	2173
2174	2174	/*
r18355	r18356
2181	2181
2182	2182	WRITE_LINE_MEMBER(rmnimbus_state::sio_interrupt)
2183	2183	{
2184		if(LOG_SIO)
2185		logerror("SIO Interrupt state=%02X\n",state);
	2184	if(LOG_SIO)
	2185	logerror("SIO Interrupt state=%02X\n",state);
2186	2186
2187		// Don't re-trigger if already active !
2188		if(state!=m_sio_int_state)
2189		{
2190		m_sio_int_state=state;
	2187	// Don't re-trigger if already active !
	2188	if(state!=m_sio_int_state)
	2189	{
	2190	m_sio_int_state=state;
2191	2191
2192		if(state)
2193		external_int(machine(),0,EXTERNAL_INT_Z80SIO);
2194		}
	2192	if(state)
	2193	external_int(machine(),0,EXTERNAL_INT_Z80SIO);
	2194	}
2195	2195	}
2196	2196
2197	2197	#ifdef UNUSED_FUNCTION
r18355	r18356
2209	2209
2210	2210	READ16_MEMBER(rmnimbus_state::sio_serial_receive)
2211	2211	{
2212		if(offset==0)
2213		{
2214		return keyboard_queue_read(machine());
2215		}
2216		else
2217		return -1;
	2212	if(offset==0)
	2213	{
	2214	return keyboard_queue_read(machine());
	2215	}
	2216	else
	2217	return -1;
2218	2218	}
2219	2219
2220	2220	/* Floppy disk */
r18355	r18356
2222	2222	static void fdc_reset(running_machine &machine)
2223	2223	{
2224	2224	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2225		device_t *fdc = machine.device(FDC_TAG);
	2225	device_t *fdc = machine.device(FDC_TAG);
2226	2226
2227	2227	state->m_nimbus_drives.reg400=0;
2228		state->m_nimbus_drives.reg410_in=0;
2229		state->m_nimbus_drives.reg410_out=0;
2230		state->m_nimbus_drives.int_ff=0;
	2228	state->m_nimbus_drives.reg410_in=0;
	2229	state->m_nimbus_drives.reg410_out=0;
	2230	state->m_nimbus_drives.int_ff=0;
2231	2231	wd17xx_set_pause_time(fdc,FDC_PAUSE);
2232	2232	}
2233	2233
2234	2234	static void set_disk_int(running_machine &machine, int state)
2235	2235	{
2236	2236	rmnimbus_state *drvstate = machine.driver_data<rmnimbus_state>();
2237		if(LOG_DISK)
2238		logerror("nimbus_drives_intrq = %d\n",state);
	2237	if(LOG_DISK)
	2238	logerror("nimbus_drives_intrq = %d\n",state);
2239	2239
2240		if(drvstate->m_iou_reg092 & DISK_INT_ENABLE)
2241		{
2242		drvstate->m_nimbus_drives.int_ff=state;
	2240	if(drvstate->m_iou_reg092 & DISK_INT_ENABLE)
	2241	{
	2242	drvstate->m_nimbus_drives.int_ff=state;
2243	2243
2244		if(state)
2245		external_int(machine,0,EXTERNAL_INT_DISK);
2246		}
	2244	if(state)
	2245	external_int(machine,0,EXTERNAL_INT_DISK);
	2246	}
2247	2247	}
2248	2248
2249	2249	WRITE_LINE_MEMBER(rmnimbus_state::nimbus_fdc_intrq_w)
2250	2250	{
2251		set_disk_int(machine(),state);
	2251	set_disk_int(machine(),state);
2252	2252	}
2253	2253
2254	2254	WRITE_LINE_MEMBER(rmnimbus_state::nimbus_fdc_drq_w)
2255	2255	{
2256		if(LOG_DISK)
2257		logerror("nimbus_drives_drq_w(%d)\n", state);
	2256	if(LOG_DISK)
	2257	logerror("nimbus_drives_drq_w(%d)\n", state);
2258	2258
2259		if(state && FDC_DRQ_ENABLED(this))
2260		drq_callback(machine(),1);
	2259	if(state && FDC_DRQ_ENABLED(this))
	2260	drq_callback(machine(),1);
2261	2261	}
2262	2262
2263	2263	static UINT8 fdc_driveno(UINT8 drivesel)
r18355	r18356
2360	2360	WRITE8_MEMBER(rmnimbus_state::nimbus_disk_w)
2361	2361	{
2362	2362	device_t *fdc = machine().device(FDC_TAG);
2363		int pc=space.device().safe_pc();
2364		UINT8 reg400_old = m_nimbus_drives.reg400;
	2363	int pc=space.device().safe_pc();
	2364	UINT8 reg400_old = m_nimbus_drives.reg400;
2365	2365
2366		if(LOG_DISK_FDD && ((offset*2)<=0x10))
2367		logerror("Nimbus FDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
	2366	if(LOG_DISK_FDD && ((offset*2)<=0x10))
	2367	logerror("Nimbus FDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
2368	2368
2369		if((LOG_DISK_HDD) && (((offset*2)>=0x10) \|\| (offset==0)))
2370		logerror("Nimbus HDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
	2369	if((LOG_DISK_HDD) && (((offset*2)>=0x10) \|\| (offset==0)))
	2370	logerror("Nimbus HDCW at %05X write of %02X to %04X\n",pc,data,(offset*2)+0x400);
2371	2371
2372	2372	rmnimbus_state *state = machine().driver_data<rmnimbus_state>();
2373		switch(offset*2)
	2373	switch(offset*2)
2374	2374	{
2375		case 0x00 :
2376		m_nimbus_drives.reg400=data;
2377		wd17xx_set_drive(fdc,FDC_DRIVE());
2378		wd17xx_set_side(fdc, FDC_SIDE());
	2375	case 0x00 :
	2376	m_nimbus_drives.reg400=data;
	2377	wd17xx_set_drive(fdc,FDC_DRIVE());
	2378	wd17xx_set_side(fdc, FDC_SIDE());
2379	2379
2380		// Nimbus FDC is hard wired for double density
2381		//wd17xx_set_density(fdc, DEN_MFM_LO);
	2380	// Nimbus FDC is hard wired for double density
	2381	//wd17xx_set_density(fdc, DEN_MFM_LO);
2382	2382
2383		// if we enable hdc drq with a pending condition, act on it
2384		if((data & HDC_DRQ_MASK) && (~reg400_old & HDC_DRQ_MASK))
2385		hdc_drq(machine());
	2383	// if we enable hdc drq with a pending condition, act on it
	2384	if((data & HDC_DRQ_MASK) && (~reg400_old & HDC_DRQ_MASK))
	2385	hdc_drq(machine());
2386	2386
2387		break;
	2387	break;
2388	2388	case 0x08 :
2389	2389	wd17xx_command_w(fdc, space, 0, data);
2390	2390	break;
r18355	r18356
2397	2397	case 0x0E :
2398	2398	wd17xx_data_w(fdc, space, 0, data);
2399	2399	break;
2400		case 0x10 :
2401		hdc_ctrl_write(machine(),data);
2402		break;
	2400	case 0x10 :
	2401	hdc_ctrl_write(machine(),data);
	2402	break;
2403	2403
2404		case 0x18 :
2405		m_scsibus->scsi_data_w(data);
2406		hdc_post_rw(machine());
2407		break;
	2404	case 0x18 :
	2405	m_scsibus->scsi_data_w(data);
	2406	hdc_post_rw(machine());
	2407	break;
2408	2408	}
2409	2409	}
2410	2410
r18355	r18356
2412	2412	{
2413	2413	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2414	2414
2415		state->m_nimbus_drives.reg410_in=0;
2416		state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_req_r() ? HDC_REQ_MASK : 0);
2417		state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_cd_r() ? HDC_CD_MASK : 0);
2418		state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_io_r() ? HDC_IO_MASK : 0);
2419		state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_bsy_r() ? HDC_BSY_MASK : 0);
2420		state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_msg_r() ? HDC_MSG_MASK : 0);
	2415	state->m_nimbus_drives.reg410_in=0;
	2416	state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_req_r() ? HDC_REQ_MASK : 0);
	2417	state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_cd_r() ? HDC_CD_MASK : 0);
	2418	state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_io_r() ? HDC_IO_MASK : 0);
	2419	state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_bsy_r() ? HDC_BSY_MASK : 0);
	2420	state->m_nimbus_drives.reg410_in \|= (state->m_scsibus->scsi_msg_r() ? HDC_MSG_MASK : 0);
2421	2421
2422		state->m_nimbus_drives.drq_ff=0;
	2422	state->m_nimbus_drives.drq_ff=0;
2423	2423	}
2424	2424
2425	2425	static void hdc_ctrl_write(running_machine &machine, UINT8 data)
2426	2426	{
2427	2427	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2428	2428
2429		// If we enable the HDC interupt, and an interrupt is pending, go deal with it.
2430		if(((data & HDC_IRQ_MASK) && (~state->m_nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
2431		((~state->m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2432		set_disk_int(machine,1);
	2429	// If we enable the HDC interupt, and an interrupt is pending, go deal with it.
	2430	if(((data & HDC_IRQ_MASK) && (~state->m_nimbus_drives.reg410_out & HDC_IRQ_MASK)) &&
	2431	((~state->m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
	2432	set_disk_int(machine,1);
2433	2433
2434		state->m_nimbus_drives.reg410_out=data;
	2434	state->m_nimbus_drives.reg410_out=data;
2435	2435
2436		state->m_scsibus->scsi_rst_w((data & HDC_RESET_MASK) ? 0 : 1);
2437		state->m_scsibus->scsi_sel_w((data & HDC_SEL_MASK) ? 0 : 1);
	2436	state->m_scsibus->scsi_rst_w((data & HDC_RESET_MASK) ? 0 : 1);
	2437	state->m_scsibus->scsi_sel_w((data & HDC_SEL_MASK) ? 0 : 1);
2438	2438	}
2439	2439
2440	2440	static void hdc_post_rw(running_machine &machine)
2441	2441	{
2442	2442	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2443	2443
2444		if((state->m_nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
2445		state->m_scsibus->scsi_ack_w(0);
	2444	if((state->m_nimbus_drives.reg410_in & HDC_REQ_MASK)==0)
	2445	state->m_scsibus->scsi_ack_w(0);
2446	2446
2447		state->m_nimbus_drives.drq_ff=0;
	2447	state->m_nimbus_drives.drq_ff=0;
2448	2448	}
2449	2449
2450	2450	static void hdc_drq(running_machine &machine)
2451	2451	{
2452	2452	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2453		if(HDC_DRQ_ENABLED() && state->m_nimbus_drives.drq_ff)
2454		{
2455		drq_callback(machine,1);
2456		}
	2453	if(HDC_DRQ_ENABLED() && state->m_nimbus_drives.drq_ff)
	2454	{
	2455	drq_callback(machine,1);
	2456	}
2457	2457	}
2458	2458
2459	2459	WRITE_LINE_MEMBER( rmnimbus_state::nimbus_scsi_bsy_w )
r18355	r18356
2483	2483
2484	2484	void rmnimbus_state::nimbus_scsi_linechange( UINT8 mask, UINT8 state )
2485	2485	{
2486		UINT8 last = 0;
	2486	UINT8 last = 0;
2487	2487
2488		last=m_nimbus_drives.reg410_in & mask;
	2488	last=m_nimbus_drives.reg410_in & mask;
2489	2489
2490		if(state)
2491		m_nimbus_drives.reg410_in\|=mask;
2492		else
2493		m_nimbus_drives.reg410_in&=~mask;
	2490	if(state)
	2491	m_nimbus_drives.reg410_in\|=mask;
	2492	else
	2493	m_nimbus_drives.reg410_in&=~mask;
2494	2494
2495	2495
2496		if(HDC_IRQ_ENABLED() && ((~m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
2497		set_disk_int(machine(),1);
2498		else
2499		set_disk_int(machine(),0);
	2496	if(HDC_IRQ_ENABLED() && ((~m_nimbus_drives.reg410_in & HDC_INT_TRIGGER)==HDC_INT_TRIGGER))
	2497	set_disk_int(machine(),1);
	2498	else
	2499	set_disk_int(machine(),0);
2500	2500
2501		if( mask == HDC_REQ_MASK )
2502		{
2503		if (state==0)
2504		{
2505		if(((m_nimbus_drives.reg410_in & HDC_CD_MASK)==HDC_CD_MASK) && (last!=0))
2506		{
2507		m_nimbus_drives.drq_ff=1;
2508		hdc_drq(machine());
2509		}
2510		}
2511		else
	2501	if( mask == HDC_REQ_MASK )
	2502	{
	2503	if (state==0)
2512	2504	{
	2505	if(((m_nimbus_drives.reg410_in & HDC_CD_MASK)==HDC_CD_MASK) && (last!=0))
	2506	{
	2507	m_nimbus_drives.drq_ff=1;
	2508	hdc_drq(machine());
	2509	}
	2510	}
	2511	else
	2512	{
2513	2513	m_scsibus->scsi_ack_w(1);
2514	2514	}
2515		}
	2515	}
2516	2516	}
2517	2517
2518	2518	/* 8031/8051 Peripheral controler 80186 side */
r18355	r18356
2520	2520	static void pc8031_reset(running_machine &machine)
2521	2521	{
2522	2522	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2523		device_t *er59256 = machine.device(ER59256_TAG);
	2523	device_t *er59256 = machine.device(ER59256_TAG);
2524	2524
2525		logerror("peripheral controler reset\n");
	2525	logerror("peripheral controler reset\n");
2526	2526
2527		memset(&state->m_ipc_interface,0,sizeof(state->m_ipc_interface));
	2527	memset(&state->m_ipc_interface,0,sizeof(state->m_ipc_interface));
2528	2528
2529		if(!er59256_data_loaded(er59256))
2530		er59256_preload_rom(er59256,def_config,ARRAY_LENGTH(def_config));
	2529	if(!er59256_data_loaded(er59256))
	2530	er59256_preload_rom(er59256,def_config,ARRAY_LENGTH(def_config));
2531	2531	}
2532	2532
2533	2533
r18355	r18356
2535	2535	static void ipc_dumpregs()
2536	2536	{
2537	2537	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2538		logerror("in_data=%02X, in_status=%02X, out_data=%02X, out_status=%02X\n",
2539		state->m_ipc_interface.ipc_in, state->m_ipc_interface.status_in,
2540		state->m_ipc_interface.ipc_out, state->m_ipc_interface.status_out);
	2538	logerror("in_data=%02X, in_status=%02X, out_data=%02X, out_status=%02X\n",
	2539	state->m_ipc_interface.ipc_in, state->m_ipc_interface.status_in,
	2540	state->m_ipc_interface.ipc_out, state->m_ipc_interface.status_out);
2541	2541
2542	2542	}
2543	2543	#endif
r18355	r18356
2545	2545	READ8_MEMBER(rmnimbus_state::nimbus_pc8031_r)
2546	2546	{
2547	2547	int pc=space.device().safe_pc();
2548		UINT8 result;
	2548	UINT8 result;
2549	2549
2550		switch(offset*2)
2551		{
2552		case 0x00 : result=m_ipc_interface.ipc_out;
2553		m_ipc_interface.status_in &= ~IPC_IN_READ_PEND;
2554		m_ipc_interface.status_out &= ~IPC_OUT_BYTE_AVAIL;
2555		break;
	2550	switch(offset*2)
	2551	{
	2552	case 0x00 : result=m_ipc_interface.ipc_out;
	2553	m_ipc_interface.status_in &= ~IPC_IN_READ_PEND;
	2554	m_ipc_interface.status_out &= ~IPC_OUT_BYTE_AVAIL;
	2555	break;
2556	2556
2557		case 0x02 : result=m_ipc_interface.status_out;
2558		break;
	2557	case 0x02 : result=m_ipc_interface.status_out;
	2558	break;
2559	2559
2560		default : result=0; break;
2561		}
	2560	default : result=0; break;
	2561	}
2562	2562
2563		if(LOG_PC8031_186)
2564		logerror("Nimbus PCIOR %08X read of %04X returns %02X\n",pc,(offset*2)+0xC0,result);
	2563	if(LOG_PC8031_186)
	2564	logerror("Nimbus PCIOR %08X read of %04X returns %02X\n",pc,(offset*2)+0xC0,result);
2565	2565
2566		return result;
	2566	return result;
2567	2567	}
2568	2568
2569	2569	WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_w)
2570	2570	{
2571	2571	int pc=space.device().safe_pc();
2572	2572
2573		switch(offset*2)
2574		{
2575		case 0x00 : m_ipc_interface.ipc_in=data;
2576		m_ipc_interface.status_in \|= IPC_IN_BYTE_AVAIL;
2577		m_ipc_interface.status_in &= ~IPC_IN_ADDR;
2578		m_ipc_interface.status_out \|= IPC_OUT_READ_PEND;
2579		break;
	2573	switch(offset*2)
	2574	{
	2575	case 0x00 : m_ipc_interface.ipc_in=data;
	2576	m_ipc_interface.status_in \|= IPC_IN_BYTE_AVAIL;
	2577	m_ipc_interface.status_in &= ~IPC_IN_ADDR;
	2578	m_ipc_interface.status_out \|= IPC_OUT_READ_PEND;
	2579	break;
2580	2580
2581		case 0x02 : m_ipc_interface.ipc_in=data;
2582		m_ipc_interface.status_in \|= IPC_IN_BYTE_AVAIL;
2583		m_ipc_interface.status_in \|= IPC_IN_ADDR;
2584		m_ipc_interface.status_out \|= IPC_OUT_READ_PEND;
2585		break;
2586		}
	2581	case 0x02 : m_ipc_interface.ipc_in=data;
	2582	m_ipc_interface.status_in \|= IPC_IN_BYTE_AVAIL;
	2583	m_ipc_interface.status_in \|= IPC_IN_ADDR;
	2584	m_ipc_interface.status_out \|= IPC_OUT_READ_PEND;
	2585	break;
	2586	}
2587	2587
2588		if(LOG_PC8031_186)
2589		logerror("Nimbus PCIOW %08X write of %02X to %04X\n",pc,data,(offset*2)+0xC0);
	2588	if(LOG_PC8031_186)
	2589	logerror("Nimbus PCIOW %08X write of %02X to %04X\n",pc,data,(offset*2)+0xC0);
2590	2590
2591	2591	}
2592	2592
r18355	r18356
2595	2595	READ8_MEMBER(rmnimbus_state::nimbus_pc8031_iou_r)
2596	2596	{
2597	2597	int pc=space.device().safe_pc();
2598		UINT8 result = 0;
	2598	UINT8 result = 0;
2599	2599
2600		switch (offset & 0x01)
2601		{
2602		case 0x00 : result=m_ipc_interface.ipc_in;
2603		m_ipc_interface.status_out &= ~IPC_OUT_READ_PEND;
2604		m_ipc_interface.status_in &= ~IPC_IN_BYTE_AVAIL;
2605		break;
	2600	switch (offset & 0x01)
	2601	{
	2602	case 0x00 : result=m_ipc_interface.ipc_in;
	2603	m_ipc_interface.status_out &= ~IPC_OUT_READ_PEND;
	2604	m_ipc_interface.status_in &= ~IPC_IN_BYTE_AVAIL;
	2605	break;
2606	2606
2607		case 0x01 : result=m_ipc_interface.status_in;
2608		break;
2609		}
	2607	case 0x01 : result=m_ipc_interface.status_in;
	2608	break;
	2609	}
2610	2610
2611		if(((offset==2) \|\| (offset==3)) && (m_iou_reg092 & PC8031_INT_ENABLE))
2612		external_int(machine(),0,EXTERNAL_INT_PC8031_8C);
	2611	if(((offset==2) \|\| (offset==3)) && (m_iou_reg092 & PC8031_INT_ENABLE))
	2612	external_int(machine(),0,EXTERNAL_INT_PC8031_8C);
2613	2613
2614		if(LOG_PC8031)
2615		logerror("8031: PCIOR %04X read of %04X returns %02X\n",pc,offset,result);
	2614	if(LOG_PC8031)
	2615	logerror("8031: PCIOR %04X read of %04X returns %02X\n",pc,offset,result);
2616	2616
2617		return result;
	2617	return result;
2618	2618	}
2619	2619
2620	2620	WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_iou_w)
2621	2621	{
2622	2622	int pc=space.device().safe_pc();
2623	2623
2624		if(LOG_PC8031)
2625		logerror("8031 PCIOW %04X write of %02X to %04X\n",pc,data,offset);
	2624	if(LOG_PC8031)
	2625	logerror("8031 PCIOW %04X write of %02X to %04X\n",pc,data,offset);
2626	2626
2627		switch(offset & 0x03)
2628		{
2629		case 0x00 : m_ipc_interface.ipc_out=data;
2630		m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
2631		m_ipc_interface.status_out &= ~IPC_OUT_ADDR;
2632		m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
2633		break;
	2627	switch(offset & 0x03)
	2628	{
	2629	case 0x00 : m_ipc_interface.ipc_out=data;
	2630	m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
	2631	m_ipc_interface.status_out &= ~IPC_OUT_ADDR;
	2632	m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
	2633	break;
2634	2634
2635		case 0x01 : m_ipc_interface.ipc_out=data;
2636		m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
2637		m_ipc_interface.status_out \|= IPC_OUT_ADDR;
2638		m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
2639		break;
	2635	case 0x01 : m_ipc_interface.ipc_out=data;
	2636	m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
	2637	m_ipc_interface.status_out \|= IPC_OUT_ADDR;
	2638	m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
	2639	break;
2640	2640
2641		case 0x02 : m_ipc_interface.ipc_out=data;
2642		m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
2643		m_ipc_interface.status_out &= ~IPC_OUT_ADDR;
2644		m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
2645		if(m_iou_reg092 & PC8031_INT_ENABLE)
2646		external_int(machine(),0,EXTERNAL_INT_PC8031_8F);
2647		break;
	2641	case 0x02 : m_ipc_interface.ipc_out=data;
	2642	m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
	2643	m_ipc_interface.status_out &= ~IPC_OUT_ADDR;
	2644	m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
	2645	if(m_iou_reg092 & PC8031_INT_ENABLE)
	2646	external_int(machine(),0,EXTERNAL_INT_PC8031_8F);
	2647	break;
2648	2648
2649		case 0x03 : m_ipc_interface.ipc_out=data;
2650		//m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
2651		m_ipc_interface.status_out \|= IPC_OUT_ADDR;
2652		m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
2653		if(m_iou_reg092 & PC8031_INT_ENABLE)
2654		external_int(machine(),0,EXTERNAL_INT_PC8031_8E);
2655		break;
2656		}
	2649	case 0x03 : m_ipc_interface.ipc_out=data;
	2650	//m_ipc_interface.status_out \|= IPC_OUT_BYTE_AVAIL;
	2651	m_ipc_interface.status_out \|= IPC_OUT_ADDR;
	2652	m_ipc_interface.status_in \|= IPC_IN_READ_PEND;
	2653	if(m_iou_reg092 & PC8031_INT_ENABLE)
	2654	external_int(machine(),0,EXTERNAL_INT_PC8031_8E);
	2655	break;
	2656	}
2657	2657	}
2658	2658
2659	2659	READ8_MEMBER(rmnimbus_state::nimbus_pc8031_port_r)
2660	2660	{
2661	2661	device_t *er59256 = machine().device(ER59256_TAG);
2662		int pc=space.device().safe_pc();
2663		UINT8 result = 0;
	2662	int pc=space.device().safe_pc();
	2663	UINT8 result = 0;
2664	2664
2665		if(LOG_PC8031_PORT)
2666		logerror("8031: PCPORTR %04X read of %04X returns %02X\n",pc,offset,result);
	2665	if(LOG_PC8031_PORT)
	2666	logerror("8031: PCPORTR %04X read of %04X returns %02X\n",pc,offset,result);
2667	2667
2668		switch(offset)
2669		{
2670		case 0x01 : result=er59256_get_iobits(er59256);
2671		}
	2668	switch(offset)
	2669	{
	2670	case 0x01 : result=er59256_get_iobits(er59256);
	2671	}
2672	2672
2673		return result;
	2673	return result;
2674	2674	}
2675	2675
2676	2676	WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_port_w)
2677	2677	{
2678	2678	device_t *er59256 = machine().device(ER59256_TAG);
2679		int pc=space.device().safe_pc();
	2679	int pc=space.device().safe_pc();
2680	2680
2681		switch (offset)
2682		{
2683		case 0x01 : er59256_set_iobits(er59256,(data&0x0F));
2684		}
	2681	switch (offset)
	2682	{
	2683	case 0x01 : er59256_set_iobits(er59256,(data&0x0F));
	2684	}
2685	2685
2686		if(LOG_PC8031_PORT)
2687		logerror("8031 PCPORTW %04X write of %02X to %04X\n",pc,data,offset);
	2686	if(LOG_PC8031_PORT)
	2687	logerror("8031 PCPORTW %04X write of %02X to %04X\n",pc,data,offset);
2688	2688	}
2689	2689
2690	2690
r18355	r18356
2693	2693	READ8_MEMBER(rmnimbus_state::nimbus_iou_r)
2694	2694	{
2695	2695	int pc=space.device().safe_pc();
2696		UINT8 result=0;
	2696	UINT8 result=0;
2697	2697
2698		if(offset==0)
2699		{
2700		result=m_iou_reg092;
2701		}
	2698	if(offset==0)
	2699	{
	2700	result=m_iou_reg092;
	2701	}
2702	2702
2703		if(LOG_IOU)
2704		logerror("Nimbus IOUR %08X read of %04X returns %02X\n",pc,(offset*2)+0x92,result);
	2703	if(LOG_IOU)
	2704	logerror("Nimbus IOUR %08X read of %04X returns %02X\n",pc,(offset*2)+0x92,result);
2705	2705
2706		return result;
	2706	return result;
2707	2707	}
2708	2708
2709	2709	WRITE8_MEMBER(rmnimbus_state::nimbus_iou_w)
2710	2710	{
2711	2711	int pc=space.device().safe_pc();
2712		device_t *msm5205 = machine().device(MSM5205_TAG);
	2712	device_t *msm5205 = machine().device(MSM5205_TAG);
2713	2713
2714		if(LOG_IOU)
2715		logerror("Nimbus IOUW %08X write of %02X to %04X\n",pc,data,(offset*2)+0x92);
	2714	if(LOG_IOU)
	2715	logerror("Nimbus IOUW %08X write of %02X to %04X\n",pc,data,(offset*2)+0x92);
2716	2716
2717		if(offset==0)
2718		{
2719		m_iou_reg092=data;
2720		msm5205_reset_w(msm5205, (data & MSM5205_INT_ENABLE) ? 0 : 1);
2721		}
	2717	if(offset==0)
	2718	{
	2719	m_iou_reg092=data;
	2720	msm5205_reset_w(msm5205, (data & MSM5205_INT_ENABLE) ? 0 : 1);
	2721	}
2722	2722	}
2723	2723
2724	2724	static void iou_reset(running_machine &machine)
2725	2725	{
2726	2726	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2727		state->m_iou_reg092=0x00;
	2727	state->m_iou_reg092=0x00;
2728	2728	}
2729	2729
2730	2730	/*
r18355	r18356
2744	2744	static void rmni_sound_reset(running_machine &machine)
2745	2745	{
2746	2746	rmnimbus_state *state = machine.driver_data<rmnimbus_state>();
2747		//device_t *ay8910 = machine.device(AY8910_TAG);
2748		device_t *msm5205 = machine.device(MSM5205_TAG);
	2747	//device_t *ay8910 = machine.device(AY8910_TAG);
	2748	device_t *msm5205 = machine.device(MSM5205_TAG);
2749	2749
2750		//ay8910_reset_ym(ay8910);
2751		msm5205_reset_w(msm5205, 1);
	2750	//ay8910_reset_ym(ay8910);
	2751	msm5205_reset_w(msm5205, 1);
2752	2752
2753		state->m_last_playmode=MSM5205_S48_4B;
2754		msm5205_playmode_w(msm5205,state->m_last_playmode);
	2753	state->m_last_playmode=MSM5205_S48_4B;
	2754	msm5205_playmode_w(msm5205,state->m_last_playmode);
2755	2755
2756		state->m_ay8910_a=0;
	2756	state->m_ay8910_a=0;
2757	2757	}
2758	2758
2759	2759	READ8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_r)
2760	2760	{
2761	2761	device_t *ay8910 = machine().device(AY8910_TAG);
2762		UINT8 result=0;
	2762	UINT8 result=0;
2763	2763
2764		if ((offset*2)==0)
2765		result=ay8910_r(ay8910,space, 0);
	2764	if ((offset*2)==0)
	2765	result=ay8910_r(ay8910,space, 0);
2766	2766
2767		return result;
	2767	return result;
2768	2768	}
2769	2769
2770	2770	WRITE8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_w)
r18355	r18356
2772	2772	int pc=space.device().safe_pc();
2773	2773	device_t *ay8910 = machine().device(AY8910_TAG);
2774	2774
2775		if(LOG_SOUND)
2776		logerror("Nimbus SoundW %05X write of %02X to %04X\n",pc,data,(offset*2)+0xE0);
	2775	if(LOG_SOUND)
	2776	logerror("Nimbus SoundW %05X write of %02X to %04X\n",pc,data,(offset*2)+0xE0);
2777	2777
2778		switch (offset*2)
2779		{
2780		case 0x00 : ay8910_data_address_w(ay8910, space, 1, data); break;
2781		case 0x02 : ay8910_data_address_w(ay8910, space, 0, data); break;
2782		}
	2778	switch (offset*2)
	2779	{
	2780	case 0x00 : ay8910_data_address_w(ay8910, space, 1, data); break;
	2781	case 0x02 : ay8910_data_address_w(ay8910, space, 0, data); break;
	2782	}
2783	2783
2784	2784	}
2785	2785
2786	2786	WRITE8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_porta_w)
2787	2787	{
2788		device_t *msm5205 = machine().device(MSM5205_TAG);
	2788	device_t *msm5205 = machine().device(MSM5205_TAG);
2789	2789
2790		msm5205_data_w(msm5205, data);
	2790	msm5205_data_w(msm5205, data);
2791	2791
2792		// Mouse code needs a copy of this.
2793		m_ay8910_a=data;
	2792	// Mouse code needs a copy of this.
	2793	m_ay8910_a=data;
2794	2794	}
2795	2795
2796	2796	WRITE8_MEMBER(rmnimbus_state::nimbus_sound_ay8910_portb_w)
2797	2797	{
2798		device_t *msm5205 = machine().device(MSM5205_TAG);
	2798	device_t *msm5205 = machine().device(MSM5205_TAG);
2799	2799
2800		if((data & 0x07)!=m_last_playmode)
2801		{
2802		m_last_playmode=(data & 0x07);
2803		msm5205_playmode_w(msm5205, m_last_playmode);
2804		}
	2800	if((data & 0x07)!=m_last_playmode)
	2801	{
	2802	m_last_playmode=(data & 0x07);
	2803	msm5205_playmode_w(msm5205, m_last_playmode);
	2804	}
2805	2805	}
2806	2806
2807	2807	void nimbus_msm5205_vck(device_t *device)
2808	2808	{
2809	2809	rmnimbus_state *state = device->machine().driver_data<rmnimbus_state>();
2810		if(state->m_iou_reg092 & MSM5205_INT_ENABLE)
2811		external_int(device->machine(),0,EXTERNAL_INT_MSM5205);
	2810	if(state->m_iou_reg092 & MSM5205_INT_ENABLE)
	2811	external_int(device->machine(),0,EXTERNAL_INT_MSM5205);
2812	2812	}
2813	2813
2814	2814	static const int MOUSE_XYA[3][4] = { { 0, 0, 0, 0 }, { 1, 1, 0, 0 }, { 0, 1, 1, 0 } };
r18355	r18356
2819	2819	static void mouse_js_reset(running_machine &machine)
2820	2820	{
2821	2821	rmnimbus_state *drvstate = machine.driver_data<rmnimbus_state>();
2822		mouse_joy_state *state = &drvstate->m_nimbus_mouse;
	2822	mouse_joy_state *state = &drvstate->m_nimbus_mouse;
2823	2823
2824		state->m_mouse_px=0;
2825		state->m_mouse_py=0;
2826		state->m_mouse_x=128;
2827		state->m_mouse_y=128;
2828		state->m_mouse_pc=0;
2829		state->m_mouse_pcx=0;
2830		state->m_mouse_pcy=0;
2831		state->m_intstate_x=0;
2832		state->m_intstate_y=0;
2833		state->m_reg0a4=0xC0;
	2824	state->m_mouse_px=0;
	2825	state->m_mouse_py=0;
	2826	state->m_mouse_x=128;
	2827	state->m_mouse_y=128;
	2828	state->m_mouse_pc=0;
	2829	state->m_mouse_pcx=0;
	2830	state->m_mouse_pcy=0;
	2831	state->m_intstate_x=0;
	2832	state->m_intstate_y=0;
	2833	state->m_reg0a4=0xC0;
2834	2834
2835		// Setup timer to poll the mouse
2836		state->m_mouse_timer->adjust(attotime::zero, 0, attotime::from_hz(1000));
	2835	// Setup timer to poll the mouse
	2836	state->m_mouse_timer->adjust(attotime::zero, 0, attotime::from_hz(1000));
2837	2837	}
2838	2838
2839	2839	TIMER_CALLBACK_MEMBER(rmnimbus_state::mouse_callback)
2840	2840	{
2841		UINT8 x = 0;
2842		UINT8 y = 0;
	2841	UINT8 x = 0;
	2842	UINT8 y = 0;
2843	2843	// int pc=machine().device(MAINCPU_TAG)->safe_pc();
2844	2844
2845		UINT8 intstate_x;
2846		UINT8 intstate_y;
2847		int xint;
2848		int yint;
	2845	UINT8 intstate_x;
	2846	UINT8 intstate_y;
	2847	int xint;
	2848	int yint;
2849	2849
2850		mouse_joy_state *state = &m_nimbus_mouse;
	2850	mouse_joy_state *state = &m_nimbus_mouse;
2851	2851
2852	2852
2853	2853	state->m_reg0a4 = machine().root_device().ioport(MOUSE_BUTTON_TAG)->read() \| 0xC0;
2854	2854	x = machine().root_device().ioport(MOUSEX_TAG)->read();
2855		y = machine().root_device().ioport(MOUSEY_TAG)->read();
	2855	y = machine().root_device().ioport(MOUSEY_TAG)->read();
2856	2856
2857		UINT8 mxa;
2858		UINT8 mxb;
2859		UINT8 mya;
2860		UINT8 myb;
	2857	UINT8 mxa;
	2858	UINT8 mxb;
	2859	UINT8 mya;
	2860	UINT8 myb;
2861	2861
2862		//logerror("poll_mouse()\n");
	2862	//logerror("poll_mouse()\n");
2863	2863
2864	2864	if (x == state->m_mouse_x)
2865	2865	{
r18355	r18356
2887	2887	state->m_mouse_py = MOUSE_PHASE_NEGATIVE;
2888	2888	}
2889	2889
2890		switch (state->m_mouse_px)
2891		{
2892		case MOUSE_PHASE_STATIC : break;
2893		case MOUSE_PHASE_POSITIVE : state->m_mouse_pcx++; break;
2894		case MOUSE_PHASE_NEGATIVE : state->m_mouse_pcx--; break;
2895		}
2896		state->m_mouse_pcx &= 0x03;
	2890	switch (state->m_mouse_px)
	2891	{
	2892	case MOUSE_PHASE_STATIC : break;
	2893	case MOUSE_PHASE_POSITIVE : state->m_mouse_pcx++; break;
	2894	case MOUSE_PHASE_NEGATIVE : state->m_mouse_pcx--; break;
	2895	}
	2896	state->m_mouse_pcx &= 0x03;
2897	2897
2898		switch (state->m_mouse_py)
2899		{
2900		case MOUSE_PHASE_STATIC : break;
2901		case MOUSE_PHASE_POSITIVE : state->m_mouse_pcy++; break;
2902		case MOUSE_PHASE_NEGATIVE : state->m_mouse_pcy--; break;
2903		}
2904		state->m_mouse_pcy &= 0x03;
	2898	switch (state->m_mouse_py)
	2899	{
	2900	case MOUSE_PHASE_STATIC : break;
	2901	case MOUSE_PHASE_POSITIVE : state->m_mouse_pcy++; break;
	2902	case MOUSE_PHASE_NEGATIVE : state->m_mouse_pcy--; break;
	2903	}
	2904	state->m_mouse_pcy &= 0x03;
2905	2905
2906	2906	// mxb = MOUSE_XYB[state->m_mouse_px][state->m_mouse_pcx]; // XB
2907	2907	// mxa = MOUSE_XYA[state->m_mouse_px][state->m_mouse_pcx]; // XA
r18355	r18356
2913	2913	mya = MOUSE_XYA[1][state->m_mouse_pcy]; // YA
2914	2914	myb = MOUSE_XYB[1][state->m_mouse_pcy]; // YB
2915	2915
2916		if ((state->m_mouse_py!=MOUSE_PHASE_STATIC) \|\| (state->m_mouse_px!=MOUSE_PHASE_STATIC))
2917		{
	2916	if ((state->m_mouse_py!=MOUSE_PHASE_STATIC) \|\| (state->m_mouse_px!=MOUSE_PHASE_STATIC))
	2917	{
2918	2918	// logerror("mouse_px=%02X, mouse_py=%02X, mouse_pcx=%02X, mouse_pcy=%02X\n",
2919	2919	// state->m_mouse_px,state->m_mouse_py,state->m_mouse_pcx,state->m_mouse_pcy);
2920	2920
2921	2921	// logerror("mxb=%02x, mxa=%02X (mxb ^ mxa)=%02X, (ay8910_a & 0xC0)=%02X, (mxb ^ mxa) ^ ((ay8910_a & 0x80) >> 7)=%02X\n",
2922	2922	// mxb,mxa, (mxb ^ mxa) , (state->m_ay8910_a & 0xC0), (mxb ^ mxa) ^ ((state->m_ay8910_a & 0x40) >> 6));
2923		}
	2923	}
2924	2924
2925		intstate_x = (mxb ^ mxa) ^ ((m_ay8910_a & 0x40) >> 6);
2926		intstate_y = (myb ^ mya) ^ ((m_ay8910_a & 0x80) >> 7);
	2925	intstate_x = (mxb ^ mxa) ^ ((m_ay8910_a & 0x40) >> 6);
	2926	intstate_y = (myb ^ mya) ^ ((m_ay8910_a & 0x80) >> 7);
2927	2927
2928		if (MOUSE_INT_ENABLED(this))
2929		{
2930		if ((intstate_x==1) && (state->m_intstate_x==0))
	2928	if (MOUSE_INT_ENABLED(this))
	2929	{
	2930	if ((intstate_x==1) && (state->m_intstate_x==0))
2931	2931	// if (intstate_x!=state->m_intstate_x)
2932		{
	2932	{
2933	2933
2934		xint=mxa ? EXTERNAL_INT_MOUSE_XR : EXTERNAL_INT_MOUSE_XL;
	2934	xint=mxa ? EXTERNAL_INT_MOUSE_XR : EXTERNAL_INT_MOUSE_XL;
2935	2935
2936		external_int(machine(),0,xint);
	2936	external_int(machine(),0,xint);
2937	2937
2938	2938	// logerror("Xint:%02X, mxb=%02X\n",xint,mxb);
2939		}
	2939	}
2940	2940
2941		if ((intstate_y==1) && (state->m_intstate_y==0))
	2941	if ((intstate_y==1) && (state->m_intstate_y==0))
2942	2942	// if (intstate_y!=state->m_intstate_y)
2943		{
2944		yint=myb ? EXTERNAL_INT_MOUSE_YU : EXTERNAL_INT_MOUSE_YD;
	2943	{
	2944	yint=myb ? EXTERNAL_INT_MOUSE_YU : EXTERNAL_INT_MOUSE_YD;
2945	2945
2946		external_int(machine(),0,yint);
	2946	external_int(machine(),0,yint);
2947	2947	// logerror("Yint:%02X, myb=%02X\n",yint,myb);
2948		}
2949		}
2950		else
2951		{
2952		state->m_reg0a4 &= 0xF0;
2953		state->m_reg0a4 \|= ( mxb & 0x01) << 3; // XB
2954		state->m_reg0a4 \|= (~mxb & 0x01) << 2; // XA
2955		state->m_reg0a4 \|= (~myb & 0x01) << 1; // YA
2956		state->m_reg0a4 \|= ( myb & 0x01) << 0; // YB
2957		}
	2948	}
	2949	}
	2950	else
	2951	{
	2952	state->m_reg0a4 &= 0xF0;
	2953	state->m_reg0a4 \|= ( mxb & 0x01) << 3; // XB
	2954	state->m_reg0a4 \|= (~mxb & 0x01) << 2; // XA
	2955	state->m_reg0a4 \|= (~myb & 0x01) << 1; // YA
	2956	state->m_reg0a4 \|= ( myb & 0x01) << 0; // YB
	2957	}
2958	2958
2959		state->m_mouse_x = x;
2960		state->m_mouse_y = y;
	2959	state->m_mouse_x = x;
	2960	state->m_mouse_y = y;
2961	2961
2962		if ((state->m_mouse_py!=MOUSE_PHASE_STATIC) \|\| (state->m_mouse_px!=MOUSE_PHASE_STATIC))
2963		{
	2962	if ((state->m_mouse_py!=MOUSE_PHASE_STATIC) \|\| (state->m_mouse_px!=MOUSE_PHASE_STATIC))
	2963	{
2964	2964	// logerror("pc=%05X, reg0a4=%02X, reg092=%02X, ay_a=%02X, x=%02X, y=%02X, px=%02X, py=%02X, intstate_x=%02X, intstate_y=%02X\n",
2965	2965	// pc,state->m_reg0a4,state->m_iou_reg092,state->m_ay8910_a,state->m_mouse_x,state->m_mouse_y,state->m_mouse_px,state->m_mouse_py,intstate_x,intstate_y);
2966		}
	2966	}
2967	2967
2968		state->m_intstate_x=intstate_x;
2969		state->m_intstate_y=intstate_y;
	2968	state->m_intstate_x=intstate_x;
	2969	state->m_intstate_y=intstate_y;
2970	2970	}
2971	2971
2972	2972	READ8_MEMBER(rmnimbus_state::nimbus_mouse_js_r)
r18355	r18356
3036	3036
3037	3037	const via6522_interface nimbus_via =
3038	3038	{
3039		DEVCB_NULL, //via_user_read_porta,
	3039	DEVCB_NULL, //via_user_read_porta,
3040	3040	DEVCB_DRIVER_MEMBER(rmnimbus_state,nimbus_via_read_portb),
3041		DEVCB_NULL, //via_user_read_ca1,
3042		DEVCB_NULL, //via_user_read_cb1,
3043		DEVCB_NULL, //via_user_read_ca2,
3044		DEVCB_NULL, //via_user_read_cb2,
	3041	DEVCB_NULL, //via_user_read_ca1,
	3042	DEVCB_NULL, //via_user_read_cb1,
	3043	DEVCB_NULL, //via_user_read_ca2,
	3044	DEVCB_NULL, //via_user_read_cb2,
3045	3045	DEVCB_DEVICE_MEMBER(CENTRONICS_TAG, centronics_device, write),
3046	3046	DEVCB_DRIVER_MEMBER(rmnimbus_state,nimbus_via_write_portb),
3047	3047	DEVCB_NULL, //via_user_write_ca1
3048	3048	DEVCB_NULL, //via_user_write_cb1
3049	3049	DEVCB_DEVICE_LINE_MEMBER(CENTRONICS_TAG, centronics_device, strobe_w),
3050		DEVCB_NULL, //via_user_write_cb2,
	3050	DEVCB_NULL, //via_user_write_cb2,
3051	3051	DEVCB_DRIVER_LINE_MEMBER(rmnimbus_state,nimbus_via_irq_w)
3052	3052	};
3053	3053
r18355	r18356
3056	3056	via6522_device *via_1 = machine().device<via6522_device>(VIA_TAG);
3057	3057	via_1->write_ca1(!state); /* ack seems to be inverted? */
3058	3058	}
3059

trunk/src/mess/includes/rmnimbus.h
r18355	r18356
14	14	#define MAINCPU_TAG "maincpu"
15	15	#define IOCPU_TAG "iocpu"
16	16
17		#define num_ioports 0x80
18		#define NIMBUS_KEYROWS 11
19		#define KEYBOARD_QUEUE_SIZE 32
	17	#define num_ioports 0x80
	18	#define NIMBUS_KEYROWS 11
	19	#define KEYBOARD_QUEUE_SIZE 32
20	20
21	21	#define SCREEN_WIDTH_PIXELS 640
22	22	#define SCREEN_HEIGHT_LINES 250
23	23	#define SCREEN_NO_COLOURS 16
24	24
25		#define NO_VIDREGS (0x30/2)
	25	#define NO_VIDREGS (0x30/2)
26	26
27	27	/* Nimbus sub-bios structures for debugging */
28	28
r18355	r18356
66	66	/* 80186 internal stuff */
67	67	struct mem_state
68	68	{
69		UINT16 lower;
70		UINT16 upper;
71		UINT16 middle;
72		UINT16 middle_size;
73		UINT16 peripheral;
	69	UINT16 lower;
	70	UINT16 upper;
	71	UINT16 middle;
	72	UINT16 middle_size;
	73	UINT16 peripheral;
74	74	};
75	75
76	76	struct timer_state
77	77	{
78		UINT16 control;
79		UINT16 maxA;
80		UINT16 maxB;
81		UINT16 count;
	78	UINT16 control;
	79	UINT16 maxA;
	80	UINT16 maxB;
	81	UINT16 count;
82	82	emu_timer *int_timer;
83	83	emu_timer *time_timer;
84		UINT8 time_timer_active;
85		attotime last_time;
	84	UINT8 time_timer_active;
	85	attotime last_time;
86	86	};
87	87
88	88	struct dma_state
89	89	{
90		UINT32 source;
91		UINT32 dest;
92		UINT16 count;
93		UINT16 control;
94		UINT8 finished;
	90	UINT32 source;
	91	UINT32 dest;
	92	UINT16 count;
	93	UINT16 control;
	94	UINT8 finished;
95	95	emu_timer *finish_timer;
96	96	};
97	97
98	98	struct intr_state
99	99	{
100		UINT8 pending;
101		UINT16 ack_mask;
102		UINT16 priority_mask;
103		UINT16 in_service;
104		UINT16 request;
105		UINT16 status;
106		UINT16 poll_status;
107		UINT16 timer;
108		UINT16 dma[2];
109		UINT16 ext[4];
	100	UINT8 pending;
	101	UINT16 ack_mask;
	102	UINT16 priority_mask;
	103	UINT16 in_service;
	104	UINT16 request;
	105	UINT16 status;
	106	UINT16 poll_status;
	107	UINT16 timer;
	108	UINT16 dma[2];
	109	UINT16 ext[4];
110	110	UINT16 ext_vector[2]; // external vectors, when in cascade mode
111	111	};
112	112
113	113	struct i186_state
114	114	{
115		struct timer_state timer[3];
116		struct dma_state dma[2];
117		struct intr_state intr;
118		struct mem_state mem;
	115	struct timer_state timer[3];
	116	struct dma_state dma[2];
	117	struct intr_state intr;
	118	struct mem_state mem;
119	119	};
120	120
121	121	struct keyboard_t
r18355	r18356
247	247
248	248	/* Z80 SIO for keyboard */
249	249
250		#define Z80SIO_TAG "z80sio"
	250	#define Z80SIO_TAG "z80sio"
251	251
252	252	extern const z80sio_interface nimbus_sio_intf;
253	253
254	254	/* Floppy/Fixed drive interface */
255	255
256	256	#define FDC_TAG "wd2793"
257		#define FDC_PAUSE 10000
	257	#define FDC_PAUSE 10000
258	258
259	259	extern const wd17xx_interface nimbus_wd17xx_interface;
260	260
r18355	r18356
363	363
364	364	/* Paralell / User port BBC compatible ! */
365	365
366		#define VIA_TAG "via6522"
367		#define CENTRONICS_TAG "centronics"
	366	#define VIA_TAG "via6522"
	367	#define CENTRONICS_TAG "centronics"
368	368
369		#define VIA_INT 0x03
	369	#define VIA_INT 0x03
370	370
371	371	extern const via6522_interface nimbus_via;
372	372
r18355	r18356
392	392	public:
393	393	rmnimbus_state(const machine_config &mconfig, device_type type, const char *tag)
394	394	: driver_device(mconfig, type, tag),
395		m_scsibus(*this, SCSIBUS_TAG ":host")
	395	m_scsibus(*this, SCSIBUS_TAG ":host")
396	396	{
397	397	}
398	398

trunk/src/mess/drivers/rmnimbus.c
r18355	r18356
29	29	{
30	30	/normal brightness /
31	31	{ 0x00,0x00,0x00 }, /* black */
32		{ 0x00,0x00,0x80 }, /* blue */
33		{ 0x80,0x00,0x00 }, /* red */
34		{ 0x80,0x00,0x80 }, /* magenta */
35		{ 0x00,0x80,0x00 }, /* green */
36		{ 0x00,0x80,0x80 }, /* cyan */
37		{ 0x80,0x80,0x00 }, /* yellow */
38		{ 0x80,0x80,0x80 }, /* light grey */
	32	{ 0x00,0x00,0x80 }, /* blue */
	33	{ 0x80,0x00,0x00 }, /* red */
	34	{ 0x80,0x00,0x80 }, /* magenta */
	35	{ 0x00,0x80,0x00 }, /* green */
	36	{ 0x00,0x80,0x80 }, /* cyan */
	37	{ 0x80,0x80,0x00 }, /* yellow */
	38	{ 0x80,0x80,0x80 }, /* light grey */
39	39
40	40	/enhanced brightness/
41		{ 0x40,0x40,0x40 }, /* dark grey */
42		{ 0x00,0x00,0xFF }, /* light blue */
43		{ 0xFF,0x00,0x00 }, /* light red */
44		{ 0xFF,0x00,0xFF }, /* light magenta */
45		{ 0x00,0xFF,0x00 }, /* light green */
46		{ 0x00,0xFF,0xFF }, /* light cyan */
47		{ 0xFF,0xFF,0x00 }, /* yellow */
48		{ 0xFF,0xFF,0xFF } /* white */
	41	{ 0x40,0x40,0x40 }, /* dark grey */
	42	{ 0x00,0x00,0xFF }, /* light blue */
	43	{ 0xFF,0x00,0x00 }, /* light red */
	44	{ 0xFF,0x00,0xFF }, /* light magenta */
	45	{ 0x00,0xFF,0x00 }, /* light green */
	46	{ 0x00,0xFF,0xFF }, /* light cyan */
	47	{ 0xFF,0xFF,0x00 }, /* yellow */
	48	{ 0xFF,0xFF,0xFF } /* white */
49	49	};
50	50
51	51	static const floppy_interface nimbus_floppy_interface =
r18355	r18356
68	68	{
69	69	AY8910_LEGACY_OUTPUT,
70	70	AY8910_DEFAULT_LOADS,
71		DEVCB_NULL, /* portA read */
72		DEVCB_NULL, /* portB read */
	71	DEVCB_NULL, /* portA read */
	72	DEVCB_NULL, /* portB read */
73	73	DEVCB_DRIVER_MEMBER(rmnimbus_state, nimbus_sound_ay8910_porta_w), /* portA write */
74	74	DEVCB_DRIVER_MEMBER(rmnimbus_state, nimbus_sound_ay8910_portb_w) /* portB write */
75	75	};
76	76
77	77	static const msm5205_interface msm5205_config =
78	78	{
79		nimbus_msm5205_vck, /* VCK function */
80		MSM5205_S48_4B /* 8 kHz */
	79	nimbus_msm5205_vck, /* VCK function */
	80	MSM5205_S48_4B /* 8 kHz */
81	81	};
82	82
83	83	//-------------------------------------------------
r18355	r18356
105	105	};
106	106
107	107	static ADDRESS_MAP_START(nimbus_mem, AS_PROGRAM, 16, rmnimbus_state )
108		AM_RANGE( 0x00000, 0x1FFFF ) AM_RAMBANK(RAM_BANK00_TAG)
109		AM_RANGE( 0x20000, 0x3FFFF ) AM_RAMBANK(RAM_BANK01_TAG)
110		AM_RANGE( 0x40000, 0x5FFFF ) AM_RAMBANK(RAM_BANK02_TAG)
111		AM_RANGE( 0x60000, 0x7FFFF ) AM_RAMBANK(RAM_BANK03_TAG)
112		AM_RANGE( 0x80000, 0x9FFFF ) AM_RAMBANK(RAM_BANK04_TAG)
113		AM_RANGE( 0xA0000, 0xBFFFF ) AM_RAMBANK(RAM_BANK05_TAG)
114		AM_RANGE( 0xC0000, 0xDFFFF ) AM_RAMBANK(RAM_BANK06_TAG)
115		AM_RANGE( 0xE0000, 0xEFFFF ) AM_RAMBANK(RAM_BANK07_TAG)
116		AM_RANGE( 0xF0000, 0xFFFFF ) AM_ROM AM_REGION(MAINCPU_TAG, 0x0f0000)
	108	AM_RANGE( 0x00000, 0x1FFFF ) AM_RAMBANK(RAM_BANK00_TAG)
	109	AM_RANGE( 0x20000, 0x3FFFF ) AM_RAMBANK(RAM_BANK01_TAG)
	110	AM_RANGE( 0x40000, 0x5FFFF ) AM_RAMBANK(RAM_BANK02_TAG)
	111	AM_RANGE( 0x60000, 0x7FFFF ) AM_RAMBANK(RAM_BANK03_TAG)
	112	AM_RANGE( 0x80000, 0x9FFFF ) AM_RAMBANK(RAM_BANK04_TAG)
	113	AM_RANGE( 0xA0000, 0xBFFFF ) AM_RAMBANK(RAM_BANK05_TAG)
	114	AM_RANGE( 0xC0000, 0xDFFFF ) AM_RAMBANK(RAM_BANK06_TAG)
	115	AM_RANGE( 0xE0000, 0xEFFFF ) AM_RAMBANK(RAM_BANK07_TAG)
	116	AM_RANGE( 0xF0000, 0xFFFFF ) AM_ROM AM_REGION(MAINCPU_TAG, 0x0f0000)
117	117	ADDRESS_MAP_END
118	118
119	119	static ADDRESS_MAP_START(nimbus_io, AS_IO, 16, rmnimbus_state )
120		AM_RANGE( 0x0000, 0x0031) AM_READWRITE(nimbus_video_io_r, nimbus_video_io_w)
121		AM_RANGE( 0x0032, 0x007f) AM_READWRITE(nimbus_io_r, nimbus_io_w)
122		AM_RANGE( 0x0080, 0x0081) AM_READWRITE8(nimbus_mcu_r, nimbus_mcu_w, 0x00FF)
123		AM_RANGE( 0x0092, 0x0093) AM_READWRITE8(nimbus_iou_r, nimbus_iou_w, 0x00FF)
124		AM_RANGE( 0x00A4, 0x00A5) AM_READWRITE8(nimbus_mouse_js_r, nimbus_mouse_js_w, 0x00FF)
125		AM_RANGE( 0X00c0, 0X00cf) AM_READWRITE8(nimbus_pc8031_r, nimbus_pc8031_w, 0x00FF)
126		AM_RANGE( 0X00e0, 0X00ef) AM_READWRITE8(nimbus_sound_ay8910_r, nimbus_sound_ay8910_w, 0x00FF)
127		AM_RANGE( 0x00f0, 0x00f7) AM_DEVREADWRITE8(Z80SIO_TAG, z80sio_device, read, write, 0x00ff)
128		AM_RANGE( 0x0400, 0x041f) AM_READWRITE8(nimbus_disk_r, nimbus_disk_w, 0x00FF)
	120	AM_RANGE( 0x0000, 0x0031) AM_READWRITE(nimbus_video_io_r, nimbus_video_io_w)
	121	AM_RANGE( 0x0032, 0x007f) AM_READWRITE(nimbus_io_r, nimbus_io_w)
	122	AM_RANGE( 0x0080, 0x0081) AM_READWRITE8(nimbus_mcu_r, nimbus_mcu_w, 0x00FF)
	123	AM_RANGE( 0x0092, 0x0093) AM_READWRITE8(nimbus_iou_r, nimbus_iou_w, 0x00FF)
	124	AM_RANGE( 0x00A4, 0x00A5) AM_READWRITE8(nimbus_mouse_js_r, nimbus_mouse_js_w, 0x00FF)
	125	AM_RANGE( 0X00c0, 0X00cf) AM_READWRITE8(nimbus_pc8031_r, nimbus_pc8031_w, 0x00FF)
	126	AM_RANGE( 0X00e0, 0X00ef) AM_READWRITE8(nimbus_sound_ay8910_r, nimbus_sound_ay8910_w, 0x00FF)
	127	AM_RANGE( 0x00f0, 0x00f7) AM_DEVREADWRITE8(Z80SIO_TAG, z80sio_device, read, write, 0x00ff)
	128	AM_RANGE( 0x0400, 0x041f) AM_READWRITE8(nimbus_disk_r, nimbus_disk_w, 0x00FF)
129	129	AM_RANGE( 0x0480, 0x049f) AM_DEVREADWRITE8(VIA_TAG, via6522_device, read, write, 0x00FF)
130	130	AM_RANGE( 0xff00, 0xffff) AM_READWRITE(nimbus_i186_internal_port_r, nimbus_i186_internal_port_w)/* CPU 80186 */
131	131	ADDRESS_MAP_END
r18355	r18356
138	138
139	139	PORT_START("KEY0") /* Key row 0 scancodes 00..07 */
140	140	//PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1) PORT_CHAR('1')
141		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED)
	141	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED)
142	142	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC) PORT_CHAR(0x1B)
143	143	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1") PORT_CODE(KEYCODE_1) PORT_CHAR('1')
144	144	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("2") PORT_CODE(KEYCODE_2) PORT_CHAR('2')
145	145	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("3") PORT_CODE(KEYCODE_3) PORT_CHAR('3')
146	146	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("4") PORT_CODE(KEYCODE_4) PORT_CHAR('4')
147	147	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("5") PORT_CODE(KEYCODE_5) PORT_CHAR('5')
148		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("6") PORT_CODE(KEYCODE_6) PORT_CHAR('6')
	148	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("6") PORT_CODE(KEYCODE_6) PORT_CHAR('6')
149	149
150	150	PORT_START("KEY1") /* Key row 1 scancodes 08..0F */
151	151	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("7") PORT_CODE(KEYCODE_7) PORT_CHAR('7')
r18355	r18356
155	155	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("-") PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-')
156	156	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("=") PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=')
157	157	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BSPACE") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(0x08)
158		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
	158	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR(0x09)
159	159
160	160	PORT_START("KEY2") /* Key row 2 scancodes 10..17 */
161	161	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Q") PORT_CODE(KEYCODE_Q) PORT_CHAR('Q')
r18355	r18356
165	165	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("T") PORT_CODE(KEYCODE_T) PORT_CHAR('T')
166	166	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('Y')
167	167	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('U')
168		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I')
	168	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('I')
169	169
170	170	PORT_START("KEY3") /* Key row 3 scancodes 18..1F */
171	171	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('O')
r18355	r18356
175	175	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ENTER") PORT_CODE(KEYCODE_ENTER) PORT_CHAR(0x0D)
176	176	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) // Ether control
177	177	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("A") PORT_CODE(KEYCODE_A) PORT_CHAR('A')
178		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S')
	178	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("S") PORT_CODE(KEYCODE_S) PORT_CHAR('S')
179	179
180	180	PORT_START("KEY4") /* Key row 4 scancodes 20..27 */
181	181	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("D") PORT_CODE(KEYCODE_D) PORT_CHAR('D')
r18355	r18356
185	185	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("J") PORT_CODE(KEYCODE_J) PORT_CHAR('J')
186	186	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("K") PORT_CODE(KEYCODE_K) PORT_CHAR('K')
187	187	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("L") PORT_CODE(KEYCODE_L) PORT_CHAR('L')
188		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(";") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';')
	188	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(";") PORT_CODE(KEYCODE_COLON) PORT_CHAR(';')
189	189
190	190	PORT_START("KEY5") /* Key row 5 scancodes 28..2F */
191		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("#") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('#')
	191	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("#") PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('#')
192	192	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("BACKSLASH") PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR('\\')
193	193	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("LSHIFT") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
194	194	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("TILDE") PORT_CODE(KEYCODE_TILDE) PORT_CHAR('`')
r18355	r18356
199	199
200	200
201	201	PORT_START("KEY6") /* Key row 6 scancodes 30..37 */
202		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B')
203		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N')
	202	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("B") PORT_CODE(KEYCODE_B) PORT_CHAR('B')
	203	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("N") PORT_CODE(KEYCODE_N) PORT_CHAR('N')
204	204	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("M") PORT_CODE(KEYCODE_M) PORT_CHAR('M')
205	205	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(",") PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',')
206	206	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME(".") PORT_CODE(KEYCODE_STOP) PORT_CHAR('.')
r18355	r18356
209	209	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("PRSCR") PORT_CODE(KEYCODE_ASTERISK) PORT_CHAR('*')
210	210
211	211	PORT_START("KEY7") /* Key row 7 scancodes 38..3F */
212		PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ALT") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT)
213		PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
	212	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("ALT") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT)
	213	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
214	214	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CAPS") PORT_CODE(KEYCODE_CAPSLOCK)
215	215	PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F1") PORT_CODE(KEYCODE_F1)
216	216	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F2") PORT_CODE(KEYCODE_F2)
r18355	r18356
219	219	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F5") PORT_CODE(KEYCODE_F5)
220	220
221	221
222		PORT_START("KEY8") /* Key row 8 scancodes 40..47 */
	222	PORT_START("KEY8") /* Key row 8 scancodes 40..47 */
223	223	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F6") PORT_CODE(KEYCODE_F6)
224	224	PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F7") PORT_CODE(KEYCODE_F7)
225	225	PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F8") PORT_CODE(KEYCODE_F8)
r18355	r18356
227	227	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F10") PORT_CODE(KEYCODE_F10)
228	228	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("NUMLK") PORT_CODE(KEYCODE_NUMLOCK)
229	229	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("SCRLK") PORT_CODE(KEYCODE_SCRLOCK)
230		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP7") PORT_CODE(KEYCODE_7_PAD) PORT_CHAR('7')
	230	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP7") PORT_CODE(KEYCODE_7_PAD) PORT_CHAR('7')
231	231
232	232	PORT_START("KEY9") /* Key row 9 scancodes 48..4F */
233	233	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP8") PORT_CODE(KEYCODE_8_PAD) //PORT_CHAR('8')
r18355	r18356
237	237	PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP5") PORT_CODE(KEYCODE_5_PAD) //PORT_CHAR('5')
238	238	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP6") PORT_CODE(KEYCODE_6_PAD) //PORT_CHAR('6')
239	239	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP+") PORT_CODE(KEYCODE_PLUS_PAD) //PORT_CHAR('+')
240		PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP1") PORT_CODE(KEYCODE_1_PAD) //PORT_CHAR('1')
	240	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP1") PORT_CODE(KEYCODE_1_PAD) //PORT_CHAR('1')
241	241
242	242	PORT_START("KEY10") /* Key row 10 scancodes 50..57 */
243	243	PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP2") PORT_CODE(KEYCODE_2_PAD) //PORT_CHAR('2')
r18355	r18356
248	248	PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED)
249	249	PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNUSED)
250	250	PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED)
251		//PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP5") PORT_CODE(KEYCODE_5_PAD) PORT_CHAR('5')
	251	//PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP5") PORT_CODE(KEYCODE_5_PAD) PORT_CHAR('5')
252	252	//PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP6") PORT_CODE(KEYCODE_6_PAD) PORT_CHAR('6')
253	253	//PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP+") PORT_CODE(KEYCODE_PLUS_PAD) PORT_CHAR('+')
254		//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP1") PORT_CODE(KEYCODE_1_PAD) PORT_CHAR('1')
	254	//PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("KP1") PORT_CODE(KEYCODE_1_PAD) PORT_CHAR('1')
255	255
256	256	PORT_START(JOYSTICK0_TAG)
257	257	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1) PORT_8WAY // XB
r18355	r18356
261	261	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
262	262	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
263	263
264		PORT_START(MOUSE_BUTTON_TAG) /* Mouse buttons */
	264	PORT_START(MOUSE_BUTTON_TAG) /* Mouse buttons */
265	265	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON2) PORT_NAME("Mouse Button 2") PORT_CODE(MOUSECODE_BUTTON2)
266	266	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON1) PORT_NAME("Mouse Button 1") PORT_CODE(MOUSECODE_BUTTON1)
267	267
r18355	r18356
292	292	int colourno;
293	293
294	294	for ( colourno = 0; colourno < SCREEN_NO_COLOURS; colourno++ )
295		{
	295	{
296	296	palette_set_color_rgb(machine(), colourno, nimbus_palette[colourno][RED], nimbus_palette[colourno][GREEN], nimbus_palette[colourno][BLUE]);
297	297	}
298	298	}
299	299
300	300
301	301	static MACHINE_CONFIG_START( nimbus, rmnimbus_state )
302		/* basic machine hardware */
303		MCFG_CPU_ADD(MAINCPU_TAG, I80186, 10000000)
304		MCFG_CPU_PROGRAM_MAP(nimbus_mem)
305		MCFG_CPU_IO_MAP(nimbus_io)
	302	/* basic machine hardware */
	303	MCFG_CPU_ADD(MAINCPU_TAG, I80186, 10000000)
	304	MCFG_CPU_PROGRAM_MAP(nimbus_mem)
	305	MCFG_CPU_IO_MAP(nimbus_io)
306	306
307		MCFG_CPU_ADD(IOCPU_TAG, I8031, 11059200)
308		MCFG_CPU_PROGRAM_MAP(nimbus_iocpu_mem)
309		MCFG_CPU_IO_MAP(nimbus_iocpu_io)
	307	MCFG_CPU_ADD(IOCPU_TAG, I8031, 11059200)
	308	MCFG_CPU_PROGRAM_MAP(nimbus_iocpu_mem)
	309	MCFG_CPU_IO_MAP(nimbus_iocpu_io)
310	310
311	311
312	312
313		/* video hardware */
314		MCFG_SCREEN_ADD("screen", RASTER)
315		MCFG_SCREEN_REFRESH_RATE(50)
316		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(100))
	313	/* video hardware */
	314	MCFG_SCREEN_ADD("screen", RASTER)
	315	MCFG_SCREEN_REFRESH_RATE(50)
	316	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(100))
317	317	MCFG_SCREEN_UPDATE_DRIVER(rmnimbus_state, screen_update_nimbus)
318	318	MCFG_SCREEN_VBLANK_DRIVER(rmnimbus_state, screen_eof_nimbus)
319	319
320		MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_SCANLINE)
	320	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_SCANLINE)
321	321
322		MCFG_PALETTE_LENGTH(SCREEN_NO_COLOURS * 3)
	322	MCFG_PALETTE_LENGTH(SCREEN_NO_COLOURS * 3)
323	323
324		MCFG_SCREEN_SIZE(650, 260)
325		MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
	324	MCFG_SCREEN_SIZE(650, 260)
	325	MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 249)
326	326
327	327
328	328
329		/* Backing storage */
	329	/* Backing storage */
330	330	MCFG_WD2793_ADD(FDC_TAG, nimbus_wd17xx_interface )
331	331	MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(nimbus_floppy_interface)
332	332
r18355	r18356
337	337	MCFG_SCSIDEV_ADD(SCSIBUS_TAG ":harddisk3", SCSIHD, SCSI_ID_3)
338	338	MCFG_SCSICB_ADD(SCSIBUS_TAG ":host", scsibus_config)
339	339
340		MCFG_RAM_ADD(RAM_TAG)
	340	MCFG_RAM_ADD(RAM_TAG)
341	341	MCFG_RAM_DEFAULT_SIZE("1536K")
342	342	MCFG_RAM_EXTRA_OPTIONS("128K,256K,384K,512K,640K,1024K")
343	343
344		/* Peripheral chips */
345		MCFG_Z80SIO_ADD(Z80SIO_TAG, 4000000, nimbus_sio_intf)
	344	/* Peripheral chips */
	345	MCFG_Z80SIO_ADD(Z80SIO_TAG, 4000000, nimbus_sio_intf)
346	346
347		MCFG_ER59256_ADD(ER59256_TAG)
	347	MCFG_ER59256_ADD(ER59256_TAG)
348	348
349	349	MCFG_VIA6522_ADD(VIA_TAG, 1000000, nimbus_via)
350	350	MCFG_CENTRONICS_PRINTER_ADD(CENTRONICS_TAG, nimbus_centronics_config)
r18355	r18356
364	364
365	365
366	366	ROM_START( nimbus )
367		ROM_REGION( 0x100000, MAINCPU_TAG, 0 )
	367	ROM_REGION( 0x100000, MAINCPU_TAG, 0 )
368	368
369		ROM_SYSTEM_BIOS(0, "v131a", "Nimbus BIOS v1.31a (1986-06-18)")
370		ROMX_LOAD("sys1-1.31a-16128-1986-06-18.rom", 0xf0001, 0x8000, CRC(6416eb05) SHA1(1b640163a7efbc24381c7b24976a8609c066959b),ROM_SKIP(1) \| ROM_BIOS(1) )
371		ROMX_LOAD("sys2-1.31a-16129-1986-06-18.rom", 0xf0000, 0x8000, CRC(b224359d) SHA1(456bbe37afcd4429cca76ba2d6bd534dfda3fc9c),ROM_SKIP(1) \| ROM_BIOS(1) )
	369	ROM_SYSTEM_BIOS(0, "v131a", "Nimbus BIOS v1.31a (1986-06-18)")
	370	ROMX_LOAD("sys1-1.31a-16128-1986-06-18.rom", 0xf0001, 0x8000, CRC(6416eb05) SHA1(1b640163a7efbc24381c7b24976a8609c066959b),ROM_SKIP(1) \| ROM_BIOS(1) )
	371	ROMX_LOAD("sys2-1.31a-16129-1986-06-18.rom", 0xf0000, 0x8000, CRC(b224359d) SHA1(456bbe37afcd4429cca76ba2d6bd534dfda3fc9c),ROM_SKIP(1) \| ROM_BIOS(1) )
372	372
373		ROM_SYSTEM_BIOS(1, "v132f", "Nimbus BIOS v1.32f (1989-10-20)")
374		ROMX_LOAD("sys-1-1.32f-22779-1989-10-20.rom", 0xf0001, 0x8000, CRC(786c31e8) SHA1(da7f828f7f96087518bea1a3d89fee59b283b4ba),ROM_SKIP(1) \| ROM_BIOS(2) )
375		ROMX_LOAD("sys-2-1.32f-22779-1989-10-20.rom", 0xf0000, 0x8000, CRC(0be3db64) SHA1(af806405ec6fbc20385705f90d5059a47de17b08),ROM_SKIP(1) \| ROM_BIOS(2) )
	373	ROM_SYSTEM_BIOS(1, "v132f", "Nimbus BIOS v1.32f (1989-10-20)")
	374	ROMX_LOAD("sys-1-1.32f-22779-1989-10-20.rom", 0xf0001, 0x8000, CRC(786c31e8) SHA1(da7f828f7f96087518bea1a3d89fee59b283b4ba),ROM_SKIP(1) \| ROM_BIOS(2) )
	375	ROMX_LOAD("sys-2-1.32f-22779-1989-10-20.rom", 0xf0000, 0x8000, CRC(0be3db64) SHA1(af806405ec6fbc20385705f90d5059a47de17b08),ROM_SKIP(1) \| ROM_BIOS(2) )
376	376
377		ROM_SYSTEM_BIOS(2, "v140d", "Nimbus BIOS v1.40d (1990-xx-xx)")
378		ROMX_LOAD("sys-1-1.40d.rom", 0xf0001, 0x8000, CRC(b8d3dc0b) SHA1(82e0dcdc6c7a83339af68d6cb61211fcb14bed88),ROM_SKIP(1) \| ROM_BIOS(3) )
379		ROMX_LOAD("sys-2-1.40d.rom", 0xf0000, 0x8000, CRC(b0826b0b) SHA1(3baa369a0e7ef138ca29aae0ee8a89ab670a02b9),ROM_SKIP(1) \| ROM_BIOS(3) )
	377	ROM_SYSTEM_BIOS(2, "v140d", "Nimbus BIOS v1.40d (1990-xx-xx)")
	378	ROMX_LOAD("sys-1-1.40d.rom", 0xf0001, 0x8000, CRC(b8d3dc0b) SHA1(82e0dcdc6c7a83339af68d6cb61211fcb14bed88),ROM_SKIP(1) \| ROM_BIOS(3) )
	379	ROMX_LOAD("sys-2-1.40d.rom", 0xf0000, 0x8000, CRC(b0826b0b) SHA1(3baa369a0e7ef138ca29aae0ee8a89ab670a02b9),ROM_SKIP(1) \| ROM_BIOS(3) )
380	380
381		ROM_REGION( 0x4000, IOCPU_TAG, 0 )
382		ROM_LOAD("hexec-v1.02u-13488-1985-10-29.rom", 0x0000, 0x1000, CRC(75c6adfd) SHA1(0f11e0b7386c6368d20e1fc7a6196d670f924825))
	381	ROM_REGION( 0x4000, IOCPU_TAG, 0 )
	382	ROM_LOAD("hexec-v1.02u-13488-1985-10-29.rom", 0x0000, 0x1000, CRC(75c6adfd) SHA1(0f11e0b7386c6368d20e1fc7a6196d670f924825))
383	383	ROM_END
384	384
385	385

199869 Revisions