MAME SVN History

199869 Revisions

r18327 Sunday 7th October, 2012 at 09:12:56 UTC by Curt Coder
srcclean (nw)

[hash]	a2600.xml cbm2_cart.xml cbm2_flop.xml p500_flop.xml pc8801_flop.xml pc98.xml
[src/emu]	clifront.c devdelegate.c devdelegate.h device.h driver.c driver.h
[src/emu/cpu/tms0980]	tms0980.c
[src/emu/machine]	53c810.c ds75160a.h ds75161a.c ds75161a.h mos6526.c rtc4543.c s3c2400.c s3c2410.c scsibus.c seibu_cop.c
[src/emu/sound]	sn76496.c
[src/emu/video]	pc_vga.c pc_vga.h tms9928a.c
[src/mame/drivers]	8080bw.c blackt96.c calchase.c cd32.c cdi.c cps1.c deshoros.c firebeat.c gammagic.c ggconnie.c intrscti.c jack.c jpmsys5.c kontest.c magictg.c magtouch.c mediagx.c ninjakd2.c nsm.c pangofun.c pcat_dyn.c pcat_nit.c pipedrm.c pntnpuzl.c queen.c raiden2.c saturn.c savquest.c shangha3.c spectra.c su2000.c taitowlf.c techno.c vicdual.c vlc.c xtom3d.c
[src/mame/includes]	archimds.h bfm_sc45.h bzone.h crbaloon.h deco32.h decocass.h dkong.h irobot.h kaneko16.h m79amb.h megadriv.h mw8080bw.h ninjakd2.h orbit.h stv.h vicdual.h
[src/mame/machine]	archimds.c genpin.h megacd.c megacd.h pcecommn.h seicop.c
[src/mame/video]	awpvid.c dkong.c jack.c ninjakd2.c
[src/mess/drivers]	a2600.c ami1200.c amiga.c astrocde.c bml3.c c128.c c64.c cbm2.c d6800.c elwro800.c indiana.c jr100.c korgm1.c n64.c pc8801.c pv9234.c rainbow.c test_t400.c ti99_4p.c ti99_4x.c tm990189.c vic10.c x68k.c xerox820.c xor100.c
[src/mess/includes]	atarist.h cbm2.h comquest.h concept.h dccons.h fmtowns.h kramermc.h vtech2.h x68k.h
[src/mess/machine]	a2arcadebd.c amigakbd.h bebox.c cbm2_graphic.c kr2376.c msx.c pc.c rx01.c vtech2.c
[src/mess/video]	isa_svga_cirrus.c isa_svga_cirrus.h isa_svga_s3.c isa_svga_s3.h isa_svga_tseng.c isa_svga_tseng.h isa_vga.c isa_vga.h isa_vga_ati.c isa_vga_ati.h nubus_vikbw.h

trunk/hash/pc98.xml
r18326	r18327
16	16	<!--
17	17	PC-9821Xw System Restore startup disk
18	18
19		this is a System Restore startup disk for PC-9821Xw
20		but not a Windows install source(need more disk?)
	19	this is a System Restore startup disk for PC-9821Xw
	20	but not a Windows install source(need more disk?)
21	21
22	22	only have some part of Windows file and a Video driver(CLGD?).
23	23	-->

trunk/hash/cbm2_cart.xml
r18326	r18327
6	6	<description>Calc Result</description>
7	7	<year>1983</year>
8	8	<publisher>Handic Software</publisher>
9
	9
10	10	<part name="cart" interface="cbm2_cart">
11	11	<dataarea name="bank3" size="0x2000">
12	12	<rom name="calc_result-bx700.bin" size="0x2000" crc="4775ebb3" sha1="5c6928a9cd8a3ce6a1d11221292b832295d6543e" offset="0" />
r18326	r18327
24	24	<description>ProfiText</description>
25	25	<year>198?</year>
26	26	<publisher><unknown></publisher>
27
	27
28	28	<part name="cart" interface="cbm2_cart">
29	29	<dataarea name="bank1" size="0x2000">
30	30	<rom name="profitext.bin" size="0x2000" crc="ac622a2b" sha1="a02fcd187b7493a08379bbaef3d4296a083d30c8" offset="0" />
r18326	r18327
36	36	<description>Demo 1</description>
37	37	<year>198?</year>
38	38	<publisher><unknown></publisher>
39
	39
40	40	<part name="cart" interface="cbm2_cart">
41	41	<dataarea name="bank1" size="0x2000">
42	42	<rom name="cbm610-cart1-red-left.bin" size="0x2000" crc="be426f3d" sha1="da6f1099fd09165f8ee454e2e517cfc523deb8b7" offset="0" />
r18326	r18327
52	52	<description>Demo 2</description>
53	53	<year>198?</year>
54	54	<publisher><unknown></publisher>
55
	55
56	56	<part name="cart" interface="cbm2_cart">
57	57	<dataarea name="bank1" size="0x2000">
58	58	<rom name="cbm610-cart2-white-left.bin" size="0x2000" crc="aeb6881c" sha1="4bdabbd7d6d642f916b5a91155396c98fce591a3" offset="0" />
r18326	r18327
68	68	<description>Moni610</description>
69	69	<year>2008</year>
70	70	<publisher>Ullrich von Bassewitz</publisher>
71
	71
72	72	<part name="cart" interface="cbm2_cart">
73	73	<dataarea name="bank1" size="0x2000">
74	74	<rom name="moni.bin" size="0x2000" crc="43b08d1f" sha1="9c0c24907e85674348dd58e81e6da64e157e9d0f" offset="0" />
r18326	r18327
80	80	<description>VT52 Emulator</description>
81	81	<year>1986</year>
82	82	<publisher><unknown></publisher>
83
	83
84	84	<part name="cart" interface="cbm2_cart">
85	85	<dataarea name="bank2" size="0x2000">
86	86	<rom name="vt52emu.bin" size="0x2000" crc="b3b6173a" sha1="dd4a412a1a6ce4272b02d731364dd6dc96a4570b" offset="0" />
r18326	r18327
92	92	<description>High Resolution Graphics</description>
93	93	<year>198?</year>
94	94	<publisher>Commodore</publisher>
95
	95
96	96	<part name="cart" interface="cbm2_cart">
97	97	<feature name="slot" value="graphic" />
98	98
r18326	r18327
106	106	<description>Word Result</description>
107	107	<year>198?</year>
108	108	<publisher>Handic Software</publisher>
109
	109
110	110	<part name="cart" interface="cbm2_cart">
111	111	<dataarea name="bank1" size="0x1000">
112	112	<!-- this is the Commodore 64 character generator ROM, used as a copy protection dongle -->

trunk/hash/cbm2_flop.xml
r18326	r18327
1	1	<?xml version="1.0"?>
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3	<softwarelist name="cbm2_flop" description="Commodore CBM-II diskettes">
4
	4
5	5	<software name="burnin">
6	6	<description>Factory Burn In Diagnostics for B Series</description>
7	7	<year>1983</year>
r18326	r18327
13	13	</dataarea>
14	14	</part>
15	15	</software>
16
	16
17	17	<software name="termv2">
18	18	<description>Terminal Version 2.0 for B Series</description>
19	19	<year>1983</year>

trunk/hash/a2600.xml
r18326	r18327
355	355	</part>
356	356	</software>
357	357
358		<software name="decathln">
	358	<software name="decathln">
359	359	<description>The Activision Decathlon</description>
360	360	<year>1983</year>
361	361	<publisher>Activision</publisher>
r18326	r18327
597	597	</part>
598	598	</software>
599	599
600		<software name="abwerniee" cloneof="abwernie">
	600	<software name="abwerniee" cloneof="abwernie">
601	601	<!-- controller not emulated -->
602	602	<description>Alpha Beam with Ernie (PAL)</description>
603	603	<year>1983</year>

trunk/hash/pc8801_flop.xml
r18326	r18327
54516	54516	</software>
54517	54517
54518	54518
54519		<!-- AKA PC-8001_Game_Pack_vol.3
	54519	<!-- AKA PC-8001_Game_Pack_vol.3
54520	54520	BUGFIRE
54521	54521	CHECK POINT
54522	54522	EUROPE(?) (タイトル不明、ヨーロッパ戦線的なゲームです)

trunk/hash/p500_flop.xml
r18326	r18327
1	1	<?xml version="1.0"?>
2	2	<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
3	3	<softwarelist name="p500_flop" description="Commodore P500 diskettes">
4
	4
5	5	<software name="burnin">
6	6	<description>Factory Burn In Diagnostics for P500</description>
7	7	<year>1983</year>

trunk/src/emu/clifront.c
r18326	r18327
1283	1283
1284	1284
1285	1285	/*-------------------------------------------------
1286		verifysoftware - verify roms from the software
	1286	verifysoftware - verify roms from the software
1287	1287	list of the specified driver(s)
1288	1288	-------------------------------------------------*/
1289	1289	void cli_frontend::verifysoftware(const char *gamename)

trunk/src/emu/video/tms9928a.c
r18326	r18327
97	97	{
98	98	m_50hz = is_50hz;
99	99	m_reva = is_reva;
100		// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
	100	// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
101	101	}
102	102
103	103
r18326	r18327
108	108	{
109	109	m_50hz = false;
110	110	m_reva = true;
111		// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
	111	// static_set_addrmap(*this, AS_DATA, ADDRESS_MAP_NAME(memmap));
112	112	}
113	113
114	114

trunk/src/emu/video/pc_vga.c
r18326	r18327
203	203
204	204	// Avoid an infinite loop when displaying. 0 is not possible anyway.
205	205	vga.crtc.maximum_scan_line = 1;
206
207	206
208		// copy over interfaces
209		vga.read_dipswitch = read8_delegate(); //read_dipswitch;
	207
	208	// copy over interfaces
	209	vga.read_dipswitch = read8_delegate(); //read_dipswitch;
210	210	vga.svga_intf.vram_size = 0x100000;
211	211	vga.svga_intf.seq_regcount = 0x05;
212	212	vga.svga_intf.crtc_regcount = 0x19;
213	213
214		vga.memory = auto_alloc_array_clear(machine(), UINT8, vga.svga_intf.vram_size);
	214	vga.memory = auto_alloc_array_clear(machine(), UINT8, vga.svga_intf.vram_size);
215	215	}
216	216
217	217	void svga_device::device_start()
r18326	r18327
231	231
232	232	// Avoid an infinite loop when displaying. 0 is not possible anyway.
233	233	vga.crtc.maximum_scan_line = 1;
234
235	234
236		// copy over interfaces
237		vga.read_dipswitch = read8_delegate(); //read_dipswitch;
	235
	236	// copy over interfaces
	237	vga.read_dipswitch = read8_delegate(); //read_dipswitch;
238	238	vga.svga_intf.vram_size = 0x200000;
239	239	vga.svga_intf.seq_regcount = 0x08;
240	240	vga.svga_intf.crtc_regcount = 0x19;
241	241
242		vga.memory = auto_alloc_array_clear(machine(), UINT8, vga.svga_intf.vram_size);
	242	vga.memory = auto_alloc_array_clear(machine(), UINT8, vga.svga_intf.vram_size);
243	243	}
244	244
245	245	void ati_vga_device::device_start()
r18326	r18327
1599	1599	case 3:
1600	1600	if (!vga.read_dipswitch.isnull() && vga.read_dipswitch(space, 0, mem_mask) & 0x01)
1601	1601	data \|= 0x10;
1602		else
	1602	else
1603	1603	data \|= 0x10;
1604	1604	break;
1605	1605	case 2:
1606	1606	if (!vga.read_dipswitch.isnull() && vga.read_dipswitch(space, 0, mem_mask) & 0x02)
1607	1607	data \|= 0x10;
1608		else
	1608	else
1609	1609	data \|= 0x10;
1610	1610	break;
1611	1611	case 1:
1612	1612	if (!vga.read_dipswitch.isnull() && vga.read_dipswitch(space, 0, mem_mask) & 0x04)
1613	1613	data \|= 0x10;
1614		else
	1614	else
1615	1615	data \|= 0x10;
1616	1616	break;
1617	1617	case 0:
1618	1618	if (!vga.read_dipswitch.isnull() && vga.read_dipswitch(space, 0, mem_mask) & 0x08)
1619	1619	data \|= 0x10;
1620		else
	1620	else
1621	1621	data \|= 0x10;
1622	1622	break;
1623	1623	}
r18326	r18327
2045	2045	MCFG_SCREEN_UPDATE_DEVICE("vga", trident_vga_device, screen_update)
2046	2046
2047	2047	MCFG_PALETTE_LENGTH(0x100)
2048
	2048
2049	2049	MCFG_DEVICE_ADD("vga", TRIDENT_VGA, 0)
2050	2050	MACHINE_CONFIG_END
2051	2051
r18326	r18327
2055	2055	MCFG_SCREEN_UPDATE_DEVICE("vga", cirrus_vga_device, screen_update)
2056	2056
2057	2057	MCFG_PALETTE_LENGTH(0x100)
2058
	2058
2059	2059	MCFG_DEVICE_ADD("vga", CIRRUS_VGA, 0)
2060	2060	MACHINE_CONFIG_END
2061	2061

trunk/src/emu/video/pc_vga.h
r18326	r18327
27	27
28	28
29	29	virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
30
	30
31	31	virtual READ8_MEMBER(port_03b0_r);
32	32	virtual WRITE8_MEMBER(port_03b0_w);
33	33	virtual READ8_MEMBER(port_03c0_r);
r18326	r18327
48	48	void vga_vh_vga(bitmap_rgb32 &bitmap, const rectangle &cliprect);
49	49	void vga_vh_cga(bitmap_rgb32 &bitmap, const rectangle &cliprect);
50	50	void vga_vh_mono(bitmap_rgb32 &bitmap, const rectangle &cliprect);
51		virtual UINT8 pc_vga_choosevideomode();
	51	virtual UINT8 pc_vga_choosevideomode();
52	52	void recompute_params_clock(int divisor, int xtal);
53	53	UINT8 crtc_reg_read(UINT8 index);
54	54	void recompute_params();
r18326	r18327
64	64	inline UINT8 rotate_right(UINT8 val);
65	65	inline UINT8 vga_logical_op(UINT8 data, UINT8 plane, UINT8 mask);
66	66	inline UINT8 vga_latch_write(int offs, UINT8 data);
67
	67
68	68	protected:
69	69	struct
70	70	{
r18326	r18327
183	183
184	184	/* oak vga */
185	185	struct { UINT8 reg; } oak;
186		} vga;
	186	} vga;
187	187	};
188	188
189	189
r18326	r18327
196	196	{
197	197	public:
198	198	// construction/destruction
199		svga_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
	199	svga_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t *owner, UINT32 clock);
200	200
201	201	virtual UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
202	202	protected:
r18326	r18327
588	588	virtual WRITE8_MEMBER(port_03d0_w);
589	589	virtual READ8_MEMBER(mem_r);
590	590	virtual WRITE8_MEMBER(mem_w);
591
	591
592	592	protected:
593	593	private:
594	594	};

trunk/src/emu/machine/seibu_cop.c
r18326	r18327
178	178	WRITE16_MEMBER(seibu_cop_device::dma_unk_param_w)
179	179	{
180	180	/*
181		This sets up a DMA mode of some sort
182		0x0e00: grainbow, cupsoc
183		0x0a00: legionna, godzilla, denjinmk
184		0x0600: heatbrl
185		0x1e00: zeroteam, xsedae
186		raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs
187		(both only uses 0x14 and 0x15 as DMAs afaik)
	181	This sets up a DMA mode of some sort
	182	0x0e00: grainbow, cupsoc
	183	0x0a00: legionna, godzilla, denjinmk
	184	0x0600: heatbrl
	185	0x1e00: zeroteam, xsedae
	186	raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs
	187	(both only uses 0x14 and 0x15 as DMAs afaik)
188	188	*/
189	189	COMBINE_DATA(&m_dma_unk_param);
190	190	}
r18326	r18327
271	271	0x86 is used by Seibu Cup Soccer
272	272	0x87 is used by Denjin Makai
273	273
274		TODO:
	274	TODO:
275	275	- Denjin Makai mode 4 is totally guessworked.
276	276	- SD Gundam doesn't fade colors correctly, it should have the text layer / sprites with normal gradient and the rest dimmed in most cases,
277	277	presumably bad RAM table or bad algorithm

trunk/src/emu/machine/s3c2400.c
r18326	r18327
62	62	space.install_legacy_readwrite_handler( *device, 0x15800000, 0x15800007, FUNC(s3c24xx_adc_r), FUNC(s3c24xx_adc_w));
63	63	space.install_legacy_readwrite_handler( *device, 0x15900000, 0x15900017, FUNC(s3c24xx_spi_0_r), FUNC(s3c24xx_spi_0_w));
64	64	space.install_legacy_readwrite_handler( *device, 0x15a00000, 0x15a0003f, FUNC(s3c24xx_mmc_r), FUNC(s3c24xx_mmc_w));
65
	65
66	66	s3c24xx_video_start( device, device->machine());
67	67	}
68	68

trunk/src/emu/machine/mos6526.c
r18326	r18327
9	9
10	10	/*
11	11
12		TODO:
	12	TODO:
13	13
14		- pass Lorenz test suite 2.15
15		- ICR01
16		- IMR
17		- CIA1TA/TB
18		- CIA2TA/TB
19		- pass VICE cia tests
20		- 8520 read/write
21		- 5710 read/write
22		- optimize
	14	- pass Lorenz test suite 2.15
	15	- ICR01
	16	- IMR
	17	- CIA1TA/TB
	18	- CIA2TA/TB
	19	- pass VICE cia tests
	20	- 8520 read/write
	21	- 5710 read/write
	22	- optimize
23	23
24	24	*/
25	25
r18326	r18327
49	49	SDR,
50	50	ICR, IMR = ICR,
51	51	CRA,
52		CRB
	52	CRB
53	53	};
54	54
55	55
r18326	r18327
79	79
80	80	#define CRA_START 0x01
81	81	#define CRA_STARTED BIT(m_cra, 0)
82		#define CRA_PBON BIT(m_cra, 1)
	82	#define CRA_PBON BIT(m_cra, 1)
83	83	#define CRA_OUTMODE BIT(m_cra, 2)
84	84	#define CRA_RUNMODE BIT(m_cra, 3)
85	85	#define CRA_LOAD BIT(m_cra, 4)
86		#define CRA_INMODE BIT(m_cra, 5)
87		#define CRA_SPMODE BIT(m_cra, 6)
88		#define CRA_TODIN BIT(m_cra, 7)
	86	#define CRA_INMODE BIT(m_cra, 5)
	87	#define CRA_SPMODE BIT(m_cra, 6)
	88	#define CRA_TODIN BIT(m_cra, 7)
89	89
90	90
91	91	// control register B
r18326	r18327
99	99
100	100	#define CRB_START 0x01
101	101	#define CRB_STARTED BIT(m_crb, 0)
102		#define CRB_PBON BIT(m_crb, 1)
	102	#define CRB_PBON BIT(m_crb, 1)
103	103	#define CRB_OUTMODE BIT(m_crb, 2)
104	104	#define CRB_RUNMODE BIT(m_crb, 3)
105		#define CRB_LOAD BIT(m_crb, 4)
106		#define CRB_INMODE ((m_crb & 0x60) >> 5)
107		#define CRB_ALARM BIT(m_crb, 7)
	105	#define CRB_LOAD BIT(m_crb, 4)
	106	#define CRB_INMODE ((m_crb & 0x60) >> 5)
	107	#define CRB_ALARM BIT(m_crb, 7)
108	108
109	109
110	110
r18326	r18327
253	253
254	254	if ((value & 0x0f) >= 0x0a)
255	255	value += 0x10 - 0x0a;
256
	256
257	257	return value;
258	258	}
259	259
r18326	r18327
270	270	UINT8 hour = (UINT8) (m_tod >> 24);
271	271
272	272	m_tod_count++;
273
	273
274	274	if (m_tod_count == (CRA_TODIN ? 5 : 6))
275	275	{
276	276	m_tod_count = 0;
r18326	r18327
531	531	{
532	532	// timer A pipeline
533	533	m_count_a3 = m_count_a2;
534
	534
535	535	switch (CRA_INMODE)
536	536	{
537	537	case CRA_INMODE_PHI2:
r18326	r18327
566	566	case CRB_INMODE_CNT:
567	567	m_count_b2 = m_count_b1;
568	568	break;
569
	569
570	570	case CRB_INMODE_TA:
571	571	m_count_b2 = m_ta_out;
572	572	break;
573
	573
574	574	case CRB_INMODE_CNT_TA:
575	575	m_count_b2 = m_ta_out && m_cnt;
576	576	break;
r18326	r18327
594	594
595	595
596	596	//-------------------------------------------------
597		// synchronize -
	597	// synchronize -
598	598	//-------------------------------------------------
599	599
600	600	inline void mos6526_device::synchronize()
r18326	r18327
709	709	save_item(NAME(m_tb_latch));
710	710	save_item(NAME(m_cra));
711	711	save_item(NAME(m_crb));
712
	712
713	713	save_item(NAME(m_tod_count));
714	714	save_item(NAME(m_tod));
715	715	save_item(NAME(m_tod_latch));
r18326	r18327
838	838
839	839	case PRB:
840	840	data = (m_in_pb_func(0) & ~m_ddrb) \| (m_prb & m_ddrb);
841
	841
842	842	if (CRA_PBON)
843	843	{
844	844	int pb6 = CRA_OUTMODE ? m_ta_pb6 : m_ta_out;
r18326	r18327
854	854	data &= ~0x80;
855	855	data \|= pb7 << 7;
856	856	}
857
	857
858	858	m_pc = 0;
859	859	m_out_pc_func(m_pc);
860	860	break;
861
	861
862	862	case DDRA:
863	863	data = m_ddra;
864	864	break;
865
	865
866	866	case DDRB:
867	867	data = m_ddrb;
868	868	break;
869
	869
870	870	case TA_LO:
871	871	data = m_ta & 0xff;
872	872	break;
873
	873
874	874	case TA_HI:
875	875	data = m_ta >> 8;
876	876	break;
877
	877
878	878	case TB_LO:
879	879	data = m_tb & 0xff;
880	880	break;
881
	881
882	882	case TB_HI:
883	883	data = m_tb >> 8;
884	884	break;
885
	885
886	886	case TOD_10THS:
887	887	data = read_tod(0);
888	888
889	889	m_tod_latched = false;
890	890	break;
891
	891
892	892	case TOD_SEC:
893	893	data = read_tod(1);
894	894	break;
895
	895
896	896	case TOD_MIN:
897	897	data = read_tod(2);
898	898	break;
899
	899
900	900	case TOD_HR:
901	901	if (!m_tod_latched)
902	902	{
r18326	r18327
906	906
907	907	data = read_tod(3);
908	908	break;
909
	909
910	910	case SDR:
911	911	data = m_sdr;
912	912	break;
913
	913
914	914	case ICR:
915	915	data = (m_ir1 << 7) \| m_icr;
916	916
r18326	r18327
922	922	m_irq = false;
923	923	m_out_irq_func(CLEAR_LINE);
924	924	break;
925
	925
926	926	case CRA:
927	927	data = m_cra;
928	928	break;
929
	929
930	930	case CRB:
931	931	data = m_crb;
932	932	break;
r18326	r18327
952	952	case PRB:
953	953	m_prb = data;
954	954	update_pb();
955
	955
956	956	m_pc = 0;
957	957	m_out_pc_func(m_pc);
958	958	break;
959
	959
960	960	case DDRA:
961	961	m_ddra = data;
962	962	update_pa();
963	963	break;
964
	964
965	965	case DDRB:
966	966	m_ddrb = data;
967	967	update_pb();
968	968	break;
969
	969
970	970	case TA_LO:
971	971	m_ta_latch = (m_ta_latch & 0xff00) \| data;
972	972
r18326	r18327
975	975	m_ta = (m_ta & 0xff00) \| data;
976	976	}
977	977	break;
978
	978
979	979	case TA_HI:
980	980	m_ta_latch = (data << 8) \| (m_ta_latch & 0xff);
981	981
r18326	r18327
989	989	m_ta = (data << 8) \| (m_ta & 0xff);
990	990	}
991	991	break;
992
	992
993	993	case TB_LO:
994	994	m_tb_latch = (m_tb_latch & 0xff00) \| data;
995	995
r18326	r18327
998	998	m_tb = (m_tb & 0xff00) \| data;
999	999	}
1000	1000	break;
1001
	1001
1002	1002	case TB_HI:
1003	1003	m_tb_latch = (data << 8) \| (m_tb_latch & 0xff);
1004	1004
r18326	r18327
1012	1012	m_tb = (data << 8) \| (m_tb & 0xff);
1013	1013	}
1014	1014	break;
1015
	1015
1016	1016	case TOD_10THS:
1017	1017	write_tod(0, data);
1018	1018
1019	1019	m_tod_stopped = false;
1020	1020	break;
1021
	1021
1022	1022	case TOD_SEC:
1023	1023	write_tod(1, data);
1024	1024	break;
1025
	1025
1026	1026	case TOD_MIN:
1027	1027	write_tod(2, data);
1028	1028	break;
1029
	1029
1030	1030	case TOD_HR:
1031	1031	m_tod_stopped = true;
1032	1032
r18326	r18327
1038	1038
1039	1039	write_tod(3, data);
1040	1040	break;
1041
	1041
1042	1042	case SDR:
1043	1043	m_sdr = data;
1044	1044	m_sdr_empty = false;
1045	1045	break;
1046
	1046
1047	1047	case IMR:
1048	1048	if (IMR_SET)
1049	1049	{
r18326	r18327
1059	1059	m_ir0 = 1;
1060	1060	}
1061	1061	break;
1062
	1062
1063	1063	case CRA:
1064	1064	set_cra(data);
1065	1065	break;
1066
	1066
1067	1067	case CRB:
1068	1068	set_crb(data);
1069	1069	break;
r18326	r18327
1134	1134	m_count_a0 = 1;
1135	1135	m_count_b0 = 1;
1136	1136	}
1137
	1137
1138	1138	m_cnt = state;
1139	1139	}
1140	1140

trunk/src/emu/machine/rtc4543.c
r18326	r18327
2	2
3	3	rtc4543.c - Epson R4543 real-time clock chip emulation
4	4	by R. Belmont
5
	5
6	6	TODO: writing (not done by System 12 or 23 so no test case)
7
	7
8	8	**********************************************************************/
9	9
10	10	#include "rtc4543.h"
r18326	r18327
93	93	{
94	94	static const int weekday[7] = { 7, 1, 2, 3, 4, 5, 6 };
95	95
96		m_regs[0] = make_bcd(second); // seconds (BCD, 0-59) in bits 0-6, bit 7 = battery low
97		m_regs[1] = make_bcd(minute); // minutes (BCD, 0-59)
	96	m_regs[0] = make_bcd(second); // seconds (BCD, 0-59) in bits 0-6, bit 7 = battery low
	97	m_regs[1] = make_bcd(minute); // minutes (BCD, 0-59)
98	98	m_regs[2] = make_bcd(hour); // hour (BCD, 0-23)
99	99	m_regs[3] = make_bcd(weekday[day_of_week]); // low nibble = day of the week
100	100	m_regs[3] \|= (make_bcd(day) & 0x0f)<<4; // high nibble = low digit of day

trunk/src/emu/machine/s3c2410.c
r18326	r18327
65	65	space.install_legacy_readwrite_handler( *device, 0x59000000, 0x59000017, FUNC(s3c24xx_spi_0_r), FUNC(s3c24xx_spi_0_w));
66	66	space.install_legacy_readwrite_handler( *device, 0x59000020, 0x59000037, FUNC(s3c24xx_spi_1_r), FUNC(s3c24xx_spi_1_w));
67	67	space.install_legacy_readwrite_handler( *device, 0x5a000000, 0x5a000043, FUNC(s3c24xx_sdi_r), FUNC(s3c24xx_sdi_w));
68
	68
69	69	s3c24xx_video_start( device, device->machine());
70	70	}
71	71

trunk/src/emu/machine/ds75160a.h
r18326	r18327
81	81	devcb_resolved_write8 m_out_bus_func;
82	82
83	83	UINT8 m_data;
84
	84
85	85	int m_te;
86	86	int m_pe;
87	87	};

trunk/src/emu/machine/53c810.c
r18326	r18327
393	393
394	394	UINT8 lsi53c810_device::lsi53c810_reg_r( int offset )
395	395	{
396		// logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, space.device().safe_pc());
	396	// logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, space.device().safe_pc());
397	397	switch(offset)
398	398	{
399	399	case 0x00: /* SCNTL0 */
r18326	r18327
476	476
477	477	void lsi53c810_device::lsi53c810_reg_w(int offset, UINT8 data)
478	478	{
479		// logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, space.device().safe_pc());
	479	// logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, space.device().safe_pc());
480	480	switch(offset)
481	481	{
482	482	case 0x00: /* SCNTL0 */

trunk/src/emu/machine/scsibus.c
r18326	r18327
406	406	if(state)
407	407	{
408	408	data_idx++;
409
	409
410	410	// If the data buffer is full flush it to the SCSI disk
411	411
412	412	data_last = (bytes_left >= sectorbytes) ? sectorbytes : bytes_left;

trunk/src/emu/machine/ds75161a.c
r18326	r18327
95	95	m_in_eoi_func.resolve(m_in_eoi_cb, *this);
96	96	m_in_atn_func.resolve(m_in_atn_cb, *this);
97	97	m_in_srq_func.resolve(m_in_srq_cb, *this);
98
	98
99	99	m_out_ren_func.resolve(m_out_ren_cb, *this);
100	100	m_out_ifc_func.resolve(m_out_ifc_cb, *this);
101	101	m_out_ndac_func.resolve(m_out_ndac_cb, *this);

trunk/src/emu/machine/ds75161a.h
r18326	r18327
91	91	DECLARE_READ_LINE_MEMBER( eoi_r );
92	92	DECLARE_READ_LINE_MEMBER( atn_r );
93	93	DECLARE_READ_LINE_MEMBER( srq_r );
94
	94
95	95	DECLARE_WRITE_LINE_MEMBER( ren_w );
96	96	DECLARE_WRITE_LINE_MEMBER( ifc_w );
97	97	DECLARE_WRITE_LINE_MEMBER( ndac_w );

trunk/src/emu/sound/sn76496.c
r18326	r18327
104	104	frequency register, while the others have 0x400 as before. Should fix a bug
105	105	or two on sega games, particularly Vigilante on Sega Master System. Verified
106	106	on SMS hardware.
107
	107
108	108	27/06/2012: Michael Zapf
109	109	Converted to modern device, legacy devices were gradually removed afterwards.
110	110

trunk/src/emu/device.h
r18326	r18327
987	987	// query relative to the parent, if we have one
988	988	if (m_owner != NULL)
989	989	return m_owner->subdevice(tag);
990
	990
991	991	// otherwise, it's NULL unless the tag is absolute
992	992	return (tag[0] == ':') ? subdevice(tag) : NULL;
993	993	}

trunk/src/emu/cpu/tms0980/tms0980.c
r18326	r18327
269	269	const tms0980_config *config;
270	270	address_space *program;
271	271	address_space *data;
272
	272
273	273	devcb_resolved_read8 m_read_k;
274	274	devcb_resolved_write16 m_write_o;
275	275	devcb_resolved_write16 m_write_r;
r18326	r18327
509	509
510	510	cpustate->program = &device->space( AS_PROGRAM );
511	511	cpustate->data = &device->space( AS_PROGRAM );
512
	512
513	513	cpustate->m_read_k.resolve(cpustate->config->read_k, *device);
514	514	cpustate->m_write_o.resolve(cpustate->config->write_o, *device);
515	515	cpustate->m_write_r.resolve(cpustate->config->write_r, *device);

trunk/src/emu/devdelegate.c
r18326	r18327
42	42
43	43	//-------------------------------------------------
44	44	// bound_object - use the device name to locate
45		// a device relative to the given search root;
46		// fatal error if not found
	45	// a device relative to the given search root;
	46	// fatal error if not found
47	47	//-------------------------------------------------
48	48
49	49	delegate_late_bind &device_delegate_helper::bound_object(device_t &search_root)
r18326	r18327
57	57
58	58	//-------------------------------------------------
59	59	// safe_tag - return a tag string or (unknown) if
60		// the object is not valid
	60	// the object is not valid
61	61	//-------------------------------------------------
62	62
63	63	const char device_delegate_helper::safe_tag(device_t object)

trunk/src/emu/devdelegate.h
r18326	r18327
57	57	protected:
58	58	// constructor
59	59	device_delegate_helper(const char *devname) : m_device_name(devname) { }
60
	60
61	61	// internal helpers
62	62	delegate_late_bind &bound_object(device_t &search_root);
63	63	static const char safe_tag(device_t object);

trunk/src/emu/driver.c
r18326	r18327
42	42
43	43
44	44	//**************************************************************************
45		// ADDRESS_MAPS
	45	// ADDRESS_MAPS
46	46	//**************************************************************************
47	47
48	48	// default address map

trunk/src/emu/driver.h
r18326	r18327
166	166	// ======================> driver_device
167	167
168	168	// base class for machine driver-specific devices
169		class driver_device : public device_t,
	169	class driver_device : public device_t,
170	170	public device_memory_interface
171	171	{
172	172	public:
r18326	r18327
204	204
205	205	// dummy driver_init callbacks
206	206	void init_0() { }
207
	207
208	208	// memory helpers
209	209	address_space &generic_space() const { return space(AS_PROGRAM); }
210	210

trunk/src/mess/machine/a2arcadebd.c
r18326	r18327
3	3	a2arcadeboard.c
4	4
5	5	Implementation of the Third Millenium Engineering Arcade Board
6
	6
7	7	TODO:
8	8	- VDPTEST program seems to want more than 16K of RAM, but docs/ads/press releases say 16k, period
9	9	- MLDEMO program needs vsync IRQ from the TMS but doesn't program the registers the way our emulation
10	10	wants to enable IRQs
11
	11
12	12	*********************************************************************/
13	13
14	14	#include "emu.h"
r18326	r18327
120	120	case 1:
121	121	return m_tms->register_read(space, 0);
122	122
123		case 6:
	123	case 6:
124	124	return ay8910_r(m_ay, space, 0);
125	125	}
126	126
r18326	r18327
146	146	case 6:
147	147	ay8910_data_w(m_ay, space, 0, data);
148	148	break;
149		}
	149	}
150	150	}
151	151
152	152	WRITE_LINE_MEMBER( a2bus_arcboard_device::tms_irq_w )

trunk/src/mess/machine/amigakbd.h
r18326	r18327
7	7	//**************************************************************************
8	8
9	9	#define MCFG_AMIGA_KEYBOARD_ADD(_tag) \
10		MCFG_DEVICE_ADD(_tag, AMIGAKBD, 0)
	10	MCFG_DEVICE_ADD(_tag, AMIGAKBD, 0)
11	11
12	12
13	13
r18326	r18327
25	25
26	26	// optional information overrides
27	27	virtual ioport_constructor device_input_ports() const;
28
	28
29	29	DECLARE_INPUT_CHANGED_MEMBER( kbd_update );
30
	30
31	31	protected:
32	32	// device-level overrides
33	33	virtual void device_start();
34	34	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
35
	35
36	36	void kbd_sendscancode(UINT8 scancode );
37		private:
	37	private:
38	38	UINT8 *m_buf;
39	39	int m_buf_pos;
40	40	int m_cur_pos;
41		emu_timer *m_timer;
	41	emu_timer *m_timer;
42	42	};
43	43
44	44	// device type definition

trunk/src/mess/machine/kr2376.c
r18326	r18327
344	344	assert(device->tag() != NULL);
345	345
346	346	kr2376->intf = (const kr2376_interface*)device->static_config();
347
	347
348	348	assert(kr2376->intf != NULL);
349	349	assert(kr2376->intf->clock > 0);
350	350

trunk/src/mess/machine/cbm2_graphic.c
r18326	r18327
9	9
10	10	/*
11	11
12		TODO:
	12	TODO:
13	13
14		- version A (EF9365, 512x512 interlaced, 1 page)
15		- version B (EF9366, 512x256 non-interlaced, 2 pages)
	14	- version A (EF9365, 512x512 interlaced, 1 page)
	15	- version B (EF9366, 512x256 non-interlaced, 2 pages)
16	16
17	17	*/
18	18
r18326	r18327
41	41	// ef9345_interface gdp_intf
42	42	//-------------------------------------------------
43	43
44		static const ef9345_interface gdp_intf =
	44	static const ef9345_interface gdp_intf =
45	45	{
46	46	SCREEN_TAG
47	47	};
r18326	r18327
145	145	else if (offset == 0x7f90)
146	146	{
147	147	/*
148
149		bit description
150
151		0 light pen
152		1
153		2
154		3
155		4
156		5
157		6
158		7
159
160		*/
	148
	149	bit description
	150
	151	0 light pen
	152	1
	153	2
	154	3
	155	4
	156	5
	157	6
	158	7
	159
	160	*/
161	161	}
162	162	else if (offset == 0x7fb0)
163	163	{
r18326	r18327
184	184	if (offset == 0x7f80)
185	185	{
186	186	/*
187
188		bit description
189
190		0 hard copy (0=active)
191		1 operating page select (version B)
192		2
193		3 read-modify-write (1=active)
194		4 display switch (1=graphic)
195		5 display page select (version B)
196		6
197		7
198
199		*/
	187
	188	bit description
	189
	190	0 hard copy (0=active)
	191	1 operating page select (version B)
	192	2
	193	3 read-modify-write (1=active)
	194	4 display switch (1=graphic)
	195	5 display page select (version B)
	196	6
	197	7
	198
	199	*/
200	200	}
201	201	else if (offset >= 0x7ff0)
202	202	{

trunk/src/mess/machine/vtech2.c
r18326	r18327
146	146	write8_delegate(FUNC(vtech2_state::mwa_bank3), this),
147	147	write8_delegate(FUNC(vtech2_state::mwa_bank4), this),
148	148	};
149
	149
150	150	machine().device("maincpu")->memory().space(AS_PROGRAM).install_readwrite_handler(offset * 0x4000, offset * 0x4000 + 0x3fff, mra_bank_soft[offset], mwa_bank_soft[offset]);
151	151	}
152	152	else

trunk/src/mess/machine/bebox.c
r18326	r18327
227	227	}
228	228
229	229	WRITE64_MEMBER(bebox_state::bebox_cpu1_imask_w )
230		{
	230	{
231	231	UINT32 old_imask = m_cpu_imask[1];
232	232
233	233	bebox_mbreg32_w(&m_cpu_imask[1], data, mem_mask);
r18326	r18327
610	610	/*
611	611	static READ64_MEMBER(bebox_state::bebox_video_r )
612	612	{
613		UINT64 result = 0;
614		mem_mask = FLIPENDIAN_INT64(mem_mask);
615		if (ACCESSING_BITS_0_7)
616		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 0, mem_mask >> 0) << 0;
617		if (ACCESSING_BITS_8_15)
618		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 1, mem_mask >> 8) << 8;
619		if (ACCESSING_BITS_16_23)
620		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 2, mem_mask >> 16) << 16;
621		if (ACCESSING_BITS_24_31)
622		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 3, mem_mask >> 24) << 24;
623		if (ACCESSING_BITS_32_39)
624		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 4, mem_mask >> 32) << 32;
625		if (ACCESSING_BITS_40_47)
626		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 5, mem_mask >> 40) << 40;
627		if (ACCESSING_BITS_48_55)
628		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 6, mem_mask >> 48) << 48;
629		if (ACCESSING_BITS_56_63)
630		result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 7, mem_mask >> 56) << 56;
631		return FLIPENDIAN_INT64(result);
	613	UINT64 result = 0;
	614	mem_mask = FLIPENDIAN_INT64(mem_mask);
	615	if (ACCESSING_BITS_0_7)
	616	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 0, mem_mask >> 0) << 0;
	617	if (ACCESSING_BITS_8_15)
	618	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 1, mem_mask >> 8) << 8;
	619	if (ACCESSING_BITS_16_23)
	620	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 2, mem_mask >> 16) << 16;
	621	if (ACCESSING_BITS_24_31)
	622	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 3, mem_mask >> 24) << 24;
	623	if (ACCESSING_BITS_32_39)
	624	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 4, mem_mask >> 32) << 32;
	625	if (ACCESSING_BITS_40_47)
	626	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 5, mem_mask >> 40) << 40;
	627	if (ACCESSING_BITS_48_55)
	628	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 6, mem_mask >> 48) << 48;
	629	if (ACCESSING_BITS_56_63)
	630	result \|= (UINT64)vga_mem_linear_r(space, offset * 8 + 7, mem_mask >> 56) << 56;
	631	return FLIPENDIAN_INT64(result);
632	632	}
633	633
634	634
635	635	static WRITE64_MEMBER(bebox_state::bebox_video_w )
636	636	{
637		data = FLIPENDIAN_INT64(data);
638		mem_mask = FLIPENDIAN_INT64(mem_mask);
639		if (ACCESSING_BITS_0_7)
640		vga_mem_linear_w(space, offset * 8 + 0, data >> 0 , mem_mask >> 0);
641		if (ACCESSING_BITS_8_15)
642		vga_mem_linear_w(space, offset * 8 + 1, data >> 8 , mem_mask >> 8);
643		if (ACCESSING_BITS_16_23)
644		vga_mem_linear_w(space, offset * 8 + 2, data >> 16, mem_mask >> 16);
645		if (ACCESSING_BITS_24_31)
646		vga_mem_linear_w(space, offset * 8 + 3, data >> 24, mem_mask >> 24);
647		if (ACCESSING_BITS_32_39)
648		vga_mem_linear_w(space, offset * 8 + 4, data >> 32, mem_mask >> 32);
649		if (ACCESSING_BITS_40_47)
650		vga_mem_linear_w(space, offset * 8 + 5, data >> 40, mem_mask >> 40);
651		if (ACCESSING_BITS_48_55)
652		vga_mem_linear_w(space, offset * 8 + 6, data >> 48, mem_mask >> 48);
653		if (ACCESSING_BITS_56_63)
654		vga_mem_linear_w(space, offset * 8 + 7, data >> 56, mem_mask >> 56);
	637	data = FLIPENDIAN_INT64(data);
	638	mem_mask = FLIPENDIAN_INT64(mem_mask);
	639	if (ACCESSING_BITS_0_7)
	640	vga_mem_linear_w(space, offset * 8 + 0, data >> 0 , mem_mask >> 0);
	641	if (ACCESSING_BITS_8_15)
	642	vga_mem_linear_w(space, offset * 8 + 1, data >> 8 , mem_mask >> 8);
	643	if (ACCESSING_BITS_16_23)
	644	vga_mem_linear_w(space, offset * 8 + 2, data >> 16, mem_mask >> 16);
	645	if (ACCESSING_BITS_24_31)
	646	vga_mem_linear_w(space, offset * 8 + 3, data >> 24, mem_mask >> 24);
	647	if (ACCESSING_BITS_32_39)
	648	vga_mem_linear_w(space, offset * 8 + 4, data >> 32, mem_mask >> 32);
	649	if (ACCESSING_BITS_40_47)
	650	vga_mem_linear_w(space, offset * 8 + 5, data >> 40, mem_mask >> 40);
	651	if (ACCESSING_BITS_48_55)
	652	vga_mem_linear_w(space, offset * 8 + 6, data >> 48, mem_mask >> 48);
	653	if (ACCESSING_BITS_56_63)
	654	vga_mem_linear_w(space, offset * 8 + 7, data >> 56, mem_mask >> 56);
655	655	}
656	656	*/
657	657	/*************************************
r18326	r18327
662	662
663	663
664	664	READ8_MEMBER(bebox_state::bebox_page_r)
665		{
	665	{
666	666	UINT8 data = m_at_pages[offset % 0x10];
667	667
668	668	switch(offset % 8)
r18326	r18327
685	685
686	686
687	687	WRITE8_MEMBER(bebox_state::bebox_page_w)
688		{
	688	{
689	689	m_at_pages[offset % 0x10] = data;
690	690
691	691	switch(offset % 8)
r18326	r18327
711	711
712	712
713	713	WRITE8_MEMBER(bebox_state::bebox_80000480_w)
714		{
	714	{
715	715	switch(offset % 8)
716	716	{
717	717	case 1:
r18326	r18327
910	910
911	911
912	912	READ64_MEMBER(bebox_state::scsi53c810_r )
913		{
	913	{
914	914	int reg = offset*8;
915	915	UINT64 r = 0;
916	916	if (!(mem_mask & U64(0xff00000000000000))) {
r18326	r18327
943	943
944	944
945	945	WRITE64_MEMBER(bebox_state::scsi53c810_w )
946		{
	946	{
947	947	int reg = offset*8;
948	948	if (!(mem_mask & U64(0xff00000000000000))) {
949	949	m_lsi53c810->lsi53c810_reg_w(reg+0, data >> 56);

trunk/src/mess/machine/msx.c
r18326	r18327
119	119	{ "SUPERLODE", SLOT_SUPERLODERUNNER },
120	120	{ "MAJUTSUSHI", SLOT_MAJUTSUSHI },
121	121	};
122
	122
123	123	for (int i = 0; i < ARRAY_LENGTH(mapper_types) && type < 0; i++)
124	124	{
125	125	if (!mame_stricmp(mapper, mapper_types[i].mapper_name))

trunk/src/mess/machine/pc.c
r18326	r18327
924	924	key \|= machine().root_device().ioport("Y10")->read();
925	925	key \|= machine().root_device().ioport("Y11")->read();
926	926	key \|= machine().root_device().ioport("Y12")->read();
927		// DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, mc1502_keyb.pulsing,
928		// (key \|\| mc1502_keyb.pulsing) ? " will IRQ" : ""));
	927	// DBG_LOG(1,"mc1502_k_s_c",("= %02X (%d) %s\n", key, mc1502_keyb.pulsing,
	928	// (key \|\| mc1502_keyb.pulsing) ? " will IRQ" : ""));
929	929
930	930	/*
931	931	If a key is pressed and we're not pulsing yet, start pulsing the IRQ1;
r18326	r18327
946	946
947	947	READ8_MEMBER(pc_state::mc1502_ppi_porta_r)
948	948	{
949		// DBG_LOG(1,"mc1502_ppi_porta_r",("= %02X\n", mc1502_keyb.latch));
	949	// DBG_LOG(1,"mc1502_ppi_porta_r",("= %02X\n", mc1502_keyb.latch));
950	950	return mc1502_keyb.latch;
951	951	}
952	952
953	953	WRITE8_MEMBER(pc_state::mc1502_ppi_porta_w)
954	954	{
955		// DBG_LOG(1,"mc1502_ppi_porta_w",("( %02X )\n", data));
	955	// DBG_LOG(1,"mc1502_ppi_porta_w",("( %02X )\n", data));
956	956	mc1502_keyb.latch = data;
957	957	if (mc1502_keyb.pulsing)
958	958	mc1502_keyb.pulsing--;
r18326	r18327
961	961
962	962	WRITE8_MEMBER(pc_state::mc1502_ppi_portb_w)
963	963	{
964		// DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
	964	// DBG_LOG(2,"mc1502_ppi_portb_w",("( %02X )\n", data));
965	965	m_ppi_portb = data;
966	966	pit8253_gate2_w(machine().device("pit8253"), BIT(data, 0));
967	967	pc_speaker_set_spkrdata( machine(), data & 0x02 );
r18326	r18327
981	981	// 0x10 -- SNDOUT
982	982	data = ( data & ~0x10 ) \| ( (BIT(m_ppi_portb, 1) && timer2_output) ? 0x10 : 0x00 );
983	983
984		// DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
985		// data, tap_val, timer2_output, machine().describe_context()));
	984	// DBG_LOG(2,"mc1502_ppi_portc_r",("= %02X (tap_val %f t2out %d) at %s\n",
	985	// data, tap_val, timer2_output, machine().describe_context()));
986	986	return data;
987	987	}
988	988
r18326	r18327
1003	1003	if (mc1502_keyb.mask & 0x0400) { key \|= machine().root_device().ioport("Y11")->read(); }
1004	1004	if (mc1502_keyb.mask & 0x0800) { key \|= machine().root_device().ioport("Y12")->read(); }
1005	1005	key ^= 0xff;
1006		// DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
	1006	// DBG_LOG(2,"mc1502_kppi_porta_r",("= %02X\n", key));
1007	1007	return key;
1008	1008	}
1009	1009
r18326	r18327
1015	1015	mc1502_keyb.mask \|= 1 << 11;
1016	1016	else
1017	1017	mc1502_keyb.mask &= ~(1 << 11);
1018		// DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
	1018	// DBG_LOG(2,"mc1502_kppi_portb_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
1019	1019	}
1020	1020
1021	1021	WRITE8_MEMBER(pc_state::mc1502_kppi_portc_w)
1022	1022	{
1023	1023	mc1502_keyb.mask &= ~(7 << 8);
1024	1024	mc1502_keyb.mask \|= ((data ^ 7) & 7) << 8;
1025		// DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
	1025	// DBG_LOG(2,"mc1502_kppi_portc_w",("( %02X -> %04X )\n", data, mc1502_keyb.mask));
1026	1026	}
1027	1027
1028	1028

trunk/src/mess/machine/rx01.c
r18326	r18327
176	176
177	177	void rx01_device::data_write(UINT16 data)
178	178	{
179		// printf("data_write %04x\n",data);
	179	// printf("data_write %04x\n",data);
180	180	// data can be written only if TR is set
181	181	if (BIT(m_rxcs,7)) m_rxdb = data;
182	182	machine().scheduler().timer_set(attotime::from_msec(100), FUNC(command_execution_callback), 0, this);
r18326	r18327
185	185	UINT16 rx01_device::data_read()
186	186	{
187	187	if (m_state==RX01_EMPTY && BIT(m_rxcs,7)) m_rxcs &= (1<<7); // clear TR bit;
188		// printf("data_read %04x\n",m_rxdb);
	188	// printf("data_read %04x\n",m_rxdb);
189	189	return m_rxdb;
190	190	}
191	191

trunk/src/mess/includes/vtech2.h
r18326	r18327
56	56	DECLARE_MACHINE_RESET(laser700);
57	57	UINT32 screen_update_laser(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
58	58	INTERRUPT_GEN_MEMBER(vtech2_interrupt);
59
	59
60	60	int mra_bank(int bank, int offs);
61	61	void mwa_bank(int bank, int offs, int data);
62
	62
63	63	DECLARE_WRITE8_MEMBER(mwa_bank1);
64	64	DECLARE_WRITE8_MEMBER(mwa_bank2);
65	65	DECLARE_WRITE8_MEMBER(mwa_bank3);
66	66	DECLARE_WRITE8_MEMBER(mwa_bank4);
67	67	DECLARE_READ8_MEMBER(mra_bank1);
68		DECLARE_READ8_MEMBER(mra_bank2);
	68	DECLARE_READ8_MEMBER(mra_bank2);
69	69	DECLARE_READ8_MEMBER(mra_bank3);
70		DECLARE_READ8_MEMBER(mra_bank4);
	70	DECLARE_READ8_MEMBER(mra_bank4);
71	71	};
72	72
73	73

trunk/src/mess/includes/concept.h
r18326	r18327
54	54	virtual void video_start();
55	55	UINT32 screen_update_concept(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
56	56	INTERRUPT_GEN_MEMBER(concept_interrupt);
57
	57
58	58	void install_expansion_slot(int slot,
59	59	read8_delegate reg_read, write8_delegate reg_write,
60	60	read8_delegate rom_read, write8_delegate rom_write);
61
	61
62	62	void concept_fdc_init(int slot);
63	63	void concept_hdc_init(int slot);
64	64
r18326	r18327
68	68
69	69	DECLARE_READ8_MEMBER(concept_hdc_reg_r);
70	70	DECLARE_WRITE8_MEMBER(concept_hdc_reg_w);
71		DECLARE_READ8_MEMBER(concept_hdc_rom_r);
	71	DECLARE_READ8_MEMBER(concept_hdc_rom_r);
72	72	DECLARE_READ8_MEMBER(via_in_a);
73	73	DECLARE_WRITE8_MEMBER(via_out_a);
74	74	DECLARE_READ8_MEMBER(via_in_b);

trunk/src/mess/includes/kramermc.h
r18326	r18327
19	19	DECLARE_DRIVER_INIT(kramermc);
20	20	virtual void machine_reset();
21	21	virtual void video_start();
22		UINT32 screen_update_kramermc(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	22	UINT32 screen_update_kramermc(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
23	23	DECLARE_READ8_MEMBER(kramermc_port_a_r);
24	24	DECLARE_READ8_MEMBER(kramermc_port_b_r);
25	25	DECLARE_WRITE8_MEMBER(kramermc_port_a_w);

trunk/src/mess/includes/cbm2.h
r18326	r18327
100	100	DECLARE_MACHINE_START( cbm2_pal );
101	101	DECLARE_MACHINE_RESET( cbm2 );
102	102
103		virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	103	virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
104	104	int casseg1, int casseg2, int casseg3, int casseg4, int rasseg1, int rasseg2, int rasseg3, int rasseg4);
105	105
106	106	void bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int sysioen, int dramen,
107		int casseg1, int casseg2, int casseg3, int casseg4, int buframcs, int extbufcs, int *vidramcs,
	107	int casseg1, int casseg2, int casseg3, int casseg4, int buframcs, int extbufcs, int *vidramcs,
108	108	int diskromcs, int csbank1, int csbank2, int csbank3, int basiccs, int knbcs, int *kernalcs,
109	109	int crtccs, int cs1, int sidcs, int extprtcs, int ciacs, int aciacs, int tript1cs, int tript2cs);
110	110
r18326	r18327
172	172	: cbm2_state(mconfig, type, tag)
173	173	{ }
174	174
175		virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	175	virtual void read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
176	176	int casseg1, int casseg2, int casseg3, int casseg4, int rasseg1, int rasseg2, int rasseg3, int rasseg4);
177	177
178	178	DECLARE_READ8_MEMBER( tpi2_pc_r );
r18326	r18327
203	203
204	204	void read_pla1(offs_t offset, int bras, int busy2, int sphi2, int clrnibcsb, int procvid, int refen, int ba, int aec, int srw,
205	205	int datxen, int dramxen, int clrniben, int segf, int _64kcasen, int casenb, int viddaten, int viddat_tr);
206
	206
207	207	void read_pla2(offs_t offset, offs_t va, int ba, int sphi2, int vicen, int ae, int segf, int bcas, int bank0,
208	208	int clrnibcsb, int extbufcs, int discromcs, int buframcs, int charomcs, int procvid, int viccs, int vidmatcs);
209	209
r18326	r18327
212	212	int clrnibcs, int extbufcs, int discromcs, int buframcs, int charomcs, int viccs, int *vidmatcs,
213	213	int csbank1, int csbank2, int csbank3, int basiclocs, int basichics, int kernalcs,
214	214	int cs1, int sidcs, int extprtcs, int ciacs, int aciacs, int tript1cs, int tript2cs, int aec, int *vsysaden);
215
	215
216	216	UINT8 read_memory(address_space &space, offs_t offset, offs_t va, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas, UINT8 *clrnib);
217	217	void write_memory(address_space &space, offs_t offset, UINT8 data, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas);
218	218

trunk/src/mess/includes/atarist.h
r18326	r18327
333	333
334	334	TIMER_CALLBACK_MEMBER(atariste_dmasound_tick);
335	335	TIMER_CALLBACK_MEMBER(atariste_microwire_tick);
336
	336
337	337	void dmasound_set_state(int level);
338	338	void dmasound_tick();
339	339	void microwire_shift();

trunk/src/mess/includes/fmtowns.h
r18326	r18327
252	252	void poll_keyboard();
253	253	void mouse_timeout();
254	254	void wait_end();
255		public:
	255	public:
256	256	INTERRUPT_GEN_MEMBER(towns_vsync_irq);
257	257	TIMER_CALLBACK_MEMBER(towns_cd_status_ready);
258	258	TIMER_CALLBACK_MEMBER(towns_cdrom_read_byte);

trunk/src/mess/includes/x68k.h
r18326	r18327
297	297	DECLARE_WRITE_LINE_MEMBER(mfp_irq_callback);
298	298	DECLARE_WRITE_LINE_MEMBER(x68k_scsi_irq);
299	299	DECLARE_WRITE_LINE_MEMBER(x68k_scsi_drq);
300
	300
301	301	void mfp_init();
302	302	void x68k_keyboard_ctrl_w(int data);
303	303	int x68k_keyboard_pop_scancode();
r18326	r18327
308	308	void md_6button_init();
309	309	UINT8 md_6button_r(int port);
310	310	UINT8 xpd1lr_r(int port);
311
	311
312	312	DECLARE_WRITE_LINE_MEMBER(x68k_fm_irq);
313	313	DECLARE_WRITE_LINE_MEMBER(x68k_irq2_line);
314	314
r18326	r18327
345	345	DECLARE_READ16_MEMBER(x68k_exp_r);
346	346	DECLARE_WRITE16_MEMBER(x68k_exp_w);
347	347	DECLARE_READ16_MEMBER(x68k_scc_r);
348
	348
349	349	DECLARE_READ16_MEMBER(x68k_spritereg_r);
350	350	DECLARE_WRITE16_MEMBER(x68k_spritereg_w);
351	351	DECLARE_READ16_MEMBER(x68k_spriteram_r);
r18326	r18327
367	367	void x68k_draw_text(bitmap_ind16 &bitmap, int xscr, int yscr, rectangle rect);
368	368	void x68k_draw_gfx_scanline(bitmap_ind16 &bitmap, rectangle cliprect, UINT8 priority);
369	369	void x68k_draw_gfx(bitmap_ind16 &bitmap,rectangle cliprect);
370		void x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect);
	370	void x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect);
371	371	};
372	372
373	373

trunk/src/mess/includes/comquest.h
r18326	r18327
24	24	DECLARE_WRITE8_MEMBER(comquest_write);
25	25	virtual void machine_reset();
26	26	virtual void video_start();
27		UINT32 screen_update_comquest(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	27	UINT32 screen_update_comquest(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
28	28	};
29	29
30	30	#endif /* COMQUEST_H_ */

trunk/src/mess/includes/dccons.h
r18326	r18327
8	8	DECLARE_DRIVER_INIT(dc);
9	9	DECLARE_DRIVER_INIT(dcus);
10	10	DECLARE_DRIVER_INIT(dcjp);
11
	11
12	12	DECLARE_READ64_MEMBER(dcus_idle_skip_r);
13	13	DECLARE_READ64_MEMBER(dcjp_idle_skip_r);
14
	14
15	15	DECLARE_MACHINE_RESET(dc_console);
16	16	DECLARE_READ64_MEMBER(dc_pdtra_r);
17	17	DECLARE_WRITE64_MEMBER(dc_pdtra_w);
18	18	DECLARE_READ64_MEMBER(dc_arm_r);
19	19	DECLARE_WRITE64_MEMBER(dc_arm_w);
20	20	DECLARE_WRITE64_MEMBER(ta_texture_directpath0_w);
21		DECLARE_WRITE64_MEMBER(ta_texture_directpath1_w);
22		private:
	21	DECLARE_WRITE64_MEMBER(ta_texture_directpath1_w);
	22	private:
23	23	UINT64 PDTRA, PCTRA;
24
	24
25	25	};

trunk/src/mess/video/isa_svga_cirrus.c
r18326	r18327
26	26	MCFG_SCREEN_UPDATE_DEVICE("vga", cirrus_vga_device, screen_update)
27	27
28	28	MCFG_PALETTE_LENGTH(0x100)
29
	29
30	30	MCFG_DEVICE_ADD("vga", CIRRUS_VGA, 0)
31	31	MACHINE_CONFIG_END
32	32
r18326	r18327
74	74	set_isa_device();
75	75
76	76	m_vga = subdevice<cirrus_vga_device>("vga");
77
	77
78	78	m_isa->install_rom(this, 0xc0000, 0xc7fff, 0, 0, "svga", "dm_clgd5430");
79	79
80	80	m_isa->install_device(0x03b0, 0x03bf, 0, 0, read8_delegate(FUNC(cirrus_vga_device::port_03b0_r),m_vga), write8_delegate(FUNC(cirrus_vga_device::port_03b0_w),m_vga));

trunk/src/mess/video/isa_svga_cirrus.h
r18326	r18327
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26	26	virtual const rom_entry *device_rom_region() const;
27
	27
28	28	DECLARE_READ8_MEMBER(input_port_0_r);
29	29	protected:
30	30	// device-level overrides
31	31	virtual void device_start();
32	32	virtual void device_reset();
33		private:
34		cirrus_vga_device *m_vga;
	33	private:
	34	cirrus_vga_device *m_vga;
35	35	};
36	36
37	37

trunk/src/mess/video/isa_svga_tseng.c
r18326	r18327
26	26	MCFG_SCREEN_UPDATE_DEVICE("vga", tseng_vga_device, screen_update)
27	27
28	28	MCFG_PALETTE_LENGTH(0x100)
29
	29
30	30	MCFG_DEVICE_ADD("vga", TSENG_VGA, 0)
31	31	MACHINE_CONFIG_END
32	32
r18326	r18327
74	74	set_isa_device();
75	75
76	76	m_vga = subdevice<tseng_vga_device>("vga");
77
	77
78	78	m_isa->install_rom(this, 0xc0000, 0xc7fff, 0, 0, "et4000", "et4000");
79	79
80	80	m_isa->install_device(0x3b0, 0x3bf, 0, 0, read8_delegate(FUNC(tseng_vga_device::port_03b0_r),m_vga), write8_delegate(FUNC(tseng_vga_device::port_03b0_w),m_vga));

trunk/src/mess/video/isa_svga_tseng.h
r18326	r18327
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26	26	virtual const rom_entry *device_rom_region() const;
27
	27
28	28	DECLARE_READ8_MEMBER(input_port_0_r);
29	29	protected:
30	30	// device-level overrides
31	31	virtual void device_start();
32	32	virtual void device_reset();
33		private:
	33	private:
34	34	tseng_vga_device *m_vga;
35	35	};
36	36

trunk/src/mess/video/isa_svga_s3.c
r18326	r18327
27	27	MCFG_SCREEN_UPDATE_DEVICE("vga", s3_vga_device, screen_update)
28	28
29	29	MCFG_PALETTE_LENGTH(0x100)
30
	30
31	31	MCFG_DEVICE_ADD("vga", S3_VGA, 0)
32	32	MACHINE_CONFIG_END
33	33

trunk/src/mess/video/isa_svga_s3.h
r18326	r18327
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26	26	virtual const rom_entry *device_rom_region() const;
27
	27
28	28	DECLARE_READ8_MEMBER(input_port_0_r);
29	29	protected:
30	30	// device-level overrides
31	31	virtual void device_start();
32	32	virtual void device_reset();
33		private:
	33	private:
34	34	s3_vga_device *m_vga;
35	35	ibm8514a_device *m_8514;
36	36	};

trunk/src/mess/video/isa_vga_ati.c
r18326	r18327
29	29	MCFG_SCREEN_UPDATE_DEVICE("vga", ati_vga_device, screen_update)
30	30
31	31	MCFG_PALETTE_LENGTH(0x100)
32
	32
33	33	MCFG_DEVICE_ADD("vga", ATI_VGA, 0)
34	34	MACHINE_CONFIG_END
35	35
r18326	r18327
78	78
79	79	m_vga = subdevice<ati_vga_device>("vga");
80	80	m_8514 = subdevice<mach8_device>("vga:8514a");
81
	81
82	82	m_isa->install_rom(this, 0xc0000, 0xc7fff, 0, 0, "vga", "gfxultra");
83	83
84	84	m_isa->install_device(0x1ce, 0x1cf, 0, 0, read8_delegate(FUNC(ati_vga_device::ati_port_ext_r),m_vga), write8_delegate(FUNC(ati_vga_device::ati_port_ext_w),m_vga));

trunk/src/mess/video/isa_vga_ati.h
r18326	r18327
31	31	// optional information overrides
32	32	virtual machine_config_constructor device_mconfig_additions() const;
33	33	virtual const rom_entry *device_rom_region() const;
34
	34
35	35	DECLARE_READ8_MEMBER(input_port_0_r);
36	36	protected:
37	37	// device-level overrides
38	38	virtual void device_start();
39	39	virtual void device_reset();
40		private:
	40	private:
41	41	ati_vga_device *m_vga;
42	42	mach8_device *m_8514;
43	43	};

trunk/src/mess/video/nubus_vikbw.h
r18326	r18327
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26	26	virtual const rom_entry *device_rom_region() const;
27
	27
28	28	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
29	29	protected:
30	30	// device-level overrides

trunk/src/mess/video/isa_vga.c
r18326	r18327
62	62	void isa8_vga_device::device_start()
63	63	{
64	64	set_isa_device();
65
	65
66	66	m_vga = subdevice<vga_device>("vga");
67	67
68	68	m_isa->install_rom(this, 0xc0000, 0xc7fff, 0, 0, "ibm_vga", "ibm_vga");

trunk/src/mess/video/isa_vga.h
r18326	r18327
24	24	// optional information overrides
25	25	virtual machine_config_constructor device_mconfig_additions() const;
26	26	virtual const rom_entry *device_rom_region() const;
27
	27
28	28	DECLARE_READ8_MEMBER(input_port_0_r);
29	29	protected:
30	30	// device-level overrides

trunk/src/mess/drivers/xerox820.c
r18326	r18327
559	559
560	560	WRITE_LINE_MEMBER(xerox820_state::ctc_z0_w)
561	561	{
562		// device_t *device = machine().device(Z80CTC_TAG);
	562	// device_t *device = machine().device(Z80CTC_TAG);
563	563	// z80ctc_trg1_w(device, state);
564	564	}
565	565
566	566	WRITE_LINE_MEMBER(xerox820_state::ctc_z2_w)
567	567	{
568		// device_t *device = machine().device(Z80CTC_TAG);
	568	// device_t *device = machine().device(Z80CTC_TAG);
569	569
570	570	// z80ctc_trg3_w(device, state);
571	571	}

trunk/src/mess/drivers/n64.c
r18326	r18327
18	18	{
19	19	public:
20	20	n64_mess_state(const machine_config &mconfig, device_type type, const char *tag)
21		: n64_state(mconfig, type, tag)
	21	: n64_state(mconfig, type, tag)
22	22	{ }
23	23
24	24	DECLARE_READ32_MEMBER(dd_null_r);

trunk/src/mess/drivers/jr100.c
r18326	r18327
265	265	DEVCB_NULL, /* in_ca2_func */
266	266	DEVCB_NULL, /* in_cb2_func */
267	267	DEVCB_DRIVER_MEMBER(jr100_state,jr100_via_write_a), /* out_a_func */
268		DEVCB_DRIVER_MEMBER(jr100_state,jr100_via_write_b), /* out_b_func */
	268	DEVCB_DRIVER_MEMBER(jr100_state,jr100_via_write_b), /* out_b_func */
269	269	DEVCB_NULL, /* out_ca1_func */
270	270	DEVCB_NULL, /* out_cb1_func */
271	271	DEVCB_NULL, /* out_ca2_func */
272		DEVCB_DRIVER_LINE_MEMBER(jr100_state, jr100_via_write_cb2), /* out_cb2_func */
	272	DEVCB_DRIVER_LINE_MEMBER(jr100_state, jr100_via_write_cb2), /* out_cb2_func */
273	273	DEVCB_NULL /* irq_func */
274	274	};
275	275	static const cassette_interface jr100_cassette_interface =

trunk/src/mess/drivers/tm990189.c
r18326	r18327
144	144	DECLARE_MACHINE_RESET(tm990_189);
145	145	DECLARE_MACHINE_START(tm990_189_v);
146	146	DECLARE_MACHINE_RESET(tm990_189_v);
147
	147
148	148	TIMER_DEVICE_CALLBACK_MEMBER(display_callback);
149	149	TIMER_CALLBACK_MEMBER(clear_load);
150	150	void hold_load();

trunk/src/mess/drivers/x68k.c
r18326	r18327
436	436	}
437	437
438	438	void x68k_state::x68k_keyboard_push_scancode(unsigned char code)
439		{
	439	{
440	440	m_keyboard.keynum++;
441	441	if(m_keyboard.keynum >= 1)
442	442	{ // keyboard buffer full

trunk/src/mess/drivers/astrocde.c
r18326	r18327
17	17	{
18	18	public:
19	19	astrocde_mess_state(const machine_config &mconfig, device_type type, const char *tag)
20		: astrocde_state(mconfig, type, tag)
	20	: astrocde_state(mconfig, type, tag)
21	21	{ }
22	22
23	23	void get_ram_expansion_settings(int &ram_expansion_installed, int &write_protect_on, int &expansion_ram_start, int &expansion_ram_end, int &shadow_ram_end);

trunk/src/mess/drivers/test_t400.c
r18326	r18327
21	21
22	22	WRITE8_MEMBER( t400_test_suite_state::port_l_w )
23	23	{
24		// printf("L: %u\n", data);
	24	// printf("L: %u\n", data);
25	25	}
26	26
27	27	static ADDRESS_MAP_START( cop_io, AS_IO, 8, t400_test_suite_state )

trunk/src/mess/drivers/c64.c
r18326	r18327
422	422	READ8_MEMBER( c64_state::sid_potx_r )
423	423	{
424	424	UINT8 cia1_pa = m_cia1->pa_r();
425
	425
426	426	int sela = BIT(cia1_pa, 6);
427	427	int selb = BIT(cia1_pa, 7);
428	428
r18326	r18327
437	437	READ8_MEMBER( c64_state::sid_poty_r )
438	438	{
439	439	UINT8 cia1_pa = m_cia1->pa_r();
440
	440
441	441	int sela = BIT(cia1_pa, 6);
442	442	int selb = BIT(cia1_pa, 7);
443	443

trunk/src/mess/drivers/indiana.c
r18326	r18327
37	37	AM_RANGE(0x7f6003b0, 0x7f6003bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
38	38	AM_RANGE(0x7f6003c0, 0x7f6003cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
39	39	AM_RANGE(0x7f6003d0, 0x7f6003df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
40		AM_RANGE(0x7f7a0000, 0x7f7bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
41		AM_RANGE(0x80000000, 0x803fffff) AM_MIRROR(0x7fc00000) AM_RAM // 4 MB RAM
	40	AM_RANGE(0x7f7a0000, 0x7f7bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
	41	AM_RANGE(0x80000000, 0x803fffff) AM_MIRROR(0x7fc00000) AM_RAM // 4 MB RAM
42	42	ADDRESS_MAP_END
43	43
44	44

trunk/src/mess/drivers/pv9234.c
r18326	r18327
79	79	{
80	80	j = (data & 0xff000000) >> 24;
81	81	data <<= 8;
82		// printf("%c",j); // this prints 'OFF' to the console.
	82	// printf("%c",j); // this prints 'OFF' to the console.
83	83	logerror("debug1=%02x %c\n",j,j);
84	84	}
85		// printf("\n");
	85	// printf("\n");
86	86	}
87	87	}
88	88

trunk/src/mess/drivers/ami1200.c
r18326	r18327
326	326	MCFG_FLOPPY_DRIVE_ADD("fd1", amiga_floppies, 0, 0, amiga_fdc::floppy_formats)
327	327	MCFG_FLOPPY_DRIVE_ADD("fd2", amiga_floppies, 0, 0, amiga_fdc::floppy_formats)
328	328	MCFG_FLOPPY_DRIVE_ADD("fd3", amiga_floppies, 0, 0, amiga_fdc::floppy_formats)
329
	329
330	330	MCFG_AMIGA_KEYBOARD_ADD("kbd")
331	331	MACHINE_CONFIG_END
332	332

trunk/src/mess/drivers/korgm1.c
r18326	r18327
1	1	/***************************************************************************
2	2
3		Korg M1 (c) 1988
	3	Korg M1 (c) 1988
4	4
5		skeleton driver
	5	skeleton driver
6	6
7		Note: driver isn't yet hooked up to mess.lst / mess.mak, until a ROM
8		dump is found.
	7	Note: driver isn't yet hooked up to mess.lst / mess.mak, until a ROM
	8	dump is found.
9	9
10	10	***************************************************************************/
11	11
r18326	r18327
51	51
52	52	static ADDRESS_MAP_START( korgm1_map, AS_PROGRAM, 16, korgm1_state )
53	53	AM_RANGE(0x00000, 0x0ffff) AM_RAM // 64 KB
54		// AM_RANGE(0x50000, 0x57fff) AM_RAM // memory card 32 KB
	54	// AM_RANGE(0x50000, 0x57fff) AM_RAM // memory card 32 KB
55	55	AM_RANGE(0xe0000, 0xfffff) AM_ROM AM_REGION("ipl", 0)
56	56	ADDRESS_MAP_END
57	57
58	58	static ADDRESS_MAP_START( korgm1_io, AS_IO, 16, korgm1_state )
59		// AM_RANGE(0x0000, 0x00ff) internal peripheral (?)
60		// AM_RANGE(0x0100, 0x01ff) VDF 1 (MB87404)
61		// AM_RANGE(0x0200, 0x02ff) VDF 2 (MB87404)
62		// AM_RANGE(0x0500, 0x0503) MDE (MB87405)
63		// AM_RANGE(0x0600, 0x0601) OPZ 1 (8-bit port)
64		// AM_RANGE(0x0700, 0x0701) OPZ 2 (8-bit port)
65		// AM_RANGE(0x0800, 0x0801) SCAN (8-bit port) (keyboard)
66		// AM_RANGE(0x0900, 0x09??) A/D Converter (M58990P, Joystick, "value" and After Touch routes here) **
67		// AM_RANGE(0x0a00, 0x0a03) PPI (CXD1095, presumably i8255 compatible, LCD, LED and SW routes here) *
68		// AM_RANGE(0x0b00, 0x0b01) LCDC (8-bit port)
69		// AM_RANGE(0x1000, 0x11ff) TG (MB87402)
70		// AM_RANGE(0x2000, 0x23ff) SCSI
71		// AM_RANGE(0x3000, 0x33ff) FDC
	59	// AM_RANGE(0x0000, 0x00ff) internal peripheral (?)
	60	// AM_RANGE(0x0100, 0x01ff) VDF 1 (MB87404)
	61	// AM_RANGE(0x0200, 0x02ff) VDF 2 (MB87404)
	62	// AM_RANGE(0x0500, 0x0503) MDE (MB87405)
	63	// AM_RANGE(0x0600, 0x0601) OPZ 1 (8-bit port)
	64	// AM_RANGE(0x0700, 0x0701) OPZ 2 (8-bit port)
	65	// AM_RANGE(0x0800, 0x0801) SCAN (8-bit port) (keyboard)
	66	// AM_RANGE(0x0900, 0x09??) A/D Converter (M58990P, Joystick, "value" and After Touch routes here) **
	67	// AM_RANGE(0x0a00, 0x0a03) PPI (CXD1095, presumably i8255 compatible, LCD, LED and SW routes here) *
	68	// AM_RANGE(0x0b00, 0x0b01) LCDC (8-bit port)
	69	// AM_RANGE(0x1000, 0x11ff) TG (MB87402)
	70	// AM_RANGE(0x2000, 0x23ff) SCSI
	71	// AM_RANGE(0x3000, 0x33ff) FDC
72	72	// TG 2?
73	73	ADDRESS_MAP_END
74	74
r18326	r18327
145	145	#endif
146	146
147	147	static GFXDECODE_START( korgm1 )
148		// GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
	148	// GFXDECODE_ENTRY( "gfx1", 0, charlayout, 0, 1 )
149	149	GFXDECODE_END
150	150
151	151
r18326	r18327
202	202	ROM_REGION( 0x200000, "pcm", ROMREGION_ERASE00 )
203	203	ROM_LOAD( "pcm.rom", 0x00000, 0x200000, NO_DUMP )
204	204
205		// ROM_REGION( 0x10000, "gfx1", ROMREGION_ERASE00 )
	205	// ROM_REGION( 0x10000, "gfx1", ROMREGION_ERASE00 )
206	206	ROM_END
207	207
208	208	GAME( 1988, korgm1, 0, korgm1, korgm1, 0, ROT0, "Korg", "M1", GAME_IS_SKELETON )

trunk/src/mess/drivers/pc8801.c
r18326	r18327
2348	2348	/*
2349	2349	TIMER_DEVICE_CALLBACK_MEMBER(pc8801_state::pc8801_rtc_irq)
2350	2350	{
2351		if(m_timer_irq_mask)
2352		pc8801_raise_irq(machine(),1<<(2),1);
	2351	if(m_timer_irq_mask)
	2352	pc8801_raise_irq(machine(),1<<(2),1);
2353	2353	}
2354	2354	*/
2355	2355

trunk/src/mess/drivers/cbm2.c
r18326	r18327
2	2
3	3	TODO:
4	4
5		- CIA timers fail in burn-in test
6		- NTSC variants unable to load from disk
7		- shift lock
8		- Hungarian keyboard
9		- cbm620hu charom banking?
10		- read VIC video/color RAM thru PLA (Sphi2 = 1, AE = 0)
11		- user port
12		- co-processor bus
13		- 8088 co-processor board
	5	- CIA timers fail in burn-in test
	6	- NTSC variants unable to load from disk
	7	- shift lock
	8	- Hungarian keyboard
	9	- cbm620hu charom banking?
	10	- read VIC video/color RAM thru PLA (Sphi2 = 1, AE = 0)
	11	- user port
	12	- co-processor bus
	13	- 8088 co-processor board
14	14
15	15	*/
16	16
r18326	r18327
45	45	// read_pla - low profile PLA read
46	46	//-------------------------------------------------
47	47
48		void cbm2_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	48	void cbm2_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
49	49	int casseg1, int casseg2, int casseg3, int casseg4, int rasseg1, int rasseg2, int rasseg3, int rasseg4)
50	50	{
51	51	UINT32 input = P0 << 15 \| P1 << 14 \| P2 << 13 \| P3 << 12 \| busy2 << 11 \| eras << 10 \| ecas << 9 \| refen << 8 \| cas << 7 \| ras << 6;
r18326	r18327
66	66	// read_pla - high profile PLA read
67	67	//-------------------------------------------------
68	68
69		void cbm2hp_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
	69	void cbm2hp_state::read_pla(offs_t offset, int ras, int cas, int refen, int eras, int ecas, int busy2,
70	70	int casseg1, int casseg2, int casseg3, int casseg4, int rasseg1, int rasseg2, int rasseg3, int rasseg4)
71	71	{
72	72	UINT32 input = ras << 13 \| cas << 12 \| refen << 11 \| eras << 10 \| ecas << 9 \| busy2 << 8 \| P3 << 3 \| P2 << 2 \| P1 << 1 \| P0;
r18326	r18327
88	88	//-------------------------------------------------
89	89
90	90	void cbm2_state::bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int sysioen, int dramen,
91		int casseg1, int casseg2, int casseg3, int casseg4, int buframcs, int extbufcs, int *vidramcs,
	91	int casseg1, int casseg2, int casseg3, int casseg4, int buframcs, int extbufcs, int *vidramcs,
92	92	int diskromcs, int csbank1, int csbank2, int csbank3, int basiccs, int knbcs, int *kernalcs,
93	93	int crtccs, int cs1, int sidcs, int extprtcs, int ciacs, int aciacs, int tript1cs, int tript2cs)
94	94	{
r18326	r18327
333	333	{
334	334	UINT32 input = P0 << 15 \| P2 << 14 \| bras << 13 \| P1 << 12 \| P3 << 11 \| busy2 << 10 \| m_statvid << 9 \| sphi2 << 8 \|
335	335	clrnibcsb << 7 \| m_dramon << 6 \| procvid << 5 \| refen << 4 \| m_vicdotsel << 3 \| ba << 2 \| aec << 1 \| srw;
336
	336
337	337	UINT32 data = m_pla1->read(input);
338	338
339	339	*datxen = BIT(data, 0);
r18326	r18327
356	356	{
357	357	UINT32 input = VA12 << 15 \| ba << 14 \| A13 << 13 \| A15 << 12 \| A14 << 11 \| A11 << 10 \| A10 << 9 \| A12 << 8 \|
358	358	sphi2 << 7 \| vicen << 6 \| m_statvid << 5 \| m_vicdotsel << 4 \| ae << 3 \| segf << 2 \| bcas << 1 \| bank0;
359
	359
360	360	UINT32 data = m_pla2->read(input);
361	361
362	362	*clrnibcsb = BIT(data, 0);
r18326	r18327
385	385
386	386	int clrnibcsb = 1, procvid = 1, segf = 1;
387	387
388		read_pla1(offset, bras, busy2, sphi2, clrnibcsb, procvid, refen, ba, *aec, srw,
	388	read_pla1(offset, bras, busy2, sphi2, clrnibcsb, procvid, refen, ba, *aec, srw,
389	389	datxen, dramxen, clrniben, &segf, _64kcasen, casenb, viddaten, viddat_tr);
390	390
391	391	int bank0 = 1, vicen = 1;
r18326	r18327
429	429	*clrnibcs = clrnibcsb \|\| bcas;
430	430	*vidmatcs = vidmatcsb \|\| bcas;
431	431
432		read_pla1(offset, bras, busy2, sphi2, clrnibcsb, procvid, refen, ba, *aec, srw,
	432	read_pla1(offset, bras, busy2, sphi2, clrnibcsb, procvid, refen, ba, *aec, srw,
433	433	datxen, dramxen, clrniben, &segf, _64kcasen, casenb, viddaten, viddat_tr);
434	434	}
435	435
r18326	r18327
441	441	UINT8 p500_state::read_memory(address_space &space, offs_t offset, offs_t va, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas, UINT8 *clrnib)
442	442	{
443	443	int srw = 1, busy2 = 1, refen = 0;
444
	444
445	445	int datxen = 1, dramxen = 1, clrniben = 1, _64kcasen = 1, casenb = 1, viddaten = 1, viddat_tr = 1;
446	446	int clrnibcs = 1, extbufcs = 1, discromcs = 1, buframcs = 1, charomcs = 1, viccs = 1, vidmatcs = 1;
447	447	int csbank1 = 1, csbank2 = 1, csbank3 = 1, basiclocs = 1, basichics = 1, kernalcs = 1;
r18326	r18327
476	476	data = m_charom[va & 0xfff];
477	477	}
478	478	}
479
	479
480	480	if (clrniben)
481	481	{
482	482	if (!clrnibcs && !vsysaden)
r18326	r18327
564	564	{
565	565	int srw = 0, busy2 = 1, refen = 0;
566	566	offs_t va = 0xffff;
567
	567
568	568	int datxen = 1, dramxen = 1, clrniben = 1, _64kcasen = 1, casenb = 1, viddaten = 1, viddat_tr = 1;
569	569	int clrnibcs = 1, extbufcs = 1, discromcs = 1, buframcs = 1, charomcs = 1, viccs = 1, vidmatcs = 1;
570	570	int csbank1 = 1, csbank2 = 1, csbank3 = 1, basiclocs = 1, basichics = 1, kernalcs = 1;
r18326	r18327
675	675	READ8_MEMBER( p500_state::vic_videoram_r )
676	676	{
677	677	/*
678		int sphi0 = 0, sphi1 = 1, sphi2 = 0, ba = 1, ae = 0, bras = 0, bcas = 0;
679		offs_t va = offset;
	678	int sphi0 = 0, sphi1 = 1, sphi2 = 0, ba = 1, ae = 0, bras = 0, bcas = 0;
	679	offs_t va = offset;
680	680
681		return read_memory(space, 0, va, sphi0, sphi1, sphi2, ba, ae, bras, bcas);
682		*/
	681	return read_memory(space, 0, va, sphi0, sphi1, sphi2, ba, ae, bras, bcas);
	682	*/
683	683	/*
684		int ba = 1, ae = 0, bras = 1, bcas = 0;
685		UINT8 clrnib = 0xf;
	684	int ba = 1, ae = 0, bras = 1, bcas = 0;
	685	UINT8 clrnib = 0xf;
686	686
	687	if (offset < 0x1000)
	688	{
	689	return read_memory(space, 0, offset, 0, 1, 0, ba, ae, bras, bcas, &clrnib);
	690	}
	691	else
	692	{
	693	return read_memory(space, 0, offset, 1, 0, 1, ba, ae, bras, bcas, &clrnib);
	694	}
	695	*/
	696
687	697	if (offset < 0x1000)
688	698	{
689		return read_memory(space, 0, offset, 0, 1, 0, ba, ae, bras, bcas, &clrnib);
690		}
691		else
692		{
693		return read_memory(space, 0, offset, 1, 0, 1, ba, ae, bras, bcas, &clrnib);
694		}
695		*/
696
697		if (offset < 0x1000)
698		{
699	699	return m_charom[offset & 0xfff];
700	700	}
701	701	else
r18326	r18327
961	961	{
962	962	int color = BIT(data, 7) ^ BIT(code, 7) ^ BIT(ma, 13);
963	963	if (cursor_x == column) color ^= 1;
964
	964
965	965	bitmap.pix32(y, x++) = RGB_MONOCHROME_GREEN[color];
966	966
967	967	data <<= 1;
r18326	r18327
1000	1000	{
1001	1001	int color = BIT(data, 7) ^ BIT(code, 7) ^ BIT(ma, 13);
1002	1002	if (cursor_x == column) color ^= 1;
1003
	1003
1004	1004	bitmap.pix32(y, x++) = RGB_MONOCHROME_GREEN[color];
1005	1005
1006	1006	data <<= 1;
r18326	r18327
1106	1106	READ8_MEMBER( cbm2_state::tpi1_pa_r )
1107	1107	{
1108	1108	/*
1109
1110		bit description
1111
1112		0 0
1113		1 0
1114		2 REN
1115		3 ATN
1116		4 DAV
1117		5 EOI
1118		6 NDAC
1119		7 NRFD
1120
1121		*/
1122	1109
	1110	bit description
	1111
	1112	0 0
	1113	1 0
	1114	2 REN
	1115	3 ATN
	1116	4 DAV
	1117	5 EOI
	1118	6 NDAC
	1119	7 NRFD
	1120
	1121	*/
	1122
1123	1123	UINT8 data = 0;
1124	1124
1125	1125	// IEEE-488
r18326	r18327
1136	1136	WRITE8_MEMBER( cbm2_state::tpi1_pa_w )
1137	1137	{
1138	1138	/*
1139
1140		bit description
1141
1142		0 75161A DC
1143		1 75161A TE
1144		2 REN
1145		3 ATN
1146		4 DAV
1147		5 EOI
1148		6 NDAC
1149		7 NRFD
1150
1151		*/
1152	1139
	1140	bit description
	1141
	1142	0 75161A DC
	1143	1 75161A TE
	1144	2 REN
	1145	3 ATN
	1146	4 DAV
	1147	5 EOI
	1148	6 NDAC
	1149	7 NRFD
	1150
	1151	*/
	1152
1153	1153	// IEEE-488
1154	1154	m_ieee2->dc_w(BIT(data, 0));
1155	1155
r18326	r18327
1167	1167	READ8_MEMBER( cbm2_state::tpi1_pb_r )
1168	1168	{
1169	1169	/*
1170
1171		bit description
1172
1173		0 IFC
1174		1 SRQ
1175		2 user port PB2
1176		3 user port PB3
1177		4
1178		5
1179		6
1180		7 CASS SW
1181
1182		*/
1183	1170
	1171	bit description
	1172
	1173	0 IFC
	1174	1 SRQ
	1175	2 user port PB2
	1176	3 user port PB3
	1177	4
	1178	5
	1179	6
	1180	7 CASS SW
	1181
	1182	*/
	1183
1184	1184	UINT8 data = 0;
1185	1185
1186	1186	// IEEE-488
1187	1187	data \|= m_ieee2->ifc_r();
1188	1188	data \|= m_ieee2->srq_r() << 1;
1189
	1189
1190	1190	// user port
1191	1191	//data \|= m_user->pb2_r() << 2;
1192	1192	//data \|= m_user->pb3_r() << 3;
r18326	r18327
1200	1200	WRITE8_MEMBER( cbm2_state::tpi1_pb_w )
1201	1201	{
1202	1202	/*
1203
1204		bit description
1205
1206		0 IFC
1207		1 SRQ
1208		2 user port PB2
1209		3 user port PB3
1210		4 DRAMON
1211		5 CASS WRT
1212		6 CASS MTR
1213		7
1214
1215		*/
1216	1203
	1204	bit description
	1205
	1206	0 IFC
	1207	1 SRQ
	1208	2 user port PB2
	1209	3 user port PB3
	1210	4 DRAMON
	1211	5 CASS WRT
	1212	6 CASS MTR
	1213	7
	1214
	1215	*/
	1216
1217	1217	// IEEE-488
1218		m_ieee2->ifc_w(BIT(data, 0));
1219		m_ieee2->srq_w(BIT(data, 1));
	1218	m_ieee2->ifc_w(BIT(data, 0));
	1219	m_ieee2->srq_w(BIT(data, 1));
1220	1220
1221	1221	// user port
1222	1222	//m_user->pb2_w(BIT(data, 2));
r18326	r18327
1313	1313	READ8_MEMBER( cbm2_state::tpi2_pc_r )
1314	1314	{
1315	1315	/*
1316
1317		bit description
1318
1319		0 COLUMN 0
1320		1 COLUMN 1
1321		2 COLUMN 2
1322		3 COLUMN 3
1323		4 COLUMN 4
1324		5 COLUMN 5
1325		6 0=PAL, 1=NTSC
1326		7 0
1327
1328		*/
1329	1316
	1317	bit description
	1318
	1319	0 COLUMN 0
	1320	1 COLUMN 1
	1321	2 COLUMN 2
	1322	3 COLUMN 3
	1323	4 COLUMN 4
	1324	5 COLUMN 5
	1325	6 0=PAL, 1=NTSC
	1326	7 0
	1327
	1328	*/
	1329
1330	1330	return (m_ntsc << 6) \| (read_keyboard() & 0x3f);
1331	1331	}
1332	1332
1333	1333	READ8_MEMBER( cbm2hp_state::tpi2_pc_r )
1334	1334	{
1335	1335	/*
1336
1337		bit description
1338
1339		0 COLUMN 0
1340		1 COLUMN 1
1341		2 COLUMN 2
1342		3 COLUMN 3
1343		4 COLUMN 4
1344		5 COLUMN 5
1345		6 1
1346		7 1
1347
1348		*/
1349	1336
	1337	bit description
	1338
	1339	0 COLUMN 0
	1340	1 COLUMN 1
	1341	2 COLUMN 2
	1342	3 COLUMN 3
	1343	4 COLUMN 4
	1344	5 COLUMN 5
	1345	6 1
	1346	7 1
	1347
	1348	*/
	1349
1350	1350	return read_keyboard();
1351	1351	}
1352	1352
1353	1353	READ8_MEMBER( p500_state::tpi2_pc_r )
1354	1354	{
1355	1355	/*
1356
1357		bit description
1358
1359		0 COLUMN 0
1360		1 COLUMN 1
1361		2 COLUMN 2
1362		3 COLUMN 3
1363		4 COLUMN 4
1364		5 COLUMN 5
1365		6 0
1366		7 0
1367
1368		*/
1369	1356
	1357	bit description
	1358
	1359	0 COLUMN 0
	1360	1 COLUMN 1
	1361	2 COLUMN 2
	1362	3 COLUMN 3
	1363	4 COLUMN 4
	1364	5 COLUMN 5
	1365	6 0
	1366	7 0
	1367
	1368	*/
	1369
1370	1370	return read_keyboard();
1371	1371	}
1372	1372
1373	1373	WRITE8_MEMBER( p500_state::tpi2_pc_w )
1374	1374	{
1375	1375	/*
1376
1377		bit description
1378
1379		0
1380		1
1381		2
1382		3
1383		4
1384		5
1385		6 VICBNKSEL0
1386		7 VICBNKSEL1
1387
1388		*/
1389	1376
	1377	bit description
	1378
	1379	0
	1380	1
	1381	2
	1382	3
	1383	4
	1384	5
	1385	6 VICBNKSEL0
	1386	7 VICBNKSEL1
	1387
	1388	*/
	1389
1390	1390	m_vicbnksel = data >> 6;
1391	1391	}
1392	1392
r18326	r18327
1437	1437	READ8_MEMBER( cbm2_state::cia_pa_r )
1438	1438	{
1439	1439	/*
1440
1441		bit description
1442
1443		0 IEEE-488 D0, user port 1D0
1444		1 IEEE-488 D1, user port 1D1
1445		2 IEEE-488 D2, user port 1D2
1446		3 IEEE-488 D3, user port 1D3
1447		4 IEEE-488 D4, user port 1D4
1448		5 IEEE-488 D5, user port 1D5
1449		6 IEEE-488 D6, user port 1D6, LTPN
1450		7 IEEE-488 D7, user port 1D7, GAME TRIGGER 24
1451
1452		*/
1453	1440
	1441	bit description
	1442
	1443	0 IEEE-488 D0, user port 1D0
	1444	1 IEEE-488 D1, user port 1D1
	1445	2 IEEE-488 D2, user port 1D2
	1446	3 IEEE-488 D3, user port 1D3
	1447	4 IEEE-488 D4, user port 1D4
	1448	5 IEEE-488 D5, user port 1D5
	1449	6 IEEE-488 D6, user port 1D6, LTPN
	1450	7 IEEE-488 D7, user port 1D7, GAME TRIGGER 24
	1451
	1452	*/
	1453
1454	1454	UINT8 data = 0;
1455	1455
1456	1456	// IEEE-488
r18326	r18327
1469	1469	WRITE8_MEMBER( cbm2_state::cia_pa_w )
1470	1470	{
1471	1471	/*
1472
1473		bit description
1474
1475		0 IEEE-488 D0, user port 1D0
1476		1 IEEE-488 D1, user port 1D1
1477		2 IEEE-488 D2, user port 1D2
1478		3 IEEE-488 D3, user port 1D3
1479		4 IEEE-488 D4, user port 1D4
1480		5 IEEE-488 D5, user port 1D5
1481		6 IEEE-488 D6, user port 1D6
1482		7 IEEE-488 D7, user port 1D7
1483
1484		*/
1485	1472
	1473	bit description
	1474
	1475	0 IEEE-488 D0, user port 1D0
	1476	1 IEEE-488 D1, user port 1D1
	1477	2 IEEE-488 D2, user port 1D2
	1478	3 IEEE-488 D3, user port 1D3
	1479	4 IEEE-488 D4, user port 1D4
	1480	5 IEEE-488 D5, user port 1D5
	1481	6 IEEE-488 D6, user port 1D6
	1482	7 IEEE-488 D7, user port 1D7
	1483
	1484	*/
	1485
1486	1486	// IEEE-488
1487	1487	m_ieee1->write(space, 0, data);
1488	1488
r18326	r18327
1496	1496	READ8_MEMBER( cbm2_state::cia_pb_r )
1497	1497	{
1498	1498	/*
1499
1500		bit description
1501
1502		0 user port 2D0, GAME10
1503		1 user port 2D1, GAME11
1504		2 user port 2D2, GAME12
1505		3 user port 2D3, GAME13
1506		4 user port 2D4, GAME20
1507		5 user port 2D5, GAME21
1508		6 user port 2D6, GAME22
1509		7 user port 2D7, GAME23
1510
1511		*/
1512	1499
	1500	bit description
	1501
	1502	0 user port 2D0, GAME10
	1503	1 user port 2D1, GAME11
	1504	2 user port 2D2, GAME12
	1505	3 user port 2D3, GAME13
	1506	4 user port 2D4, GAME20
	1507	5 user port 2D5, GAME21
	1508	6 user port 2D6, GAME22
	1509	7 user port 2D7, GAME23
	1510
	1511	*/
	1512
1513	1513	UINT8 data = 0;
1514	1514
1515	1515	// joystick
r18326	r18327
1525	1525	WRITE8_MEMBER( cbm2_state::cia_pb_w )
1526	1526	{
1527	1527	/*
1528
1529		bit description
1530
1531		0 user port 2D0
1532		1 user port 2D1
1533		2 user port 2D2
1534		3 user port 2D3
1535		4 user port 2D4
1536		5 user port 2D5
1537		6 user port 2D6
1538		7 user port 2D7
1539
1540		*/
1541	1528
	1529	bit description
	1530
	1531	0 user port 2D0
	1532	1 user port 2D1
	1533	2 user port 2D2
	1534	3 user port 2D3
	1535	4 user port 2D4
	1536	5 user port 2D5
	1537	6 user port 2D6
	1538	7 user port 2D7
	1539
	1540	*/
	1541
1542	1542	//m_user->data2_w(data);
1543	1543	}
1544	1544

trunk/src/mess/drivers/vic10.c
r18326	r18327
254	254	READ8_MEMBER( vic10_state::sid_potx_r )
255	255	{
256	256	UINT8 cia_pa = m_cia->pa_r();
257
	257
258	258	int sela = BIT(cia_pa, 6);
259	259	int selb = BIT(cia_pa, 7);
260	260
r18326	r18327
269	269	READ8_MEMBER( vic10_state::sid_poty_r )
270	270	{
271	271	UINT8 cia_pa = m_cia->pa_r();
272
	272
273	273	int sela = BIT(cia_pa, 6);
274	274	int selb = BIT(cia_pa, 7);
275	275

trunk/src/mess/drivers/c128.c
r18326	r18327
969	969	READ8_MEMBER( c128_state::sid_potx_r )
970	970	{
971	971	UINT8 cia1_pa = m_cia1->pa_r();
972
	972
973	973	int sela = BIT(cia1_pa, 6);
974	974	int selb = BIT(cia1_pa, 7);
975	975
r18326	r18327
984	984	READ8_MEMBER( c128_state::sid_poty_r )
985	985	{
986	986	UINT8 cia1_pa = m_cia1->pa_r();
987
	987
988	988	int sela = BIT(cia1_pa, 6);
989	989	int selb = BIT(cia1_pa, 7);
990	990

trunk/src/mess/drivers/d6800.c
r18326	r18327
78	78	UINT8 m_portb;
79	79	virtual void machine_start();
80	80	virtual void machine_reset();
81		public:
	81	public:
82	82	UINT32 screen_update_d6800(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
83	83	TIMER_DEVICE_CALLBACK_MEMBER(d6800_p);
84	84	};

trunk/src/mess/drivers/ti99_4p.c
r18326	r18327
96	96	virtual void machine_start();
97	97	DECLARE_MACHINE_RESET(ti99_4p);
98	98	TIMER_DEVICE_CALLBACK_MEMBER(sgcpu_hblank_interrupt);
99
	99
100	100	void set_tms9901_INT2_from_v9938(v99x8_device &vdp, int state);
101	101
102	102	tms9900_device* m_cpu;

trunk/src/mess/drivers/ti99_4x.c
r18326	r18327
88	88
89	89	DECLARE_INPUT_CHANGED_MEMBER( load_interrupt );
90	90	TIMER_DEVICE_CALLBACK_MEMBER(ti99_4ev_hblank_interrupt);
91
	91
92	92	// Some values to keep
93	93	tms9900_device* m_cpu;
94	94	tms9901_device* m_tms9901;

trunk/src/mess/drivers/elwro800.c
r18326	r18327
49	49	DECLARE_WRITE8_MEMBER(elwro800jr_fdc_control_w);
50	50	DECLARE_READ8_MEMBER(elwro800jr_io_r);
51	51	DECLARE_WRITE8_MEMBER(elwro800jr_io_w);
52		DECLARE_MACHINE_RESET(elwro800);
	52	DECLARE_MACHINE_RESET(elwro800);
53	53	INTERRUPT_GEN_MEMBER(elwro800jr_interrupt);
54	54	DECLARE_READ8_MEMBER(i8255_port_c_r);
55	55	DECLARE_WRITE8_MEMBER(i8255_port_c_w);

trunk/src/mess/drivers/a2600.c
r18326	r18327
47	47	a2600_state(const machine_config &mconfig, device_type type, const char *tag)
48	48	: driver_device(mconfig, type, tag)
49	49	, m_riot_ram(*this, "riot_ram")
50		// , m_joy1(*this, CONTROL1_TAG)
51		// , m_joy2(*this, CONTROL2_TAG)
	50	// , m_joy1(*this, CONTROL1_TAG)
	51	// , m_joy2(*this, CONTROL2_TAG)
52	52	{ }
53	53
54	54	dpc_t m_dpc;
r18326	r18327
128	128	DECLARE_READ8_MEMBER(riot_input_port_8_r);
129	129
130	130	protected:
131		// required_device<vcs_control_port_device> m_joy1;
132		// required_device<vcs_control_port_device> m_joy2;
	131	// required_device<vcs_control_port_device> m_joy1;
	132	// required_device<vcs_control_port_device> m_joy2;
133	133	int next_bank();
134	134	void modeF8_switch(UINT16 offset, UINT8 data);
135	135	void modeFA_switch(UINT16 offset, UINT8 data);
r18326	r18327
1276	1276	case 0x00: /* Joystick */
1277	1277	case 0x05: /* Joystick w/Boostergrip */
1278	1278	val \|= machine().root_device().ioport("SWA_JOY")->read() & 0xF0;
1279		// val \|= ( m_joy1->joy_r() & 0x0F ) << 4;
	1279	// val \|= ( m_joy1->joy_r() & 0x0F ) << 4;
1280	1280	break;
1281	1281	case 0x01: /* Paddle */
1282	1282	val \|= machine().root_device().ioport("SWA_PAD")->read() & 0xF0;
r18326	r18327
2315	2315	/* devices */
2316	2316	MCFG_RIOT6532_ADD("riot", MASTER_CLOCK_NTSC / 3, r6532_interface)
2317	2317
2318		// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
2319		// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
	2318	// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
	2319	// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
2320	2320
2321	2321	MCFG_FRAGMENT_ADD(a2600_cartslot)
2322	2322	MCFG_SOFTWARE_LIST_FILTER("cart_list", "NTSC")
r18326	r18327
2351	2351	/* devices */
2352	2352	MCFG_RIOT6532_ADD("riot", MASTER_CLOCK_PAL / 3, r6532_interface)
2353	2353
2354		// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
2355		// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
	2354	// MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
	2355	// MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
2356	2356
2357	2357	MCFG_FRAGMENT_ADD(a2600_cartslot)
2358	2358	MCFG_SOFTWARE_LIST_FILTER("cart_list", "PAL")

trunk/src/mess/drivers/xor100.c
r18326	r18327
482	482	DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), /* interrupt handler */
483	483	DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z0_w), /* ZC/TO0 callback */
484	484	DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z1_w), /* ZC/TO1 callback */
485		DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z2_w) /* ZC/TO2 callback */
	485	DEVCB_DRIVER_LINE_MEMBER(xor100_state,ctc_z2_w) /* ZC/TO2 callback */
486	486	};
487	487
488	488	/* WD1795-02 Interface */

trunk/src/mess/drivers/bml3.c
r18326	r18327
111	111	virtual void machine_start();
112	112	virtual void video_start();
113	113	virtual void palette_init();
114		public:
	114	public:
115	115	UINT32 screen_update_bml3(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
116	116	INTERRUPT_GEN_MEMBER(bml3_irq);
117	117	INTERRUPT_GEN_MEMBER(bml3_timer_firq);
r18326	r18327
893	893	MCFG_CPU_ADD("maincpu",M6809, XTAL_1MHz)
894	894	MCFG_CPU_PROGRAM_MAP(bml3_mem)
895	895	MCFG_CPU_VBLANK_INT_DRIVER("screen", bml3_state, bml3_timer_firq)
896		// MCFG_CPU_PERIODIC_INT_DRIVER(bml3_state, bml3_firq, 45)
	896	// MCFG_CPU_PERIODIC_INT_DRIVER(bml3_state, bml3_firq, 45)
897	897
898	898	// MCFG_MACHINE_RESET_OVERRIDE(bml3_state,bml3)
899	899

trunk/src/mess/drivers/rainbow.c
r18326	r18327
130	130
131	131	void update_kbd_irq();
132	132	virtual void machine_reset();
133		public:
	133	public:
134	134	UINT32 screen_update_rainbow(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
135	135	INTERRUPT_GEN_MEMBER(vblank_irq);
136	136	TIMER_DEVICE_CALLBACK_MEMBER(keyboard_tick);

trunk/src/mess/drivers/amiga.c
r18326	r18327
424	424	MCFG_FLOPPY_DRIVE_ADD("fd1", amiga_floppies, 0, 0, amiga_fdc::floppy_formats)
425	425	MCFG_FLOPPY_DRIVE_ADD("fd2", amiga_floppies, 0, 0, amiga_fdc::floppy_formats)
426	426	MCFG_FLOPPY_DRIVE_ADD("fd3", amiga_floppies, 0, 0, amiga_fdc::floppy_formats)
427
	427
428	428	MCFG_AMIGA_KEYBOARD_ADD("kbd")
429	429	MACHINE_CONFIG_END
430	430

trunk/src/mame/drivers/pcat_nit.c
r18326	r18327
212	212	AM_RANGE(0x0280, 0x0283) AM_READNOP
213	213	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
214	214	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
215		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	215	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
216	216	AM_RANGE(0x03f8, 0x03ff) AM_DEVREADWRITE8("ns16450_0", ns16450_device, ins8250_r, ins8250_w, 0xffffffff)
217	217	ADDRESS_MAP_END
218	218

trunk/src/mame/drivers/kontest.c
r18326	r18327
53	53
54	54	virtual void video_start();
55	55	virtual void palette_init();
56		public:
	56	public:
57	57	INTERRUPT_GEN_MEMBER(kontest_interrupt);
58	58	};
59	59

trunk/src/mame/drivers/magtouch.c
r18326	r18327
181	181	AM_RANGE(0x02e0, 0x02e7) AM_READWRITE8(magtouch_io_r, magtouch_io_w, 0xffffffff)
182	182	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
183	183	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
184		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	184	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
185	185	AM_RANGE(0x03f8, 0x03ff) AM_DEVREADWRITE8("ns16450_0", ns16450_device, ins8250_r, ins8250_w, 0xffffffff)
186	186	ADDRESS_MAP_END
187	187

trunk/src/mame/drivers/techno.c
r18326	r18327
49	49	private:
50	50	bool m_digwait;
51	51	UINT8 m_keyrow;
52		public:
	52	public:
53	53	INTERRUPT_GEN_MEMBER(techno_intgen);
54	54	};
55	55

trunk/src/mame/drivers/pangofun.c
r18326	r18327
125	125	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff)
126	126	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
127	127	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
128		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	128	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
129	129	ADDRESS_MAP_END
130	130
131	131	#define AT_KEYB_HELPER(bit, text, key1) \

trunk/src/mame/drivers/firebeat.c
r18326	r18327
217	217	DECLARE_WRITE32_MEMBER(lamp_output3_ppp_w);
218	218	DECLARE_READ32_MEMBER(ppc_spu_share_r);
219	219	DECLARE_WRITE32_MEMBER(ppc_spu_share_w);
220		DECLARE_READ16_MEMBER(spu_unk_r);
	220	DECLARE_READ16_MEMBER(spu_unk_r);
221	221	TIMER_CALLBACK_MEMBER(keyboard_timer_callback);
222	222	};
223	223

trunk/src/mame/drivers/cps1.c
r18326	r18327
3063	3063
3064	3064	/* video hardware */
3065	3065	MCFG_SCREEN_ADD("screen", RASTER)
3066		// MCFG_SCREEN_REFRESH_RATE(59.61) /* verified on one of the input gates of the 74ls08@4J on GNG romboard 88620-b-2 */
3067		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
3068		// MCFG_SCREEN_SIZE(648, 328)
3069		// MCFG_SCREEN_VISIBLE_AREA(88, (64-8)8-1, 28, 308-1 )
	3066	// MCFG_SCREEN_REFRESH_RATE(59.61) /* verified on one of the input gates of the 74ls08@4J on GNG romboard 88620-b-2 */
	3067	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	3068	// MCFG_SCREEN_SIZE(648, 328)
	3069	// MCFG_SCREEN_VISIBLE_AREA(88, (64-8)8-1, 28, 308-1 )
3070	3070	MCFG_SCREEN_RAW_PARAMS(XTAL_16MHz/2, 518, 64, 448, 259, 16, 240) /* guess: assume that CPS-1 uses the same exact timings as CPS-2 */
3071	3071	MCFG_SCREEN_UPDATE_DRIVER(cps_state, screen_update_cps1)
3072	3072	MCFG_SCREEN_VBLANK_DRIVER(cps_state, screen_eof_cps1)

trunk/src/mame/drivers/su2000.c
r18326	r18327
102	102	AM_IMPORT_FROM(pcat32_io_common)
103	103	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
104	104	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
105		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	105	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
106	106	ADDRESS_MAP_END
107	107
108	108

trunk/src/mame/drivers/blackt96.c
r18326	r18327
362	362	PORT_BIT( 0x0040, IP_ACTIVE_HIGH, IPT_UNKNOWN )
363	363	PORT_BIT( 0x0080, IP_ACTIVE_HIGH, IPT_UNKNOWN )
364	364	PORT_BIT( 0xff00, IP_ACTIVE_HIGH, IPT_UNKNOWN )
365
	365
366	366	#if 0
367	367	PORT_START("IN2")
368	368	PORT_DIPNAME( 0x0001, 0x0001, "2" )

trunk/src/mame/drivers/magictg.c
r18326	r18327
212	212	virtual void machine_start();
213	213	virtual void machine_reset();
214	214	virtual void video_start();
215		public:
	215	public:
216	216	UINT32 screen_update_magictg(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
217	217	};
218	218

trunk/src/mame/drivers/taitowlf.c
r18326	r18327
489	489	#if ENABLE_VGA
490	490	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
491	491	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
492		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	492	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
493	493	#endif
494	494	AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w)
495	495	AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)

trunk/src/mame/drivers/pntnpuzl.c
r18326	r18327
311	311	AM_RANGE(0x28001a, 0x28001b) AM_WRITENOP
312	312
313	313	/* standard VGA */
314		AM_RANGE(0x3a0000, 0x3bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffff)
	314	AM_RANGE(0x3a0000, 0x3bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffff)
315	315	AM_RANGE(0x3c03b0, 0x3c03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffff)
316	316	AM_RANGE(0x3c03c0, 0x3c03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffff)
317		AM_RANGE(0x3c03d0, 0x3c03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffff)
	317	AM_RANGE(0x3c03d0, 0x3c03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffff)
318	318
319	319	AM_RANGE(0x400000, 0x407fff) AM_RAM
320	320	ADDRESS_MAP_END

trunk/src/mame/drivers/spectra.c
r18326	r18327
212	212
213	213	static const sn76477_interface sn76477_intf =
214	214	{
215		RES_M(1000), /* 4 noise_res */
216		RES_M(1000), /* 5 filter_res */
217		CAP_N(0), /* 6 filter_cap */
218		RES_K(470), /* 7 decay_res */
219		CAP_N(1), /* 8 attack_decay_cap */
220		RES_K(22), /* 10 attack_res */
221		RES_K(100), /* 11 amplitude_res */
222		RES_K(52), /* 12 feedback_res */
223		5.0, /* 16 vco_voltage */
224		CAP_U(0.01), /* 17 vco_cap */
225		RES_K(390), /* 18 vco_res */
226		0.0, /* 19 pitch_voltage */
227		RES_M(1), /* 20 slf_res */
228		CAP_U(0.1), /* 21 slf_cap */
229		CAP_U(0.47), /* 23 oneshot_cap */
230		RES_K(470), /* 24 oneshot_res */
	215	RES_M(1000), /* 4 noise_res */
	216	RES_M(1000), /* 5 filter_res */
	217	CAP_N(0), /* 6 filter_cap */
	218	RES_K(470), /* 7 decay_res */
	219	CAP_N(1), /* 8 attack_decay_cap */
	220	RES_K(22), /* 10 attack_res */
	221	RES_K(100), /* 11 amplitude_res */
	222	RES_K(52), /* 12 feedback_res */
	223	5.0, /* 16 vco_voltage */
	224	CAP_U(0.01), /* 17 vco_cap */
	225	RES_K(390), /* 18 vco_res */
	226	0.0, /* 19 pitch_voltage */
	227	RES_M(1), /* 20 slf_res */
	228	CAP_U(0.1), /* 21 slf_cap */
	229	CAP_U(0.47), /* 23 oneshot_cap */
	230	RES_K(470), /* 24 oneshot_res */
231	231	0, /* 22 vco (variable) */
232	232	0, /* 26 mixer A (grounded) */
233	233	0, /* 25 mixer B (variable) */

trunk/src/mame/drivers/raiden2.c
r18326	r18327
1924	1924	MCFG_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK)
1925	1925
1926	1926	MCFG_SCREEN_ADD("screen", RASTER)
1927		// MCFG_SCREEN_REFRESH_RATE(55.47) /* verified on pcb */
	1927	// MCFG_SCREEN_REFRESH_RATE(55.47) /* verified on pcb */
1928	1928	MCFG_SCREEN_RAW_PARAMS(XTAL_32MHz/4,546,0,408,264,0,328) /* hand-tuned to match ~55.47 */
1929	1929	MCFG_SCREEN_UPDATE_DRIVER(raiden2_state, screen_update_raiden2)
1930	1930	MCFG_GFXDECODE(raiden2)

trunk/src/mame/drivers/gammagic.c
r18326	r18327
15	15	1 Motherboard MICRONICS M55Hi-Plus PCI/ISA, Chipset INTEL i430HX (TRITON II), 64 MB Ram (4 SIMM M x 16 MB SIMM)
16	16	On board Sound Blaster Vibra 16C chipset.
17	17	1 TOSHIBA CD-ROM or DVD-ROM Drive w/Bootable CD-ROM with Game.
18		1 OAK SVGA PCI Video Board.
	18	1 OAK SVGA PCI Video Board.
19	19	1 Voodoo Graphics PCI Video Board, connected to the monitor.
20	20	1 21" SVGA Color Monitor, 16x9 Aspect, Vertical mount, with touchscreen.
21	21	1 Bally's IO-Board, Based on 68000 procesor as interface to all gaming devices
r18326	r18327
88	88	device_t *m_pic8259_2;
89	89	device_t *m_dma8237_1;
90	90	device_t *m_dma8237_2;
91
	91
92	92	emu_timer *m_atapi_timer;
93	93	//SCSIInstance *m_inserted_cdrom;
94	94
r18326	r18327
101	101	/* memory */
102	102	UINT8 m_atapi_regs[ATAPI_REG_MAX];
103	103	UINT8 m_atapi_data[ATAPI_DATA_SIZE];
104
	104
105	105	DECLARE_DRIVER_INIT(gammagic);
106	106	};
107	107
r18326	r18327
221	221	/*
222	222	static READ32_HANDLER( atapi_r )
223	223	{
224		gammagic_state *state = space.machine().driver_data<gammagic_state>();
225		UINT8 *atapi_regs = state->m_atapi_regs;
226		//running_machine &machine = space.machine();
227		int reg, data;
	224	gammagic_state *state = space.machine().driver_data<gammagic_state>();
	225	UINT8 *atapi_regs = state->m_atapi_regs;
	226	//running_machine &machine = space.machine();
	227	int reg, data;
228	228
229		if (mem_mask == 0x0000ffff) // word-wide command read
230		{
	229	if (mem_mask == 0x0000ffff) // word-wide command read
	230	{
231	231	logerror("ATAPI: packet read = %04x\n", state->m_atapi_data[state->m_atapi_data_ptr]);
232	232
233		// assert IRQ and drop DRQ
234		if (state->m_atapi_data_ptr == 0 && state->m_atapi_data_len == 0)
235		{
236		// get the data from the device
237		if( state->m_atapi_xferlen > 0 )
238		{
239		SCSIReadData( state->m_inserted_cdrom, state->m_atapi_data, state->m_atapi_xferlen );
240		state->m_atapi_data_len = state->m_atapi_xferlen;
241		}
	233	// assert IRQ and drop DRQ
	234	if (state->m_atapi_data_ptr == 0 && state->m_atapi_data_len == 0)
	235	{
	236	// get the data from the device
	237	if( state->m_atapi_xferlen > 0 )
	238	{
	239	SCSIReadData( state->m_inserted_cdrom, state->m_atapi_data, state->m_atapi_xferlen );
	240	state->m_atapi_data_len = state->m_atapi_xferlen;
	241	}
242	242
243		if (state->m_atapi_xfermod > MAX_TRANSFER_SIZE)
244		{
245		state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
246		state->m_atapi_xfermod = state->m_atapi_xfermod - MAX_TRANSFER_SIZE;
247		}
248		else
249		{
250		state->m_atapi_xferlen = state->m_atapi_xfermod;
251		state->m_atapi_xfermod = 0;
252		}
	243	if (state->m_atapi_xfermod > MAX_TRANSFER_SIZE)
	244	{
	245	state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
	246	state->m_atapi_xfermod = state->m_atapi_xfermod - MAX_TRANSFER_SIZE;
	247	}
	248	else
	249	{
	250	state->m_atapi_xferlen = state->m_atapi_xfermod;
	251	state->m_atapi_xfermod = 0;
	252	}
253	253
254		//verboselog\\( machine, 2, "atapi_r: atapi_xferlen=%d\n", state->m_atapi_xferlen );
255		if( state->m_atapi_xferlen != 0 )
256		{
257		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_SERVDSC;
258		atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
259		}
260		else
261		{
262		logerror("ATAPI: dropping DRQ\n");
263		atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
264		atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
265		}
	254	//verboselog\\( machine, 2, "atapi_r: atapi_xferlen=%d\n", state->m_atapi_xferlen );
	255	if( state->m_atapi_xferlen != 0 )
	256	{
	257	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_SERVDSC;
	258	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
	259	}
	260	else
	261	{
	262	logerror("ATAPI: dropping DRQ\n");
	263	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	264	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
	265	}
266	266
267		atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
268		atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
	267	atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
	268	atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
269	269
270		atapi_irq(space.machine(), ASSERT_LINE);
271		}
	270	atapi_irq(space.machine(), ASSERT_LINE);
	271	}
272	272
273		if( state->m_atapi_data_ptr < state->m_atapi_data_len )
274		{
275		data = state->m_atapi_data[state->m_atapi_data_ptr++];
276		data \|= ( state->m_atapi_data[state->m_atapi_data_ptr++] << 8 );
277		if( state->m_atapi_data_ptr >= state->m_atapi_data_len )
278		{
279
280		state->m_atapi_data_ptr = 0;
281		state->m_atapi_data_len = 0;
	273	if( state->m_atapi_data_ptr < state->m_atapi_data_len )
	274	{
	275	data = state->m_atapi_data[state->m_atapi_data_ptr++];
	276	data \|= ( state->m_atapi_data[state->m_atapi_data_ptr++] << 8 );
	277	if( state->m_atapi_data_ptr >= state->m_atapi_data_len )
	278	{
282	279
283		if( state->m_atapi_xferlen == 0 )
284		{
285		atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
286		atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
287		atapi_irq(space.machine(), ASSERT_LINE);
288		}
289		}
290		}
291		else
292		{
293		data = 0;
294		}
295		}
296		else
297		{
298		atapi_irq(space.machine(), CLEAR_LINE);
299		int shift;
300		shift = 0;
301		reg = offset<<2;
302		switch(mem_mask)
303		{
304		case 0x000000ff:
305		break;
306		case 0x0000ff00:
307		reg+=1;
308		data >>= 8;
309		shift=8;
310		break;
311		case 0x00ff0000:
312		reg+=2;
313		data >>=16;
314		shift=16;
315		break;
316		case 0xff000000:
317		reg+=3;
318		data >>=24;
319		shift=24;
320		break;
321		}
322		data = atapi_regs[reg];
323		data <<= shift;
324		}
325		return data;
	280	state->m_atapi_data_ptr = 0;
	281	state->m_atapi_data_len = 0;
	282
	283	if( state->m_atapi_xferlen == 0 )
	284	{
	285	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	286	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
	287	atapi_irq(space.machine(), ASSERT_LINE);
	288	}
	289	}
	290	}
	291	else
	292	{
	293	data = 0;
	294	}
	295	}
	296	else
	297	{
	298	atapi_irq(space.machine(), CLEAR_LINE);
	299	int shift;
	300	shift = 0;
	301	reg = offset<<2;
	302	switch(mem_mask)
	303	{
	304	case 0x000000ff:
	305	break;
	306	case 0x0000ff00:
	307	reg+=1;
	308	data >>= 8;
	309	shift=8;
	310	break;
	311	case 0x00ff0000:
	312	reg+=2;
	313	data >>=16;
	314	shift=16;
	315	break;
	316	case 0xff000000:
	317	reg+=3;
	318	data >>=24;
	319	shift=24;
	320	break;
	321	}
	322	data = atapi_regs[reg];
	323	data <<= shift;
	324	}
	325	return data;
326	326	}
327	327
328	328	static WRITE32_HANDLER( atapi_w )
329	329	{
330		gammagic_state *state = space.machine().driver_data<gammagic_state>();
331		UINT8 *atapi_regs = state->m_atapi_regs;
332		UINT8 *atapi_data = state->m_atapi_data;
333		int reg;
334		if (mem_mask == 0x0000ffff) // word-wide command write
335		{
336		atapi_data[state->m_atapi_data_ptr++] = data & 0xff;
337		atapi_data[state->m_atapi_data_ptr++] = data >> 8;
	330	gammagic_state *state = space.machine().driver_data<gammagic_state>();
	331	UINT8 *atapi_regs = state->m_atapi_regs;
	332	UINT8 *atapi_data = state->m_atapi_data;
	333	int reg;
	334	if (mem_mask == 0x0000ffff) // word-wide command write
	335	{
	336	atapi_data[state->m_atapi_data_ptr++] = data & 0xff;
	337	atapi_data[state->m_atapi_data_ptr++] = data >> 8;
338	338
339		if (state->m_atapi_cdata_wait)
340		{
341		logerror("ATAPI: waiting, ptr %d wait %d\n", state->m_atapi_data_ptr, state->m_atapi_cdata_wait);
342		if (state->m_atapi_data_ptr == state->m_atapi_cdata_wait)
343		{
344		// send it to the device
345		SCSIWriteData( state->m_inserted_cdrom, atapi_data, state->m_atapi_cdata_wait );
	339	if (state->m_atapi_cdata_wait)
	340	{
	341	logerror("ATAPI: waiting, ptr %d wait %d\n", state->m_atapi_data_ptr, state->m_atapi_cdata_wait);
	342	if (state->m_atapi_data_ptr == state->m_atapi_cdata_wait)
	343	{
	344	// send it to the device
	345	SCSIWriteData( state->m_inserted_cdrom, atapi_data, state->m_atapi_cdata_wait );
346	346
347		// assert IRQ
348		atapi_irq(space.machine(), ASSERT_LINE);
	347	// assert IRQ
	348	atapi_irq(space.machine(), ASSERT_LINE);
349	349
350		// not sure here, but clear DRQ at least?
351		atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
352		}
353		}
	350	// not sure here, but clear DRQ at least?
	351	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	352	}
	353	}
354	354
355		else if ( state->m_atapi_data_ptr == 12 )
356		{
357		int phase;
358		// reset data pointer for reading SCSI results
359		state->m_atapi_data_ptr = 0;
360		state->m_atapi_data_len = 0;
	355	else if ( state->m_atapi_data_ptr == 12 )
	356	{
	357	int phase;
	358	// reset data pointer for reading SCSI results
	359	state->m_atapi_data_ptr = 0;
	360	state->m_atapi_data_len = 0;
361	361
362		// send it to the SCSI device
363		SCSISetCommand( state->m_inserted_cdrom, state->m_atapi_data, 12 );
364		SCSIExecCommand( state->m_inserted_cdrom, &state->m_atapi_xferlen );
365		SCSIGetPhase( state->m_inserted_cdrom, &phase );
	362	// send it to the SCSI device
	363	SCSISetCommand( state->m_inserted_cdrom, state->m_atapi_data, 12 );
	364	SCSIExecCommand( state->m_inserted_cdrom, &state->m_atapi_xferlen );
	365	SCSIGetPhase( state->m_inserted_cdrom, &phase );
366	366
367		if (state->m_atapi_xferlen != -1)
368		{
369		logerror("ATAPI: SCSI command %02x returned %d bytes from the device\n", atapi_data[0]&0xff, state->m_atapi_xferlen);
	367	if (state->m_atapi_xferlen != -1)
	368	{
	369	logerror("ATAPI: SCSI command %02x returned %d bytes from the device\n", atapi_data[0]&0xff, state->m_atapi_xferlen);
370	370
371		// store the returned command length in the ATAPI regs, splitting into
372		// multiple transfers if necessary
373		state->m_atapi_xfermod = 0;
374		if (state->m_atapi_xferlen > MAX_TRANSFER_SIZE)
375		{
376		state->m_atapi_xfermod = state->m_atapi_xferlen - MAX_TRANSFER_SIZE;
377		state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
378		}
379
380		atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
381		atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
	371	// store the returned command length in the ATAPI regs, splitting into
	372	// multiple transfers if necessary
	373	state->m_atapi_xfermod = 0;
	374	if (state->m_atapi_xferlen > MAX_TRANSFER_SIZE)
	375	{
	376	state->m_atapi_xfermod = state->m_atapi_xferlen - MAX_TRANSFER_SIZE;
	377	state->m_atapi_xferlen = MAX_TRANSFER_SIZE;
	378	}
382	379
383		if (state->m_atapi_xferlen == 0)
384		{
385		// if no data to return, set the registers properly
386		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRDY;
387		atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO\|ATAPI_INTREASON_COMMAND;
388		}
389		else
390		{
391		// indicate data ready: set DRQ and DMA ready, and IO in INTREASON
392		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_SERVDSC;
393		atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
394		}
	380	atapi_regs[ATAPI_REG_COUNTLOW] = state->m_atapi_xferlen & 0xff;
	381	atapi_regs[ATAPI_REG_COUNTHIGH] = (state->m_atapi_xferlen>>8)&0xff;
395	382
396		switch( phase )
397		{
398		case SCSI_PHASE_DATAOUT:
399		state->m_atapi_cdata_wait = state->m_atapi_xferlen;
400		break;
401		}
	383	if (state->m_atapi_xferlen == 0)
	384	{
	385	// if no data to return, set the registers properly
	386	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRDY;
	387	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO\|ATAPI_INTREASON_COMMAND;
	388	}
	389	else
	390	{
	391	// indicate data ready: set DRQ and DMA ready, and IO in INTREASON
	392	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_SERVDSC;
	393	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_IO;
	394	}
402	395
403		// perform special ATAPI processing of certain commands
404		switch (atapi_data[0]&0xff)
405		{
406		case 0x00: // BUS RESET / TEST UNIT READY
407		case 0xbb: // SET CDROM SPEED
408		atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
409		break;
	396	switch( phase )
	397	{
	398	case SCSI_PHASE_DATAOUT:
	399	state->m_atapi_cdata_wait = state->m_atapi_xferlen;
	400	break;
	401	}
410	402
411		case 0x45: // PLAY
412		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_BSY;
413		state->m_atapi_timer->adjust( downcast<cpu_device *>(&space->device())->cycles_to_attotime( ATAPI_CYCLES_PER_SECTOR ) );
414		break;
415		}
	403	// perform special ATAPI processing of certain commands
	404	switch (atapi_data[0]&0xff)
	405	{
	406	case 0x00: // BUS RESET / TEST UNIT READY
	407	case 0xbb: // SET CDROM SPEED
	408	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	409	break;
416	410
417		// assert IRQ
418		atapi_irq(space.machine(), ASSERT_LINE);
419		}
420		else
421		{
422		logerror("ATAPI: SCSI device returned error!\n");
	411	case 0x45: // PLAY
	412	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_BSY;
	413	state->m_atapi_timer->adjust( downcast<cpu_device *>(&space->device())->cycles_to_attotime( ATAPI_CYCLES_PER_SECTOR ) );
	414	break;
	415	}
423	416
424		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_CHECK;
425		atapi_regs[ATAPI_REG_ERRFEAT] = 0x50; // sense key = ILLEGAL REQUEST
426		atapi_regs[ATAPI_REG_COUNTLOW] = 0;
427		atapi_regs[ATAPI_REG_COUNTHIGH] = 0;
428		}
429		}
430		}
431		else
432		{
433		reg = offset<<2;
434		switch(mem_mask)
435		{
436		case 0x000000ff:
437		break;
438		case 0x0000ff00:
439		reg+=1;
440		data >>= 8;
441		break;
442		case 0x00ff0000:
443		reg+=2;
444		data >>=16;
445		break;
446		case 0xff000000:
447		reg+=3;
448		data >>=24;
449		break;
450		}
	417	// assert IRQ
	418	atapi_irq(space.machine(), ASSERT_LINE);
	419	}
	420	else
	421	{
	422	logerror("ATAPI: SCSI device returned error!\n");
451	423
452		atapi_regs[reg] = data;
453		logerror("ATAPI: reg %d = %x (offset %x mask %x PC=%x)\n", reg, data, offset, mem_mask, cpu_get_pc(&space->device()));
	424	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ \| ATAPI_STAT_CHECK;
	425	atapi_regs[ATAPI_REG_ERRFEAT] = 0x50; // sense key = ILLEGAL REQUEST
	426	atapi_regs[ATAPI_REG_COUNTLOW] = 0;
	427	atapi_regs[ATAPI_REG_COUNTHIGH] = 0;
	428	}
	429	}
	430	}
	431	else
	432	{
	433	reg = offset<<2;
	434	switch(mem_mask)
	435	{
	436	case 0x000000ff:
	437	break;
	438	case 0x0000ff00:
	439	reg+=1;
	440	data >>= 8;
	441	break;
	442	case 0x00ff0000:
	443	reg+=2;
	444	data >>=16;
	445	break;
	446	case 0xff000000:
	447	reg+=3;
	448	data >>=24;
	449	break;
	450	}
454	451
455		if (reg == ATAPI_REG_CMDSTATUS)
456		{
457		logerror("ATAPI command %x issued! (PC=%x)\n", data, cpu_get_pc(&space->device()));
458		switch (data)
459		{
460		case 0xa0: // PACKET
461		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
462		atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_COMMAND;
	452	atapi_regs[reg] = data;
	453	logerror("ATAPI: reg %d = %x (offset %x mask %x PC=%x)\n", reg, data, offset, mem_mask, cpu_get_pc(&space->device()));
463	454
464		state->m_atapi_data_ptr = 0;
465		state->m_atapi_data_len = 0;
	455	if (reg == ATAPI_REG_CMDSTATUS)
	456	{
	457	logerror("ATAPI command %x issued! (PC=%x)\n", data, cpu_get_pc(&space->device()));
	458	switch (data)
	459	{
	460	case 0xa0: // PACKET
	461	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
	462	atapi_regs[ATAPI_REG_INTREASON] = ATAPI_INTREASON_COMMAND;
466	463
467		// we have no data
468		state->m_atapi_xferlen = 0;
469		state->m_atapi_xfermod = 0;
	464	state->m_atapi_data_ptr = 0;
	465	state->m_atapi_data_len = 0;
470	466
471		state->m_atapi_cdata_wait = 0;
472		break;
	467	// we have no data
	468	state->m_atapi_xferlen = 0;
	469	state->m_atapi_xfermod = 0;
473	470
474		case 0xa1: // IDENTIFY PACKET DEVICE
475		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
	471	state->m_atapi_cdata_wait = 0;
	472	break;
476	473
477		state->m_atapi_data_ptr = 0;
478		state->m_atapi_data_len = 512;
	474	case 0xa1: // IDENTIFY PACKET DEVICE
	475	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_DRQ;
479	476
480		// we have no data
481		state->m_atapi_xferlen = 0;
482		state->m_atapi_xfermod = 0;
	477	state->m_atapi_data_ptr = 0;
	478	state->m_atapi_data_len = 512;
483	479
484		memset( atapi_data, 0, state->m_atapi_data_len );
	480	// we have no data
	481	state->m_atapi_xferlen = 0;
	482	state->m_atapi_xfermod = 0;
485	483
486		atapi_data[ 0 ^ 1 ] = 0x85; // ATAPI device, cmd set 5 compliant, DRQ within 3 ms of PACKET command
487		atapi_data[ 1 ^ 1 ] = 0x80; // ATAPI device, removable media
	484	memset( atapi_data, 0, state->m_atapi_data_len );
488	485
489		memset( &atapi_data[ 46 ], ' ', 8 );
490		atapi_data[ 46 ^ 1 ] = '1';
491		atapi_data[ 47 ^ 1 ] = '.';
492		atapi_data[ 48 ^ 1 ] = '0';
493
494
495		memset( &atapi_data[ 54 ], ' ', 40 );
496		atapi_data[ 54 ^ 1 ] = 'T';
497		atapi_data[ 55 ^ 1 ] = 'O';
498		atapi_data[ 56 ^ 1 ] = 'S';
499		atapi_data[ 57 ^ 1 ] = 'H';
500		atapi_data[ 58 ^ 1 ] = 'I';
501		atapi_data[ 59 ^ 1 ] = 'B';
502		atapi_data[ 60 ^ 1 ] = 'A';
503		atapi_data[ 61 ^ 1 ] = ' ';
504		atapi_data[ 62 ^ 1 ] = 'X';
505		atapi_data[ 63 ^ 1 ] = 'M';
506		atapi_data[ 64 ^ 1 ] = '-';
507		atapi_data[ 65 ^ 1 ] = '3';
508		atapi_data[ 66 ^ 1 ] = '3';
509		atapi_data[ 67 ^ 1 ] = '0';
510		atapi_data[ 68 ^ 1 ] = '1';
511		atapi_data[ 69 ^ 1 ] = ' ';
	486	atapi_data[ 0 ^ 1 ] = 0x85; // ATAPI device, cmd set 5 compliant, DRQ within 3 ms of PACKET command
	487	atapi_data[ 1 ^ 1 ] = 0x80; // ATAPI device, removable media
512	488
513		atapi_data[ 98 ^ 1 ] = 0x06; // Word 49=Capabilities, IORDY may be disabled (bit_10), LBA Supported mandatory (bit_9)
514		atapi_data[ 99 ^ 1 ] = 0x00;
	489	memset( &atapi_data[ 46 ], ' ', 8 );
	490	atapi_data[ 46 ^ 1 ] = '1';
	491	atapi_data[ 47 ^ 1 ] = '.';
	492	atapi_data[ 48 ^ 1 ] = '0';
515	493
516		atapi_regs[ATAPI_REG_COUNTLOW] = 0;
517		atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
518	494
519		atapi_irq(space.machine(), ASSERT_LINE);
520		break;
521		case 0xec: //IDENTIFY DEVICE - Must abort here and set for packet data
522		atapi_regs[ATAPI_REG_ERRFEAT] = ATAPI_ERRFEAT_ABRT;
523		atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_CHECK;
524
525		atapi_irq(space.machine(), ASSERT_LINE);
526
527		case 0xef: // SET FEATURES
528		atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	495	memset( &atapi_data[ 54 ], ' ', 40 );
	496	atapi_data[ 54 ^ 1 ] = 'T';
	497	atapi_data[ 55 ^ 1 ] = 'O';
	498	atapi_data[ 56 ^ 1 ] = 'S';
	499	atapi_data[ 57 ^ 1 ] = 'H';
	500	atapi_data[ 58 ^ 1 ] = 'I';
	501	atapi_data[ 59 ^ 1 ] = 'B';
	502	atapi_data[ 60 ^ 1 ] = 'A';
	503	atapi_data[ 61 ^ 1 ] = ' ';
	504	atapi_data[ 62 ^ 1 ] = 'X';
	505	atapi_data[ 63 ^ 1 ] = 'M';
	506	atapi_data[ 64 ^ 1 ] = '-';
	507	atapi_data[ 65 ^ 1 ] = '3';
	508	atapi_data[ 66 ^ 1 ] = '3';
	509	atapi_data[ 67 ^ 1 ] = '0';
	510	atapi_data[ 68 ^ 1 ] = '1';
	511	atapi_data[ 69 ^ 1 ] = ' ';
529	512
530		state->m_atapi_data_ptr = 0;
531		state->m_atapi_data_len = 0;
	513	atapi_data[ 98 ^ 1 ] = 0x06; // Word 49=Capabilities, IORDY may be disabled (bit_10), LBA Supported mandatory (bit_9)
	514	atapi_data[ 99 ^ 1 ] = 0x00;
532	515
533		atapi_irq(space.machine(), ASSERT_LINE);
534		break;
	516	atapi_regs[ATAPI_REG_COUNTLOW] = 0;
	517	atapi_regs[ATAPI_REG_COUNTHIGH] = 2;
535	518
536		default:
537		logerror("ATAPI: Unknown IDE command %x\n", data);
538		break;
539		}
540		}
541		}
	519	atapi_irq(space.machine(), ASSERT_LINE);
	520	break;
	521	case 0xec: //IDENTIFY DEVICE - Must abort here and set for packet data
	522	atapi_regs[ATAPI_REG_ERRFEAT] = ATAPI_ERRFEAT_ABRT;
	523	atapi_regs[ATAPI_REG_CMDSTATUS] = ATAPI_STAT_CHECK;
	524
	525	atapi_irq(space.machine(), ASSERT_LINE);
	526
	527	case 0xef: // SET FEATURES
	528	atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
	529
	530	state->m_atapi_data_ptr = 0;
	531	state->m_atapi_data_len = 0;
	532
	533	atapi_irq(space.machine(), ASSERT_LINE);
	534	break;
	535
	536	default:
	537	logerror("ATAPI: Unknown IDE command %x\n", data);
	538	break;
	539	}
	540	}
	541	}
542	542	}
543	543	*/
544	544	// Memory is mostly handled by the chipset
r18326	r18327
569	569	AM_RANGE(0x03f0, 0x0cf7) AM_NOP
570	570	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
571	571	AM_RANGE(0x0400, 0xffff) AM_NOP
572
573	572
	573
574	574	ADDRESS_MAP_END
575	575
576	576	#define AT_KEYB_HELPER(bit, text, key1) \
r18326	r18327
596	596	AT_KEYB_HELPER( 0x0800, "F1", KEYCODE_S ) /* F1 3B BB */
597	597	AT_KEYB_HELPER( 0x1000, "F2", KEYCODE_D ) /* F2 3C BC */
598	598	AT_KEYB_HELPER( 0x4000, "F4", KEYCODE_F ) /* F4 3E BE */
599
600	599
	600
601	601	PORT_START("pc_keyboard_4")
602	602	AT_KEYB_HELPER( 0x0004, "F8", KEYCODE_F8 ) // f8=42 /f10=44 /minus 4a /plus=4e
603	603	AT_KEYB_HELPER( 0x0010, "F10", KEYCODE_F10 ) // f8=42 /f10=44 /minus 4a /plus=4e
r18326	r18327
607	607
608	608	PORT_START("pc_keyboard_5")
609	609	AT_KEYB_HELPER( 0x0001, "KP 2(DN)", KEYCODE_2_PAD ) /* Keypad 2 (Down arrow) 50 D0 */
610
	610
611	611	PORT_START("pc_keyboard_6")
612	612	AT_KEYB_HELPER( 0x0040, "(MF2)Cursor Up", KEYCODE_UP ) /* Up 67 e7 */
613	613	AT_KEYB_HELPER( 0x0080, "(MF2)Page Up", KEYCODE_PGUP ) /* Page Up 68 e8 */
r18326	r18327
643	643	static MACHINE_RESET( gammagic )
644	644	{
645	645	//gammagic_state *state = machine.driver_data<gammagic_state>();
646
	646
647	647	//void *cd;
648		//SCSIGetDevice( state->m_inserted_cdrom, &cd );
649
	648	//SCSIGetDevice( state->m_inserted_cdrom, &cd );
	649
650	650	}
651	651
652	652
653	653	/*static void atapi_irq(running_machine &machine, int state)
654	654	{
655		gammagic_state *drvstate = machine.driver_data<gammagic_state>();
656		pic8259_ir6_w(drvstate->m_pic8259_2, state);
	655	gammagic_state *drvstate = machine.driver_data<gammagic_state>();
	656	pic8259_ir6_w(drvstate->m_pic8259_2, state);
657	657	}
658	658
659	659	static void atapi_exit(running_machine& machine)
660	660	{
661		gammagic_state *state = machine.driver_data<gammagic_state>();
662		SCSIDeleteInstance(state->m_inserted_cdrom);
	661	gammagic_state *state = machine.driver_data<gammagic_state>();
	662	SCSIDeleteInstance(state->m_inserted_cdrom);
663	663
664	664	}
665	665	*/
r18326	r18327
667	667	static void atapi_init(running_machine &machine)
668	668	{
669	669	gammagic_state *state = machine.driver_data<gammagic_state>();
670
	670
671	671	state->m_atapi_regs[ATAPI_REG_CMDSTATUS] = 0;
672	672	state->m_atapi_regs[ATAPI_REG_ERRFEAT] = 1;
673	673	state->m_atapi_regs[ATAPI_REG_COUNTLOW] = 0x14;
r18326	r18327
675	675	state->m_atapi_data_ptr = 0;
676	676	state->m_atapi_data_len = 0;
677	677	state->m_atapi_cdata_wait = 0;
678
	678
679	679	//SCSIAllocInstance( machine, &SCSIClassCr589, &state->m_inserted_cdrom, ":cdrom" );
680
	680
681	681	//machine.add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(atapi_exit), &machine));
682	682
683	683	}
r18326	r18327
782	782	MCFG_PIC8259_ADD( "pic8259_1", gammagic_pic8259_1_config )
783	783	MCFG_PIC8259_ADD( "pic8259_2", gammagic_pic8259_2_config )
784	784	MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
785		// MCFG_I82371SB_ADD("i82371sb")
786		// MCFG_I82439TX_ADD("i82439tx", "maincpu", "user")
	785	// MCFG_I82371SB_ADD("i82371sb")
	786	// MCFG_I82439TX_ADD("i82439tx", "maincpu", "user")
787	787	MCFG_PCI_BUS_ADD("pcibus", 0)
788		// MCFG_PCI_BUS_DEVICE(0, "i82439tx", i82439tx_pci_read, i82439tx_pci_write)
789		// MCFG_PCI_BUS_DEVICE(1, "i82371sb", i82371sb_pci_read, i82371sb_pci_write)
	788	// MCFG_PCI_BUS_DEVICE(0, "i82439tx", i82439tx_pci_read, i82439tx_pci_write)
	789	// MCFG_PCI_BUS_DEVICE(1, "i82371sb", i82371sb_pci_read, i82371sb_pci_write)
790	790	/* video hardware */
791	791	MCFG_FRAGMENT_ADD( pcvideo_vga )
792	792
r18326	r18327
797	797	{
798	798	init_pc_common(machine(), PCCOMMON_KEYBOARD_AT, gammagic_set_keyb_int);
799	799	kbdc8042_init(machine(), &at8042);
800		atapi_init(machine());
801		}
	800	atapi_init(machine());
	801	}
802	802
803	803	ROM_START( gammagic )
804	804	ROM_REGION32_LE(0x40000, "user", 0)
805		//Original Memory Set
	805	//Original Memory Set
806	806	//ROM_LOAD("m7s04.rom", 0, 0x40000, CRC(3689f5a9) SHA1(8daacdb0dc6783d2161680564ffe83ac2515f7ef))
807	807	//ROM_LOAD("otivga_tx2953526.rom", 0x0000, 0x8000, CRC(916491af) SHA1(d64e3a43a035d70ace7a2d0603fc078f22d237e1))
808
	808
809	809	//Temp. Memory Set (Only for initial driver development stage)
810	810	ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
811	811	ROM_CONTINUE( 0x0001, 0x4000 )
812	812	ROM_LOAD("5hx29.bin", 0x20000, 0x20000, CRC(07719a55) SHA1(b63993fd5186cdb4f28c117428a507cd069e1f68))
813
	813
814	814	DISK_REGION( "cdrom" )
815	815	DISK_IMAGE_READONLY( "gammagic", 0,SHA1(caa8fc885d84dbc07fb0604c76cd23c873a65ce6) )
816	816	ROM_END
817	817
818	818	ROM_START( 99bottles )
819	819	ROM_REGION32_LE(0x40000, "user", 0)
820		//Original BIOS/VGA-BIOS Rom Set
821		//ROM_LOAD("m7s04.rom", 0, 0x40000, CRC(3689f5a9) SHA1(8daacdb0dc6783d2161680564ffe83ac2515f7ef))
	820	//Original BIOS/VGA-BIOS Rom Set
	821	//ROM_LOAD("m7s04.rom", 0, 0x40000, CRC(3689f5a9) SHA1(8daacdb0dc6783d2161680564ffe83ac2515f7ef))
822	822	//ROM_LOAD("otivga_tx2953526.rom", 0x0000, 0x8000, CRC(916491af) SHA1(d64e3a43a035d70ace7a2d0603fc078f22d237e1))
823
	823
824	824	//Temporary (Chipset compatible Rom Set, only for driver development stage)
825	825	ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
826	826	ROM_CONTINUE( 0x0001, 0x4000 )

trunk/src/mame/drivers/cdi.c
r18326	r18327
625	625
626	626	// The Quizard games are RETAIL CD-i units, with additional JAMMA adapters & dongles for protection, hence being 'clones' of the system.
627	627
628		GAME( 1995, cdibios, 0, cdi_base, quizard, driver_device, 0, ROT0, "Philips", "CD-i Bios", GAME_IMPERFECT_SOUND \| GAME_IMPERFECT_GRAPHICS \| GAME_IS_BIOS_ROOT )
	628	GAME( 1995, cdibios, 0, cdi_base, quizard, driver_device, 0, ROT0, "Philips", "CD-i Bios", GAME_IMPERFECT_SOUND \| GAME_IMPERFECT_GRAPHICS \| GAME_IS_BIOS_ROOT )
629	629	// Working
630	630	GAME( 1995, quizrd12, cdibios, quizrd12, quizard, driver_device, 0, ROT0, "TAB Austria", "Quizard 1.2", GAME_IMPERFECT_SOUND \| GAME_UNEMULATED_PROTECTION )
631	631	GAME( 1995, quizrd17, cdibios, quizrd17, quizard, driver_device, 0, ROT0, "TAB Austria", "Quizard 1.7", GAME_IMPERFECT_SOUND \| GAME_UNEMULATED_PROTECTION )

trunk/src/mame/drivers/nsm.c
r18326	r18327
90	90	m_cru_data[m_cru_count] = 0;
91	91	}
92	92	m_cru_data[m_cru_count] \|= (data << offset);
93
	93
94	94	UINT8 i,j;
95	95	int segments;
96	96	if (!m_cru_count && (offset == 7))

trunk/src/mame/drivers/queen.c
r18326	r18327
543	543	AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
544	544	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
545	545	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
546		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	546	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
547	547	AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
548	548
549	549	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

trunk/src/mame/drivers/xtom3d.c
r18326	r18327
551	551	AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
552	552	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
553	553	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
554		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	554	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
555	555	AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
556	556
557	557	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

trunk/src/mame/drivers/jpmsys5.c
r18326	r18327
12	12	* Monopoly Deluxe
13	13
14	14	Known Issues:
15		* Some features used by the AWP games such as reels and meters
16		are not emulated.
17		* Timing for reels, and other opto devices is controlled by the same clock
18		as the lamps, in a weird daisychain setup.
	15	* Some features used by the AWP games such as reels and meters
	16	are not emulated.
	17	* Timing for reels, and other opto devices is controlled by the same clock
	18	as the lamps, in a weird daisychain setup.
19	19
20	20	AWP game notes:
21	21	The byte at 0x81 of the EVEN 68k rom appears to be some kind of
r18326	r18327
766	766	{
767	767	case 2:
768	768	{
769		return ioport("COINS")->read() << 8;
	769	return ioport("COINS")->read() << 8;
770	770	}
771	771	break;
772	772	default:
r18326	r18327
856	856	PORT_CONFSETTING( 0x02, "13")
857	857	PORT_CONFSETTING( 0x01, "14")
858	858	PORT_CONFSETTING( 0x00, "15")
859
	859
860	860	PORT_START("DIRECT")
861	861	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Back door") PORT_CODE(KEYCODE_R) PORT_TOGGLE
862	862	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Cash door") PORT_CODE(KEYCODE_T) PORT_TOGGLE

trunk/src/mame/drivers/ninjakd2.c
r18326	r18327
911	911	int num_banks = (machine().root_device().memregion("maincpu")->bytes() - 0x10000) / 0x4000;
912	912	machine().root_device().membank("bank1")->configure_entries(0, num_banks, machine().root_device().memregion("maincpu")->base() + 0x10000, 0x4000);
913	913	machine().root_device().membank("bank1")->set_entry(0);
914
	914
915	915	m_rom_bank_mask = num_banks - 1;
916	916	}
917	917
918	918	MACHINE_START_MEMBER(ninjakd2_state,omegaf)
919	919	{
920	920	omegaf_io_protection_start();
921
	921
922	922	machine_start();
923	923	}
924	924
925	925	MACHINE_RESET_MEMBER(ninjakd2_state,omegaf)
926	926	{
927	927	omegaf_io_protection_reset();
928
	928
929	929	machine_reset();
930	930	}
931	931
r18326	r18327
1481	1481	ROM[1] = 0x03; // and 3
1482	1482	ROM[2] = 0x18;
1483	1483	ROM[3] = 0xf6; // jr $-8
1484
	1484
1485	1485	m_maincpu->space(AS_PROGRAM).install_read_handler(offset, offset, read8_delegate(FUNC(ninjakd2_state::robokid_motion_error_verbose_r), this));
1486	1486	}
1487	1487

trunk/src/mame/drivers/pipedrm.c
r18326	r18327
191	191	state->membank("bank1")->set_entry(data & 0x7);
192	192
193	193	/* map to the fromance gfx register */
194		state->fromance_gfxreg_w(space, offset, ((data >> 6) & 0x01) \| /* flipscreen */
	194	state->fromance_gfxreg_w(space, offset, ((data >> 6) & 0x01) \| /* flipscreen */
195	195	((~data >> 2) & 0x02)); /* videoram select */
196	196	}
197	197

trunk/src/mame/drivers/mediagx.c
r18326	r18327
186	186	virtual void machine_reset();
187	187	virtual void video_start();
188	188	UINT32 screen_update_mediagx(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
189		DECLARE_READ32_MEMBER(speedup0_r);
190		DECLARE_READ32_MEMBER(speedup1_r);
191		DECLARE_READ32_MEMBER(speedup2_r);
192		DECLARE_READ32_MEMBER(speedup3_r);
193		DECLARE_READ32_MEMBER(speedup4_r);
194		DECLARE_READ32_MEMBER(speedup5_r);
195		DECLARE_READ32_MEMBER(speedup6_r);
196		DECLARE_READ32_MEMBER(speedup7_r);
197		DECLARE_READ32_MEMBER(speedup8_r);
198		DECLARE_READ32_MEMBER(speedup9_r);
199		DECLARE_READ32_MEMBER(speedup10_r);
200		DECLARE_READ32_MEMBER(speedup11_r);
	189	DECLARE_READ32_MEMBER(speedup0_r);
	190	DECLARE_READ32_MEMBER(speedup1_r);
	191	DECLARE_READ32_MEMBER(speedup2_r);
	192	DECLARE_READ32_MEMBER(speedup3_r);
	193	DECLARE_READ32_MEMBER(speedup4_r);
	194	DECLARE_READ32_MEMBER(speedup5_r);
	195	DECLARE_READ32_MEMBER(speedup6_r);
	196	DECLARE_READ32_MEMBER(speedup7_r);
	197	DECLARE_READ32_MEMBER(speedup8_r);
	198	DECLARE_READ32_MEMBER(speedup9_r);
	199	DECLARE_READ32_MEMBER(speedup10_r);
	200	DECLARE_READ32_MEMBER(speedup11_r);
201	201	TIMER_DEVICE_CALLBACK_MEMBER(sound_timer_callback);
202	202	};
203	203

trunk/src/mame/drivers/deshoros.c
r18326	r18327
59	59	virtual void machine_start();
60	60	virtual void machine_reset();
61	61	virtual void video_start();
62		public:
	62	public:
63	63	UINT32 screen_update_destiny(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
64	64	};
65	65

trunk/src/mame/drivers/ggconnie.c
r18326	r18327
30	30	: pce_common_state(mconfig, type, tag) { }
31	31
32	32	DECLARE_WRITE8_MEMBER(lamp_w);
33		DECLARE_WRITE8_MEMBER(output_w);
	33	DECLARE_WRITE8_MEMBER(output_w);
34	34	};
35	35
36	36

trunk/src/mame/drivers/8080bw.c
r18326	r18327
2343	2343
2344	2344	TIMER_DEVICE_CALLBACK_MEMBER(_8080bw_state::claybust_gun_callback)
2345	2345	{
2346
	2346
2347	2347	// reset gun latch
2348	2348	m_claybust_gun_pos = 0;
2349	2349	}
r18326	r18327
2358	2358	if (newval)
2359	2359	{
2360	2360	/*
2361		The game registers a valid shot after the gun trigger is pressed, and IN1 d0 is high.
2362		It latches the gun position and then compares it with VRAM contents: 1 byte/8 pixels, 0 means miss.
2363		IN1 d0 probably indicates if the latch is ready or not (glitches happen otherwise)
	2361	The game registers a valid shot after the gun trigger is pressed, and IN1 d0 is high.
	2362	It latches the gun position and then compares it with VRAM contents: 1 byte/8 pixels, 0 means miss.
	2363	IN1 d0 probably indicates if the latch is ready or not (glitches happen otherwise)
2364	2364
2365		in $06
2366		cpi $04
2367		rc
2368		mov h,a
2369		in $02
2370		mov l,a
2371		lxi d,$1ffe <-- this is where the +2 comes from
2372		dad d
2373		out $00
2374		mov a,m
2375		ana a
2376		rz
2377		*/
	2365	in $06
	2366	cpi $04
	2367	rc
	2368	mov h,a
	2369	in $02
	2370	mov l,a
	2371	lxi d,$1ffe <-- this is where the +2 comes from
	2372	dad d
	2373	out $00
	2374	mov a,m
	2375	ana a
	2376	rz
	2377	*/
2378	2378	UINT8 gunx = ioport("GUNX")->read_safe(0x00);
2379	2379	UINT8 guny = ioport("GUNY")->read_safe(0x20);
2380	2380	m_claybust_gun_pos = ((gunx >> 3) \| (guny << 5)) + 2;
r18326	r18327
2426	2426
2427	2427	static INPUT_PORTS_START( gunchamp )
2428	2428	PORT_INCLUDE( claybust )
2429
	2429
2430	2430	PORT_MODIFY("IN1")
2431	2431
2432	2432	// switch is 6-pos, but DNS06:5 and DNS06:6 are not connected
r18326	r18327
2461	2461
2462	2462	MCFG_TIMER_DRIVER_ADD("claybust_gun", _8080bw_state, claybust_gun_callback)
2463	2463
2464		MCFG_MACHINE_START_OVERRIDE(_8080bw_state, claybust)
	2464	MCFG_MACHINE_START_OVERRIDE(_8080bw_state, claybust)
2465	2465
2466	2466	/* sound hardware */
2467	2467	// TODO: discrete sound

trunk/src/mame/drivers/vlc.c
r18326	r18327
13	13	- 2x 62256 NVRAM + batt (connect in 16bits)
14	14	- 2x 6264 BACKUP + batt (connect in 8bits)
15	15	- 1x MODEM XE1214 from XECOM (300/1200 Baud)
16
17
18
	16
	17
	18
19	19	on MAME 0.145u4
20	20	Yves
21	21	Todo :
r18326	r18327
37	37
38	38	U50 4Bit D Flop Register is connect on D3..D0
39	39	this one seem to have 2 use.
40		1. keep track of the PAL16R8 state
	40	1. keep track of the PAL16R8 state
41	41	2. DOOR SWITCH is connect on U50 Clear pin (D3..D0 LOW = Door Open)
42	42	Write Clock 4 bits in D-Flop Register
43	43	Read OE 4 bits on D3..D0
r18326	r18327
89	89	BOOT:FE1AA9 0000 dc.b 0
90	90
91	91
92		BOOT:FE19F0 INI_CRTC6845:
	92	BOOT:FE19F0 INI_CRTC6845:
93	93	BOOT:FE19F0 48E7 8140 movem.l d0/d7/a1,-(sp)
94	94	BOOT:FE19F4 2258 movea.l (a0)+,a1 * type1 = 0xA50000, type2 = 0xA80000
95	95	BOOT:FE19F6 50D1 st (a1)
r18326	r18327
102	102	BOOT:FE1A0A * A0 = 0xB00000
103	103	BOOT:FE1A0E 7E0D moveq #$D,d7
104	104	BOOT:FE1A10
105		BOOT:FE1A10 LOOP:
	105	BOOT:FE1A10 LOOP:
106	106	BOOT:FE1A10 13C7 0090 0001 move.b d7,(CRTC_ADR)
107	107	BOOT:FE1A16 13D9 0090 8001 move.b (a1)+,(CRTC_DAT)
108	108	BOOT:FE1A1C 51CF FFF2 dbf d7,LOOP
r18326	r18327
111	111
112	112
113	113	* MC6845 Initialization *
114		Htotal Hdisp HsyncPos HsyncW Vtotal VtotalAdj Vdisp VsyncPos InterMode MaxScanAdr CurStart CurEnd StartAdrH StartAdrL CurH CurL LightPenH LightPenL
	114	Htotal Hdisp HsyncPos HsyncW Vtotal VtotalAdj Vdisp VsyncPos InterMode MaxScanAdr CurStart CurEnd StartAdrH StartAdrL CurH CurL LightPenH LightPenL
115	115	-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
116	116	register: 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17
117	117	-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
118	118	nevada TYPE1 : 42 31 35 03 32 02 31 31 00 07 00 00 00 00 00 00 00 00
119	119	nevada TYPE2 : 64 45 51 06 32 02 31 31 00 07 00 00 00 00 00 00 00 00
120
	120
121	121	*/
122	122
123	123
r18326	r18327
160	160	device_t *m_duart18_68681;
161	161	device_t *m_duart39_68681;
162	162	device_t *m_duart40_68681;
163
	163
164	164	required_device<cpu_device> m_maincpu;
165	165	optional_device<microtouch_device> m_microtouch;
166	166
167	167	required_shared_ptr<UINT16> m_nvram;
168	168	required_shared_ptr<UINT16> m_backup;
169
	169
170	170	UINT16 m_datA40000;
171
	171
172	172	//UINT8* m_videoram;
173	173	//UINT8* m_colorram;
174
	174
175	175	UINT16* m_videoram;
176	176	tilemap_t *m_bg_tilemap;
177	177
178
	178
179	179	DECLARE_DRIVER_INIT(nevada);
180	180	};
181	181
r18326	r18327
185	185
186	186	PAL is connected on the UPPER byte D15..D8
187	187	Adress A40000..A40001
188		2 Type of PAL (one for game, the other is to set game to fabric default)
	188	2 Type of PAL (one for game, the other is to set game to fabric default)
189	189
190		there is a 74LS173 on the LOWER byte that used bit D3..D0
	190	there is a 74LS173 on the LOWER byte that used bit D3..D0
191	191	funny thing , the DOOR ACCESS Switch is connected on the CLEAR PIN of this 4bits register
192	192	so when D3..D0 are LOW , DOOR is OPEN
193	193	*/
194	194	static const UINT8 pal35[256] = {
195		0x11, 0x42, 0x5B, 0xCA, 0x19, 0x42, 0x5B, 0xCA, 0x38, 0x63, 0x3A, 0x63, 0x3A, 0x63, 0x3A, 0x63,
196		0xD3, 0x08, 0x5B, 0xCA, 0x19, 0xCA, 0x19, 0xCA, 0x18, 0xEB, 0x18, 0xEB, 0x18, 0xEB, 0x18, 0xEB,
197		0xD3, 0xCA, 0x5B, 0xCC, 0x5B, 0xCC, 0x5B, 0xCC, 0xBA, 0x63, 0x38, 0x65, 0x38, 0x65, 0x38, 0x65,
198		0xD1, 0xCA, 0x5B, 0xC8, 0x5B, 0xC8, 0x5B, 0xC8, 0x9A, 0xEB, 0x1A, 0xED, 0x1A, 0xED, 0x1A, 0xED,
199		0x0C, 0x65, 0xF0, 0x00, 0x64, 0xF5, 0x04, 0x65, 0xB8, 0x25, 0x20, 0x20, 0x24, 0x24, 0x24, 0x24,
200		0xF0, 0x00, 0xF8, 0x00, 0xFC, 0x00, 0xFC, 0x00, 0xB8, 0x3D, 0xFC, 0x19, 0xFC, 0x19, 0xFC, 0x19,
201		0x44, 0xF9, 0xC4, 0xF9, 0xC4, 0xFD, 0xC4, 0xFD, 0xFC, 0xFD, 0xFC, 0xFD, 0xFC, 0xFD, 0xFC, 0xFD,
202		0xC0, 0xD9, 0xC8, 0xD9, 0xC8, 0xD9, 0xC8, 0xD9, 0xD8, 0xD9, 0xD8, 0xD9, 0xD8, 0xD9, 0xD8, 0xD9,
203		0x0C, 0x44, 0xFB, 0x04, 0x67, 0xD4, 0x0C, 0x44, 0xBA, 0x24, 0x22, 0x02, 0x26, 0x06, 0x26, 0x06,
204		0xFB, 0x00, 0xFB, 0x00, 0xEF, 0x10, 0xCE, 0x18, 0xEF, 0x18, 0xEF, 0x18, 0xFF, 0x18, 0xFF, 0x18,
205		0x44, 0xF8, 0xC6, 0xD8, 0xCE, 0xDC, 0xCE, 0xDC, 0xEF, 0x9E, 0x67, 0xB8, 0x67, 0xBC, 0x67, 0xBC,
206		0xC6, 0xD8, 0xCA, 0xD8, 0xCA, 0xD8, 0xCA, 0xD8, 0xCB, 0x9A, 0xEF, 0x9A, 0xFF, 0xD8, 0xDB, 0xD8,
207		0x66, 0xF4, 0x00, 0x64, 0xBA, 0x25, 0x22, 0x22, 0x26, 0x26, 0x26, 0x26, 0xF2, 0x00, 0xFA, 0x00,
208		0xFA, 0x00, 0xFA, 0x00, 0xBA, 0x3D, 0xFA, 0x19, 0xFA, 0x19, 0xFA, 0x19, 0x44, 0xF9, 0xC2, 0xF0,
209		0xC2, 0xF4, 0xC2, 0xF4, 0xFA, 0xF4, 0xFA, 0xF4, 0xFA, 0xF4, 0xFA, 0xF4, 0xC2, 0xD0, 0xCA, 0xD0,
210		0xCA, 0xD0, 0xCA, 0xD0, 0xDA, 0xD0, 0xDA, 0xD0, 0xDA, 0xD0, 0xDA, 0xD0, 0x08, 0x63, 0xD3, 0x08
	195	0x11, 0x42, 0x5B, 0xCA, 0x19, 0x42, 0x5B, 0xCA, 0x38, 0x63, 0x3A, 0x63, 0x3A, 0x63, 0x3A, 0x63,
	196	0xD3, 0x08, 0x5B, 0xCA, 0x19, 0xCA, 0x19, 0xCA, 0x18, 0xEB, 0x18, 0xEB, 0x18, 0xEB, 0x18, 0xEB,
	197	0xD3, 0xCA, 0x5B, 0xCC, 0x5B, 0xCC, 0x5B, 0xCC, 0xBA, 0x63, 0x38, 0x65, 0x38, 0x65, 0x38, 0x65,
	198	0xD1, 0xCA, 0x5B, 0xC8, 0x5B, 0xC8, 0x5B, 0xC8, 0x9A, 0xEB, 0x1A, 0xED, 0x1A, 0xED, 0x1A, 0xED,
	199	0x0C, 0x65, 0xF0, 0x00, 0x64, 0xF5, 0x04, 0x65, 0xB8, 0x25, 0x20, 0x20, 0x24, 0x24, 0x24, 0x24,
	200	0xF0, 0x00, 0xF8, 0x00, 0xFC, 0x00, 0xFC, 0x00, 0xB8, 0x3D, 0xFC, 0x19, 0xFC, 0x19, 0xFC, 0x19,
	201	0x44, 0xF9, 0xC4, 0xF9, 0xC4, 0xFD, 0xC4, 0xFD, 0xFC, 0xFD, 0xFC, 0xFD, 0xFC, 0xFD, 0xFC, 0xFD,
	202	0xC0, 0xD9, 0xC8, 0xD9, 0xC8, 0xD9, 0xC8, 0xD9, 0xD8, 0xD9, 0xD8, 0xD9, 0xD8, 0xD9, 0xD8, 0xD9,
	203	0x0C, 0x44, 0xFB, 0x04, 0x67, 0xD4, 0x0C, 0x44, 0xBA, 0x24, 0x22, 0x02, 0x26, 0x06, 0x26, 0x06,
	204	0xFB, 0x00, 0xFB, 0x00, 0xEF, 0x10, 0xCE, 0x18, 0xEF, 0x18, 0xEF, 0x18, 0xFF, 0x18, 0xFF, 0x18,
	205	0x44, 0xF8, 0xC6, 0xD8, 0xCE, 0xDC, 0xCE, 0xDC, 0xEF, 0x9E, 0x67, 0xB8, 0x67, 0xBC, 0x67, 0xBC,
	206	0xC6, 0xD8, 0xCA, 0xD8, 0xCA, 0xD8, 0xCA, 0xD8, 0xCB, 0x9A, 0xEF, 0x9A, 0xFF, 0xD8, 0xDB, 0xD8,
	207	0x66, 0xF4, 0x00, 0x64, 0xBA, 0x25, 0x22, 0x22, 0x26, 0x26, 0x26, 0x26, 0xF2, 0x00, 0xFA, 0x00,
	208	0xFA, 0x00, 0xFA, 0x00, 0xBA, 0x3D, 0xFA, 0x19, 0xFA, 0x19, 0xFA, 0x19, 0x44, 0xF9, 0xC2, 0xF0,
	209	0xC2, 0xF4, 0xC2, 0xF4, 0xFA, 0xF4, 0xFA, 0xF4, 0xFA, 0xF4, 0xFA, 0xF4, 0xC2, 0xD0, 0xCA, 0xD0,
	210	0xCA, 0xD0, 0xCA, 0xD0, 0xDA, 0xD0, 0xDA, 0xD0, 0xDA, 0xD0, 0xDA, 0xD0, 0x08, 0x63, 0xD3, 0x08
211	211	};
212	212
213	213
r18326	r18327
231	231
232	232	static const gfx_layout charlayout =
233	233	{
234		/* Todo , just for sample */
235
	234	/* Todo , just for sample */
	235
236	236	8,8,
237	237	RGN_FRAC(1,4),
238	238	4,
r18326	r18327
246	246	/*
247	247	static WRITE16_HANDLER( nevada_videoram_w )
248	248	{
249		// Todo, Just for sample
	249	// Todo, Just for sample
250	250
251		nevada_state *state = space->machine().driver_data<nevada_state>();
252		state->m_videoram[offset] = data;
253		state->m_bg_tilemap->mark_tile_dirty(offset);
	251	nevada_state *state = space->machine().driver_data<nevada_state>();
	252	state->m_videoram[offset] = data;
	253	state->m_bg_tilemap->mark_tile_dirty(offset);
254	254
255	255	}
256	256	*/
257	257	/***************************************************************************/
258	258	static GFXDECODE_START( nevada )
259		/* Todo , just for sample */
	259	/* Todo , just for sample */
260	260	GFXDECODE_ENTRY( "gfx1", 0x0000, charlayout, 0, 8 )
261	261	GFXDECODE_END
262	262
r18326	r18327
264	264	/*
265	265	static TILE_GET_INFO( get_bg_tile_info )
266	266	{
267		// Todo, Just for sample
268		nevada_state *state = machine.driver_data<nevada_state>();
	267	// Todo, Just for sample
	268	nevada_state *state = machine.driver_data<nevada_state>();
269	269
270		int attr = state->m_colorram[tile_index];
271		int code = ((attr & 1) << 8) \| state->m_videoram[tile_index];
272		int bank = (attr & 0x02) >> 1;
273		int color = (attr & 0x3c) >> 2;
	270	int attr = state->m_colorram[tile_index];
	271	int code = ((attr & 1) << 8) \| state->m_videoram[tile_index];
	272	int bank = (attr & 0x02) >> 1;
	273	int color = (attr & 0x3c) >> 2;
274	274
275		SET_TILE_INFO(bank, code, color, 0);
	275	SET_TILE_INFO(bank, code, color, 0);
276	276
277	277	}
278	278	*/
r18326	r18327
280	280	/***************************************************************************/
281	281	static VIDEO_START( nevada )
282	282	{
283		// todo
	283	// todo
284	284	/*
285		nevada_state *state = machine.driver_data<nevada_state>();
286		state->m_bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
287		*/
	285	nevada_state *state = machine.driver_data<nevada_state>();
	286	state->m_bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 32, 32);
	287	*/
288	288	}
289	289
290	290	/***************************************************************************/
291	291	static SCREEN_UPDATE_IND16( nevada )
292	292	{
293	293	// Todo
294		/*
295		nevada_state *state = screen.machine().driver_data<nevada_state>();
296		state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
297		*/
298		return 0;
	294	/*
	295	nevada_state *state = screen.machine().driver_data<nevada_state>();
	296	state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
	297	*/
	298	return 0;
299	299	}
300	300
301	301	/***************************************************************************/
r18326	r18327
319	319	if (file)
320	320	file->read(state->m_nvram,state->m_nvram.bytes());
321	321	else
322		{
	322	{
323	323	UINT16* defaultram = (UINT16 *) state->memregion("defaults")->base();
324	324	memset(state->m_nvram,0x00,state->m_nvram.bytes());
325	325	if (defaultram) memcpy(state->m_nvram, state->memregion("defaults")->base(), state->memregion("defaults")->bytes());
326		}
	326	}
327	327	}
328	328	}
329	329
330	330	/***************************************************************************
331	331
332		U18 MC68681 RS232 UART SIDEA = MODEM 1200 Baud
	332	U18 MC68681 RS232 UART SIDEA = MODEM 1200 Baud
333	333	U18 MC68681 RS232 UART SIDEB = not used
334	334	Interrupt 4
335	335	***************************************************************************/
336	336
337	337	static void duart18_irq_handler(device_t *device, int state, UINT8 vector )
338		{
	338	{
339	339	device->machine().device("maincpu")->execute().set_input_line_and_vector(4, state, vector);
340	340	};
341	341
342	342	/***************************************************************************/
343	343	static void duart18_tx(device_t *device, int channel, UINT8 data)
344	344	{
345		// nevada_state *state = device->machine().driver_data<nevada_state>();
346		/* Todo , just for sample */
	345	// nevada_state *state = device->machine().driver_data<nevada_state>();
	346	/* Todo , just for sample */
347	347	if ( channel == 0 )
348	348	{
349		// Modem 1200 Baud
350		}
	349	// Modem 1200 Baud
	350	}
351	351	};
352	352
353	353	/***************************************************************************/
r18326	r18327
367	367	***************************************************************************/
368	368
369	369	static void duart39_irq_handler( device_t *device, int state, UINT8 vector )
370		{
	370	{
371	371	device->machine().device("maincpu")->execute().set_input_line_and_vector(3, state, vector);
372	372	};
373	373
374	374	/***************************************************************************/
375	375	static void duart39_tx(device_t *device, int channel, UINT8 data)
376	376	{
377		// nevada_state *state = device->machine().driver_data<nevada_state>();
378		/* Todo , just for sample */
	377	// nevada_state *state = device->machine().driver_data<nevada_state>();
	378	/* Todo , just for sample */
379	379	if ( channel == 0 )
380	380	{
381	381	// Printer
382		}
	382	}
383	383	else
384	384	{
385	385	// Player Tracking Interface J2 (not used)
386		}
387
	386	}
	387
388	388	};
389	389
390	390	/***************************************************************************/
r18326	r18327
406	406
407	407	static void duart40_irq_handler( device_t *device, int state, UINT8 vector )
408	408	{
409		/* Todo , just for sample */
	409	/* Todo , just for sample */
410	410	device->machine().device("maincpu")->execute().set_input_line_and_vector(5, state, vector);
411	411	};
412	412
413	413	/***************************************************************************/
414	414	static void duart40_tx( device_t *device, int channel, UINT8 data )
415	415	{
416		/* Todo , just for sample */
	416	/* Todo , just for sample */
417	417	nevada_state *state = device->machine().driver_data<nevada_state>();
418	418	if ( channel == 0 )
419	419	{
r18326	r18327
421	421	}
422	422	else
423	423	{
424		// JCM Bill Acceptor
425		}
	424	// JCM Bill Acceptor
	425	}
426	426	};
427	427	/***************************************************************************/
428	428	WRITE8_MEMBER( nevada_state::microtouch_tx )
429	429	{
430		/* Todo , just for sample */
	430	/* Todo , just for sample */
431	431	duart68681_rx_data(m_duart40_68681, 0, data);
432	432	}
433	433
r18326	r18327
464	464	{
465	465	AY8910_LEGACY_OUTPUT,
466	466	AY8910_DEFAULT_LOADS,
467		// DEVCB_INPUT_PORT("DSW1"), /* not used */
468		// DEVCB_INPUT_PORT("DSW2"), /* not used */
	467	// DEVCB_INPUT_PORT("DSW1"), /* not used */
	468	// DEVCB_INPUT_PORT("DSW2"), /* not used */
469	469	DEVCB_NULL, /* callback for display state changes */
470	470	DEVCB_NULL, /* callback for cursor state changes */
471	471	DEVCB_NULL,
r18326	r18327
474	474
475	475	/***************************************************************************/
476	476	static READ16_HANDLER(io_board_r)
477		{
478		// IO board Serial communication 0xA00000
479		return 1;
	477	{
	478	// IO board Serial communication 0xA00000
	479	return 1;
480	480	}
481	481	/***************************************************************************/
482	482	static WRITE16_HANDLER(io_board_w)
r18326	r18327
491	491
492	492	/***************************************************************************/
493	493	static READ16_HANDLER( nevada_sec_r )
494		{
495		nevada_state *state = space.machine().driver_data<nevada_state>();
496		// D3..D0 = DOOR OPEN or Track STATE of PAL35
497		UINT16 res;
498		/* UPPER byte is use for input in PAL35 */
	494	{
	495	nevada_state *state = space.machine().driver_data<nevada_state>();
	496	// D3..D0 = DOOR OPEN or Track STATE of PAL35
	497	UINT16 res;
	498	/* UPPER byte is use for input in PAL35 */
499	499	// 74LS173 $bits Register used LOWER bits D3..D0 for PAL35 state and DOOR LOGIC SWITCH
500		res = pal35[state->m_datA40000 >> 8];
	500	res = pal35[state->m_datA40000 >> 8];
501	501	res = res << 8;
502	502	res = res \| (state->m_datA40000 & 0x00FF);
503
	503
504	504	return res;
505	505	}
506	506	/***************************************************************************/
507	507	static WRITE16_HANDLER( nevada_sec_w )
508		{
509		nevada_state *state = space.machine().driver_data<nevada_state>();
	508	{
	509	nevada_state *state = space.machine().driver_data<nevada_state>();
510	510	// 74LS173 $bits Register used LOWER bits D3..D0 for DOOR LOGIC SWITCH
511		state->m_datA40000 = data \| 0x00f0; // since D7..D4 are not used and are connected to PULLUP
512		// popmessage("WRITE %04x %04x ",datA40000,data);
	511	state->m_datA40000 = data \| 0x00f0; // since D7..D4 are not used and are connected to PULLUP
	512	// popmessage("WRITE %04x %04x ",datA40000,data);
513	513	}
514	514
515	515	/***************************************************************************/
r18326	r18327
521	521	1 x COIN DOOR SW
522	522	1 x TOP DOOR SW
523	523	1 x COMPUTER DOOR SW
524
	524
525	525	Interrupt Vector
526	526	INT1 RTC MSM6242
527	527	INT2 nc
r18326	r18327
539	539
540	540	U18 MC68681 RS232 UART SIDEA = MODEM LOW SPEED 1200 BAUD from XECOM
541	541
542		U18 MC68681 PIN4 IP1 from U16 (75HC189 pin6) from PIN2 J90 UNKNOWN !
	542	U18 MC68681 PIN4 IP1 from U16 (75HC189 pin6) from PIN2 J90 UNKNOWN !
543	543	U18 MC68681 PIN36 IP2 ACCESS DOOR SWITCH
544	544	U18 MC68681 PIN2 IP3 LOW Battery Detector for ACCESS DOOR SWITCH
545	545	U18 MC68681 PIN39 IP4 from U12 75174 UNKNOWN !
r18326	r18327
561	561	// missing adress for :
562	562	// external I/O board communication via PAL23
563	563
564		A23 A22 A21 A20 \| A19 A18 A17 A16 \| A15 A14 A13 A12 \| A11 A10 A9 A8 \| A7 A6 A5 A4 \| A3 A2 A1 xx
	564	A23 A22 A21 A20 \| A19 A18 A17 A16 \| A15 A14 A13 A12 \| A11 A10 A9 A8 \| A7 A6 A5 A4 \| A3 A2 A1 xx
565	565	Memory Map (generic)
566	566	--------------------
567	567	00000000 0000FFFF NVRAM (only 0..FFFF vector and jump) 16bits
568	568	00010000 00011FFF BACKUP1 8bits
569		00020000 00021FFF BACKUP2 8bits
	569	00020000 00021FFF BACKUP2 8bits
570	570	00B00000 00B01FFF VIDEO RAM 8bits
571	571	00FA0000 00FBFFFF Not used (Expension board SRAM)
572	572	00FC0000 00FDFFFF PROGRAM 16bits
573	573	00FE0000 00FFFFFF BOOTLOADER 16bits
574	574
575		00010001
	575	00010001
576	576	00014001
577	577	00020001
578	578	00024001
r18326	r18327
582	582	00A08001 I/O Board Communication
583	583	00A10000 WDT STROBE DS1232 WatchDog Controller (this adress reset Strobe of Ds1232)
584	584	00A20001 AY8912 BDIR AUDIO Data bus on D7..D0
585		00A28001 AY8912 BC1 AUDIO
	585	00A28001 AY8912 BC1 AUDIO
586	586	00A300x1 6242 CS RTC U41 A0..A3 (A4..A7 ON A0..A3) Data bus on D3..D0
587	587	00A4000x PAL CS READ U35 SECURITY PAL16R8 Data bus on D15..D8
588	588	00A4000x PAL CLK WRITE U35 SECURITY PAL16R8
r18326	r18327
591	591	00B100x0 68681 CS UART U40 RS1..RS4 REGISTER (A4..A7 ON RS1..RS4) Data bus on D7..D0
592	592	00B200x0 68681 CS UART U39 RS1..RS4 REGISTER (A4..A7 ON RS1..RS4) Data bus on D7..D0
593	593	00E000x0 68681 CS UART U18 RS1..RS4 REGISTER (A4..A7 ON RS1..RS4) Data bus on D15..D8
594		*/
	594	*/
595	595	/***************************************************************************/
596	596	static ADDRESS_MAP_START( nevada_map, AS_PROGRAM, 16,nevada_state )
597	597	AM_RANGE(0x00000000, 0x0000ffff) AM_RAM AM_SHARE("nvram")
598	598	AM_RANGE(0x00010000, 0x00021fff) AM_RAM AM_SHARE("backup")
599		AM_RANGE(0x00900000, 0x00900001) AM_DEVWRITE8("crtc",mc6845_device, address_w,0x00ff )
	599	AM_RANGE(0x00900000, 0x00900001) AM_DEVWRITE8("crtc",mc6845_device, address_w,0x00ff )
600	600	AM_RANGE(0x00908000, 0x00908001) AM_DEVWRITE8("crtc",mc6845_device,register_w,0x00ff )
601	601	AM_RANGE(0x00a00000, 0x00a00001) AM_READWRITE_LEGACY (io_board_r,io_board_w)
602	602	AM_RANGE(0x00a08000, 0x00a08001) AM_WRITE_LEGACY(io_board_x)
603	603	AM_RANGE(0x00a10000, 0x00a10001) AM_WRITE(watchdog_reset16_w )
604		AM_RANGE(0x00a20000, 0x00a20001) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_w,0x00ff )
605		AM_RANGE(0x00a28000, 0x00a28001) AM_DEVWRITE8_LEGACY("aysnd", ay8910_data_w ,0x00ff )
	604	AM_RANGE(0x00a20000, 0x00a20001) AM_DEVWRITE8_LEGACY("aysnd", ay8910_address_w,0x00ff )
	605	AM_RANGE(0x00a28000, 0x00a28001) AM_DEVWRITE8_LEGACY("aysnd", ay8910_data_w ,0x00ff )
606	606	AM_RANGE(0x00a30000, 0x00A300ff) AM_DEVREADWRITE8("rtc",msm6242_device, read, write, 0x00ff)
607	607	AM_RANGE(0x00a40000, 0x00A40001) AM_READWRITE_LEGACY( nevada_sec_r, nevada_sec_w)
608	608	//AM_RANGE(0x00b00000, 0x00b01fff) AM_RAM_WRITE(nevada_videoram_w) AM_BASE_MEMBER(nevada_state, m_videoram)
r18326	r18327
621	621
622	622	ADDRESS_MAP_END
623	623	/*
624		U18 MC68681 PIN4 IP1 from U16 (75HC189 pin6) from PIN2 J90 UNKNOWN !
	624	U18 MC68681 PIN4 IP1 from U16 (75HC189 pin6) from PIN2 J90 UNKNOWN !
625	625	U18 MC68681 PIN36 IP2 ACCESS DOOR SWITCH
626	626	U18 MC68681 PIN2 IP3 LOW Battery Detector for ACCESS DOOR SWITCH
627	627	U18 MC68681 PIN39 IP4 from U12 75174 UNKNOWN !
r18326	r18327
656	656	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN2 )
657	657	PORT_START("DSW3")
658	658	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN3 )
659		PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN4 )
	659	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_COIN4 )
660	660	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON7 ) PORT_NAME("LOW BATT U51")
661	661	INPUT_PORTS_END
662	662
r18326	r18327
694	694	{
695	695
696	696	nevada_state *state = machine.driver_data<nevada_state>();
697
	697
698	698	state->m_duart18_68681 = machine.device( "duart18_68681" );
699	699	state->m_duart39_68681 = machine.device( "duart39_68681" );
700	700	state->m_duart40_68681 = machine.device( "duart40_68681" );
r18326	r18327
710	710	MCFG_CPU_ADD("maincpu", M68000, MASTER_CPU)
711	711	MCFG_CPU_PROGRAM_MAP(nevada_map)
712	712	MCFG_CPU_IO_MAP(nevada_iomap) //0x10000 0x20000
713
	713
714	714	MCFG_MACHINE_RESET(nevada)
715	715	MCFG_WATCHDOG_TIME_INIT(attotime::from_msec(150)) /* 150ms Ds1232 TD to Ground */
716
717
718		MCFG_NVRAM_HANDLER(nevada)
719	716
	717
	718	MCFG_NVRAM_HANDLER(nevada)
	719
720	720	// video hardware
721	721	MCFG_SCREEN_ADD("screen", RASTER)
722	722	MCFG_SCREEN_REFRESH_RATE(60)
723		MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
	723	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
724	724	MCFG_SCREEN_SIZE((42+1)8, (32+1)8) /* From MC6845 init, registers 00 & 04 (programmed with value-1). */
725	725	MCFG_SCREEN_VISIBLE_AREA(08, 318-1, 08, 318-1) /* From MC6845 init, registers 01 & 06. */
726	726	MCFG_SCREEN_UPDATE_STATIC(nevada)
r18326	r18327
729	729	MCFG_PALETTE_LENGTH(256)
730	730	MCFG_PALETTE_INIT(nevada)
731	731	MCFG_VIDEO_START(nevada)
732
	732
733	733	MCFG_MC6845_ADD("crtc", MC6845, MC6845_CLOCK, mc6845_intf)
734
	734
735	735	// sound hardware
736	736	MCFG_SPEAKER_STANDARD_MONO("mono")
737	737
738	738	MCFG_SOUND_ADD("aysnd", AY8912, SOUND_CLOCK)
739	739	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
740
	740
741	741	MCFG_DUART68681_ADD( "duart18_68681", XTAL_3_6864MHz , nevada_duart18_68681_config ) // UARTA = Modem 1200Baud
742	742	MCFG_DUART68681_ADD( "duart39_68681", XTAL_3_6864MHz , nevada_duart39_68681_config ) // UARTA = Printer
743	743	MCFG_DUART68681_ADD( "duart40_68681", XTAL_3_6864MHz , nevada_duart40_68681_config ) // UARTA = Touch , UARTB = Bill Acceptor
744	744	MCFG_MICROTOUCH_ADD( "microtouch", nevada_microtouch_config )
745	745	/* devices */
746	746	MCFG_MSM6242_ADD("rtc", nevada_rtc_intf)
747
	747
748	748	MACHINE_CONFIG_END
749	749
750	750	/***************************************************************************/
751	751	ROM_START( nevada )
752		ROM_REGION( 0x1000000, "maincpu", 0 ) /* 2 x 27C512 */
	752	ROM_REGION( 0x1000000, "maincpu", 0 ) /* 2 x 27C512 */
753	753	ROM_LOAD16_BYTE( "u9even.bin" , 0xfc0000, 0x010000, CRC(ADB207BD) SHA1(3E3509B78FDF32785F92CB21272694673D25C563) ) // program fc0000..fdffff
754	754	ROM_LOAD16_BYTE( "u10odd.bin" , 0xfc0001, 0x010000, CRC(A79778D7) SHA1(6FF969F09D9781479360BCA3403B927099AD6481) )
755
	755
756	756	ROM_LOAD16_BYTE( "u31even.bin", 0xfe0000, 0x010000, CRC(C9779F30) SHA1(5310B3D8B5E887313CE8059BD72D0730A295074F) ) // Boot fe0000..ffffff
757		ROM_LOAD16_BYTE( "u32odd.bin" , 0xfe0001, 0x010000, CRC(51035ED1) SHA1(66CBF582CDF34CF3DDE30CF8A99BBCED4AF1CE6F) )
758
	757	ROM_LOAD16_BYTE( "u32odd.bin" , 0xfe0001, 0x010000, CRC(51035ED1) SHA1(66CBF582CDF34CF3DDE30CF8A99BBCED4AF1CE6F) )
	758
759	759	ROM_REGION16_BE( 0x0010000, "defaults", 0 ) /* 2 x 62256 NVRAM */
760	760	ROM_LOAD16_BYTE( "u30nv_even.bin", 0x000000, 0x008000, CRC(11f5c663) SHA1(f447fd59010bc7fbbda321c5aaf13e23c2aebd40) ) // NVRAM even (RESET + Vector table in NVRAM)
761	761	ROM_LOAD16_BYTE( "u33nv_odd.bin" , 0x000001, 0x008000, CRC(20623da2) SHA1(2dd31a96f0a3454855cd975e8ee95e43316344e0) ) // NVRAM odd
r18326	r18327
766	766	/*
767	767	BACKUP RAM
768	768	PAL DUMP
769		*/
	769	*/
770	770	ROM_END
771	771
772	772	/***************************************************************************/
r18326	r18327
775	775	*************************/
776	776	DRIVER_INIT_MEMBER(nevada_state,nevada)
777	777	{
778		UINT16 ROM = (UINT16 )memregion("maincpu")->base();
779
	778	UINT16 ROM = (UINT16 )memregion("maincpu")->base();
	779
780	780	memset(m_backup,0x00,m_backup.bytes()); // temp
781
	781
782	782	/* Patch for WDT test with int Level7 */
783	783	/* PATCH FE0086 4278 0414 Clrf $0414 */
784	784	/* this skip the test for the WDT */
785		// ROM[0xFE0086/2] = 0x4278;
786		// ROM[0xFE0088/2] = 0x0414;
787
788		// Skip PAL SECURITY
	785	// ROM[0xFE0086/2] = 0x4278;
	786	// ROM[0xFE0088/2] = 0x0414;
	787
	788	// Skip PAL SECURITY
789	789	ROM[0xFE0248/2] = 0x4E71; // nop
790	790	ROM[0xFE05D0/2] = 0x4E71; // nop
791	791	ROM[0xFE05D8/2] = 0x6014; // bra
792	792	ROM[0xFE0606/2] = 0x600A; // bra
793		// ROM[0xFE18B4/2] = 0x4E71; // nop
794
795
	793	// ROM[0xFE18B4/2] = 0x4E71; // nop
	794
	795
796	796	}
797	797	/***************************************************************************/
798	798

trunk/src/mame/drivers/jack.c
r18326	r18327
74	74	- When On (0x80), lives are set to 255 (0xff) but they are NOT infinite
75	75
76	76	Other bits from DSW2 (but bit 5) don't seem to be read / tested at all ...
77
78	77
	78
79	79	***************************************************************************/
80	80
81	81	#include "emu.h"
r18326	r18327
146	146	// d0: related to test mode?
147	147	// d1: unused?
148	148	// d2: ?
149
	149
150	150	// d3-d4: palette bank
151	151	int palette_bank = data & (machine().total_colors() - 1) >> 3 & 0x18;
152	152	if (m_joinem_palette_bank != palette_bank)
r18326	r18327
157	157
158	158	// d5: assume nmi enable
159	159	m_joinem_nmi_enable = data & 0x20;
160
	160
161	161	// d6: unused?
162	162
163	163	// d7: flip screen
r18326	r18327
890	890	MACHINE_START_MEMBER(jack_state,joinem)
891	891	{
892	892	m_joinem_palette_bank = 0;
893
	893
894	894	save_item(NAME(m_joinem_nmi_enable));
895	895	save_item(NAME(m_joinem_palette_bank));
896	896	}

trunk/src/mame/drivers/shangha3.c
r18326	r18327
557	557	MCFG_VIDEO_ATTRIBUTES(VIDEO_HAS_SHADOWS)
558	558
559	559	MCFG_SCREEN_ADD("screen", RASTER)
560		// MCFG_SCREEN_REFRESH_RATE(60)
561		// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
562		// MCFG_SCREEN_SIZE(2416, 1616)
563		// MCFG_SCREEN_VISIBLE_AREA(016, 2416-1, 116, 1516-1)
	560	// MCFG_SCREEN_REFRESH_RATE(60)
	561	// MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
	562	// MCFG_SCREEN_SIZE(2416, 1616)
	563	// MCFG_SCREEN_VISIBLE_AREA(016, 2416-1, 116, 1516-1)
564	564	MCFG_SCREEN_RAW_PARAMS(BLOCKEN_MASTER_CLOCK/6,512,0,2416,263,116,1516) / refresh rate is unknown */
565	565
566	566	MCFG_SCREEN_UPDATE_DRIVER(shangha3_state, screen_update_shangha3)

trunk/src/mame/drivers/savquest.c
r18326	r18327
419	419	AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w)
420	420	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
421	421	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
422		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	422	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
423	423	AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w)
424	424
425	425	AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)

trunk/src/mame/drivers/vicdual.c
r18326	r18327
108	108	/* increment the coin counter */
109	109	coin_counter_w(machine(), 0, 1);
110	110	coin_counter_w(machine(), 0, 0);
111
	111
112	112	coin_in();
113	113	}
114	114	}
r18326	r18327
460	460	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("DOOR:1") // 1 switch located on the inside of the coin door
461	461	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
462	462	PORT_DIPSETTING( 0x08, DEF_STR( On ) )
463
	463
464	464	// There is no dipswitch: on a physical level, these settings are applied by grounding
465	465	// otherwise floating pins (ground wires are provided on pin 1/30)
466	466	PORT_DIPNAME( 0x10, 0x10, "Allow Free Game" ) PORT_DIPLOCATION("PIN:5") // 26
r18326	r18327
921	921	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
922	922
923	923	PORT_START("IN2")
924		// PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_timer_value, NULL) // it's like this according to the schematics, but gameplay speed is too fast;
	924	// PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_timer_value, NULL) // it's like this according to the schematics, but gameplay speed is too fast;
925	925	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_composite_blank_comp, NULL) // gameplay speed is correct now, there's likely an error in the schematics then...
926	926	PORT_BIT( 0x7e, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
927	927	PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_read_coin_status, NULL)
r18326	r18327
1278	1278	PORT_DIPNAME( 0x03, 0x01, "Head On 2 Lives" ) PORT_DIPLOCATION("SW1:1,2")
1279	1279	PORT_DIPSETTING( 0x00, "2" )
1280	1280	PORT_DIPSETTING( 0x01, "3" )
1281		// PORT_DIPSETTING( 0x02, "3" ) // dupe
	1281	// PORT_DIPSETTING( 0x02, "3" ) // dupe
1282	1282	PORT_DIPSETTING( 0x03, "4" )
1283	1283
1284	1284	/* There's probably a bug in the Invinco game code:
r18326	r18327
1290	1290	PORT_DIPNAME( 0x03, 0x03, "Invinco Lives" ) PORT_DIPLOCATION("SW1:3,4")
1291	1291	PORT_DIPSETTING( 0x03, "3" )
1292	1292	PORT_DIPSETTING( 0x02, "4" )
1293		// PORT_DIPSETTING( 0x01, "5" ) // results in 3, see above
1294		// PORT_DIPSETTING( 0x00, "6" ) // results in 4, see above
	1293	// PORT_DIPSETTING( 0x01, "5" ) // results in 3, see above
	1294	// PORT_DIPSETTING( 0x00, "6" ) // results in 4, see above
1295	1295
1296	1296	INPUT_PORTS_END
1297	1297
r18326	r18327
1646	1646	PORT_DIPSETTING( 0x00, "3" )
1647	1647	PORT_DIPSETTING( 0x01, "4" )
1648	1648	PORT_DIPSETTING( 0x02, "5" )
1649		// PORT_DIPSETTING( 0x03, "5" ) // dupe
	1649	// PORT_DIPSETTING( 0x03, "5" ) // dupe
1650	1650	INPUT_PORTS_END
1651	1651
1652	1652
r18326	r18327
1700	1700	PORT_DIPSETTING( 0x00, "3" )
1701	1701	PORT_DIPSETTING( 0x01, "4" )
1702	1702	PORT_DIPSETTING( 0x02, "5" )
1703		// PORT_DIPSETTING( 0x03, "5" ) // dupe
	1703	// PORT_DIPSETTING( 0x03, "5" ) // dupe
1704	1704	INPUT_PORTS_END
1705	1705
1706	1706
r18326	r18327
2064	2064	PORT_START("IN1")
2065	2065	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* probably unused */
2066	2066	PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,samurai_protection_r, (void *)1)
2067		PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") // unknown, but used
	2067	PORT_DIPNAME( 0x04, 0x00, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:2") // unknown, but used
2068	2068	PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
2069	2069	PORT_DIPSETTING( 0x00, DEF_STR( On ) )
2070	2070	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, vicdual_state,vicdual_get_composite_blank_comp, NULL)
r18326	r18327
2201	2201	m_nsub_play_counter++;
2202	2202	}
2203	2203	}
2204
	2204
2205	2205	// increment coin counter
2206	2206	coin_counter_w(machine(), which, 1);
2207	2207	coin_counter_w(machine(), which, 0);
r18326	r18327
2211	2211	case 2:
2212	2212	m_nsub_play_counter++;
2213	2213	break;
2214
	2214
2215	2215	default:
2216	2216	break;
2217	2217	}
r18326	r18327
2249	2249	PORT_DIPSETTING( 0x03, DEF_STR( 3C_1C ) )
2250	2250	PORT_DIPSETTING( 0x02, DEF_STR( 2C_1C ) )
2251	2251	PORT_DIPSETTING( 0x01, DEF_STR( 1C_1C ) )
2252		// PORT_DIPSETTING( 0x00, DEF_STR( 0C_1C ) ) // invalid
	2252	// PORT_DIPSETTING( 0x00, DEF_STR( 0C_1C ) ) // invalid
2253	2253	PORT_DIPNAME( 0x78, 0x08, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW:4,5,6,7")
2254	2254	PORT_DIPSETTING( 0x40, "Shared With Coin A" )
2255		// PORT_DIPSETTING( 0x00, DEF_STR( 1C_0C ) ) // invalid
	2255	// PORT_DIPSETTING( 0x00, DEF_STR( 1C_0C ) ) // invalid
2256	2256	PORT_DIPSETTING( 0x08, DEF_STR( 1C_1C ) )
2257	2257	PORT_DIPSETTING( 0x10, DEF_STR( 1C_2C ) )
2258	2258	PORT_DIPSETTING( 0x18, DEF_STR( 1C_3C ) )
r18326	r18327
2280	2280	MACHINE_RESET_MEMBER(vicdual_state,nsub)
2281	2281	{
2282	2282	m_nsub_coin_counter = ioport("COINAGE")->read() & 7;
2283
	2283
2284	2284	machine_reset();
2285	2285	}
2286	2286

trunk/src/mame/drivers/cd32.c
r18326	r18327
1475	1475	/***************************************************************************************************/
1476	1476
1477	1477	// these are clones of the cd32 SYSTEM because they run on a stock retail unit, with additional HW
1478		GAME( 1993, cd32bios, 0, cd32base, cd32, cd32_state, cd32, ROT0, "Commodore Business Machines", "CD32 Bios", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND \| GAME_IS_BIOS_ROOT )
	1478	GAME( 1993, cd32bios, 0, cd32base, cd32, cd32_state, cd32, ROT0, "Commodore Business Machines", "CD32 Bios", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND \| GAME_IS_BIOS_ROOT )
1479	1479	GAME( 1995, cndypuzl, cd32bios, cd32base, cndypuzl, cd32_state, cndypuzl, ROT0, "CD Express", "Candy Puzzle (v1.0)", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND )
1480	1480	GAME( 1995, haremchl, cd32bios, cd32base, haremchl, cd32_state, haremchl, ROT0, "CD Express", "Harem Challenge", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND )
1481	1481	GAME( 1995, lsrquiz, cd32bios, cd32base, lsrquiz, cd32_state, lsrquiz, ROT0, "CD Express", "Laser Quiz Italy", GAME_IMPERFECT_GRAPHICS\|GAME_IMPERFECT_SOUND ) /* no player 2 inputs (ingame) */

trunk/src/mame/drivers/intrscti.c
r18326	r18327
90	90	static ADDRESS_MAP_START( intrscti_sub_map, AS_PROGRAM, 8, intrscti_state )
91	91	AM_RANGE(0x0000, 0x07ff) AM_ROM
92	92	AM_RANGE(0x2000, 0x23ff) AM_RAM
93		// AM_RANGE(0x0000, 0xffff) AM_WRITENOP
	93	// AM_RANGE(0x0000, 0xffff) AM_WRITENOP
94	94	ADDRESS_MAP_END
95	95
96	96	static ADDRESS_MAP_START( intrscti_sub_io_map, AS_IO, 8, intrscti_state )
97	97	ADDRESS_MAP_GLOBAL_MASK(0xff)
98		// AM_RANGE(0x00, 0xff) AM_NOP
	98	// AM_RANGE(0x00, 0xff) AM_NOP
99	99	ADDRESS_MAP_END
100	100
101	101

trunk/src/mame/drivers/saturn.c
r18326	r18327
1986	1986	MACHINE_RESET_MEMBER(saturn_state,saturn)
1987	1987	{
1988	1988	m_scsp_last_line = 0;
1989
	1989
1990	1990	// don't let the slave cpu and the 68k go anywhere
1991	1991	machine().device("slave")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
1992	1992	machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
r18326	r18327
2067	2067	MACHINE_RESET_MEMBER(saturn_state,stv)
2068	2068	{
2069	2069	m_scsp_last_line = 0;
2070
	2070
2071	2071	// don't let the slave cpu and the 68k go anywhere
2072	2072	machine().device("slave")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
2073	2073	machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);

trunk/src/mame/drivers/calchase.c
r18326	r18327
601	601	AM_RANGE(0x03a0, 0x03a7) AM_NOP //To debug
602	602	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", trident_vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
603	603	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", trident_vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
604		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", trident_vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	604	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", trident_vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
605	605	AM_RANGE(0x03e0, 0x03ef) AM_NOP //To debug
606	606	AM_RANGE(0x0378, 0x037f) AM_NOP //To debug
607	607	// AM_RANGE(0x0300, 0x03af) AM_NOP

trunk/src/mame/drivers/pcat_dyn.c
r18326	r18327
70	70	AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff)
71	71	AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff)
72	72	AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff)
73		AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
	73	AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff)
74	74	ADDRESS_MAP_END
75	75
76	76	#define AT_KEYB_HELPER(bit, text, key1) \

trunk/src/mame/machine/megacd.c
r18326	r18327
159	159	MCFG_TIMER_DRIVER_ADD("stamp_timer", sega_segacd_device, segacd_gfx_conversion_timer_callback)
160	160	MCFG_TIMER_DRIVER_ADD("scd_dma_timer", sega_segacd_device, scd_dma_timer_callback)
161	161
162
163	162
	163
164	164	MCFG_DEFAULT_LAYOUT( layout_megacd )
165	165
166	166	MCFG_SOUND_ADD( "cdda", CDDA, 0 )
r18326	r18327
1100	1100
1101	1101	WRITE16_MEMBER( sega_segacd_device::scd_a12000_halt_reset_w )
1102	1102	{
1103
1104	1103
	1104
1105	1105	UINT16 old_halt = a12000_halt_reset_reg;
1106	1106
1107	1107	COMBINE_DATA(&a12000_halt_reset_reg);
r18326	r18327
1170	1170
1171	1171	READ16_MEMBER( sega_segacd_device::scd_a12002_memory_mode_r )
1172	1172	{
1173
1174	1173
	1174
1175	1175	int temp = scd_rammode;
1176	1176	int temp2 = 0;
1177	1177
r18326	r18327
1208	1208
1209	1209	WRITE8_MEMBER( sega_segacd_device::scd_a12002_memory_mode_w_0_7 )
1210	1210	{
1211
1212	1211
1213	1212
	1213
1214	1214	//printf("scd_a12002_memory_mode_w_0_7 %04x\n",data);
1215	1215
1216	1216	segacd_4meg_prgbank = (data&0x00c0)>>6;
r18326	r18327
1234	1234
1235	1235	WRITE16_MEMBER( sega_segacd_device::scd_a12002_memory_mode_w )
1236	1236	{
1237
1238	1237
	1238
1239	1239	if (ACCESSING_BITS_8_15)
1240	1240	scd_a12002_memory_mode_w_8_15(space, 0, data>>8, mem_mask>>8);
1241	1241
r18326	r18327
1248	1248
1249	1249	READ16_MEMBER( sega_segacd_device::segacd_sub_memory_mode_r )
1250	1250	{
1251
1252	1251
	1252
1253	1253	int temp = scd_rammode;
1254	1254	int temp2 = 0;
1255	1255
r18326	r18327
1270	1270
1271	1271	WRITE8_MEMBER( sega_segacd_device::segacd_sub_memory_mode_w_0_7 )
1272	1272	{
1273
1274	1273
1275	1274
	1275
1276	1276	segacd_memory_priority_mode = (data&0x0018)>>3;
1277	1277
1278	1278	// If the mode bit is 0 then we're requesting a change to
r18326	r18327
1330	1330	WRITE16_MEMBER( sega_segacd_device::segacd_sub_memory_mode_w )
1331	1331	{
1332	1332	//printf("segacd_sub_memory_mode_w %04x %04x\n", data, mem_mask);
1333
1334	1333
	1334
1335	1335	if (ACCESSING_BITS_8_15)
1336	1336	segacd_sub_memory_mode_w_8_15(space, 0, data>>8, mem_mask>>8);
1337	1337
r18326	r18327
1352	1352
1353	1353	READ16_MEMBER( sega_segacd_device::segacd_comms_flags_r )
1354	1354	{
1355
	1355
1356	1356	return segacd_comms_flags;
1357	1357	}
1358	1358
1359	1359	WRITE16_MEMBER( sega_segacd_device::segacd_comms_flags_subcpu_w )
1360	1360	{
1361
1362	1361
	1362
1363	1363	if (ACCESSING_BITS_8_15) // Dragon's Lair
1364	1364	{
1365	1365	segacd_comms_flags = (segacd_comms_flags & 0xff00) \| ((data >> 8) & 0x00ff);
r18326	r18327
1374	1374
1375	1375	WRITE16_MEMBER( sega_segacd_device::segacd_comms_flags_maincpu_w )
1376	1376	{
1377
1378	1377
	1378
1379	1379	if (ACCESSING_BITS_8_15)
1380	1380	{
1381	1381	segacd_comms_flags = (segacd_comms_flags & 0x00ff) \| (data & 0xff00);
r18326	r18327
1410	1410
1411	1411	READ16_MEMBER( sega_segacd_device::segacd_comms_main_part1_r )
1412	1412	{
1413
	1413
1414	1414	return segacd_comms_part1[offset];
1415	1415	}
1416	1416
1417	1417	WRITE16_MEMBER( sega_segacd_device::segacd_comms_main_part1_w )
1418	1418	{
1419
	1419
1420	1420	COMBINE_DATA(&segacd_comms_part1[offset]);
1421	1421	}
1422	1422
1423	1423	READ16_MEMBER( sega_segacd_device::segacd_comms_main_part2_r )
1424	1424	{
1425
	1425
1426	1426	return segacd_comms_part2[offset];
1427	1427	}
1428	1428
r18326	r18327
1434	1434
1435	1435	READ16_MEMBER( sega_segacd_device::segacd_comms_sub_part1_r )
1436	1436	{
1437
	1437
1438	1438	return segacd_comms_part1[offset];
1439	1439	}
1440	1440
r18326	r18327
1445	1445
1446	1446	READ16_MEMBER( sega_segacd_device::segacd_comms_sub_part2_r )
1447	1447	{
1448
	1448
1449	1449	return segacd_comms_part2[offset];
1450	1450	}
1451	1451
1452	1452	WRITE16_MEMBER( sega_segacd_device::segacd_comms_sub_part2_w )
1453	1453	{
1454
	1454
1455	1455	COMBINE_DATA(&segacd_comms_part2[offset]);
1456	1456	}
1457	1457
r18326	r18327
1620	1620
1621	1621	READ16_MEMBER( sega_segacd_device::scd_a12006_hint_register_r )
1622	1622	{
1623
	1623
1624	1624	return segacd_hint_register;
1625	1625	}
1626	1626
1627	1627	WRITE16_MEMBER( sega_segacd_device::scd_a12006_hint_register_w )
1628	1628	{
1629
	1629
1630	1630	COMBINE_DATA(&segacd_hint_register);
1631	1631	}
1632	1632
r18326	r18327
2129	2129
2130	2130	READ16_MEMBER( sega_segacd_device::segacd_irq_mask_r )
2131	2131	{
2132
	2132
2133	2133	return segacd_irq_mask;
2134	2134	}
2135	2135
r18326	r18327
2138	2138	if (ACCESSING_BITS_0_7)
2139	2139	{
2140	2140	UINT16 control = CDD_CONTROL;
2141
	2141
2142	2142	// printf("segacd_irq_mask_w %04x %04x (CDD control is %04x)\n",data, mem_mask, control);
2143	2143
2144	2144	if (data & 0x10)
r18326	r18327
2166	2166
2167	2167	READ16_MEMBER( sega_segacd_device::segacd_cdd_ctrl_r )
2168	2168	{
2169
	2169
2170	2170	return CDD_CONTROL;
2171	2171	}
2172	2172
r18326	r18327
2176	2176	if (ACCESSING_BITS_0_7)
2177	2177	{
2178	2178	UINT16 control = CDD_CONTROL;
2179
2180	2179
	2180
2181	2181	//printf("segacd_cdd_ctrl_w %04x %04x (control %04x irq %04x\n", data, mem_mask, control, segacd_irq_mask);
2182	2182
2183	2183	data &=0x4; // only HOCK bit is writable
r18326	r18327
2580	2580	segacd_irq3_timer = machine().device<timer_device>(":segacd:irq3_timer");
2581	2581
2582	2582	address_space& space = machine().device("maincpu")->memory().space(AS_PROGRAM);
2583
	2583
2584	2584	segacd_font_bits = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:segacd_font")->ptr());
2585	2585	segacd_backupram = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:backupram")->ptr());
2586	2586	segacd_dataram = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:dataram")->ptr());
2587		// segacd_dataram2 = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:dataram2")->ptr());
	2587	// segacd_dataram2 = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:dataram2")->ptr());
2588	2588	segacd_4meg_prgram = reinterpret_cast<UINT16 *>(machine().root_device().memshare(":segacd:segacd_program")->ptr());
2589
	2589
2590	2590	segacd_4meg_prgbank = 0;
2591	2591
2592	2592
r18326	r18327
2618	2618
2619	2619	space.install_read_handler (0x0000070, 0x0000073, read16_delegate(FUNC(sega_segacd_device::scd_hint_vector_r),this) );
2620	2620
2621
2622	2621
2623	2622
2624	2623
	2624
2625	2625	/* create the char set (gfx will then be updated dynamically from RAM) */
2626	2626	machine().gfx[0] = auto_alloc(machine(), gfx_element(machine(), sega_16x16_r00_f0_layout, (UINT8 *)segacd_dataram, 0, 0));
2627	2627	machine().gfx[1] = auto_alloc(machine(), gfx_element(machine(), sega_16x16_r01_f0_layout, (UINT8 *)segacd_dataram, 0, 0));
r18326	r18327
2698	2698
2699	2699
2700	2700	// initialize some stuff on reset
2701
	2701
2702	2702	segacd_ram_writeprotect_bits = 0;
2703	2703	segacd_4meg_prgbank = 0;
2704	2704	segacd_memory_priority_mode = 0;

trunk/src/mame/machine/megacd.h
r18326	r18327
370	370	UINT16 segacd_imagebuffer_start_address;
371	371	UINT16 segacd_imagebuffer_offset;
372	372
373
	373
374	374	UINT16 segacd_comms_flags;// = 0x0000;
375	375	UINT16 segacd_comms_part1[0x8];
376	376	UINT16 segacd_comms_part2[0x8];
r18326	r18327
422	422	UINT32 CDD_EXT;
423	423	UINT16 CDD_CONTROL;
424	424	INT16 CDD_DONE;
425
	425
426	426	TIMER_DEVICE_CALLBACK_MEMBER( segacd_irq3_timer_callback );
427	427	TIMER_DEVICE_CALLBACK_MEMBER( scd_dma_timer_callback );
428	428	TIMER_DEVICE_CALLBACK_MEMBER( segacd_access_timer_callback );
r18326	r18327
480	480	void SCD_GET_TILE_INFO_32x32_1x1( int& tile_region, int& tileno, int tile_index );
481	481	void SCD_GET_TILE_INFO_16x16_16x16( int& tile_region, int& tileno, int tile_index );
482	482	void SCD_GET_TILE_INFO_32x32_16x16( int& tile_region, int& tileno, int tile_index );
483
	483
484	484	TILE_GET_INFO_MEMBER( get_stampmap_16x16_1x1_tile_info );
485	485	TILE_GET_INFO_MEMBER( get_stampmap_32x32_1x1_tile_info );
486	486	TILE_GET_INFO_MEMBER( get_stampmap_16x16_16x16_tile_info );
r18326	r18327
556	556	WRITE16_MEMBER( segacd_stampmap_base_address_w );
557	557	READ16_MEMBER( segacd_imagebuffer_start_address_r );
558	558	WRITE16_MEMBER( segacd_imagebuffer_start_address_w );
559		READ16_MEMBER( segacd_imagebuffer_offset_r );
	559	READ16_MEMBER( segacd_imagebuffer_offset_r );
560	560	WRITE16_MEMBER( segacd_imagebuffer_offset_w );
561		READ16_MEMBER( segacd_imagebuffer_vcell_size_r );
	561	READ16_MEMBER( segacd_imagebuffer_vcell_size_r );
562	562	WRITE16_MEMBER( segacd_imagebuffer_vcell_size_w );
563	563	READ16_MEMBER( segacd_imagebuffer_hdot_size_r );
564	564	WRITE16_MEMBER( segacd_imagebuffer_hdot_size_w );
r18326	r18327
569	569	READ16_MEMBER( segacd_cdfader_r );
570	570	WRITE16_MEMBER( segacd_cdfader_w );
571	571	READ16_MEMBER( segacd_backupram_r );
572		WRITE16_MEMBER( segacd_backupram_w );
	572	WRITE16_MEMBER( segacd_backupram_w );
573	573	READ16_MEMBER( segacd_font_color_r );
574	574	WRITE16_MEMBER( segacd_font_color_w );
575	575	READ16_MEMBER( segacd_font_converted_r );

trunk/src/mame/machine/seicop.c
r18326	r18327
2048	2048
2049	2049	{
2050	2050	height = UINT8(cop_collision_info[offs].hitbox_y >> 8);
2051		start_y = INT8(cop_collision_info[offs].hitbox_y);
	2051	start_y = INT8(cop_collision_info[offs].hitbox_y);
2052	2052	width = UINT8(cop_collision_info[offs].hitbox_x >> 8);
2053		start_x = INT8(cop_collision_info[offs].hitbox_x);
2054		}
	2053	start_x = INT8(cop_collision_info[offs].hitbox_x);
	2054	}
2055	2055
2056	2056	cop_collision_info[offs].min_x = (cop_collision_info[offs].x >> 16) + start_x;
2057	2057	cop_collision_info[offs].max_x = cop_collision_info[offs].min_x + width;
r18326	r18327
2089	2089
2090	2090	//if(res == 0)
2091	2091	//popmessage("0:%08x %08x %08x 1:%08x %08x %08x\n",cop_collision_info[0].x,cop_collision_info[0].y,cop_collision_info[0].hitbox,cop_collision_info[1].x,cop_collision_info[1].y,cop_collision_info[1].hitbox);
2092		// popmessage("0:%08x %08x %08x %08x 1:%08x %08x %08x %08x\n",cop_collision_info[0].min_x,cop_collision_info[0].max_x,cop_collision_info[0].min_y, cop_collision_info[0].max_y,
2093		// cop_collision_info[1].min_x,cop_collision_info[1].max_x,cop_collision_info[1].min_y, cop_collision_info[1].max_y);
	2092	// popmessage("0:%08x %08x %08x %08x 1:%08x %08x %08x %08x\n",cop_collision_info[0].min_x,cop_collision_info[0].max_x,cop_collision_info[0].min_y, cop_collision_info[0].max_y,
	2093	// cop_collision_info[1].min_x,cop_collision_info[1].max_x,cop_collision_info[1].min_y, cop_collision_info[1].max_y);
2094	2094
2095	2095	return res;
2096	2096	}
r18326	r18327
2779	2779	cur_angle = INT8(space.read_byte(cop_register[0] + (0x34 ^ 3)));
2780	2780	//space.write_byte(cop_register[0] + (0^3),space.read_byte(cop_register[0] + (0^3)) & 0xfb); //correct?
2781	2781	/*
2782		0x00 0x00 0x60 0x00
2783		0x00 0x20 0x60 0x20
2784		0x00 0x40 0x60 0x60
2785		0x00 0x60 0x60 0x60
2786		0x00 0x80 0x60 0xa0
2787		0x00 0xa0 0x60 0xa0
2788		0x00 0xc0 0x60 0xc0
2789		0x00 0xe0 0x60 0xe0
2790		*/
	2782	0x00 0x00 0x60 0x00
	2783	0x00 0x20 0x60 0x20
	2784	0x00 0x40 0x60 0x60
	2785	0x00 0x60 0x60 0x60
	2786	0x00 0x80 0x60 0xa0
	2787	0x00 0xa0 0x60 0xa0
	2788	0x00 0xc0 0x60 0xc0
	2789	0x00 0xe0 0x60 0xe0
	2790	*/
2791	2791
2792	2792	if(cur_angle > cop_angle_compare)
2793	2793	{

trunk/src/mame/machine/pcecommn.h
r18326	r18327
18	18	: driver_device(mconfig, type, tag) { }
19	19
20	20	DECLARE_WRITE8_MEMBER(pce_joystick_w);
21		DECLARE_READ8_MEMBER(pce_joystick_r);
22
	21	DECLARE_READ8_MEMBER(pce_joystick_r);
	22
23	23	DECLARE_DRIVER_INIT(pce_common);
24
	24
25	25	virtual UINT8 joy_read();
26	26	private:
27		UINT8 m_io_port_options; /driver-specific options for the PCE/
	27	UINT8 m_io_port_options; /driver-specific options for the PCE/
28	28	int m_joystick_port_select; /* internal index of joystick ports */
29	29	int m_joystick_data_select; /* which nibble of joystick data we want */
30	30	};

trunk/src/mame/machine/archimds.c
r18326	r18327
867	867	case VIDC_HCR: m_vidc_regs[VIDC_HCR] = ((val >> 14)<<1)+1; break;
868	868	// case VIDC_HSWR: m_vidc_regs[VIDC_HSWR] = (val >> 14)+1; break;
869	869	case VIDC_HBSR: m_vidc_regs[VIDC_HBSR] = ((val >> 14)<<1)+1; break;
870		case VIDC_HDSR: m_vidc_regs[VIDC_HDSR] = (val >> 14); break;
871		case VIDC_HDER: m_vidc_regs[VIDC_HDER] = (val >> 14); break;
	870	case VIDC_HDSR: m_vidc_regs[VIDC_HDSR] = (val >> 14); break;
	871	case VIDC_HDER: m_vidc_regs[VIDC_HDER] = (val >> 14); break;
872	872	case VIDC_HBER: m_vidc_regs[VIDC_HBER] = ((val >> 14)<<1)+1; break;
873	873	// #define VIDC_HCSR 0x98
874	874	// #define VIDC_HIR 0x9c

trunk/src/mame/machine/genpin.h
r18326	r18327
30	30	MACHINE_CONFIG_EXTERN( genpin_audio );
31	31
32	32
33		#endif /* GENPIN_H_ */
		No newline at end of file
	33	#endif /* GENPIN_H_ */

trunk/src/mame/includes/decocass.h
r18326	r18327
210	210	DECLARE_WRITE8_MEMBER(decocass_center_v_shift_w);
211	211
212	212	void decocass_video_state_save_init();
213
	213
214	214	DECLARE_WRITE8_MEMBER(ram_w);
215	215	DECLARE_WRITE8_MEMBER(charram_w);
216	216	DECLARE_WRITE8_MEMBER(fgvideoram_w);
r18326	r18327
239	239	DECLARE_READ8_MEMBER(decocass_type5_r);
240	240	DECLARE_WRITE8_MEMBER(decocass_type5_w);
241	241	DECLARE_READ8_MEMBER(decocass_nodong_r);
242
	242
243	243	void draw_object(bitmap_ind16 &bitmap, const rectangle &cliprect);
244	244	void draw_center(bitmap_ind16 &bitmap, const rectangle &cliprect);
245	245	void mark_bg_tile_dirty(offs_t offset);
246	246	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, int color,
247	247	int sprite_y_adjust, int sprite_y_adjust_flip_screen,
248	248	UINT8 *sprite_ram, int interleave);
249
	249
250	250	void draw_missiles(bitmap_ind16 &bitmap, const rectangle &cliprect,
251	251	int missile_y_adjust, int missile_y_adjust_flip_screen,
252		UINT8 *missile_ram, int interleave);
	252	UINT8 *missile_ram, int interleave);
253	253	};
254	254

trunk/src/mame/includes/m79amb.h
r18326	r18327
14	14	required_shared_ptr<UINT8> m_mask;
15	15
16	16	required_device<discrete_device> m_discrete;
17
	17
18	18	/* misc */
19	19	UINT8 m_lut_gun1[0x100];
20	20	UINT8 m_lut_gun2[0x100];

trunk/src/mame/includes/bzone.h
r18326	r18327
18	18	m_discrete(*this, "discrete") { }
19	19
20	20	optional_device<discrete_device> m_discrete;
21
	21
22	22	UINT8 m_analog_data;
23	23	UINT8 m_rb_input_select;
24	24	DECLARE_WRITE8_MEMBER(bzone_coin_counter_w);

trunk/src/mame/includes/orbit.h
r18326	r18327
27	27	/* memory pointers */
28	28	required_shared_ptr<UINT8> m_playfield_ram;
29	29	required_shared_ptr<UINT8> m_sprite_ram;
30
	30
31	31	required_device<discrete_device> m_discrete;
32	32
33	33	/* video-related */

trunk/src/mame/includes/archimds.h
r18326	r18327
68	68	UINT8 m_ioc_regs[0x80/4];
69	69	UINT8 m_vidc_bpp_mode;
70	70	UINT8 m_vidc_interlace;
71
	71
72	72	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
73	73	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
74	74	private:
r18326	r18327
77	77	static const device_timer_id TIMER_VIDEO = 1;
78	78	static const device_timer_id TIMER_AUDIO = 2;
79	79	static const device_timer_id TIMER_IOC = 3;
80
	80
81	81	void vidc_vblank();
82	82	void vidc_video_tick();
83	83	void vidc_audio_tick();
84	84	void ioc_timer(int param);
85
86		void vidc_dynamic_res_change();
	85
	86	void vidc_dynamic_res_change();
87	87	void latch_timer_cnt(int tmr);
88	88	void a310_set_timer(int tmr);
89	89	DECLARE_READ32_MEMBER(ioc_ctrl_r);
r18326	r18327
99	99	UINT8 m_vidc_pixel_clk;
100	100	UINT8 m_vidc_stereo_reg[8];
101	101	emu_timer m_timer[4], m_snd_timer, *m_vid_timer;
102		emu_timer *m_vbl_timer;
	102	emu_timer *m_vbl_timer;
103	103	};
104	104
105	105	/* IOC registers */

trunk/src/mame/includes/dkong.h
r18326	r18327
110	110	const UINT8 * m_color_codes;
111	111	emu_timer * m_scanline_timer;
112	112	INT8 m_vidhw; /* Selected video hardware RS Conversion / TKG04 */
113
	113
114	114	optional_device<discrete_device> m_discrete;
115	115	/* radar scope */
116	116

trunk/src/mame/includes/irobot.h
r18326	r18327
74	74	DECLARE_READ8_MEMBER(irobot_status_r);
75	75	DECLARE_WRITE8_MEMBER(irobot_paletteram_w);
76	76	DECLARE_READ8_MEMBER(quad_pokeyn_r);
77		DECLARE_WRITE8_MEMBER(quad_pokeyn_w);
	77	DECLARE_WRITE8_MEMBER(quad_pokeyn_w);
78	78	DECLARE_DRIVER_INIT(irobot);
79	79	virtual void machine_reset();
80	80	virtual void video_start();

trunk/src/mame/includes/vicdual.h
r18326	r18327
33	33
34	34	void coin_in();
35	35	void assert_coin_status();
36
	36
37	37	DECLARE_WRITE8_MEMBER(vicdual_videoram_w);
38	38	DECLARE_WRITE8_MEMBER(vicdual_characterram_w);
39	39	DECLARE_READ8_MEMBER(depthch_io_r);

trunk/src/mame/includes/megadriv.h
r18326	r18327
107	107	: driver_device(mconfig, type, tag),
108	108	m_vdp(*this,"gen_vdp"),
109	109	m_megadrive_ram(*this,"megadrive_ram")
110		{
	110	{
111	111	sega_cd_connected = 0;
112	112	}
113	113	required_device<sega_genesis_vdp_device> m_vdp;
r18326	r18327
273	273	DECLARE_VIDEO_START(segac2_new);
274	274	DECLARE_MACHINE_START(segac2);
275	275	DECLARE_MACHINE_RESET(segac2);
276
	276
277	277	UINT32 screen_update_segac2_new(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
278	278	};
279	279
r18326	r18327
313	313	DECLARE_DRIVER_INIT(megaplay);
314	314	DECLARE_VIDEO_START(megplay);
315	315	DECLARE_MACHINE_RESET(megaplay);
316
	316
317	317	UINT32 screen_update_megplay(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
318	318	void screen_eof_megaplay(screen_device &screen, bool state);
319	319	};

trunk/src/mame/includes/kaneko16.h
r18326	r18327
116	116	DECLARE_DRIVER_INIT(berlwall);
117	117	DECLARE_PALETTE_INIT(berlwall);
118	118	DECLARE_VIDEO_START(berlwall);
119		UINT32 screen_update_berlwall(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	119	UINT32 screen_update_berlwall(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
120	120	};
121	121
122	122	class kaneko16_shogwarr_state : public kaneko16_state

trunk/src/mame/includes/mw8080bw.h
r18326	r18327
47	47	required_shared_ptr<UINT8> m_main_ram;
48	48	optional_shared_ptr<UINT8> m_colorram;
49	49	optional_device<discrete_device> m_discrete;
50
	50
51	51	/* sound-related */
52	52	UINT8 m_port_1_last;
53	53	UINT8 m_port_2_last;
r18326	r18327
78	78	samples_device *m_samples2;
79	79	device_t *m_sn1;
80	80	device_t *m_sn2;
81		device_t *m_sn;
	81	device_t *m_sn;
82	82
83	83	DECLARE_READ8_MEMBER(mw8080bw_shift_result_rev_r);
84	84	DECLARE_READ8_MEMBER(mw8080bw_reversable_shift_result_r);

trunk/src/mame/includes/deco32.h
r18326	r18327
107	107	DECLARE_VIDEO_START(nslasher);
108	108	UINT32 screen_update_captaven(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
109	109	UINT32 screen_update_fghthist(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
110		UINT32 screen_update_nslasher(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	110	UINT32 screen_update_nslasher(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
111	111	void screen_eof_captaven(screen_device &screen, bool state);
112	112	INTERRUPT_GEN_MEMBER(deco32_vbl_interrupt);
113	113	TIMER_DEVICE_CALLBACK_MEMBER(interrupt_gen);

trunk/src/mame/includes/crbaloon.h
r18326	r18327
24	24	required_shared_ptr<UINT8> m_colorram;
25	25	required_shared_ptr<UINT8> m_spriteram;
26	26	required_shared_ptr<UINT8> m_pc3092_data;
27		required_device<discrete_device> m_discrete;
	27	required_device<discrete_device> m_discrete;
28	28	UINT16 m_collision_address;
29	29	UINT8 m_collision_address_clear;
30	30	tilemap_t *m_bg_tilemap;

trunk/src/mame/includes/ninjakd2.h
r18326	r18327
47	47	void omegaf_io_protection_reset();
48	48	void robokid_motion_error_kludge(UINT16 offset);
49	49	void video_init_common(UINT32 vram_alloc_size);
50
	50
51	51	DECLARE_WRITE8_MEMBER(ninjakd2_bankselect_w);
52	52	DECLARE_WRITE8_MEMBER(ninjakd2_soundreset_w);
53	53	DECLARE_WRITE8_MEMBER(ninjakd2_pcm_play_w);

trunk/src/mame/includes/stv.h
r18326	r18327
202	202	UINT32 screen_update_stv_vdp2(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
203	203	TIMER_DEVICE_CALLBACK_MEMBER(saturn_scanline);
204	204	TIMER_DEVICE_CALLBACK_MEMBER(saturn_slave_scanline);
205
	205
206	206	void scu_do_transfer(UINT8 event);
207	207	void scu_test_pending_irq();
208	208	DECLARE_READ32_MEMBER(saturn_scu_r);
r18326	r18327
233	233	void saturn_init_driver(int rgn);
234	234
235	235	int m_scsp_last_line;
236
	236
237	237	};
238	238
239	239	#define MASTER_CLOCK_352 57272720

trunk/src/mame/includes/bfm_sc45.h
r18326	r18327
56	56
57	57	int m_chk41addr;
58	58	bool m_dochk41;
59
	59
60	60	UINT16 m_mainram[0x10000/2];
61	61
62	62

trunk/src/mame/video/ninjakd2.c
r18326	r18327
1	1	/******************************************************************************
2	2
3	3	UPL "sprite framebuffer" hardware
4
	4
5	5	Functions to emulate the video hardware
6	6
7	7	******************************************************************************/
r18326	r18327
118	118	m_robokid_bg0_videoram = auto_alloc_array_clear(machine(), UINT8, vram_alloc_size);
119	119	m_robokid_bg1_videoram = auto_alloc_array_clear(machine(), UINT8, vram_alloc_size);
120	120	m_robokid_bg2_videoram = auto_alloc_array_clear(machine(), UINT8, vram_alloc_size);
121
	121
122	122	save_pointer(NAME(m_robokid_bg0_videoram), vram_alloc_size);
123	123	save_pointer(NAME(m_robokid_bg1_videoram), vram_alloc_size);
124	124	save_pointer(NAME(m_robokid_bg2_videoram), vram_alloc_size);
r18326	r18327
352	352	counts as one sprite drawn.
353	353	This is proven by Mutant Night, which doesn't work correctly (leaves shots
354	354	on screen) if we don't take big sprites into account.
355		*/
	355	*/
356	356
357	357	for (;;)
358	358	{

trunk/src/mame/video/awpvid.c
r18326	r18327
7	7
8	8	This is a primitive handler for generating reels with multiple symbols visible
9	9	hanging off steppers.c .
10
11		TODO: Add any lamping persistance simulations we need.
12	10
	11	TODO: Add any lamping persistance simulations we need.
	12
13	13	**************************************************************************************/
14	14
15	15	#include "emu.h"

trunk/src/mame/video/jack.c
r18326	r18327
133	133	case 0:
134	134	m_bg_tilemap->set_scrolly(offset >> 2, -data);
135	135	break;
136
	136
137	137	// byte 1/2/3: no effect?
138	138	default:
139	139	break;
140	140	}
141
	141
142	142	m_scrollram[offset] = data;
143	143	}
144	144

trunk/src/mame/video/dkong.c
r18326	r18327
129	129	{
130	130	{ RES_NET_AMP_DARLINGTON, 470 * TRS_J1, 470*(1-TRS_J1), 3, { 1000, 470, 220 } },
131	131	{ RES_NET_AMP_DARLINGTON, 470 * TRS_J1, 470*(1-TRS_J1), 3, { 1000, 470, 220 } },
132		{ RES_NET_AMP_EMITTER, 680 * TRS_J1, 680(1-TRS_J1), 2, { 470, 220, 0 } } / radarscp */
	132	{ RES_NET_AMP_EMITTER, 680 * TRS_J1, 680(1-TRS_J1), 2, { 470, 220, 0 } } / radarscp */
133	133	}
134	134	};
135	135
r18326	r18327
139	139	{
140	140	{ RES_NET_AMP_DARLINGTON, 470, 4700, 0, { 0 } },
141	141	{ RES_NET_AMP_DARLINGTON, 470, 4700, 0, { 0 } },
142		{ RES_NET_AMP_EMITTER, 470, 4700, 0, { 0 } } /* radarscp */
	142	{ RES_NET_AMP_EMITTER, 470, 4700, 0, { 0 } } /* radarscp */
143	143	}
144	144	};
145	145
r18326	r18327
713	713	int sig;
714	714
715	715	/* vsync is divided by 2 by a LS161
716		* The resulting 30 Hz signal clocks a LFSR (LS164) operating as a
717		* random number generator.
718		*/
	716	* The resulting 30 Hz signal clocks a LFSR (LS164) operating as a
	717	* random number generator.
	718	*/
719	719
720	720	if ( line_cnt == 0)
721	721	{

199869 Revisions