trunk/src/mess/drivers/a2600.c
| r18298 | r18299 | |
|---|
| 721 | 721 | /* These read handlers will return the byte from the new bank */ |
| 722 | 722 | READ8_MEMBER(a2600_state::modeF8_switch_r) |
| 723 | 723 | { |
| 724 | | modeF8_switch(offset, 0); |
| 724 | if ( !space.debugger_access() ) |
| 725 | { |
| 726 | modeF8_switch(offset, 0); |
| 727 | } |
| 725 | 728 | return m_bank_base[1][0xff8 + offset]; |
| 726 | 729 | } |
| 727 | 730 | |
| 728 | 731 | READ8_MEMBER(a2600_state::modeFA_switch_r) |
| 729 | 732 | { |
| 730 | | modeFA_switch(offset, 0); |
| 733 | if ( !space.debugger_access() ) |
| 734 | { |
| 735 | modeFA_switch(offset, 0); |
| 736 | } |
| 731 | 737 | return m_bank_base[1][0xff8 + offset]; |
| 732 | 738 | } |
| 733 | 739 | |
| 734 | 740 | READ8_MEMBER(a2600_state::modeF6_switch_r) |
| 735 | 741 | { |
| 736 | | modeF6_switch(offset, 0); |
| 742 | if ( ! space.debugger_access() ) |
| 743 | { |
| 744 | modeF6_switch(offset, 0); |
| 745 | } |
| 737 | 746 | return m_bank_base[1][0xff6 + offset]; |
| 738 | 747 | } |
| 739 | 748 | |
| 740 | 749 | READ8_MEMBER(a2600_state::modeF4_switch_r) |
| 741 | 750 | { |
| 742 | | modeF4_switch(offset, 0); |
| 751 | if ( ! space.debugger_access() ) |
| 752 | { |
| 753 | modeF4_switch(offset, 0); |
| 754 | } |
| 743 | 755 | return m_bank_base[1][0xff4 + offset]; |
| 744 | 756 | } |
| 745 | 757 | |
| 746 | 758 | READ8_MEMBER(a2600_state::modeE0_switch_r) |
| 747 | 759 | { |
| 748 | | modeE0_switch(offset, 0); |
| 760 | if ( ! space.debugger_access() ) |
| 761 | { |
| 762 | modeE0_switch(offset, 0); |
| 763 | } |
| 749 | 764 | return m_bank_base[4][0x3e0 + offset]; |
| 750 | 765 | } |
| 751 | 766 | |
| 752 | 767 | READ8_MEMBER(a2600_state::modeE7_switch_r) |
| 753 | 768 | { |
| 754 | | modeE7_switch(offset, 0); |
| 769 | if ( ! space.debugger_access() ) |
| 770 | { |
| 771 | modeE7_switch(offset, 0); |
| 772 | } |
| 755 | 773 | return m_bank_base[1][0xfe0 + offset]; |
| 756 | 774 | } |
| 757 | 775 | |
| 758 | 776 | READ8_MEMBER(a2600_state::modeE7_RAM_switch_r) |
| 759 | 777 | { |
| 760 | | modeE7_RAM_switch(offset, 0); |
| 778 | if ( ! space.debugger_access() ) |
| 779 | { |
| 780 | modeE7_RAM_switch(offset, 0); |
| 781 | } |
| 761 | 782 | return 0; |
| 762 | 783 | } |
| 763 | 784 | |
| 764 | 785 | READ8_MEMBER(a2600_state::modeUA_switch_r) |
| 765 | 786 | { |
| 766 | | modeUA_switch(offset, 0); |
| 787 | if ( ! space.debugger_access() ) |
| 788 | { |
| 789 | modeUA_switch(offset, 0); |
| 790 | } |
| 767 | 791 | return 0; |
| 768 | 792 | } |
| 769 | 793 | |
| 770 | 794 | READ8_MEMBER(a2600_state::modeDC_switch_r) |
| 771 | 795 | { |
| 772 | | modeDC_switch(offset, 0); |
| 796 | if ( ! space.debugger_access() ) |
| 797 | { |
| 798 | modeDC_switch(offset, 0); |
| 799 | } |
| 773 | 800 | return m_bank_base[1][0xff0 + offset]; |
| 774 | 801 | } |
| 775 | 802 | |
| 776 | 803 | READ8_MEMBER(a2600_state::modeFV_switch_r) |
| 777 | 804 | { |
| 778 | | modeFV_switch(offset, 0); |
| 805 | if ( ! space.debugger_access() ) |
| 806 | { |
| 807 | modeFV_switch(offset, 0); |
| 808 | } |
| 779 | 809 | return m_bank_base[1][0xfd0 + offset]; |
| 780 | 810 | } |
| 781 | 811 | |
| 782 | 812 | READ8_MEMBER(a2600_state::modeJVP_switch_r) |
| 783 | 813 | { |
| 784 | | modeJVP_switch(offset, 0); |
| 814 | if ( ! space.debugger_access() ) |
| 815 | { |
| 816 | modeJVP_switch(offset, 0); |
| 817 | } |
| 785 | 818 | return m_riot_ram[ 0x20 + offset ]; |
| 786 | 819 | } |
| 787 | 820 | |