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r18263 Wednesday 3rd October, 2012 at 14:09:31 UTC by Miodrag Milanović
cleanup (nw)
[src/mess/drivers]pcw16.c
[src/mess/includes]pcw16.h

trunk/src/mess/includes/pcw16.h
r18262r18263
9595   UINT8 read_bank_data(UINT8 type, UINT16 offset);
9696   void write_bank_data(UINT8 type, UINT16 offset, UINT8 data);
9797   virtual void machine_start();
98   virtual void machine_reset();
9899   virtual void video_start();
99100   virtual void palette_init();
100101   UINT32 screen_update_pcw16(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
trunk/src/mess/drivers/pcw16.c
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152152
153153static ADDRESS_MAP_START(pcw16_map, AS_PROGRAM, 8, pcw16_state )
154154   AM_RANGE(0x0000, 0xffff) AM_READWRITE(pcw16_mem_r, pcw16_mem_w)
155//  AM_RANGE(0x0000, 0x3fff) AM_READ_BANK("bank1") AM_WRITE_BANK("bank5")
156//  AM_RANGE(0x4000, 0x7fff) AM_READ_BANK("bank2") AM_WRITE_BANK("bank6")
157//  AM_RANGE(0x8000, 0xbfff) AM_READ_BANK("bank3") AM_WRITE_BANK("bank7")
158//  AM_RANGE(0xc000, 0xffff) AM_READ_BANK("bank4") AM_WRITE_BANK("bank8")
159155ADDRESS_MAP_END
160156
161157
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164160   m_colour_palette[offset & 0x0f] = data & 31;
165161}
166162
167/*
168static const char *const pcw16_write_handler_dram[4] =
169{
170   "bank5",
171   "bank6",
172   "bank7",
173   "bank8"
174};
175
176static const char *const pcw16_read_handler_dram[4] =
177{
178   "bank1",
179   "bank2",
180   "bank3",
181   "bank4"
182};
183
184
185
186// PCW16 Flash interface
187// PCW16 can have two 1mb flash chips
188
189// read flash0
190static int pcw16_flash0_bank_handler_r(running_machine &machine, int bank, int offset)
191{
192   pcw16_state *state = machine.driver_data<pcw16_state>();
193   intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash0");
194   int flash_offset = (state->m_banks[bank]<<14) | offset;
195   return flash->read(flash_offset);
196}
197
198// read flash1
199static int pcw16_flash1_bank_handler_r(running_machine &machine, int bank, int offset)
200{
201   pcw16_state *state = machine.driver_data<pcw16_state>();
202   intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash1");
203   int flash_offset = ((state->m_banks[bank]&0x03f)<<14) | offset;
204
205   return flash->read(flash_offset);
206}
207
208// flash 0
209static  READ8_HANDLER(pcw16_flash0_bank_handler0_r)
210{
211   return pcw16_flash0_bank_handler_r(space.machine(),0, offset);
212}
213
214static  READ8_HANDLER(pcw16_flash0_bank_handler1_r)
215{
216   return pcw16_flash0_bank_handler_r(space.machine(),1, offset);
217}
218
219static  READ8_HANDLER(pcw16_flash0_bank_handler2_r)
220{
221   return pcw16_flash0_bank_handler_r(space.machine(),2, offset);
222}
223
224static  READ8_HANDLER(pcw16_flash0_bank_handler3_r)
225{
226   return pcw16_flash0_bank_handler_r(space.machine(),3, offset);
227}
228
229// flash 1
230static  READ8_HANDLER(pcw16_flash1_bank_handler0_r)
231{
232   return pcw16_flash1_bank_handler_r(space.machine(),0, offset);
233}
234
235static  READ8_HANDLER(pcw16_flash1_bank_handler1_r)
236{
237   return pcw16_flash1_bank_handler_r(space.machine(),1, offset);
238}
239
240static  READ8_HANDLER(pcw16_flash1_bank_handler2_r)
241{
242   return pcw16_flash1_bank_handler_r(space.machine(),2, offset);
243}
244
245static  READ8_HANDLER(pcw16_flash1_bank_handler3_r)
246{
247   return pcw16_flash1_bank_handler_r(space.machine(),3, offset);
248}
249
250static const struct { read8_space_func func; const char *name; } pcw16_flash0_bank_handlers_r[4] =
251{
252   { FUNC(pcw16_flash0_bank_handler0_r) },
253   { FUNC(pcw16_flash0_bank_handler1_r) },
254   { FUNC(pcw16_flash0_bank_handler2_r) },
255   { FUNC(pcw16_flash0_bank_handler3_r) }
256};
257
258static const struct { read8_space_func func; const char *name; } pcw16_flash1_bank_handlers_r[4] =
259{
260   { FUNC(pcw16_flash1_bank_handler0_r) },
261   { FUNC(pcw16_flash1_bank_handler1_r) },
262   { FUNC(pcw16_flash1_bank_handler2_r) },
263   { FUNC(pcw16_flash1_bank_handler3_r) }
264};
265
266// write flash0
267static void pcw16_flash0_bank_handler_w(running_machine &machine, int bank, int offset, int data)
268{
269   pcw16_state *state = machine.driver_data<pcw16_state>();
270   intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash0");
271
272   int flash_offset = (state->m_banks[bank]<<14) | offset;
273
274   flash->write(flash_offset, data);
275}
276
277// read flash1
278static void pcw16_flash1_bank_handler_w(running_machine &machine, int bank, int offset, int data)
279{
280   pcw16_state *state = machine.driver_data<pcw16_state>();
281   intel_e28f008sa_device *flash = machine.device<intel_e28f008sa_device>("flash1");
282
283   int flash_offset = ((state->m_banks[bank]&0x03f)<<14) | offset;
284
285   flash->write(flash_offset,data);
286}
287
288// flash 0
289static WRITE8_HANDLER(pcw16_flash0_bank_handler0_w)
290{
291   pcw16_flash0_bank_handler_w(space.machine(),0, offset, data);
292}
293
294
295static WRITE8_HANDLER(pcw16_flash0_bank_handler1_w)
296{
297   pcw16_flash0_bank_handler_w(space.machine(),1, offset, data);
298}
299
300static WRITE8_HANDLER(pcw16_flash0_bank_handler2_w)
301{
302   pcw16_flash0_bank_handler_w(space.machine(),2, offset, data);
303}
304
305static WRITE8_HANDLER(pcw16_flash0_bank_handler3_w)
306{
307   pcw16_flash0_bank_handler_w(space.machine(),3, offset, data);
308}
309
310
311// flash 1
312static WRITE8_HANDLER(pcw16_flash1_bank_handler0_w)
313{
314   pcw16_flash1_bank_handler_w(space.machine(),0, offset, data);
315}
316
317
318static WRITE8_HANDLER(pcw16_flash1_bank_handler1_w)
319{
320   pcw16_flash1_bank_handler_w(space.machine(),1, offset, data);
321}
322
323static WRITE8_HANDLER(pcw16_flash1_bank_handler2_w)
324{
325   pcw16_flash1_bank_handler_w(space.machine(),2, offset, data);
326}
327
328static WRITE8_HANDLER(pcw16_flash1_bank_handler3_w)
329{
330   pcw16_flash1_bank_handler_w(space.machine(),3, offset, data);
331}
332
333static const struct { write8_space_func func; const char *name; } pcw16_flash0_bank_handlers_w[4] =
334{
335   { FUNC(pcw16_flash0_bank_handler0_w) },
336   { FUNC(pcw16_flash0_bank_handler1_w) },
337   { FUNC(pcw16_flash0_bank_handler2_w) },
338   { FUNC(pcw16_flash0_bank_handler3_w) }
339};
340
341static const struct { write8_space_func func; const char *name; } pcw16_flash1_bank_handlers_w[4] =
342{
343   { FUNC(pcw16_flash1_bank_handler0_w) },
344   { FUNC(pcw16_flash1_bank_handler1_w) },
345   { FUNC(pcw16_flash1_bank_handler2_w) },
346   { FUNC(pcw16_flash1_bank_handler3_w) }
347};
348
349enum PCW16_RAM_TYPE
350{
351   // rom which is really first block of flash0
352   PCW16_MEM_ROM,
353   // flash 0
354   PCW16_MEM_FLASH_1,
355   // flash 1 i.e. unexpanded pcw16
356   PCW16_MEM_FLASH_2,
357   // dram
358   PCW16_MEM_DRAM,
359   // no mem. i.e. unexpanded pcw16
360   PCW16_MEM_NONE
361};
362
363READ8_MEMBER(pcw16_state::pcw16_no_mem_r)
364{
365   return 0x0ff;
366}
367
368
369static void pcw16_set_bank_handlers(running_machine &machine, int bank, PCW16_RAM_TYPE type)
370{
371    address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
372    pcw16_state *state = machine.driver_data<pcw16_state>();
373    switch (type) {
374    case PCW16_MEM_ROM:
375        // rom
376        space.install_read_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_read_handler_dram[bank]);
377        space.nop_write((bank * 0x4000), (bank * 0x4000) + 0x3fff);
378        break;
379
380    case PCW16_MEM_FLASH_1:
381        // sram
382        space.install_legacy_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash0_bank_handlers_r[bank].func, pcw16_flash0_bank_handlers_r[bank].name);
383        space.install_legacy_write_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash0_bank_handlers_w[bank].func, pcw16_flash0_bank_handlers_w[bank].name);
384        break;
385
386    case PCW16_MEM_FLASH_2:
387        space.install_legacy_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash1_bank_handlers_r[bank].func, pcw16_flash1_bank_handlers_r[bank].name);
388        space.install_legacy_write_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_flash1_bank_handlers_w[bank].func, pcw16_flash1_bank_handlers_w[bank].name);
389        break;
390
391    case PCW16_MEM_NONE:
392        space.install_read_handler((bank * 0x4000), (bank * 0x4000) + 0x3fff, read8_delegate(FUNC(pcw16_state::pcw16_no_mem_r),state));
393        space.nop_write((bank * 0x4000), (bank * 0x4000) + 0x3fff);
394        break;
395
396    default:
397    case PCW16_MEM_DRAM:
398        // dram
399        space.install_read_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_read_handler_dram[bank]);
400        space.install_write_bank((bank * 0x4000), (bank * 0x4000) + 0x3fff, pcw16_write_handler_dram[bank]);
401        break;
402    }
403
404}
405
406static void pcw16_update_bank(running_machine &machine, int bank)
407{
408    pcw16_state *state = machine.driver_data<pcw16_state>();
409    unsigned char *mem_ptr = NULL; // machine.device<ram_device>(RAM_TAG)->pointer();
410    int bank_id = 0;
411    int bank_offs = 0;
412    char bank1[10];
413    char bank2[10];
414
415    // get memory bank
416    bank_id = state->m_banks[bank];
417
418
419    if ((bank_id & 0x080)==0)
420    {
421        bank_offs = 0;
422
423        if (bank_id<4)
424        {
425            //lower 4 banks are write protected. Use the rom
426            //loaded
427            mem_ptr = &state->memregion("maincpu")->base()[0x010000];
428        }
429        else
430        {
431            intelfsh8_device *flashdev;
432
433            // nvram
434            if ((bank_id & 0x040)==0)
435            {
436                flashdev = machine.device<intelfsh8_device>("flash0");
437            }
438            else
439            {
440                flashdev = machine.device<intelfsh8_device>("flash1");
441            }
442
443            mem_ptr = (unsigned char *)flashdev->space().get_read_ptr(0);
444        }
445
446    }
447    else
448    {
449        bank_offs = 128;
450         //dram
451        mem_ptr = machine.device<ram_device>(RAM_TAG)->pointer();
452    }
453
454    mem_ptr = mem_ptr + ((bank_id - bank_offs)<<14);
455    state->m_mem_ptr[bank] = (char*)mem_ptr;
456    sprintf(bank1,"bank%d",(bank+1));
457    sprintf(bank2,"bank%d",(bank+5));
458    state->membank(bank1)->set_base(mem_ptr);
459    state->membank(bank2)->set_base(mem_ptr);
460
461    if ((bank_id & 0x080)==0)
462    {
463        // selections 0-3 within the first 64k are write protected
464        if (bank_id<4)
465        {
466            // rom
467            pcw16_set_bank_handlers(machine, bank, PCW16_MEM_ROM);
468        }
469        else
470        {
471            // selections 0-63 are for flash-rom 0, selections
472            // 64-128 are for flash-rom 1
473            if ((bank_id & 0x040)==0)
474            {
475                pcw16_set_bank_handlers(machine, bank, PCW16_MEM_FLASH_1);
476            }
477            else
478            {
479                pcw16_set_bank_handlers(machine, bank, PCW16_MEM_FLASH_2);
480            }
481        }
482    }
483    else
484    {
485        pcw16_set_bank_handlers(machine, bank, PCW16_MEM_DRAM);
486    }
487}
488
489
490// update memory h/w
491static void pcw16_update_memory(running_machine &machine)
492{
493  pcw16_update_bank(machine, 0);
494  pcw16_update_bank(machine, 1);
495  pcw16_update_bank(machine, 2);
496  pcw16_update_bank(machine, 3);
497
498}
499*/
500163UINT8 pcw16_state::read_bank_data(UINT8 type, UINT16 offset)
501164{
502165   if(type & 0x80) // DRAM
r18262r18263
621284   //logerror("bank w: %d block: %02x\n", offset, data);
622285
623286   m_banks[offset] = data;
624
625   //pcw16_update_memory(machine());
626287}
627288
628289WRITE8_MEMBER(pcw16_state::pcw16_video_control_w)
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13921053ADDRESS_MAP_END
13931054
13941055
1395static void pcw16_reset(running_machine &machine)
1056void pcw16_state::machine_reset()
13961057{
1397   pcw16_state *state = machine.driver_data<pcw16_state>();
13981058   /* initialise defaults */
1399   state->m_fdc_int_code = 2;
1059   m_fdc_int_code = 2;
14001060   /* clear terminal count */
1401   pc_fdc_set_tc_state(machine, 0);
1061   pc_fdc_set_tc_state(machine(), 0);
14021062   /* select first rom page */
1403   state->m_banks[0] = 0;
1063   m_banks[0] = 0;
14041064//  pcw16_update_memory(machine);
14051065
14061066   /* temp rtc setup */
1407   state->m_rtc_seconds = 0;
1408   state->m_rtc_minutes = 0;
1409   state->m_rtc_hours = 0;
1410   state->m_rtc_days_max = 0;
1411   state->m_rtc_days = 1;
1412   state->m_rtc_months = 1;
1413   state->m_rtc_years = 0;
1414   state->m_rtc_control = 1;
1415   state->m_rtc_256ths_seconds = 0;
1067   m_rtc_seconds = 0;
1068   m_rtc_minutes = 0;
1069   m_rtc_hours = 0;
1070   m_rtc_days_max = 0;
1071   m_rtc_days = 1;
1072   m_rtc_months = 1;
1073   m_rtc_years = 0;
1074   m_rtc_control = 1;
1075   m_rtc_256ths_seconds = 0;
14161076
1417   state->pcw16_keyboard_init();
1077   pcw16_keyboard_init();
14181078}
14191079
14201080
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14301090   at_keyboard_init(machine(), AT_KEYBOARD_TYPE_AT);
14311091   at_keyboard_set_scan_code_set(3);
14321092
1433   pcw16_reset(machine());
1434
14351093   beep_set_state(speaker,0);
14361094   beep_set_frequency(speaker,3750);
14371095}

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