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r18261 Wednesday 3rd October, 2012 at 13:45:23 UTC by Miodrag Milanović
modernization and cleanup of x68k (no whatsnew)

[src/mess/drivers]	x68k.c
[src/mess/includes]	x68k.h
[src/mess/video]	x68k.c

trunk/src/mess/drivers/x68k.c

r18260	r18261
168	168	}
169	169	#endif
170	170
171		static void mfp_init(running_machine &machine)
	171	void x68k_state::mfp_init()
172	172	{
173		x68k_state *state = machine.driver_data<x68k_state>();
174		state->m_mfp.tadr = state->m_mfp.tbdr = state->m_mfp.tcdr = state->m_mfp.tddr = 0xff;
	173	m_mfp.tadr = m_mfp.tbdr = m_mfp.tcdr = m_mfp.tddr = 0xff;
175	174
176		state->m_mfp.irqline = 6;  // MFP is connected to 68000 IRQ line 6
177		state->m_mfp.current_irq = -1;  // No current interrupt
	175	m_mfp.irqline = 6;  // MFP is connected to 68000 IRQ line 6
	176	m_mfp.current_irq = -1;  // No current interrupt
178	177
179	178	#if 0
180	179	mfp_timer[0] = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(x68k_state::mfp_timer_a_callback),this));
r18260	r18261
338	337	}
339	338
340	339	// 4 channel DMA controller (Hitachi HD63450)
341		static WRITE16_HANDLER( x68k_dmac_w )
	340	WRITE16_HANDLER(x68k_state::x68k_dmac_w)
342	341	{
343		device_t* device = space.machine().device("hd63450");
	342	device_t* device = machine().device("hd63450");
344	343	hd63450_w(device, space, offset, data, mem_mask);
345	344	}
346	345
347		static READ16_HANDLER( x68k_dmac_r )
	346	READ16_HANDLER(x68k_state::x68k_dmac_r)
348	347	{
349		device_t* device = space.machine().device("hd63450");
	348	device_t* device = machine().device("hd63450");
350	349	return hd63450_r(device, space, offset, mem_mask);
351	350	}
352	351
353		static void x68k_keyboard_ctrl_w(x68k_state *state, int data)
	352	void x68k_state::x68k_keyboard_ctrl_w(int data)
354	353	{
355	354	/* Keyboard control commands:
356	355	00xxxxxx - TV Control
r18260	r18261
403	402
404	403	if((data & 0xf8) == 0x48)  // Keyboard enable
405	404	{
406		state->m_keyboard.enabled = data & 0x01;
407		logerror("KB: Keyboard enable bit = %i\n",state->m_keyboard.enabled);
	405	m_keyboard.enabled = data & 0x01;
	406	logerror("KB: Keyboard enable bit = %i\n",m_keyboard.enabled);
408	407	}
409	408
410	409	if((data & 0xf0) == 0x60)  // Key delay time
411	410	{
412		state->m_keyboard.delay = data & 0x0f;
	411	m_keyboard.delay = data & 0x0f;
413	412	logerror("KB: Keypress delay time is now %ims\n",(data & 0x0f)*100+200);
414	413	}
415	414
416	415	if((data & 0xf0) == 0x70)  // Key repeat rate
417	416	{
418		state->m_keyboard.repeat = data & 0x0f;
	417	m_keyboard.repeat = data & 0x0f;
419	418	logerror("KB: Keypress repeat rate is now %ims\n",((data & 0x0f)^2)*5+30);
420	419	}
421	420
422	421	}
423	422
424		static int x68k_keyboard_pop_scancode(x68k_state *state)
	423	int x68k_state::x68k_keyboard_pop_scancode()
425	424	{
426	425	int ret;
427		if(state->m_keyboard.keynum == 0)  // no scancodes in USART buffer
	426	if(m_keyboard.keynum == 0)  // no scancodes in USART buffer
428	427	return 0x00;
429	428
430		state->m_keyboard.keynum--;
431		ret = state->m_keyboard.buffer[state->m_keyboard.tailpos++];
432		if(state->m_keyboard.tailpos > 15)
433		state->m_keyboard.tailpos = 0;
	429	m_keyboard.keynum--;
	430	ret = m_keyboard.buffer[m_keyboard.tailpos++];
	431	if(m_keyboard.tailpos > 15)
	432	m_keyboard.tailpos = 0;
434	433
435	434	logerror("MFP: Keyboard buffer pop 0x%02x\n",ret);
436	435	return ret;
437	436	}
438	437
439		static void x68k_keyboard_push_scancode(running_machine &machine,unsigned char code)
440		{
441		x68k_state *state = machine.driver_data<x68k_state>();
442		state->m_keyboard.keynum++;
443		if(state->m_keyboard.keynum >= 1)
	438	void x68k_state::x68k_keyboard_push_scancode(unsigned char code)
	439	{
	440	m_keyboard.keynum++;
	441	if(m_keyboard.keynum >= 1)
444	442	{ // keyboard buffer full
445		if(state->m_keyboard.enabled != 0)
	443	if(m_keyboard.enabled != 0)
446	444	{
447		state->m_mfp.rsr |= 0x80;  // Buffer full
	445	m_mfp.rsr |= 0x80;  // Buffer full
448	446	//          mfp_trigger_irq(MFP_IRQ_RX_FULL);
449		if(machine.root_device().ioport("options")->read() & 0x01)
	447	if(machine().root_device().ioport("options")->read() & 0x01)
450	448	{
451		state->m_current_vector[6] = 0x4c;
452		machine.device("maincpu")->execute().set_input_line_and_vector(6,ASSERT_LINE,0x4c);
	449	m_current_vector[6] = 0x4c;
	450	machine().device("maincpu")->execute().set_input_line_and_vector(6,ASSERT_LINE,0x4c);
453	451	logerror("MFP: Receive buffer full IRQ sent\n");
454	452	}
455	453	}
456	454	}
457		state->m_keyboard.buffer[state->m_keyboard.headpos++] = code;
458		if(state->m_keyboard.headpos > 15)
	455	m_keyboard.buffer[m_keyboard.headpos++] = code;
	456	if(m_keyboard.headpos > 15)
459	457	{
460		state->m_keyboard.headpos = 0;
	458	m_keyboard.headpos = 0;
461	459	//      mfp_trigger_irq(MFP_IRQ_RX_ERROR);
462		state->m_current_vector[6] = 0x4b;
	460	m_current_vector[6] = 0x4b;
463	461	//      machine.device("maincpu")->execute().set_input_line_and_vector(6,ASSERT_LINE,0x4b);
464	462	}
465	463	}
r18260	r18261
480	478	{
481	479	if(m_keyboard.keyon[x] != 0)
482	480	{
483		x68k_keyboard_push_scancode(machine(),0x80 + x);
	481	x68k_keyboard_push_scancode(0x80 + x);
484	482	m_keyboard.keytime[x] = 0;
485	483	m_keyboard.keyon[x] = 0;
486	484	m_keyboard.last_pressed = 0;
r18260	r18261
492	490	{
493	491	if(machine().root_device().ioport(keynames[m_keyboard.last_pressed / 32])->read() & (1 << (m_keyboard.last_pressed % 32)))
494	492	{
495		x68k_keyboard_push_scancode(machine(),m_keyboard.last_pressed);
	493	x68k_keyboard_push_scancode(m_keyboard.last_pressed);
496	494	m_keyboard.keytime[m_keyboard.last_pressed] = (m_keyboard.repeat^2)*5+30;
497	495	logerror("KB: Holding key 0x%02x\n",m_keyboard.last_pressed);
498	496	}
r18260	r18261
501	499	{
502	500	if(m_keyboard.keyon[x] == 0)
503	501	{
504		x68k_keyboard_push_scancode(machine(),x);
	502	x68k_keyboard_push_scancode(x);
505	503	m_keyboard.keytime[x] = m_keyboard.delay * 100 + 200;
506	504	m_keyboard.keyon[x] = 1;
507	505	m_keyboard.last_pressed = x;
r18260	r18261
528	526	// mouse input
529	527	// port B of the Z8530 SCC
530	528	// typically read from the SCC data port on receive buffer full interrupt per byte
531		static int x68k_read_mouse(running_machine &machine)
	529	int x68k_state::x68k_read_mouse()
532	530	{
533		x68k_state *state = machine.driver_data<x68k_state>();
534		scc8530_t *scc = machine.device<scc8530_t>("scc");
	531	scc8530_t *scc = machine().device<scc8530_t>("scc");
535	532	char val = 0;
536	533	char ipt = 0;
537	534
538	535	if(!(scc->get_reg_b(5) & 0x02))
539	536	return 0xff;
540	537
541		switch(state->m_mouse.inputtype)
	538	switch(m_mouse.inputtype)
542	539	{
543	540	case 0:
544		ipt = machine.root_device().ioport("mouse1")->read();
	541	ipt = machine().root_device().ioport("mouse1")->read();
545	542	break;
546	543	case 1:
547		val = machine.root_device().ioport("mouse2")->read();
548		ipt = val - state->m_mouse.last_mouse_x;
549		state->m_mouse.last_mouse_x = val;
	544	val = machine().root_device().ioport("mouse2")->read();
	545	ipt = val - m_mouse.last_mouse_x;
	546	m_mouse.last_mouse_x = val;
550	547	break;
551	548	case 2:
552		val = machine.root_device().ioport("mouse3")->read();
553		ipt = val - state->m_mouse.last_mouse_y;
554		state->m_mouse.last_mouse_y = val;
	549	val = machine().root_device().ioport("mouse3")->read();
	550	ipt = val - m_mouse.last_mouse_y;
	551	m_mouse.last_mouse_y = val;
555	552	break;
556	553	}
557		state->m_mouse.inputtype++;
558		if(state->m_mouse.inputtype > 2)
	554	m_mouse.inputtype++;
	555	if(m_mouse.inputtype > 2)
559	556	{
560	557	int i_val = scc->get_reg_b(0);
561		state->m_mouse.inputtype = 0;
562		state->m_mouse.bufferempty = 1;
	558	m_mouse.inputtype = 0;
	559	m_mouse.bufferempty = 1;
563	560	i_val &= ~0x01;
564	561	scc->set_reg_b(0, i_val);
565	562	logerror("SCC: mouse buffer empty\n");
r18260	r18261
574	571	0xe98005 - Z8530 command port A
575	572	0xe98007 - Z8530 data port A  (RS232)
576	573	*/
577		static READ16_HANDLER( x68k_scc_r )
	574	READ16_MEMBER(x68k_state::x68k_scc_r )
578	575	{
579		scc8530_t *scc = space.machine().device<scc8530_t>("scc");
	576	scc8530_t *scc = machine().device<scc8530_t>("scc");
580	577	offset %= 4;
581	578	switch(offset)
582	579	{
583	580	case 0:
584	581	return scc->reg_r(space, 0);
585	582	case 1:
586		return x68k_read_mouse(space.machine());
	583	return x68k_read_mouse();
587	584	case 2:
588	585	return scc->reg_r(space, 1);
589	586	case 3:
r18260	r18261
593	590	}
594	591	}
595	592
596		static WRITE16_HANDLER( x68k_scc_w )
	593	WRITE16_MEMBER(x68k_state::x68k_scc_w )
597	594	{
598		x68k_state *state = space.machine().driver_data<x68k_state>();
599		scc8530_t *scc = space.machine().device<scc8530_t>("scc");
	595	scc8530_t *scc = machine().device<scc8530_t>("scc");
600	596	offset %= 4;
601	597
602	598	switch(offset)
603	599	{
604	600	case 0:
605	601	scc->reg_w(space, 0,(UINT8)data);
606		if((scc->get_reg_b(5) & 0x02) != state->m_scc_prev)
	602	if((scc->get_reg_b(5) & 0x02) != m_scc_prev)
607	603	{
608	604	if(scc->get_reg_b(5) & 0x02)  // Request to Send
609	605	{
610	606	int val = scc->get_reg_b(0);
611		state->m_mouse.bufferempty = 0;
	607	m_mouse.bufferempty = 0;
612	608	val |= 0x01;
613	609	scc->set_reg_b(0,val);
614	610	}
r18260	r18261
624	620	scc->reg_w(space, 3,(UINT8)data);
625	621	break;
626	622	}
627		state->m_scc_prev = scc->get_reg_b(5) & 0x02;
	623	m_scc_prev = scc->get_reg_b(5) & 0x02;
628	624	}
629	625
630	626	TIMER_CALLBACK_MEMBER(x68k_state::x68k_scc_ack)
r18260	r18261
652	648	}
653	649	}
654	650
655		static void x68k_set_adpcm(running_machine &machine)
	651	void x68k_state::x68k_set_adpcm()
656	652	{
657		x68k_state *state = machine.driver_data<x68k_state>();
658		device_t *dev = machine.device("hd63450");
	653	device_t *dev = machine().device("hd63450");
659	654	UINT32 rate = 0;
660	655
661		switch(state->m_adpcm.rate & 0x0c)
	656	switch(m_adpcm.rate & 0x0c)
662	657	{
663	658	case 0x00:
664	659	rate = 7812/2;
r18260	r18261
673	668	logerror("PPI: Invalid ADPCM sample rate set.\n");
674	669	rate = 15625/2;
675	670	}
676		if(state->m_adpcm.clock != 0)
	671	if(m_adpcm.clock != 0)
677	672	rate = rate/2;
678	673	hd63450_set_timer(dev,3,attotime::from_hz(rate));
679	674	}
r18260	r18261
684	679	// Button inputs (Start, A, B and C) are read in bits 5 and 6 (rather than 4
685	680	// and 5 like on a Megadrive)
686	681
687		static UINT8 md_3button_r(device_t* device, int port)
	682	UINT8 x68k_state::md_3button_r(int port)
688	683	{
689		x68k_state *state = device->machine().driver_data<x68k_state>();
690	684	if(port == 1)
691	685	{
692		UINT8 porta = device->machine().root_device().ioport("md3b")->read() & 0xff;
693		UINT8 portb = (state->ioport("md3b")->read() >> 8) & 0xff;
694		if(state->m_mdctrl.mux1 & 0x10)
	686	UINT8 porta = machine().root_device().ioport("md3b")->read() & 0xff;
	687	UINT8 portb = (ioport("md3b")->read() >> 8) & 0xff;
	688	if(m_mdctrl.mux1 & 0x10)
695	689	{
696	690	return porta | 0x90;
697	691	}
r18260	r18261
702	696	}
703	697	if(port == 2)
704	698	{
705		UINT8 porta = (device->machine().root_device().ioport("md3b")->read() >> 16) & 0xff;
706		UINT8 portb = (device->machine().root_device().ioport("md3b")->read() >> 24) & 0xff;
707		if(state->m_mdctrl.mux2 & 0x20)
	699	UINT8 porta = (machine().root_device().ioport("md3b")->read() >> 16) & 0xff;
	700	UINT8 portb = (machine().root_device().ioport("md3b")->read() >> 24) & 0xff;
	701	if(m_mdctrl.mux2 & 0x20)
708	702	{
709	703	return porta | 0x90;
710	704	}
r18260	r18261
727	721	m_mdctrl.seq2 = 0;
728	722	}
729	723
730		static void md_6button_init(running_machine &machine)
	724	void x68k_state::md_6button_init()
731	725	{
732		x68k_state *state = machine.driver_data<x68k_state>();
733		state->m_mdctrl.io_timeout1 = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(x68k_state::md_6button_port1_timeout),state));
734		state->m_mdctrl.io_timeout2 = machine.scheduler().timer_alloc(timer_expired_delegate(FUNC(x68k_state::md_6button_port2_timeout),state));
	726	m_mdctrl.io_timeout1 = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x68k_state::md_6button_port1_timeout),this));
	727	m_mdctrl.io_timeout2 = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x68k_state::md_6button_port2_timeout),this));
735	728	}
736	729
737		static UINT8 md_6button_r(device_t* device, int port)
	730	UINT8 x68k_state::md_6button_r(int port)
738	731	{
739		x68k_state *state = device->machine().driver_data<x68k_state>();
740	732	if(port == 1)
741	733	{
742		UINT8 porta = device->machine().root_device().ioport("md6b")->read() & 0xff;
743		UINT8 portb = (device->machine().root_device().ioport("md6b")->read() >> 8) & 0xff;
744		UINT8 extra = state->ioport("md6b_extra")->read() & 0x0f;
	734	UINT8 porta = machine().root_device().ioport("md6b")->read() & 0xff;
	735	UINT8 portb = (machine().root_device().ioport("md6b")->read() >> 8) & 0xff;
	736	UINT8 extra = ioport("md6b_extra")->read() & 0x0f;
745	737
746		switch(state->m_mdctrl.seq1)
	738	switch(m_mdctrl.seq1)
747	739	{
748	740	case 1:
749	741	default:
750		if(state->m_mdctrl.mux1 & 0x10)
	742	if(m_mdctrl.mux1 & 0x10)
751	743	{
752	744	return porta | 0x90;
753	745	}
r18260	r18261
756	748	return (portb & 0x60) | (porta & 0x03) | 0x90;
757	749	}
758	750	case 2:
759		if(state->m_mdctrl.mux1 & 0x10)
	751	if(m_mdctrl.mux1 & 0x10)
760	752	{
761	753	return porta | 0x90;
762	754	}
r18260	r18261
765	757	return (portb & 0x60) | 0x90;
766	758	}
767	759	case 3:
768		if(state->m_mdctrl.mux1 & 0x10)
	760	if(m_mdctrl.mux1 & 0x10)
769	761	{
770	762	return (porta & 0x60) | (extra & 0x0f) | 0x90;
771	763	}
r18260	r18261
777	769	}
778	770	if(port == 2)
779	771	{
780		UINT8 porta = (device->machine().root_device().ioport("md6b")->read() >> 16) & 0xff;
781		UINT8 portb = (device->machine().root_device().ioport("md6b")->read() >> 24) & 0xff;
782		UINT8 extra = (device->machine().root_device().ioport("md6b_extra")->read() >> 4) & 0x0f;
	772	UINT8 porta = (machine().root_device().ioport("md6b")->read() >> 16) & 0xff;
	773	UINT8 portb = (machine().root_device().ioport("md6b")->read() >> 24) & 0xff;
	774	UINT8 extra = (machine().root_device().ioport("md6b_extra")->read() >> 4) & 0x0f;
783	775
784		switch(state->m_mdctrl.seq2)
	776	switch(m_mdctrl.seq2)
785	777	{
786	778	case 1:
787	779	default:
788		if(state->m_mdctrl.mux2 & 0x20)
	780	if(m_mdctrl.mux2 & 0x20)
789	781	{
790	782	return porta | 0x90;
791	783	}
r18260	r18261
794	786	return (portb & 0x60) | (porta & 0x03) | 0x90;
795	787	}
796	788	case 2:
797		if(state->m_mdctrl.mux2 & 0x20)
	789	if(m_mdctrl.mux2 & 0x20)
798	790	{
799	791	return porta | 0x90;
800	792	}
r18260	r18261
803	795	return (portb & 0x60) | 0x90;
804	796	}
805	797	case 3:
806		if(state->m_mdctrl.mux2 & 0x20)
	798	if(m_mdctrl.mux2 & 0x20)
807	799	{
808	800	return (porta & 0x60) | (extra & 0x0f) | 0x90;
809	801	}
r18260	r18261
823	815	// Output is the same as for standard controllers, but when ctl is high,
824	816	// the directions refer to the right D-pad, and when low, the left D-pad
825	817	// The buttons are read the same as normal, regardless of ctl.
826		static UINT8 xpd1lr_r(device_t* device, int port)
	818	UINT8 x68k_state::xpd1lr_r(int port)
827	819	{
828		x68k_state *state = device->machine().driver_data<x68k_state>();
829	820	if(port == 1)
830	821	{
831		UINT8 porta = device->machine().root_device().ioport("xpd1lr")->read() & 0xff;
832		UINT8 portb = (state->ioport("xpd1lr")->read() >> 8) & 0xff;
833		if(state->m_mdctrl.mux1 & 0x10)
	822	UINT8 porta = machine().root_device().ioport("xpd1lr")->read() & 0xff;
	823	UINT8 portb = (ioport("xpd1lr")->read() >> 8) & 0xff;
	824	if(m_mdctrl.mux1 & 0x10)
834	825	{
835	826	return porta;
836	827	}
r18260	r18261
841	832	}
842	833	if(port == 2)
843	834	{
844		UINT8 porta = (device->machine().root_device().ioport("xpd1lr")->read() >> 16) & 0xff;
845		UINT8 portb = (device->machine().root_device().ioport("xpd1lr")->read() >> 24) & 0xff;
846		if(state->m_mdctrl.mux2 & 0x20)
	835	UINT8 porta = (machine().root_device().ioport("xpd1lr")->read() >> 16) & 0xff;
	836	UINT8 portb = (machine().root_device().ioport("xpd1lr")->read() >> 24) & 0xff;
	837	if(m_mdctrl.mux2 & 0x20)
847	838	{
848	839	return porta;
849	840	}
r18260	r18261
868	859	else
869	860	return 0xff;
870	861	case 0x01:  // 3-button Megadrive gamepad
871		return md_3button_r(machine().device("ppi8255"),1);
	862	return md_3button_r(1);
872	863	case 0x02:  // 6-button Megadrive gamepad
873		return md_6button_r(machine().device("ppi8255"),1);
	864	return md_6button_r(1);
874	865	case 0x03:  // XPD-1LR
875		return xpd1lr_r(machine().device("ppi8255"),1);
	866	return xpd1lr_r(1);
876	867	}
877	868
878	869	return 0xff;
r18260	r18261
890	881	else
891	882	return 0xff;
892	883	case 0x10:  // 3-button Megadrive gamepad
893		return md_3button_r(machine().device("ppi8255"),2);
	884	return md_3button_r(2);
894	885	case 0x20:  // 6-button Megadrive gamepad
895		return md_6button_r(machine().device("ppi8255"),2);
	886	return md_6button_r(2);
896	887	case 0x30:  // XPD-1LR
897		return xpd1lr_r(machine().device("ppi8255"),2);
	888	return xpd1lr_r(2);
898	889	}
899	890
900	891	return 0xff;
r18260	r18261
923	914	{
924	915	m_adpcm.pan = data & 0x03;
925	916	m_adpcm.rate = data & 0x0c;
926		x68k_set_adpcm(machine());
	917	x68k_set_adpcm();
927	918	okim6258_set_divider(oki, (data >> 2) & 3);
928	919	}
929	920
r18260	r18261
951	942
952	943
953	944	// NEC uPD72065 at 0xe94000
954		static WRITE16_HANDLER( x68k_fdc_w )
	945	WRITE16_MEMBER(x68k_state::x68k_fdc_w)
955	946	{
956		x68k_state *state = space.machine().driver_data<x68k_state>();
957		device_t *fdc = space.machine().device("upd72065");
	947	device_t *fdc = machine().device("upd72065");
958	948	unsigned int drive, x;
959	949	switch(offset)
960	950	{
r18260	r18261
966	956	x = data & 0x0f;
967	957	for(drive=0;drive<4;drive++)
968	958	{
969		if(state->m_fdc.selected_drive & (1 << drive))
	959	if(m_fdc.selected_drive & (1 << drive))
970	960	{
971	961	if(!(x & (1 << drive)))  // functions take place on 1->0 transitions of drive bits only
972	962	{
973		state->m_fdc.led_ctrl[drive] = data & 0x80;  // blinking drive LED if no disk inserted
974		state->m_fdc.led_eject[drive] = data & 0x40;  // eject button LED (on when set to 0)
	963	m_fdc.led_ctrl[drive] = data & 0x80;  // blinking drive LED if no disk inserted
	964	m_fdc.led_eject[drive] = data & 0x40;  // eject button LED (on when set to 0)
975	965	output_set_indexed_value("eject_drv",drive,(data & 0x40) ? 1 : 0);
976	966	if(data & 0x20)  // ejects disk
977	967	{
978		(dynamic_cast<device_image_interface *>(floppy_get_device(space.machine(), drive)))->unload();
979		floppy_mon_w(floppy_get_device(space.machine(), drive), ASSERT_LINE);
	968	(dynamic_cast<device_image_interface *>(floppy_get_device(machine(), drive)))->unload();
	969	floppy_mon_w(floppy_get_device(machine(), drive), ASSERT_LINE);
980	970	}
981	971	}
982	972	}
983	973	}
984		state->m_fdc.selected_drive = data & 0x0f;
	974	m_fdc.selected_drive = data & 0x0f;
985	975	logerror("FDC: signal control set to %02x\n",data);
986	976	break;
987	977	case 0x03:
988		state->m_fdc.media_density[data & 0x03] = data & 0x10;
989		state->m_fdc.motor[data & 0x03] = data & 0x80;
990		floppy_mon_w(floppy_get_device(space.machine(), data & 0x03), !BIT(data, 7));
	978	m_fdc.media_density[data & 0x03] = data & 0x10;
	979	m_fdc.motor[data & 0x03] = data & 0x80;
	980	floppy_mon_w(floppy_get_device(machine(), data & 0x03), !BIT(data, 7));
991	981	if(data & 0x80)
992	982	{
993	983	for(drive=0;drive<4;drive++) // enable motor for this drive
994	984	{
995	985	if(drive == (data & 0x03))
996	986	{
997		floppy_mon_w(floppy_get_device(space.machine(), drive), CLEAR_LINE);
	987	floppy_mon_w(floppy_get_device(machine(), drive), CLEAR_LINE);
998	988	output_set_indexed_value("access_drv",drive,0);
999	989	}
1000	990	else
r18260	r18261
1005	995	{
1006	996	for(drive=0;drive<4;drive++)
1007	997	{
1008		floppy_mon_w(floppy_get_device(space.machine(), drive), ASSERT_LINE);
	998	floppy_mon_w(floppy_get_device(machine(), drive), ASSERT_LINE);
1009	999	output_set_indexed_value("access_drv",drive,1);
1010	1000	}
1011	1001	}
1012		floppy_drive_set_ready_state(floppy_get_device(space.machine(), 0),1,1);
1013		floppy_drive_set_ready_state(floppy_get_device(space.machine(), 1),1,1);
1014		floppy_drive_set_ready_state(floppy_get_device(space.machine(), 2),1,1);
1015		floppy_drive_set_ready_state(floppy_get_device(space.machine(), 3),1,1);
	1002	floppy_drive_set_ready_state(floppy_get_device(machine(), 0),1,1);
	1003	floppy_drive_set_ready_state(floppy_get_device(machine(), 1),1,1);
	1004	floppy_drive_set_ready_state(floppy_get_device(machine(), 2),1,1);
	1005	floppy_drive_set_ready_state(floppy_get_device(machine(), 3),1,1);
1016	1006	#if 0
1017	1007	for(drive=0;drive<4;drive++)
1018	1008	{
r18260	r18261
1030	1020	}
1031	1021	}
1032	1022
1033		static READ16_HANDLER( x68k_fdc_r )
	1023	READ16_MEMBER(x68k_state::x68k_fdc_r)
1034	1024	{
1035		x68k_state *state = space.machine().driver_data<x68k_state>();
1036	1025	unsigned int ret;
1037	1026	int x;
1038		device_t *fdc = space.machine().device("upd72065");
	1027	device_t *fdc = machine().device("upd72065");
1039	1028
1040	1029	switch(offset)
1041	1030	{
r18260	r18261
1047	1036	ret = 0x00;
1048	1037	for(x=0;x<4;x++)
1049	1038	{
1050		if(state->m_fdc.selected_drive & (1 << x))
	1039	if(m_fdc.selected_drive & (1 << x))
1051	1040	{
1052	1041	ret = 0x00;
1053		if(state->m_fdc.disk_inserted[x] != 0)
	1042	if(m_fdc.disk_inserted[x] != 0)
1054	1043	{
1055	1044	ret |= 0x80;
1056	1045	}
r18260	r18261
1104	1093	m_fdc.drq_state = state;
1105	1094	}
1106	1095
1107		static WRITE16_HANDLER( x68k_fm_w )
	1096	WRITE16_MEMBER(x68k_state::x68k_fm_w)
1108	1097	{
1109	1098	switch(offset)
1110	1099	{
1111	1100	case 0x00:
1112	1101	case 0x01:
1113		ym2151_w(space.machine().device("ym2151"), space, offset, data);
	1102	ym2151_w(machine().device("ym2151"), space, offset, data);
1114	1103	break;
1115	1104	}
1116	1105	}
1117	1106
1118		static READ16_HANDLER( x68k_fm_r )
	1107	READ16_MEMBER(x68k_state::x68k_fm_r)
1119	1108	{
1120	1109	if(offset == 0x01)
1121		return ym2151_r(space.machine().device("ym2151"), space, 1);
	1110	return ym2151_r(machine().device("ym2151"), space, 1);
1122	1111
1123	1112	return 0xffff;
1124	1113	}
r18260	r18261
1133	1122	// CT2 - 1 = Set ready state of FDC
1134	1123	upd765_ready_w(fdc,data & 0x01);
1135	1124	m_adpcm.clock = data & 0x02;
1136		x68k_set_adpcm(machine());
	1125	x68k_set_adpcm();
1137	1126	okim6258_set_clock(okim, data & 0x02 ? 4000000 : 8000000);
1138	1127	}
1139	1128
r18260	r18261
1153	1142	- bits 7-2 = vector
1154	1143	- bits 1,0 = device (00 = FDC, 01 = FDD, 10 = HDD, 11 = Printer)
1155	1144	*/
1156		static WRITE16_HANDLER( x68k_ioc_w )
	1145	WRITE16_MEMBER(x68k_state::x68k_ioc_w)
1157	1146	{
1158		x68k_state *state = space.machine().driver_data<x68k_state>();
1159	1147	switch(offset)
1160	1148	{
1161	1149	case 0x00:
1162		state->m_ioc.irqstatus = data & 0x0f;
	1150	m_ioc.irqstatus = data & 0x0f;
1163	1151	logerror("I/O: Status register write %02x\n",data);
1164	1152	break;
1165	1153	case 0x01:
1166	1154	switch(data & 0x03)
1167	1155	{
1168	1156	case 0x00:
1169		state->m_ioc.fdcvector = data & 0xfc;
	1157	m_ioc.fdcvector = data & 0xfc;
1170	1158	logerror("IOC: FDC IRQ vector = 0x%02x\n",data & 0xfc);
1171	1159	break;
1172	1160	case 0x01:
1173		state->m_ioc.fddvector = data & 0xfc;
	1161	m_ioc.fddvector = data & 0xfc;
1174	1162	logerror("IOC: FDD IRQ vector = 0x%02x\n",data & 0xfc);
1175	1163	break;
1176	1164	case 0x02:
1177		state->m_ioc.hdcvector = data & 0xfc;
	1165	m_ioc.hdcvector = data & 0xfc;
1178	1166	logerror("IOC: HDD IRQ vector = 0x%02x\n",data & 0xfc);
1179	1167	break;
1180	1168	case 0x03:
1181		state->m_ioc.prnvector = data & 0xfc;
	1169	m_ioc.prnvector = data & 0xfc;
1182	1170	logerror("IOC: Printer IRQ vector = 0x%02x\n",data & 0xfc);
1183	1171	break;
1184	1172	}
r18260	r18261
1186	1174	}
1187	1175	}
1188	1176
1189		static READ16_HANDLER( x68k_ioc_r )
	1177	READ16_MEMBER(x68k_state::x68k_ioc_r)
1190	1178	{
1191		x68k_state *state = space.machine().driver_data<x68k_state>();
1192	1179	switch(offset)
1193	1180	{
1194	1181	case 0x00:
1195	1182	logerror("I/O: Status register read\n");
1196		return (state->m_ioc.irqstatus & 0xdf) | 0x20;
	1183	return (m_ioc.irqstatus & 0xdf) | 0x20;
1197	1184	default:
1198	1185	return 0x00;
1199	1186	}
r18260	r18261
1219	1206	Any other value, then SRAM is read only.
1220	1207	Port 8 (0xe8e00f) - Power off control - write 0x00, 0x0f, 0x0f sequentially to switch power off.
1221	1208	*/
1222		static WRITE16_HANDLER( x68k_sysport_w )
	1209	WRITE16_MEMBER(x68k_state::x68k_sysport_w)
1223	1210	{
1224		x68k_state *state = space.machine().driver_data<x68k_state>();
1225	1211	switch(offset)
1226	1212	{
1227	1213	case 0x00:
1228		state->m_sysport.contrast = data & 0x0f;  // often used for screen fades / blanking
	1214	m_sysport.contrast = data & 0x0f;  // often used for screen fades / blanking
1229	1215	// TODO: implement a decent, not slow, brightness control
1230	1216	break;
1231	1217	case 0x01:
1232		state->m_sysport.monitor = data & 0x08;
	1218	m_sysport.monitor = data & 0x08;
1233	1219	break;
1234	1220	case 0x03:
1235		state->m_sysport.keyctrl = data & 0x08;  // bit 3 = enable keyboard data transmission
	1221	m_sysport.keyctrl = data & 0x08;  // bit 3 = enable keyboard data transmission
1236	1222	break;
1237	1223	case 0x06:
1238		state->m_sysport.sram_writeprotect = data;
	1224	m_sysport.sram_writeprotect = data;
1239	1225	break;
1240	1226	default:
1241	1227	//      logerror("SYS: [%08x] Wrote %04x to invalid or unimplemented system port %04x\n",space.device().safe_pc(),data,offset);
r18260	r18261
1243	1229	}
1244	1230	}
1245	1231
1246		static READ16_HANDLER( x68k_sysport_r )
	1232	READ16_MEMBER(x68k_state::x68k_sysport_r)
1247	1233	{
1248		x68k_state *state = space.machine().driver_data<x68k_state>();
1249	1234	int ret = 0;
1250	1235	switch(offset)
1251	1236	{
1252	1237	case 0x00:  // monitor contrast setting (bits3-0)
1253		return state->m_sysport.contrast;
	1238	return m_sysport.contrast;
1254	1239	case 0x01:  // monitor control (bit3) / 3D Scope (bits1,0)
1255		ret |= state->m_sysport.monitor;
	1240	ret |= m_sysport.monitor;
1256	1241	return ret;
1257	1242	case 0x03:  // bit 3 = key control (is 1 if keyboard is connected)
1258	1243	return 0x08;
1259	1244	case 0x05:  // CPU type and speed
1260		return state->m_sysport.cputype;
	1245	return m_sysport.cputype;
1261	1246	default:
1262	1247	logerror("Read from invalid or unimplemented system port %04x\n",offset);
1263	1248	return 0xff;
r18260	r18261
1265	1250	}
1266	1251
1267	1252	#ifdef UNUSED_FUNCTION
1268		static READ16_HANDLER( x68k_mfp_r )
	1253	READ16_MEMBER(x68k_state::x68k_mfp_r)
1269	1254	{
1270		device_t *x68k_mfp = space.machine().device(MC68901_TAG);
	1255	device_t *x68k_mfp = machine().device(MC68901_TAG);
1271	1256
1272	1257	return mc68901_register_r(x68k_mfp, offset);
1273	1258	}
1274	1259	#endif
1275	1260
1276		static READ16_HANDLER( x68k_mfp_r )
	1261	READ16_MEMBER(x68k_state::x68k_mfp_r)
1277	1262	{
1278		x68k_state *state = space.machine().driver_data<x68k_state>();
1279	1263
1280	1264	// Initial settings indicate that IRQs are generated for FM (YM2151), Receive buffer error or full,
1281	1265	// MFP Timer C, and the power switch
r18260	r18261
1285	1269	#if 0
1286	1270	case 0x00:  // GPIP - General purpose I/O register (read-only)
1287	1271	ret = 0x23;
1288		if(machine.primary_screen->vpos() == state->m_crtc.reg[9])
	1272	if(machine.primary_screen->vpos() == m_crtc.reg[9])
1289	1273	ret |= 0x40;
1290		if(state->m_crtc.vblank == 0)
	1274	if(m_crtc.vblank == 0)
1291	1275	ret |= 0x10;  // Vsync signal (low if in vertical retrace)
1292		//      if(state->m_mfp.isrb & 0x08)
	1276	//      if(m_mfp.isrb & 0x08)
1293	1277	//          ret |= 0x08;  // FM IRQ signal
1294		if(machine.primary_screen->hpos() > state->m_crtc.width - 32)
	1278	if(machine.primary_screen->hpos() > m_crtc.width - 32)
1295	1279	ret |= 0x80;  // Hsync signal
1296	1280	//      logerror("MFP: [%08x] Reading offset %i (ret=%02x)\n",space.device().safe_pc(),offset,ret);
1297	1281	return ret;  // bit 5 is always 1
1298	1282	case 3:
1299		return state->m_mfp.iera;
	1283	return m_mfp.iera;
1300	1284	case 4:
1301		return state->m_mfp.ierb;
	1285	return m_mfp.ierb;
1302	1286	case 5:
1303		return state->m_mfp.ipra;
	1287	return m_mfp.ipra;
1304	1288	case 6:
1305		return state->m_mfp.iprb;
	1289	return m_mfp.iprb;
1306	1290	case 7:
1307		if(state->m_mfp.eoi_mode == 0)  // forced low in auto EOI mode
	1291	if(m_mfp.eoi_mode == 0)  // forced low in auto EOI mode
1308	1292	return 0;
1309	1293	else
1310		return state->m_mfp.isra;
	1294	return m_mfp.isra;
1311	1295	case 8:
1312		if(state->m_mfp.eoi_mode == 0)  // forced low in auto EOI mode
	1296	if(m_mfp.eoi_mode == 0)  // forced low in auto EOI mode
1313	1297	return 0;
1314	1298	else
1315		return state->m_mfp.isrb;
	1299	return m_mfp.isrb;
1316	1300	case 9:
1317		return state->m_mfp.imra;
	1301	return m_mfp.imra;
1318	1302	case 10:
1319		return state->m_mfp.imrb;
	1303	return m_mfp.imrb;
1320	1304	case 15:  // TADR
1321		return state->m_mfp.timer[0].counter;  // Timer data registers return their main counter values
	1305	return m_mfp.timer[0].counter;  // Timer data registers return their main counter values
1322	1306	case 16:  // TBDR
1323		return state->m_mfp.timer[1].counter;
	1307	return m_mfp.timer[1].counter;
1324	1308	case 17:  // TCDR
1325		return state->m_mfp.timer[2].counter;
	1309	return m_mfp.timer[2].counter;
1326	1310	case 18:  // TDDR
1327		return state->m_mfp.timer[3].counter;
	1311	return m_mfp.timer[3].counter;
1328	1312	#endif
1329	1313	case 21:  // RSR
1330		return state->m_mfp.rsr;
	1314	return m_mfp.rsr;
1331	1315	case 22:  // TSR
1332		return state->m_mfp.tsr | 0x80;  // buffer is typically empty?
	1316	return m_mfp.tsr | 0x80;  // buffer is typically empty?
1333	1317	case 23:
1334		return x68k_keyboard_pop_scancode(state);
	1318	return x68k_keyboard_pop_scancode();
1335	1319	default:
1336		if (ACCESSING_BITS_0_7) return state->m_mfpdev->read(space, offset);
	1320	if (ACCESSING_BITS_0_7) return m_mfpdev->read(space, offset);
1337	1321	}
1338	1322	return 0xffff;
1339	1323	}
1340	1324
1341		static WRITE16_HANDLER( x68k_mfp_w )
	1325	WRITE16_MEMBER(x68k_state::x68k_mfp_w)
1342	1326	{
1343		x68k_state *state = space.machine().driver_data<x68k_state>();
1344	1327
1345	1328	/* For the Interrupt registers, the bits are set out as such:
1346	1329	Reg A - bit 7: GPIP7 (HSync)
r18260	r18261
1367	1350	// All bits are inputs generally, so no action taken.
1368	1351	break;
1369	1352	case 1:  // AER
1370		state->m_mfp.aer = data;
	1353	m_mfp.aer = data;
1371	1354	break;
1372	1355	case 2:  // DDR
1373		state->m_mfp.ddr = data;  // usually all bits are 0 (input)
	1356	m_mfp.ddr = data;  // usually all bits are 0 (input)
1374	1357	break;
1375	1358	case 3:  // IERA
1376		state->m_mfp.iera = data;
	1359	m_mfp.iera = data;
1377	1360	break;
1378	1361	case 4:  // IERB
1379		state->m_mfp.ierb = data;
	1362	m_mfp.ierb = data;
1380	1363	break;
1381	1364	case 5:  // IPRA
1382		state->m_mfp.ipra = data;
	1365	m_mfp.ipra = data;
1383	1366	break;
1384	1367	case 6:  // IPRB
1385		state->m_mfp.iprb = data;
	1368	m_mfp.iprb = data;
1386	1369	break;
1387	1370	case 7:
1388		state->m_mfp.isra = data;
	1371	m_mfp.isra = data;
1389	1372	break;
1390	1373	case 8:
1391		state->m_mfp.isrb = data;
	1374	m_mfp.isrb = data;
1392	1375	break;
1393	1376	case 9:
1394		state->m_mfp.imra = data;
	1377	m_mfp.imra = data;
1395	1378	//      mfp_update_irq(0);
1396	1379	//      logerror("MFP: IRQ Mask A write: %02x\n",data);
1397	1380	break;
1398	1381	case 10:
1399		state->m_mfp.imrb = data;
	1382	m_mfp.imrb = data;
1400	1383	//      mfp_update_irq(0);
1401	1384	//      logerror("MFP: IRQ Mask B write: %02x\n",data);
1402	1385	break;
1403	1386	case 11:  // VR
1404		state->m_mfp.vr = 0x40;//data;  // High 4 bits = high 4 bits of IRQ vector
1405		state->m_mfp.eoi_mode = data & 0x08;  // 0 = Auto, 1 = Software End-of-interrupt
1406		if(state->m_mfp.eoi_mode == 0)  // In-service registers are cleared if this bit is cleared.
	1387	m_mfp.vr = 0x40;//data;  // High 4 bits = high 4 bits of IRQ vector
	1388	m_mfp.eoi_mode = data & 0x08;  // 0 = Auto, 1 = Software End-of-interrupt
	1389	if(m_mfp.eoi_mode == 0)  // In-service registers are cleared if this bit is cleared.
1407	1390	{
1408		state->m_mfp.isra = 0;
1409		state->m_mfp.isrb = 0;
	1391	m_mfp.isra = 0;
	1392	m_mfp.isrb = 0;
1410	1393	}
1411	1394	break;
1412	1395	case 12:  // TACR
1413		state->m_mfp.tacr = data;
	1396	m_mfp.tacr = data;
1414	1397	mfp_set_timer(0,data & 0x0f);
1415	1398	break;
1416	1399	case 13:  // TBCR
1417		state->m_mfp.tbcr = data;
	1400	m_mfp.tbcr = data;
1418	1401	mfp_set_timer(1,data & 0x0f);
1419	1402	break;
1420	1403	case 14:  // TCDCR
1421		state->m_mfp.tcdcr = data;
	1404	m_mfp.tcdcr = data;
1422	1405	mfp_set_timer(2,(data & 0x70)>>4);
1423	1406	mfp_set_timer(3,data & 0x07);
1424	1407	break;
1425	1408	case 15:  // TADR
1426		state->m_mfp.tadr = data;
1427		state->m_mfp.timer[0].counter = data;
	1409	m_mfp.tadr = data;
	1410	m_mfp.timer[0].counter = data;
1428	1411	break;
1429	1412	case 16:  // TBDR
1430		state->m_mfp.tbdr = data;
1431		state->m_mfp.timer[1].counter = data;
	1413	m_mfp.tbdr = data;
	1414	m_mfp.timer[1].counter = data;
1432	1415	break;
1433	1416	case 17:  // TCDR
1434		state->m_mfp.tcdr = data;
1435		state->m_mfp.timer[2].counter = data;
	1417	m_mfp.tcdr = data;
	1418	m_mfp.timer[2].counter = data;
1436	1419	break;
1437	1420	case 18:  // TDDR
1438		state->m_mfp.tddr = data;
1439		state->m_mfp.timer[3].counter = data;
	1421	m_mfp.tddr = data;
	1422	m_mfp.timer[3].counter = data;
1440	1423	break;
1441	1424	case 20:
1442		state->m_mfp.ucr = data;
	1425	m_mfp.ucr = data;
1443	1426	break;
1444	1427	#endif
1445	1428	case 21:
1446	1429	if(data & 0x01)
1447		state->m_mfp.usart.recv_enable = 1;
	1430	m_mfp.usart.recv_enable = 1;
1448	1431	else
1449		state->m_mfp.usart.recv_enable = 0;
	1432	m_mfp.usart.recv_enable = 0;
1450	1433	break;
1451	1434	case 22:
1452	1435	if(data & 0x01)
1453		state->m_mfp.usart.send_enable = 1;
	1436	m_mfp.usart.send_enable = 1;
1454	1437	else
1455		state->m_mfp.usart.send_enable = 0;
	1438	m_mfp.usart.send_enable = 0;
1456	1439	break;
1457	1440	case 23:
1458		if(state->m_mfp.usart.send_enable != 0)
	1441	if(m_mfp.usart.send_enable != 0)
1459	1442	{
1460	1443	// Keyboard control command.
1461		state->m_mfp.usart.send_buffer = data;
1462		x68k_keyboard_ctrl_w(state, data);
	1444	m_mfp.usart.send_buffer = data;
	1445	x68k_keyboard_ctrl_w(data);
1463	1446	//          logerror("MFP: [%08x] USART Sent data %04x\n",space.device().safe_pc(),data);
1464	1447	}
1465	1448	break;
1466	1449	default:
1467		if (ACCESSING_BITS_0_7) state->m_mfpdev->write(space, offset, data & 0xff);
	1450	if (ACCESSING_BITS_0_7) m_mfpdev->write(space, offset, data & 0xff);
1468	1451	return;
1469	1452	}
1470	1453	}
1471	1454
1472	1455
1473		static WRITE16_HANDLER( x68k_ppi_w )
	1456	WRITE16_MEMBER(x68k_state::x68k_ppi_w)
1474	1457	{
1475		i8255_device *ppi = space.machine().device<i8255_device>("ppi8255");
	1458	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
1476	1459	ppi->write(space,offset & 0x03,data);
1477	1460	}
1478	1461
1479		static READ16_HANDLER( x68k_ppi_r )
	1462	READ16_MEMBER(x68k_state::x68k_ppi_r)
1480	1463	{
1481		i8255_device *ppi = space.machine().device<i8255_device>("ppi8255");
	1464	i8255_device *ppi = machine().device<i8255_device>("ppi8255");
1482	1465	return ppi->read(space,offset & 0x03);
1483	1466	}
1484	1467
1485		static READ16_HANDLER( x68k_rtc_r )
	1468	READ16_MEMBER(x68k_state::x68k_rtc_r)
1486	1469	{
1487		x68k_state *state = space.machine().driver_data<x68k_state>();
1488
1489		return state->m_rtc->read(space, offset);
	1470	return m_rtc->read(space, offset);
1490	1471	}
1491	1472
1492		static WRITE16_HANDLER( x68k_rtc_w )
	1473	WRITE16_MEMBER(x68k_state::x68k_rtc_w)
1493	1474	{
1494		x68k_state *state = space.machine().driver_data<x68k_state>();
1495
1496		state->m_rtc->write(space, offset, data);
	1475	m_rtc->write(space, offset, data);
1497	1476	}
1498	1477
1499	1478	WRITE_LINE_MEMBER(x68k_state::x68k_rtc_alarm_irq)
r18260	r18261
1519	1498	}
1520	1499
1521	1500
1522		static WRITE16_HANDLER( x68k_sram_w )
	1501	WRITE16_MEMBER(x68k_state::x68k_sram_w)
1523	1502	{
1524		x68k_state *state = space.machine().driver_data<x68k_state>();
1525
1526		if(state->m_sysport.sram_writeprotect == 0x31)
	1503	if(m_sysport.sram_writeprotect == 0x31)
1527	1504	{
1528		COMBINE_DATA(state->m_nvram16 + offset);
	1505	COMBINE_DATA(m_nvram16 + offset);
1529	1506	}
1530	1507	}
1531	1508
1532		static READ16_HANDLER( x68k_sram_r )
	1509	READ16_MEMBER(x68k_state::x68k_sram_r)
1533	1510	{
1534		x68k_state *state = space.machine().driver_data<x68k_state>();
1535	1511	// HACKS!
1536	1512	//  if(offset == 0x5a/2)  // 0x5a should be 0 if no SASI HDs are present.
1537	1513	//      return 0x0000;
1538	1514	if(offset == 0x08/2)
1539		return space.machine().device<ram_device>(RAM_TAG)->size() >> 16;  // RAM size
	1515	return machine().device<ram_device>(RAM_TAG)->size() >> 16;  // RAM size
1540	1516	#if 0
1541	1517	if(offset == 0x46/2)
1542	1518	return 0x0024;
r18260	r18261
1545	1521	if(offset == 0x70/2)
1546	1522	return 0x0700;
1547	1523	#endif
1548		return state->m_nvram16[offset];
	1524	return m_nvram16[offset];
1549	1525	}
1550	1526
1551		static READ32_HANDLER( x68k_sram32_r )
	1527	READ32_MEMBER(x68k_state::x68k_sram32_r)
1552	1528	{
1553		x68k_state *state = space.machine().driver_data<x68k_state>();
1554	1529	if(offset == 0x08/4)
1555		return (space.machine().device<ram_device>(RAM_TAG)->size() & 0xffff0000);  // RAM size
	1530	return (machine().device<ram_device>(RAM_TAG)->size() & 0xffff0000);  // RAM size
1556	1531	#if 0
1557	1532	if(offset == 0x46/2)
1558	1533	return 0x0024;
r18260	r18261
1561	1536	if(offset == 0x70/2)
1562	1537	return 0x0700;
1563	1538	#endif
1564		return state->m_nvram32[offset];
	1539	return m_nvram32[offset];
1565	1540	}
1566	1541
1567		static WRITE32_HANDLER( x68k_sram32_w )
	1542	WRITE32_MEMBER(x68k_state::x68k_sram32_w)
1568	1543	{
1569		x68k_state *state = space.machine().driver_data<x68k_state>();
1570		if(state->m_sysport.sram_writeprotect == 0x31)
	1544	if(m_sysport.sram_writeprotect == 0x31)
1571	1545	{
1572		COMBINE_DATA(state->m_nvram32 + offset);
	1546	COMBINE_DATA(m_nvram32 + offset);
1573	1547	}
1574	1548	}
1575	1549
1576		static WRITE16_HANDLER( x68k_vid_w )
	1550	WRITE16_MEMBER(x68k_state::x68k_vid_w)
1577	1551	{
1578		x68k_state *state = space.machine().driver_data<x68k_state>();
1579	1552	int val;
1580	1553	if(offset < 0x100)  // Graphic layer palette
1581	1554	{
1582		COMBINE_DATA(state->m_video.gfx_pal+offset);
1583		val = state->m_video.gfx_pal[offset];
1584		palette_set_color_rgb(space.machine(),offset,(val & 0x07c0) >> 3,(val & 0xf800) >> 8,(val & 0x003e) << 2);
	1555	COMBINE_DATA(m_video.gfx_pal+offset);
	1556	val = m_video.gfx_pal[offset];
	1557	palette_set_color_rgb(machine(),offset,(val & 0x07c0) >> 3,(val & 0xf800) >> 8,(val & 0x003e) << 2);
1585	1558	return;
1586	1559	}
1587	1560
1588	1561	if(offset >= 0x100 && offset < 0x200)  // Text / Sprites / Tilemap palette
1589	1562	{
1590		COMBINE_DATA(state->m_video.text_pal+(offset-0x100));
1591		val = state->m_video.text_pal[offset-0x100];
1592		palette_set_color_rgb(space.machine(),offset,(val & 0x07c0) >> 3,(val & 0xf800) >> 8,(val & 0x003e) << 2);
	1563	COMBINE_DATA(m_video.text_pal+(offset-0x100));
	1564	val = m_video.text_pal[offset-0x100];
	1565	palette_set_color_rgb(machine(),offset,(val & 0x07c0) >> 3,(val & 0xf800) >> 8,(val & 0x003e) << 2);
1593	1566	return;
1594	1567	}
1595	1568
1596	1569	switch(offset)
1597	1570	{
1598	1571	case 0x200:
1599		COMBINE_DATA(state->m_video.reg);
	1572	COMBINE_DATA(m_video.reg);
1600	1573	break;
1601	1574	case 0x280:  // priority levels
1602		COMBINE_DATA(state->m_video.reg+1);
	1575	COMBINE_DATA(m_video.reg+1);
1603	1576	if(ACCESSING_BITS_0_7)
1604	1577	{
1605		state->m_video.gfxlayer_pri[0] = data & 0x0003;
1606		state->m_video.gfxlayer_pri[1] = (data & 0x000c) >> 2;
1607		state->m_video.gfxlayer_pri[2] = (data & 0x0030) >> 4;
1608		state->m_video.gfxlayer_pri[3] = (data & 0x00c0) >> 6;
	1578	m_video.gfxlayer_pri[0] = data & 0x0003;
	1579	m_video.gfxlayer_pri[1] = (data & 0x000c) >> 2;
	1580	m_video.gfxlayer_pri[2] = (data & 0x0030) >> 4;
	1581	m_video.gfxlayer_pri[3] = (data & 0x00c0) >> 6;
1609	1582	}
1610	1583	if(ACCESSING_BITS_8_15)
1611	1584	{
1612		state->m_video.gfx_pri = (data & 0x0300) >> 8;
1613		state->m_video.text_pri = (data & 0x0c00) >> 10;
1614		state->m_video.sprite_pri = (data & 0x3000) >> 12;
1615		if(state->m_video.gfx_pri == 3)
1616		state->m_video.gfx_pri--;
1617		if(state->m_video.text_pri == 3)
1618		state->m_video.text_pri--;
1619		if(state->m_video.sprite_pri == 3)
1620		state->m_video.sprite_pri--;
	1585	m_video.gfx_pri = (data & 0x0300) >> 8;
	1586	m_video.text_pri = (data & 0x0c00) >> 10;
	1587	m_video.sprite_pri = (data & 0x3000) >> 12;
	1588	if(m_video.gfx_pri == 3)
	1589	m_video.gfx_pri--;
	1590	if(m_video.text_pri == 3)
	1591	m_video.text_pri--;
	1592	if(m_video.sprite_pri == 3)
	1593	m_video.sprite_pri--;
1621	1594	}
1622	1595	break;
1623	1596	case 0x300:
1624		COMBINE_DATA(state->m_video.reg+2);
	1597	COMBINE_DATA(m_video.reg+2);
1625	1598	break;
1626	1599	default:
1627	1600	logerror("VC: Invalid video controller write (offset = 0x%04x, data = %04x)\n",offset,data);
1628	1601	}
1629	1602	}
1630	1603
1631		static READ16_HANDLER( x68k_vid_r )
	1604	READ16_MEMBER(x68k_state::x68k_vid_r)
1632	1605	{
1633		x68k_state *state = space.machine().driver_data<x68k_state>();
1634	1606	if(offset < 0x100)
1635		return state->m_video.gfx_pal[offset];
	1607	return m_video.gfx_pal[offset];
1636	1608
1637	1609	if(offset >= 0x100 && offset < 0x200)
1638		return state->m_video.text_pal[offset-0x100];
	1610	return m_video.text_pal[offset-0x100];
1639	1611
1640	1612	switch(offset)
1641	1613	{
1642	1614	case 0x200:
1643		return state->m_video.reg[0];
	1615	return m_video.reg[0];
1644	1616	case 0x280:
1645		return state->m_video.reg[1];
	1617	return m_video.reg[1];
1646	1618	case 0x300:
1647		return state->m_video.reg[2];
	1619	return m_video.reg[2];
1648	1620	default:
1649	1621	logerror("VC: Invalid video controller read (offset = 0x%04x)\n",offset);
1650	1622	}
r18260	r18261
1652	1624	return 0xff;
1653	1625	}
1654	1626
1655		static READ16_HANDLER( x68k_areaset_r )
	1627	READ16_MEMBER(x68k_state::x68k_areaset_r)
1656	1628	{
1657	1629	// register is write-only
1658	1630	return 0xffff;
1659	1631	}
1660	1632
1661		static WRITE16_HANDLER( x68k_areaset_w )
	1633	WRITE16_MEMBER(x68k_state::x68k_areaset_w)
1662	1634	{
1663	1635	// TODO
1664	1636	logerror("SYS: Supervisor area set: 0x%02x\n",data & 0xff);
1665	1637	}
1666	1638
1667		static WRITE16_HANDLER( x68k_enh_areaset_w )
	1639	WRITE16_MEMBER(x68k_state::x68k_enh_areaset_w )
1668	1640	{
1669	1641	// TODO
1670	1642	logerror("SYS: Enhanced Supervisor area set (from %iMB): 0x%02x\n",(offset + 1) * 2,data & 0xff);
r18260	r18261
1688	1660	}
1689	1661	}
1690	1662
1691		static READ16_HANDLER( x68k_rom0_r )
	1663	READ16_MEMBER(x68k_state::x68k_rom0_r)
1692	1664	{
1693		x68k_state *state = space.machine().driver_data<x68k_state>();
1694	1665	/* this location contains the address of some expansion device ROM, if no ROM exists,
1695	1666	then access causes a bus error */
1696		state->m_current_vector[2] = 0x02;  // bus error
1697		state->m_current_irq_line = 2;
1698		//  space.machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1699		if(state->ioport("options")->read() & 0x02)
	1667	m_current_vector[2] = 0x02;  // bus error
	1668	m_current_irq_line = 2;
	1669	//  machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
	1670	if(ioport("options")->read() & 0x02)
1700	1671	{
1701	1672	offset *= 2;
1702	1673	if(ACCESSING_BITS_0_7)
1703	1674	offset++;
1704		space.machine().scheduler().timer_set(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),state), 0xbffffc+offset);
	1675	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),this), 0xbffffc+offset);
1705	1676	}
1706	1677	return 0xff;
1707	1678	}
1708	1679
1709		static WRITE16_HANDLER( x68k_rom0_w )
	1680	WRITE16_MEMBER(x68k_state::x68k_rom0_w)
1710	1681	{
1711		x68k_state *state = space.machine().driver_data<x68k_state>();
1712	1682	/* this location contains the address of some expansion device ROM, if no ROM exists,
1713	1683	then access causes a bus error */
1714		state->m_current_vector[2] = 0x02;  // bus error
1715		state->m_current_irq_line = 2;
1716		//  space.machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1717		if(state->ioport("options")->read() & 0x02)
	1684	m_current_vector[2] = 0x02;  // bus error
	1685	m_current_irq_line = 2;
	1686	//  machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
	1687	if(ioport("options")->read() & 0x02)
1718	1688	{
1719	1689	offset *= 2;
1720	1690	if(ACCESSING_BITS_0_7)
1721	1691	offset++;
1722		space.machine().scheduler().timer_set(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),state), 0xbffffc+offset);
	1692	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),this), 0xbffffc+offset);
1723	1693	}
1724	1694	}
1725	1695
1726		static READ16_HANDLER( x68k_emptyram_r )
	1696	READ16_MEMBER(x68k_state::x68k_emptyram_r)
1727	1697	{
1728		x68k_state *state = space.machine().driver_data<x68k_state>();
1729	1698	/* this location is unused RAM, access here causes a bus error
1730	1699	Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
1731		state->m_current_vector[2] = 0x02;  // bus error
1732		state->m_current_irq_line = 2;
1733		//  space.machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1734		if(state->ioport("options")->read() & 0x02)
	1700	m_current_vector[2] = 0x02;  // bus error
	1701	m_current_irq_line = 2;
	1702	//  machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
	1703	if(ioport("options")->read() & 0x02)
1735	1704	{
1736	1705	offset *= 2;
1737	1706	if(ACCESSING_BITS_0_7)
1738	1707	offset++;
1739		space.machine().scheduler().timer_set(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),state), offset);
	1708	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),this), offset);
1740	1709	}
1741	1710	return 0xff;
1742	1711	}
1743	1712
1744		static WRITE16_HANDLER( x68k_emptyram_w )
	1713	WRITE16_MEMBER(x68k_state::x68k_emptyram_w)
1745	1714	{
1746		x68k_state *state = space.machine().driver_data<x68k_state>();
1747	1715	/* this location is unused RAM, access here causes a bus error
1748	1716	Often a method for detecting amount of installed RAM, is to read or write at 1MB intervals, until a bus error occurs */
1749		state->m_current_vector[2] = 0x02;  // bus error
1750		state->m_current_irq_line = 2;
1751		//  space.machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1752		if(state->ioport("options")->read() & 0x02)
	1717	m_current_vector[2] = 0x02;  // bus error
	1718	m_current_irq_line = 2;
	1719	//  machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
	1720	if(ioport("options")->read() & 0x02)
1753	1721	{
1754	1722	offset *= 2;
1755	1723	if(ACCESSING_BITS_0_7)
1756	1724	offset++;
1757		space.machine().scheduler().timer_set(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),state), offset);
	1725	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(4), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),this), offset);
1758	1726	}
1759	1727	}
1760	1728
1761		static READ16_HANDLER( x68k_exp_r )
	1729	READ16_MEMBER(x68k_state::x68k_exp_r)
1762	1730	{
1763		x68k_state *state = space.machine().driver_data<x68k_state>();
1764	1731	/* These are expansion devices, if not present, they cause a bus error */
1765		if(state->ioport("options")->read() & 0x02)
	1732	if(ioport("options")->read() & 0x02)
1766	1733	{
1767		state->m_current_vector[2] = 0x02;  // bus error
1768		state->m_current_irq_line = 2;
	1734	m_current_vector[2] = 0x02;  // bus error
	1735	m_current_irq_line = 2;
1769	1736	offset *= 2;
1770	1737	if(ACCESSING_BITS_0_7)
1771	1738	offset++;
1772		space.machine().scheduler().timer_set(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime(16), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),state), 0xeafa00+offset);
	1739	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(16), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),this), 0xeafa00+offset);
1773	1740	//      machine.device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1774	1741	}
1775	1742	return 0xffff;
1776	1743	}
1777	1744
1778		static WRITE16_HANDLER( x68k_exp_w )
	1745	WRITE16_MEMBER(x68k_state::x68k_exp_w)
1779	1746	{
1780		x68k_state *state = space.machine().driver_data<x68k_state>();
1781	1747	/* These are expansion devices, if not present, they cause a bus error */
1782		if(state->ioport("options")->read() & 0x02)
	1748	if(ioport("options")->read() & 0x02)
1783	1749	{
1784		state->m_current_vector[2] = 0x02;  // bus error
1785		state->m_current_irq_line = 2;
	1750	m_current_vector[2] = 0x02;  // bus error
	1751	m_current_irq_line = 2;
1786	1752	offset *= 2;
1787	1753	if(ACCESSING_BITS_0_7)
1788	1754	offset++;
1789		space.machine().scheduler().timer_set(space.machine().device<cpu_device>("maincpu")->cycles_to_attotime(16), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),state), 0xeafa00+offset);
	1755	machine().scheduler().timer_set(machine().device<cpu_device>("maincpu")->cycles_to_attotime(16), timer_expired_delegate(FUNC(x68k_state::x68k_bus_error),this), 0xeafa00+offset);
1790	1756	//      machine.device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,state->m_current_vector[2]);
1791	1757	}
1792	1758	}
r18260	r18261
1821	1787	}
1822	1788	}
1823	1789
1824		static void x68k_fm_irq(device_t *device, int irq)
	1790	WRITE_LINE_MEMBER(x68k_state::x68k_fm_irq)
1825	1791	{
1826		x68k_state *state = device->machine().driver_data<x68k_state>();
1827		if(irq == CLEAR_LINE)
	1792	if(state == CLEAR_LINE)
1828	1793	{
1829		state->m_mfp.gpio |= 0x08;
1830		state->m_mfpdev->i3_w(1);
	1794	m_mfp.gpio |= 0x08;
	1795	m_mfpdev->i3_w(1);
1831	1796	}
1832	1797	else
1833	1798	{
1834		state->m_mfp.gpio &= ~0x08;
1835		state->m_mfpdev->i3_w(0);
	1799	m_mfp.gpio &= ~0x08;
	1800	m_mfpdev->i3_w(0);
1836	1801	}
1837	1802	}
1838	1803
r18260	r18261
1942	1907
1943	1908	static ADDRESS_MAP_START(x68k_map, AS_PROGRAM, 16, x68k_state )
1944	1909	//  AM_RANGE(0x000000, 0xbfffff) AM_RAMBANK(1)
1945		AM_RANGE(0xbffffc, 0xbfffff) AM_READWRITE_LEGACY(x68k_rom0_r, x68k_rom0_w)
1946		//  AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE_LEGACY(x68k_gvram_r, x68k_gvram_w) AM_SHARE("gvram")
1947		//  AM_RANGE(0xe00000, 0xe7ffff) AM_READWRITE_LEGACY(x68k_tvram_r, x68k_tvram_w) AM_SHARE("tvram")
	1910	AM_RANGE(0xbffffc, 0xbfffff) AM_READWRITE(x68k_rom0_r, x68k_rom0_w)
	1911	//  AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE(x68k_gvram_r, x68k_gvram_w) AM_SHARE("gvram")
	1912	//  AM_RANGE(0xe00000, 0xe7ffff) AM_READWRITE(x68k_tvram_r, x68k_tvram_w) AM_SHARE("tvram")
1948	1913	AM_RANGE(0xc00000, 0xdfffff) AM_RAMBANK("bank2") AM_SHARE("gvram16")
1949	1914	AM_RANGE(0xe00000, 0xe7ffff) AM_RAMBANK("bank3") AM_SHARE("tvram16")
1950		AM_RANGE(0xe80000, 0xe81fff) AM_READWRITE_LEGACY(x68k_crtc_r, x68k_crtc_w)
1951		AM_RANGE(0xe82000, 0xe83fff) AM_READWRITE_LEGACY(x68k_vid_r, x68k_vid_w)
1952		AM_RANGE(0xe84000, 0xe85fff) AM_READWRITE_LEGACY(x68k_dmac_r, x68k_dmac_w)
1953		AM_RANGE(0xe86000, 0xe87fff) AM_READWRITE_LEGACY(x68k_areaset_r, x68k_areaset_w)
1954		AM_RANGE(0xe88000, 0xe89fff) AM_READWRITE_LEGACY(x68k_mfp_r, x68k_mfp_w)
1955		AM_RANGE(0xe8a000, 0xe8bfff) AM_READWRITE_LEGACY(x68k_rtc_r, x68k_rtc_w)
1956		//  AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE_LEGACY(x68k_printer_r, x68k_printer_w)
1957		AM_RANGE(0xe8e000, 0xe8ffff) AM_READWRITE_LEGACY(x68k_sysport_r, x68k_sysport_w)
1958		AM_RANGE(0xe90000, 0xe91fff) AM_READWRITE_LEGACY(x68k_fm_r, x68k_fm_w)
	1915	AM_RANGE(0xe80000, 0xe81fff) AM_READWRITE(x68k_crtc_r, x68k_crtc_w)
	1916	AM_RANGE(0xe82000, 0xe83fff) AM_READWRITE(x68k_vid_r, x68k_vid_w)
	1917	AM_RANGE(0xe84000, 0xe85fff) AM_READWRITE(x68k_dmac_r, x68k_dmac_w)
	1918	AM_RANGE(0xe86000, 0xe87fff) AM_READWRITE(x68k_areaset_r, x68k_areaset_w)
	1919	AM_RANGE(0xe88000, 0xe89fff) AM_READWRITE(x68k_mfp_r, x68k_mfp_w)
	1920	AM_RANGE(0xe8a000, 0xe8bfff) AM_READWRITE(x68k_rtc_r, x68k_rtc_w)
	1921	//  AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
	1922	AM_RANGE(0xe8e000, 0xe8ffff) AM_READWRITE(x68k_sysport_r, x68k_sysport_w)
	1923	AM_RANGE(0xe90000, 0xe91fff) AM_READWRITE(x68k_fm_r, x68k_fm_w)
1959	1924	AM_RANGE(0xe92000, 0xe92001) AM_DEVREADWRITE8_LEGACY("okim6258", okim6258_status_r, okim6258_ctrl_w, 0x00ff)
1960	1925	AM_RANGE(0xe92002, 0xe92003) AM_DEVREADWRITE8_LEGACY("okim6258", okim6258_status_r, okim6258_data_w, 0x00ff)
1961		AM_RANGE(0xe94000, 0xe95fff) AM_READWRITE_LEGACY(x68k_fdc_r, x68k_fdc_w)
	1926	AM_RANGE(0xe94000, 0xe95fff) AM_READWRITE(x68k_fdc_r, x68k_fdc_w)
1962	1927	AM_RANGE(0xe96000, 0xe9601f) AM_DEVREADWRITE("x68k_hdc", x68k_hdc_image_device, hdc_r, hdc_w)
1963		AM_RANGE(0xe98000, 0xe99fff) AM_READWRITE_LEGACY(x68k_scc_r, x68k_scc_w)
1964		AM_RANGE(0xe9a000, 0xe9bfff) AM_READWRITE_LEGACY(x68k_ppi_r, x68k_ppi_w)
1965		AM_RANGE(0xe9c000, 0xe9dfff) AM_READWRITE_LEGACY(x68k_ioc_r, x68k_ioc_w)
1966		AM_RANGE(0xea0000, 0xea1fff) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)  // external SCSI ROM and controller
1967		AM_RANGE(0xeafa00, 0xeafa1f) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)
1968		AM_RANGE(0xeafa80, 0xeafa89) AM_READWRITE_LEGACY(x68k_areaset_r, x68k_enh_areaset_w)
1969		AM_RANGE(0xeb0000, 0xeb7fff) AM_READWRITE_LEGACY(x68k_spritereg_r, x68k_spritereg_w)
1970		AM_RANGE(0xeb8000, 0xebffff) AM_READWRITE_LEGACY(x68k_spriteram_r, x68k_spriteram_w)
1971		AM_RANGE(0xece000, 0xece3ff) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)  // User I/O
1972		//  AM_RANGE(0xed0000, 0xed3fff) AM_READWRITE_LEGACY(sram_r, sram_w)
	1928	AM_RANGE(0xe98000, 0xe99fff) AM_READWRITE(x68k_scc_r, x68k_scc_w)
	1929	AM_RANGE(0xe9a000, 0xe9bfff) AM_READWRITE(x68k_ppi_r, x68k_ppi_w)
	1930	AM_RANGE(0xe9c000, 0xe9dfff) AM_READWRITE(x68k_ioc_r, x68k_ioc_w)
	1931	AM_RANGE(0xea0000, 0xea1fff) AM_READWRITE(x68k_exp_r, x68k_exp_w)  // external SCSI ROM and controller
	1932	AM_RANGE(0xeafa00, 0xeafa1f) AM_READWRITE(x68k_exp_r, x68k_exp_w)
	1933	AM_RANGE(0xeafa80, 0xeafa89) AM_READWRITE(x68k_areaset_r, x68k_enh_areaset_w)
	1934	AM_RANGE(0xeb0000, 0xeb7fff) AM_READWRITE(x68k_spritereg_r, x68k_spritereg_w)
	1935	AM_RANGE(0xeb8000, 0xebffff) AM_READWRITE(x68k_spriteram_r, x68k_spriteram_w)
	1936	AM_RANGE(0xece000, 0xece3ff) AM_READWRITE(x68k_exp_r, x68k_exp_w)  // User I/O
	1937	//  AM_RANGE(0xed0000, 0xed3fff) AM_READWRITE(sram_r, sram_w)
1973	1938	AM_RANGE(0xed0000, 0xed3fff) AM_RAMBANK("bank4") AM_SHARE("nvram16")
1974	1939	AM_RANGE(0xed4000, 0xefffff) AM_NOP
1975	1940	AM_RANGE(0xf00000, 0xfbffff) AM_ROM
1976		AM_RANGE(0xfc0000, 0xfdffff) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)  // internal SCSI ROM
	1941	AM_RANGE(0xfc0000, 0xfdffff) AM_READWRITE(x68k_exp_r, x68k_exp_w)  // internal SCSI ROM
1977	1942	AM_RANGE(0xfe0000, 0xffffff) AM_ROM
1978	1943	ADDRESS_MAP_END
1979	1944
1980	1945	static ADDRESS_MAP_START(x68kxvi_map, AS_PROGRAM, 16, x68k_state )
1981	1946	//  AM_RANGE(0x000000, 0xbfffff) AM_RAMBANK(1)
1982		AM_RANGE(0xbffffc, 0xbfffff) AM_READWRITE_LEGACY(x68k_rom0_r, x68k_rom0_w)
1983		//  AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE_LEGACY(x68k_gvram_r, x68k_gvram_w) AM_SHARE("gvram")
1984		//  AM_RANGE(0xe00000, 0xe7ffff) AM_READWRITE_LEGACY(x68k_tvram_r, x68k_tvram_w) AM_SHARE("tvram")
	1947	AM_RANGE(0xbffffc, 0xbfffff) AM_READWRITE(x68k_rom0_r, x68k_rom0_w)
	1948	//  AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE(x68k_gvram_r, x68k_gvram_w) AM_SHARE("gvram")
	1949	//  AM_RANGE(0xe00000, 0xe7ffff) AM_READWRITE(x68k_tvram_r, x68k_tvram_w) AM_SHARE("tvram")
1985	1950	AM_RANGE(0xc00000, 0xdfffff) AM_RAMBANK("bank2") AM_SHARE("gvram16")
1986	1951	AM_RANGE(0xe00000, 0xe7ffff) AM_RAMBANK("bank3") AM_SHARE("tvram16")
1987		AM_RANGE(0xe80000, 0xe81fff) AM_READWRITE_LEGACY(x68k_crtc_r, x68k_crtc_w)
1988		AM_RANGE(0xe82000, 0xe83fff) AM_READWRITE_LEGACY(x68k_vid_r, x68k_vid_w)
1989		AM_RANGE(0xe84000, 0xe85fff) AM_READWRITE_LEGACY(x68k_dmac_r, x68k_dmac_w)
1990		AM_RANGE(0xe86000, 0xe87fff) AM_READWRITE_LEGACY(x68k_areaset_r, x68k_areaset_w)
1991		AM_RANGE(0xe88000, 0xe89fff) AM_READWRITE_LEGACY(x68k_mfp_r, x68k_mfp_w)
1992		AM_RANGE(0xe8a000, 0xe8bfff) AM_READWRITE_LEGACY(x68k_rtc_r, x68k_rtc_w)
1993		//  AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE_LEGACY(x68k_printer_r, x68k_printer_w)
1994		AM_RANGE(0xe8e000, 0xe8ffff) AM_READWRITE_LEGACY(x68k_sysport_r, x68k_sysport_w)
1995		AM_RANGE(0xe90000, 0xe91fff) AM_READWRITE_LEGACY(x68k_fm_r, x68k_fm_w)
	1952	AM_RANGE(0xe80000, 0xe81fff) AM_READWRITE(x68k_crtc_r, x68k_crtc_w)
	1953	AM_RANGE(0xe82000, 0xe83fff) AM_READWRITE(x68k_vid_r, x68k_vid_w)
	1954	AM_RANGE(0xe84000, 0xe85fff) AM_READWRITE(x68k_dmac_r, x68k_dmac_w)
	1955	AM_RANGE(0xe86000, 0xe87fff) AM_READWRITE(x68k_areaset_r, x68k_areaset_w)
	1956	AM_RANGE(0xe88000, 0xe89fff) AM_READWRITE(x68k_mfp_r, x68k_mfp_w)
	1957	AM_RANGE(0xe8a000, 0xe8bfff) AM_READWRITE(x68k_rtc_r, x68k_rtc_w)
	1958	//  AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
	1959	AM_RANGE(0xe8e000, 0xe8ffff) AM_READWRITE(x68k_sysport_r, x68k_sysport_w)
	1960	AM_RANGE(0xe90000, 0xe91fff) AM_READWRITE(x68k_fm_r, x68k_fm_w)
1996	1961	AM_RANGE(0xe92000, 0xe92001) AM_DEVREADWRITE8_LEGACY("okim6258", okim6258_status_r, okim6258_ctrl_w, 0x00ff)
1997	1962	AM_RANGE(0xe92002, 0xe92003) AM_DEVREADWRITE8_LEGACY("okim6258", okim6258_status_r, okim6258_data_w, 0x00ff)
1998		AM_RANGE(0xe94000, 0xe95fff) AM_READWRITE_LEGACY(x68k_fdc_r, x68k_fdc_w)
	1963	AM_RANGE(0xe94000, 0xe95fff) AM_READWRITE(x68k_fdc_r, x68k_fdc_w)
1999	1964	//  AM_RANGE(0xe96000, 0xe9601f) AM_DEVREADWRITE_LEGACY("x68k_hdc",x68k_hdc_r, x68k_hdc_w)
2000	1965	AM_RANGE(0xe96020, 0xe9603f) AM_DEVREADWRITE8("scsi:mb89352",mb89352_device,mb89352_r,mb89352_w,0x00ff)
2001		AM_RANGE(0xe98000, 0xe99fff) AM_READWRITE_LEGACY(x68k_scc_r, x68k_scc_w)
2002		AM_RANGE(0xe9a000, 0xe9bfff) AM_READWRITE_LEGACY(x68k_ppi_r, x68k_ppi_w)
2003		AM_RANGE(0xe9c000, 0xe9dfff) AM_READWRITE_LEGACY(x68k_ioc_r, x68k_ioc_w)
2004		AM_RANGE(0xea0000, 0xea1fff) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)  // external SCSI ROM and controller
2005		AM_RANGE(0xeafa00, 0xeafa1f) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)
2006		AM_RANGE(0xeafa80, 0xeafa89) AM_READWRITE_LEGACY(x68k_areaset_r, x68k_enh_areaset_w)
2007		AM_RANGE(0xeb0000, 0xeb7fff) AM_READWRITE_LEGACY(x68k_spritereg_r, x68k_spritereg_w)
2008		AM_RANGE(0xeb8000, 0xebffff) AM_READWRITE_LEGACY(x68k_spriteram_r, x68k_spriteram_w)
2009		AM_RANGE(0xece000, 0xece3ff) AM_READWRITE_LEGACY(x68k_exp_r, x68k_exp_w)  // User I/O
2010		//  AM_RANGE(0xed0000, 0xed3fff) AM_READWRITE_LEGACY(sram_r, sram_w)
	1966	AM_RANGE(0xe98000, 0xe99fff) AM_READWRITE(x68k_scc_r, x68k_scc_w)
	1967	AM_RANGE(0xe9a000, 0xe9bfff) AM_READWRITE(x68k_ppi_r, x68k_ppi_w)
	1968	AM_RANGE(0xe9c000, 0xe9dfff) AM_READWRITE(x68k_ioc_r, x68k_ioc_w)
	1969	AM_RANGE(0xea0000, 0xea1fff) AM_READWRITE(x68k_exp_r, x68k_exp_w)  // external SCSI ROM and controller
	1970	AM_RANGE(0xeafa00, 0xeafa1f) AM_READWRITE(x68k_exp_r, x68k_exp_w)
	1971	AM_RANGE(0xeafa80, 0xeafa89) AM_READWRITE(x68k_areaset_r, x68k_enh_areaset_w)
	1972	AM_RANGE(0xeb0000, 0xeb7fff) AM_READWRITE(x68k_spritereg_r, x68k_spritereg_w)
	1973	AM_RANGE(0xeb8000, 0xebffff) AM_READWRITE(x68k_spriteram_r, x68k_spriteram_w)
	1974	AM_RANGE(0xece000, 0xece3ff) AM_READWRITE(x68k_exp_r, x68k_exp_w)  // User I/O
	1975	//  AM_RANGE(0xed0000, 0xed3fff) AM_READWRITE(sram_r, sram_w)
2011	1976	AM_RANGE(0xed0000, 0xed3fff) AM_RAMBANK("bank4") AM_SHARE("nvram16")
2012	1977	AM_RANGE(0xed4000, 0xefffff) AM_NOP
2013	1978	AM_RANGE(0xf00000, 0xfbffff) AM_ROM
r18260	r18261
2018	1983	static ADDRESS_MAP_START(x68030_map, AS_PROGRAM, 32, x68k_state )
2019	1984	ADDRESS_MAP_GLOBAL_MASK(0x00ffffff)  // Still only has 24-bit address space
2020	1985	//  AM_RANGE(0x000000, 0xbfffff) AM_RAMBANK(1)
2021		AM_RANGE(0xbffffc, 0xbfffff) AM_READWRITE16_LEGACY(x68k_rom0_r, x68k_rom0_w,0xffffffff)
2022		//  AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE_LEGACY(x68k_gvram_r, x68k_gvram_w) AM_SHARE("gvram")
2023		//  AM_RANGE(0xe00000, 0xe7ffff) AM_READWRITE_LEGACY(x68k_tvram_r, x68k_tvram_w) AM_SHARE("tvram")
	1986	AM_RANGE(0xbffffc, 0xbfffff) AM_READWRITE16(x68k_rom0_r, x68k_rom0_w,0xffffffff)
	1987	//  AM_RANGE(0xc00000, 0xdfffff) AM_READWRITE(x68k_gvram_r, x68k_gvram_w) AM_SHARE("gvram")
	1988	//  AM_RANGE(0xe00000, 0xe7ffff) AM_READWRITE(x68k_tvram_r, x68k_tvram_w) AM_SHARE("tvram")
2024	1989	AM_RANGE(0xc00000, 0xdfffff) AM_RAMBANK("bank2") AM_SHARE("gvram32")
2025	1990	AM_RANGE(0xe00000, 0xe7ffff) AM_RAMBANK("bank3") AM_SHARE("tvram32")
2026		AM_RANGE(0xe80000, 0xe81fff) AM_READWRITE16_LEGACY(x68k_crtc_r, x68k_crtc_w,0xffffffff)
2027		AM_RANGE(0xe82000, 0xe83fff) AM_READWRITE16_LEGACY(x68k_vid_r, x68k_vid_w,0xffffffff)
2028		AM_RANGE(0xe84000, 0xe85fff) AM_READWRITE16_LEGACY(x68k_dmac_r, x68k_dmac_w,0xffffffff)
2029		AM_RANGE(0xe86000, 0xe87fff) AM_READWRITE16_LEGACY(x68k_areaset_r, x68k_areaset_w,0xffffffff)
2030		AM_RANGE(0xe88000, 0xe89fff) AM_READWRITE16_LEGACY(x68k_mfp_r, x68k_mfp_w,0xffffffff)
2031		AM_RANGE(0xe8a000, 0xe8bfff) AM_READWRITE16_LEGACY(x68k_rtc_r, x68k_rtc_w,0xffffffff)
2032		//  AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE_LEGACY(x68k_printer_r, x68k_printer_w)
2033		AM_RANGE(0xe8e000, 0xe8ffff) AM_READWRITE16_LEGACY(x68k_sysport_r, x68k_sysport_w,0xffffffff)
2034		AM_RANGE(0xe90000, 0xe91fff) AM_READWRITE16_LEGACY(x68k_fm_r, x68k_fm_w,0xffffffff)
	1991	AM_RANGE(0xe80000, 0xe81fff) AM_READWRITE16(x68k_crtc_r, x68k_crtc_w,0xffffffff)
	1992	AM_RANGE(0xe82000, 0xe83fff) AM_READWRITE16(x68k_vid_r, x68k_vid_w,0xffffffff)
	1993	AM_RANGE(0xe84000, 0xe85fff) AM_READWRITE16(x68k_dmac_r, x68k_dmac_w,0xffffffff)
	1994	AM_RANGE(0xe86000, 0xe87fff) AM_READWRITE16(x68k_areaset_r, x68k_areaset_w,0xffffffff)
	1995	AM_RANGE(0xe88000, 0xe89fff) AM_READWRITE16(x68k_mfp_r, x68k_mfp_w,0xffffffff)
	1996	AM_RANGE(0xe8a000, 0xe8bfff) AM_READWRITE16(x68k_rtc_r, x68k_rtc_w,0xffffffff)
	1997	//  AM_RANGE(0xe8c000, 0xe8dfff) AM_READWRITE(x68k_printer_r, x68k_printer_w)
	1998	AM_RANGE(0xe8e000, 0xe8ffff) AM_READWRITE16(x68k_sysport_r, x68k_sysport_w,0xffffffff)
	1999	AM_RANGE(0xe90000, 0xe91fff) AM_READWRITE16(x68k_fm_r, x68k_fm_w,0xffffffff)
2035	2000	AM_RANGE(0xe92000, 0xe92003) AM_DEVREAD8_LEGACY("okim6258", okim6258_status_r, 0x00ff00ff) AM_WRITE8(x68030_adpcm_w, 0x00ff00ff)
2036		AM_RANGE(0xe94000, 0xe95fff) AM_READWRITE16_LEGACY(x68k_fdc_r, x68k_fdc_w,0xffffffff)
	2001	AM_RANGE(0xe94000, 0xe95fff) AM_READWRITE16(x68k_fdc_r, x68k_fdc_w,0xffffffff)
2037	2002	//  AM_RANGE(0xe96000, 0xe9601f) AM_DEVREADWRITE16_LEGACY("x68k_hdc",x68k_hdc_r, x68k_hdc_w,0xffffffff)
2038	2003	AM_RANGE(0xe96020, 0xe9603f) AM_DEVREADWRITE8("scsi:mb89352",mb89352_device,mb89352_r,mb89352_w,0x00ff00ff)
2039		AM_RANGE(0xe98000, 0xe99fff) AM_READWRITE16_LEGACY(x68k_scc_r, x68k_scc_w,0xffffffff)
2040		AM_RANGE(0xe9a000, 0xe9bfff) AM_READWRITE16_LEGACY(x68k_ppi_r, x68k_ppi_w,0xffffffff)
2041		AM_RANGE(0xe9c000, 0xe9dfff) AM_READWRITE16_LEGACY(x68k_ioc_r, x68k_ioc_w,0xffffffff)
	2004	AM_RANGE(0xe98000, 0xe99fff) AM_READWRITE16(x68k_scc_r, x68k_scc_w,0xffffffff)
	2005	AM_RANGE(0xe9a000, 0xe9bfff) AM_READWRITE16(x68k_ppi_r, x68k_ppi_w,0xffffffff)
	2006	AM_RANGE(0xe9c000, 0xe9dfff) AM_READWRITE16(x68k_ioc_r, x68k_ioc_w,0xffffffff)
2042	2007	AM_RANGE(0xea0000, 0xea1fff) AM_NOP//AM_READWRITE16_LEGACY(x68k_exp_r, x68k_exp_w,0xffffffff)  // external SCSI ROM and controller
2043		AM_RANGE(0xeafa00, 0xeafa1f) AM_READWRITE16_LEGACY(x68k_exp_r, x68k_exp_w,0xffffffff)
2044		AM_RANGE(0xeafa80, 0xeafa8b) AM_READWRITE16_LEGACY(x68k_areaset_r, x68k_enh_areaset_w,0xffffffff)
2045		AM_RANGE(0xeb0000, 0xeb7fff) AM_READWRITE16_LEGACY(x68k_spritereg_r, x68k_spritereg_w,0xffffffff)
2046		AM_RANGE(0xeb8000, 0xebffff) AM_READWRITE16_LEGACY(x68k_spriteram_r, x68k_spriteram_w,0xffffffff)
2047		AM_RANGE(0xece000, 0xece3ff) AM_READWRITE16_LEGACY(x68k_exp_r, x68k_exp_w,0xffffffff)  // User I/O
2048		//  AM_RANGE(0xed0000, 0xed3fff) AM_READWRITE_LEGACY(sram_r, sram_w)
	2008	AM_RANGE(0xeafa00, 0xeafa1f) AM_READWRITE16(x68k_exp_r, x68k_exp_w,0xffffffff)
	2009	AM_RANGE(0xeafa80, 0xeafa8b) AM_READWRITE16(x68k_areaset_r, x68k_enh_areaset_w,0xffffffff)
	2010	AM_RANGE(0xeb0000, 0xeb7fff) AM_READWRITE16(x68k_spritereg_r, x68k_spritereg_w,0xffffffff)
	2011	AM_RANGE(0xeb8000, 0xebffff) AM_READWRITE16(x68k_spriteram_r, x68k_spriteram_w,0xffffffff)
	2012	AM_RANGE(0xece000, 0xece3ff) AM_READWRITE16(x68k_exp_r, x68k_exp_w,0xffffffff)  // User I/O
	2013	//  AM_RANGE(0xed0000, 0xed3fff) AM_READWRITE(sram_r, sram_w)
2049	2014	AM_RANGE(0xed0000, 0xed3fff) AM_RAMBANK("bank4") AM_SHARE("nvram32")
2050	2015	AM_RANGE(0xed4000, 0xefffff) AM_NOP
2051	2016	AM_RANGE(0xf00000, 0xfbffff) AM_ROM
r18260	r18261
2111	2076
2112	2077	static const ym2151_interface x68k_ym2151_interface =
2113	2078	{
2114		DEVCB_LINE(x68k_fm_irq),
	2079	DEVCB_DRIVER_LINE_MEMBER(x68k_state,x68k_fm_irq),
2115	2080	DEVCB_DRIVER_MEMBER(x68k_state,x68k_ct_w)  // CT1, CT2 from YM2151 port 0x1b
2116	2081	};
2117	2082
r18260	r18261
2470	2435	machine().device("maincpu")->execute().set_input_line_and_vector(2,ASSERT_LINE,m_current_vector[2]);
2471	2436	}
2472	2437
2473		static void x68k_irq2_line(device_t* device,int state)
	2438	WRITE_LINE_MEMBER(x68k_state::x68k_irq2_line)
2474	2439	{
2475		x68k_state *tstate = device->machine().driver_data<x68k_state>();
2476	2440	if(state==ASSERT_LINE)
2477	2441	{
2478		tstate->m_net_timer->adjust(attotime::from_usec(16));
	2442	m_net_timer->adjust(attotime::from_usec(16));
2479	2443	}
2480	2444	else
2481		device->machine().device("maincpu")->execute().set_input_line_and_vector(2,CLEAR_LINE,tstate->m_current_vector[2]);
	2445	machine().device("maincpu")->execute().set_input_line_and_vector(2,CLEAR_LINE,m_current_vector[2]);
2482	2446	logerror("EXP: IRQ2 set to %i\n",state);
2483	2447
2484	2448	}
r18260	r18261
2515	2479
2516	2480	static X68K_EXPANSION_INTERFACE(x68k_exp_intf)
2517	2481	{
2518		DEVCB_LINE(x68k_irq2_line),
	2482	DEVCB_DRIVER_LINE_MEMBER(x68k_state,x68k_irq2_line),
2519	2483	DEVCB_CPU_INPUT_LINE("maincpu", M68K_IRQ_4),
2520	2484	DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_NMI),
2521	2485	DEVCB_NULL  // RESET
r18260	r18261
2564	2528	m_crtc.reg[7] = 552;  // Vertical end
2565	2529	m_crtc.reg[8] = 27;   // Horizontal adjust
2566	2530
2567		mfp_init(machine());
	2531	mfp_init();
2568	2532
2569	2533	m_scanline = machine().primary_screen->vpos();// = m_crtc.reg[6];  // Vertical start
2570	2534
r18260	r18261
2604	2568	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
2605	2569	/*  Install RAM handlers  */
2606	2570	m_spriteram = (UINT16*)(*memregion("user1"));
2607		space.install_legacy_read_handler(0x000000,0xbffffb,0xffffffff,0,FUNC(x68k_emptyram_r));
2608		space.install_legacy_write_handler(0x000000,0xbffffb,0xffffffff,0,FUNC(x68k_emptyram_w));
	2571	space.install_read_handler(0x000000,0xbffffb,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_emptyram_r),this));
	2572	space.install_write_handler(0x000000,0xbffffb,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_emptyram_w),this));
2609	2573	space.install_readwrite_bank(0x000000,machine().device<ram_device>(RAM_TAG)->size()-1,0xffffffff,0,"bank1");
2610	2574	membank("bank1")->set_base(machine().device<ram_device>(RAM_TAG)->pointer());
2611		space.install_legacy_read_handler(0xc00000,0xdfffff,0xffffffff,0,FUNC(x68k_gvram_r));
2612		space.install_legacy_write_handler(0xc00000,0xdfffff,0xffffffff,0,FUNC(x68k_gvram_w));
	2575	space.install_read_handler(0xc00000,0xdfffff,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_gvram_r),this));
	2576	space.install_write_handler(0xc00000,0xdfffff,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_gvram_w),this));
2613	2577	membank("bank2")->set_base(m_gvram16);  // so that code in VRAM is executable - needed for Terra Cresta
2614		space.install_legacy_read_handler(0xe00000,0xe7ffff,0xffffffff,0,FUNC(x68k_tvram_r));
2615		space.install_legacy_write_handler(0xe00000,0xe7ffff,0xffffffff,0,FUNC(x68k_tvram_w));
	2578	space.install_read_handler(0xe00000,0xe7ffff,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_tvram_r),this));
	2579	space.install_write_handler(0xe00000,0xe7ffff,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_tvram_w),this));
2616	2580	membank("bank3")->set_base(m_tvram16);  // so that code in VRAM is executable - needed for Terra Cresta
2617		space.install_legacy_read_handler(0xed0000,0xed3fff,0xffffffff,0,FUNC(x68k_sram_r));
2618		space.install_legacy_write_handler(0xed0000,0xed3fff,0xffffffff,0,FUNC(x68k_sram_w));
	2581	space.install_read_handler(0xed0000,0xed3fff,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_sram_r),this));
	2582	space.install_write_handler(0xed0000,0xed3fff,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_sram_w),this));
2619	2583	membank("bank4")->set_base(m_nvram16);  // so that code in SRAM is executable, there is an option for booting from SRAM
2620	2584
2621	2585	// start keyboard timer
r18260	r18261
2634	2598	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
2635	2599	/*  Install RAM handlers  */
2636	2600	m_spriteram = (UINT16*)(*memregion("user1"));
2637		space.install_legacy_read_handler(0x000000,0xbffffb,0xffffffff,0,FUNC(x68k_rom0_r),0xffffffff);
2638		space.install_legacy_write_handler(0x000000,0xbffffb,0xffffffff,0,FUNC(x68k_rom0_w),0xffffffff);
	2601	space.install_read_handler(0x000000,0xbffffb,0xffffffff,0,read16_delegate(FUNC(x68k_state::x68k_rom0_r),this),0xffffffff);
	2602	space.install_write_handler(0x000000,0xbffffb,0xffffffff,0,write16_delegate(FUNC(x68k_state::x68k_rom0_w),this),0xffffffff);
2639	2603	space.install_readwrite_bank(0x000000,machine().device<ram_device>(RAM_TAG)->size()-1,0xffffffff,0,"bank1");
2640	2604	membank("bank1")->set_base(machine().device<ram_device>(RAM_TAG)->pointer());
2641		space.install_legacy_read_handler(0xc00000,0xdfffff,0xffffffff,0,FUNC(x68k_gvram32_r));
2642		space.install_legacy_write_handler(0xc00000,0xdfffff,0xffffffff,0,FUNC(x68k_gvram32_w));
	2605	space.install_read_handler(0xc00000,0xdfffff,0xffffffff,0,read32_delegate(FUNC(x68k_state::x68k_gvram32_r),this));
	2606	space.install_write_handler(0xc00000,0xdfffff,0xffffffff,0,write32_delegate(FUNC(x68k_state::x68k_gvram32_w),this));
2643	2607	membank("bank2")->set_base(m_gvram32);  // so that code in VRAM is executable - needed for Terra Cresta
2644		space.install_legacy_read_handler(0xe00000,0xe7ffff,0xffffffff,0,FUNC(x68k_tvram32_r));
2645		space.install_legacy_write_handler(0xe00000,0xe7ffff,0xffffffff,0,FUNC(x68k_tvram32_w));
	2608	space.install_read_handler(0xe00000,0xe7ffff,0xffffffff,0,read32_delegate(FUNC(x68k_state::x68k_tvram32_r),this));
	2609	space.install_write_handler(0xe00000,0xe7ffff,0xffffffff,0,write32_delegate(FUNC(x68k_state::x68k_tvram32_w),this));
2646	2610	membank("bank3")->set_base(m_tvram32);  // so that code in VRAM is executable - needed for Terra Cresta
2647		space.install_legacy_read_handler(0xed0000,0xed3fff,0xffffffff,0,FUNC(x68k_sram32_r));
2648		space.install_legacy_write_handler(0xed0000,0xed3fff,0xffffffff,0,FUNC(x68k_sram32_w));
	2611	space.install_read_handler(0xed0000,0xed3fff,0xffffffff,0,read32_delegate(FUNC(x68k_state::x68k_sram32_r),this));
	2612	space.install_write_handler(0xed0000,0xed3fff,0xffffffff,0,write32_delegate(FUNC(x68k_state::x68k_sram32_w),this));
2649	2613	membank("bank4")->set_base(m_nvram32);  // so that code in SRAM is executable, there is an option for booting from SRAM
2650	2614
2651	2615	// start keyboard timer
r18260	r18261
2680	2644	// copy last half of BIOS to a user region, to use for inital startup
2681	2645	memcpy(user2,(rom+0xff0000),0x10000);
2682	2646
2683		mfp_init(machine());
	2647	mfp_init();
2684	2648
2685	2649	machine().device("maincpu")->execute().set_irq_acknowledge_callback(x68k_int_ack);
2686	2650
r18260	r18261
2696	2660	m_net_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(x68k_state::x68k_net_irq),this));
2697	2661
2698	2662	// Initialise timers for 6-button MD controllers
2699		md_6button_init(machine());
	2663	md_6button_init();
2700	2664
2701	2665	m_sysport.cputype = 0xff;  // 68000, 10MHz
2702	2666	m_is_32bit = false;

trunk/src/mess/includes/x68k.h

r18260	r18261
297	297	DECLARE_WRITE_LINE_MEMBER(mfp_irq_callback);
298	298	DECLARE_WRITE_LINE_MEMBER(x68k_scsi_irq);
299	299	DECLARE_WRITE_LINE_MEMBER(x68k_scsi_drq);
	300
	301	void mfp_init();
	302	void x68k_keyboard_ctrl_w(int data);
	303	int x68k_keyboard_pop_scancode();
	304	void x68k_keyboard_push_scancode(unsigned char code);
	305	int x68k_read_mouse();
	306	void x68k_set_adpcm();
	307	UINT8 md_3button_r(int port);
	308	void md_6button_init();
	309	UINT8 md_6button_r(int port);
	310	UINT8 xpd1lr_r(int port);
	311
	312	DECLARE_WRITE_LINE_MEMBER(x68k_fm_irq);
	313	DECLARE_WRITE_LINE_MEMBER(x68k_irq2_line);
	314
	315	DECLARE_WRITE16_MEMBER(x68k_dmac_w);
	316	DECLARE_READ16_MEMBER(x68k_dmac_r);
	317	DECLARE_WRITE16_MEMBER(x68k_scc_w);
	318	DECLARE_WRITE16_MEMBER(x68k_fdc_w);
	319	DECLARE_READ16_MEMBER(x68k_fdc_r);
	320	DECLARE_WRITE16_MEMBER(x68k_fm_w);
	321	DECLARE_READ16_MEMBER(x68k_fm_r);
	322	DECLARE_WRITE16_MEMBER(x68k_ioc_w);
	323	DECLARE_READ16_MEMBER(x68k_ioc_r);
	324	DECLARE_WRITE16_MEMBER(x68k_sysport_w);
	325	DECLARE_READ16_MEMBER(x68k_sysport_r);
	326	DECLARE_READ16_MEMBER(x68k_mfp_r);
	327	DECLARE_WRITE16_MEMBER(x68k_mfp_w);
	328	DECLARE_WRITE16_MEMBER(x68k_ppi_w);
	329	DECLARE_READ16_MEMBER(x68k_ppi_r);
	330	DECLARE_READ16_MEMBER(x68k_rtc_r);
	331	DECLARE_WRITE16_MEMBER(x68k_rtc_w);
	332	DECLARE_WRITE16_MEMBER(x68k_sram_w);
	333	DECLARE_READ16_MEMBER(x68k_sram_r);
	334	DECLARE_READ32_MEMBER(x68k_sram32_r);
	335	DECLARE_WRITE32_MEMBER(x68k_sram32_w);
	336	DECLARE_WRITE16_MEMBER(x68k_vid_w);
	337	DECLARE_READ16_MEMBER(x68k_vid_r);
	338	DECLARE_READ16_MEMBER(x68k_areaset_r);
	339	DECLARE_WRITE16_MEMBER(x68k_areaset_w);
	340	DECLARE_WRITE16_MEMBER(x68k_enh_areaset_w);
	341	DECLARE_READ16_MEMBER(x68k_rom0_r);
	342	DECLARE_WRITE16_MEMBER(x68k_rom0_w);
	343	DECLARE_READ16_MEMBER(x68k_emptyram_r);
	344	DECLARE_WRITE16_MEMBER(x68k_emptyram_w);
	345	DECLARE_READ16_MEMBER(x68k_exp_r);
	346	DECLARE_WRITE16_MEMBER(x68k_exp_w);
	347	DECLARE_READ16_MEMBER(x68k_scc_r);
	348
	349	DECLARE_READ16_MEMBER(x68k_spritereg_r);
	350	DECLARE_WRITE16_MEMBER(x68k_spritereg_w);
	351	DECLARE_READ16_MEMBER(x68k_spriteram_r);
	352	DECLARE_WRITE16_MEMBER(x68k_spriteram_w);
	353	DECLARE_WRITE16_MEMBER(x68k_crtc_w);
	354	DECLARE_READ16_MEMBER(x68k_crtc_r);
	355	DECLARE_WRITE16_MEMBER(x68k_gvram_w);
	356	DECLARE_READ16_MEMBER(x68k_gvram_r);
	357	DECLARE_WRITE16_MEMBER(x68k_tvram_w);
	358	DECLARE_READ16_MEMBER(x68k_tvram_r);
	359	DECLARE_WRITE32_MEMBER(x68k_gvram32_w);
	360	DECLARE_READ32_MEMBER(x68k_gvram32_r);
	361	DECLARE_WRITE32_MEMBER(x68k_tvram32_w);
	362	DECLARE_READ32_MEMBER(x68k_tvram32_r);
	363	private:
	364	inline void x68k_plot_pixel(bitmap_ind16 &bitmap, int x, int y, UINT32 color);
	365	void x68k_crtc_text_copy(int src, int dest);
	366	void x68k_crtc_refresh_mode();
	367	void x68k_draw_text(bitmap_ind16 &bitmap, int xscr, int yscr, rectangle rect);
	368	void x68k_draw_gfx_scanline(bitmap_ind16 &bitmap, rectangle cliprect, UINT8 priority);
	369	void x68k_draw_gfx(bitmap_ind16 &bitmap,rectangle cliprect);
	370	void x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect);
300	371	};
301	372
302	373
303		/*----------- defined in drivers/x68k.c -----------*/
304	374
305		#ifdef UNUSED_FUNCTION
306		void mfp_trigger_irq(int);
307		TIMER_CALLBACK(mfp_timer_a_callback);
308		TIMER_CALLBACK(mfp_timer_b_callback);
309		TIMER_CALLBACK(mfp_timer_c_callback);
310		TIMER_CALLBACK(mfp_timer_d_callback);
311		#endif
312
313		/*----------- defined in video/x68k.c -----------*/
314		DECLARE_READ16_HANDLER( x68k_spritereg_r );
315		DECLARE_WRITE16_HANDLER( x68k_spritereg_w );
316		DECLARE_READ16_HANDLER( x68k_spriteram_r );
317		DECLARE_WRITE16_HANDLER( x68k_spriteram_w );
318		DECLARE_WRITE16_HANDLER( x68k_crtc_w );
319		DECLARE_READ16_HANDLER( x68k_crtc_r );
320		DECLARE_WRITE16_HANDLER( x68k_gvram_w );
321		DECLARE_READ16_HANDLER( x68k_gvram_r );
322		DECLARE_WRITE16_HANDLER( x68k_tvram_w );
323		DECLARE_READ16_HANDLER( x68k_tvram_r );
324		DECLARE_WRITE32_HANDLER( x68k_gvram32_w );
325		DECLARE_READ32_HANDLER( x68k_gvram32_r );
326		DECLARE_WRITE32_HANDLER( x68k_tvram32_w );
327		DECLARE_READ32_HANDLER( x68k_tvram32_r );
328
329
330	375	#endif /* X68K_H_ */

trunk/src/mess/video/x68k.c

r18260	r18261
33	33
34	34
35	35
36		static void x68k_crtc_refresh_mode(running_machine &machine);
37
38		INLINE void x68k_plot_pixel(bitmap_ind16 &bitmap, int x, int y, UINT32 color)
	36	inline void x68k_state::x68k_plot_pixel(bitmap_ind16 &bitmap, int x, int y, UINT32 color)
39	37	{
40	38	bitmap.pix16(y, x) = (UINT16)color;
41	39	}
r18260	r18261
78	76	return NULL;  // should never reach here either.
79	77	}
80	78	*/
81		static void x68k_crtc_text_copy(x68k_state *state, int src, int dest)
	79	void x68k_state::x68k_crtc_text_copy(int src, int dest)
82	80	{
83	81	// copys one raster in T-VRAM to another raster
84	82	UINT16* tvram;
r18260	r18261
86	84	int dest_ram = dest * 256;
87	85	int line;
88	86
89		if(state->m_is_32bit)
90		tvram = (UINT16*)state->m_tvram32.target();
	87	if(m_is_32bit)
	88	tvram = (UINT16*)m_tvram32.target();
91	89	else
92		tvram = (UINT16*)state->m_tvram16.target();
	90	tvram = (UINT16*)m_tvram16.target();
93	91
94	92	if(dest > 250)
95	93	return;  // for some reason, Salamander causes a SIGSEGV in a debug build in this function.
r18260	r18261
114	112	m_crtc.operation &= ~bit;
115	113	}
116	114
117		static void x68k_crtc_refresh_mode(running_machine &machine)
	115	void x68k_state::x68k_crtc_refresh_mode()
118	116	{
119		x68k_state *state = machine.driver_data<x68k_state>();
120	117	//  rectangle rect;
121	118	//  double scantime;
122	119	rectangle scr,visiblescr;
123	120	int length;
124	121
125	122	// Calculate data from register values
126		state->m_crtc.vmultiple = 1;
127		if((state->m_crtc.reg[20] & 0x10) != 0 && (state->m_crtc.reg[20] & 0x0c) == 0)
128		state->m_crtc.vmultiple = 2;  // 31.5kHz + 256 lines = doublescan
129		if(state->m_crtc.interlace != 0)
130		state->m_crtc.vmultiple = 0.5f;  // 31.5kHz + 1024 lines or 15kHz + 512 lines = interlaced
131		state->m_crtc.htotal = (state->m_crtc.reg[0] + 1) * 8;
132		state->m_crtc.vtotal = (state->m_crtc.reg[4] + 1) / state->m_crtc.vmultiple; // default is 567 (568 scanlines)
133		state->m_crtc.hbegin = (state->m_crtc.reg[2] * 8) + 1;
134		state->m_crtc.hend = (state->m_crtc.reg[3] * 8);
135		state->m_crtc.vbegin = (state->m_crtc.reg[6]) / state->m_crtc.vmultiple;
136		state->m_crtc.vend = (state->m_crtc.reg[7] - 1) / state->m_crtc.vmultiple;
137		state->m_crtc.hsync_end = (state->m_crtc.reg[1]) * 8;
138		state->m_crtc.vsync_end = (state->m_crtc.reg[5]) / state->m_crtc.vmultiple;
139		state->m_crtc.hsyncadjust = state->m_crtc.reg[8];
140		scr.set(0, state->m_crtc.htotal - 8, 0, state->m_crtc.vtotal);
141		if(scr.max_y <= state->m_crtc.vend)
142		scr.max_y = state->m_crtc.vend + 2;
143		if(scr.max_x <= state->m_crtc.hend)
144		scr.max_x = state->m_crtc.hend + 2;
145		visiblescr.set(state->m_crtc.hbegin, state->m_crtc.hend, state->m_crtc.vbegin, state->m_crtc.vend);
	123	m_crtc.vmultiple = 1;
	124	if((m_crtc.reg[20] & 0x10) != 0 && (m_crtc.reg[20] & 0x0c) == 0)
	125	m_crtc.vmultiple = 2;  // 31.5kHz + 256 lines = doublescan
	126	if(m_crtc.interlace != 0)
	127	m_crtc.vmultiple = 0.5f;  // 31.5kHz + 1024 lines or 15kHz + 512 lines = interlaced
	128	m_crtc.htotal = (m_crtc.reg[0] + 1) * 8;
	129	m_crtc.vtotal = (m_crtc.reg[4] + 1) / m_crtc.vmultiple; // default is 567 (568 scanlines)
	130	m_crtc.hbegin = (m_crtc.reg[2] * 8) + 1;
	131	m_crtc.hend = (m_crtc.reg[3] * 8);
	132	m_crtc.vbegin = (m_crtc.reg[6]) / m_crtc.vmultiple;
	133	m_crtc.vend = (m_crtc.reg[7] - 1) / m_crtc.vmultiple;
	134	m_crtc.hsync_end = (m_crtc.reg[1]) * 8;
	135	m_crtc.vsync_end = (m_crtc.reg[5]) / m_crtc.vmultiple;
	136	m_crtc.hsyncadjust = m_crtc.reg[8];
	137	scr.set(0, m_crtc.htotal - 8, 0, m_crtc.vtotal);
	138	if(scr.max_y <= m_crtc.vend)
	139	scr.max_y = m_crtc.vend + 2;
	140	if(scr.max_x <= m_crtc.hend)
	141	scr.max_x = m_crtc.hend + 2;
	142	visiblescr.set(m_crtc.hbegin, m_crtc.hend, m_crtc.vbegin, m_crtc.vend);
146	143
147	144	// expand visible area to the size indicated by CRTC reg 20
148		length = state->m_crtc.hend - state->m_crtc.hbegin;
149		if (length < state->m_crtc.width)
	145	length = m_crtc.hend - m_crtc.hbegin;
	146	if (length < m_crtc.width)
150	147	{
151		visiblescr.min_x = state->m_crtc.hbegin - ((state->m_crtc.width - length)/2);
152		visiblescr.max_x = state->m_crtc.hend + ((state->m_crtc.width - length)/2);
	148	visiblescr.min_x = m_crtc.hbegin - ((m_crtc.width - length)/2);
	149	visiblescr.max_x = m_crtc.hend + ((m_crtc.width - length)/2);
153	150	}
154		length = state->m_crtc.vend - state->m_crtc.vbegin;
155		if (length < state->m_crtc.height)
	151	length = m_crtc.vend - m_crtc.vbegin;
	152	if (length < m_crtc.height)
156	153	{
157		visiblescr.min_y = state->m_crtc.vbegin - ((state->m_crtc.height - length)/2);
158		visiblescr.max_y = state->m_crtc.vend + ((state->m_crtc.height - length)/2);
	154	visiblescr.min_y = m_crtc.vbegin - ((m_crtc.height - length)/2);
	155	visiblescr.max_y = m_crtc.vend + ((m_crtc.height - length)/2);
159	156	}
160	157	// bounds check
161	158	if(visiblescr.min_x < 0)
r18260	r18261
167	164	if(visiblescr.max_y >= scr.max_y - 1)
168	165	visiblescr.max_y = scr.max_y - 2;
169	166
170		//  logerror("CRTC regs - %i %i %i %i  - %i %i %i %i - %i - %i\n",state->m_crtc.reg[0],state->m_crtc.reg[1],state->m_crtc.reg[2],state->m_crtc.reg[3],
171		//      state->m_crtc.reg[4],state->m_crtc.reg[5],state->m_crtc.reg[6],state->m_crtc.reg[7],state->m_crtc.reg[8],state->m_crtc.reg[9]);
	167	//  logerror("CRTC regs - %i %i %i %i  - %i %i %i %i - %i - %i\n",m_crtc.reg[0],m_crtc.reg[1],m_crtc.reg[2],m_crtc.reg[3],
	168	//      m_crtc.reg[4],m_crtc.reg[5],m_crtc.reg[6],m_crtc.reg[7],m_crtc.reg[8],m_crtc.reg[9]);
172	169	logerror("video_screen_configure(machine.primary_screen,%i,%i,[%i,%i,%i,%i],55.45)\n",scr.max_x,scr.max_y,visiblescr.min_x,visiblescr.min_y,visiblescr.max_x,visiblescr.max_y);
173		machine.primary_screen->configure(scr.max_x,scr.max_y,visiblescr,HZ_TO_ATTOSECONDS(55.45));
	170	machine().primary_screen->configure(scr.max_x,scr.max_y,visiblescr,HZ_TO_ATTOSECONDS(55.45));
174	171	}
175	172
176	173	TIMER_CALLBACK_MEMBER(x68k_state::x68k_hsync)
r18260	r18261
370	367	*    Operation Port bits are cleared automatically when the requested
371	368	*    operation is completed.
372	369	*/
373		WRITE16_HANDLER( x68k_crtc_w )
	370	WRITE16_MEMBER(x68k_state::x68k_crtc_w )
374	371	{
375		x68k_state *state = space.machine().driver_data<x68k_state>();
376		COMBINE_DATA(state->m_crtc.reg+offset);
	372	COMBINE_DATA(m_crtc.reg+offset);
377	373	switch(offset)
378	374	{
379	375	case 0:
r18260	r18261
385	381	case 6:
386	382	case 7:
387	383	case 8:
388		x68k_crtc_refresh_mode(space.machine());
	384	x68k_crtc_refresh_mode();
389	385	break;
390	386	case 9:  // CRTC raster IRQ (GPIP6)
391	387	{
392	388	attotime irq_time;
393		irq_time = space.machine().primary_screen->time_until_pos((data) / state->m_crtc.vmultiple,2);
	389	irq_time = machine().primary_screen->time_until_pos((data) / m_crtc.vmultiple,2);
394	390
395	391	if(irq_time.as_double() > 0)
396		state->m_raster_irq->adjust(irq_time, (data) / state->m_crtc.vmultiple);
	392	m_raster_irq->adjust(irq_time, (data) / m_crtc.vmultiple);
397	393	}
398	394	logerror("CRTC: Write to raster IRQ register - %i\n",data);
399	395	break;
400	396	case 20:
401	397	if(ACCESSING_BITS_0_7)
402	398	{
403		state->m_crtc.interlace = 0;
	399	m_crtc.interlace = 0;
404	400	switch(data & 0x0c)
405	401	{
406	402	case 0x00:
407		state->m_crtc.height = 256;
	403	m_crtc.height = 256;
408	404	break;
409	405	case 0x08:
410	406	case 0x0c:  // TODO: 1024 vertical, if horizontal freq = 31kHz
411		state->m_crtc.height = 512;
412		state->m_crtc.interlace = 1;  // if 31kHz, 1024 lines = interlaced
	407	m_crtc.height = 512;
	408	m_crtc.interlace = 1;  // if 31kHz, 1024 lines = interlaced
413	409	break;
414	410	case 0x04:
415		state->m_crtc.height = 512;
416		if(!(state->m_crtc.reg[20] & 0x0010))  // if 15kHz, 512 lines = interlaced
417		state->m_crtc.interlace = 1;
	411	m_crtc.height = 512;
	412	if(!(m_crtc.reg[20] & 0x0010))  // if 15kHz, 512 lines = interlaced
	413	m_crtc.interlace = 1;
418	414	break;
419	415	}
420	416	switch(data & 0x03)
421	417	{
422	418	case 0x00:
423		state->m_crtc.width = 256;
	419	m_crtc.width = 256;
424	420	break;
425	421	case 0x01:
426		state->m_crtc.width = 512;
	422	m_crtc.width = 512;
427	423	break;
428	424	case 0x02:
429	425	case 0x03:  // 0x03 = 50MHz clock mode (XVI only)
430		state->m_crtc.width = 768;
	426	m_crtc.width = 768;
431	427	break;
432	428	}
433	429	}
434	430	/*      if(ACCESSING_BITS_8_15)
435	431	{
436		state->m_crtc.interlace = 0;
	432	m_crtc.interlace = 0;
437	433	if(data & 0x0400)
438		state->m_crtc.interlace = 1;
	434	m_crtc.interlace = 1;
439	435	}*/
440		x68k_crtc_refresh_mode(space.machine());
	436	x68k_crtc_refresh_mode();
441	437	break;
442	438	case 576:  // operation register
443		state->m_crtc.operation = data;
	439	m_crtc.operation = data;
444	440	if(data & 0x08)  // text screen raster copy
445	441	{
446		x68k_crtc_text_copy(state, (state->m_crtc.reg[22] & 0xff00) >> 8,(state->m_crtc.reg[22] & 0x00ff));
447		space.machine().scheduler().timer_set(attotime::from_msec(1), timer_expired_delegate(FUNC(x68k_state::x68k_crtc_operation_end),state), 0x02);  // time taken to do operation is a complete guess.
	442	x68k_crtc_text_copy((m_crtc.reg[22] & 0xff00) >> 8,(m_crtc.reg[22] & 0x00ff));
	443	machine().scheduler().timer_set(attotime::from_msec(1), timer_expired_delegate(FUNC(x68k_state::x68k_crtc_operation_end),this), 0x02);  // time taken to do operation is a complete guess.
448	444	}
449	445	if(data & 0x02)  // high-speed graphic screen clear
450	446	{
451		if(state->m_is_32bit)
452		memset(state->m_gvram32,0,0x40000);
	447	if(m_is_32bit)
	448	memset(m_gvram32,0,0x40000);
453	449	else
454		memset(state->m_gvram16,0,0x40000);
455		space.machine().scheduler().timer_set(attotime::from_msec(10), timer_expired_delegate(FUNC(x68k_state::x68k_crtc_operation_end),state), 0x02);  // time taken to do operation is a complete guess.
	450	memset(m_gvram16,0,0x40000);
	451	machine().scheduler().timer_set(attotime::from_msec(10), timer_expired_delegate(FUNC(x68k_state::x68k_crtc_operation_end),this), 0x02);  // time taken to do operation is a complete guess.
456	452	}
457	453	break;
458	454	}
459		//  logerror("CRTC: [%08x] Wrote %04x to CRTC register %i\n",space.machine().device("maincpu")->safe_pc(),data,offset);
	455	//  logerror("CRTC: [%08x] Wrote %04x to CRTC register %i\n",machine().device("maincpu")->safe_pc(),data,offset);
460	456	}
461	457
462		READ16_HANDLER( x68k_crtc_r )
	458	READ16_MEMBER(x68k_state::x68k_crtc_r )
463	459	{
464		x68k_state *state = space.machine().driver_data<x68k_state>();
465	460	#if 0
466	461	switch(offset)
467	462	{
r18260	r18261
473	468
474	469	if(offset < 24)
475	470	{
476		//      logerror("CRTC: [%08x] Read %04x from CRTC register %i\n",space.machine().device("maincpu")->safe_pc(),state->m_crtc.reg[offset],offset);
	471	//      logerror("CRTC: [%08x] Read %04x from CRTC register %i\n",machine().device("maincpu")->safe_pc(),m_crtc.reg[offset],offset);
477	472	switch(offset)
478	473	{
479	474	case 9:
r18260	r18261
482	477	case 11:
483	478	case 12:  // Graphic layer 0 scroll
484	479	case 13:
485		return state->m_crtc.reg[offset] & 0x3ff;
	480	return m_crtc.reg[offset] & 0x3ff;
486	481	case 14:  // Graphic layer 1 scroll
487	482	case 15:
488	483	case 16:  // Graphic layer 2 scroll
489	484	case 17:
490	485	case 18:  // Graphic layer 3 scroll
491	486	case 19:
492		return state->m_crtc.reg[offset] & 0x1ff;
	487	return m_crtc.reg[offset] & 0x1ff;
493	488	default:
494		return state->m_crtc.reg[offset];
	489	return m_crtc.reg[offset];
495	490	}
496	491	}
497	492	if(offset == 576) // operation port, operation bits are set to 0 when operation is complete
498		return state->m_crtc.operation;
	493	return m_crtc.operation;
499	494	//  logerror("CRTC: [%08x] Read from unknown CRTC register %i\n",activecpu_get_pc(),offset);
500	495	return 0xffff;
501	496	}
502	497
503		WRITE16_HANDLER( x68k_gvram_w )
	498	WRITE16_MEMBER(x68k_state::x68k_gvram_w )
504	499	{
505		x68k_state *state = space.machine().driver_data<x68k_state>();
506	500	UINT16* gvram;
507	501	//  int xloc,yloc,pageoffset;
508	502	/*
r18260	r18261
520	514	Page 3 - 0xd00000-0xd7ffff    Page 4 - 0xd80000-0xdfffff
521	515	*/
522	516
523		if(state->m_is_32bit)
524		gvram = (UINT16*)state->m_gvram32.target();
	517	if(m_is_32bit)
	518	gvram = (UINT16*)m_gvram32.target();
525	519	else
526		gvram = (UINT16*)state->m_gvram16.target();
	520	gvram = (UINT16*)m_gvram16.target();
527	521
528	522	// handle different G-VRAM page setups
529		if(state->m_crtc.reg[20] & 0x08)  // G-VRAM set to buffer
	523	if(m_crtc.reg[20] & 0x08)  // G-VRAM set to buffer
530	524	{
531	525	if(offset < 0x40000)
532	526	COMBINE_DATA(gvram+offset);
533	527	}
534	528	else
535	529	{
536		switch(state->m_crtc.reg[20] & 0x0300)
	530	switch(m_crtc.reg[20] & 0x0300)
537	531	{
538	532	case 0x0300:
539	533	if(offset < 0x40000)
r18260	r18261
573	567	}
574	568	}
575	569
576		WRITE16_HANDLER( x68k_tvram_w )
	570	WRITE16_MEMBER(x68k_state::x68k_tvram_w )
577	571	{
578		x68k_state *state = space.machine().driver_data<x68k_state>();
579	572	UINT16* tvram;
580	573	UINT16 text_mask;
581	574
582		if(state->m_is_32bit)
583		tvram = (UINT16*)state->m_tvram32.target();
	575	if(m_is_32bit)
	576	tvram = (UINT16*)m_tvram32.target();
584	577	else
585		tvram = (UINT16*)state->m_tvram16.target();
	578	tvram = (UINT16*)m_tvram16.target();
586	579
587		text_mask = ~(state->m_crtc.reg[23]) & mem_mask;
	580	text_mask = ~(m_crtc.reg[23]) & mem_mask;
588	581
589		if(!(state->m_crtc.reg[21] & 0x0200)) // text access mask enable
	582	if(!(m_crtc.reg[21] & 0x0200)) // text access mask enable
590	583	text_mask = 0xffff & mem_mask;
591	584
592	585	mem_mask = text_mask;
593	586
594		if(state->m_crtc.reg[21] & 0x0100)
	587	if(m_crtc.reg[21] & 0x0100)
595	588	{  // simultaneous T-VRAM plane access (I think ;))
596	589	int plane,wr;
597	590	offset = offset & 0x00ffff;
598		wr = (state->m_crtc.reg[21] & 0x00f0) >> 4;
	591	wr = (m_crtc.reg[21] & 0x00f0) >> 4;
599	592	for(plane=0;plane<4;plane++)
600	593	{
601	594	if(wr & (1 << plane))
r18260	r18261
610	603	}
611	604	}
612	605
613		READ16_HANDLER( x68k_gvram_r )
	606	READ16_MEMBER(x68k_state::x68k_gvram_r )
614	607	{
615		x68k_state *state = space.machine().driver_data<x68k_state>();
616	608	const UINT16* gvram;
617	609	UINT16 ret = 0;
618	610
619		if(state->m_is_32bit)
620		gvram = (const UINT16*)state->m_gvram32.target();
	611	if(m_is_32bit)
	612	gvram = (const UINT16*)m_gvram32.target();
621	613	else
622		gvram = (const UINT16*)state->m_gvram16.target();
	614	gvram = (const UINT16*)m_gvram16.target();
623	615
624		if(state->m_crtc.reg[20] & 0x08)  // G-VRAM set to buffer
	616	if(m_crtc.reg[20] & 0x08)  // G-VRAM set to buffer
625	617	return gvram[offset];
626	618
627		switch(state->m_crtc.reg[20] & 0x0300)  // colour setup determines G-VRAM use
	619	switch(m_crtc.reg[20] & 0x0300)  // colour setup determines G-VRAM use
628	620	{
629	621	case 0x0300: // 65,536 colour (RGB) - 16-bits per word
630	622	if(offset < 0x40000)
r18260	r18261
658	650	return ret;
659	651	}
660	652
661		READ16_HANDLER( x68k_tvram_r )
	653	READ16_MEMBER(x68k_state::x68k_tvram_r )
662	654	{
663		x68k_state *state = space.machine().driver_data<x68k_state>();
664	655	const UINT16* tvram;
665	656
666		if(state->m_is_32bit)
667		tvram = (const UINT16*)state->m_tvram32.target();
	657	if(m_is_32bit)
	658	tvram = (const UINT16*)m_tvram32.target();
668	659	else
669		tvram = (const UINT16*)state->m_tvram16.target();
	660	tvram = (const UINT16*)m_tvram16.target();
670	661
671	662	return tvram[offset];
672	663	}
673	664
674		READ32_HANDLER( x68k_tvram32_r )
	665	READ32_MEMBER(x68k_state::x68k_tvram32_r )
675	666	{
676	667	UINT32 ret = 0;
677	668
r18260	r18261
683	674	return ret;
684	675	}
685	676
686		READ32_HANDLER( x68k_gvram32_r )
	677	READ32_MEMBER(x68k_state::x68k_gvram32_r )
687	678	{
688	679	UINT32 ret = 0;
689	680
r18260	r18261
695	686	return ret;
696	687	}
697	688
698		WRITE32_HANDLER( x68k_tvram32_w )
	689	WRITE32_MEMBER(x68k_state::x68k_tvram32_w )
699	690	{
700	691	if(ACCESSING_BITS_0_7)
701	692	x68k_tvram_w(space,(offset*2)+1,data,0x00ff);
r18260	r18261
707	698	x68k_tvram_w(space,offset*2,data >> 16,0xff00);
708	699	}
709	700
710		WRITE32_HANDLER( x68k_gvram32_w )
	701	WRITE32_MEMBER(x68k_state::x68k_gvram32_w )
711	702	{
712	703	if(ACCESSING_BITS_0_7)
713	704	x68k_gvram_w(space,(offset*2)+1,data,0x00ff);
r18260	r18261
719	710	x68k_gvram_w(space,offset*2,data >> 16,0xff00);
720	711	}
721	712
722		WRITE16_HANDLER( x68k_spritereg_w )
	713	WRITE16_MEMBER(x68k_state::x68k_spritereg_w )
723	714	{
724		x68k_state *state = space.machine().driver_data<x68k_state>();
725		COMBINE_DATA(state->m_spritereg+offset);
	715	COMBINE_DATA(m_spritereg+offset);
726	716	switch(offset)
727	717	{
728	718	case 0x400:
729		state->m_bg0_8->set_scrollx(0,(data - state->m_crtc.hbegin - state->m_crtc.bg_hshift) & 0x3ff);
730		state->m_bg0_16->set_scrollx(0,(data - state->m_crtc.hbegin - state->m_crtc.bg_hshift) & 0x3ff);
	719	m_bg0_8->set_scrollx(0,(data - m_crtc.hbegin - m_crtc.bg_hshift) & 0x3ff);
	720	m_bg0_16->set_scrollx(0,(data - m_crtc.hbegin - m_crtc.bg_hshift) & 0x3ff);
731	721	break;
732	722	case 0x401:
733		state->m_bg0_8->set_scrolly(0,(data - state->m_crtc.vbegin) & 0x3ff);
734		state->m_bg0_16->set_scrolly(0,(data - state->m_crtc.vbegin) & 0x3ff);
	723	m_bg0_8->set_scrolly(0,(data - m_crtc.vbegin) & 0x3ff);
	724	m_bg0_16->set_scrolly(0,(data - m_crtc.vbegin) & 0x3ff);
735	725	break;
736	726	case 0x402:
737		state->m_bg1_8->set_scrollx(0,(data - state->m_crtc.hbegin - state->m_crtc.bg_hshift) & 0x3ff);
738		state->m_bg1_16->set_scrollx(0,(data - state->m_crtc.hbegin - state->m_crtc.bg_hshift) & 0x3ff);
	727	m_bg1_8->set_scrollx(0,(data - m_crtc.hbegin - m_crtc.bg_hshift) & 0x3ff);
	728	m_bg1_16->set_scrollx(0,(data - m_crtc.hbegin - m_crtc.bg_hshift) & 0x3ff);
739	729	break;
740	730	case 0x403:
741		state->m_bg1_8->set_scrolly(0,(data - state->m_crtc.vbegin) & 0x3ff);
742		state->m_bg1_16->set_scrolly(0,(data - state->m_crtc.vbegin) & 0x3ff);
	731	m_bg1_8->set_scrolly(0,(data - m_crtc.vbegin) & 0x3ff);
	732	m_bg1_16->set_scrolly(0,(data - m_crtc.vbegin) & 0x3ff);
743	733	break;
744	734	case 0x406:  // BG H-DISP (normally equals CRTC reg 2 value + 4)
745	735	if(data != 0x00ff)
746	736	{
747		state->m_crtc.bg_visible_width = (state->m_crtc.reg[3] - ((data & 0x003f) - 4)) * 8;
748		state->m_crtc.bg_hshift = ((data - (state->m_crtc.reg[2]+4)) * 8);
749		if(state->m_crtc.bg_hshift > 0)
750		state->m_crtc.bg_hshift = 0;
	737	m_crtc.bg_visible_width = (m_crtc.reg[3] - ((data & 0x003f) - 4)) * 8;
	738	m_crtc.bg_hshift = ((data - (m_crtc.reg[2]+4)) * 8);
	739	if(m_crtc.bg_hshift > 0)
	740	m_crtc.bg_hshift = 0;
751	741	}
752	742	break;
753	743	case 0x407:  // BG V-DISP (like CRTC reg 6)
754		state->m_crtc.bg_vshift = state->m_crtc.vshift;
	744	m_crtc.bg_vshift = m_crtc.vshift;
755	745	break;
756	746	case 0x408:  // BG H/V-Res
757		state->m_crtc.bg_hvres = data & 0x1f;
	747	m_crtc.bg_hvres = data & 0x1f;
758	748	if(data != 0xff)
759	749	{  // Handle when the PCG is using 256 and the CRTC is using 512
760		if((state->m_crtc.bg_hvres & 0x0c) == 0x00 && (state->m_crtc.reg[20] & 0x0c) == 0x04)
761		state->m_crtc.bg_double = 2;
	750	if((m_crtc.bg_hvres & 0x0c) == 0x00 && (m_crtc.reg[20] & 0x0c) == 0x04)
	751	m_crtc.bg_double = 2;
762	752	else
763		state->m_crtc.bg_double = 1;
	753	m_crtc.bg_double = 1;
764	754	}
765	755	else
766		state->m_crtc.bg_double = 1;
	756	m_crtc.bg_double = 1;
767	757	break;
768	758	}
769	759	}
770	760
771		READ16_HANDLER( x68k_spritereg_r )
	761	READ16_MEMBER(x68k_state::x68k_spritereg_r )
772	762	{
773		x68k_state *state = space.machine().driver_data<x68k_state>();
774	763	if(offset >= 0x400 && offset < 0x404)
775		return state->m_spritereg[offset] & 0x3ff;
776		return state->m_spritereg[offset];
	764	return m_spritereg[offset] & 0x3ff;
	765	return m_spritereg[offset];
777	766	}
778	767
779		WRITE16_HANDLER( x68k_spriteram_w )
	768	WRITE16_MEMBER(x68k_state::x68k_spriteram_w )
780	769	{
781		x68k_state *state = space.machine().driver_data<x68k_state>();
782		COMBINE_DATA(state->m_spriteram+offset);
783		state->m_video.tile8_dirty[offset / 16] = 1;
784		state->m_video.tile16_dirty[offset / 64] = 1;
	770	COMBINE_DATA(m_spriteram+offset);
	771	m_video.tile8_dirty[offset / 16] = 1;
	772	m_video.tile16_dirty[offset / 64] = 1;
785	773	if(offset < 0x2000)
786	774	{
787		state->m_bg1_8->mark_all_dirty();
788		state->m_bg1_16->mark_all_dirty();
789		state->m_bg0_8->mark_all_dirty();
790		state->m_bg0_16->mark_all_dirty();
	775	m_bg1_8->mark_all_dirty();
	776	m_bg1_16->mark_all_dirty();
	777	m_bg0_8->mark_all_dirty();
	778	m_bg0_16->mark_all_dirty();
791	779	}
792	780	if(offset >= 0x2000 && offset < 0x3000)
793	781	{
794		state->m_bg1_8->mark_tile_dirty(offset & 0x0fff);
795		state->m_bg1_16->mark_tile_dirty(offset & 0x0fff);
	782	m_bg1_8->mark_tile_dirty(offset & 0x0fff);
	783	m_bg1_16->mark_tile_dirty(offset & 0x0fff);
796	784	}
797	785	if(offset >= 0x3000)
798	786	{
799		state->m_bg0_8->mark_tile_dirty(offset & 0x0fff);
800		state->m_bg0_16->mark_tile_dirty(offset & 0x0fff);
	787	m_bg0_8->mark_tile_dirty(offset & 0x0fff);
	788	m_bg0_16->mark_tile_dirty(offset & 0x0fff);
801	789	}
802	790	}
803	791
804		READ16_HANDLER( x68k_spriteram_r )
	792	READ16_MEMBER(x68k_state::x68k_spriteram_r )
805	793	{
806		x68k_state *state = space.machine().driver_data<x68k_state>();
807		return state->m_spriteram[offset];
	794	return m_spriteram[offset];
808	795	}
809	796
810		static void x68k_draw_text(running_machine &machine,bitmap_ind16 &bitmap, int xscr, int yscr, rectangle rect)
	797	void x68k_state::x68k_draw_text(bitmap_ind16 &bitmap, int xscr, int yscr, rectangle rect)
811	798	{
812		x68k_state *state = machine.driver_data<x68k_state>();
813	799	const UINT16* tvram;
814	800	unsigned int line,pixel; // location on screen
815	801	UINT32 loc;  // location in TVRAM
816	802	UINT32 colour;
817	803	int bit;
818	804
819		if(state->m_is_32bit)
820		tvram = (const UINT16*)state->m_tvram32.target();
	805	if(m_is_32bit)
	806	tvram = (const UINT16*)m_tvram32.target();
821	807	else
822		tvram = (const UINT16*)state->m_tvram16.target();
	808	tvram = (const UINT16*)m_tvram16.target();
823	809
824	810	for(line=rect.min_y;line<=rect.max_y;line++)  // per scanline
825	811	{
826	812	// adjust for scroll registers
827		loc = (((line - state->m_crtc.vbegin) + yscr) & 0x3ff) * 64;
	813	loc = (((line - m_crtc.vbegin) + yscr) & 0x3ff) * 64;
828	814	loc += (xscr / 16) & 0x7f;
829	815	loc &= 0xffff;
830	816	bit = 15 - (xscr & 0x0f);
r18260	r18261
834	820	+ (((tvram[loc+0x10000] >> bit) & 0x01) ? 2 : 0)
835	821	+ (((tvram[loc+0x20000] >> bit) & 0x01) ? 4 : 0)
836	822	+ (((tvram[loc+0x30000] >> bit) & 0x01) ? 8 : 0);
837		if(state->m_video.text_pal[colour] != 0x0000)  // any colour but black
	823	if(m_video.text_pal[colour] != 0x0000)  // any colour but black
838	824	{
839	825	// Colour 0 is displayable if the text layer is at the priority level 2
840		if(colour == 0 && (state->m_video.reg[1] & 0x0c00) == 0x0800)
841		bitmap.pix16(line, pixel) = 512 + (state->m_video.text_pal[colour] >> 1);
	826	if(colour == 0 && (m_video.reg[1] & 0x0c00) == 0x0800)
	827	bitmap.pix16(line, pixel) = 512 + (m_video.text_pal[colour] >> 1);
842	828	else
843	829	if(colour != 0)
844		bitmap.pix16(line, pixel) = 512 + (state->m_video.text_pal[colour] >> 1);
	830	bitmap.pix16(line, pixel) = 512 + (m_video.text_pal[colour] >> 1);
845	831	}
846	832	bit--;
847	833	if(bit < 0)
r18260	r18261
854	840	}
855	841	}
856	842
857		static void x68k_draw_gfx_scanline(running_machine &machine, bitmap_ind16 &bitmap, rectangle cliprect, UINT8 priority)
	843	void x68k_state::x68k_draw_gfx_scanline( bitmap_ind16 &bitmap, rectangle cliprect, UINT8 priority)
858	844	{
859		x68k_state *state = machine.driver_data<x68k_state>();
860	845	const UINT16* gvram;
861	846	int pixel;
862	847	int page;
r18260	r18261
867	852	int shift;
868	853	int scanline;
869	854
870		if(state->m_is_32bit)
871		gvram = (const UINT16*)state->m_gvram32.target();
	855	if(m_is_32bit)
	856	gvram = (const UINT16*)m_gvram32.target();
872	857	else
873		gvram = (const UINT16*)state->m_gvram16.target();
	858	gvram = (const UINT16*)m_gvram16.target();
874	859
875	860	for(scanline=cliprect.min_y;scanline<=cliprect.max_y;scanline++)  // per scanline
876	861	{
877		if(state->m_crtc.reg[20] & 0x0400)  // 1024x1024 "real" screen size - use 1024x1024 16-colour gfx layer
	862	if(m_crtc.reg[20] & 0x0400)  // 1024x1024 "real" screen size - use 1024x1024 16-colour gfx layer
878	863	{
879	864	// adjust for scroll registers
880		if(state->m_video.reg[2] & 0x0010 && priority == state->m_video.gfxlayer_pri[0])
	865	if(m_video.reg[2] & 0x0010 && priority == m_video.gfxlayer_pri[0])
881	866	{
882		xscr = (state->m_crtc.reg[12] & 0x3ff);
883		yscr = (state->m_crtc.reg[13] & 0x3ff);
884		lineoffset = (((scanline - state->m_crtc.vbegin) + yscr) & 0x3ff) * 1024;
	867	xscr = (m_crtc.reg[12] & 0x3ff);
	868	yscr = (m_crtc.reg[13] & 0x3ff);
	869	lineoffset = (((scanline - m_crtc.vbegin) + yscr) & 0x3ff) * 1024;
885	870	loc = xscr & 0x3ff;
886		for(pixel=state->m_crtc.hbegin;pixel<=state->m_crtc.hend;pixel++)
	871	for(pixel=m_crtc.hbegin;pixel<=m_crtc.hend;pixel++)
887	872	{
888	873	switch(lineoffset & 0xc0000)
889	874	{
r18260	r18261
901	886	break;
902	887	}
903	888	if(colour != 0)
904		bitmap.pix16(scanline, pixel) = 512 + (state->m_video.gfx_pal[colour] >> 1);
	889	bitmap.pix16(scanline, pixel) = 512 + (m_video.gfx_pal[colour] >> 1);
905	890	loc++;
906	891	loc &= 0x3ff;
907	892	}
r18260	r18261
909	894	}
910	895	else  // else 512x512 "real" screen size
911	896	{
912		if(state->m_video.reg[2] & (1 << priority))
	897	if(m_video.reg[2] & (1 << priority))
913	898	{
914		page = state->m_video.gfxlayer_pri[priority];
	899	page = m_video.gfxlayer_pri[priority];
915	900	// adjust for scroll registers
916		switch(state->m_video.reg[0] & 0x03)
	901	switch(m_video.reg[0] & 0x03)
917	902	{
918	903	case 0x00: // 16 colours
919		xscr = ((state->m_crtc.reg[12+(page*2)])) & 0x1ff;
920		yscr = ((state->m_crtc.reg[13+(page*2)])) & 0x1ff;
921		lineoffset = (((scanline - state->m_crtc.vbegin) + yscr) & 0x1ff) * 512;
	904	xscr = ((m_crtc.reg[12+(page*2)])) & 0x1ff;
	905	yscr = ((m_crtc.reg[13+(page*2)])) & 0x1ff;
	906	lineoffset = (((scanline - m_crtc.vbegin) + yscr) & 0x1ff) * 512;
922	907	loc = xscr & 0x1ff;
923	908	shift = 4;
924		for(pixel=state->m_crtc.hbegin;pixel<=state->m_crtc.hend;pixel++)
	909	for(pixel=m_crtc.hbegin;pixel<=m_crtc.hend;pixel++)
925	910	{
926	911	colour = ((gvram[lineoffset + loc] >> page*shift) & 0x000f);
927	912	if(colour != 0)
928		bitmap.pix16(scanline, pixel) = 512 + (state->m_video.gfx_pal[colour & 0x0f] >> 1);
	913	bitmap.pix16(scanline, pixel) = 512 + (m_video.gfx_pal[colour & 0x0f] >> 1);
929	914	loc++;
930	915	loc &= 0x1ff;
931	916	}
r18260	r18261
933	918	case 0x01: // 256 colours
934	919	if(page == 0 || page == 2)
935	920	{
936		xscr = ((state->m_crtc.reg[12+(page*2)])) & 0x1ff;
937		yscr = ((state->m_crtc.reg[13+(page*2)])) & 0x1ff;
938		lineoffset = (((scanline - state->m_crtc.vbegin) + yscr) & 0x1ff) * 512;
	921	xscr = ((m_crtc.reg[12+(page*2)])) & 0x1ff;
	922	yscr = ((m_crtc.reg[13+(page*2)])) & 0x1ff;
	923	lineoffset = (((scanline - m_crtc.vbegin) + yscr) & 0x1ff) * 512;
939	924	loc = xscr & 0x1ff;
940	925	shift = 4;
941		for(pixel=state->m_crtc.hbegin;pixel<=state->m_crtc.hend;pixel++)
	926	for(pixel=m_crtc.hbegin;pixel<=m_crtc.hend;pixel++)
942	927	{
943	928	colour = ((gvram[lineoffset + loc] >> page*shift) & 0x00ff);
944	929	if(colour != 0)
945		bitmap.pix16(scanline, pixel) = 512 + (state->m_video.gfx_pal[colour & 0xff] >> 1);
	930	bitmap.pix16(scanline, pixel) = 512 + (m_video.gfx_pal[colour & 0xff] >> 1);
946	931	loc++;
947	932	loc &= 0x1ff;
948	933	}
949	934	}
950	935	break;
951	936	case 0x03: // 65536 colours
952		xscr = ((state->m_crtc.reg[12])) & 0x1ff;
953		yscr = ((state->m_crtc.reg[13])) & 0x1ff;
954		lineoffset = (((scanline - state->m_crtc.vbegin) + yscr) & 0x1ff) * 512;
	937	xscr = ((m_crtc.reg[12])) & 0x1ff;
	938	yscr = ((m_crtc.reg[13])) & 0x1ff;
	939	lineoffset = (((scanline - m_crtc.vbegin) + yscr) & 0x1ff) * 512;
955	940	loc = xscr & 0x1ff;
956		for(pixel=state->m_crtc.hbegin;pixel<=state->m_crtc.hend;pixel++)
	941	for(pixel=m_crtc.hbegin;pixel<=m_crtc.hend;pixel++)
957	942	{
958	943	colour = gvram[lineoffset + loc];
959	944	if(colour != 0)
r18260	r18261
968	953	}
969	954	}
970	955
971		static void x68k_draw_gfx(running_machine &machine, bitmap_ind16 &bitmap,rectangle cliprect)
	956	void x68k_state::x68k_draw_gfx(bitmap_ind16 &bitmap,rectangle cliprect)
972	957	{
973		x68k_state *state = machine.driver_data<x68k_state>();
974	958	int priority;
975	959	//rectangle rect;
976	960	//int xscr,yscr;
977	961	//int gpage;
978	962
979		if(state->m_crtc.reg[20] & 0x0800)  // if graphic layers are set to buffer, then they aren't visible
	963	if(m_crtc.reg[20] & 0x0800)  // if graphic layers are set to buffer, then they aren't visible
980	964	return;
981	965
982	966	for(priority=3;priority>=0;priority--)
983	967	{
984		x68k_draw_gfx_scanline(machine, bitmap,cliprect,priority);
	968	x68k_draw_gfx_scanline(bitmap,cliprect,priority);
985	969	}
986	970	}
987	971
988	972	// Sprite controller "Cynthia" at 0xeb0000
989		static void x68k_draw_sprites(running_machine &machine, bitmap_ind16 &bitmap, int priority, rectangle cliprect)
	973	void x68k_state::x68k_draw_sprites(bitmap_ind16 &bitmap, int priority, rectangle cliprect)
990	974	{
991		x68k_state *state = machine.driver_data<x68k_state>();
992	975	/*
993	976	0xeb0000 - 0xeb07ff - Sprite registers (up to 128)
994	977	+ 00 : b9-0,  Sprite X position
r18260	r18261
1022	1005
1023	1006	for(ptr=508;ptr>=0;ptr-=4)  // stepping through sprites
1024	1007	{
1025		pri = state->m_spritereg[ptr+3] & 0x03;
	1008	pri = m_spritereg[ptr+3] & 0x03;
1026	1009	#ifdef MAME_DEBUG
1027		if(!(machine.input().code_pressed(KEYCODE_I)))
	1010	if(!(machine().input().code_pressed(KEYCODE_I)))
1028	1011	#endif
1029	1012	if(pri == priority)
1030	1013	{  // if at the right priority level, draw the sprite
1031	1014	rectangle rect;
1032		int code = state->m_spritereg[ptr+2] & 0x00ff;
1033		int colour = (state->m_spritereg[ptr+2] & 0x0f00) >> 8;
1034		int xflip = state->m_spritereg[ptr+2] & 0x4000;
1035		int yflip = state->m_spritereg[ptr+2] & 0x8000;
1036		int sx = (state->m_spritereg[ptr+0] & 0x3ff) - 16;
1037		int sy = (state->m_spritereg[ptr+1] & 0x3ff) - 16;
	1015	int code = m_spritereg[ptr+2] & 0x00ff;
	1016	int colour = (m_spritereg[ptr+2] & 0x0f00) >> 8;
	1017	int xflip = m_spritereg[ptr+2] & 0x4000;
	1018	int yflip = m_spritereg[ptr+2] & 0x8000;
	1019	int sx = (m_spritereg[ptr+0] & 0x3ff) - 16;
	1020	int sy = (m_spritereg[ptr+1] & 0x3ff) - 16;
1038	1021
1039		rect.min_x=state->m_crtc.hshift;
1040		rect.min_y=state->m_crtc.vshift;
1041		rect.max_x=rect.min_x + state->m_crtc.visible_width-1;
1042		rect.max_y=rect.min_y + state->m_crtc.visible_height-1;
	1022	rect.min_x=m_crtc.hshift;
	1023	rect.min_y=m_crtc.vshift;
	1024	rect.max_x=rect.min_x + m_crtc.visible_width-1;
	1025	rect.max_y=rect.min_y + m_crtc.visible_height-1;
1043	1026
1044		sx += state->m_crtc.bg_hshift;
1045		sx += state->m_sprite_shift;
	1027	sx += m_crtc.bg_hshift;
	1028	sx += m_sprite_shift;
1046	1029
1047		drawgfxzoom_transpen(bitmap,cliprect,machine.gfx[1],code,colour+0x10,xflip,yflip,state->m_crtc.hbegin+sx,state->m_crtc.vbegin+(sy*state->m_crtc.bg_double),0x10000,0x10000*state->m_crtc.bg_double,0x00);
	1030	drawgfxzoom_transpen(bitmap,cliprect,machine().gfx[1],code,colour+0x10,xflip,yflip,m_crtc.hbegin+sx,m_crtc.vbegin+(sy*m_crtc.bg_double),0x10000,0x10000*m_crtc.bg_double,0x00);
1048	1031	}
1049	1032	}
1050	1033	}
r18260	r18261
1214	1197	{
1215	1198	// Graphics screen(s)
1216	1199	if(priority == m_video.gfx_pri)
1217		x68k_draw_gfx(machine(),bitmap,rect);
	1200	x68k_draw_gfx(bitmap,rect);
1218	1201
1219	1202	// Sprite / BG Tiles
1220	1203	if(priority == m_video.sprite_pri /*&& (m_spritereg[0x404] & 0x0200)*/ && (m_video.reg[2] & 0x0040))
1221	1204	{
1222		x68k_draw_sprites(machine(), bitmap,1,rect);
	1205	x68k_draw_sprites(bitmap,1,rect);
1223	1206	if((m_spritereg[0x404] & 0x0008))
1224	1207	{
1225	1208	if((m_spritereg[0x404] & 0x0030) == 0x10)  // BG1 TXSEL
r18260	r18261
1235	1218	x68k_bg1->draw(bitmap,rect,0,0);
1236	1219	}
1237	1220	}
1238		x68k_draw_sprites(machine(),bitmap,2,rect);
	1221	x68k_draw_sprites(bitmap,2,rect);
1239	1222	if((m_spritereg[0x404] & 0x0001))
1240	1223	{
1241	1224	if((m_spritereg[0x404] & 0x0006) == 0x02)  // BG0 TXSEL
r18260	r18261
1251	1234	x68k_bg1->draw(bitmap,rect,0,0);
1252	1235	}
1253	1236	}
1254		x68k_draw_sprites(machine(),bitmap,3,rect);
	1237	x68k_draw_sprites(bitmap,3,rect);
1255	1238	}
1256	1239
1257	1240	// Text screen
r18260	r18261
1260	1243	xscr = (m_crtc.reg[10] & 0x3ff);
1261	1244	yscr = (m_crtc.reg[11] & 0x3ff);
1262	1245	if(!(m_crtc.reg[20] & 0x1000))  // if text layer is set to buffer, then it's not visible
1263		x68k_draw_text(machine(),bitmap,xscr,yscr,rect);
	1246	x68k_draw_text(bitmap,xscr,yscr,rect);
1264	1247	}
1265	1248	}
1266	1249

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