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r18232 Monday 1st October, 2012 at 13:34:42 UTC by Robbbert
AFTOR : more wip
[src/mame]mame.mak
[src/mame/drivers]wico.c
[src/mame/layout]wico.lay*

trunk/src/mame/mame.mak
r18231r18232
22702270
22712271$(DRIVERS)/wecleman.o:   $(LAYOUT)/wecleman.lh
22722272
2273$(DRIVERS)/wico.o:   $(LAYOUT)/wico.lh
2274
22732275$(DRIVERS)/zac2650.o:   $(LAYOUT)/tinv2650.lh
22742276
22752277$(DRIVERS)/zac_1.o:   $(LAYOUT)/zac_1.lh
trunk/src/mame/layout/wico.lay
r0r18232
1<!-- g627.lay -->
2
3<!-- 2012-09-11: Initial version.  [Robbbert] -->
4
5<mamelayout version="2">
6
7   <element name="digit" defstate="0">
8      <led7seg>
9         <color red="1.0" green="0.0" blue="0.0" />
10      </led7seg>
11   </element>
12
13   <element name="background">
14      <rect>
15         <bounds left="0" top="0" right="1" bottom="1" />
16         <color red="0.0" green="0.0" blue="0.0" />
17      </rect>
18   </element>
19   <element name="P0"><text string="Ball / Match"><color red="1.0" green="1.0" blue="1.0" /></text></element>
20   <element name="P1"><text string="Credits"><color red="1.0" green="1.0" blue="1.0" /></text></element>
21   <element name="P3"><text string="East"><color red="1.0" green="1.0" blue="1.0" /></text></element>
22   <element name="P4"><text string="North"><color red="1.0" green="1.0" blue="1.0" /></text></element>
23   <element name="P5"><text string="West"><color red="1.0" green="1.0" blue="1.0" /></text></element>
24   <element name="P6"><text string="South"><color red="1.0" green="1.0" blue="1.0" /></text></element>
25
26   <view name="Default Layout">
27
28      <!-- Background -->
29      <backdrop element="background">
30         <bounds left="0" top="20" right="274" bottom="394" />
31      </backdrop>
32
33      <!-- LEDs -->
34
35      <!-- Player 1 Score -->
36
37      <bezel name="digit0" element="digit">
38         <bounds left="10" top="45" right="44" bottom="84" />
39      </bezel>
40      <bezel name="digit1" element="digit">
41         <bounds left="54" top="45" right="88" bottom="84" />
42      </bezel>
43      <bezel name="digit2" element="digit">
44         <bounds left="98" top="45" right="132" bottom="84" />
45      </bezel>
46      <bezel name="digit3" element="digit">
47         <bounds left="142" top="45" right="176" bottom="84" />
48      </bezel>
49      <bezel name="digit4" element="digit">
50         <bounds left="186" top="45" right="220" bottom="84" />
51      </bezel>
52      <bezel name="digit5" element="digit">
53         <bounds left="230" top="45" right="264" bottom="84" />
54      </bezel>
55
56      <!-- Player 2 Score -->
57      <bezel name="digit10" element="digit">
58         <bounds left="10" top="105" right="44" bottom="144" />
59      </bezel>
60      <bezel name="digit11" element="digit">
61         <bounds left="54" top="105" right="88" bottom="144" />
62      </bezel>
63      <bezel name="digit12" element="digit">
64         <bounds left="98" top="105" right="132" bottom="144" />
65      </bezel>
66      <bezel name="digit13" element="digit">
67         <bounds left="142" top="105" right="176" bottom="144" />
68      </bezel>
69      <bezel name="digit14" element="digit">
70         <bounds left="186" top="105" right="220" bottom="144" />
71      </bezel>
72      <bezel name="digit15" element="digit">
73         <bounds left="230" top="105" right="264" bottom="144" />
74      </bezel>
75
76      <!-- Player 3 Score -->
77      <bezel name="digit20" element="digit">
78         <bounds left="10" top="165" right="44" bottom="204" />
79      </bezel>
80      <bezel name="digit21" element="digit">
81         <bounds left="54" top="165" right="88" bottom="204" />
82      </bezel>
83      <bezel name="digit22" element="digit">
84         <bounds left="98" top="165" right="132" bottom="204" />
85      </bezel>
86      <bezel name="digit23" element="digit">
87         <bounds left="142" top="165" right="176" bottom="204" />
88      </bezel>
89      <bezel name="digit24" element="digit">
90         <bounds left="186" top="165" right="220" bottom="204" />
91      </bezel>
92      <bezel name="digit25" element="digit">
93         <bounds left="230" top="165" right="264" bottom="204" />
94      </bezel>
95
96      <!-- Player 4 Score -->
97      <bezel name="digit30" element="digit">
98         <bounds left="10" top="225" right="44" bottom="264" />
99      </bezel>
100      <bezel name="digit31" element="digit">
101         <bounds left="54" top="225" right="88" bottom="264" />
102      </bezel>
103      <bezel name="digit32" element="digit">
104         <bounds left="98" top="225" right="132" bottom="264" />
105      </bezel>
106      <bezel name="digit33" element="digit">
107         <bounds left="142" top="225" right="176" bottom="264" />
108      </bezel>
109      <bezel name="digit34" element="digit">
110         <bounds left="186" top="225" right="220" bottom="264" />
111      </bezel>
112      <bezel name="digit35" element="digit">
113         <bounds left="230" top="225" right="264" bottom="264" />
114      </bezel>
115
116      <!-- Credits and Balls -->
117      <bezel name="digit50" element="digit">
118         <bounds left="10" top="345" right="44" bottom="384" />
119      </bezel>
120      <bezel name="digit51" element="digit">
121         <bounds left="54" top="345" right="88" bottom="384" />
122      </bezel>
123      <bezel name="digit52" element="digit">
124         <bounds left="98" top="345" right="132" bottom="384" />
125      </bezel>
126      <bezel name="digit53" element="digit">
127         <bounds left="142" top="345" right="176" bottom="384" />
128      </bezel>
129      <bezel name="digit54" element="digit">
130         <bounds left="186" top="345" right="220" bottom="384" />
131      </bezel>
132      <bezel name="digit55" element="digit">
133         <bounds left="230" top="345" right="264" bottom="384" />
134      </bezel>
135      <bezel element="P0"><bounds left="200" right="258" top="330" bottom="342" /></bezel>
136      <bezel element="P1"><bounds left="30" right="88" top="330" bottom="342" /></bezel>
137      <bezel element="P3"><bounds left="100" right="180" top="30" bottom="42" /></bezel>
138      <bezel element="P4"><bounds left="100" right="180" top="90" bottom="102" /></bezel>
139      <bezel element="P5"><bounds left="100" right="180" top="150" bottom="162" /></bezel>
140      <bezel element="P6"><bounds left="100" right="180" top="210" bottom="222" /></bezel>
141   </view>
142</mamelayout>
trunk/src/mame/drivers/wico.c
r18231r18232
1313#include "cpu/m6809/m6809.h"
1414#include "machine/nvram.h"
1515#include "sound/sn76496.h"
16//#include "wico.lh"
16#include "wico.lh"
1717
1818
1919class wico_state : public driver_device
r18231r18232
2727   m_samples(*this, "samples")
2828   { }
2929
30   DECLARE_READ8_MEMBER(lampst_r);
31   DECLARE_READ8_MEMBER(switch_r);
32   DECLARE_WRITE8_MEMBER(muxen_w);
33   DECLARE_WRITE8_MEMBER(muxld_w);
34   DECLARE_WRITE8_MEMBER(dled0_w);
35   DECLARE_WRITE8_MEMBER(dled1_w);
3036   DECLARE_WRITE8_MEMBER(zcres_w);
3137   DECLARE_WRITE8_MEMBER(wdogcl_w);
3238   DECLARE_READ8_MEMBER(gentmrcl_r);
r18231r18232
4551private:
4652   bool m_zcen;
4753   bool m_gten;
54   bool m_disp_on;
55   bool m_diag_on;
4856   UINT8 m_firqtimer;
57   UINT8 m_digit;
4958public:
5059   DECLARE_DRIVER_INIT(wico);
5160};
r18231r18232
5362// housekeeping cpu
5463static ADDRESS_MAP_START( hcpu_map, AS_PROGRAM, 8, wico_state )
5564   AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("sharedram")
56   //AM_RANGE(0x1fe0, 0x1fe0) AM_NOP //AM_WRITE(muxld_w)
65   AM_RANGE(0x1fe0, 0x1fe0) AM_WRITE(muxld_w)
5766   //AM_RANGE(0x1fe1, 0x1fe1) AM_WRITE(store_w)
58   //AM_RANGE(0x1fe2, 0x1fe2) AM_WRITE(muxen_w)
67   AM_RANGE(0x1fe2, 0x1fe2) AM_WRITE(muxen_w)
5968   //AM_RANGE(0x1fe3, 0x1fe3) AM_WRITE(csols_w)
60   //AM_RANGE(0x1fe4, 0x1fe4) AM_READWRITE(msols_r,msols_w)
69   AM_RANGE(0x1fe4, 0x1fe4) AM_READNOP //AM_WRITE(msols_w)
6170   AM_RANGE(0x1fe5, 0x1fe5) AM_DEVWRITE("sn76494", sn76494_new_device, write)
6271   AM_RANGE(0x1fe6, 0x1fe6) AM_WRITE(wdogcl_w)
6372   AM_RANGE(0x1fe7, 0x1fe7) AM_WRITE(zcres_w)
64   //AM_RANGE(0x1fe8, 0x1fe8) AM_WRITE(dled0_w)
65   //AM_RANGE(0x1fe9, 0x1fe9) AM_WRITE(dled1_w)
73   AM_RANGE(0x1fe8, 0x1fe8) AM_WRITE(dled0_w)
74   AM_RANGE(0x1fe9, 0x1fe9) AM_WRITE(dled1_w)
6675   AM_RANGE(0x1fea, 0x1fea) AM_READ(gentmrcl_r)
67   //AM_RANGE(0x1feb, 0x1feb) AM_READ(lampst_r)
76   AM_RANGE(0x1feb, 0x1feb) AM_READ(lampst_r)
6877   //AM_RANGE(0x1fec, 0x1fec) AM_READ(sast_r)
6978   //AM_RANGE(0x1fed, 0x1fed) AM_READ(solst1_r)
7079   //AM_RANGE(0x1fee, 0x1fee) AM_READ(solst0_r)
71   //AM_RANGE(0x1fef, 0x1fef) AM_READ(switch_r)
80   AM_RANGE(0x1fef, 0x1fef) AM_READ(switch_r)
7281   AM_RANGE(0xf000, 0xffff) AM_ROM
7382ADDRESS_MAP_END
7483
7584// command cpu
7685static ADDRESS_MAP_START( ccpu_map, AS_PROGRAM, 8, wico_state )
7786   AM_RANGE(0x0000, 0x07ff) AM_RAM AM_SHARE("sharedram") // 2128  2k RAM
78   //AM_RANGE(0x1fe0, 0x1fe0) AM_WRITE(muxld_w) // to display module
87   AM_RANGE(0x1fe0, 0x1fe0) AM_WRITE(muxld_w) // to display module
7988   //AM_RANGE(0x1fe1, 0x1fe1) AM_WRITE(store_w) // enable save to nvram
80   //AM_RANGE(0x1fe2, 0x1fe2) AM_WRITE(muxen_w) // digit to display on diagnostic LED; d0=L will disable main displays
89   AM_RANGE(0x1fe2, 0x1fe2) AM_WRITE(muxen_w) // digit to display on diagnostic LED; d0=L will disable main displays
8190   //AM_RANGE(0x1fe3, 0x1fe3) AM_WRITE(csols_w) // solenoid column
82   //AM_RANGE(0x1fe4, 0x1fe4) AM_WRITE(msols_w) // solenoid row
91   //AM_RANGE(0x1fe4, 0x1fe4) AM_READNOP AM_WRITE(msols_w) // solenoid row
8392   AM_RANGE(0x1fe5, 0x1fe5) AM_DEVWRITE("sn76494", sn76494_new_device, write)
8493   AM_RANGE(0x1fe6, 0x1fe6) AM_WRITE(wdogcl_w) // watchdog clear
8594   AM_RANGE(0x1fe7, 0x1fe7) AM_WRITE(zcres_w) // enable IRQ on hcpu
86   //AM_RANGE(0x1fe8, 0x1fe8) AM_WRITE(dled0_w) // turn off diagnostic LED
87   //AM_RANGE(0x1fe9, 0x1fe9) AM_WRITE(dled1_w) // turn on diagnostic LED
95   AM_RANGE(0x1fe8, 0x1fe8) AM_WRITE(dled0_w) // turn off diagnostic LED
96   AM_RANGE(0x1fe9, 0x1fe9) AM_WRITE(dled1_w) // turn on diagnostic LED
8897   AM_RANGE(0x1fea, 0x1fea) AM_READ(gentmrcl_r) // enable IRQ on ccpu
89   //AM_RANGE(0x1feb, 0x1feb) AM_READ(lampst_r) // lamps?
98   AM_RANGE(0x1feb, 0x1feb) AM_READ(lampst_r) // lamps?
9099   //AM_RANGE(0x1fec, 0x1fec) AM_READ(sast_r) // a pwron pulse to d0 L->H
91100   //AM_RANGE(0x1fed, 0x1fed) AM_READ(solst1_r) // switches
92101   //AM_RANGE(0x1fee, 0x1fee) AM_READ(solst0_r) // switches
93   //AM_RANGE(0x1fef, 0x1fef) AM_READ(switch_r) // switches
102   AM_RANGE(0x1fef, 0x1fef) AM_READ(switch_r) // switches
94103   AM_RANGE(0x4000, 0x40ff) AM_RAM AM_SHARE("nvram") // X2212 4bit x 256 NVRAM, stores only when store_w is active
95104   AM_RANGE(0x8000, 0x9fff) AM_ROM
96105   AM_RANGE(0xe000, 0xffff) AM_ROM
r18231r18232
120129   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Oil Pit Release") PORT_CODE(KEYCODE_Z)
121130   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Oil Pit Target") PORT_CODE(KEYCODE_C)
122131   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Waterhole Release") PORT_CODE(KEYCODE_V)
123   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Outhole") PORT_CODE(KEYCODE_X)
132   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Outhole") PORT_CODE(KEYCODE_X) // not working
124133   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Spinner") PORT_CODE(KEYCODE_B)
125134   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollunder") PORT_CODE(KEYCODE_N)
126135   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Spinner") PORT_CODE(KEYCODE_M)
r18231r18232
128137   PORT_START("X6")
129138   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L SLingshot") PORT_CODE(KEYCODE_COMMA)
130139   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Slingshot") PORT_CODE(KEYCODE_STOP)
131   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Drop Bank E")
132   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Drop Bank P")
133   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Drop Bank A")
134   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Drop Bank C")
135   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Drop Bank S")
136   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Drop Bank E")
140   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Drop Bank E") PORT_CODE(KEYCODE_A)
141   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Drop Bank P") PORT_CODE(KEYCODE_S)
142   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Drop Bank A") PORT_CODE(KEYCODE_D)
143   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Drop Bank C") PORT_CODE(KEYCODE_F)
144   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Drop Bank S") PORT_CODE(KEYCODE_G)
145   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Drop Bank E") PORT_CODE(KEYCODE_H)
137146   PORT_START("X7")
138147   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Target Zone E")
139148   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Target Zone D")
r18231r18232
144153   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Target Zone A")
145154   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Target Zone F")
146155   PORT_START("X8")
147   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Outlane Target")
148   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Outlane Target")
149   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollover R Outlane")
150   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollover M Outlane")
151   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollover L Outlane")
152   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Rollover R Outlane")
153   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Rollover M Outlane")
154   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Rollover L Outlane")
156   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Outlane Target") PORT_CODE(KEYCODE_MINUS)
157   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Outlane Target") PORT_CODE(KEYCODE_EQUALS)
158   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollover R Outlane") PORT_CODE(KEYCODE_J)
159   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollover M Outlane") PORT_CODE(KEYCODE_K)
160   PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Rollover L Outlane") PORT_CODE(KEYCODE_L)
161   PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Rollover R Outlane") PORT_CODE(KEYCODE_QUOTE)
162   PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Rollover M Outlane") PORT_CODE(KEYCODE_ENTER)
163   PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("L Rollover L Outlane") PORT_CODE(KEYCODE_SLASH)
155164   PORT_START("X9")
156165   PORT_START("XA")
157   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Door Slam") PORT_CODE(KEYCODE_B)
166   PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Door Slam")
158167   PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_TILT) PORT_NAME("Playfield Tilt")
159168   PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Pendulum Tilt")
160169   PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("R Flipper Lane Change")
r18231r18232
276285   m_zcen = 0;
277286   m_gten = 0;
278287   m_firqtimer = 0;
288   m_digit = 0;
289   m_disp_on = 0;
290   m_diag_on = 0;
279291}
280292
281293DRIVER_INIT_MEMBER(wico_state,wico)
282294{
283295}
284296
297// diagnostic display off
298WRITE8_MEMBER( wico_state::dled0_w )
299{
300   m_diag_on = 0;
301}
302
303// diagnostic display on
304WRITE8_MEMBER( wico_state::dled1_w )
305{
306   m_diag_on = 1;
307}
308
309// write to diagnostic display
310WRITE8_MEMBER( wico_state::muxen_w )
311{
312   static const UINT8 patterns[16] = { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x6f, 0x77, 0x7c, 0x39, 0x5e, 0x79, 0x71 }; // MC14495
313   UINT8 segments = 0;
314   if (m_diag_on)
315      segments = patterns[data>>4];
316   output_set_digit_value(41, segments);
317}
318
319// reset digit/scan counter
320WRITE8_MEMBER( wico_state::muxld_w )
321{
322   m_digit = 0;
323}
324
325// enable zero-crossing interrupt
285326WRITE8_MEMBER( wico_state::zcres_w )
286327{
287328   m_zcen = 1;
288329}
289330
331// enable firq
290332READ8_MEMBER( wico_state::gentmrcl_r )
291333{
292334   m_gten = 1;
293335   return 0xff;
294336}
295337
338// read a switch row
339READ8_MEMBER( wico_state::switch_r )
340{
341   char kbdrow[8];
342   sprintf(kbdrow,"X%X",m_shared_ram[0x95]);
343   return ioport(kbdrow)->read();
344}
345
346// write digits in main display
347READ8_MEMBER( wico_state::lampst_r )
348{
349   UINT8 i;
350   for (i = 0; i < 5; i++)
351      output_set_digit_value(i * 10 + (m_shared_ram[0x96] & 7), m_shared_ram[0x7f9 + i]);
352   return 0xff;
353}
354
355// reset watchdog and enable housekeeping cpu
296356WRITE8_MEMBER( wico_state::wdogcl_w )
297357{
298358   m_hcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
r18231r18232
341401   MCFG_NVRAM_ADD_0FILL("nvram")
342402
343403   /* Video */
344   //MCFG_DEFAULT_LAYOUT(layout_wico)
404   MCFG_DEFAULT_LAYOUT(layout_wico)
345405
346406   /* Sound */
347407   MCFG_FRAGMENT_ADD( genpin_audio )
348408   MCFG_SOUND_ADD("sn76494", SN76494_NEW, 10000000 / 64)
349   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
409   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
350410   MCFG_SOUND_CONFIG(psg_intf)
351411MACHINE_CONFIG_END
352412

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