trunk/src/emu/cpu/m6502/ops09.h
| r18158 | r18159 | |
| 128 | 128 | EAH = RDMEM(ZPD); \ |
| 129 | 129 | EAWH = PBWH; \ |
| 130 | 130 | if (EAL + Y > 0xff) \ |
| 131 | | cpustate->icount--; \ |
| 131 | cpustate->icount--; \ |
| 132 | 132 | EAW += Y |
| 133 | 133 | |
| 134 | /*************************************************************** |
| 135 | * EA = zero page indirect + Y (post indexed) |
| 136 | * subtract 1 cycle if page boundary is crossed |
| 137 | ***************************************************************/ |
| 138 | #undef EA_IDY_P |
| 139 | #define EA_IDY_P \ |
| 140 | ZPL = RDOPARG(); \ |
| 141 | EAL = RDMEM(ZPD); \ |
| 142 | ZPL++; \ |
| 143 | EAH = RDMEM(ZPD); \ |
| 144 | EAWH = PBWH; \ |
| 145 | if (EAL + Y > 0xff) { \ |
| 146 | RDMEM( ( EAH << 8 ) | ( ( EAL + Y ) & 0xff ) ); \ |
| 147 | } \ |
| 148 | EAW += Y; |
| 134 | 149 | |
| 135 | 150 | /*************************************************************** |
| 136 | 151 | * EA = zero page indirect + Y (post indexed) |
| r18158 | r18159 | |
| 144 | 159 | EAH = RDMEM(ZPD); \ |
| 145 | 160 | EAWH = IBWH; \ |
| 146 | 161 | if (EAL + Y > 0xff) \ |
| 147 | | cpustate->icount--; \ |
| 162 | cpustate->icount--; \ |
| 148 | 163 | EAW += Y |
| 149 | 164 | |
| 150 | 165 | /*************************************************************** |
| r18158 | r18159 | |
| 172 | 187 | { \ |
| 173 | 188 | tmp = RDOPARG(); \ |
| 174 | 189 | EAW = PCW + (signed char)tmp; \ |
| 175 | | cpustate->icount -= (PCH == EAH) ? 1 : 2; \ |
| 190 | cpustate->icount -= (PCH == EAH) ? 1 : 2; \ |
| 176 | 191 | PCD = EAD|PB; \ |
| 177 | 192 | } \ |
| 178 | 193 | else \ |
| 179 | 194 | { \ |
| 180 | 195 | PCW++; \ |
| 181 | | cpustate->icount -= 1; \ |
| 196 | cpustate->icount -= 1; \ |
| 182 | 197 | } |
| 183 | 198 | |
| 184 | 199 | /* 6502 ******************************************************** |
trunk/src/emu/cpu/m6502/m6509.c
| r18158 | r18159 | |
| 81 | 81 | address_space *space; |
| 82 | 82 | direct_read_data *direct; |
| 83 | 83 | |
| 84 | int int_occured; |
| 84 | 85 | int icount; |
| 85 | 86 | |
| 86 | 87 | devcb_resolved_read8 rdmem_id; /* readmem callback for indexed instructions */ |
| r18158 | r18159 | |
| 157 | 158 | cpustate->rdmem_id.resolve(nullrcb, *device); |
| 158 | 159 | cpustate->wrmem_id.resolve(nullwcb, *device); |
| 159 | 160 | } |
| 161 | |
| 162 | device->save_item(NAME(cpustate->pc.w.l)); |
| 163 | device->save_item(NAME(cpustate->sp.w.l)); |
| 164 | device->save_item(NAME(cpustate->p)); |
| 165 | device->save_item(NAME(cpustate->a)); |
| 166 | device->save_item(NAME(cpustate->x)); |
| 167 | device->save_item(NAME(cpustate->y)); |
| 168 | device->save_item(NAME(cpustate->pending_irq)); |
| 169 | device->save_item(NAME(cpustate->after_cli)); |
| 170 | device->save_item(NAME(cpustate->nmi_state)); |
| 171 | device->save_item(NAME(cpustate->irq_state)); |
| 172 | device->save_item(NAME(cpustate->so_state)); |
| 160 | 173 | } |
| 161 | 174 | |
| 162 | 175 | static CPU_RESET( m6509 ) |
| r18158 | r18159 | |
| 177 | 190 | cpustate->p = F_T|F_B|F_I|F_Z|(P&F_D); /* set T, I and Z flags */ |
| 178 | 191 | cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ |
| 179 | 192 | cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ |
| 180 | | cpustate->irq_callback = NULL; |
| 193 | cpustate->irq_state = 0; |
| 194 | cpustate->nmi_state = 0; |
| 181 | 195 | } |
| 182 | 196 | |
| 183 | 197 | static CPU_EXIT( m6509 ) |
| r18158 | r18159 | |
| 239 | 253 | LOG((": irq line is clear\n")); |
| 240 | 254 | } |
| 241 | 255 | } |
| 242 | | else |
| 243 | | if( cpustate->pending_irq ) |
| 244 | | m6509_take_irq(cpustate); |
| 256 | else { |
| 257 | if ( cpustate->pending_irq == 2 ) { |
| 258 | if ( cpustate->int_occured - cpustate->icount > 1 ) { |
| 259 | cpustate->pending_irq = 1; |
| 260 | } |
| 261 | } |
| 262 | if( cpustate->pending_irq == 1 ) |
| 263 | m6509_take_irq(cpustate); |
| 264 | if ( cpustate->pending_irq == 2 ) { |
| 265 | cpustate->pending_irq = 1; |
| 266 | } |
| 267 | } |
| 245 | 268 | |
| 246 | 269 | } while (cpustate->icount > 0); |
| 247 | 270 | } |
| r18158 | r18159 | |
| 284 | 307 | { |
| 285 | 308 | LOG(( "M6509 '%s' set_irq_line(ASSERT)\n", cpustate->device->tag())); |
| 286 | 309 | cpustate->pending_irq = 1; |
| 310 | cpustate->int_occured = cpustate->icount; |
| 287 | 311 | } |
| 288 | 312 | } |
| 289 | 313 | } |
| r18158 | r18159 | |
| 401 | 425 | cpustate->p & 0x01 ? 'C':'.'); |
| 402 | 426 | break; |
| 403 | 427 | |
| 404 | | case CPUINFO_STR_REGISTER + M6509_PC: sprintf(info->s, "PC:%04X", cpustate->pc.w.l); break; |
| 428 | case CPUINFO_STR_REGISTER + M6509_PC: sprintf(info->s, "PC:%05X", cpustate->pc.d); break; |
| 405 | 429 | case CPUINFO_STR_REGISTER + M6509_S: sprintf(info->s, "S:%02X", cpustate->sp.b.l); break; |
| 406 | 430 | case CPUINFO_STR_REGISTER + M6509_P: sprintf(info->s, "P:%02X", cpustate->p); break; |
| 407 | 431 | case CPUINFO_STR_REGISTER + M6509_A: sprintf(info->s, "A:%02X", cpustate->a); break; |
| r18158 | r18159 | |
| 409 | 433 | case CPUINFO_STR_REGISTER + M6509_Y: sprintf(info->s, "Y:%02X", cpustate->y); break; |
| 410 | 434 | case CPUINFO_STR_REGISTER + M6509_PC_BANK: sprintf(info->s, "M0:%01X", cpustate->pc_bank.b.h2); break; |
| 411 | 435 | case CPUINFO_STR_REGISTER + M6509_IND_BANK: sprintf(info->s, "M1:%01X", cpustate->ind_bank.b.h2); break; |
| 412 | | case CPUINFO_STR_REGISTER + M6509_EA: sprintf(info->s, "EA:%04X", cpustate->ea.w.l); break; |
| 436 | case CPUINFO_STR_REGISTER + M6509_EA: sprintf(info->s, "EA:%05X", cpustate->ea.d); break; |
| 413 | 437 | case CPUINFO_STR_REGISTER + M6509_ZP: sprintf(info->s, "ZP:%03X", cpustate->zp.w.l); break; |
| 414 | 438 | } |
| 415 | 439 | } |