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r18085 Sunday 23rd September, 2012 at 09:18:37 UTC by Fabio Priuli
(MESS) nes.c: moved bankswitch functions into nes_carts_state. no whatsnew. among other things, this  allowed to remove around a thousand of machine() parameters passed to re-get the state class at each bankswitch operation. readability says thanks.

[src/mess/includes]	nes.h nes_mmc.h
[src/mess/machine]	nes.c nes_ines.c nes_mmc.c nes_pcb.c

trunk/src/mess/machine/nes_ines.c

r18084	r18085
53	53	{
54	54	case 0x1fe:
55	55	m_mmc_latch1 = data & 0x80;
56		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	56	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
57	57	break;
58	58	case 0x1ff:
59		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	59	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
60	60	break;
61	61
62	62	case 0x401:
r18084	r18085
78	78
79	79	if (!m_mmc_latch1)   // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
80	80	{
81		prg16_89ab(machine(), data >> 2);
82		// chr8(machine(), data & 0x03, ???);
	81	prg16_89ab(data >> 2);
	82	// chr8(data & 0x03, ???);
83	83	// due to lack of info on the exact behavior, we simply act as if mmc_latch1=1
84	84	if (m_mmc_chr_source == CHRROM)
85		chr8(machine(), data & 0x03, CHRROM);
	85	chr8(data & 0x03, CHRROM);
86	86	}
87	87	else if (m_mmc_chr_source == CHRROM)         // otherwise, we can use CHRROM (when present)
88		chr8(machine(), data, CHRROM);
	88	chr8(data, CHRROM);
89	89	}
90	90
91	91	/*************************************************************
r18084	r18085
103	103	{
104	104	LOG_MMC(("mapper8_w, offset: %04x, data: %02x\n", offset, data));
105	105
106		chr8(machine(), data & 0x07, CHRROM);
107		prg16_89ab(machine(), data >> 3);
	106	chr8(data & 0x07, CHRROM);
	107	prg16_89ab(data >> 3);
108	108	}
109	109
110	110	/*************************************************************
r18084	r18085
126	126	switch (offset)
127	127	{
128	128	case 0x1fe:
129		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	129	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
130	130	break;
131	131	case 0x1ff:
132		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	132	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
133	133	break;
134	134
135	135	case 0x401:
r18084	r18085
144	144	break;
145	145
146	146	case 0x404:
147		prg8_89(machine(), data);
	147	prg8_89(data);
148	148	break;
149	149	case 0x405:
150		prg8_ab(machine(), data);
	150	prg8_ab(data);
151	151	break;
152	152	case 0x406:
153		prg8_cd(machine(), data);
	153	prg8_cd(data);
154	154	break;
155	155	case 0x407:
156		prg8_ef(machine(), data);
	156	prg8_ef(data);
157	157	break;
158	158
159	159	case 0x410:
r18084	r18085
164	164	case 0x415:
165	165	case 0x416:
166	166	case 0x417:
167		chr1_x(machine(), offset & 7, data, CHRROM);
	167	chr1_x(offset & 7, data, CHRROM);
168	168	break;
169	169	}
170	170	}

trunk/src/mess/machine/nes_pcb.c

r18084	r18085
718	718	{
719	719	LOG_MMC(("uxrom_w, offset: %04x, data: %02x\n", offset, data));
720	720
721		prg16_89ab(machine(), data);
	721	prg16_89ab(data);
722	722	}
723	723
724	724	/*************************************************************
r18084	r18085
741	741	{
742	742	LOG_MMC(("uxrom_cc_w, offset: %04x, data: %02x\n", offset, data));
743	743
744		prg16_cdef(machine(), data);
	744	prg16_cdef(data);
745	745	}
746	746
747	747	/*************************************************************
r18084	r18085
764	764	{
765	765	LOG_MMC(("un1rom_w, offset: %04x, data: %02x\n", offset, data));
766	766
767		prg16_89ab(machine(), data >> 2);
	767	prg16_89ab(data >> 2);
768	768	}
769	769
770	770	/*************************************************************
r18084	r18085
797	797
798	798	if (m_ce_mask)
799	799	{
800		chr8(machine(), data & ~m_ce_mask, CHRROM);
	800	chr8(data & ~m_ce_mask, CHRROM);
801	801
802	802	if ((data & m_ce_mask) == m_ce_state)
803	803	m_chr_open_bus = 0;
r18084	r18085
805	805	m_chr_open_bus = 1;
806	806	}
807	807	else
808		chr8(machine(), data, CHRROM);
	808	chr8(data, CHRROM);
809	809	}
810	810
811	811	/*************************************************************
r18084	r18085
848	848	WRITE8_MEMBER(nes_carts_state::cprom_w)
849	849	{
850	850	LOG_MMC(("cprom_w, offset: %04x, data: %02x\n", offset, data));
851		chr4_4(machine(), data, CHRRAM);
	851	chr4_4(data, CHRRAM);
852	852	}
853	853
854	854	/*************************************************************
r18084	r18085
871	871	{
872	872	LOG_MMC(("axrom_w, offset: %04x, data: %02x\n", offset, data));
873	873
874		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
875		prg32(machine(), data);
	874	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	875	prg32(data);
876	876	}
877	877
878	878	/*************************************************************
r18084	r18085
893	893	/* Deadly Towers is really a BxROM game - the demo screens look wrong using mapper 7. */
894	894	LOG_MMC(("bxrom_w, offset: %04x, data: %02x\n", offset, data));
895	895
896		prg32(machine(), data);
	896	prg32(data);
897	897	}
898	898
899	899	/*************************************************************
r18084	r18085
912	912	{
913	913	LOG_MMC(("gxrom_w, offset %04x, data: %02x\n", offset, data));
914	914
915		prg32(machine(), (data & 0xf0) >> 4);
916		chr8(machine(), data & 0x0f, CHRROM);
	915	prg32((data & 0xf0) >> 4);
	916	chr8(data & 0x0f, CHRROM);
917	917	}
918	918
919	919	/*************************************************************
r18084	r18085
950	950	}
951	951	case STD_SXROM_A:   // ignore WRAM enable bit
952	952	if (state->m_battery_size > 0x2000)
953		wram_bank(machine, ((state->m_mmc_reg[1] & 3) >> 2), NES_BATTERY);
	953	state->wram_bank(((state->m_mmc_reg[1] & 3) >> 2), NES_BATTERY);
954	954	else if (state->m_battery_size)
955		wram_bank(machine, 0, NES_BATTERY);
	955	state->wram_bank(0, NES_BATTERY);
956	956	break;
957	957	case STD_SOROM:      // there are 2 WRAM banks only and battery is bank 2 for the cart (hence, we invert bank, because we have battery first)
958	958	if (!BIT(state->m_mmc_reg[3], 4))
r18084	r18085
963	963	break;
964	964	}
965	965	case STD_SOROM_A:   // ignore WRAM enable bit
966		wram_bank(machine, 0, bank ? NES_BATTERY : NES_WRAM);
	966	state->wram_bank(0, bank ? NES_BATTERY : NES_WRAM);
967	967	break;
968	968	}
969	969	}
r18084	r18085
989	989	case 0x00:
990	990	case 0x04:
991	991	//          printf("PRG 32 bank %d \n", (prg_offset + state->m_mmc_reg[3]) >> 1);
992		prg32(machine, (prg_offset + state->m_mmc_reg[3]) >> 1);
	992	state->prg32((prg_offset + state->m_mmc_reg[3]) >> 1);
993	993	break;
994	994	case 0x08:
995	995	//          printf("PRG 16 bank %d (high) \n", prg_offset + state->m_mmc_reg[3]);
996		prg16_89ab(machine, prg_offset + 0);
997		prg16_cdef(machine, prg_offset + state->m_mmc_reg[3]);
	996	state->prg16_89ab(prg_offset + 0);
	997	state->prg16_cdef(prg_offset + state->m_mmc_reg[3]);
998	998	break;
999	999	case 0x0c:
1000	1000	//          printf("PRG 16 bank %d (low) \n", prg_offset + state->m_mmc_reg[3]);
1001		prg16_89ab(machine, prg_offset + state->m_mmc_reg[3]);
1002		prg16_cdef(machine, prg_offset + 0x0f);
	1001	state->prg16_89ab(prg_offset + state->m_mmc_reg[3]);
	1002	state->prg16_cdef(prg_offset + 0x0f);
1003	1003	break;
1004	1004	}
1005	1005	}
r18084	r18085
1017	1017
1018	1018	if (chr_mode)
1019	1019	{
1020		chr4_0(machine, state->m_mmc_reg[1] & 0x1f, state->m_mmc_chr_source);
1021		chr4_4(machine, state->m_mmc_reg[2] & 0x1f, state->m_mmc_chr_source);
	1020	state->chr4_0(state->m_mmc_reg[1] & 0x1f, state->m_mmc_chr_source);
	1021	state->chr4_4(state->m_mmc_reg[2] & 0x1f, state->m_mmc_chr_source);
1022	1022	}
1023	1023	else
1024		chr8(machine, (state->m_mmc_reg[1] & 0x1f) >> 1, state->m_mmc_chr_source);
	1024	state->chr8((state->m_mmc_reg[1] & 0x1f) >> 1, state->m_mmc_chr_source);
1025	1025	}
1026	1026
1027	1027	static void common_sxrom_write_handler( address_space &space, offs_t offset, UINT8 data, int board )
r18084	r18085
1043	1043	else
1044	1044	{
1045	1045	state->m_mmc1_reg_write_enable = 0;
1046		space.machine().scheduler().synchronize(FUNC(mmc1_resync_callback));
	1046	machine.scheduler().synchronize(FUNC(mmc1_resync_callback));
1047	1047	}
1048	1048
1049	1049	if (data & 0x80)
r18084	r18085
1074	1074
1075	1075	switch (state->m_mmc_reg[0] & 0x03)
1076	1076	{
1077		case 0: set_nt_mirroring(machine, PPU_MIRROR_LOW); break;
1078		case 1: set_nt_mirroring(machine, PPU_MIRROR_HIGH); break;
1079		case 2: set_nt_mirroring(machine, PPU_MIRROR_VERT); break;
1080		case 3: set_nt_mirroring(machine, PPU_MIRROR_HORZ); break;
	1077	case 0: state->set_nt_mirroring(PPU_MIRROR_LOW); break;
	1078	case 1: state->set_nt_mirroring(PPU_MIRROR_HIGH); break;
	1079	case 2: state->set_nt_mirroring(PPU_MIRROR_VERT); break;
	1080	case 3: state->set_nt_mirroring(PPU_MIRROR_HORZ); break;
1081	1081	}
1082	1082	mmc1_set_chr(machine);
1083	1083	mmc1_set_prg_wram(space, board);
r18084	r18085
1125	1125	{
1126	1126	LOG_MMC(("mmc2 vrom latch switch (bank 0 low): %02x\n", state->m_mmc_reg[0]));
1127	1127	state->m_mmc_latch1 = 0xfd;
1128		chr4_0(device->machine(), state->m_mmc_reg[0], CHRROM);
	1128	state->chr4_0(state->m_mmc_reg[0], CHRROM);
1129	1129	}
1130	1130	else if ((offset & 0x3ff0) == 0x0fe0)
1131	1131	{
1132	1132	LOG_MMC(("mmc2 vrom latch switch (bank 0 high): %02x\n", state->m_mmc_reg[1]));
1133	1133	state->m_mmc_latch1 = 0xfe;
1134		chr4_0(device->machine(), state->m_mmc_reg[1], CHRROM);
	1134	state->chr4_0(state->m_mmc_reg[1], CHRROM);
1135	1135	}
1136	1136	else if ((offset & 0x3ff0) == 0x1fd0)
1137	1137	{
1138	1138	LOG_MMC(("mmc2 vrom latch switch (bank 1 low): %02x\n", state->m_mmc_reg[2]));
1139	1139	state->m_mmc_latch2 = 0xfd;
1140		chr4_4(device->machine(), state->m_mmc_reg[2], CHRROM);
	1140	state->chr4_4(state->m_mmc_reg[2], CHRROM);
1141	1141	}
1142	1142	else if ((offset & 0x3ff0) == 0x1fe0)
1143	1143	{
1144	1144	LOG_MMC(("mmc2 vrom latch switch (bank 0 high): %02x\n", state->m_mmc_reg[3]));
1145	1145	state->m_mmc_latch2 = 0xfe;
1146		chr4_4(device->machine(), state->m_mmc_reg[3], CHRROM);
	1146	state->chr4_4(state->m_mmc_reg[3], CHRROM);
1147	1147	}
1148	1148	}
1149	1149
r18084	r18085
1153	1153	switch (offset & 0x7000)
1154	1154	{
1155	1155	case 0x2000:
1156		prg8_89(machine(), data);
	1156	prg8_89(data);
1157	1157	break;
1158	1158	case 0x3000:
1159	1159	m_mmc_reg[0] = data;
1160	1160	if (m_mmc_latch1 == 0xfd)
1161		chr4_0(machine(), m_mmc_reg[0], CHRROM);
	1161	chr4_0(m_mmc_reg[0], CHRROM);
1162	1162	break;
1163	1163	case 0x4000:
1164	1164	m_mmc_reg[1] = data;
1165	1165	if (m_mmc_latch1 == 0xfe)
1166		chr4_0(machine(), m_mmc_reg[1], CHRROM);
	1166	chr4_0(m_mmc_reg[1], CHRROM);
1167	1167	break;
1168	1168	case 0x5000:
1169	1169	m_mmc_reg[2] = data;
1170	1170	if (m_mmc_latch2 == 0xfd)
1171		chr4_4(machine(), m_mmc_reg[2], CHRROM);
	1171	chr4_4(m_mmc_reg[2], CHRROM);
1172	1172	break;
1173	1173	case 0x6000:
1174	1174	m_mmc_reg[3] = data;
1175	1175	if (m_mmc_latch2 == 0xfe)
1176		chr4_4(machine(), m_mmc_reg[3], CHRROM);
	1176	chr4_4(m_mmc_reg[3], CHRROM);
1177	1177	break;
1178	1178	case 0x7000:
1179		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1179	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1180	1180	break;
1181	1181	default:
1182	1182	LOG_MMC(("MMC2 uncaught w: %04x:%02x\n", offset, data));
r18084	r18085
1202	1202	switch (offset & 0x7000)
1203	1203	{
1204	1204	case 0x2000:
1205		prg16_89ab(machine(), data);
	1205	prg16_89ab(data);
1206	1206	break;
1207	1207	default:
1208	1208	pxrom_w(space, offset, data, mem_mask);
r18084	r18085
1244	1244	}
1245	1245	}
1246	1246
	1247	// base MMC3 simply calls prg8_x
	1248	static void mmc3_base_prg_cb( running_machine &machine, int start, int bank )
	1249	{
	1250	nes_state *state = machine.driver_data<nes_state>();
	1251	state->prg8_x(start, bank);
	1252	}
	1253
	1254	// base MMC3 simply calls chr1_x
	1255	static void mmc3_base_chr_cb( running_machine &machine, int start, int bank, int source )
	1256	{
	1257	nes_state *state = machine.driver_data<nes_state>();
	1258	state->chr1_x(start, bank, source);
	1259	}
	1260
	1261
1247	1262	static void mmc3_set_prg( running_machine &machine, int prg_base, int prg_mask )
1248	1263	{
1249	1264	nes_state *state = machine.driver_data<nes_state>();
r18084	r18085
1332	1347	break;
1333	1348
1334	1349	case 0x2000:
1335		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1350	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1336	1351	break;
1337	1352
1338	1353	case 0x2001:
r18084	r18085
1466	1481	nes_state *state = machine.driver_data<nes_state>();
1467	1482	if (state->m_mmc3_latch & 0x80)
1468	1483	{
1469		set_nt_page(machine, 0, CIRAM, (state->m_mmc_vrom_bank[2] & 0x80) >> 7, 1);
1470		set_nt_page(machine, 1, CIRAM, (state->m_mmc_vrom_bank[3] & 0x80) >> 7, 1);
1471		set_nt_page(machine, 2, CIRAM, (state->m_mmc_vrom_bank[4] & 0x80) >> 7, 1);
1472		set_nt_page(machine, 3, CIRAM, (state->m_mmc_vrom_bank[5] & 0x80) >> 7, 1);
	1484	state->set_nt_page(0, CIRAM, (state->m_mmc_vrom_bank[2] & 0x80) >> 7, 1);
	1485	state->set_nt_page(1, CIRAM, (state->m_mmc_vrom_bank[3] & 0x80) >> 7, 1);
	1486	state->set_nt_page(2, CIRAM, (state->m_mmc_vrom_bank[4] & 0x80) >> 7, 1);
	1487	state->set_nt_page(3, CIRAM, (state->m_mmc_vrom_bank[5] & 0x80) >> 7, 1);
1473	1488	}
1474	1489	else
1475	1490	{
1476		set_nt_page(machine, 0, CIRAM, (state->m_mmc_vrom_bank[0] & 0x80) >> 7, 1);
1477		set_nt_page(machine, 1, CIRAM, (state->m_mmc_vrom_bank[0] & 0x80) >> 7, 1);
1478		set_nt_page(machine, 2, CIRAM, (state->m_mmc_vrom_bank[1] & 0x80) >> 7, 1);
1479		set_nt_page(machine, 3, CIRAM, (state->m_mmc_vrom_bank[1] & 0x80) >> 7, 1);
	1491	state->set_nt_page(0, CIRAM, (state->m_mmc_vrom_bank[0] & 0x80) >> 7, 1);
	1492	state->set_nt_page(1, CIRAM, (state->m_mmc_vrom_bank[0] & 0x80) >> 7, 1);
	1493	state->set_nt_page(2, CIRAM, (state->m_mmc_vrom_bank[1] & 0x80) >> 7, 1);
	1494	state->set_nt_page(3, CIRAM, (state->m_mmc_vrom_bank[1] & 0x80) >> 7, 1);
1480	1495	}
1481	1496	}
1482	1497
1483	1498	static void txsrom_chr_cb( running_machine &machine, int start, int bank, int source )
1484	1499	{
	1500	nes_state *state = machine.driver_data<nes_state>();
1485	1501	txsrom_set_mirror(machine);   // we could probably update only for one (e.g. the first) call, to slightly optimize the code
1486		chr1_x(machine, start, bank, source);
	1502	state->chr1_x(start, bank, source);
1487	1503	}
1488	1504
1489	1505	WRITE8_MEMBER(nes_carts_state::txsrom_w)
r18084	r18085
1526	1542	chr_mask[i] =  (state->m_mmc_vrom_bank[i] & 0x40) ? 0x07 : 0x3f;
1527	1543	}
1528	1544
1529		chr1_x(machine, chr_page ^ 0, ((state->m_mmc_vrom_bank[0] & ~0x01) & chr_mask[0]), chr_src[0]);
1530		chr1_x(machine, chr_page ^ 1, ((state->m_mmc_vrom_bank[0] |  0x01) & chr_mask[0]), chr_src[0]);
1531		chr1_x(machine, chr_page ^ 2, ((state->m_mmc_vrom_bank[1] & ~0x01) & chr_mask[1]), chr_src[1]);
1532		chr1_x(machine, chr_page ^ 3, ((state->m_mmc_vrom_bank[1] |  0x01) & chr_mask[1]), chr_src[1]);
1533		chr1_x(machine, chr_page ^ 4, (state->m_mmc_vrom_bank[2] & chr_mask[2]), chr_src[2]);
1534		chr1_x(machine, chr_page ^ 5, (state->m_mmc_vrom_bank[3] & chr_mask[3]), chr_src[3]);
1535		chr1_x(machine, chr_page ^ 6, (state->m_mmc_vrom_bank[4] & chr_mask[4]), chr_src[4]);
1536		chr1_x(machine, chr_page ^ 7, (state->m_mmc_vrom_bank[5] & chr_mask[5]), chr_src[5]);
	1545	state->chr1_x(chr_page ^ 0, ((state->m_mmc_vrom_bank[0] & ~0x01) & chr_mask[0]), chr_src[0]);
	1546	state->chr1_x(chr_page ^ 1, ((state->m_mmc_vrom_bank[0] |  0x01) & chr_mask[0]), chr_src[0]);
	1547	state->chr1_x(chr_page ^ 2, ((state->m_mmc_vrom_bank[1] & ~0x01) & chr_mask[1]), chr_src[1]);
	1548	state->chr1_x(chr_page ^ 3, ((state->m_mmc_vrom_bank[1] |  0x01) & chr_mask[1]), chr_src[1]);
	1549	state->chr1_x(chr_page ^ 4, (state->m_mmc_vrom_bank[2] & chr_mask[2]), chr_src[2]);
	1550	state->chr1_x(chr_page ^ 5, (state->m_mmc_vrom_bank[3] & chr_mask[3]), chr_src[3]);
	1551	state->chr1_x(chr_page ^ 6, (state->m_mmc_vrom_bank[4] & chr_mask[4]), chr_src[4]);
	1552	state->chr1_x(chr_page ^ 7, (state->m_mmc_vrom_bank[5] & chr_mask[5]), chr_src[5]);
1537	1553	}
1538	1554
1539	1555	WRITE8_MEMBER(nes_carts_state::tqrom_w)
r18084	r18085
1640	1656	switch (state->m_mmc5_chr_mode)
1641	1657	{
1642	1658	case 0:   // 8k banks
1643		chr8(machine, state->m_mmc5_vrom_regA[7] & 0xff, CHRROM);
	1659	state->chr8(state->m_mmc5_vrom_regA[7] & 0xff, CHRROM);
1644	1660	break;
1645	1661
1646	1662	case 1:   // 4k banks
1647		chr4_0(machine, state->m_mmc5_vrom_regA[3] & 0xff, CHRROM);
1648		chr4_4(machine, state->m_mmc5_vrom_regA[7] & 0xff, CHRROM);
	1663	state->chr4_0(state->m_mmc5_vrom_regA[3] & 0xff, CHRROM);
	1664	state->chr4_4(state->m_mmc5_vrom_regA[7] & 0xff, CHRROM);
1649	1665	break;
1650	1666
1651	1667	case 2:   // 2k banks
1652		chr2_0(machine, state->m_mmc5_vrom_regA[1], CHRROM);
1653		chr2_2(machine, state->m_mmc5_vrom_regA[3], CHRROM);
1654		chr2_4(machine, state->m_mmc5_vrom_regA[5], CHRROM);
1655		chr2_6(machine, state->m_mmc5_vrom_regA[7], CHRROM);
	1668	state->chr2_0(state->m_mmc5_vrom_regA[1], CHRROM);
	1669	state->chr2_2(state->m_mmc5_vrom_regA[3], CHRROM);
	1670	state->chr2_4(state->m_mmc5_vrom_regA[5], CHRROM);
	1671	state->chr2_6(state->m_mmc5_vrom_regA[7], CHRROM);
1656	1672	break;
1657	1673
1658	1674	case 3:   // 1k banks
1659		chr1_0(machine, state->m_mmc5_vrom_regA[0], CHRROM);
1660		chr1_1(machine, state->m_mmc5_vrom_regA[1], CHRROM);
1661		chr1_2(machine, state->m_mmc5_vrom_regA[2], CHRROM);
1662		chr1_3(machine, state->m_mmc5_vrom_regA[3], CHRROM);
1663		chr1_4(machine, state->m_mmc5_vrom_regA[4], CHRROM);
1664		chr1_5(machine, state->m_mmc5_vrom_regA[5], CHRROM);
1665		chr1_6(machine, state->m_mmc5_vrom_regA[6], CHRROM);
1666		chr1_7(machine, state->m_mmc5_vrom_regA[7], CHRROM);
	1675	state->chr1_0(state->m_mmc5_vrom_regA[0], CHRROM);
	1676	state->chr1_1(state->m_mmc5_vrom_regA[1], CHRROM);
	1677	state->chr1_2(state->m_mmc5_vrom_regA[2], CHRROM);
	1678	state->chr1_3(state->m_mmc5_vrom_regA[3], CHRROM);
	1679	state->chr1_4(state->m_mmc5_vrom_regA[4], CHRROM);
	1680	state->chr1_5(state->m_mmc5_vrom_regA[5], CHRROM);
	1681	state->chr1_6(state->m_mmc5_vrom_regA[6], CHRROM);
	1682	state->chr1_7(state->m_mmc5_vrom_regA[7], CHRROM);
1667	1683	break;
1668	1684	}
1669	1685	}
r18084	r18085
1674	1690	switch (state->m_mmc5_chr_mode)
1675	1691	{
1676	1692	case 0:   // 8k banks
1677		chr8(machine, state->m_mmc5_vrom_regB[3] & 0xff, CHRROM);
	1693	state->chr8(state->m_mmc5_vrom_regB[3] & 0xff, CHRROM);
1678	1694	break;
1679	1695
1680	1696	case 1:   // 4k banks
1681		chr4_0(machine, state->m_mmc5_vrom_regB[3] & 0xff, CHRROM);
1682		chr4_4(machine, state->m_mmc5_vrom_regB[3] & 0xff, CHRROM);
	1697	state->chr4_0(state->m_mmc5_vrom_regB[3] & 0xff, CHRROM);
	1698	state->chr4_4(state->m_mmc5_vrom_regB[3] & 0xff, CHRROM);
1683	1699	break;
1684	1700
1685	1701	case 2:   // 2k banks
1686		chr2_0(machine, state->m_mmc5_vrom_regB[1], CHRROM);
1687		chr2_2(machine, state->m_mmc5_vrom_regB[3], CHRROM);
1688		chr2_4(machine, state->m_mmc5_vrom_regB[1], CHRROM);
1689		chr2_6(machine, state->m_mmc5_vrom_regB[3], CHRROM);
	1702	state->chr2_0(state->m_mmc5_vrom_regB[1], CHRROM);
	1703	state->chr2_2(state->m_mmc5_vrom_regB[3], CHRROM);
	1704	state->chr2_4(state->m_mmc5_vrom_regB[1], CHRROM);
	1705	state->chr2_6(state->m_mmc5_vrom_regB[3], CHRROM);
1690	1706	break;
1691	1707
1692	1708	case 3:   // 1k banks
1693		chr1_0(machine, state->m_mmc5_vrom_regB[0], CHRROM);
1694		chr1_1(machine, state->m_mmc5_vrom_regB[1], CHRROM);
1695		chr1_2(machine, state->m_mmc5_vrom_regB[2], CHRROM);
1696		chr1_3(machine, state->m_mmc5_vrom_regB[3], CHRROM);
1697		chr1_4(machine, state->m_mmc5_vrom_regB[0], CHRROM);
1698		chr1_5(machine, state->m_mmc5_vrom_regB[1], CHRROM);
1699		chr1_6(machine, state->m_mmc5_vrom_regB[2], CHRROM);
1700		chr1_7(machine, state->m_mmc5_vrom_regB[3], CHRROM);
	1709	state->chr1_0(state->m_mmc5_vrom_regB[0], CHRROM);
	1710	state->chr1_1(state->m_mmc5_vrom_regB[1], CHRROM);
	1711	state->chr1_2(state->m_mmc5_vrom_regB[2], CHRROM);
	1712	state->chr1_3(state->m_mmc5_vrom_regB[3], CHRROM);
	1713	state->chr1_4(state->m_mmc5_vrom_regB[0], CHRROM);
	1714	state->chr1_5(state->m_mmc5_vrom_regB[1], CHRROM);
	1715	state->chr1_6(state->m_mmc5_vrom_regB[2], CHRROM);
	1716	state->chr1_7(state->m_mmc5_vrom_regB[3], CHRROM);
1701	1717	break;
1702	1718	}
1703	1719	}
r18084	r18085
1711	1727	switch (state->m_mmc5_prg_mode)
1712	1728	{
1713	1729	case 0:   // 32k banks
1714		prg32(machine, state->m_mmc5_prg_regs[3] >> 2);
	1730	state->prg32(state->m_mmc5_prg_regs[3] >> 2);
1715	1731	break;
1716	1732
1717	1733	case 1:   // 16k banks
r18084	r18085
1726	1742	state->membank("bank2")->set_entry(state->m_prg_bank[1]);
1727	1743	}
1728	1744	else
1729		prg16_89ab(machine, bank1 >> 1);
	1745	state->prg16_89ab(bank1 >> 1);
1730	1746
1731		prg16_cdef(machine, state->m_mmc5_prg_regs[3] >> 1);
	1747	state->prg16_cdef(state->m_mmc5_prg_regs[3] >> 1);
1732	1748	break;
1733	1749
1734	1750	case 2:   // 16k-8k banks
r18084	r18085
1744	1760	state->membank("bank2")->set_entry(state->m_prg_bank[1]);
1745	1761	}
1746	1762	else
1747		prg16_89ab(machine, (bank1 & 0x7f) >> 1);
	1763	state->prg16_89ab((bank1 & 0x7f) >> 1);
1748	1764
1749	1765	if (!BIT(bank3, 7))
1750	1766	{
r18084	r18085
1752	1768	state->membank("bank3")->set_entry(state->m_prg_bank[2]);
1753	1769	}
1754	1770	else
1755		prg8_cd(machine, bank3 & 0x7f);
	1771	state->prg8_cd(bank3 & 0x7f);
1756	1772
1757		prg8_ef(machine, state->m_mmc5_prg_regs[3]);
	1773	state->prg8_ef(state->m_mmc5_prg_regs[3]);
1758	1774	break;
1759	1775
1760	1776	case 3:   // 8k banks
r18084	r18085
1769	1785	state->membank("bank1")->set_entry(state->m_prg_bank[0]);
1770	1786	}
1771	1787	else
1772		prg8_89(machine, bank1 & 0x7f);
	1788	state->prg8_89(bank1 & 0x7f);
1773	1789
1774	1790	if (!BIT(bank2, 7))
1775	1791	{
r18084	r18085
1777	1793	state->membank("bank2")->set_entry(state->m_prg_bank[1]);
1778	1794	}
1779	1795	else
1780		prg8_ab(machine, bank2 & 0x7f);
	1796	state->prg8_ab(bank2 & 0x7f);
1781	1797
1782	1798	if (!BIT(bank3, 7))
1783	1799	{
r18084	r18085
1785	1801	state->membank("bank3")->set_entry(state->m_prg_bank[2]);
1786	1802	}
1787	1803	else
1788		prg8_cd(machine, bank3 & 0x7f);
	1804	state->prg8_cd(bank3 & 0x7f);
1789	1805
1790		prg8_ef(machine, state->m_mmc5_prg_regs[3]);
	1806	state->prg8_ef(state->m_mmc5_prg_regs[3]);
1791	1807	break;
1792	1808	}
1793	1809	}
r18084	r18085
1825	1841
1826	1842	static void mmc5_ppu_mirror( running_machine &machine, int page, int src )
1827	1843	{
	1844	nes_state *state = machine.driver_data<nes_state>();
1828	1845	switch (src)
1829	1846	{
1830	1847	case 0:   /* CIRAM0 */
1831		set_nt_page(machine, page, CIRAM, 0, 1);
	1848	state->set_nt_page(page, CIRAM, 0, 1);
1832	1849	break;
1833	1850	case 1:   /* CIRAM1 */
1834		set_nt_page(machine, page, CIRAM, 1, 1);
	1851	state->set_nt_page(page, CIRAM, 1, 1);
1835	1852	break;
1836	1853	case 2:   /* ExRAM */
1837		set_nt_page(machine, page, EXRAM, 0, 1);   // actually only works during rendering.
	1854	state->set_nt_page(page, EXRAM, 0, 1);   // actually only works during rendering.
1838	1855	break;
1839	1856	case 3: /* Fill Registers */
1840		set_nt_page(machine, page, MMC5FILL, 0, 0);
	1857	state->set_nt_page(page, MMC5FILL, 0, 0);
1841	1858	break;
1842	1859	default:
1843	1860	fatalerror("This should never happen\n");
r18084	r18085
1966	1983	LOG_MMC(("MMC5 mid RAM bank select: %02x\n", data & 0x07));
1967	1984	// FIXME: a few Koei games have both WRAM & BWRAM but here we don't support this (yet)
1968	1985	if (m_battery)
1969		wram_bank(machine(), data, NES_BATTERY);
	1986	wram_bank(data, NES_BATTERY);
1970	1987	else
1971		wram_bank(machine(), data, NES_WRAM);
	1988	wram_bank(data, NES_WRAM);
1972	1989	break;
1973	1990
1974	1991
r18084	r18085
2031	2048	/* 1k switch */
2032	2049	m_MMC5_vrom_bank[0] = data | (m_mmc5_high_chr << 8);
2033	2050	//                  mapper5_sync_vrom(0);
2034		chr1_0(machine(), m_MMC5_vrom_bank[0], CHRROM);
	2051	chr1_0(m_MMC5_vrom_bank[0], CHRROM);
2035	2052	//                  m_nes_vram_sprite[0] = m_MMC5_vrom_bank[0] * 64;
2036	2053	//                  vrom_next[0] = 4;
2037	2054	//                  vrom_page_a = 1;
r18084	r18085
2045	2062	{
2046	2063	case 0x02:
2047	2064	/* 2k switch */
2048		chr2_0(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2065	chr2_0(data | (m_mmc5_high_chr << 8), CHRROM);
2049	2066	break;
2050	2067	case 0x03:
2051	2068	/* 1k switch */
2052	2069	m_MMC5_vrom_bank[1] = data | (m_mmc5_high_chr << 8);
2053	2070	//                  mapper5_sync_vrom(0);
2054		chr1_1(machine(), m_MMC5_vrom_bank[1], CHRROM);
	2071	chr1_1(m_MMC5_vrom_bank[1], CHRROM);
2055	2072	//                  m_nes_vram_sprite[1] = m_MMC5_vrom_bank[0] * 64;
2056	2073	//                  vrom_next[1] = 5;
2057	2074	//                  vrom_page_a = 1;
r18084	r18085
2067	2084	/* 1k switch */
2068	2085	m_MMC5_vrom_bank[2] = data | (m_mmc5_high_chr << 8);
2069	2086	//                  mapper5_sync_vrom(0);
2070		chr1_2(machine(), m_MMC5_vrom_bank[2], CHRROM);
	2087	chr1_2(m_MMC5_vrom_bank[2], CHRROM);
2071	2088	//                  m_nes_vram_sprite[2] = m_MMC5_vrom_bank[0] * 64;
2072	2089	//                  vrom_next[2] = 6;
2073	2090	//                  vrom_page_a = 1;
r18084	r18085
2080	2097	switch (m_mmc5_chr_mode)
2081	2098	{
2082	2099	case 0x01:
2083		chr4_0(machine(), data, CHRROM);
	2100	chr4_0(data, CHRROM);
2084	2101	break;
2085	2102	case 0x02:
2086	2103	/* 2k switch */
2087		chr2_2(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2104	chr2_2(data | (m_mmc5_high_chr << 8), CHRROM);
2088	2105	break;
2089	2106	case 0x03:
2090	2107	/* 1k switch */
2091	2108	m_MMC5_vrom_bank[3] = data | (m_mmc5_high_chr << 8);
2092	2109	//                  mapper5_sync_vrom(0);
2093		chr1_3(machine(), m_MMC5_vrom_bank[3], CHRROM);
	2110	chr1_3(m_MMC5_vrom_bank[3], CHRROM);
2094	2111	//                  m_nes_vram_sprite[3] = m_MMC5_vrom_bank[0] * 64;
2095	2112	//                  vrom_next[3] = 7;
2096	2113	//                  vrom_page_a = 1;
r18084	r18085
2106	2123	/* 1k switch */
2107	2124	m_MMC5_vrom_bank[4] = data | (m_mmc5_high_chr << 8);
2108	2125	//                  mapper5_sync_vrom(0);
2109		chr1_4(machine(), m_MMC5_vrom_bank[4], CHRROM);
	2126	chr1_4(m_MMC5_vrom_bank[4], CHRROM);
2110	2127	//                  m_nes_vram_sprite[4] = m_MMC5_vrom_bank[0] * 64;
2111	2128	//                  vrom_next[0] = 0;
2112	2129	//                  vrom_page_a = 0;
r18084	r18085
2120	2137	{
2121	2138	case 0x02:
2122	2139	/* 2k switch */
2123		chr2_4(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2140	chr2_4(data | (m_mmc5_high_chr << 8), CHRROM);
2124	2141	break;
2125	2142	case 0x03:
2126	2143	/* 1k switch */
2127	2144	m_MMC5_vrom_bank[5] = data | (m_mmc5_high_chr << 8);
2128	2145	//                  mapper5_sync_vrom(0);
2129		chr1_5(machine(), m_MMC5_vrom_bank[5], CHRROM);
	2146	chr1_5(m_MMC5_vrom_bank[5], CHRROM);
2130	2147	//                  m_nes_vram_sprite[5] = m_MMC5_vrom_bank[0] * 64;
2131	2148	//                  vrom_next[1] = 1;
2132	2149	//                  vrom_page_a = 0;
r18084	r18085
2142	2159	/* 1k switch */
2143	2160	m_MMC5_vrom_bank[6] = data | (m_mmc5_high_chr << 8);
2144	2161	//                  mapper5_sync_vrom(0);
2145		chr1_6(machine(), m_MMC5_vrom_bank[6], CHRROM);
	2162	chr1_6(m_MMC5_vrom_bank[6], CHRROM);
2146	2163	//                  m_nes_vram_sprite[6] = m_MMC5_vrom_bank[0] * 64;
2147	2164	//                  vrom_next[2] = 2;
2148	2165	//                  vrom_page_a = 0;
r18084	r18085
2156	2173	{
2157	2174	case 0x00:
2158	2175	/* 8k switch */
2159		chr8(machine(), data, CHRROM);
	2176	chr8(data, CHRROM);
2160	2177	break;
2161	2178	case 0x01:
2162	2179	/* 4k switch */
2163		chr4_4(machine(), data, CHRROM);
	2180	chr4_4(data, CHRROM);
2164	2181	break;
2165	2182	case 0x02:
2166	2183	/* 2k switch */
2167		chr2_6(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2184	chr2_6(data | (m_mmc5_high_chr << 8), CHRROM);
2168	2185	break;
2169	2186	case 0x03:
2170	2187	/* 1k switch */
2171	2188	m_MMC5_vrom_bank[7] = data | (m_mmc5_high_chr << 8);
2172	2189	//                  mapper5_sync_vrom(0);
2173		chr1_7(machine(), m_MMC5_vrom_bank[7], CHRROM);
	2190	chr1_7(m_MMC5_vrom_bank[7], CHRROM);
2174	2191	//                  m_nes_vram_sprite[7] = m_MMC5_vrom_bank[0] * 64;
2175	2192	//                  vrom_next[3] = 3;
2176	2193	//                  vrom_page_a = 0;
r18084	r18085
2188	2205	//                  nes_vram[vrom_next[0]] = data * 64;
2189	2206	//                  nes_vram[0 + (vrom_page_a*4)] = data * 64;
2190	2207	//                  nes_vram[0] = data * 64;
2191		chr1_4(machine(), m_MMC5_vrom_bank[8], CHRROM);
	2208	chr1_4(m_MMC5_vrom_bank[8], CHRROM);
2192	2209	//                  mapper5_sync_vrom(1);
2193	2210	if (!m_vrom_page_b)
2194	2211	{
r18084	r18085
2204	2221	{
2205	2222	case 0x02:
2206	2223	/* 2k switch */
2207		chr2_0(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2208		chr2_4(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2224	chr2_0(data | (m_mmc5_high_chr << 8), CHRROM);
	2225	chr2_4(data | (m_mmc5_high_chr << 8), CHRROM);
2209	2226	break;
2210	2227	case 0x03:
2211	2228	/* 1k switch */
r18084	r18085
2213	2230	//                  nes_vram[vrom_next[1]] = data * 64;
2214	2231	//                  nes_vram[1 + (vrom_page_a*4)] = data * 64;
2215	2232	//                  nes_vram[1] = data * 64;
2216		chr1_5(machine(), m_MMC5_vrom_bank[9], CHRROM);
	2233	chr1_5(m_MMC5_vrom_bank[9], CHRROM);
2217	2234	//                  mapper5_sync_vrom(1);
2218	2235	if (!m_vrom_page_b)
2219	2236	{
r18084	r18085
2233	2250	//                  nes_vram[vrom_next[2]] = data * 64;
2234	2251	//                  nes_vram[2 + (vrom_page_a*4)] = data * 64;
2235	2252	//                  nes_vram[2] = data * 64;
2236		chr1_6(machine(), m_MMC5_vrom_bank[10], CHRROM);
	2253	chr1_6(m_MMC5_vrom_bank[10], CHRROM);
2237	2254	//                  mapper5_sync_vrom(1);
2238	2255	if (!m_vrom_page_b)
2239	2256	{
r18084	r18085
2250	2267	case 0x00:
2251	2268	/* 8k switch */
2252	2269	/* switches in first half of an 8K bank!) */
2253		chr4_0(machine(), data << 1, CHRROM);
2254		chr4_4(machine(), data << 1, CHRROM);
	2270	chr4_0(data << 1, CHRROM);
	2271	chr4_4(data << 1, CHRROM);
2255	2272	break;
2256	2273	case 0x01:
2257	2274	/* 4k switch */
2258		chr4_0(machine(), data, CHRROM);
2259		chr4_4(machine(), data, CHRROM);
	2275	chr4_0(data, CHRROM);
	2276	chr4_4(data, CHRROM);
2260	2277	break;
2261	2278	case 0x02:
2262	2279	/* 2k switch */
2263		chr2_2(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
2264		chr2_6(machine(), data | (m_mmc5_high_chr << 8), CHRROM);
	2280	chr2_2(data | (m_mmc5_high_chr << 8), CHRROM);
	2281	chr2_6(data | (m_mmc5_high_chr << 8), CHRROM);
2265	2282	break;
2266	2283	case 0x03:
2267	2284	/* 1k switch */
r18084	r18085
2269	2286	//                  nes_vram[vrom_next[3]] = data * 64;
2270	2287	//                  nes_vram[3 + (vrom_page_a*4)] = data * 64;
2271	2288	//                  nes_vram[3] = data * 64;
2272		chr1_7(machine(), m_MMC5_vrom_bank[11], CHRROM);
	2289	chr1_7(m_MMC5_vrom_bank[11], CHRROM);
2273	2290	//                  mapper5_sync_vrom(1);
2274	2291	if (!m_vrom_page_b)
2275	2292	{
r18084	r18085
2341	2358
2342	2359	static void ntbrom_mirror( running_machine &machine, int mirror, int mirr0, int mirr1 )
2343	2360	{
	2361	nes_state *state = machine.driver_data<nes_state>();
2344	2362	switch (mirror)
2345	2363	{
2346	2364	case 0x00:
2347		set_nt_mirroring(machine, PPU_MIRROR_HORZ);
	2365	state->set_nt_mirroring(PPU_MIRROR_HORZ);
2348	2366	break;
2349	2367	case 0x01:
2350		set_nt_mirroring(machine, PPU_MIRROR_VERT);
	2368	state->set_nt_mirroring(PPU_MIRROR_VERT);
2351	2369	break;
2352	2370	case 0x02:
2353		set_nt_mirroring(machine, PPU_MIRROR_LOW);
	2371	state->set_nt_mirroring(PPU_MIRROR_LOW);
2354	2372	break;
2355	2373	case 0x03:
2356		set_nt_mirroring(machine, PPU_MIRROR_HIGH);
	2374	state->set_nt_mirroring(PPU_MIRROR_HIGH);
2357	2375	break;
2358	2376	case 0x10:
2359		set_nt_page(machine, 0, ROM, mirr0 | 0x80, 0);
2360		set_nt_page(machine, 1, ROM, mirr1 | 0x80, 0);
2361		set_nt_page(machine, 2, ROM, mirr0 | 0x80, 0);
2362		set_nt_page(machine, 3, ROM, mirr1 | 0x80, 0);
	2377	state->set_nt_page(0, ROM, mirr0 | 0x80, 0);
	2378	state->set_nt_page(1, ROM, mirr1 | 0x80, 0);
	2379	state->set_nt_page(2, ROM, mirr0 | 0x80, 0);
	2380	state->set_nt_page(3, ROM, mirr1 | 0x80, 0);
2363	2381	break;
2364	2382	case 0x11:
2365		set_nt_page(machine, 0, ROM, mirr0 | 0x80, 0);
2366		set_nt_page(machine, 1, ROM, mirr0 | 0x80, 0);
2367		set_nt_page(machine, 2, ROM, mirr1 | 0x80, 0);
2368		set_nt_page(machine, 3, ROM, mirr1 | 0x80, 0);
	2383	state->set_nt_page(0, ROM, mirr0 | 0x80, 0);
	2384	state->set_nt_page(1, ROM, mirr0 | 0x80, 0);
	2385	state->set_nt_page(2, ROM, mirr1 | 0x80, 0);
	2386	state->set_nt_page(3, ROM, mirr1 | 0x80, 0);
2369	2387	break;
2370	2388	case 0x12:
2371		set_nt_page(machine, 0, ROM, mirr0 | 0x80, 0);
2372		set_nt_page(machine, 1, ROM, mirr0 | 0x80, 0);
2373		set_nt_page(machine, 2, ROM, mirr0 | 0x80, 0);
2374		set_nt_page(machine, 3, ROM, mirr0 | 0x80, 0);
	2389	state->set_nt_page(0, ROM, mirr0 | 0x80, 0);
	2390	state->set_nt_page(1, ROM, mirr0 | 0x80, 0);
	2391	state->set_nt_page(2, ROM, mirr0 | 0x80, 0);
	2392	state->set_nt_page(3, ROM, mirr0 | 0x80, 0);
2375	2393	break;
2376	2394	case 0x13:
2377		set_nt_page(machine, 0, ROM, mirr1 | 0x80, 0);
2378		set_nt_page(machine, 1, ROM, mirr1 | 0x80, 0);
2379		set_nt_page(machine, 2, ROM, mirr1 | 0x80, 0);
2380		set_nt_page(machine, 3, ROM, mirr1 | 0x80, 0);
	2395	state->set_nt_page(0, ROM, mirr1 | 0x80, 0);
	2396	state->set_nt_page(1, ROM, mirr1 | 0x80, 0);
	2397	state->set_nt_page(2, ROM, mirr1 | 0x80, 0);
	2398	state->set_nt_page(3, ROM, mirr1 | 0x80, 0);
2381	2399	break;
2382	2400	}
2383	2401	}
r18084	r18085
2390	2408	switch (offset & 0x7000)
2391	2409	{
2392	2410	case 0x0000:
2393		chr2_0(machine(), data, CHRROM);
	2411	chr2_0(data, CHRROM);
2394	2412	break;
2395	2413	case 0x1000:
2396		chr2_2(machine(), data, CHRROM);
	2414	chr2_2(data, CHRROM);
2397	2415	break;
2398	2416	case 0x2000:
2399		chr2_4(machine(), data, CHRROM);
	2417	chr2_4(data, CHRROM);
2400	2418	break;
2401	2419	case 0x3000:
2402		chr2_6(machine(), data, CHRROM);
	2420	chr2_6(data, CHRROM);
2403	2421	break;
2404	2422	case 0x4000:
2405	2423	m_mmc_latch1 = data & 0x7f;
r18084	r18085
2414	2432	ntbrom_mirror(machine(), m_mmc_reg[0], m_mmc_latch1, m_mmc_latch2);
2415	2433	break;
2416	2434	case 0x7000:
2417		prg16_89ab(machine(), data);
	2435	prg16_89ab(data);
2418	2436	break;
2419	2437	default:
2420	2438	LOG_MMC(("ntbrom_w uncaught write, offset: %04x, data: %02x\n", offset, data));
r18084	r18085
2474	2492	switch (m_mmc_latch1)
2475	2493	{
2476	2494	case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
2477		chr1_x(machine(), m_mmc_latch1, data, CHRROM);
	2495	chr1_x(m_mmc_latch1, data, CHRROM);
2478	2496	break;
2479	2497
2480	2498	case 8:
r18084	r18085
2482	2500	{
2483	2501	// is PRG ROM
2484	2502	space.unmap_write(0x6000, 0x7fff);
2485		prg8_67(machine(), data & 0x3f);
	2503	prg8_67(data & 0x3f);
2486	2504	}
2487	2505	else if (data & 0x80)
2488	2506	{
r18084	r18085
2494	2512	break;
2495	2513
2496	2514	case 9:
2497		prg8_89(machine(), data);
	2515	prg8_89(data);
2498	2516	break;
2499	2517	case 0x0a:
2500		prg8_ab(machine(), data);
	2518	prg8_ab(data);
2501	2519	break;
2502	2520	case 0x0b:
2503		prg8_cd(machine(), data);
	2521	prg8_cd(data);
2504	2522	break;
2505	2523	case 0x0c:
2506	2524	switch (data & 0x03)
2507	2525	{
2508		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
2509		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
2510		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
2511		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	2526	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	2527	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	2528	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	2529	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
2512	2530	}
2513	2531	break;
2514	2532	case 0x0d:
r18084	r18085
2564	2582	case 1:
2565	2583	switch (m_mmc_latch1 & 0x07)
2566	2584	{
2567		case 0: chr2_0(machine(), data >> 1, CHRROM); break;
2568		case 1: chr2_2(machine(), data >> 1, CHRROM); break;
2569		case 2: chr1_4(machine(), data | 0x40, CHRROM); break;
2570		case 3: chr1_5(machine(), data | 0x40, CHRROM); break;
2571		case 4: chr1_6(machine(), data | 0x40, CHRROM); break;
2572		case 5: chr1_7(machine(), data | 0x40, CHRROM); break;
2573		case 6: prg8_89(machine(), data); break;
2574		case 7: prg8_ab(machine(), data); break;
	2585	case 0: chr2_0(data >> 1, CHRROM); break;
	2586	case 1: chr2_2(data >> 1, CHRROM); break;
	2587	case 2: chr1_4(data | 0x40, CHRROM); break;
	2588	case 3: chr1_5(data | 0x40, CHRROM); break;
	2589	case 4: chr1_6(data | 0x40, CHRROM); break;
	2590	case 5: chr1_7(data | 0x40, CHRROM); break;
	2591	case 6: prg8_89(data); break;
	2592	case 7: prg8_ab(data); break;
2575	2593	}
2576	2594	break;
2577	2595	case 0:
r18084	r18085
2600	2618
2601	2619	// additional mirroring control when writing to even addresses
2602	2620	if (!(offset & 1))
2603		set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	2621	set_nt_mirroring(BIT(data, 6) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
2604	2622
2605	2623	dxrom_w(space, offset, data, mem_mask);
2606	2624	}
r18084	r18085
2625	2643	if (offset >= 0x2000)
2626	2644	{
2627	2645	if (!(offset & 1))
2628		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	2646	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
2629	2647	return;
2630	2648	}
2631	2649
r18084	r18085
2634	2652	case 1:
2635	2653	switch (m_mmc_latch1 & 0x07)
2636	2654	{
2637		case 2: chr2_0(machine(), data, CHRROM); break;
2638		case 3: chr2_2(machine(), data, CHRROM); break;
2639		case 4: chr2_4(machine(), data, CHRROM); break;
2640		case 5: chr2_6(machine(), data, CHRROM); break;
2641		case 6: BIT(m_mmc_latch1, 6) ? prg8_cd(machine(), data) : prg8_89(machine(), data); break;
2642		case 7: prg8_ab(machine(), data); break;
	2655	case 2: chr2_0(data, CHRROM); break;
	2656	case 3: chr2_2(data, CHRROM); break;
	2657	case 4: chr2_4(data, CHRROM); break;
	2658	case 5: chr2_6(data, CHRROM); break;
	2659	case 6: BIT(m_mmc_latch1, 6) ? prg8_cd(data) : prg8_89(data); break;
	2660	case 7: prg8_ab(data); break;
2643	2661	}
2644	2662	break;
2645	2663	case 0:
r18084	r18085
2674	2692	mode = m_mmc_latch1 & 0x07;
2675	2693	switch (mode)
2676	2694	{
2677		case 0: chr2_0(machine(), data >> 1, CHRROM); break;
2678		case 1: chr2_2(machine(), data >> 1, CHRROM); break;
	2695	case 0: chr2_0(data >> 1, CHRROM); break;
	2696	case 1: chr2_2(data >> 1, CHRROM); break;
2679	2697	case 2:
2680	2698	case 3:
2681	2699	case 4:
2682	2700	case 5:
2683		chr1_x(machine(), 2 + mode, data, CHRROM);
	2701	chr1_x(2 + mode, data, CHRROM);
2684	2702	m_mmc_reg[mode - 2] = BIT(data, 5);
2685	2703	if (!BIT(m_mmc_latch1, 7))
2686	2704	{
2687		set_nt_page(machine(), 0, CIRAM, m_mmc_reg[0], 1);
2688		set_nt_page(machine(), 1, CIRAM, m_mmc_reg[1], 1);
2689		set_nt_page(machine(), 2, CIRAM, m_mmc_reg[2], 1);
2690		set_nt_page(machine(), 3, CIRAM, m_mmc_reg[3], 1);
	2705	set_nt_page(0, CIRAM, m_mmc_reg[0], 1);
	2706	set_nt_page(1, CIRAM, m_mmc_reg[1], 1);
	2707	set_nt_page(2, CIRAM, m_mmc_reg[2], 1);
	2708	set_nt_page(3, CIRAM, m_mmc_reg[3], 1);
2691	2709	}
2692	2710	else
2693		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	2711	set_nt_mirroring(PPU_MIRROR_HORZ);
2694	2712	break;
2695		case 6: prg8_89(machine(), data); break;
2696		case 7: prg8_ab(machine(), data); break;
	2713	case 6: prg8_89(data); break;
	2714	case 7: prg8_ab(data); break;
2697	2715	}
2698	2716	break;
2699	2717	case 0:
r18084	r18085
2718	2736	{
2719	2737	LOG_MMC(("dis_74x377_w, offset: %04x, data: %02x\n", offset, data));
2720	2738
2721		chr8(machine(), data >> 4, m_mmc_chr_source);
2722		prg32(machine(), data & 0x0f);
	2739	chr8(data >> 4, m_mmc_chr_source);
	2740	prg32(data & 0x0f);
2723	2741	}
2724	2742
2725	2743	/*************************************************************
r18084	r18085
2734	2752	{
2735	2753	LOG_MMC(("dis_74x139x74_m_w, offset: %04x, data: %02x\n", offset, data));
2736	2754
2737		chr8(machine(), ((data & 0x02) >> 1) | ((data & 0x01) << 1), CHRROM);
	2755	chr8(((data & 0x02) >> 1) | ((data & 0x01) << 1), CHRROM);
2738	2756	}
2739	2757
2740	2758	/*************************************************************
r18084	r18085
2751	2769	{
2752	2770	LOG_MMC(("dis_74x161x138_m_w, offset: %04x, data: %02x\n", offset, data));
2753	2771
2754		chr8(machine(), data >> 2, CHRROM);
2755		prg32(machine(), data);
	2772	chr8(data >> 2, CHRROM);
	2773	prg32(data);
2756	2774	}
2757	2775
2758	2776	/*************************************************************
r18084	r18085
2772	2790	LOG_MMC(("dis_74x161x161x32_w, offset: %04x, data: %02x\n", offset, data));
2773	2791
2774	2792	if (!m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
2775		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
2776		chr8(machine(), data, CHRROM);
2777		prg16_89ab(machine(), data >> 4);
	2793	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	2794	chr8(data, CHRROM);
	2795	prg16_89ab(data >> 4);
2778	2796	}
2779	2797
2780	2798	/*************************************************************
r18084	r18085
2828	2846	{
2829	2847	case 0: case 1: case 2: case 3:
2830	2848	case 4: case 5: case 6: case 7:
2831		chr1_x(machine(), offset & 0x07, data, m_mmc_chr_source);
	2849	chr1_x(offset & 0x07, data, m_mmc_chr_source);
2832	2850	break;
2833	2851	case 8:
2834		prg16_89ab(machine(), data);
	2852	prg16_89ab(data);
2835	2853	break;
2836	2854	case 9:
2837	2855	switch (data & 0x03)
2838	2856	{
2839		case 0: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
2840		case 1: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
2841		case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
2842		case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	2857	case 0: set_nt_mirroring(PPU_MIRROR_VERT); break;
	2858	case 1: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	2859	case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
	2860	case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
2843	2861	}
2844	2862	break;
2845	2863	case 0x0a:
r18084	r18085
2878	2896	for (i = 0; i < 8; i++)
2879	2897	mmc_helper |= ((state->m_mmc_reg[i] & 0x01) << 4);
2880	2898
2881		prg16_89ab(machine, mmc_helper | state->m_mmc_latch1);
2882		prg16_cdef(machine, mmc_helper | 0x0f);
	2899	state->prg16_89ab(mmc_helper | state->m_mmc_latch1);
	2900	state->prg16_cdef(mmc_helper | 0x0f);
2883	2901	}
2884	2902
2885	2903	WRITE8_MEMBER(nes_carts_state::fjump2_w)
r18084	r18085
2919	2937	{
2920	2938	LOG_MMC(("bandai_ks_w, offset: %04x, data: %02x\n", offset, data));
2921	2939
2922		prg16_89ab(machine(), data ^ 0x08);
	2940	prg16_89ab(data ^ 0x08);
2923	2941	}
2924	2942
2925	2943	/*************************************************************
r18084	r18085
2940	2958	UINT8 mmc_helper;
2941	2959	LOG_MMC(("mapper96_w, offset: %04x, data: %02x\n", offset, data));
2942	2960
2943		prg32(machine(), data);
	2961	prg32(data);
2944	2962
2945	2963	m_mmc_latch1 = data;
2946	2964	mmc_helper = (m_mmc_latch1 & 0x03) | (data & 0x04);
2947		chr4_0(machine(), mmc_helper, CHRRAM);
2948		chr4_4(machine(), 0x03 | (data & 0x04), CHRRAM);
	2965	chr4_0(mmc_helper, CHRRAM);
	2966	chr4_4(0x03 | (data & 0x04), CHRRAM);
2949	2967	}
2950	2968
2951	2969	/*************************************************************
r18084	r18085
2962	2980	{
2963	2981	LOG_MMC(("lrog017_w, offset: %04x, data: %02x\n", offset, data));
2964	2982
2965		prg32(machine(), data);
2966		chr2_0(machine(), (data >> 4), CHRROM);
	2983	prg32(data);
	2984	chr2_0((data >> 4), CHRROM);
2967	2985	}
2968	2986
2969	2987	/*************************************************************
r18084	r18085
2978	2996	{
2979	2997	LOG_MMC(("irem_hd_w, offset: %04x, data: %02x\n", offset, data));
2980	2998
2981		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
2982		chr8(machine(), data >> 4, CHRROM);
2983		prg16_89ab(machine(), data);
	2999	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	3000	chr8(data >> 4, CHRROM);
	3001	prg16_89ab(data);
2984	3002	}
2985	3003
2986	3004	/*************************************************************
r18084	r18085
3001	3019
3002	3020	if (offset < 0x4000)
3003	3021	{
3004		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
3005		prg16_cdef(machine(), data);
	3022	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	3023	prg16_cdef(data);
3006	3024	}
3007	3025	}
3008	3026
r18084	r18085
3024	3042	{
3025	3043	case 0x0000:
3026	3044	// NEStopia here differs a little bit
3027		m_mmc_latch1 ? prg8_cd(machine(), data) : prg8_89(machine(), data);
	3045	m_mmc_latch1 ? prg8_cd(data) : prg8_89(data);
3028	3046	break;
3029	3047	case 0x1000:
3030	3048	m_mmc_latch1 = BIT(data, 1);
3031	3049	if (!m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
3032		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3050	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3033	3051	break;
3034	3052	case 0x2000:
3035		prg8_ab(machine(), data);
	3053	prg8_ab(data);
3036	3054	break;
3037	3055	case 0x3000:
3038		chr1_x(machine(), offset & 0x07, data, CHRROM);
	3056	chr1_x(offset & 0x07, data, CHRROM);
3039	3057	break;
3040	3058	}
3041	3059	}
r18084	r18085
3078	3096	switch (offset & 0x7fff)
3079	3097	{
3080	3098	case 0x0000:
3081		prg8_89(machine(), data);
	3099	prg8_89(data);
3082	3100	break;
3083	3101
3084	3102	case 0x1001:
3085		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3103	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3086	3104	break;
3087	3105
3088	3106	case 0x1003:
r18084	r18085
3102	3120	break;
3103	3121
3104	3122	case 0x2000:
3105		prg8_ab(machine(), data);
	3123	prg8_ab(data);
3106	3124	break;
3107	3125
3108	3126	case 0x3000: case 0x3001: case 0x3002: case 0x3003:
3109	3127	case 0x3004: case 0x3005: case 0x3006: case 0x3007:
3110		chr1_x(machine(), offset & 0x07, data, CHRROM);
	3128	chr1_x(offset & 0x07, data, CHRROM);
3111	3129	break;
3112	3130
3113	3131	case 0x4000:
3114		prg8_cd(machine(), data);
	3132	prg8_cd(data);
3115	3133	break;
3116	3134
3117	3135	default:
r18084	r18085
3192	3210	{
3193	3211	case 0x0000:
3194	3212	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0xf0) | (data & 0x0f);
3195		prg8_89(machine(), m_mmc_prg_bank[0]);
	3213	prg8_89(m_mmc_prg_bank[0]);
3196	3214	break;
3197	3215	case 0x0001:
3198	3216	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0x0f) | (data << 4);
3199		prg8_89(machine(), m_mmc_prg_bank[0]);
	3217	prg8_89(m_mmc_prg_bank[0]);
3200	3218	break;
3201	3219	case 0x0002:
3202	3220	m_mmc_prg_bank[1] = (m_mmc_prg_bank[1] & 0xf0) | (data & 0x0f);
3203		prg8_ab(machine(), m_mmc_prg_bank[1]);
	3221	prg8_ab(m_mmc_prg_bank[1]);
3204	3222	break;
3205	3223	case 0x0003:
3206	3224	m_mmc_prg_bank[1] = (m_mmc_prg_bank[1] & 0x0f) | (data << 4);
3207		prg8_ab(machine(), m_mmc_prg_bank[1]);
	3225	prg8_ab(m_mmc_prg_bank[1]);
3208	3226	break;
3209	3227	case 0x1000:
3210	3228	m_mmc_prg_bank[2] = (m_mmc_prg_bank[2] & 0xf0) | (data & 0x0f);
3211		prg8_cd(machine(), m_mmc_prg_bank[2]);
	3229	prg8_cd(m_mmc_prg_bank[2]);
3212	3230	break;
3213	3231	case 0x1001:
3214	3232	m_mmc_prg_bank[2] = (m_mmc_prg_bank[2] & 0x0f) | (data << 4);
3215		prg8_cd(machine(), m_mmc_prg_bank[2]);
	3233	prg8_cd(m_mmc_prg_bank[2]);
3216	3234	break;
3217	3235
3218	3236	/* $9002, 3 (1002, 3) uncaught = Jaleco Baseball writes 0 */
r18084	r18085
3228	3246	else
3229	3247	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
3230	3248
3231		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	3249	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
3232	3250	break;
3233	3251
3234	3252	case 0x6000:
r18084	r18085
3255	3273	case 0x7002:
3256	3274	switch (data & 0x03)
3257	3275	{
3258		case 0: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
3259		case 1: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
3260		case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
3261		case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	3276	case 0: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	3277	case 1: set_nt_mirroring(PPU_MIRROR_VERT); break;
	3278	case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
	3279	case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
3262	3280	}
3263	3281	break;
3264	3282
r18084	r18085
3283	3301	WRITE8_MEMBER(nes_carts_state::jf11_m_w)
3284	3302	{
3285	3303	LOG_MMC(("jf11_m_w, offset: %04x, data: %02x\n", offset, data));
3286		chr8(machine(), data, CHRROM);
3287		prg32(machine(), data >> 4);
	3304	chr8(data, CHRROM);
	3305	prg32(data >> 4);
3288	3306	}
3289	3307
3290	3308	/*************************************************************
r18084	r18085
3307	3325
3308	3326	if (offset == 0)
3309	3327	{
3310		prg32(machine(), (data >> 4) & 0x03);
3311		chr8(machine(), ((data >> 4) & 0x04) | (data & 0x03), CHRROM);
	3328	prg32((data >> 4) & 0x03);
	3329	chr8(((data >> 4) & 0x04) | (data & 0x03), CHRROM);
3312	3330	}
3313	3331
3314	3332	if (offset == 0x1000)
r18084	r18085
3334	3352	{
3335	3353	LOG_MMC(("jf16_w, offset: %04x, data: %02x\n", offset, data));
3336	3354
3337		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
3338		chr8(machine(), data >> 4, CHRROM);
3339		prg16_89ab(machine(), data);
	3355	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	3356	chr8(data >> 4, CHRROM);
	3357	prg16_89ab(data);
3340	3358	}
3341	3359
3342	3360	/*************************************************************
r18084	r18085
3359	3377	LOG_MMC(("jf17_w, offset: %04x, data: %02x\n", offset, data));
3360	3378
3361	3379	if (BIT(data, 7))
3362		prg16_89ab(machine(), data & 0x0f);
	3380	prg16_89ab(data & 0x0f);
3363	3381	if (BIT(data, 6))
3364		chr8(machine(), data & 0x0f, CHRROM);
	3382	chr8(data & 0x0f, CHRROM);
3365	3383	if (BIT(data, 5) && !BIT(data,4))
3366	3384	LOG_MMC(("Jaleco JF-17 sound write, data: %02x\n", data & 0x1f));
3367	3385	}
r18084	r18085
3385	3403	LOG_MMC(("jf19_w, offset: %04x, data: %02x\n", offset, data));
3386	3404
3387	3405	if (BIT(data, 7))
3388		prg16_cdef(machine(), data & 0x0f);
	3406	prg16_cdef(data & 0x0f);
3389	3407	if (BIT(data, 6))
3390		chr8(machine(), data & 0x0f, CHRROM);
	3408	chr8(data & 0x0f, CHRROM);
3391	3409	if (BIT(data, 5) && !BIT(data,4))
3392	3410	LOG_MMC(("Jaleco JF-19 sound write, data: %02x\n", data & 0x1f));
3393	3411	}
r18084	r18085
3411	3429	switch (offset & 0x7000)
3412	3430	{
3413	3431	case 0x0000:
3414		prg8_89(machine(), data);
	3432	prg8_89(data);
3415	3433	break;
3416	3434	case 0x1000:
3417		set_nt_mirroring(machine(), (data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	3435	set_nt_mirroring((data & 0x01) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
3418	3436	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & 0x0f) | ((data & 0x02) << 3);
3419	3437	m_mmc_vrom_bank[1] = (m_mmc_vrom_bank[1] & 0x0f) | ((data & 0x04) << 2);
3420		chr4_0(machine(), m_mmc_vrom_bank[0], CHRROM);
3421		chr4_4(machine(), m_mmc_vrom_bank[1], CHRROM);
	3438	chr4_0(m_mmc_vrom_bank[0], CHRROM);
	3439	chr4_4(m_mmc_vrom_bank[1], CHRROM);
3422	3440	break;
3423	3441	case 0x2000:
3424		prg8_ab(machine(), data);
	3442	prg8_ab(data);
3425	3443	break;
3426	3444	case 0x4000:
3427		prg8_cd(machine(), data);
	3445	prg8_cd(data);
3428	3446	break;
3429	3447	case 0x6000:
3430	3448	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & 0x10) | (data & 0x0f);
3431		chr4_0(machine(), m_mmc_vrom_bank[0], CHRROM);
	3449	chr4_0(m_mmc_vrom_bank[0], CHRROM);
3432	3450	break;
3433	3451	case 0x7000:
3434	3452	m_mmc_vrom_bank[1] = (m_mmc_vrom_bank[1] & 0x10) | (data & 0x0f);
3435		chr4_4(machine(), m_mmc_vrom_bank[1], CHRROM);
	3453	chr4_4(m_mmc_vrom_bank[1], CHRROM);
3436	3454	break;
3437	3455	}
3438	3456	}
r18084	r18085
3454	3472	LOG_MMC(("konami_vrc2_w, offset: %04x, data: %02x\n", offset, data));
3455	3473
3456	3474	if (offset < 0x1000)
3457		prg8_89(machine(), data);
	3475	prg8_89(data);
3458	3476	else if (offset < 0x2000)
3459	3477	{
3460	3478	switch (data & 0x03)
3461	3479	{
3462		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
3463		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
3464		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
3465		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	3480	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	3481	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	3482	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	3483	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
3466	3484	}
3467	3485	}
3468	3486	else if (offset < 0x3000)
3469		prg8_ab(machine(), data);
	3487	prg8_ab(data);
3470	3488	else if (offset < 0x7000)
3471	3489	{
3472	3490	bank = ((shifted_offs & 0x7000) - 0x3000) / 0x0800 + BIT(shifted_offs, 9);
r18084	r18085
3474	3492	mask = (0xf0 >> shift);
3475	3493	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & mask)
3476	3494	| (((data >> m_vrc_ls_chr) & 0x0f) << shift);
3477		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	3495	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
3478	3496	}
3479	3497	else
3480	3498	logerror("konami_vrc2_w uncaught write, addr: %04x value: %02x\n", offset + 0x8000, data);
r18084	r18085
3516	3534	m_IRQ_count |= (data & 0x0f) << 4;
3517	3535	break;
3518	3536	case 0x7000:
3519		prg16_89ab(machine(), data);
	3537	prg16_89ab(data);
3520	3538	break;
3521	3539	default:
3522	3540	logerror("konami_vrc3_w uncaught write, offset %04x, data: %02x\n", offset, data);
r18084	r18085
3537	3555	nes_state *state = machine.driver_data<nes_state>();
3538	3556	if (state->m_mmc_latch1 & 0x02)
3539	3557	{
3540		prg8_89(machine, 0xfe);
3541		prg8_cd(machine, state->m_mmc_prg_bank[0]);
	3558	state->prg8_89(0xfe);
	3559	state->prg8_cd(state->m_mmc_prg_bank[0]);
3542	3560	}
3543	3561	else
3544	3562	{
3545		prg8_89(machine, state->m_mmc_prg_bank[0]);
3546		prg8_cd(machine, 0xfe);
	3563	state->prg8_89(state->m_mmc_prg_bank[0]);
	3564	state->prg8_cd(0xfe);
3547	3565	}
3548	3566	}
3549	3567
r18084	r18085
3573	3591	vrc4_set_prg(machine());
3574	3592	}
3575	3593	else if (offset >= 0x2000 && offset < 0x3000)
3576		prg8_ab(machine(), data);
	3594	prg8_ab(data);
3577	3595	else
3578	3596	{
3579	3597	switch (shifted_offs & 0x7300)
r18084	r18085
3582	3600	case 0x1100:
3583	3601	switch (data & 0x03)
3584	3602	{
3585		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
3586		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
3587		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
3588		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	3603	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	3604	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	3605	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	3606	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
3589	3607	}
3590	3608	break;
3591	3609	case 0x1200:
r18084	r18085
3613	3631	shift = BIT(shifted_offs, 8) * 4;
3614	3632	mask = (0xf0 >> shift);
3615	3633	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & mask) | ((data & 0x0f) << shift);
3616		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	3634	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
3617	3635	break;
3618	3636	case 0x7000:
3619	3637	m_IRQ_count_latch = (m_IRQ_count_latch & 0xf0) | (data & 0x0f);
r18084	r18085
3656	3674	LOG_MMC(("konami_vrc6_w, offset: %04x, data: %02x\n", offset, data));
3657	3675
3658	3676	if (offset < 0x1000)
3659		prg16_89ab(machine(), data);
	3677	prg16_89ab(data);
3660	3678	else if (offset >= 0x4000 && offset < 0x5000)
3661		prg8_cd(machine(), data);
	3679	prg8_cd(data);
3662	3680	else
3663	3681	{
3664	3682	switch (shifted_offs & 0x7300)
r18084	r18085
3677	3695	case 0x3300:
3678	3696	switch (data & 0x0c)
3679	3697	{
3680		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
3681		case 0x04: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
3682		case 0x08: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
3683		case 0x0c: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	3698	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	3699	case 0x04: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	3700	case 0x08: set_nt_mirroring(PPU_MIRROR_LOW); break;
	3701	case 0x0c: set_nt_mirroring(PPU_MIRROR_HIGH); break;
3684	3702	}
3685	3703	break;
3686	3704	case 0x5000:
r18084	r18085
3692	3710	case 0x6200:
3693	3711	case 0x6300:
3694	3712	bank = ((shifted_offs & 0x7000) - 0x5000) / 0x0400 + ((shifted_offs & 0x0300) >> 8);
3695		chr1_x(machine(), bank, data, CHRROM);
	3713	chr1_x(bank, data, CHRROM);
3696	3714	break;
3697	3715	case 0x7000:
3698	3716	m_IRQ_count_latch = data;
r18084	r18085
3734	3752	switch (offset & 0x7018)
3735	3753	{
3736	3754	case 0x0000:
3737		prg8_89(machine(), data);
	3755	prg8_89(data);
3738	3756	break;
3739	3757	case 0x0008:
3740	3758	case 0x0010:
3741	3759	case 0x0018:
3742		prg8_ab(machine(), data);
	3760	prg8_ab(data);
3743	3761	break;
3744	3762
3745	3763	case 0x1000:
3746		prg8_cd(machine(), data);
	3764	prg8_cd(data);
3747	3765	break;
3748	3766
3749	3767	/* TODO: there are sound regs in here */
r18084	r18085
3765	3783	case 0x5010:
3766	3784	case 0x5018:
3767	3785	bank = ((offset & 0x7000) - 0x2000) / 0x0800 + ((offset & 0x0018) ? 1 : 0);
3768		chr1_x(machine(), bank, data, m_mmc_chr_source);
	3786	chr1_x(bank, data, m_mmc_chr_source);
3769	3787	break;
3770	3788
3771	3789	case 0x6000:
3772	3790	switch (data & 0x03)
3773	3791	{
3774		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
3775		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
3776		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
3777		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	3792	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	3793	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	3794	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	3795	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
3778	3796	}
3779	3797	break;
3780	3798	case 0x6008: case 0x6010: case 0x6018:
r18084	r18085
3869	3887
3870	3888	static void namcot163_set_mirror( running_machine &machine, UINT8 page, UINT8 data )
3871	3889	{
	3890	nes_state *state = machine.driver_data<nes_state>();
3872	3891	if (!(data < 0xe0))
3873		set_nt_page(machine, page, CIRAM, data & 0x01, 1);
	3892	state->set_nt_page(page, CIRAM, data & 0x01, 1);
3874	3893	else
3875		set_nt_page(machine, page, ROM, data, 0);
	3894	state->set_nt_page(page, ROM, data, 0);
3876	3895	}
3877	3896
3878	3897	WRITE8_MEMBER(nes_carts_state::namcot163_w)
r18084	r18085
3884	3903	case 0x1000: case 0x1800:
3885	3904	case 0x2000: case 0x2800:
3886	3905	case 0x3000: case 0x3800:
3887		chr1_x(machine(), offset / 0x800, data, CHRROM);
	3906	chr1_x(offset / 0x800, data, CHRROM);
3888	3907	break;
3889	3908	case 0x4000:
3890	3909	namcot163_set_mirror(machine(), 0, data);
r18084	r18085
3899	3918	namcot163_set_mirror(machine(), 3, data);
3900	3919	break;
3901	3920	case 0x6000:
3902		prg8_89(machine(), data & 0x3f);
	3921	prg8_89(data & 0x3f);
3903	3922	break;
3904	3923	case 0x6800:
3905	3924	m_mmc_latch1 = data & 0xc0;      // this should enable High CHRRAM, but we still have to properly implement it!
3906		prg8_ab(machine(), data & 0x3f);
	3925	prg8_ab(data & 0x3f);
3907	3926	break;
3908	3927	case 0x7000:
3909		prg8_cd(machine(), data & 0x3f);
	3928	prg8_cd(data & 0x3f);
3910	3929	break;
3911	3930	case 0x7800:
3912	3931	LOG_MMC(("Namcot-163 sound address write, data: %02x\n", data));
r18084	r18085
3932	3951
3933	3952	if (m_chr_chunks)
3934	3953	{
3935		chr4_0(machine(), data & 0x0f, CHRROM);
3936		chr4_4(machine(), data >> 4, CHRROM);
	3954	chr4_0(data & 0x0f, CHRROM);
	3955	chr4_4(data >> 4, CHRROM);
3937	3956	}
3938	3957	else
3939		prg16_89ab(machine(), data & 0x0f);
	3958	prg16_89ab(data & 0x0f);
3940	3959	}
3941	3960
3942	3961	/*************************************************************
r18084	r18085
3956	3975	LOG_MMC(("sunsoft2_w, offset: %04x, data: %02x\n", offset, data));
3957	3976
3958	3977	if (!m_hard_mirroring)   // there are two 'variants' depending on hardwired or mapper ctrl mirroring
3959		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	3978	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
3960	3979	if (m_chr_chunks)
3961		chr8(machine(), sunsoft_helper, CHRROM);
	3980	chr8(sunsoft_helper, CHRROM);
3962	3981
3963		prg16_89ab(machine(), data >> 4);
	3982	prg16_89ab(data >> 4);
3964	3983	}
3965	3984
3966	3985	/*************************************************************
r18084	r18085
4003	4022	switch (offset & 0x7800)
4004	4023	{
4005	4024	case 0x0800:
4006		chr2_0(machine(), data, CHRROM);
	4025	chr2_0(data, CHRROM);
4007	4026	break;
4008	4027	case 0x1800:
4009		chr2_2(machine(), data, CHRROM);
	4028	chr2_2(data, CHRROM);
4010	4029	break;
4011	4030	case 0x2800:
4012		chr2_4(machine(), data, CHRROM);
	4031	chr2_4(data, CHRROM);
4013	4032	break;
4014	4033	case 0x3800:
4015		chr2_6(machine(), data, CHRROM);
	4034	chr2_6(data, CHRROM);
4016	4035	break;
4017	4036	case 0x4000:
4018	4037	case 0x4800:
r18084	r18085
4029	4048	case 0x6800:
4030	4049	switch (data & 3)
4031	4050	{
4032		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
4033		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
4034		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
4035		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	4051	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	4052	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	4053	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	4054	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
4036	4055	}
4037	4056	break;
4038	4057	case 0x7800:
4039		prg16_89ab(machine(), data);
	4058	prg16_89ab(data);
4040	4059	break;
4041	4060	default:
4042	4061	LOG_MMC(("sunsoft3_w uncaught write, offset: %04x, data: %02x\n", offset, data));
r18084	r18085
4065	4084	switch (offset & 0x7003)
4066	4085	{
4067	4086	case 0x0000:
4068		set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4069		prg8_89(machine(), data);
	4087	set_nt_mirroring(BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4088	prg8_89(data);
4070	4089	break;
4071	4090	case 0x0001:
4072		prg8_ab(machine(), data);
	4091	prg8_ab(data);
4073	4092	break;
4074	4093	case 0x0002:
4075		chr2_0(machine(), data, CHRROM);
	4094	chr2_0(data, CHRROM);
4076	4095	break;
4077	4096	case 0x0003:
4078		chr2_2(machine(), data, CHRROM);
	4097	chr2_2(data, CHRROM);
4079	4098	break;
4080	4099	case 0x2000:
4081		chr1_4(machine(), data, CHRROM);
	4100	chr1_4(data, CHRROM);
4082	4101	break;
4083	4102	case 0x2001:
4084		chr1_5(machine(), data, CHRROM);
	4103	chr1_5(data, CHRROM);
4085	4104	break;
4086	4105	case 0x2002:
4087		chr1_6(machine(), data, CHRROM);
	4106	chr1_6(data, CHRROM);
4088	4107	break;
4089	4108	case 0x2003:
4090		chr1_7(machine(), data, CHRROM);
	4109	chr1_7(data, CHRROM);
4091	4110	break;
4092	4111	}
4093	4112	}
r18084	r18085
4118	4137	switch (offset & 0x7003)
4119	4138	{
4120	4139	case 0x0000:
4121		prg8_89(machine(), data);
	4140	prg8_89(data);
4122	4141	break;
4123	4142	case 0x0001:
4124	4143	case 0x0002:
r18084	r18085
4142	4161	m_IRQ_enable = 0;
4143	4162	break;
4144	4163	case 0x6000:
4145		set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4164	set_nt_mirroring(BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4146	4165	break;
4147	4166	}
4148	4167	}
r18084	r18085
4168	4187	switch (offset)
4169	4188	{
4170	4189	case 0x1ef0:
4171		chr2_0(machine(), (data & 0x7f) >> 1, CHRROM);
	4190	chr2_0((data & 0x7f) >> 1, CHRROM);
4172	4191	break;
4173	4192	case 0x1ef1:
4174		chr2_2(machine(), (data & 0x7f) >> 1, CHRROM);
	4193	chr2_2((data & 0x7f) >> 1, CHRROM);
4175	4194	break;
4176	4195	case 0x1ef2:
4177		chr1_4(machine(), data, CHRROM);
	4196	chr1_4(data, CHRROM);
4178	4197	break;
4179	4198	case 0x1ef3:
4180		chr1_5(machine(), data, CHRROM);
	4199	chr1_5(data, CHRROM);
4181	4200	break;
4182	4201	case 0x1ef4:
4183		chr1_6(machine(), data, CHRROM);
	4202	chr1_6(data, CHRROM);
4184	4203	break;
4185	4204	case 0x1ef5:
4186		chr1_7(machine(), data, CHRROM);
	4205	chr1_7(data, CHRROM);
4187	4206	break;
4188	4207	case 0x1ef6:
4189	4208	case 0x1ef7:
4190		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4209	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4191	4210	break;
4192	4211	case 0x1ef8:
4193	4212	case 0x1ef9:
r18084	r18085
4195	4214	break;
4196	4215	case 0x1efa:
4197	4216	case 0x1efb:
4198		prg8_89(machine(), data);
	4217	prg8_89(data);
4199	4218	break;
4200	4219	case 0x1efc:
4201	4220	case 0x1efd:
4202		prg8_ab(machine(), data);
	4221	prg8_ab(data);
4203	4222	break;
4204	4223	case 0x1efe:
4205	4224	case 0x1eff:
4206		prg8_cd(machine(), data);
	4225	prg8_cd(data);
4207	4226	break;
4208	4227	default:
4209	4228	logerror("mapper80_m_w uncaught addr: %04x, value: %02x\n", offset + 0x6000, data);
r18084	r18085
4239	4258	switch (offset)
4240	4259	{
4241	4260	case 0x1ef0:
4242		set_nt_page(machine(), 0, CIRAM, (data & 0x80) ? 1 : 0, 1);
4243		set_nt_page(machine(), 1, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4261	set_nt_page(0, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4262	set_nt_page(1, CIRAM, (data & 0x80) ? 1 : 0, 1);
4244	4263	break;
4245	4264	case 0x1ef1:
4246		set_nt_page(machine(), 2, CIRAM, (data & 0x80) ? 1 : 0, 1);
4247		set_nt_page(machine(), 3, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4265	set_nt_page(2, CIRAM, (data & 0x80) ? 1 : 0, 1);
	4266	set_nt_page(3, CIRAM, (data & 0x80) ? 1 : 0, 1);
4248	4267	break;
4249	4268	}
4250	4269
r18084	r18085
4272	4291	nes_state *state = machine.driver_data<nes_state>();
4273	4292	if (state->m_mmc_latch1)
4274	4293	{
4275		chr2_4(machine, state->m_mmc_vrom_bank[0] >> 1, CHRROM);
4276		chr2_6(machine, state->m_mmc_vrom_bank[1] >> 1, CHRROM);
	4294	state->chr2_4(state->m_mmc_vrom_bank[0] >> 1, CHRROM);
	4295	state->chr2_6(state->m_mmc_vrom_bank[1] >> 1, CHRROM);
4277	4296	}
4278	4297	else
4279	4298	{
4280		chr2_0(machine, state->m_mmc_vrom_bank[0] >> 1, CHRROM);
4281		chr2_2(machine, state->m_mmc_vrom_bank[1] >> 1, CHRROM);
	4299	state->chr2_0(state->m_mmc_vrom_bank[0] >> 1, CHRROM);
	4300	state->chr2_2(state->m_mmc_vrom_bank[1] >> 1, CHRROM);
4282	4301	}
4283		chr1_x(machine, 4 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[2], CHRROM);
4284		chr1_x(machine, 5 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[3], CHRROM);
4285		chr1_x(machine, 6 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[4], CHRROM);
4286		chr1_x(machine, 7 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[5], CHRROM);
	4302	state->chr1_x(4 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[2], CHRROM);
	4303	state->chr1_x(5 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[3], CHRROM);
	4304	state->chr1_x(6 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[4], CHRROM);
	4305	state->chr1_x(7 ^ state->m_mmc_latch1, state->m_mmc_vrom_bank[5], CHRROM);
4287	4306	}
4288	4307
4289	4308	WRITE8_MEMBER(nes_carts_state::x1017_m_w)
r18084	r18085
4312	4331	}
4313	4332	break;
4314	4333	case 0x1ef6:
4315		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	4334	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
4316	4335	m_mmc_latch1 = ((data & 0x02) << 1);
4317	4336	x1017_set_chr(machine());
4318	4337	break;
r18084	r18085
4322	4341	m_mmc_reg[(offset & 0x0f) - 7] = data;
4323	4342	break;
4324	4343	case 0x1efa:
4325		prg8_89(machine(), data >> 2);
	4344	prg8_89(data >> 2);
4326	4345	break;
4327	4346	case 0x1efb:
4328		prg8_ab(machine(), data >> 2);
	4347	prg8_ab(data >> 2);
4329	4348	break;
4330	4349	case 0x1efc:
4331		prg8_cd(machine(), data >> 2);
	4350	prg8_cd(data >> 2);
4332	4351	break;
4333	4352	default:
4334	4353	logerror("x1017_m_w uncaught write, addr: %04x, value: %02x\n", offset + 0x6000, data);
r18084	r18085
4376	4395	offset += 0x8000;
4377	4396	data |= (space.read_byte(offset) & 1);
4378	4397
4379		chr8(machine(), data >> 4, CHRROM);
4380		prg32(machine(), data);
	4398	chr8(data >> 4, CHRROM);
	4399	prg32(data);
4381	4400	}
4382	4401
4383	4402	/*************************************************************
r18084	r18085
4395	4414	switch (offset)
4396	4415	{
4397	4416	case 0x1ffd:
4398		prg32(machine(), data);
	4417	prg32(data);
4399	4418	break;
4400	4419	case 0x1ffe:
4401		chr4_0(machine(), data, CHRROM);
	4420	chr4_0(data, CHRROM);
4402	4421	break;
4403	4422	case 0x1fff:
4404		chr4_4(machine(), data, CHRROM);
	4423	chr4_4(data, CHRROM);
4405	4424	break;
4406	4425	}
4407	4426	}
r18084	r18085
4425	4444
4426	4445	if (!(offset & 0x0100))
4427	4446	{
4428		prg32(machine(), data >> 3);
4429		chr8(machine(), data, CHRROM);
	4447	prg32(data >> 3);
	4448	chr8(data, CHRROM);
4430	4449	}
4431	4450	}
4432	4451
r18084	r18085
4444	4463	UINT8 pmode;
4445	4464	LOG_MMC(("ae_act52_w, offset: %04x, data: %02x\n", offset, data));
4446	4465
4447		set_nt_mirroring(machine(), BIT(offset, 13) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4466	set_nt_mirroring(BIT(offset, 13) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4448	4467
4449	4468	cbank = (data & 0x03) | ((offset & 0x0f) << 2);
4450		chr8(machine(), cbank, CHRROM);
	4469	chr8(cbank, CHRROM);
4451	4470
4452	4471	pmode = offset & 0x20;
4453	4472	pbank = (offset & 0x1fc0) >> 6;
4454	4473	if (pmode)
4455	4474	{
4456		prg16_89ab(machine(), pbank);
4457		prg16_cdef(machine(), pbank);
	4475	prg16_89ab(pbank);
	4476	prg16_cdef(pbank);
4458	4477	}
4459	4478	else
4460		prg32(machine(), pbank >> 1);
	4479	prg32(pbank >> 1);
4461	4480	}
4462	4481
4463	4482
r18084	r18085
4484	4503	return;
4485	4504	if (offset < 0x00a5)
4486	4505	{
4487		prg32(machine(), (offset - 0x0065) & 0x03);
	4506	prg32((offset - 0x0065) & 0x03);
4488	4507	return;
4489	4508	}
4490	4509	if (offset < 0x00e5)
4491	4510	{
4492		chr8(machine(), (offset - 0x00a5) & 0x07, CHRROM);
	4511	chr8((offset - 0x00a5) & 0x07, CHRROM);
4493	4512	}
4494	4513	}
4495	4514
r18084	r18085
4519	4538	switch (offset & 0x0007)
4520	4539	{
4521	4540	case 0x0000:
4522		prg8_89(machine(), data);
	4541	prg8_89(data);
4523	4542	break;
4524	4543	case 0x0001:
4525		prg8_ab(machine(), data);
	4544	prg8_ab(data);
4526	4545	break;
4527	4546	case 0x0002:
4528		prg8_cd(machine(), data);
	4547	prg8_cd(data);
4529	4548	break;
4530	4549	case 0x0003:
4531		prg8_ef(machine(), data);
	4550	prg8_ef(data);
4532	4551	break;
4533	4552	case 0x0004:
4534		chr2_0(machine(), data, CHRROM);
	4553	chr2_0(data, CHRROM);
4535	4554	break;
4536	4555	case 0x0005:
4537		chr2_2(machine(), data, CHRROM);
	4556	chr2_2(data, CHRROM);
4538	4557	break;
4539	4558	case 0x0006:
4540		chr2_4(machine(), data, CHRROM);
	4559	chr2_4(data, CHRROM);
4541	4560	break;
4542	4561	case 0x0007:
4543		chr2_6(machine(), data, CHRROM);
	4562	chr2_6(data, CHRROM);
4544	4563	break;
4545	4564	}
4546	4565	}
r18084	r18085
4569	4588	{
4570	4589	LOG_MMC(("cne_shlz_l_w, offset: %04x, data: %02x\n", offset, data));
4571	4590
4572		prg32(machine(), data >> 4);
4573		chr8(machine(), data & 0x0f, CHRROM);
	4591	prg32(data >> 4);
	4592	chr8(data & 0x0f, CHRROM);
4574	4593	}
4575	4594
4576	4595	/*************************************************************
r18084	r18085
4590	4609	LOG_MMC(("caltron6in1_m_w, offset: %04x, data: %02x\n", offset, data));
4591	4610
4592	4611	m_mmc_latch1 = offset & 0xff;
4593		set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
4594		prg32(machine(), offset & 0x07);
	4612	set_nt_mirroring(BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	4613	prg32(offset & 0x07);
4595	4614	}
4596	4615
4597	4616	WRITE8_MEMBER(nes_carts_state::caltron6in1_w)
r18084	r18085
4599	4618	LOG_MMC(("caltron6in1_w, offset: %04x, data: %02x\n", offset, data));
4600	4619
4601	4620	if (m_mmc_latch1 & 0x04)
4602		chr8(machine(), ((m_mmc_latch1 & 0x18) >> 1) | (data & 0x03), CHRROM);
	4621	chr8(((m_mmc_latch1 & 0x18) >> 1) | (data & 0x03), CHRROM);
4603	4622	}
4604	4623
4605	4624	/*************************************************************
r18084	r18085
4628	4647	case 0x0000:
4629	4648	case 0x1000:
4630	4649	if (!m_hard_mirroring)
4631		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	4650	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
4632	4651	break;
4633	4652	case 0x4000:
4634	4653	case 0x5000:
4635	4654	case 0x6000:
4636	4655	case 0x7000:
4637		prg16_89ab(machine(), data);
	4656	prg16_89ab(data);
4638	4657	break;
4639	4658	}
4640	4659	}
r18084	r18085
4660	4679	static void bf9096_set_prg( running_machine &machine )
4661	4680	{
4662	4681	nes_state *state = machine.driver_data<nes_state>();
4663		prg16_89ab(machine, (state->m_mmc_latch2 & 0x03) | ((state->m_mmc_latch1 & 0x18) >> 1));
4664		prg16_cdef(machine, 0x03 | ((state->m_mmc_latch1 & 0x18) >> 1));
	4682	state->prg16_89ab((state->m_mmc_latch2 & 0x03) | ((state->m_mmc_latch1 & 0x18) >> 1));
	4683	state->prg16_cdef(0x03 | ((state->m_mmc_latch1 & 0x18) >> 1));
4665	4684	}
4666	4685
4667	4686	WRITE8_MEMBER(nes_carts_state::bf9096_w)
r18084	r18085
4697	4716	if (data & 0x08)
4698	4717	{
4699	4718	m_mmc_prg_bank[0] = ((data & 0x07) << 4) | (m_mmc_prg_bank[0] & 0x0f);
4700		prg16_89ab(machine(), m_mmc_prg_bank[0]);
4701		prg16_cdef(machine(), ((data & 0x07) << 4) | 0x0f);
	4719	prg16_89ab(m_mmc_prg_bank[0]);
	4720	prg16_cdef(((data & 0x07) << 4) | 0x0f);
4702	4721	}
4703	4722
4704	4723	}
4705	4724	else
4706	4725	{
4707	4726	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0x70) | (data & 0x0f);
4708		prg16_89ab(machine(), m_mmc_prg_bank[0]);
	4727	prg16_89ab(m_mmc_prg_bank[0]);
4709	4728	}
4710	4729	}
4711	4730
r18084	r18085
4747	4766	static void cony_set_prg( running_machine &machine )
4748	4767	{
4749	4768	nes_state *state = machine.driver_data<nes_state>();
4750		prg16_89ab(machine, state->m_mapper83_reg[8] & 0x3f);
4751		prg16_cdef(machine, (state->m_mapper83_reg[8] & 0x30) | 0x0f);
	4769	state->prg16_89ab(state->m_mapper83_reg[8] & 0x3f);
	4770	state->prg16_cdef((state->m_mapper83_reg[8] & 0x30) | 0x0f);
4752	4771	}
4753	4772
4754	4773	static void cony_set_chr( running_machine &machine )
r18084	r18085
4761	4780	// we should split them and possibly document the proper behavior of each variant
4762	4781	if (state->m_mmc_latch1 && !state->m_mmc_latch2)
4763	4782	{
4764		chr2_0(machine, state->m_mapper83_reg[0], CHRROM);
4765		chr2_2(machine, state->m_mapper83_reg[1], CHRROM);
4766		chr2_4(machine, state->m_mapper83_reg[6], CHRROM);
4767		chr2_6(machine, state->m_mapper83_reg[7], CHRROM);
	4783	state->chr2_0(state->m_mapper83_reg[0], CHRROM);
	4784	state->chr2_2(state->m_mapper83_reg[1], CHRROM);
	4785	state->chr2_4(state->m_mapper83_reg[6], CHRROM);
	4786	state->chr2_6(state->m_mapper83_reg[7], CHRROM);
4768	4787	}
4769	4788	else
4770	4789	{
4771		chr1_0(machine, state->m_mapper83_reg[0] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4772		chr1_1(machine, state->m_mapper83_reg[1] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4773		chr1_2(machine, state->m_mapper83_reg[2] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4774		chr1_3(machine, state->m_mapper83_reg[3] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4775		chr1_4(machine, state->m_mapper83_reg[4] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4776		chr1_5(machine, state->m_mapper83_reg[5] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4777		chr1_6(machine, state->m_mapper83_reg[6] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4778		chr1_7(machine, state->m_mapper83_reg[7] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4790	state->chr1_0(state->m_mapper83_reg[0] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4791	state->chr1_1(state->m_mapper83_reg[1] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4792	state->chr1_2(state->m_mapper83_reg[2] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4793	state->chr1_3(state->m_mapper83_reg[3] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4794	state->chr1_4(state->m_mapper83_reg[4] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4795	state->chr1_5(state->m_mapper83_reg[5] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4796	state->chr1_6(state->m_mapper83_reg[6] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
	4797	state->chr1_7(state->m_mapper83_reg[7] | ((state->m_mapper83_reg[8] & 0x30) << 4), CHRROM);
4779	4798	}
4780	4799	}
4781	4800
r18084	r18085
4799	4818	switch (data & 0x03)
4800	4819	{
4801	4820	case 0:
4802		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	4821	set_nt_mirroring(PPU_MIRROR_VERT);
4803	4822	break;
4804	4823	case 1:
4805		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	4824	set_nt_mirroring(PPU_MIRROR_HORZ);
4806	4825	break;
4807	4826	case 2:
4808		set_nt_mirroring(machine(), PPU_MIRROR_LOW);
	4827	set_nt_mirroring(PPU_MIRROR_LOW);
4809	4828	break;
4810	4829	case 3:
4811		set_nt_mirroring(machine(), PPU_MIRROR_HIGH);
	4830	set_nt_mirroring(PPU_MIRROR_HIGH);
4812	4831	break;
4813	4832	}
4814	4833	break;
r18084	r18085
4820	4839	m_IRQ_count = (data << 8) | (m_IRQ_count & 0xff);
4821	4840	break;
4822	4841	case 0x0300:
4823		prg8_89(machine(), data);
	4842	prg8_89(data);
4824	4843	break;
4825	4844	case 0x0301:
4826		prg8_ab(machine(), data);
	4845	prg8_ab(data);
4827	4846	break;
4828	4847	case 0x0302:
4829		prg8_cd(machine(), data);
	4848	prg8_cd(data);
4830	4849	break;
4831	4850	case 0x0312:
4832	4851	case 0x0313:
r18084	r18085
4888	4907	if (state->m_mmc_reg[0] & 0x10)
4889	4908	{
4890	4909	int base = (state->m_mmc_reg[1] & 0x08) << 1;
4891		prg8_89(machine, base | (state->m_mapper83_reg[0] & 0x0f));
4892		prg8_ab(machine, base | (state->m_mapper83_reg[1] & 0x0f));
4893		prg8_cd(machine, base | (state->m_mapper83_reg[2] & 0x0f));
4894		prg8_ef(machine, base | 0x0f);
	4910	state->prg8_89(base | (state->m_mapper83_reg[0] & 0x0f));
	4911	state->prg8_ab(base | (state->m_mapper83_reg[1] & 0x0f));
	4912	state->prg8_cd(base | (state->m_mapper83_reg[2] & 0x0f));
	4913	state->prg8_ef(base | 0x0f);
4895	4914	}
4896	4915	else if (state->m_mmc_reg[0] & 0x08)
4897		prg32(machine, state->m_mmc_reg[1] >> 1);
	4916	state->prg32(state->m_mmc_reg[1] >> 1);
4898	4917	else
4899	4918	{
4900		prg16_89ab(machine, state->m_mmc_reg[1]);
4901		prg16_cdef(machine, 0xff);
	4919	state->prg16_89ab(state->m_mmc_reg[1]);
	4920	state->prg16_cdef(0xff);
4902	4921	}
4903	4922	}
4904	4923
4905	4924	static void yoko_set_chr( running_machine &machine )
4906	4925	{
4907	4926	nes_state *state = machine.driver_data<nes_state>();
4908		chr2_0(machine, state->m_mapper83_reg[4], CHRROM);
4909		chr2_2(machine, state->m_mapper83_reg[5], CHRROM);
4910		chr2_4(machine, state->m_mapper83_reg[6], CHRROM);
4911		chr2_6(machine, state->m_mapper83_reg[7], CHRROM);
	4927	state->chr2_0(state->m_mapper83_reg[4], CHRROM);
	4928	state->chr2_2(state->m_mapper83_reg[5], CHRROM);
	4929	state->chr2_4(state->m_mapper83_reg[6], CHRROM);
	4930	state->chr2_6(state->m_mapper83_reg[7], CHRROM);
4912	4931	}
4913	4932
4914	4933	WRITE8_MEMBER(nes_carts_state::yoko_w)
r18084	r18085
4924	4943	case 0x400:
4925	4944	m_mmc_reg[0] = data;
4926	4945	if (data & 1)
4927		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	4946	set_nt_mirroring(PPU_MIRROR_HORZ);
4928	4947	else
4929		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	4948	set_nt_mirroring(PPU_MIRROR_VERT);
4930	4949	yoko_set_prg(machine());
4931	4950	break;
4932	4951	case 0x0800:
r18084	r18085
4968	4987	offset += 0x100;
4969	4988
4970	4989	if (offset == 0x1020)   /* 0x5020 */
4971		prg16_89ab(machine(), data);
	4990	prg16_89ab(data);
4972	4991	}
4973	4992
4974	4993	/*************************************************************
r18084	r18085
4992	5011	if (offset >= 0x200 && offset < 0x400)
4993	5012	{
4994	5013	if (offset & 1)
4995		prg16_89ab(machine(), data);
	5014	prg16_89ab(data);
4996	5015	else
4997		wram_bank(machine(), data >> 6, NES_WRAM);
	5016	wram_bank(data >> 6, NES_WRAM);
4998	5017	}
4999	5018	else if (offset >= 0x400 && offset < 0xf00)
5000	5019	m_mapper_ram[offset - 0x400] = data;
r18084	r18085
5053	5072	switch (offset)
5054	5073	{
5055	5074	case 0x0000:
5056		prg8_89(machine(), data);
	5075	prg8_89(data);
5057	5076	break;
5058	5077	case 0x0001:
5059		prg8_ab(machine(), data);
	5078	prg8_ab(data);
5060	5079	break;
5061	5080	case 0x0002:
5062		prg8_cd(machine(), data);
	5081	prg8_cd(data);
5063	5082	break;
5064	5083	case 0x0003:
5065		prg8_ef(machine(), data);
	5084	prg8_ef(data);
5066	5085	break;
5067	5086	case 0x2000:
5068	5087	case 0x2001:
r18084	r18085
5072	5091	case 0x2005:
5073	5092	case 0x2006:
5074	5093	case 0x2007:
5075		chr1_x(machine(), offset & 0x07, data, CHRROM);
	5094	chr1_x(offset & 0x07, data, CHRROM);
5076	5095	break;
5077	5096
5078	5097	case 0x5000:
5079		set_nt_mirroring(machine(), BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5098	set_nt_mirroring(BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5080	5099	break;
5081	5100
5082	5101	case 0x4001:
r18084	r18085
5137	5156	else if (!(offset < 0xf00))
5138	5157	m_mmc_reg[4] = data;
5139	5158	else if (!(offset < 0x700))
5140		prg32(machine(), ((data >> 3) & 0x02) | (data & 0x01));
	5159	prg32(((data >> 3) & 0x02) | (data & 0x01));
5141	5160	}
5142	5161
5143	5162	READ8_MEMBER(nes_carts_state::gouder_sf4_l_r)
r18084	r18085
5177	5196	{
5178	5197	LOG_MMC(("henggedianzi_w, offset: %04x, data: %02x\n", offset, data));
5179	5198
5180		prg32(machine(), data);
5181		set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5199	prg32(data);
	5200	set_nt_mirroring(BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5182	5201	}
5183	5202
5184	5203	/*************************************************************
r18084	r18085
5202	5221	offset += 0x4100;
5203	5222
5204	5223	if (offset & 0x5000)
5205		prg32(machine(), data >> 1);
	5224	prg32(data >> 1);
5206	5225	}
5207	5226
5208	5227	WRITE8_MEMBER(nes_carts_state::heng_xjzb_w)
5209	5228	{
5210	5229	LOG_MMC(("heng_xjzb_w, offset: %04x, data: %02x\n", offset, data));
5211	5230
5212		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5231	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5213	5232	}
5214	5233
5215	5234	/*************************************************************
r18084	r18085
5234	5253
5235	5254	if (!(offset & 0x100))
5236	5255	{
5237		prg32(machine(), (data & 0x38) >> 3);
5238		chr8(machine(), (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
5239		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	5256	prg32((data & 0x38) >> 3);
	5257	chr8((data & 0x07) | ((data & 0x40) >> 3), CHRROM);
	5258	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
5240	5259	}
5241	5260	}
5242	5261
r18084	r18085
5246	5265
5247	5266	if (!(offset & 0x100))
5248	5267	{
5249		prg32(machine(), (data & 0x38) >> 3);
5250		chr8(machine(), (data & 0x07) | ((data & 0x40) >> 3), CHRROM);
	5268	prg32((data & 0x38) >> 3);
	5269	chr8((data & 0x07) | ((data & 0x40) >> 3), CHRROM);
5251	5270	}
5252	5271	}
5253	5272
r18084	r18085
5270	5289	switch (offset & 0x7003)
5271	5290	{
5272	5291	case 0x0001:
5273		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5292	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5274	5293	break;
5275	5294	case 0x2000:
5276	5295	m_mmc_latch1 = data;
r18084	r18085
5279	5298	switch (m_mmc_latch1)
5280	5299	{
5281	5300	case 0:
5282		chr2_0(machine(), data >> 1, CHRROM);
	5301	chr2_0(data >> 1, CHRROM);
5283	5302	break;
5284	5303	case 1:
5285		chr1_5(machine(), data, CHRROM);
	5304	chr1_5(data, CHRROM);
5286	5305	break;
5287	5306	case 2:
5288		chr2_2(machine(), data >> 1, CHRROM);
	5307	chr2_2(data >> 1, CHRROM);
5289	5308	break;
5290	5309	case 3:
5291		chr1_7(machine(), data, CHRROM);
	5310	chr1_7(data, CHRROM);
5292	5311	break;
5293	5312	case 4:
5294		prg8_89(machine(), data);
	5313	prg8_89(data);
5295	5314	break;
5296	5315	case 5:
5297		prg8_ab(machine(), data);
	5316	prg8_ab(data);
5298	5317	break;
5299	5318	case 6:
5300		chr1_4(machine(), data, CHRROM);
	5319	chr1_4(data, CHRROM);
5301	5320	break;
5302	5321	case 7:
5303		chr1_6(machine(), data, CHRROM);
	5322	chr1_6(data, CHRROM);
5304	5323	break;
5305	5324	}
5306	5325	break;
r18084	r18085
5339	5358	switch (offset & 0x7080)
5340	5359	{
5341	5360	case 0x7000:
5342		chr4_0(machine(), data, CHRROM);
	5361	chr4_0(data, CHRROM);
5343	5362	break;
5344	5363	case 0x7080:
5345		chr4_4(machine(), data, CHRROM);
	5364	chr4_4(data, CHRROM);
5346	5365	break;
5347	5366	}
5348	5367	}
r18084	r18085
5364	5383	LOG_MMC(("ks7022_w, offset: %04x, data: %02x\n", offset, data));
5365	5384
5366	5385	if (offset == 0)
5367		set_nt_mirroring(machine(), BIT(data, 2) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5386	set_nt_mirroring(BIT(data, 2) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5368	5387
5369	5388	if (offset == 0x2000)
5370	5389	m_mmc_latch1 = data & 0x0f;
r18084	r18085
5376	5395
5377	5396	if (offset == 0x7ffc)
5378	5397	{
5379		chr8(machine(), m_mmc_latch1, CHRROM);
5380		prg16_89ab(machine(), m_mmc_latch1);
5381		prg16_cdef(machine(), m_mmc_latch1);
	5398	chr8(m_mmc_latch1, CHRROM);
	5399	prg16_89ab(m_mmc_latch1);
	5400	prg16_cdef(m_mmc_latch1);
5382	5401	}
5383	5402
5384	5403	return mmc_hi_access_rom(machine(), offset);
r18084	r18085
5400	5419	{
5401	5420	nes_state *state = machine.driver_data<nes_state>();
5402	5421
5403		prg8_67(machine, state->m_mmc_reg[4]);
5404		prg8_89(machine, state->m_mmc_reg[1]);
5405		prg8_ab(machine, state->m_mmc_reg[2]);
5406		prg8_cd(machine, state->m_mmc_reg[3]);
	5422	state->prg8_67(state->m_mmc_reg[4]);
	5423	state->prg8_89(state->m_mmc_reg[1]);
	5424	state->prg8_ab(state->m_mmc_reg[2]);
	5425	state->prg8_cd(state->m_mmc_reg[3]);
5407	5426	}
5408	5427
5409	5428	static void ks7032_irq( device_t *device, int scanline, int vblank, int blanked )
r18084	r18085
5497	5516	switch (offset & 0xc00)
5498	5517	{
5499	5518	case 0x800:
5500		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	5519	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
5501	5520	break;
5502	5521	case 0xc00:
5503		chr1_x(machine(), offset & 0x07, data, CHRROM);
	5522	chr1_x(offset & 0x07, data, CHRROM);
5504	5523	break;
5505	5524	}
5506	5525	break;
r18084	r18085
5546	5565	m_mmc_latch1 = ((offset >> 2) & 0x03) | ((offset >> 4) & 0x04);
5547	5566
5548	5567	if (offset >= 0x1000 && offset < 0x1100)
5549		prg16_89ab(machine(), m_mmc_latch1);
	5568	prg16_89ab(m_mmc_latch1);
5550	5569	}
5551	5570
5552	5571	WRITE8_MEMBER(nes_carts_state::ks7017_extra_w)
r18084	r18085
5562	5581	m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
5563	5582
5564	5583	if (offset == 0x0025) /* 0x4025 */
5565		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5584	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5566	5585	}
5567	5586
5568	5587	READ8_MEMBER(nes_carts_state::ks7017_extra_r)
r18084	r18085
5670	5689
5671	5690	if (state->m_mmc_reg[5] & 0x3f)
5672	5691	{
5673		prg8_x(machine, start, bank & 0x3f);
5674		prg8_ef(machine, state->m_mmc_reg[1]);
5675		prg8_cd(machine, state->m_mmc_reg[2]);
5676		prg8_ab(machine, state->m_mmc_reg[3]);
	5692	state->prg8_x(start, bank & 0x3f);
	5693	state->prg8_ef(state->m_mmc_reg[1]);
	5694	state->prg8_cd(state->m_mmc_reg[2]);
	5695	state->prg8_ab(state->m_mmc_reg[3]);
5677	5696	}
5678	5697	else
5679		prg8_x(machine, start, bank & 0x3f);
	5698	state->prg8_x(start, bank & 0x3f);
5680	5699	}
5681	5700
5682	5701	static void kay_pp_chr_cb( running_machine &machine, int start, int bank, int source )
r18084	r18085
5687	5706	if ((start & 0x04) == chr_page)
5688	5707	bank |= 0x100;
5689	5708
5690		chr1_x(machine, start, bank, source);
	5709	state->chr1_x(start, bank, source);
5691	5710	}
5692	5711
5693	5712	WRITE8_MEMBER(nes_carts_state::kay_pp_w)
r18084	r18085
5742	5761	{
5743	5762	nes_state *state = machine.driver_data<nes_state>();
5744	5763	if (BIT(state->m_mmc_reg[0], 7))
5745		prg32(machine, state->m_mmc_reg[0] >> 1);
	5764	state->prg32(state->m_mmc_reg[0] >> 1);
5746	5765	else
5747		prg8_x(machine, start, bank);
	5766	state->prg8_x(start, bank);
5748	5767	}
5749	5768
5750	5769	WRITE8_MEMBER(nes_carts_state::kasing_m_w)
r18084	r18085
5783	5802	{
5784	5803	LOG_MMC(("magics_md_w, offset: %04x, data: %02x\n", offset, data));
5785	5804
5786		prg32(machine(), data >> 1);
5787		chr8(machine(), data, CHRROM);
	5805	prg32(data >> 1);
	5806	chr8(data, CHRROM);
5788	5807	}
5789	5808
5790	5809	/*************************************************************
r18084	r18085
5807	5826	{
5808	5827	if (scanline == 127)
5809	5828	{
5810		chr4_0(device->machine(), 1, CHRRAM);
5811		chr4_4(device->machine(), 1, CHRRAM);
	5829	state->chr4_0(1, CHRRAM);
	5830	state->chr4_4(1, CHRRAM);
5812	5831	}
5813	5832
5814	5833	if (scanline == 239)
5815	5834	{
5816		chr4_0(device->machine(), 0, CHRRAM);
5817		chr4_4(device->machine(), 0, CHRRAM);
	5835	state->chr4_0(0, CHRRAM);
	5836	state->chr4_4(0, CHRRAM);
5818	5837	}
5819	5838	}
5820	5839
r18084	r18085
5832	5851	if (offset == 0x1100)   // 0x5100
5833	5852	{
5834	5853	if (data == 6)
5835		prg32(machine(), 3);
	5854	prg32(3);
5836	5855	return;
5837	5856	}
5838	5857
r18084	r18085
5851	5870	case 0x200:
5852	5871	m_mmc_reg[BIT(offset, 9)] = data;
5853	5872	if (!BIT(m_mmc_reg[0], 7) && m_ppu->get_current_scanline() <= 127)
5854		chr8(machine(), 0, CHRRAM);
	5873	chr8(0, CHRRAM);
5855	5874	break;
5856	5875	case 0x300:
5857	5876	m_mmc_latch1 = data;
5858	5877	break;
5859	5878	}
5860	5879
5861		prg32(machine(), (m_mmc_reg[0] & 0x0f) | ((m_mmc_reg[1] & 0x0f) << 4));
	5880	prg32((m_mmc_reg[0] & 0x0f) | ((m_mmc_reg[1] & 0x0f) << 4));
5862	5881	}
5863	5882
5864	5883	READ8_MEMBER(nes_carts_state::nanjing_l_r)
r18084	r18085
5939	5958	switch (m_mmc_latch1)
5940	5959	{
5941	5960	case 0:
5942		prg8_89(machine(), data);
	5961	prg8_89(data);
5943	5962	break;
5944	5963	case 1:
5945		prg8_ab(machine(), data);
	5964	prg8_ab(data);
5946	5965	break;
5947	5966	case 2:
5948	5967	data &= 0xfe;
5949		chr1_0(machine(), data, CHRROM);
5950		chr1_1(machine(), data + 1, CHRROM);
	5968	chr1_0(data, CHRROM);
	5969	chr1_1(data + 1, CHRROM);
5951	5970	break;
5952	5971	case 3:
5953	5972	data &= 0xfe;
5954		chr1_2(machine(), data, CHRROM);
5955		chr1_3(machine(), data + 1, CHRROM);
	5973	chr1_2(data, CHRROM);
	5974	chr1_3(data + 1, CHRROM);
5956	5975	break;
5957	5976	case 4:
5958		chr1_4(machine(), data, CHRROM);
	5977	chr1_4(data, CHRROM);
5959	5978	break;
5960	5979	case 5:
5961		chr1_5(machine(), data, CHRROM);
	5980	chr1_5(data, CHRROM);
5962	5981	break;
5963	5982	case 6:
5964		chr1_6(machine(), data, CHRROM);
	5983	chr1_6(data, CHRROM);
5965	5984	break;
5966	5985	case 7:
5967		chr1_7(machine(), data, CHRROM);
	5986	chr1_7(data, CHRROM);
5968	5987	break;
5969	5988	}
5970	5989	break;
5971	5990	case 0x6000:
5972		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	5991	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
5973	5992	break;
5974	5993	}
5975	5994	}
r18084	r18085
5996	6015	switch (offset & 0x03)
5997	6016	{
5998	6017	case 0:
5999		chr4_0(machine(), data >> 2, CHRROM);
	6018	chr4_0(data >> 2, CHRROM);
6000	6019	break;
6001	6020	case 1:
6002		chr2_4(machine(), data >> 1, CHRROM);
	6021	chr2_4(data >> 1, CHRROM);
6003	6022	break;
6004	6023	case 2:
6005		chr2_6(machine(), data >> 1 , CHRROM);
	6024	chr2_6(data >> 1 , CHRROM);
6006	6025	break;
6007	6026	case 3:
6008		prg8_89(machine(), data);
	6027	prg8_89(data);
6009	6028	break;
6010	6029	}
6011	6030	}
r18084	r18085
6035	6054	case 0x4000:
6036	6055	case 0x4004:
6037	6056	m_mmc_reg[reg + 0] = data;
6038		chr1_0(machine(), m_mmc_reg[0] | (m_mmc_reg[8] << 8), CHRROM);
	6057	chr1_0(m_mmc_reg[0] | (m_mmc_reg[8] << 8), CHRROM);
6039	6058	break;
6040	6059	case 0x4001:
6041	6060	case 0x4005:
6042	6061	m_mmc_reg[reg + 1] = data;
6043		chr1_1(machine(), m_mmc_reg[1] | (m_mmc_reg[9] << 8), CHRROM);
	6062	chr1_1(m_mmc_reg[1] | (m_mmc_reg[9] << 8), CHRROM);
6044	6063	break;
6045	6064	case 0x4002:
6046	6065	case 0x4006:
6047	6066	m_mmc_reg[reg + 2] = data;
6048		chr1_2(machine(), m_mmc_reg[2] | (m_mmc_reg[10] << 8), CHRROM);
	6067	chr1_2(m_mmc_reg[2] | (m_mmc_reg[10] << 8), CHRROM);
6049	6068	break;
6050	6069	case 0x4003:
6051	6070	case 0x4007:
6052	6071	m_mmc_reg[reg + 3] = data;
6053		chr1_3(machine(), m_mmc_reg[3] | (m_mmc_reg[11] << 8), CHRROM);
	6072	chr1_3(m_mmc_reg[3] | (m_mmc_reg[11] << 8), CHRROM);
6054	6073	break;
6055	6074	case 0x4008:
6056	6075	case 0x400c:
6057	6076	m_mmc_reg[reg + 4] = data;
6058		chr1_4(machine(), m_mmc_reg[4] | (m_mmc_reg[12] << 8), CHRROM);
	6077	chr1_4(m_mmc_reg[4] | (m_mmc_reg[12] << 8), CHRROM);
6059	6078	break;
6060	6079	case 0x4009:
6061	6080	case 0x400d:
6062	6081	m_mmc_reg[reg + 5] = data;
6063		chr1_5(machine(), m_mmc_reg[5] | (m_mmc_reg[13] << 8), CHRROM);
	6082	chr1_5(m_mmc_reg[5] | (m_mmc_reg[13] << 8), CHRROM);
6064	6083	break;
6065	6084	case 0x400a:
6066	6085	case 0x400e:
6067	6086	m_mmc_reg[reg + 6] = data;
6068		chr1_6(machine(), m_mmc_reg[6] | (m_mmc_reg[14] << 8), CHRROM);
	6087	chr1_6(m_mmc_reg[6] | (m_mmc_reg[14] << 8), CHRROM);
6069	6088	break;
6070	6089	case 0x400b:
6071	6090	case 0x400f:
6072	6091	m_mmc_reg[reg + 7] = data;
6073		chr1_7(machine(), m_mmc_reg[7] | (m_mmc_reg[15] << 8), CHRROM);
	6092	chr1_7(m_mmc_reg[7] | (m_mmc_reg[15] << 8), CHRROM);
6074	6093	break;
6075	6094	case 0x4010:
6076		prg16_89ab(machine(), data);
	6095	prg16_89ab(data);
6077	6096	break;
6078	6097	case 0x4014:
6079	6098	if (data & 1)
6080		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	6099	set_nt_mirroring(PPU_MIRROR_HORZ);
6081	6100	else
6082		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	6101	set_nt_mirroring(PPU_MIRROR_VERT);
6083	6102	break;
6084	6103	}
6085	6104	}
r18084	r18085
6103	6122	{
6104	6123	LOG_MMC(("gs2015_w, offset: %04x, data: %02x\n", offset, data));
6105	6124
6106		prg32(machine(), offset);
6107		chr8(machine(), offset >> 1, m_mmc_chr_source);
	6125	prg32(offset);
	6126	chr8(offset >> 1, m_mmc_chr_source);
6108	6127	}
6109	6128
6110	6129	/*************************************************************
r18084	r18085
6133	6152	{
6134	6153	case 0x00:
6135	6154	case 0x30:
6136		prg32(machine(), offset & 0x0f);
	6155	prg32(offset & 0x0f);
6137	6156	break;
6138	6157	case 0x10:
6139	6158	case 0x20:
6140		prg16_89ab(machine(), ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
6141		prg16_cdef(machine(), ((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
	6159	prg16_89ab(((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
	6160	prg16_cdef(((offset & 0x0f) << 1) | ((offset & 0x20) >> 4));
6142	6161	break;
6143	6162	}
6144		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6163	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6145	6164	}
6146	6165
6147	6166	/*************************************************************
r18084	r18085
6179	6198	int shift = (start < 4) ? 8 : 4;
6180	6199
6181	6200	bank |= ((state->m_mmc_reg[0] << shift) & 0x100);
6182		chr1_x(machine, start, bank, source);
	6201	state->chr1_x(start, bank, source);
6183	6202	}
6184	6203
6185	6204	/*************************************************************
r18084	r18085
6206	6225	}
6207	6226	else
6208	6227	{
6209		prg8_89(machine, state->m_mmc_extra_bank[0]);
6210		prg8_ab(machine, state->m_mmc_extra_bank[1]);
6211		prg8_cd(machine, state->m_mmc_extra_bank[2]);
6212		prg8_ef(machine, state->m_mmc_extra_bank[3]);
	6228	state->prg8_89(state->m_mmc_extra_bank[0]);
	6229	state->prg8_ab(state->m_mmc_extra_bank[1]);
	6230	state->prg8_cd(state->m_mmc_extra_bank[2]);
	6231	state->prg8_ef(state->m_mmc_extra_bank[3]);
6213	6232	}
6214	6233	}
6215	6234
r18084	r18085
6239	6258	}
6240	6259	}
6241	6260
6242		chr1_x(machine, chr_page ^ 0, chr_base2[0] | (bank[0] & chr_mask), chr);
6243		chr1_x(machine, chr_page ^ 1, chr_base2[1] | (bank[1] & chr_mask), chr);
6244		chr1_x(machine, chr_page ^ 2, chr_base2[2] | (bank[2] & chr_mask), chr);
6245		chr1_x(machine, chr_page ^ 3, chr_base2[3] | (bank[3] & chr_mask), chr);
6246		chr1_x(machine, chr_page ^ 4, chr_base2[4] | (bank[4] & chr_mask), chr);
6247		chr1_x(machine, chr_page ^ 5, chr_base2[5] | (bank[5] & chr_mask), chr);
6248		chr1_x(machine, chr_page ^ 6, chr_base2[6] | (bank[6] & chr_mask), chr);
6249		chr1_x(machine, chr_page ^ 7, chr_base2[7] | (bank[7] & chr_mask), chr);
	6261	state->chr1_x(chr_page ^ 0, chr_base2[0] | (bank[0] & chr_mask), chr);
	6262	state->chr1_x(chr_page ^ 1, chr_base2[1] | (bank[1] & chr_mask), chr);
	6263	state->chr1_x(chr_page ^ 2, chr_base2[2] | (bank[2] & chr_mask), chr);
	6264	state->chr1_x(chr_page ^ 3, chr_base2[3] | (bank[3] & chr_mask), chr);
	6265	state->chr1_x(chr_page ^ 4, chr_base2[4] | (bank[4] & chr_mask), chr);
	6266	state->chr1_x(chr_page ^ 5, chr_base2[5] | (bank[5] & chr_mask), chr);
	6267	state->chr1_x(chr_page ^ 6, chr_base2[6] | (bank[6] & chr_mask), chr);
	6268	state->chr1_x(chr_page ^ 7, chr_base2[7] | (bank[7] & chr_mask), chr);
6250	6269	}
6251	6270
6252	6271	WRITE8_MEMBER(nes_carts_state::rex_sl1632_w)
r18084	r18085
6261	6280	rex_sl1632_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
6262	6281
6263	6282	if (!(m_mmc_reg[0] & 0x02))
6264		set_nt_mirroring(machine(), BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6283	set_nt_mirroring(BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6265	6284	}
6266	6285
6267	6286	if (m_mmc_reg[0] & 0x02)
r18084	r18085
6303	6322	break;
6304	6323
6305	6324	case 0x2000:
6306		set_nt_mirroring(machine(), BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	6325	set_nt_mirroring(BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
6307	6326	break;
6308	6327
6309	6328	default:
r18084	r18085
6331	6350
6332	6351	case 0x1000:
6333	6352	m_mmc_reg[1] = data;
6334		set_nt_mirroring(machine(), BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6353	set_nt_mirroring(BIT(m_mmc_reg[1], 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6335	6354	break;
6336	6355	}
6337	6356	}
r18084	r18085
6355	6374
6356	6375	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & 0x01) | ((data & 0x0f) << 1);
6357	6376	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & 0x07) | ((data & 0xf0) >> 1);
6358		prg32(machine(), m_mmc_prg_bank[0]);
6359		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6377	prg32(m_mmc_prg_bank[0]);
	6378	chr8(m_mmc_vrom_bank[0], CHRROM);
6360	6379	}
6361	6380
6362	6381	WRITE8_MEMBER(nes_carts_state::rumblestation_w)
r18084	r18085
6365	6384
6366	6385	m_mmc_prg_bank[0] = (m_mmc_prg_bank[0] & ~0x01) | (data & 0x01);
6367	6386	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x07) | ((data & 0x70) >> 4);
6368		prg32(machine(), m_mmc_prg_bank[0]);
6369		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6387	prg32(m_mmc_prg_bank[0]);
	6388	chr8(m_mmc_vrom_bank[0], CHRROM);
6370	6389	}
6371	6390
6372	6391	/*************************************************************
r18084	r18085
6382	6401
6383	6402	static void sachen_set_mirror( running_machine &machine, UINT8 nt ) // used by mappers 137, 138, 139, 141
6384	6403	{
	6404	nes_state *state = machine.driver_data<nes_state>();
6385	6405	switch (nt)
6386	6406	{
6387	6407	case 0:
6388	6408	case 1:
6389		set_nt_mirroring(machine, nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	6409	state->set_nt_mirroring(nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6390	6410	break;
6391	6411	case 2:
6392		set_nt_page(machine, 0, CIRAM, 0, 1);
6393		set_nt_page(machine, 1, CIRAM, 1, 1);
6394		set_nt_page(machine, 2, CIRAM, 1, 1);
6395		set_nt_page(machine, 3, CIRAM, 1, 1);
	6412	state->set_nt_page(0, CIRAM, 0, 1);
	6413	state->set_nt_page(1, CIRAM, 1, 1);
	6414	state->set_nt_page(2, CIRAM, 1, 1);
	6415	state->set_nt_page(3, CIRAM, 1, 1);
6396	6416	break;
6397	6417	case 3:
6398		set_nt_mirroring(machine, PPU_MIRROR_LOW);
	6418	state->set_nt_mirroring(PPU_MIRROR_LOW);
6399	6419	break;
6400	6420	default:
6401	6421	LOG_MMC(("Mapper set NT to invalid value %02x", nt));
r18084	r18085
6418	6438	{
6419	6439	case 0x02:
6420	6440	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x08) | ((data << 3) & 0x08);
6421		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
6422		prg32(machine(), data & 0x01);
	6441	chr8(m_mmc_vrom_bank[0], CHRROM);
	6442	prg32(data & 0x01);
6423	6443	break;
6424	6444	case 0x04:
6425	6445	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x04) | ((data << 2) & 0x04);
6426		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6446	chr8(m_mmc_vrom_bank[0], CHRROM);
6427	6447	break;
6428	6448	case 0x05:
6429		prg32(machine(), data & 0x07);
	6449	prg32(data & 0x07);
6430	6450	break;
6431	6451	case 0x06:
6432	6452	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x03) | ((data << 0) & 0x03);
6433		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6453	chr8(m_mmc_vrom_bank[0], CHRROM);
6434	6454	break;
6435	6455	case 0x07:
6436	6456	sachen_set_mirror(machine(), (data >> 1) & 0x03);
r18084	r18085
6467	6487	switch (m_mmc_latch1 & 0x07)
6468	6488	{
6469	6489	case 0x00:
6470		prg32(machine(), 0);
6471		chr8(machine(), 3, CHRROM);
	6490	prg32(0);
	6491	chr8(3, CHRROM);
6472	6492	break;
6473	6493	case 0x02:
6474	6494	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x08) | ((data << 3) & 0x08);
6475		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6495	chr8(m_mmc_vrom_bank[0], CHRROM);
6476	6496	break;
6477	6497	case 0x04:
6478	6498	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x01) | ((data << 0) & 0x01);
6479		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6499	chr8(m_mmc_vrom_bank[0], CHRROM);
6480	6500	break;
6481	6501	case 0x05:
6482		prg32(machine(), data & 0x01);
	6502	prg32(data & 0x01);
6483	6503	break;
6484	6504	case 0x06:
6485	6505	m_mmc_vrom_bank[0] = (m_mmc_vrom_bank[0] & ~0x06) | ((data << 1) & 0x06);
6486		chr8(machine(), m_mmc_vrom_bank[0], CHRROM);
	6506	chr8(m_mmc_vrom_bank[0], CHRROM);
6487	6507	break;
6488	6508	case 0x07:
6489	6509	sachen_set_mirror(machine(), BIT(data, 0));
r18084	r18085
6505	6525
6506	6526	static void common_s8259_write_handler( address_space &space, offs_t offset, UINT8 data, int board )
6507	6527	{
6508		nes_state *state = space.machine().driver_data<nes_state>();
	6528	running_machine &machine = space.machine();
	6529	nes_state *state = machine.driver_data<nes_state>();
6509	6530	UINT8 bank_helper1, bank_helper2, shift, add1, add2, add3;
6510	6531
6511	6532	/* write happens only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
r18084	r18085
6520	6541	switch (state->m_mmc_latch1)
6521	6542	{
6522	6543	case 0x05:
6523		prg32(space.machine(), data);
	6544	state->prg32(data);
6524	6545	break;
6525	6546	case 0x07:
6526		sachen_set_mirror(space.machine(), BIT(data, 0) ? 0 : (data >> 1) & 0x03);
	6547	sachen_set_mirror(machine, BIT(data, 0) ? 0 : (data >> 1) & 0x03);
6527	6548	break;
6528	6549	default:
6529	6550	if (board == SACHEN_8259D)
6530	6551	{
6531	6552	if (state->m_mmc_chr_source == CHRROM)
6532	6553	{
6533		chr1_0(space.machine(), (state->m_sachen_reg[0] & 0x07), CHRROM);
6534		chr1_1(space.machine(), (state->m_sachen_reg[1] & 0x07) | (state->m_sachen_reg[4] << 4 & 0x10), CHRROM);
6535		chr1_2(space.machine(), (state->m_sachen_reg[2] & 0x07) | (state->m_sachen_reg[4] << 3 & 0x10), CHRROM);
6536		chr1_3(space.machine(), (state->m_sachen_reg[3] & 0x07) | (state->m_sachen_reg[4] << 2 & 0x10) | (state->m_sachen_reg[6] << 3 & 0x08), CHRROM);
	6554	state->chr1_0((state->m_sachen_reg[0] & 0x07), CHRROM);
	6555	state->chr1_1((state->m_sachen_reg[1] & 0x07) | (state->m_sachen_reg[4] << 4 & 0x10), CHRROM);
	6556	state->chr1_2((state->m_sachen_reg[2] & 0x07) | (state->m_sachen_reg[4] << 3 & 0x10), CHRROM);
	6557	state->chr1_3((state->m_sachen_reg[3] & 0x07) | (state->m_sachen_reg[4] << 2 & 0x10) | (state->m_sachen_reg[6] << 3 & 0x08), CHRROM);
6537	6558	}
6538	6559	}
6539	6560	else
r18084	r18085
6547	6568
6548	6569	if (state->m_mmc_chr_source == CHRROM)
6549	6570	{
6550		chr2_0(space.machine(), ((state->m_sachen_reg[bank_helper1 ? 0 : 0] & 0x07) | bank_helper2) << shift, CHRROM);
6551		chr2_2(space.machine(), ((state->m_sachen_reg[bank_helper1 ? 0 : 1] & 0x07) | bank_helper2) << shift | add1, CHRROM);
6552		chr2_4(space.machine(), ((state->m_sachen_reg[bank_helper1 ? 0 : 2] & 0x07) | bank_helper2) << shift | add2, CHRROM);
6553		chr2_6(space.machine(), ((state->m_sachen_reg[bank_helper1 ? 0 : 3] & 0x07) | bank_helper2) << shift | add3, CHRROM);
	6571	state->chr2_0(((state->m_sachen_reg[bank_helper1 ? 0 : 0] & 0x07) | bank_helper2) << shift, CHRROM);
	6572	state->chr2_2(((state->m_sachen_reg[bank_helper1 ? 0 : 1] & 0x07) | bank_helper2) << shift | add1, CHRROM);
	6573	state->chr2_4(((state->m_sachen_reg[bank_helper1 ? 0 : 2] & 0x07) | bank_helper2) << shift | add2, CHRROM);
	6574	state->chr2_6(((state->m_sachen_reg[bank_helper1 ? 0 : 3] & 0x07) | bank_helper2) << shift | add3, CHRROM);
6554	6575	}
6555	6576	}
6556	6577	break;
r18084	r18085
6590	6611	{
6591	6612	LOG_MMC(("sa009_l_w, offset: %04x, data: %02x\n", offset, data));
6592	6613
6593		chr8(machine(), data, m_mmc_chr_source);
	6614	chr8(data, m_mmc_chr_source);
6594	6615	}
6595	6616
6596	6617	/*************************************************************
r18084	r18085
6609	6630	{
6610	6631	LOG_MMC(("sa0036_w, offset: %04x, data: %02x\n", offset, data));
6611	6632
6612		chr8(machine(), data >> 7, CHRROM);
	6633	chr8(data >> 7, CHRROM);
6613	6634	}
6614	6635
6615	6636	/*************************************************************
r18084	r18085
6628	6649	{
6629	6650	LOG_MMC(("sa0037_w, offset: %04x, data: %02x\n", offset, data));
6630	6651
6631		prg32(machine(), data >> 3);
6632		chr8(machine(), data, CHRROM);
	6652	prg32(data >> 3);
	6653	chr8(data, CHRROM);
6633	6654	}
6634	6655
6635	6656	/*************************************************************
r18084	r18085
6650	6671
6651	6672	/* only if we are at 0x4100 + k * 0x200, but 0x4100 is offset = 0 */
6652	6673	if (!(offset & 0x100))
6653		chr8(machine(), data >> 7, CHRROM);
	6674	chr8(data >> 7, CHRROM);
6654	6675	}
6655	6676
6656	6677	/*************************************************************
r18084	r18085
6669	6690	{
6670	6691	LOG_MMC(("sa72008_l_w, offset: %04x, data: %02x\n", offset, data));
6671	6692
6672		prg32(machine(), data >> 2);
6673		chr8(machine(), data, CHRROM);
	6693	prg32(data >> 2);
	6694	chr8(data, CHRROM);
6674	6695	}
6675	6696
6676	6697	/*************************************************************
r18084	r18085
6714	6735
6715	6736	if ((offset & 0x103) == 0x002)
6716	6737	{
6717		prg32(machine(), ((data >> 6) & 0x02) | ((data >> 2) & 0x01));
6718		chr8(machine(), data >> 3, CHRROM);
	6738	prg32(((data >> 6) & 0x02) | ((data >> 2) & 0x01));
	6739	chr8(data >> 3, CHRROM);
6719	6740	}
6720	6741	}
6721	6742
r18084	r18085
6752	6773	if ((offset & 0x103) == 0x002)
6753	6774	{
6754	6775	m_mmc_latch1 = (data & 0x30) | ((data + 3) & 0x0f);
6755		chr8(machine(), m_mmc_latch1, CHRROM);
	6776	chr8(m_mmc_latch1, CHRROM);
6756	6777	}
6757	6778	}
6758	6779
r18084	r18085
6801	6822	subor_helper2 = 0x20;
6802	6823	}
6803	6824
6804		prg16_89ab(machine(), subor_helper1);
6805		prg16_cdef(machine(), subor_helper2);
	6825	prg16_89ab(subor_helper1);
	6826	prg16_cdef(subor_helper2);
6806	6827	}
6807	6828
6808	6829	/*************************************************************
r18084	r18085
6839	6860	subor_helper2 = 0x07;
6840	6861	}
6841	6862
6842		prg16_89ab(machine(), subor_helper1);
6843		prg16_cdef(machine(), subor_helper2);
	6863	prg16_89ab(subor_helper1);
	6864	prg16_cdef(subor_helper2);
6844	6865	}
6845	6866
6846	6867	/*************************************************************
r18084	r18085
6868	6889	else
6869	6890	bank = (bank & 0x0f) | (state->m_mmc_reg[1] & 0x10);
6870	6891
6871		prg8_x(machine, start, bank);
	6892	state->prg8_x(start, bank);
6872	6893	}
6873	6894	}
6874	6895
r18084	r18085
6881	6902	else
6882	6903	bank = (bank & 0x7f) | ((state->m_mmc_reg[1] & 0x10) << 3);
6883	6904
6884		chr1_x(machine, start, bank, source);
	6905	state->chr1_x(start, bank, source);
6885	6906	}
6886	6907
6887	6908	static void sgame_boog_set_prg( running_machine &machine )
r18084	r18085
6889	6910	nes_state *state = machine.driver_data<nes_state>();
6890	6911	if (state->m_mmc_reg[0] & 0x80)
6891	6912	{
6892		prg16_89ab(machine, (state->m_mmc_reg[0] & 0xf0) | (state->m_mmc_reg[1] & 0x10));
6893		prg16_cdef(machine, (state->m_mmc_reg[0] & 0xf0) | (state->m_mmc_reg[1] & 0x10));
	6913	state->prg16_89ab((state->m_mmc_reg[0] & 0xf0) | (state->m_mmc_reg[1] & 0x10));
	6914	state->prg16_cdef((state->m_mmc_reg[0] & 0xf0) | (state->m_mmc_reg[1] & 0x10));
6894	6915	}
6895	6916	else
6896	6917	mmc3_set_prg(machine, state->m_mmc_prg_base, state->m_mmc_prg_mask);
r18084	r18085
6981	7002	if (!m_mmc_reg[2])
6982	7003	txrom_w(space, 0x4000, data, mem_mask);
6983	7004	else
6984		set_nt_mirroring(machine(), ((data >> 7) | data) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7005	set_nt_mirroring(((data >> 7) | data) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
6985	7006	break;
6986	7007
6987	7008	case 0x4001:
r18084	r18085
7029	7050
7030	7051	if (m_map114_reg & 0x80)
7031	7052	{
7032		prg16_89ab(machine(), data & 0x1f);
7033		prg16_cdef(machine(), data & 0x1f);
	7053	prg16_89ab(data & 0x1f);
	7054	prg16_cdef(data & 0x1f);
7034	7055	}
7035	7056	else
7036	7057	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
r18084	r18085
7047	7068	switch (offset & 0x6000)
7048	7069	{
7049	7070	case 0x0000:
7050		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7071	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7051	7072	break;
7052	7073	case 0x2000:
7053	7074	m_map114_reg_enabled = 1;
r18084	r18085
7093	7114	{
7094	7115	LOG_MMC(("tengen_800008_w, offset: %04x, data: %02x\n", offset, data));
7095	7116
7096		prg32(machine(), data >> 3);
7097		chr8(machine(), data, CHRROM);
	7117	prg32(data >> 3);
	7118	chr8(data, CHRROM);
7098	7119	}
7099	7120
7100	7121	/*************************************************************
r18084	r18085
7172	7193	nes_state *state = machine.driver_data<nes_state>();
7173	7194	UINT8 prg_mode = state->m_mmc_latch1 & 0x40;
7174	7195
7175		prg8_89(machine, state->m_mmc_prg_bank[prg_mode ? 2: 0]);
7176		prg8_ab(machine, state->m_mmc_prg_bank[prg_mode ? 0: 1]);
7177		prg8_cd(machine, state->m_mmc_prg_bank[prg_mode ? 1: 2]);
	7196	state->prg8_89(state->m_mmc_prg_bank[prg_mode ? 2: 0]);
	7197	state->prg8_ab(state->m_mmc_prg_bank[prg_mode ? 0: 1]);
	7198	state->prg8_cd(state->m_mmc_prg_bank[prg_mode ? 1: 2]);
7178	7199	}
7179	7200
7180	7201	static void tengen_800032_set_chr( running_machine &machine )
r18084	r18085
7184	7205
7185	7206	if (state->m_mmc_latch1 & 0x20)
7186	7207	{
7187		chr1_x(machine, 0 ^ chr_page, state->m_mmc_vrom_bank[0], CHRROM);
7188		chr1_x(machine, 1 ^ chr_page, state->m_mmc_vrom_bank[8], CHRROM);
7189		chr1_x(machine, 2 ^ chr_page, state->m_mmc_vrom_bank[1], CHRROM);
7190		chr1_x(machine, 3 ^ chr_page, state->m_mmc_vrom_bank[9], CHRROM);
	7208	state->chr1_x(0 ^ chr_page, state->m_mmc_vrom_bank[0], CHRROM);
	7209	state->chr1_x(1 ^ chr_page, state->m_mmc_vrom_bank[8], CHRROM);
	7210	state->chr1_x(2 ^ chr_page, state->m_mmc_vrom_bank[1], CHRROM);
	7211	state->chr1_x(3 ^ chr_page, state->m_mmc_vrom_bank[9], CHRROM);
7191	7212	}
7192	7213	else
7193	7214	{
7194		chr1_x(machine, 0 ^ chr_page, state->m_mmc_vrom_bank[0] & ~0x01, CHRROM);
7195		chr1_x(machine, 1 ^ chr_page, state->m_mmc_vrom_bank[0] |  0x01, CHRROM);
7196		chr1_x(machine, 2 ^ chr_page, state->m_mmc_vrom_bank[1] & ~0x01, CHRROM);
7197		chr1_x(machine, 3 ^ chr_page, state->m_mmc_vrom_bank[1] |  0x01, CHRROM);
	7215	state->chr1_x(0 ^ chr_page, state->m_mmc_vrom_bank[0] & ~0x01, CHRROM);
	7216	state->chr1_x(1 ^ chr_page, state->m_mmc_vrom_bank[0] |  0x01, CHRROM);
	7217	state->chr1_x(2 ^ chr_page, state->m_mmc_vrom_bank[1] & ~0x01, CHRROM);
	7218	state->chr1_x(3 ^ chr_page, state->m_mmc_vrom_bank[1] |  0x01, CHRROM);
7198	7219	}
7199	7220
7200		chr1_x(machine, 4 ^ chr_page, state->m_mmc_vrom_bank[2], CHRROM);
7201		chr1_x(machine, 5 ^ chr_page, state->m_mmc_vrom_bank[3], CHRROM);
7202		chr1_x(machine, 6 ^ chr_page, state->m_mmc_vrom_bank[4], CHRROM);
7203		chr1_x(machine, 7 ^ chr_page, state->m_mmc_vrom_bank[5], CHRROM);
	7221	state->chr1_x(4 ^ chr_page, state->m_mmc_vrom_bank[2], CHRROM);
	7222	state->chr1_x(5 ^ chr_page, state->m_mmc_vrom_bank[3], CHRROM);
	7223	state->chr1_x(6 ^ chr_page, state->m_mmc_vrom_bank[4], CHRROM);
	7224	state->chr1_x(7 ^ chr_page, state->m_mmc_vrom_bank[5], CHRROM);
7204	7225	}
7205	7226
7206	7227	WRITE8_MEMBER(nes_carts_state::tengen_800032_w)
r18084	r18085
7249	7270	break;
7250	7271
7251	7272	case 0x2000:
7252		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7273	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7253	7274	break;
7254	7275
7255	7276	case 0x4000:
r18084	r18085
7293	7314	nes_state *state = machine.driver_data<nes_state>();
7294	7315	UINT8 nt_mode = state->m_mmc_latch1 & 0x80;
7295	7316
7296		set_nt_page(machine, 0, ROM, state->m_mmc_vrom_bank[nt_mode ? 2 : 0], 0);
7297		set_nt_page(machine, 1, ROM, state->m_mmc_vrom_bank[nt_mode ? 3 : 0], 0);
7298		set_nt_page(machine, 2, ROM, state->m_mmc_vrom_bank[nt_mode ? 4 : 1], 0);
7299		set_nt_page(machine, 3, ROM, state->m_mmc_vrom_bank[nt_mode ? 5 : 1], 0);
	7317	state->set_nt_page(0, ROM, state->m_mmc_vrom_bank[nt_mode ? 2 : 0], 0);
	7318	state->set_nt_page(1, ROM, state->m_mmc_vrom_bank[nt_mode ? 3 : 0], 0);
	7319	state->set_nt_page(2, ROM, state->m_mmc_vrom_bank[nt_mode ? 4 : 1], 0);
	7320	state->set_nt_page(3, ROM, state->m_mmc_vrom_bank[nt_mode ? 5 : 1], 0);
7300	7321	}
7301	7322
7302	7323	WRITE8_MEMBER(nes_carts_state::tengen_800037_w)
r18084	r18085
7396	7417	{
7397	7418	LOG_MMC(("txc_22211_w, offset: %04x, data: %02x\n", offset, data));
7398	7419
7399		prg32(machine(), m_txc_reg[2] >> 2);
7400		chr8(machine(), m_txc_reg[2], CHRROM);
	7420	prg32(m_txc_reg[2] >> 2);
	7421	chr8(m_txc_reg[2], CHRROM);
7401	7422	}
7402	7423
7403	7424	/*************************************************************
r18084	r18085
7419	7440	{
7420	7441	LOG_MMC(("txc_22211b_w, offset: %04x, data: %02x\n", offset, data));
7421	7442
7422		prg32(machine(), m_txc_reg[2] >> 2);
7423		chr8(machine(), (((data ^ m_txc_reg[2]) >> 3) & 0x02) | (((data ^ m_txc_reg[2]) >> 5) & 0x01), CHRROM);
	7443	prg32(m_txc_reg[2] >> 2);
	7444	chr8((((data ^ m_txc_reg[2]) >> 3) & 0x02) | (((data ^ m_txc_reg[2]) >> 5) & 0x01), CHRROM);
7424	7445	}
7425	7446
7426	7447	/*************************************************************
r18084	r18085
7466	7487	{
7467	7488	LOG_MMC(("txctw_l_w, offset: %04x, data: %02x\n", offset, data));
7468	7489
7469		prg32(machine(), (data >> 4) | data);
	7490	prg32((data >> 4) | data);
7470	7491	}
7471	7492
7472	7493	WRITE8_MEMBER(nes_carts_state::txc_tw_m_w)
r18084	r18085
7502	7523
7503	7524	if ((offset >= 0x400) && (offset < 0x7fff))
7504	7525	{
7505		prg32(machine(), data >> 4);
7506		chr8(machine(), data & 0x0f, CHRROM);
	7526	prg32(data >> 4);
	7527	chr8(data & 0x0f, CHRROM);
7507	7528	}
7508	7529	}
7509	7530
r18084	r18085
7532	7553	{
7533	7554	LOG_MMC(("txc_mxmdhtwo_w, offset: %04x, data: %02x\n", offset, data));
7534	7555
7535		prg32(machine(), data);
	7556	prg32(data);
7536	7557	}
7537	7558
7538	7559	/*************************************************************
r18084	r18085
7555	7576	/* MIRROR_LOW and MIRROR_HIGH are swapped! */
7556	7577	static void waixing_set_mirror( running_machine &machine, UINT8 nt )
7557	7578	{
	7579	nes_state *state = machine.driver_data<nes_state>();
7558	7580	switch (nt)
7559	7581	{
7560	7582	case 0:
7561	7583	case 1:
7562		set_nt_mirroring(machine, nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7584	state->set_nt_mirroring(nt ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7563	7585	break;
7564	7586	case 2:
7565		set_nt_mirroring(machine, PPU_MIRROR_LOW);
	7587	state->set_nt_mirroring(PPU_MIRROR_LOW);
7566	7588	break;
7567	7589	case 3:
7568		set_nt_mirroring(machine, PPU_MIRROR_HIGH);
	7590	state->set_nt_mirroring(PPU_MIRROR_HIGH);
7569	7591	break;
7570	7592	default:
7571	7593	LOG_MMC(("Mapper set NT to invalid value %02x", nt));
r18084	r18085
7576	7598	/* Luo Ke Ren X only works with this */
7577	7599	static void waixing_a_chr_cb( running_machine &machine, int start, int bank, int source )
7578	7600	{
	7601	nes_state *state = machine.driver_data<nes_state>();
7579	7602	int chr_src = (bank <= 9) ? CHRRAM : CHRROM;
7580		chr1_x(machine, start, bank, chr_src);
	7603	state->chr1_x(start, bank, chr_src);
7581	7604	}
7582	7605
7583	7606	/* Ji Jia Zhan Shi only works with this */
7584	7607	static void waixing_a1_chr_cb( running_machine &machine, int start, int bank, int source )
7585	7608	{
	7609	nes_state *state = machine.driver_data<nes_state>();
7586	7610	int chr_src = ((bank == 8) || (bank == 9)) ? CHRRAM : CHRROM;
7587		chr1_x(machine, start, bank, chr_src);
	7611	state->chr1_x(start, bank, chr_src);
7588	7612	}
7589	7613
7590	7614	WRITE8_MEMBER(nes_carts_state::waixing_a_w)
r18084	r18085
7624	7648
7625	7649	static void waixing_b_chr_cb( running_machine &machine, int start, int bank, int source )
7626	7650	{
	7651	nes_state *state = machine.driver_data<nes_state>();
7627	7652	int chr_src = BIT(bank, 7) ? CHRRAM : CHRROM;
7628		chr1_x(machine, start, bank, chr_src);
	7653	state->chr1_x(start, bank, chr_src);
7629	7654	}
7630	7655
7631	7656	/*************************************************************
r18084	r18085
7646	7671
7647	7672	static void waixing_c_chr_cb( running_machine &machine, int start, int bank, int source )
7648	7673	{
	7674	nes_state *state = machine.driver_data<nes_state>();
7649	7675	int chr_src = ((bank == 0x08) || (bank == 0x09) || (bank == 0x0a) || (bank == 0x0b)) ? CHRRAM : CHRROM;
7650		chr1_x(machine, start, bank, chr_src);
	7676	state->chr1_x(start, bank, chr_src);
7651	7677	}
7652	7678
7653	7679	/*************************************************************
r18084	r18085
7668	7694
7669	7695	static void waixing_d_chr_cb( running_machine &machine, int start, int bank, int source )
7670	7696	{
	7697	nes_state *state = machine.driver_data<nes_state>();
7671	7698	int chr_src = (bank < 0x02) ? CHRRAM : CHRROM;
7672		chr1_x(machine, start, bank, chr_src);
	7699	state->chr1_x(start, bank, chr_src);
7673	7700	}
7674	7701
7675	7702	/*************************************************************
r18084	r18085
7691	7718
7692	7719	static void waixing_e_chr_cb( running_machine &machine, int start, int bank, int source )
7693	7720	{
	7721	nes_state *state = machine.driver_data<nes_state>();
7694	7722	int chr_src = (bank < 0x04) ? CHRRAM : CHRROM;
7695		chr1_x(machine, start, bank, chr_src);
	7723	state->chr1_x(start, bank, chr_src);
7696	7724	}
7697	7725
7698	7726	/*************************************************************
r18084	r18085
7750	7778
7751	7779	static void waixing_g_chr_cb( running_machine &machine, int start, int bank, int source )
7752	7780	{
	7781	nes_state *state = machine.driver_data<nes_state>();
7753	7782	int chr_src = (bank < 0x08) ? CHRRAM : CHRROM;
7754		chr1_x(machine, start, bank, chr_src);
	7783	state->chr1_x(start, bank, chr_src);
7755	7784	}
7756	7785
7757	7786	static void waixing_g_set_chr( running_machine &machine, int chr_base, int chr_mask )
r18084	r18085
7835	7864
7836	7865	static void waixing_h_chr_cb( running_machine &machine, int start, int bank, int source )
7837	7866	{
	7867	nes_state *state = machine.driver_data<nes_state>();
7838	7868	if (source == CHRROM)
7839		chr1_x(machine, start, bank, source);
	7869	state->chr1_x(start, bank, source);
7840	7870	}
7841	7871
7842	7872	WRITE8_MEMBER(nes_carts_state::waixing_h_w)
r18084	r18085
7892	7922	switch (offset & 0x7000)
7893	7923	{
7894	7924	case 0x0000:
7895		prg8_89(machine(), data);
	7925	prg8_89(data);
7896	7926	break;
7897	7927	case 0x2000:
7898		prg8_ab(machine(), data);
	7928	prg8_ab(data);
7899	7929	break;
7900	7930	case 0x3000:
7901	7931	case 0x4000:
r18084	r18085
7907	7937	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x0f) << 4);
7908	7938	else
7909	7939	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
7910		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	7940	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
7911	7941	break;
7912	7942	case 0x7000:
7913	7943	switch (offset & 0x0c)
r18084	r18085
7953	7983	switch (offset)
7954	7984	{
7955	7985	case 0x700:
7956		set_nt_mirroring(machine(), data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	7986	set_nt_mirroring(data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
7957	7987	break;
7958	7988	case 0x701:
7959	7989	m_mmc_latch1 = (m_mmc_latch1 & 0x0c) | ((data >> 1) & 0x03);
7960		prg32(machine(), m_mmc_latch1);
	7990	prg32(m_mmc_latch1);
7961	7991	break;
7962	7992	case 0x702:
7963	7993	m_mmc_latch1 = (m_mmc_latch1 & 0x03) | ((data << 2) & 0x0c);
r18084	r18085
7994	8024	case 0x20:
7995	8025	case 0x40:
7996	8026	case 0x60:
7997		prg16_89ab(machine(), mmc_helper | ((m_mmc_reg[0] >> 1) & 0x10) | (m_mmc_reg[0] & 0x0f));
7998		prg16_cdef(machine(), mmc_helper & 0x1f);
	8027	prg16_89ab(mmc_helper | ((m_mmc_reg[0] >> 1) & 0x10) | (m_mmc_reg[0] & 0x0f));
	8028	prg16_cdef(mmc_helper & 0x1f);
7999	8029	break;
8000	8030	case 0x50:
8001		prg32(machine(), (mmc_helper >> 1) | (m_mmc_reg[0] & 0x0f));
	8031	prg32((mmc_helper >> 1) | (m_mmc_reg[0] & 0x0f));
8002	8032	break;
8003	8033	case 0x70:
8004		prg16_89ab(machine(), mmc_helper | ((m_mmc_reg[0] << 1) & 0x10) | (m_mmc_reg[0] & 0x0f));
8005		prg16_cdef(machine(), mmc_helper & 0x1f);
	8034	prg16_89ab(mmc_helper | ((m_mmc_reg[0] << 1) & 0x10) | (m_mmc_reg[0] & 0x0f));
	8035	prg16_cdef(mmc_helper & 0x1f);
8006	8036	break;
8007	8037	}
8008	8038	}
r18084	r18085
8031	8061	{
8032	8062	LOG_MMC(("waixing_zs_w, offset: %04x, data: %02x\n", offset, data));
8033	8063
8034		prg32(machine(), offset >> 3);
	8064	prg32(offset >> 3);
8035	8065
8036	8066	switch (data & 0x03)
8037	8067	{
8038		case 0: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
8039		case 1: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
8040		case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
8041		case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	8068	case 0: set_nt_mirroring(PPU_MIRROR_VERT); break;
	8069	case 1: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	8070	case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
	8071	case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
8042	8072	}
8043	8073	}
8044	8074
r18084	r18085
8061	8091	{
8062	8092	LOG_MMC(("waixing_dq8_w, offset: %04x, data: %02x\n", offset, data));
8063	8093
8064		prg32(machine(), offset >> 3);
	8094	prg32(offset >> 3);
8065	8095	}
8066	8096
8067	8097
r18084	r18085
8084	8114
8085	8115	LOG_MMC(("waixing_ps2_w, offset: %04x, data: %02x\n", offset, data));
8086	8116
8087		set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8117	set_nt_mirroring(BIT(data, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8088	8118
8089	8119	switch (offset & 0x0fff)
8090	8120	{
8091	8121	case 0x000:
8092		prg8_89(machine(), (map15_helper + 0) ^ map15_flip);
8093		prg8_ab(machine(), (map15_helper + 1) ^ map15_flip);
8094		prg8_cd(machine(), (map15_helper + 2) ^ map15_flip);
8095		prg8_ef(machine(), (map15_helper + 3) ^ map15_flip);
	8122	prg8_89((map15_helper + 0) ^ map15_flip);
	8123	prg8_ab((map15_helper + 1) ^ map15_flip);
	8124	prg8_cd((map15_helper + 2) ^ map15_flip);
	8125	prg8_ef((map15_helper + 3) ^ map15_flip);
8096	8126	break;
8097	8127	case 0x001:
8098	8128	map15_helper |= map15_flip;
8099		prg8_89(machine(), map15_helper);
8100		prg8_ab(machine(), map15_helper + 1);
8101		prg8_cd(machine(), map15_helper + 1);
8102		prg8_ef(machine(), map15_helper + 1);
	8129	prg8_89(map15_helper);
	8130	prg8_ab(map15_helper + 1);
	8131	prg8_cd(map15_helper + 1);
	8132	prg8_ef(map15_helper + 1);
8103	8133	break;
8104	8134	case 0x002:
8105	8135	map15_helper |= map15_flip;
8106		prg8_89(machine(), map15_helper);
8107		prg8_ab(machine(), map15_helper);
8108		prg8_cd(machine(), map15_helper);
8109		prg8_ef(machine(), map15_helper);
	8136	prg8_89(map15_helper);
	8137	prg8_ab(map15_helper);
	8138	prg8_cd(map15_helper);
	8139	prg8_ef(map15_helper);
8110	8140	break;
8111	8141	case 0x003:
8112	8142	map15_helper |= map15_flip;
8113		prg8_89(machine(), map15_helper);
8114		prg8_ab(machine(), map15_helper + 1);
8115		prg8_cd(machine(), map15_helper);
8116		prg8_ef(machine(), map15_helper + 1);
	8143	prg8_89(map15_helper);
	8144	prg8_ab(map15_helper + 1);
	8145	prg8_cd(map15_helper);
	8146	prg8_ef(map15_helper + 1);
8117	8147	break;
8118	8148	}
8119	8149	}
r18084	r18085
8140	8170	if (state->m_mmc_reg[0])
8141	8171	bank = ((bank & 0x01)) | ((bank >> 3) & 0x02) | ((bank >> 1) & 0x04) | ((bank << 2) & 0x18);
8142	8172
8143		prg8_x(machine, start, bank);
	8173	state->prg8_x(start, bank);
8144	8174	}
8145	8175
8146	8176	static void waixing_sec_chr_cb( running_machine &machine, int start, int bank, int source )
r18084	r18085
8151	8181	bank = ((bank & 0x03)) | ((bank >> 1) & 0x04) | ((bank >> 4) & 0x08) |
8152	8182	((bank >> 2) & 0x10) | ((bank << 3) & 0x20) | ((bank << 2) & 0xc0);
8153	8183
8154		chr1_x(machine, start, bank, source);
	8184	state->chr1_x(start, bank, source);
8155	8185	}
8156	8186
8157	8187	WRITE8_MEMBER(nes_carts_state::waixing_sec_l_w)
r18084	r18085
8186	8216	{
8187	8217	nes_state *state = machine.driver_data<nes_state>();
8188	8218
8189		chr4_0(machine, state->m_mmc_reg[0], state->m_mmc_reg[0] ? CHRRAM : CHRROM);
8190		chr4_4(machine, state->m_mmc_reg[1], state->m_mmc_reg[1] ? CHRRAM : CHRROM);
	8219	state->chr4_0(state->m_mmc_reg[0], state->m_mmc_reg[0] ? CHRRAM : CHRROM);
	8220	state->chr4_4(state->m_mmc_reg[1], state->m_mmc_reg[1] ? CHRRAM : CHRROM);
8191	8221	}
8192	8222
8193	8223	READ8_MEMBER(nes_carts_state::waixing_sh2_chr_r)
r18084	r18085
8205	8235
8206	8236	m_mmc_reg[offset >> 12] = chr_helper;
8207	8237	if (offset & 0x1000)
8208		chr4_4(machine(), m_mmc_reg[1], m_mmc_reg[1] ? CHRRAM : CHRROM);
	8238	chr4_4(m_mmc_reg[1], m_mmc_reg[1] ? CHRRAM : CHRROM);
8209	8239	else
8210		chr4_0(machine(), m_mmc_reg[0], m_mmc_reg[0] ? CHRRAM : CHRROM);
	8240	chr4_0(m_mmc_reg[0], m_mmc_reg[0] ? CHRRAM : CHRROM);
8211	8241
8212	8242	return val;
8213	8243	}
r18084	r18085
8229	8259	nes_state *state = machine.driver_data<nes_state>();
8230	8260
8231	8261	if (!(state->m_mmc_reg[0] & 0x80))
8232		prg8_x(machine, start, bank);
	8262	state->prg8_x(start, bank);
8233	8263	}
8234	8264
8235	8265	static void unl_8237_chr_cb( running_machine &machine, int start, int bank, int source )
r18084	r18085
8237	8267	nes_state *state = machine.driver_data<nes_state>();
8238	8268	bank |= ((state->m_mmc_reg[1] << 6) & 0x100);
8239	8269
8240		chr1_x(machine, start, bank, source);
	8270	state->chr1_x(start, bank, source);
8241	8271	}
8242	8272
8243	8273	WRITE8_MEMBER(nes_carts_state::unl_8237_l_w)
r18084	r18085
8251	8281	if (m_mmc_reg[0] & 0x80)
8252	8282	{
8253	8283	if (m_mmc_reg[0] & 0x20)
8254		prg32(machine(), (m_mmc_reg[0] & 0x0f) >> 1);
	8284	prg32((m_mmc_reg[0] & 0x0f) >> 1);
8255	8285	else
8256	8286	{
8257		prg16_89ab(machine(), m_mmc_reg[0] & 0x1f);
8258		prg16_cdef(machine(), m_mmc_reg[0] & 0x1f);
	8287	prg16_89ab(m_mmc_reg[0] & 0x1f);
	8288	prg16_cdef(m_mmc_reg[0] & 0x1f);
8259	8289	}
8260	8290	}
8261	8291	else
r18084	r18085
8278	8308	{
8279	8309	case 0x0000:
8280	8310	case 0x1000:
8281		set_nt_mirroring(machine(), (data | (data >> 7)) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8311	set_nt_mirroring((data | (data >> 7)) & 0x01 ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8282	8312	break;
8283	8313
8284	8314	case 0x2000:
r18084	r18085
8321	8351	static void unl_ax5705_set_prg( running_machine &machine )
8322	8352	{
8323	8353	nes_state *state = machine.driver_data<nes_state>();
8324		prg8_89(machine, state->m_mmc_prg_bank[0]);
8325		prg8_ab(machine, state->m_mmc_prg_bank[1]);
	8354	state->prg8_89(state->m_mmc_prg_bank[0]);
	8355	state->prg8_ab(state->m_mmc_prg_bank[1]);
8326	8356	}
8327	8357
8328	8358	WRITE8_MEMBER(nes_carts_state::unl_ax5705_w)
r18084	r18085
8337	8367	unl_ax5705_set_prg(machine());
8338	8368	break;
8339	8369	case 0x0008:
8340		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8370	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8341	8371	break;
8342	8372	case 0x2000:
8343	8373	m_mmc_prg_bank[1] = (data & 0x05) | ((data & 0x08) >> 2) | ((data & 0x02) << 2);
r18084	r18085
8350	8380	case 0x400a:
8351	8381	bank = ((offset & 0x4000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8352	8382	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8353		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	8383	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
8354	8384	break;
8355	8385	case 0x2009:
8356	8386	case 0x200b:
r18084	r18085
8358	8388	case 0x400b:
8359	8389	bank = ((offset & 0x4000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8360	8390	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x04) << 3) | ((data & 0x02) << 5) | ((data & 0x09) << 4);
8361		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	8391	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
8362	8392	break;
8363	8393	/* CHR banks 2, 3, 6, 7 */
8364	8394	case 0x4000:
r18084	r18085
8367	8397	case 0x6002:
8368	8398	bank = 2 + ((offset & 0x2000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8369	8399	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8370		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	8400	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
8371	8401	break;
8372	8402	case 0x4001:
8373	8403	case 0x4003:
r18084	r18085
8375	8405	case 0x6003:
8376	8406	bank = 2 + ((offset & 0x2000) ? 4 : 0) + ((offset & 0x0002) ? 1 : 0);
8377	8407	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0x0f) | ((data & 0x04) << 3) | ((data & 0x02) << 5) | ((data & 0x09) << 4);
8378		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], CHRROM);
	8408	chr1_x(bank, m_mmc_vrom_bank[bank], CHRROM);
8379	8409	break;
8380	8410	}
8381	8411	}
r18084	r18085
8394	8424	{
8395	8425	LOG_MMC(("unl_cc21_w offset: %04x, data: %02x\n", offset, data));
8396	8426
8397		set_nt_mirroring(machine(), BIT(data, 1) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
8398		chr8(machine(), (offset & 0x01), CHRROM);
	8427	set_nt_mirroring(BIT(data, 1) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	8428	chr8((offset & 0x01), CHRROM);
8399	8429	}
8400	8430
8401	8431	/*************************************************************
r18084	r18085
8498	8528	case 0x0000:
8499	8529	break;
8500	8530	case 0x2000:
8501		prg16_89ab(machine(), data);
	8531	prg16_89ab(data);
8502	8532	break;
8503	8533
8504	8534	// the part below works like VRC-2. how was the original board wired up?
r18084	r18085
8509	8539	case 0x100c:
8510	8540	switch (data & 0x03)
8511	8541	{
8512		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
8513		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
8514		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
8515		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	8542	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	8543	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	8544	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	8545	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
8516	8546	}
8517	8547	break;
8518	8548
r18084	r18085
8538	8568	else
8539	8569	m_mmc_vrom_bank[bank] = (m_mmc_vrom_bank[bank] & 0xf0) | (data & 0x0f);
8540	8570
8541		chr1_x(machine(), bank, m_mmc_vrom_bank[bank], m_mmc_chr_source);
	8571	chr1_x(bank, m_mmc_vrom_bank[bank], m_mmc_chr_source);
8542	8572	break;
8543	8573	case 0x7000:
8544	8574	m_IRQ_count_latch &= ~0x0f;
r18084	r18085
8582	8612	nes_state *state = machine.driver_data<nes_state>();
8583	8613
8584	8614	if (!(state->m_mmc_reg[0] & 0x80))
8585		prg8_x(machine, start, bank);
	8615	state->prg8_x(start, bank);
8586	8616	}
8587	8617
8588	8618	static void kof96_chr_cb( running_machine &machine, int start, int bank, int source )
r18084	r18085
8593	8623	if ((start & 0x04) == chr_page)
8594	8624	bank |= 0x100;
8595	8625
8596		chr1_x(machine, start, bank, source);
	8626	state->chr1_x(start, bank, source);
8597	8627	}
8598	8628
8599	8629	WRITE8_MEMBER(nes_carts_state::kof96_l_w)
r18084	r18085
8611	8641	new_bank = (m_mmc_reg[0] & 0x1f);
8612	8642
8613	8643	if (m_mmc_reg[0] & 0x20)
8614		prg32(machine(), new_bank >> 2);
	8644	prg32(new_bank >> 2);
8615	8645	else
8616	8646	{
8617		prg16_89ab(machine(), new_bank);
8618		prg16_cdef(machine(), new_bank);
	8647	prg16_89ab(new_bank);
	8648	prg16_cdef(new_bank);
8619	8649	}
8620	8650	}
8621	8651	else
r18084	r18085
8681	8711	m_mmc_reg[2] = 0;
8682	8712
8683	8713	if (data == 0x28)
8684		prg8_cd(machine(), 0x17);
	8714	prg8_cd(0x17);
8685	8715	else if (data == 0x2a)
8686		prg8_ab(machine(), 0x0f);
	8716	prg8_ab(0x0f);
8687	8717	break;
8688	8718
8689	8719	default:
r18084	r18085
8717	8747	case 0x0000:
8718	8748	switch (offset & 0x03)
8719	8749	{
8720		case 0x00: chr2_0(machine(), data, CHRROM); break;
8721		case 0x01: chr2_2(machine(), data, CHRROM); break;
8722		case 0x02: chr2_4(machine(), data, CHRROM); break;
8723		case 0x03: chr2_6(machine(), data, CHRROM); break;
	8750	case 0x00: chr2_0(data, CHRROM); break;
	8751	case 0x01: chr2_2(data, CHRROM); break;
	8752	case 0x02: chr2_4(data, CHRROM); break;
	8753	case 0x03: chr2_6(data, CHRROM); break;
8724	8754	}
8725	8755	break;
8726	8756	case 0x1000:
8727	8757	switch (offset & 0x03)
8728	8758	{
8729		case 0x00: prg8_89(machine(), data); break;
8730		case 0x01: prg8_ab(machine(), data); break;
	8759	case 0x00: prg8_89(data); break;
	8760	case 0x01: prg8_ab(data); break;
8731	8761	case 0x02: m_IRQ_enable = 0; m_IRQ_count = 0; break;
8732	8762	case 0x03: m_IRQ_enable = 1; m_IRQ_count = 7; break;
8733	8763	}
r18084	r18085
8752	8782
8753	8783	static void n625092_set_prg( running_machine &machine, UINT8 reg1, UINT8 reg2 )
8754	8784	{
	8785	nes_state *state = machine.driver_data<nes_state>();
8755	8786	UINT8 map221_helper1, map221_helper2;
8756	8787
8757	8788	map221_helper1 = !(reg1 & 0x01) ? reg2 :
r18084	r18085
8759	8790	map221_helper2 = !(reg1 & 0x01) ? reg2 :
8760	8791	(reg1 & 0x80) ? 0x07 : (reg2 & 0x06) | 0x01;
8761	8792
8762		prg16_89ab(machine, map221_helper1 | ((reg1 & 0x70) >> 1));
8763		prg16_cdef(machine, map221_helper2 | ((reg1 & 0x70) >> 1));
	8793	state->prg16_89ab(map221_helper1 | ((reg1 & 0x70) >> 1));
	8794	state->prg16_cdef(map221_helper2 | ((reg1 & 0x70) >> 1));
8764	8795	}
8765	8796
8766	8797	WRITE8_MEMBER(nes_carts_state::n625092_w)
r18084	r18085
8769	8800
8770	8801	if (offset < 0x4000)
8771	8802	{
8772		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8803	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8773	8804	offset = (offset >> 1) & 0xff;
8774	8805
8775	8806	if (m_mmc_latch1 != offset)
r18084	r18085
8827	8858	switch (offset)
8828	8859	{
8829	8860	case 0x0000:
8830		prg8_89(machine(), data);
	8861	prg8_89(data);
8831	8862	break;
8832	8863	case 0x0001:
8833		prg8_ab(machine(), data);
	8864	prg8_ab(data);
8834	8865	break;
8835	8866	case 0x0002:
8836	8867	//      m_mmc_prg_bank[offset & 0x02] = data;
8837		prg8_cd(machine(), data);
	8868	prg8_cd(data);
8838	8869	break;
8839	8870	case 0x1000:
8840	8871	case 0x1001:
r18084	r18085
8845	8876	case 0x1006:
8846	8877	case 0x1007:
8847	8878	//      m_mmc_vrom_bank[offset & 0x07] = data;
8848		chr1_x(machine(), offset & 0x07, data, CHRROM);
	8879	chr1_x(offset & 0x07, data, CHRROM);
8849	8880	break;
8850	8881	case 0x4002:
8851	8882	m_IRQ_enable = 0;
r18084	r18085
8857	8888	m_IRQ_count = data;
8858	8889	break;
8859	8890	case 0x5001:
8860		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8891	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8861	8892	break;
8862	8893	}
8863	8894	}
r18084	r18085
8881	8912
8882	8913	LOG_MMC(("smb2j_w, offset: %04x, data: %02x\n", offset, data));
8883	8914
8884		set_nt_mirroring(machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	8915	set_nt_mirroring((offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
8885	8916
8886	8917	if (offset & 0x0800)
8887	8918	{
r18084	r18085
8895	8926	else
8896	8927	{
8897	8928	LOG_MMC(("smb2j_w, selecting upper 16KB bank of #%02x\n", bank));
8898		prg16_cdef(machine(), 2 * bank + 1);
	8929	prg16_cdef(2 * bank + 1);
8899	8930	}
8900	8931	}
8901	8932	else
r18084	r18085
8908	8939	else
8909	8940	{
8910	8941	LOG_MMC(("smb2j_w, selecting lower 16KB bank of #%02x\n", bank));
8911		prg16_89ab(machine(), 2 * bank);
	8942	prg16_89ab(2 * bank);
8912	8943	}
8913	8944	}
8914	8945	}
r18084	r18085
8924	8955	else
8925	8956	{
8926	8957	LOG_MMC(("smb2j_w, selecting 32KB bank #%02x\n", bank));
8927		prg32(machine(), bank);
	8958	prg32(bank);
8928	8959	}
8929	8960	}
8930	8961	}
r18084	r18085
8972	9003	{
8973	9004	case 0x020:
8974	9005	prg = (data & 0x08) | ((data & 0x06) >> 1) | ((data & 0x01) << 2);
8975		prg8_cd(machine(), prg);
	9006	prg8_cd(prg);
8976	9007	break;
8977	9008	case 0x120:
8978	9009	m_IRQ_enable = data & 0x01;
r18084	r18085
8987	9018	LOG_MMC(("smb2jb_extra_w, offset: %04x, data: %02x\n", offset, data));
8988	9019
8989	9020	prg = (data & 0x08) | ((data & 0x06) >> 1) | ((data & 0x01) << 2);
8990		prg8_cd(machine(), prg);
	9021	prg8_cd(prg);
8991	9022	}
8992	9023
8993	9024	/*************************************************************
r18084	r18085
9005	9036	static void unl_sf3_set_chr( running_machine &machine, UINT8 chr_source, int chr_base, int chr_mask )
9006	9037	{
9007	9038	nes_state *state = machine.driver_data<nes_state>();
9008		chr4_0(machine, chr_base | ((state->m_mmc_vrom_bank[0] >> 1) & chr_mask), chr_source);
9009		chr2_4(machine, chr_base | (state->m_mmc_vrom_bank[1] & chr_mask), chr_source);
9010		chr2_6(machine, chr_base | (state->m_mmc_vrom_bank[2] & chr_mask), chr_source);
	9039	state->chr4_0(chr_base | ((state->m_mmc_vrom_bank[0] >> 1) & chr_mask), chr_source);
	9040	state->chr2_4(chr_base | (state->m_mmc_vrom_bank[1] & chr_mask), chr_source);
	9041	state->chr2_6(chr_base | (state->m_mmc_vrom_bank[2] & chr_mask), chr_source);
9011	9042	}
9012	9043
9013	9044	WRITE8_MEMBER(nes_carts_state::unl_sf3_w)
r18084	r18085
9074	9105	switch (offset)
9075	9106	{
9076	9107	case 0x1ef1:   /* 0x5ff1 */
9077		prg32(machine(), data >> 1);
	9108	prg32(data >> 1);
9078	9109	break;
9079	9110	case 0x1ef2:   /* 0x5ff2 */
9080		chr8(machine(), data, CHRROM);
	9111	chr8(data, CHRROM);
9081	9112	break;
9082	9113	}
9083	9114	}
r18084	r18085
9094	9125	static void racmate_update_banks( running_machine &machine )
9095	9126	{
9096	9127	nes_state *state = machine.driver_data<nes_state>();
9097		chr4_4(machine, state->m_mmc_latch1 & 0x0f, state->m_mmc_chr_source);
9098		prg16_89ab(machine, state->m_mmc_latch1 >> 1);
	9128	state->chr4_4(state->m_mmc_latch1 & 0x0f, state->m_mmc_chr_source);
	9129	state->prg16_89ab(state->m_mmc_latch1 >> 1);
9099	9130	}
9100	9131
9101	9132	WRITE8_MEMBER(nes_carts_state::unl_racmate_w)
r18084	r18085
9132	9163	{
9133	9164	m_mmc_reg[(offset >> 8) & 3] = data;
9134	9165	bank = ((m_mmc_reg[2] & 0x0f) << 4) | BIT(m_mmc_reg[1], 1) | (m_mmc_reg[0] & 0x0e);
9135		prg32(machine(), bank);
9136		chr8(machine(), 0, CHRRAM);
	9166	prg32(bank);
	9167	chr8(0, CHRRAM);
9137	9168	}
9138	9169	}
9139	9170
r18084	r18085
9188	9219	switch (offset & 0x03)
9189	9220	{
9190	9221	case 0x00:
9191		prg8_67(machine(), data);
	9222	prg8_67(data);
9192	9223	break;
9193	9224	case 0x01:
9194		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9225	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9195	9226	break;
9196	9227	case 0x02:
9197	9228	/* Check if IRQ is being enabled */
r18084	r18085
9253	9284	m_IRQ_enable = 1;
9254	9285	break;
9255	9286	case 0x6000:
9256		prg8_cd(machine(), data);
	9287	prg8_cd(data);
9257	9288	break;
9258	9289	}
9259	9290	}
r18084	r18085
9273	9304	WRITE8_MEMBER(nes_carts_state::whirl2706_w)
9274	9305	{
9275	9306	LOG_MMC(("whirl2706_w, offset: %04x, data: %02x\n", offset, data));
9276		prg8_67(machine(), data);
	9307	prg8_67(data);
9277	9308	}
9278	9309
9279	9310	/*************************************************************
r18084	r18085
9294	9325	offset += 0x100;
9295	9326
9296	9327	if ((offset & 0x43c0) == 0x41c0)
9297		prg8_67(machine(), data & 0x07);
	9328	prg8_67(data & 0x07);
9298	9329	}
9299	9330
9300	9331	/*************************************************************
r18084	r18085
9332	9363	{
9333	9364	case 0x00:
9334	9365	case 0x02:
9335		chr1_x(machine(), offset & 0x07, data & 0xfe, CHRROM);
	9366	chr1_x(offset & 0x07, data & 0xfe, CHRROM);
9336	9367	break;
9337	9368	case 0x01:
9338	9369	case 0x03:
9339		chr1_x(machine(), offset & 0x07, data | 0x01, CHRROM);
	9370	chr1_x(offset & 0x07, data | 0x01, CHRROM);
9340	9371	break;
9341	9372	case 0x04: case 0x05:
9342	9373	case 0x06: case 0x07:
9343		chr1_x(machine(), offset & 0x07, data, CHRROM);
	9374	chr1_x(offset & 0x07, data, CHRROM);
9344	9375	break;
9345	9376	case 0x08:
9346		prg8_89(machine(), data | 0x10);
	9377	prg8_89(data | 0x10);
9347	9378	break;
9348	9379	case 0x09:
9349		prg8_ab(machine(), data);
	9380	prg8_ab(data);
9350	9381	break;
9351	9382	case 0x0a:
9352		prg8_cd(machine(), data);
	9383	prg8_cd(data);
9353	9384	break;
9354	9385	case 0x0b:
9355		prg8_ef(machine(), data | 0x10);
	9386	prg8_ef(data | 0x10);
9356	9387	break;
9357	9388	case 0x0c:
9358		set_nt_mirroring(machine(), BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9389	set_nt_mirroring(BIT(data, 0) ?  PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9359	9390	break;
9360	9391	case 0x0d:
9361	9392	m_IRQ_count = 0;
r18084	r18085
9407	9438	switch (offset & 0x7003)
9408	9439	{
9409	9440	case 0x0000:
9410		prg8_89(machine(), data);
	9441	prg8_89(data);
9411	9442	break;
9412	9443	case 0x1000:
9413		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9444	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9414	9445	break;
9415	9446	case 0x2000:
9416		prg8_ab(machine(), data);
	9447	prg8_ab(data);
9417	9448	break;
9418	9449	case 0x3000:
9419	9450	case 0x3002:
r18084	r18085
9424	9455	case 0x6000:
9425	9456	case 0x6002:
9426	9457	bank = ((offset & 0x7000) - 0x3000) / 0x0800 + ((offset & 0x0002) >> 3);
9427		chr1_x(machine(), bank, data, CHRROM);
	9458	chr1_x(bank, data, CHRROM);
9428	9459	break;
9429	9460	case 0x7000:
9430	9461	m_IRQ_count = data;
r18084	r18085
9502	9533	if (state->m_mmc_reg[0] & 0x03)
9503	9534	bank = (bank & (0x3f >> (state->m_mmc_reg[0] & 0x03))) | (state->m_mmc_reg[1] << 1);
9504	9535
9505		prg8_x(machine, start, bank);
	9536	state->prg8_x(start, bank);
9506	9537	}
9507	9538	}
9508	9539
r18084	r18085
9511	9542	nes_state *state = machine.driver_data<nes_state>();
9512	9543
9513	9544	if (!(state->m_mmc_reg[0] & 0x40) && (!(state->m_mmc_reg[3] & 0x02) || (start != 1 && start != 3)))
9514		chr1_x(machine, start, ((state->m_mmc_reg[2] & 0x7f) << 3) | bank, source);
	9545	state->chr1_x(start, ((state->m_mmc_reg[2] & 0x7f) << 3) | bank, source);
9515	9546	}
9516	9547
9517	9548	#endif
r18084	r18085
9526	9557	if (!(state->m_mmc_reg[0] & 0x03))
9527	9558	bank = (bank & mask) | ((state->m_mmc_reg[1]  & (0x7f ^ mask)) << 1);
9528	9559
9529		prg8_x(machine, start, bank);
	9560	state->prg8_x(start, bank);
9530	9561	}
9531	9562	}
9532	9563
r18084	r18085
9535	9566	nes_state *state = machine.driver_data<nes_state>();
9536	9567
9537	9568	if (!(state->m_mmc_reg[0] & 0x40) && (!(state->m_mmc_reg[3] & 0x02) || (start != 1 && start != 3)))
9538		chr1_x(machine, start, ((state->m_mmc_reg[2] & 0x7f) << 3) | bank, source);
	9569	state->chr1_x(start, ((state->m_mmc_reg[2] & 0x7f) << 3) | bank, source);
9539	9570	}
9540	9571
9541	9572	static void fk23c_set_prg( running_machine &machine )
r18084	r18085
9543	9574	nes_state *state = machine.driver_data<nes_state>();
9544	9575
9545	9576	if ((state->m_mmc_reg[0] & 0x07) == 4)
9546		prg32(machine, (state->m_mmc_reg[1] & 0x7f) >> 1);
	9577	state->prg32((state->m_mmc_reg[1] & 0x7f) >> 1);
9547	9578	else if ((state->m_mmc_reg[0] & 0x07) == 3)
9548	9579	{
9549		prg16_89ab(machine, state->m_mmc_reg[1] & 0x7f);
9550		prg16_cdef(machine, state->m_mmc_reg[1] & 0x7f);
	9580	state->prg16_89ab(state->m_mmc_reg[1] & 0x7f);
	9581	state->prg16_cdef(state->m_mmc_reg[1] & 0x7f);
9551	9582	}
9552	9583	else
9553	9584	{
9554	9585	if (state->m_mmc_reg[3] & 0x02)
9555	9586	{
9556		prg8_cd(machine, state->m_mmc_reg[4]);
9557		prg8_ef(machine, state->m_mmc_reg[5]);
	9587	state->prg8_cd(state->m_mmc_reg[4]);
	9588	state->prg8_ef(state->m_mmc_reg[5]);
9558	9589	}
9559	9590	else
9560	9591	mmc3_set_prg(machine, state->m_mmc_prg_base, state->m_mmc_prg_mask);
r18084	r18085
9566	9597	nes_state *state = machine.driver_data<nes_state>();
9567	9598
9568	9599	if (state->m_mmc_reg[0] & 0x40)
9569		chr8(machine, state->m_mmc_reg[2] | state->m_mmc_cmd1, state->m_mmc_chr_source);
	9600	state->chr8(state->m_mmc_reg[2] | state->m_mmc_cmd1, state->m_mmc_chr_source);
9570	9601	else
9571	9602	{
9572	9603	if (state->m_mmc_reg[3] & 0x02)
9573	9604	{
9574	9605	int base = (state->m_mmc_reg[2] & 0x7f) << 3;
9575		chr1_x(machine, 1, base | state->m_mmc_reg[6], state->m_mmc_chr_source);
9576		chr1_x(machine, 3, base | state->m_mmc_reg[7], state->m_mmc_chr_source);
	9606	state->chr1_x(1, base | state->m_mmc_reg[6], state->m_mmc_chr_source);
	9607	state->chr1_x(3, base | state->m_mmc_reg[7], state->m_mmc_chr_source);
9577	9608	}
9578	9609	else
9579	9610	mmc3_set_chr(machine, state->m_mmc_chr_source, state->m_mmc_chr_base, state->m_mmc_chr_mask);
r18084	r18085
9627	9658	break;
9628	9659
9629	9660	case 0x2000:
9630		set_nt_mirroring(machine(), data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9661	set_nt_mirroring(data ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9631	9662	break;
9632	9663
9633	9664	default:
r18084	r18085
9657	9688	if (state->m_mmc_reg[0] & 0x80)
9658	9689	{
9659	9690	if (state->m_mmc_reg[1] & 0x80)
9660		prg32(machine, helper1);
	9691	state->prg32(helper1);
9661	9692	else
9662	9693	{
9663		prg16_89ab(machine, helper2);
9664		prg16_cdef(machine, helper2);
	9694	state->prg16_89ab(helper2);
	9695	state->prg16_cdef(helper2);
9665	9696	}
9666	9697	}
9667	9698	else
9668		prg16_cdef(machine, helper2);
	9699	state->prg16_cdef(helper2);
9669	9700	}
9670	9701
9671	9702	WRITE8_MEMBER(nes_carts_state::bmc_64in1nr_l_w)
r18084	r18085
9681	9712	case 0x1003:
9682	9713	m_mmc_reg[offset & 0x03] = data;
9683	9714	bmc_64in1nr_set_prg(machine());
9684		chr8(machine(), ((m_mmc_reg[0] >> 1) & 0x03) | (m_mmc_reg[2] << 2), CHRROM);
	9715	chr8(((m_mmc_reg[0] >> 1) & 0x03) | (m_mmc_reg[2] << 2), CHRROM);
9685	9716	break;
9686	9717	}
9687	9718	if (offset == 0x1000)   /* reg[0] also sets mirroring */
9688		set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9719	set_nt_mirroring(BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9689	9720	}
9690	9721
9691	9722	WRITE8_MEMBER(nes_carts_state::bmc_64in1nr_w)
r18084	r18085
9709	9740	{
9710	9741	LOG_MMC(("bmc_190in1_w offset: %04x, data: %02x\n", offset, data));
9711	9742
9712		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9743	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9713	9744	offset >>= 2;
9714		prg16_89ab(machine(), offset);
9715		prg16_cdef(machine(), offset);
9716		chr8(machine(), offset, CHRROM);
	9745	prg16_89ab(offset);
	9746	prg16_cdef(offset);
	9747	chr8(offset, CHRROM);
9717	9748	}
9718	9749
9719	9750	/*************************************************************
r18084	r18085
9732	9763	LOG_MMC(("bmc_a65as_w offset: %04x, data: %02x\n", offset, data));
9733	9764
9734	9765	if (data & 0x80)
9735		set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
	9766	set_nt_mirroring(BIT(data, 5) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
9736	9767	else
9737		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9768	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9738	9769
9739	9770	if (data & 0x40)
9740		prg32(machine(), data >> 1);
	9771	prg32(data >> 1);
9741	9772	else
9742	9773	{
9743		prg16_89ab(machine(), helper | (data & 0x07));
9744		prg16_cdef(machine(), helper | 0x07);
	9774	prg16_89ab(helper | (data & 0x07));
	9775	prg16_cdef(helper | 0x07);
9745	9776	}
9746	9777	}
9747	9778
r18084	r18085
9760	9791	{
9761	9792	LOG_MMC(("bmc_gs2004_w offset: %04x, data: %02x\n", offset, data));
9762	9793
9763		prg32(machine(), data);
	9794	prg32(data);
9764	9795	}
9765	9796
9766	9797	/*************************************************************
r18084	r18085
9779	9810	LOG_MMC(("bmc_gs2013_w offset: %04x, data: %02x\n", offset, data));
9780	9811
9781	9812	if (data & 0x08)
9782		prg32(machine(), data & 0x09);
	9813	prg32(data & 0x09);
9783	9814	else
9784		prg32(machine(), data & 0x07);
	9815	prg32(data & 0x07);
9785	9816	}
9786	9817
9787	9818	/*************************************************************
r18084	r18085
9802	9833	int prg_mask = masks[state->m_mmc_reg[0] & 0x07];
9803	9834
9804	9835	bank = prg_base | (bank & prg_mask);
9805		prg8_x(machine, start, bank);
	9836	state->prg8_x(start, bank);
9806	9837	}
9807	9838
9808	9839	static void bmc_s24in1sc03_chr_cb( running_machine &machine, int start, int bank, int source )
r18084	r18085
9811	9842	UINT8 chr = BIT(state->m_mmc_reg[0], 5) ? CHRRAM : CHRROM;
9812	9843	int chr_base = (state->m_mmc_reg[2] << 3) & 0xf00;
9813	9844
9814		chr1_x(machine, start, chr_base | bank, chr);
	9845	state->chr1_x(start, chr_base | bank, chr);
9815	9846	}
9816	9847
9817	9848	WRITE8_MEMBER(nes_carts_state::bmc_s24in1sc03_l_w)
r18084	r18085
9857	9888	if (m_mmc_latch2 || offset == 0)
9858	9889	{
9859	9890	m_mmc_latch1 = (m_mmc_latch1 & 0x38) | (data & 0x07);
9860		prg16_89ab(machine(), m_mmc_latch1);
	9891	prg16_89ab(m_mmc_latch1);
9861	9892	}
9862	9893	else
9863	9894	{
9864	9895	m_mmc_latch2 = 1;
9865		set_nt_mirroring(machine(), BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9896	set_nt_mirroring(BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9866	9897	mmc_helper = ((offset >> 3) & 0x20) | ((offset >> 2) & 0x18);
9867	9898	m_mmc_latch1 = mmc_helper | (m_mmc_latch1 & 0x07);
9868		prg16_89ab(machine(), m_mmc_latch1);
9869		prg16_cdef(machine(), mmc_helper | 0x07);
	9899	prg16_89ab(m_mmc_latch1);
	9900	prg16_cdef(mmc_helper | 0x07);
9870	9901	}
9871	9902	}
9872	9903
r18084	r18085
9894	9925	if (!m_mmc_latch1)
9895	9926	{
9896	9927	m_mmc_latch1 = data & 0x20;
9897		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	9928	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9898	9929	mmc_helper = (~data & 0x08) >> 3;
9899		prg16_89ab(machine(), data & ~mmc_helper);
9900		prg16_cdef(machine(), data |  mmc_helper);
	9930	prg16_89ab(data & ~mmc_helper);
	9931	prg16_cdef(data |  mmc_helper);
9901	9932	}
9902	9933	break;
9903	9934	case 1:
9904	9935	if (!m_mmc_latch1)
9905	9936	{
9906		chr8(machine(), data, CHRROM);
	9937	chr8(data, CHRROM);
9907	9938	}
9908	9939	break;
9909	9940	}
r18084	r18085
9931	9962	{
9932	9963	LOG_MMC(("novel1_w, offset: %04x, data: %02x\n", offset, data));
9933	9964
9934		prg32(machine(), offset & 0x03);
9935		chr8(machine(), offset & 0x07, CHRROM);
	9965	prg32(offset & 0x03);
	9966	chr8(offset & 0x07, CHRROM);
9936	9967	}
9937	9968
9938	9969	WRITE8_MEMBER(nes_carts_state::novel2_w)
9939	9970	{
9940	9971	LOG_MMC(("novel2_w, offset: %04x, data: %02x\n", offset, data));
9941	9972
9942		prg32(machine(), offset >> 1);
9943		chr8(machine(), offset >> 3, CHRROM);
	9973	prg32(offset >> 1);
	9974	chr8(offset >> 3, CHRROM);
9944	9975	}
9945	9976
9946	9977	/*************************************************************
r18084	r18085
9966	9997	m_mmc_latch1 = data;
9967	9998
9968	9999	if (m_mmc_latch2 & 0x80)
9969		prg32(machine(), 2 | (m_mmc_latch2 >> 6));
	10000	prg32(2 | (m_mmc_latch2 >> 6));
9970	10001	else
9971	10002	{
9972		prg16_89ab(machine(), (m_mmc_latch2 >> 5) & 0x03);
9973		prg16_cdef(machine(), (m_mmc_latch2 >> 5) & 0x03);
	10003	prg16_89ab((m_mmc_latch2 >> 5) & 0x03);
	10004	prg16_cdef((m_mmc_latch2 >> 5) & 0x03);
9974	10005	}
9975	10006
9976		set_nt_mirroring(machine(), (m_mmc_latch2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10007	set_nt_mirroring((m_mmc_latch2 & 0x08) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
9977	10008
9978		chr8(machine(), (m_mmc_latch1 & 0x03) | (m_mmc_latch2 & 0x07) | ((m_mmc_latch2 & 0x10) >> 1), CHRROM);
	10009	chr8((m_mmc_latch1 & 0x03) | (m_mmc_latch2 & 0x07) | ((m_mmc_latch2 & 0x10) >> 1), CHRROM);
9979	10010	}
9980	10011
9981	10012
r18084	r18085
9995	10026	WRITE8_MEMBER(nes_carts_state::sng32_w)
9996	10027	{
9997	10028	LOG_MMC(("sng32_w, offset: %04x, data: %02x\n", offset, data));
9998		prg32(machine(), data);
	10029	prg32(data);
9999	10030	}
10000	10031
10001	10032	/*************************************************************
r18084	r18085
10016	10047	UINT8 bank = (offset & 0x40) ? 0 : 1;
10017	10048	LOG_MMC(("bmc_gkb_w, offset: %04x, data: %02x\n", offset, data));
10018	10049
10019		prg16_89ab(machine(), offset & ~bank);
10020		prg16_cdef(machine(), offset | bank);
10021		chr8(machine(), offset >> 3, m_mmc_chr_source);
10022		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10050	prg16_89ab(offset & ~bank);
	10051	prg16_cdef(offset | bank);
	10052	chr8(offset >> 3, m_mmc_chr_source);
	10053	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10023	10054	}
10024	10055
10025	10056	/*************************************************************
r18084	r18085
10039	10070	{
10040	10071	LOG_MMC(("bmc_super700in1_w, offset :%04x, data: %02x\n", offset, data));
10041	10072
10042		chr8(machine(), ((offset & 0x1f) << 2) | (data & 0x03), CHRROM);
	10073	chr8(((offset & 0x1f) << 2) | (data & 0x03), CHRROM);
10043	10074
10044	10075	if (offset & 0x20)
10045	10076	{
10046		prg16_89ab(machine(), (offset & 0x40) | ((offset >> 8) & 0x3f));
10047		prg16_cdef(machine(), (offset & 0x40) | ((offset >> 8) & 0x3f));
	10077	prg16_89ab((offset & 0x40) | ((offset >> 8) & 0x3f));
	10078	prg16_cdef((offset & 0x40) | ((offset >> 8) & 0x3f));
10048	10079	}
10049	10080	else
10050	10081	{
10051		prg32(machine(), ((offset & 0x40) | ((offset >> 8) & 0x3f)) >> 1);
	10082	prg32(((offset & 0x40) | ((offset >> 8) & 0x3f)) >> 1);
10052	10083	}
10053	10084
10054		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10085	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10055	10086	}
10056	10087
10057	10088	/*************************************************************
r18084	r18085
10071	10102	{
10072	10103	LOG_MMC(("bmc_36in1_w, offset: %04x, data: %02x\n", offset, data));
10073	10104
10074		prg16_89ab(machine(), offset & 0x07);
10075		prg16_cdef(machine(), offset & 0x07);
10076		chr8(machine(), offset & 0x07, CHRROM);
	10105	prg16_89ab(offset & 0x07);
	10106	prg16_cdef(offset & 0x07);
	10107	chr8(offset & 0x07, CHRROM);
10077	10108
10078		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10109	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10079	10110	}
10080	10111
10081	10112	/*************************************************************
r18084	r18085
10095	10126	{
10096	10127	LOG_MMC(("bmc_21in1_w, offset: %04x, data: %02x\n", offset, data));
10097	10128
10098		prg32(machine(), offset & 0x03);
10099		chr8(machine(), offset & 0x03, CHRROM);
	10129	prg32(offset & 0x03);
	10130	chr8(offset & 0x03, CHRROM);
10100	10131	}
10101	10132
10102	10133	/*************************************************************
r18084	r18085
10118	10149
10119	10150	LOG_MMC(("bmc_150in1_w, offset: %04x, data: %02x\n", offset, data));
10120	10151
10121		prg16_89ab(machine(), bank);
10122		prg16_cdef(machine(), bank + (((bank & 0x06) == 0x06) ? 1 : 0));
10123		chr8(machine(), bank, CHRROM);
	10152	prg16_89ab(bank);
	10153	prg16_cdef(bank + (((bank & 0x06) == 0x06) ? 1 : 0));
	10154	chr8(bank, CHRROM);
10124	10155
10125		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
	10156	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
10126	10157	}
10127	10158
10128	10159	/*************************************************************
r18084	r18085
10142	10173	{
10143	10174	LOG_MMC(("bmc_35in1_w, offset: %04x, data: %02x\n", offset, data));
10144	10175
10145		prg16_89ab(machine(), (data >> 2) & 0x03);
10146		prg16_cdef(machine(), (data >> 2) & 0x03);
10147		chr8(machine(), data & 0x03, CHRROM);
	10176	prg16_89ab((data >> 2) & 0x03);
	10177	prg16_cdef((data >> 2) & 0x03);
	10178	chr8(data & 0x03, CHRROM);
10148	10179	}
10149	10180
10150	10181	/*************************************************************
r18084	r18085
10166	10197
10167	10198	LOG_MMC(("bmc_64in1_w, offset: %04x, data: %02x\n", offset, data));
10168	10199
10169		prg16_89ab(machine(), offset & ~bank);
10170		prg16_cdef(machine(), offset | bank);
10171		chr8(machine(), offset & ~bank, CHRROM);
	10200	prg16_89ab(offset & ~bank);
	10201	prg16_cdef(offset | bank);
	10202	chr8(offset & ~bank, CHRROM);
10172	10203
10173		set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
	10204	set_nt_mirroring(BIT(data, 4) ? PPU_MIRROR_HORZ: PPU_MIRROR_VERT);
10174	10205	}
10175	10206
10176	10207	/*************************************************************
r18084	r18085
10218	10249	{
10219	10250	LOG_MMC(("bmc_hik300_w, offset: %04x, data: %02x\n", offset, data));
10220	10251
10221		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10222		chr8(machine(), offset, CHRROM);
	10252	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10253	chr8(offset, CHRROM);
10223	10254
10224	10255	if (offset < 0x4000)
10225	10256	{
10226		prg16_89ab(machine(), offset);
10227		prg16_cdef(machine(), offset);
	10257	prg16_89ab(offset);
	10258	prg16_cdef(offset);
10228	10259	}
10229	10260	else
10230		prg32(machine(), offset >> 1);
	10261	prg32(offset >> 1);
10231	10262	}
10232	10263
10233	10264	/*************************************************************
r18084	r18085
10247	10278	{
10248	10279	LOG_MMC(("supergun20in1_w, offset: %04x, data: %02x\n", offset, data));
10249	10280
10250		prg16_89ab(machine(), offset >> 2);
10251		prg16_cdef(machine(), offset >> 2);
10252		chr8(machine(), offset, CHRROM);
	10281	prg16_89ab(offset >> 2);
	10282	prg16_cdef(offset >> 2);
	10283	chr8(offset, CHRROM);
10253	10284	}
10254	10285
10255	10286	/*************************************************************
r18084	r18085
10273	10304
10274	10305	LOG_MMC(("bmc_72in1_w, offset: %04x, data: %02x\n", offset, data));
10275	10306
10276		chr8(machine(), offset, CHRROM);
10277		set_nt_mirroring(machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10307	chr8(offset, CHRROM);
	10308	set_nt_mirroring((offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10278	10309
10279	10310	hi_bank = offset & 0x40;
10280	10311	size_16 = offset & 0x1000;
r18084	r18085
10285	10316	if (hi_bank)
10286	10317	bank ++;
10287	10318
10288		prg16_89ab(machine(), bank);
10289		prg16_cdef(machine(), bank);
	10319	prg16_89ab(bank);
	10320	prg16_cdef(bank);
10290	10321	}
10291	10322	else
10292		prg32(machine(), bank);
	10323	prg32(bank);
10293	10324	}
10294	10325
10295	10326	/*************************************************************
r18084	r18085
10319	10350	else
10320	10351	m_mmc_latch1 = data;
10321	10352
10322		set_nt_mirroring(machine(), BIT(m_mmc_latch1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10353	set_nt_mirroring(BIT(m_mmc_latch1, 6) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10323	10354
10324	10355	hi_bank = m_mmc_latch1 & 0x01;
10325	10356	size_16 = m_mmc_latch1 & 0x20;
r18084	r18085
10331	10362	if (hi_bank)
10332	10363	bank ++;
10333	10364
10334		prg16_89ab(machine(), bank);
10335		prg16_cdef(machine(), bank);
	10365	prg16_89ab(bank);
	10366	prg16_cdef(bank);
10336	10367	}
10337	10368	else
10338		prg32(machine(), bank);
	10369	prg32(bank);
10339	10370	}
10340	10371
10341	10372	/*************************************************************
r18084	r18085
10368	10399	if (hi_bank)
10369	10400	bank ++;
10370	10401
10371		prg16_89ab(machine(), bank);
10372		prg16_cdef(machine(), bank);
	10402	prg16_89ab(bank);
	10403	prg16_cdef(bank);
10373	10404	}
10374	10405	else
10375		prg32(machine(), bank);
	10406	prg32(bank);
10376	10407
10377	10408	if (!(offset & 0x80))
10378	10409	{
10379	10410	if (offset & 0x200)
10380		prg16_cdef(machine(), ((bank << 1) & 0x38) + 7);
	10411	prg16_cdef(((bank << 1) & 0x38) + 7);
10381	10412	else
10382		prg16_cdef(machine(), ((bank << 1) & 0x38));
	10413	prg16_cdef(((bank << 1) & 0x38));
10383	10414	}
10384	10415
10385		set_nt_mirroring(machine(), BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10416	set_nt_mirroring(BIT(data, 1) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10386	10417	}
10387	10418
10388	10419	/*************************************************************
r18084	r18085
10402	10433	{
10403	10434	LOG_MMC(("bmc_31in1_w, offset: %04x, data: %02x\n", offset, data));
10404	10435
10405		set_nt_mirroring(machine(), BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10406		chr8(machine(), offset, CHRROM);
	10436	set_nt_mirroring(BIT(data, 5) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10437	chr8(offset, CHRROM);
10407	10438
10408	10439	if ((offset & 0x1e) == 0)
10409	10440	{
10410		prg16_89ab(machine(), 0);
10411		prg16_89ab(machine(), 1);
	10441	prg16_89ab(0);
	10442	prg16_89ab(1);
10412	10443	}
10413	10444	else
10414	10445	{
10415		prg16_89ab(machine(), offset & 0x1f);
10416		prg16_89ab(machine(), offset & 0x1f);
	10446	prg16_89ab(offset & 0x1f);
	10447	prg16_89ab(offset & 0x1f);
10417	10448	}
10418	10449	}
10419	10450
r18084	r18085
10437	10468
10438	10469	if (1)   // this should flip at reset
10439	10470	{
10440		prg16_89ab(machine(), data & 0x07);
	10471	prg16_89ab(data & 0x07);
10441	10472	}
10442	10473	else
10443	10474	{
10444	10475	if (data & 0x20)
10445	10476	{
10446		prg16_89ab(machine(), (data & 0x1f) + 8);
10447		prg16_cdef(machine(), (data & 0x1f) + 8);
	10477	prg16_89ab((data & 0x1f) + 8);
	10478	prg16_cdef((data & 0x1f) + 8);
10448	10479	}
10449	10480	else
10450	10481	{
10451		prg16_89ab(machine(), (data & 0x1f) + 8);
10452		prg16_cdef(machine(), (data & 0x1f) + 9);
	10482	prg16_89ab((data & 0x1f) + 8);
	10483	prg16_cdef((data & 0x1f) + 9);
10453	10484	}
10454		set_nt_mirroring(machine(), BIT(data, 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	10485	set_nt_mirroring(BIT(data, 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
10455	10486	}
10456	10487	}
10457	10488
r18084	r18085
10472	10503	{
10473	10504	LOG_MMC(("bmc_20in1_w, offset: %04x, data: %02x\n", offset, data));
10474	10505
10475		set_nt_mirroring(machine(), BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10506	set_nt_mirroring(BIT(data, 7) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10476	10507
10477		prg16_89ab(machine(), (offset & 0x1e));
10478		prg16_cdef(machine(), (offset & 0x1e) | ((offset & 0x20) ? 1 : 0));
	10508	prg16_89ab((offset & 0x1e));
	10509	prg16_cdef((offset & 0x1e) | ((offset & 0x20) ? 1 : 0));
10479	10510	}
10480	10511
10481	10512	/*************************************************************
r18084	r18085
10498	10529
10499	10530	LOG_MMC(("bmc_110in1_w, offset: %04x, data: %02x\n", offset, data));
10500	10531
10501		set_nt_mirroring(machine(), (offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10502		prg16_89ab(machine(), map255_helper1 & ~map255_helper2);
10503		prg16_cdef(machine(), map255_helper1 | map255_helper2);
10504		chr8(machine(), ((offset >> 8) & 0x40) | (offset & 0x3f), CHRROM);
	10532	set_nt_mirroring((offset & 0x2000) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10533	prg16_89ab(map255_helper1 & ~map255_helper2);
	10534	prg16_cdef(map255_helper1 | map255_helper2);
	10535	chr8(((offset >> 8) & 0x40) | (offset & 0x3f), CHRROM);
10505	10536	}
10506	10537
10507	10538	/*************************************************************
r18084	r18085
10619	10650	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
10620	10651	}
10621	10652	else
10622		prg32(machine(), (data & 0x30) >> 4);
	10653	prg32((data & 0x30) >> 4);
10623	10654
10624	10655	m_mmc_chr_base = (data & 0xc0) << 1;
10625	10656	m_mmc_chr_mask = 0x7f;
r18084	r18085
10643	10674	static void bmc_ball11_set_banks( running_machine &machine )
10644	10675	{
10645	10676	nes_state *state = machine.driver_data<nes_state>();
10646		set_nt_mirroring(machine, (state->m_mmc_reg[0] == 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10677	state->set_nt_mirroring((state->m_mmc_reg[0] == 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10647	10678
10648	10679	if (state->m_mmc_reg[0] & 0x01)
10649	10680	{
10650		prg32(machine, state->m_mmc_reg[1]);
	10681	state->prg32(state->m_mmc_reg[1]);
10651	10682	}
10652	10683	else
10653	10684	{
10654		prg16_89ab(machine, (state->m_mmc_reg[1] << 1) | (state->m_mmc_reg[0] >> 1));
10655		prg16_cdef(machine, (state->m_mmc_reg[1] << 1) | 0x07);
	10685	state->prg16_89ab((state->m_mmc_reg[1] << 1) | (state->m_mmc_reg[0] >> 1));
	10686	state->prg16_cdef((state->m_mmc_reg[1] << 1) | 0x07);
10656	10687	}
10657	10688	}
10658	10689
r18084	r18085
10799	10830
10800	10831	chr_base |= ((state->m_mmc_reg[1] & 0x03) << 8);
10801	10832
10802		chr1_x(machine, chr_page ^ 0, chr_base | ((state->m_mmc_vrom_bank[0] & ~0x01) & chr_mask), chr);
10803		chr1_x(machine, chr_page ^ 1, chr_base | ((state->m_mmc_vrom_bank[0] |  0x01) & chr_mask), chr);
10804		chr1_x(machine, chr_page ^ 2, chr_base | ((state->m_mmc_vrom_bank[1] & ~0x01) & chr_mask), chr);
10805		chr1_x(machine, chr_page ^ 3, chr_base | ((state->m_mmc_vrom_bank[1] |  0x01) & chr_mask), chr);
10806		chr1_x(machine, chr_page ^ 4, chr_base | (state->m_mmc_vrom_bank[2] & chr_mask), chr);
10807		chr1_x(machine, chr_page ^ 5, chr_base | (state->m_mmc_vrom_bank[3] & chr_mask), chr);
10808		chr1_x(machine, chr_page ^ 6, chr_base | (state->m_mmc_vrom_bank[4] & chr_mask), chr);
10809		chr1_x(machine, chr_page ^ 7, chr_base | (state->m_mmc_vrom_bank[5] & chr_mask), chr);
	10833	state->chr1_x(chr_page ^ 0, chr_base | ((state->m_mmc_vrom_bank[0] & ~0x01) & chr_mask), chr);
	10834	state->chr1_x(chr_page ^ 1, chr_base | ((state->m_mmc_vrom_bank[0] |  0x01) & chr_mask), chr);
	10835	state->chr1_x(chr_page ^ 2, chr_base | ((state->m_mmc_vrom_bank[1] & ~0x01) & chr_mask), chr);
	10836	state->chr1_x(chr_page ^ 3, chr_base | ((state->m_mmc_vrom_bank[1] |  0x01) & chr_mask), chr);
	10837	state->chr1_x(chr_page ^ 4, chr_base | (state->m_mmc_vrom_bank[2] & chr_mask), chr);
	10838	state->chr1_x(chr_page ^ 5, chr_base | (state->m_mmc_vrom_bank[3] & chr_mask), chr);
	10839	state->chr1_x(chr_page ^ 6, chr_base | (state->m_mmc_vrom_bank[4] & chr_mask), chr);
	10840	state->chr1_x(chr_page ^ 7, chr_base | (state->m_mmc_vrom_bank[5] & chr_mask), chr);
10810	10841	}
10811	10842
10812	10843	WRITE8_MEMBER(nes_carts_state::bmc_gc6in1_l_w)
r18084	r18085
10821	10852	if (data & 0x80)
10822	10853	{
10823	10854	bank = (data & 0x0f) | ((m_mmc_reg[1] & 0x03) << 4);
10824		prg16_89ab(machine(), bank);
10825		prg16_cdef(machine(), bank);
	10855	prg16_89ab(bank);
	10856	prg16_cdef(bank);
10826	10857	}
10827	10858	else
10828	10859	bmc_gc6in1_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
r18084	r18085
10930	10961
10931	10962
10932	10963	case 0x2001:
10933		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	10964	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10934	10965	break;
10935	10966
10936	10967	default:
r18084	r18085
10984	11015
10985	11016	// not sure about this mirroring bit!!
10986	11017	// without it TN 95 in 1 has glitches in Lunar Ball; with it TN 95 in 1 has glitches in Galaxian!
10987		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11018	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
10988	11019	if (BIT(offset, 7))
10989	11020	{
10990		prg16_89ab(machine(), (offset >> 4) & 0x07);
10991		prg16_cdef(machine(), (offset >> 4) & 0x07);
	11021	prg16_89ab((offset >> 4) & 0x07);
	11022	prg16_cdef((offset >> 4) & 0x07);
10992	11023	}
10993	11024	else
10994		prg32(machine(), (offset >> 5) & 0x03);
10995		chr8(machine(), offset, CHRROM);
	11025	prg32((offset >> 5) & 0x03);
	11026	chr8(offset, CHRROM);
10996	11027	}
10997	11028
10998	11029	READ8_MEMBER(nes_carts_state::bmc_vt5201_r)
r18084	r18085
11018	11049	{
11019	11050	nes_state *state = machine.driver_data<nes_state>();
11020	11051
11021		prg8_89(machine, state->m_mmc_prg_bank[0]);
11022		prg8_ab(machine, state->m_mmc_prg_bank[1]);
11023		prg8_cd(machine, state->m_mmc_prg_bank[2]);
11024		prg8_ef(machine, state->m_mmc_prg_bank[3]);
11025		chr2_0(machine, state->m_mmc_vrom_bank[0], CHRROM);
11026		chr2_2(machine, state->m_mmc_vrom_bank[1], CHRROM);
11027		chr2_4(machine, state->m_mmc_vrom_bank[2], CHRROM);
11028		chr2_6(machine, state->m_mmc_vrom_bank[3], CHRROM);
	11052	state->prg8_89(state->m_mmc_prg_bank[0]);
	11053	state->prg8_ab(state->m_mmc_prg_bank[1]);
	11054	state->prg8_cd(state->m_mmc_prg_bank[2]);
	11055	state->prg8_ef(state->m_mmc_prg_bank[3]);
	11056	state->chr2_0(state->m_mmc_vrom_bank[0], CHRROM);
	11057	state->chr2_2(state->m_mmc_vrom_bank[1], CHRROM);
	11058	state->chr2_4(state->m_mmc_vrom_bank[2], CHRROM);
	11059	state->chr2_6(state->m_mmc_vrom_bank[3], CHRROM);
11029	11060	}
11030	11061
11031	11062	WRITE8_MEMBER(nes_carts_state::bmc_bs5_w)
r18084	r18085
11062	11093
11063	11094	if (!BIT(offset, 6))
11064	11095	{
11065		prg16_89ab(machine(), (bank << 1) | BIT(offset, 5));
11066		prg16_cdef(machine(), (bank << 1) | BIT(offset, 5));
	11096	prg16_89ab((bank << 1) | BIT(offset, 5));
	11097	prg16_cdef((bank << 1) | BIT(offset, 5));
11067	11098	}
11068	11099	else
11069		prg32(machine(), bank);
	11100	prg32(bank);
11070	11101
11071		set_nt_mirroring(machine(), BIT(offset, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11102	set_nt_mirroring(BIT(offset, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11072	11103
11073		chr8(machine(), offset & 0x0f, CHRROM);
	11104	chr8(offset & 0x0f, CHRROM);
11074	11105	}
11075	11106
11076	11107	/*************************************************************
r18084	r18085
11089	11120
11090	11121	if (BIT(offset, 7))
11091	11122	{
11092		prg16_89ab(machine(), pbank | BIT(offset, 6));
11093		prg16_cdef(machine(), pbank | BIT(offset, 6));
	11123	prg16_89ab(pbank | BIT(offset, 6));
	11124	prg16_cdef(pbank | BIT(offset, 6));
11094	11125	}
11095	11126	else
11096		prg32(machine(), pbank >> 1);
	11127	prg32(pbank >> 1);
11097	11128
11098		set_nt_mirroring(machine(), BIT(offset, 10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11129	set_nt_mirroring(BIT(offset, 10) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11099	11130
11100		chr8(machine(), cbank, CHRROM);
	11131	chr8(cbank, CHRROM);
11101	11132	}
11102	11133
11103	11134	/*************************************************************
r18084	r18085
11112	11143	{
11113	11144	nes_state *state = machine.driver_data<nes_state>();
11114	11145
11115		set_nt_mirroring(machine, BIT(state->m_mmc_reg[0], 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
	11146	state->set_nt_mirroring(BIT(state->m_mmc_reg[0], 6) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
11116	11147
11117	11148	if (BIT(state->m_mmc_reg[0], 5))
11118	11149	{
11119		prg16_89ab(machine, state->m_mmc_reg[0] & 0x1f);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
11120		prg16_cdef(machine, state->m_mmc_reg[0] & 0x1f);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
	11150	state->prg16_89ab(state->m_mmc_reg[0] & 0x1f);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
	11151	state->prg16_cdef(state->m_mmc_reg[0] & 0x1f);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
11121	11152	}
11122	11153	else
11123		prg32(machine, (state->m_mmc_reg[0] & 0x1f) >> 1);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
	11154	state->prg32((state->m_mmc_reg[0] & 0x1f) >> 1);   // FIXME: here probably we could also have PRGRAM, depending on mmc_latch1!
11124	11155
11125	11156	if (BIT(state->m_mmc_reg[1], 2))
11126		chr8(machine, 0, CHRRAM);
	11157	state->chr8(0, CHRRAM);
11127	11158	//  else
11128		//      chr8(machine, 0, CHRROM);
	11159	//      state->chr8(0, CHRROM);
11129	11160	}
11130	11161
11131	11162	WRITE8_MEMBER(nes_carts_state::bmc_gb63_w)
r18084	r18085
11158	11189	{
11159	11190	LOG_MMC(("edu2k_w, offset: %04x, data: %02x\n", offset, data));
11160	11191
11161		prg32(machine(), data & 0x1f);
11162		wram_bank(machine(), (data & 0xc0) >> 6, NES_WRAM);
	11192	prg32(data & 0x1f);
	11193	wram_bank((data & 0xc0) >> 6, NES_WRAM);
11163	11194	}
11164	11195
11165	11196	/*************************************************************
r18084	r18085
11173	11204	nes_state *state = machine.driver_data<nes_state>();
11174	11205
11175	11206	if (!(state->m_mmc_reg[0] & 0x40))
11176		prg8_x(machine, start, bank);
	11207	state->prg8_x(start, bank);
11177	11208	}
11178	11209
11179	11210	WRITE8_MEMBER(nes_carts_state::h2288_l_w)
r18084	r18085
11188	11219	{
11189	11220	UINT8 helper1 = (m_mmc_reg[0] & 0x05) | ((m_mmc_reg[0] >> 2) & 0x0a);
11190	11221	UINT8 helper2 = BIT(m_mmc_reg[0], 1);
11191		prg16_89ab(machine(), helper1 & ~helper2);
11192		prg16_cdef(machine(), helper1 |  helper2);
	11222	prg16_89ab(helper1 & ~helper2);
	11223	prg16_cdef(helper1 |  helper2);
11193	11224	}
11194	11225	else
11195	11226	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
r18084	r18085
11258	11289	nes_state *state = machine.driver_data<nes_state>();
11259	11290	int i;
11260	11291
11261		prg8_89(machine, state->m_mmc_prg_bank[0]);
11262		prg8_ab(machine, state->m_mmc_prg_bank[1]);
	11292	state->prg8_89(state->m_mmc_prg_bank[0]);
	11293	state->prg8_ab(state->m_mmc_prg_bank[1]);
11263	11294
11264	11295	for (i = 0; i < 8; i++)
11265	11296	{
r18084	r18085
11275	11306	continue;
11276	11307	}
11277	11308	if ((state->m_mmc_vrom_bank[i] == 4 || state->m_mmc_vrom_bank[i] == 5) && !state->m_mmc_latch1)
11278		chr1_x(machine, i, chr_bank & 1, CHRRAM);
	11309	state->chr1_x(i, chr_bank & 1, CHRRAM);
11279	11310	else
11280		chr1_x(machine, i, chr_bank, CHRROM);
	11311	state->chr1_x(i, chr_bank, CHRROM);
11281	11312	}
11282	11313	}
11283	11314
r18084	r18085
11310	11341	case 0x1400:
11311	11342	switch (data & 0x03)
11312	11343	{
11313		case 0: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
11314		case 1: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
11315		case 2: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
11316		case 3: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	11344	case 0: set_nt_mirroring(PPU_MIRROR_VERT); break;
	11345	case 1: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	11346	case 2: set_nt_mirroring(PPU_MIRROR_LOW); break;
	11347	case 3: set_nt_mirroring(PPU_MIRROR_HIGH); break;
11317	11348	}
11318	11349	break;
11319	11350	case 0x7000:
r18084	r18085
11369	11400	UINT8 flip = (state->m_mmc3_latch & 0x40) ? 2 : 0;
11370	11401
11371	11402	if (!(state->m_mmc_reg[3] & 0x03))
11372		prg8_x(machine, start, bank);
	11403	state->prg8_x(start, bank);
11373	11404	else if (start == flip)
11374	11405	{
11375	11406	if ((state->m_mmc_reg[3] & 0x03) == 0x03)
11376		prg32(machine, bank >> 2);
	11407	state->prg32(bank >> 2);
11377	11408	else
11378	11409	{
11379		prg16_89ab(machine, bank >> 1);
11380		prg16_cdef(machine, bank >> 1);
	11410	state->prg16_89ab(bank >> 1);
	11411	state->prg16_cdef(bank >> 1);
11381	11412	}
11382	11413	}
11383	11414	}
r18084	r18085
11387	11418	nes_state *state = machine.driver_data<nes_state>();
11388	11419
11389	11420	if (!(state->m_mmc_reg[3] & 0x10))
11390		chr1_x(machine, start, bank, source);
	11421	state->chr1_x(start, bank, source);
11391	11422	}
11392	11423
11393	11424	INLINE void pjoy84_set_base_mask( running_machine &machine )
r18084	r18085
11421	11452	m_mmc_reg[offset & 0x03] = data;
11422	11453	pjoy84_set_base_mask(machine());
11423	11454	if (m_mmc_reg[3] & 0x10)
11424		chr8(machine(), (m_mmc_chr_base >> 3) | (m_mmc_reg[2] & 0x0f), m_mmc_chr_source);
	11455	chr8((m_mmc_chr_base >> 3) | (m_mmc_reg[2] & 0x0f), m_mmc_chr_source);
11425	11456	else
11426	11457	mmc3_set_chr(machine(), m_mmc_chr_source, m_mmc_chr_base, m_mmc_chr_mask);
11427	11458	mmc3_set_prg(machine(), m_mmc_prg_base, m_mmc_prg_mask);
r18084	r18085
11458	11489	{
11459	11490	case 0x00:
11460	11491	case 0x04:
11461		prg32(machine, (prg_offset + state->m_mmc_reg[3]) >> 1);
	11492	state->prg32((prg_offset + state->m_mmc_reg[3]) >> 1);
11462	11493	break;
11463	11494	case 0x08:
11464		prg16_89ab(machine, prg_offset + 0);
11465		prg16_cdef(machine, prg_offset + state->m_mmc_reg[3]);
	11495	state->prg16_89ab(prg_offset + 0);
	11496	state->prg16_cdef(prg_offset + state->m_mmc_reg[3]);
11466	11497	break;
11467	11498	case 0x0c:
11468		prg16_89ab(machine, prg_offset + state->m_mmc_reg[3]);
11469		prg16_cdef(machine, prg_offset + 0x0f);
	11499	state->prg16_89ab(prg_offset + state->m_mmc_reg[3]);
	11500	state->prg16_cdef(prg_offset + 0x0f);
11470	11501	break;
11471	11502	}
11472	11503	}
r18084	r18085
11478	11509
11479	11510	if (chr_mode)
11480	11511	{
11481		chr4_0(machine, state->m_mmc_reg[1] & 0x1f, state->m_mmc_chr_source);
11482		chr4_4(machine, state->m_mmc_reg[2] & 0x1f, state->m_mmc_chr_source);
	11512	state->chr4_0(state->m_mmc_reg[1] & 0x1f, state->m_mmc_chr_source);
	11513	state->chr4_4(state->m_mmc_reg[2] & 0x1f, state->m_mmc_chr_source);
11483	11514	}
11484	11515	else
11485		chr8(machine, (state->m_mmc_reg[1] & 0x1f) >> 1, state->m_mmc_chr_source);
	11516	state->chr8((state->m_mmc_reg[1] & 0x1f) >> 1, state->m_mmc_chr_source);
11486	11517	}
11487	11518
11488	11519	WRITE8_MEMBER(nes_carts_state::someri_mmc1_w)
r18084	r18085
11516	11547	m_mmc_reg[0] = m_mmc1_latch;
11517	11548	switch (m_mmc_reg[0] & 0x03)
11518	11549	{
11519		case 0: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
11520		case 1: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
11521		case 2: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
11522		case 3: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
	11550	case 0: set_nt_mirroring(PPU_MIRROR_LOW); break;
	11551	case 1: set_nt_mirroring(PPU_MIRROR_HIGH); break;
	11552	case 2: set_nt_mirroring(PPU_MIRROR_VERT); break;
	11553	case 3: set_nt_mirroring(PPU_MIRROR_HORZ); break;
11523	11554	}
11524	11555	someri_mmc1_set_chr(machine());
11525	11556	someri_mmc1_set_prg(machine());
r18084	r18085
11580	11611	break;
11581	11612
11582	11613	case 0x2000:
11583		set_nt_mirroring(machine(), BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	11614	set_nt_mirroring(BIT(data, 0) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
11584	11615	break;
11585	11616	case 0x2001: break;
11586	11617	case 0x4000: m_IRQ_count_latch = data; break;
r18084	r18085
11600	11631	if (offset < 0x1000)
11601	11632	{
11602	11633	m_mmc_prg_bank[4] = data;
11603		prg8_89(machine(), m_mmc_prg_bank[4]);
	11634	prg8_89(m_mmc_prg_bank[4]);
11604	11635	}
11605	11636	else if (offset < 0x2000)
11606	11637	{
11607	11638	switch (data & 0x03)
11608	11639	{
11609		case 0x00: set_nt_mirroring(machine(), PPU_MIRROR_VERT); break;
11610		case 0x01: set_nt_mirroring(machine(), PPU_MIRROR_HORZ); break;
11611		case 0x02: set_nt_mirroring(machine(), PPU_MIRROR_LOW); break;
11612		case 0x03: set_nt_mirroring(machine(), PPU_MIRROR_HIGH); break;
	11640	case 0x00: set_nt_mirroring(PPU_MIRROR_VERT); break;
	11641	case 0x01: set_nt_mirroring(PPU_MIRROR_HORZ); break;
	11642	case 0x02: set_nt_mirroring(PPU_MIRROR_LOW); break;
	11643	case 0x03: set_nt_mirroring(PPU_MIRROR_HIGH); break;
11613	11644	}
11614	11645	}
11615	11646	else if (offset < 0x3000)
11616	11647	{
11617	11648	m_mmc_prg_bank[5] = data;
11618		prg8_ab(machine(), m_mmc_prg_bank[5]);
	11649	prg8_ab(m_mmc_prg_bank[5]);
11619	11650	}
11620	11651	else if (offset < 0x7000)
11621	11652	{
r18084	r18085
11623	11654	shift = BIT(offset, 2) * 4;
11624	11655	data = (data & 0x0f) << shift;
11625	11656	m_mmc_vrom_bank[6 + bank] = data | m_mmc_chr_base;
11626		chr1_x(machine(), bank, m_mmc_vrom_bank[6 + bank], CHRROM);
	11657	chr1_x(bank, m_mmc_vrom_bank[6 + bank], CHRROM);
11627	11658	}
11628	11659	}
11629	11660
r18084	r18085
11647	11678	switch (state->m_mmc_cmd1)
11648	11679	{
11649	11680	case 0x00:
11650		prg8_89(machine, state->m_mmc_prg_bank[4]);
11651		prg8_ab(machine, state->m_mmc_prg_bank[5]);
	11681	state->prg8_89(state->m_mmc_prg_bank[4]);
	11682	state->prg8_ab(state->m_mmc_prg_bank[5]);
11652	11683	for (i = 0; i < 8; i++)
11653		chr1_x(machine, i, state->m_mmc_vrom_bank[6 + i], CHRROM);
	11684	state->chr1_x(i, state->m_mmc_vrom_bank[6 + i], CHRROM);
11654	11685	break;
11655	11686	case 0x01:
11656	11687	mmc3_set_prg(machine, state->m_mmc_prg_base, state->m_mmc_prg_mask);
r18084	r18085
12050	12081	fatalerror("Missing PCB interface\n");
12051	12082
12052	12083	if (intf)
12053		{
	12084	{
12054	12085	m_mmc_write_low = intf->mmc_l.write;
12055	12086	if (!m_mmc_write_low.isnull()) m_mmc_write_low.late_bind(*this);
12056	12087	m_mmc_write_mid = intf->mmc_m.write;
r18084	r18085
12077	12108	m_ppu->set_latch(NULL);
12078	12109	}
12079	12110
12080		m_mmc3_prg_cb = prg8_x;
12081		m_mmc3_chr_cb = chr1_x;
	12111	m_mmc3_prg_cb = mmc3_base_prg_cb;
	12112	m_mmc3_chr_cb = mmc3_base_chr_cb;
12082	12113
12083	12114	switch (m_pcb_id)
12084	12115	{
r18084	r18085
12195	12226	int err = 0, i;
12196	12227
12197	12228	/* basic PRG config */
12198		prg32(machine(), 0);
	12229	prg32(0);
12199	12230
12200	12231	/* some boards will not use this, but directly CHRROM (resp. CHRRAM) if the board only has VROM (resp. VRAM) */
12201	12232	m_mmc_chr_source = m_chr_chunks ? CHRROM : CHRRAM;
12202		chr8(machine(), 0, m_mmc_chr_source);
	12233	chr8(0, m_mmc_chr_source);
12203	12234
12204	12235	/* Here, we init a few helpers: 4 prg banks and 16 chr banks - some mappers use them */
12205	12236	for (i = 0; i < 4; i++)
r18084	r18085
12317	12348	case KAISER_KS7017:
12318	12349	case KAISER_KS7032:
12319	12350	case KAISER_KS202:
12320		prg16_89ab(machine(), 0);
12321		prg16_cdef(machine(), m_prg_chunks - 1);
	12351	prg16_89ab(0);
	12352	prg16_cdef(m_prg_chunks - 1);
12322	12353	break;
12323	12354
12324	12355	case STD_CPROM:   // mapper 13
12325		chr4_0(machine(), 0, CHRRAM);
12326		chr4_4(machine(), 0, CHRRAM);
	12356	chr4_0(0, CHRRAM);
	12357	chr4_4(0, CHRRAM);
12327	12358	break;
12328	12359	case STD_AXROM:   // mapper 7
12329		set_nt_mirroring(machine(), PPU_MIRROR_LOW);
	12360	set_nt_mirroring(PPU_MIRROR_LOW);
12330	12361	break;
12331	12362	case STD_SXROM:   // mapper 1, 155
12332	12363	case STD_SOROM:
r18084	r18085
12337	12368	m_mmc_reg[0] = 0x0f;
12338	12369	m_mmc_reg[1] = m_mmc_reg[2] = m_mmc_reg[3] = 0;
12339	12370	m_mmc1_reg_write_enable = 1;
12340		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	12371	set_nt_mirroring(PPU_MIRROR_HORZ);
12341	12372	mmc1_set_chr(machine());
12342	12373	mmc1_set_prg(machine());
12343	12374	if (m_battery || m_wram)
12344		wram_bank(machine(), 0, (idx == STD_SOROM) ? NES_WRAM : NES_BATTERY);
	12375	wram_bank(0, (idx == STD_SOROM) ? NES_WRAM : NES_BATTERY);
12345	12376	break;
12346	12377	case STD_PXROM:   // mapper 9
12347	12378	m_mmc_reg[0] = m_mmc_reg[2] = 0;
12348	12379	m_mmc_reg[1] = m_mmc_reg[3] = 0;
12349	12380	m_mmc_latch1 = m_mmc_latch2 = 0xfe;
12350		prg8_89(machine(), 0);
12351		prg8_ab(machine(), (m_prg_chunks << 1) - 3);
12352		prg8_cd(machine(), (m_prg_chunks << 1) - 2);
12353		prg8_ef(machine(), (m_prg_chunks << 1) - 1);
	12381	prg8_89(0);
	12382	prg8_ab((m_prg_chunks << 1) - 3);
	12383	prg8_cd((m_prg_chunks << 1) - 2);
	12384	prg8_ef((m_prg_chunks << 1) - 1);
12354	12385	break;
12355	12386	case STD_FXROM: // mapper 10
12356	12387	m_mmc_reg[0] = m_mmc_reg[2] = 0;
12357	12388	m_mmc_reg[1] = m_mmc_reg[3] = 0;
12358	12389	m_mmc_latch1 = m_mmc_latch2 = 0xfe;
12359		prg16_89ab(machine(), 0);
12360		prg16_cdef(machine(), m_prg_chunks - 1);
	12390	prg16_89ab(0);
	12391	prg16_cdef(m_prg_chunks - 1);
12361	12392	break;
12362	12393	case STD_TXROM:   // mapper 4
12363	12394	case STD_TVROM:
r18084	r18085
12381	12412	case NITRA_TDA:   // mapper 250
12382	12413	if (m_four_screen_vram)   // only TXROM and DXROM have 4-screen mirroring
12383	12414	{
12384		set_nt_page(machine(), 0, CART_NTRAM, 0, 1);
12385		set_nt_page(machine(), 1, CART_NTRAM, 1, 1);
12386		set_nt_page(machine(), 2, CART_NTRAM, 2, 1);
12387		set_nt_page(machine(), 3, CART_NTRAM, 3, 1);
	12415	set_nt_page(0, CART_NTRAM, 0, 1);
	12416	set_nt_page(1, CART_NTRAM, 1, 1);
	12417	set_nt_page(2, CART_NTRAM, 2, 1);
	12418	set_nt_page(3, CART_NTRAM, 3, 1);
12388	12419	}
12389	12420	mmc3_common_initialize(machine(), 0xff, 0xff, 0);
12390	12421	break;
r18084	r18085
12415	12446	m_mmc5_prg_regs[3] = 0xff;
12416	12447	memset(m_mmc5_vrom_regA, ~0, ARRAY_LENGTH(m_mmc5_vrom_regA));
12417	12448	memset(m_mmc5_vrom_regB, ~0, ARRAY_LENGTH(m_mmc5_vrom_regB));
12418		prg16_89ab(machine(), m_prg_chunks - 2);
12419		prg16_cdef(machine(), m_prg_chunks - 1);
	12449	prg16_89ab(m_prg_chunks - 2);
	12450	prg16_cdef(m_prg_chunks - 1);
12420	12451	break;
12421	12452	case STD_NXROM:      // mapper 68
12422	12453	case SUNSOFT_DCS:      // mapper 68
12423	12454	m_mmc_reg[0] = 0;
12424		prg16_89ab(machine(), 0);
12425		prg16_cdef(machine(), m_prg_chunks - 1);
	12455	prg16_89ab(0);
	12456	prg16_cdef(m_prg_chunks - 1);
12426	12457	break;
12427	12458	case NAMCOT_34X3:   // mapper 88
12428	12459	case STD_DXROM:   // mapper 206
12429	12460	case STD_DRROM:
12430	12461	if (m_four_screen_vram)   // only TXROM and DXROM have 4-screen mirroring
12431	12462	{
12432		set_nt_page(machine(), 0, CART_NTRAM, 0, 1);
12433		set_nt_page(machine(), 1, CART_NTRAM, 1, 1);
12434		set_nt_page(machine(), 2, CART_NTRAM, 2, 1);
12435		set_nt_page(machine(), 3, CART_NTRAM, 3, 1);
	12463	set_nt_page(0, CART_NTRAM, 0, 1);
	12464	set_nt_page(1, CART_NTRAM, 1, 1);
	12465	set_nt_page(2, CART_NTRAM, 2, 1);
	12466	set_nt_page(3, CART_NTRAM, 3, 1);
12436	12467	}
12437	12468	case NAMCOT_3453:   // mapper 154
12438		prg16_89ab(machine(), m_prg_chunks - 2);
12439		prg16_cdef(machine(), m_prg_chunks - 1);
	12469	prg16_89ab(m_prg_chunks - 2);
	12470	prg16_cdef(m_prg_chunks - 1);
12440	12471	break;
12441	12472	case NAMCOT_3446:   // mapper 76
12442		prg8_89(machine(), 0);
12443		prg8_ab(machine(), 1);
12444		prg16_cdef(machine(), m_prg_chunks - 1);
12445		chr2_0(machine(), 0, CHRROM);
12446		chr2_2(machine(), 1, CHRROM);
12447		chr2_4(machine(), 2, CHRROM);
12448		chr2_6(machine(), 3, CHRROM);
	12473	prg8_89(0);
	12474	prg8_ab(1);
	12475	prg16_cdef(m_prg_chunks - 1);
	12476	chr2_0(0, CHRROM);
	12477	chr2_2(1, CHRROM);
	12478	chr2_4(2, CHRROM);
	12479	chr2_6(3, CHRROM);
12449	12480	break;
12450	12481	case BANDAI_JUMP2:   // mapper 153
12451	12482	for (i = 0; i < 8; i++)
12452	12483	m_mmc_reg[i] = 0;
12453		prg16_89ab(machine(), 0);
12454		prg16_cdef(machine(), m_prg_chunks - 1);
	12484	prg16_89ab(0);
	12485	prg16_cdef(m_prg_chunks - 1);
12455	12486	fjump2_set_prg(machine());
12456	12487	break;
12457	12488	case BANDAI_KARAOKE:   // mapper 188
12458		prg16_89ab(machine(), 0);
12459		prg16_cdef(machine(), (m_prg_chunks - 1) ^ 0x08);
	12489	prg16_89ab(0);
	12490	prg16_cdef((m_prg_chunks - 1) ^ 0x08);
12460	12491	break;
12461	12492	case IREM_LROG017:   // mapper 77
12462		chr2_2(machine(), 0, CHRROM);
12463		chr2_4(machine(), 1, CHRROM);
12464		chr2_6(machine(), 2, CHRROM);
	12493	chr2_2(0, CHRROM);
	12494	chr2_4(1, CHRROM);
	12495	chr2_6(2, CHRROM);
12465	12496	break;
12466	12497	case IREM_TAM_S1:   // mapper 97
12467		prg16_89ab(machine(), m_prg_chunks - 1);
12468		prg16_cdef(machine(), 0);
	12498	prg16_89ab(m_prg_chunks - 1);
	12499	prg16_cdef(0);
12469	12500	break;
12470	12501	case KONAMI_VRC7:   // mapper 85
12471		prg8_89(machine(), 0);
12472		prg8_ab(machine(), 0);
12473		prg8_cd(machine(), 0);
12474		prg8_ef(machine(), 0xff);
	12502	prg8_89(0);
	12503	prg8_ab(0);
	12504	prg8_cd(0);
	12505	prg8_ef(0xff);
12475	12506	break;
12476	12507	case NAMCOT_163:   // mapper 19
12477		prg16_89ab(machine(), 0);
12478		prg16_cdef(machine(), m_prg_chunks - 1);
12479		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12508	prg16_89ab(0);
	12509	prg16_cdef(m_prg_chunks - 1);
	12510	set_nt_mirroring(PPU_MIRROR_VERT);
12480	12511	break;
12481	12512	case SUNSOFT_1:   // mapper 184
12482	12513	case SUNSOFT_2:   // mapper 89 & 93
12483		prg16_89ab(machine(), 0);
12484		prg16_cdef(machine(), m_prg_chunks - 1);
	12514	prg16_89ab(0);
	12515	prg16_cdef(m_prg_chunks - 1);
12485	12516	if (!m_hard_mirroring)
12486		set_nt_mirroring(machine(), PPU_MIRROR_LOW);
	12517	set_nt_mirroring(PPU_MIRROR_LOW);
12487	12518	break;
12488	12519
12489	12520	// mapper 14
r18084	r18085
12497	12528	break;
12498	12529	// mapper 15
12499	12530	case WAIXING_PS2:
12500		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12531	set_nt_mirroring(PPU_MIRROR_VERT);
12501	12532	break;
12502	12533
12503	12534	// mapper 35
r18084	r18085
12505	12536	// mapper 42
12506	12537	case BTL_MARIOBABY:
12507	12538	case BTL_AISENSHINICOL:
12508		prg32(machine(), 0xff);
	12539	prg32(0xff);
12509	12540	break;
12510	12541
12511	12542	// mapper 40
12512	12543	case BTL_SMB2A:
12513		prg8_67(machine(), 0xfe);
12514		prg8_89(machine(), 0xfc);
12515		prg8_ab(machine(), 0xfd);
12516		prg8_cd(machine(), 0xfe);
12517		prg8_ef(machine(), 0xff);
	12544	prg8_67(0xfe);
	12545	prg8_89(0xfc);
	12546	prg8_ab(0xfd);
	12547	prg8_cd(0xfe);
	12548	prg8_ef(0xff);
12518	12549	break;
12519	12550
12520	12551	// mapper 43
r18084	r18085
12538	12569
12539	12570	// mapper 50
12540	12571	case BTL_SMB2B:
12541		prg8_67(machine(), 0x0f);
12542		prg8_89(machine(), 0x08);
12543		prg8_ab(machine(), 0x09);
12544		prg8_cd(machine(), 0);
12545		prg8_ef(machine(), 0x0b);
	12572	prg8_67(0x0f);
	12573	prg8_89(0x08);
	12574	prg8_ab(0x09);
	12575	prg8_cd(0);
	12576	prg8_ef(0x0b);
12546	12577	break;
12547	12578	// mapper 51
12548	12579	case BMC_BALLGAMES_11IN1:
r18084	r18085
12558	12589	break;
12559	12590	// mapper 54
12560	12591	case BMC_NOVELDIAMOND:
12561		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12592	set_nt_mirroring(PPU_MIRROR_VERT);
12562	12593	break;
12563	12594	// mapper 57
12564	12595	case BMC_GKA:
12565		prg16_89ab(machine(), 0);
12566		prg16_cdef(machine(), 0);
	12596	prg16_89ab(0);
	12597	prg16_cdef(0);
12567	12598	break;
12568	12599
12569	12600	// mapper 64
12570	12601	case TENGEN_800032:
12571	12602	// mapper 158
12572	12603	case TENGEN_800037:
12573		prg16_89ab(machine(), m_prg_chunks - 1);
12574		prg16_cdef(machine(), m_prg_chunks - 1);
	12604	prg16_89ab(m_prg_chunks - 1);
	12605	prg16_cdef(m_prg_chunks - 1);
12575	12606	break;
12576	12607	// mapper 71
12577	12608	case CAMERICA_BF9097:
12578		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	12609	set_nt_mirroring(PPU_MIRROR_HORZ);
12579	12610	case CAMERICA_BF9093:
12580		prg32(machine(), 0xff);
	12611	prg32(0xff);
12581	12612	break;
12582	12613
12583	12614	// mapper 79 (& 146)
12584	12615	case AVE_NINA06:
12585		set_nt_mirroring(machine(), PPU_MIRROR_HORZ);
	12616	set_nt_mirroring(PPU_MIRROR_HORZ);
12586	12617	break;
12587	12618
12588	12619	// mapper 83
12589	12620	case CONY_BOARD:
12590	12621	case YOKO_BOARD:
12591	12622	m_mapper83_reg[9] = 0x0f;
12592		prg8_cd(machine(), 0x1e);
12593		prg8_ef(machine(), 0x1f);
	12623	prg8_cd(0x1e);
	12624	prg8_ef(0x1f);
12594	12625	break;
12595	12626
12596	12627	// mapper 91
12597	12628	case UNL_MK2:
12598		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
12599		prg16_89ab(machine(), m_prg_chunks - 1);
12600		prg16_cdef(machine(), m_prg_chunks - 1);
	12629	set_nt_mirroring(PPU_MIRROR_VERT);
	12630	prg16_89ab(m_prg_chunks - 1);
	12631	prg16_cdef(m_prg_chunks - 1);
12601	12632	break;
12602	12633
12603	12634	// mapper 104
12604	12635	case CAMERICA_GOLDENFIVE:
12605		prg16_89ab(machine(), 0x00);
12606		prg16_cdef(machine(), 0x0f);
	12636	prg16_89ab(0x00);
	12637	prg16_cdef(0x0f);
12607	12638	break;
12608	12639	// mapper 106
12609	12640	case BTL_SMB3:
12610		prg8_89(machine(), (m_prg_chunks << 1) - 1);
12611		prg8_ab(machine(), 0);
12612		prg8_cd(machine(), 0);
12613		prg8_ef(machine(), (m_prg_chunks << 1) - 1);
	12641	prg8_89((m_prg_chunks << 1) - 1);
	12642	prg8_ab(0);
	12643	prg8_cd(0);
	12644	prg8_ef((m_prg_chunks << 1) - 1);
12614	12645	break;
12615	12646
12616	12647	// mapper 108
12617	12648	case WHIRLWIND_2706:
12618		prg32(machine(), 0xff);
	12649	prg32(0xff);
12619	12650	break;
12620	12651
12621	12652	// mapper 114
r18084	r18085
12663	12694
12664	12695	// mapper 120
12665	12696	case BTL_TOBIDASE:
12666		prg32(machine(), 2);
	12697	prg32(2);
12667	12698	break;
12668	12699
12669	12700	// mapper 121
r18084	r18085
12697	12728
12698	12729	// mapper 137
12699	12730	case SACHEN_8259D:
12700		chr8(machine(), m_chr_chunks - 1, CHRROM);
12701		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12731	chr8(m_chr_chunks - 1, CHRROM);
	12732	set_nt_mirroring(PPU_MIRROR_VERT);
12702	12733	break;
12703	12734	// mapper 138
12704	12735	case SACHEN_8259B:
r18084	r18085
12708	12739	case SACHEN_8259A:
12709	12740	// mapper 150
12710	12741	case SACHEN_74LS374:
12711		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12742	set_nt_mirroring(PPU_MIRROR_VERT);
12712	12743	break;
12713	12744	// mapper 143
12714	12745	case SACHEN_TCA01:
12715		prg16_89ab(machine(), 0);
12716		prg16_cdef(machine(), 1);
	12746	prg16_89ab(0);
	12747	prg16_cdef(1);
12717	12748	break;
12718	12749
12719	12750	// mapper 156
12720	12751	case OPENCORP_DAOU306:
12721		prg16_89ab(machine(), m_prg_chunks - 2);
12722		prg16_cdef(machine(), m_prg_chunks - 1);
12723		set_nt_mirroring(machine(), PPU_MIRROR_LOW);
	12752	prg16_89ab(m_prg_chunks - 2);
	12753	prg16_cdef(m_prg_chunks - 1);
	12754	set_nt_mirroring(PPU_MIRROR_LOW);
12724	12755	break;
12725	12756	// mapper 163
12726	12757	case NANJING_BOARD:
12727	12758	m_mmc_count = 0xff;
12728	12759	m_mmc_reg[0] = 0xff;
12729	12760	m_mmc_reg[1] = 0;
12730		prg16_89ab(machine(), m_prg_chunks - 2);
12731		prg16_cdef(machine(), m_prg_chunks - 1);
	12761	prg16_89ab(m_prg_chunks - 2);
	12762	prg16_cdef(m_prg_chunks - 1);
12732	12763	break;
12733	12764	// mapper 164
12734	12765	case WAIXING_FFV:
12735		prg16_89ab(machine(), 0);
12736		prg16_cdef(machine(), 0x1f);
	12766	prg16_89ab(0);
	12767	prg16_cdef(0x1f);
12737	12768	break;
12738	12769	// mapper 166
12739	12770	case SUBOR_TYPE1:
12740	12771	m_subor_reg[0] = m_subor_reg[1] = m_subor_reg[2] = m_subor_reg[3] = 0;
12741		prg16_89ab(machine(), 0);
12742		prg16_cdef(machine(), 0x07);
	12772	prg16_89ab(0);
	12773	prg16_cdef(0x07);
12743	12774	break;
12744	12775	// mapper 167
12745	12776	case SUBOR_TYPE0:
12746	12777	m_subor_reg[0] = m_subor_reg[1] = m_subor_reg[2] = m_subor_reg[3] = 0;
12747		prg16_89ab(machine(), 0);
12748		prg16_cdef(machine(), 0x20);
	12778	prg16_89ab(0);
	12779	prg16_cdef(0x20);
12749	12780	break;
12750	12781
12751	12782	// mapper 176
12752	12783	case UNL_XZY:
12753	12784	// mapper 182
12754	12785	case HOSENKAN_BOARD:
12755		prg32(machine(), (m_prg_chunks - 1) >> 1);
	12786	prg32((m_prg_chunks - 1) >> 1);
12756	12787	break;
12757	12788
12758	12789	case FUKUTAKE_BOARD:   // mapper 186
12759		prg16_89ab(machine(), 0);
12760		prg16_cdef(machine(), 0);
	12790	prg16_89ab(0);
	12791	prg16_cdef(0);
12761	12792	break;
12762	12793
12763	12794	// mapper 187
r18084	r18085
12775	12806	break;
12776	12807	// mapper 193
12777	12808	case NTDEC_FIGHTINGHERO:
12778		prg32(machine(), (m_prg_chunks - 1) >> 1);
12779		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12809	prg32((m_prg_chunks - 1) >> 1);
	12810	set_nt_mirroring(PPU_MIRROR_VERT);
12780	12811	break;
12781	12812	// mapper 197
12782	12813	case UNL_SUPERFIGHTER3:
r18084	r18085
12813	12844
12814	12845	// mapper 200
12815	12846	case BMC_36IN1:
12816		prg16_89ab(machine(), m_prg_chunks - 1);
12817		prg16_cdef(machine(), m_prg_chunks - 1);
	12847	prg16_89ab(m_prg_chunks - 1);
	12848	prg16_cdef(m_prg_chunks - 1);
12818	12849	break;
12819	12850
12820	12851	// mapper 202
r18084	r18085
12825	12856	case BMC_64IN1:
12826	12857	// mapper 214
12827	12858	case BMC_SUPERGUN_20IN1:
12828		prg16_89ab(machine(), 0);
12829		prg16_cdef(machine(), 0);
	12859	prg16_89ab(0);
	12860	prg16_cdef(0);
12830	12861	break;
12831	12862	// mapper 205
12832	12863	case BMC_15IN1:
r18084	r18085
12842	12873	break;
12843	12874	// mapper 212
12844	12875	case BMC_SUPERHIK_300IN1:
12845		chr8(machine(), 0xff, CHRROM);
12846		prg32(machine(), 0xff);
	12876	chr8(0xff, CHRROM);
	12877	prg32(0xff);
12847	12878	break;
12848	12879
12849	12880	// mapper 215
r18084	r18085
12869	12900	break;
12870	12901	// mapper 221
12871	12902	case UNL_N625092:
12872		prg16_89ab(machine(), 0);
12873		prg16_cdef(machine(), 0);
	12903	prg16_89ab(0);
	12904	prg16_cdef(0);
12874	12905	break;
12875	12906
12876	12907	// mapper 223?
r18084	r18085
12891	12922
12892	12923	// mapper 227
12893	12924	case BMC_1200IN1:
12894		prg16_89ab(machine(), 0);
12895		prg16_cdef(machine(), 0);
	12925	prg16_89ab(0);
	12926	prg16_cdef(0);
12896	12927	break;
12897	12928
12898	12929	// mapper 229
12899	12930	case BMC_31IN1:
12900		prg16_89ab(machine(), 0);
12901		prg16_cdef(machine(), 1);
12902		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12931	prg16_89ab(0);
	12932	prg16_cdef(1);
	12933	set_nt_mirroring(PPU_MIRROR_VERT);
12903	12934	break;
12904	12935	// mapper 230
12905	12936	case BMC_22GAMES:
12906		prg16_89ab(machine(), 0);
12907		prg16_cdef(machine(), 7);
	12937	prg16_89ab(0);
	12938	prg16_cdef(7);
12908	12939	break;
12909	12940	// mapper 231
12910	12941	case BMC_20IN1:
12911		prg16_89ab(machine(), 0);
12912		prg16_cdef(machine(), m_prg_chunks - 1);
12913		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12942	prg16_89ab(0);
	12943	prg16_cdef(m_prg_chunks - 1);
	12944	set_nt_mirroring(PPU_MIRROR_VERT);
12914	12945	break;
12915	12946	// mapper 232
12916	12947	case CAMERICA_BF9096:
r18084	r18085
12922	12953	// mapper 243
12923	12954	case SACHEN_74LS374_A:
12924	12955	m_mmc_vrom_bank[0] = 3;
12925		chr8(machine(), 3, CHRROM);
12926		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12956	chr8(3, CHRROM);
	12957	set_nt_mirroring(PPU_MIRROR_VERT);
12927	12958	break;
12928	12959
12929	12960	// mapper 246
12930	12961	case CNE_FSB:
12931		prg32(machine(), 0xff);
	12962	prg32(0xff);
12932	12963	break;
12933	12964	// mapper 249
12934	12965	case WAIXING_SECURITY:
r18084	r18085
12944	12975
12945	12976	// mapper 255
12946	12977	case BMC_110IN1:
12947		prg16_89ab(machine(), 0);
12948		prg16_cdef(machine(), 1);
12949		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12978	prg16_89ab(0);
	12979	prg16_cdef(1);
	12980	set_nt_mirroring(PPU_MIRROR_VERT);
12950	12981	break;
12951	12982
12952	12983	// UNIF only
r18084	r18085
12955	12986	m_mmc_reg[1] = 0x43;
12956	12987	m_mmc_reg[2] = m_mmc_reg[3] = 0;
12957	12988	bmc_64in1nr_set_prg(machine());
12958		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12989	set_nt_mirroring(PPU_MIRROR_VERT);
12959	12990	break;
12960	12991	case BMC_190IN1:
12961		prg16_89ab(machine(), 0);
12962		prg16_cdef(machine(), 0);
	12992	prg16_89ab(0);
	12993	prg16_cdef(0);
12963	12994	break;
12964	12995	case BMC_A65AS:
12965		prg16_89ab(machine(), 0);
12966		prg16_cdef(machine(), 7);
12967		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	12996	prg16_89ab(0);
	12997	prg16_cdef(7);
	12998	set_nt_mirroring(PPU_MIRROR_VERT);
12968	12999	break;
12969	13000	case BMC_GS2004:
12970	13001	case BMC_GS2013:
12971		prg32(machine(), 0xff);
	13002	prg32(0xff);
12972	13003	break;
12973	13004	case BMC_S24IN1SC03:
12974	13005	m_mmc_reg[0] = 0x24;
r18084	r18085
12979	13010	case BMC_T262:
12980	13011	m_mmc_latch1 = 0;
12981	13012	m_mmc_latch2 = 0;
12982		prg16_89ab(machine(), 0);
12983		prg16_cdef(machine(), 7);
	13013	prg16_89ab(0);
	13014	prg16_cdef(7);
12984	13015	break;
12985	13016	case DREAMTECH_BOARD:
12986		prg16_89ab(machine(), 0);
12987		prg16_cdef(machine(), 8);
	13017	prg16_89ab(0);
	13018	prg16_cdef(8);
12988	13019	break;
12989	13020	case UNL_8237:
12990	13021	m_mmc_reg[0] = m_mmc_reg[1] = m_mmc_reg[2] = 0;
r18084	r18085
12993	13024	case UNL_AX5705:
12994	13025	m_mmc_prg_bank[0] = 0;
12995	13026	m_mmc_prg_bank[1] = 1;
12996		prg8_89(machine(), m_mmc_prg_bank[0]);
12997		prg8_ab(machine(), m_mmc_prg_bank[1]);
12998		prg8_cd(machine(), 0xfe);
12999		prg8_ef(machine(), 0xff);
	13027	prg8_89(m_mmc_prg_bank[0]);
	13028	prg8_ab(m_mmc_prg_bank[1]);
	13029	prg8_cd(0xfe);
	13030	prg8_ef(0xff);
13000	13031	break;
13001	13032	case UNL_RACERMATE:
13002		chr4_0(machine(), 0, m_mmc_chr_source);
13003		chr4_4(machine(), 0, m_mmc_chr_source);
13004		prg16_89ab(machine(), 0);
13005		prg16_cdef(machine(), m_prg_chunks - 1);
	13033	chr4_0(0, m_mmc_chr_source);
	13034	chr4_4(0, m_mmc_chr_source);
	13035	prg16_89ab(0);
	13036	prg16_cdef(m_prg_chunks - 1);
13006	13037	break;
13007	13038
13008	13039	case BMC_BENSHENG_BS5:
r18084	r18085
13014	13045	break;
13015	13046
13016	13047	case BMC_810544:
13017		prg16_89ab(machine(), 0);
13018		prg16_cdef(machine(), 0);
13019		set_nt_mirroring(machine(), PPU_MIRROR_VERT);
	13048	prg16_89ab(0);
	13049	prg16_cdef(0);
	13050	set_nt_mirroring(PPU_MIRROR_VERT);
13020	13051	break;
13021	13052
13022	13053	case BMC_G63IN1:
r18084	r18085
13043	13074
13044	13075
13045	13076	case FFE_MAPPER6:
13046		prg16_89ab(machine(), 0);
13047		prg16_cdef(machine(), 7);
	13077	prg16_89ab(0);
	13078	prg16_cdef(7);
13048	13079	break;
13049	13080	case FFE_MAPPER8:
13050		prg32(machine(), 0);
	13081	prg32(0);
13051	13082	break;
13052	13083	case FFE_MAPPER17:
13053		prg16_89ab(machine(), 0);
13054		prg16_cdef(machine(), m_prg_chunks - 1);
	13084	prg16_89ab(0);
	13085	prg16_cdef(m_prg_chunks - 1);
13055	13086	break;
13056	13087
13057	13088	case UNSUPPORTED_BOARD:

trunk/src/mess/machine/nes_mmc.c

r18084	r18085
235	235
236	236	*************************************************************/
237	237
238		static void wram_bank( running_machine &machine, int bank, int source )
	238	void nes_carts_state::wram_bank(int bank, int source)
239	239	{
240		nes_state *state = machine.driver_data<nes_state>();
241
242		assert(state->m_battery || state->m_prg_ram);
	240	assert(m_battery || m_prg_ram);
243	241	if (source == NES_BATTERY)
244	242	{
245		bank &= (state->m_battery_size / 0x2000) - 1;
246		state->m_prg_bank[4] = state->m_battery_bank5_start + bank;
	243	bank &= (m_battery_size / 0x2000) - 1;
	244	m_prg_bank[4] = m_battery_bank5_start + bank;
247	245	}
248	246	else
249	247	{
250		bank &= (state->m_wram_size / 0x2000) - 1;
251		state->m_prg_bank[4] = state->m_prgram_bank5_start + bank;
	248	bank &= (m_wram_size / 0x2000) - 1;
	249	m_prg_bank[4] = m_prgram_bank5_start + bank;
252	250	}
253		state->membank("bank5")->set_entry(state->m_prg_bank[4]);
	251	membank("bank5")->set_entry(m_prg_bank[4]);
254	252	}
255	253
256	254	INLINE void prg_bank_refresh( running_machine &machine )
r18084	r18085
264	262
265	263	/* PRG ROM in 8K, 16K or 32K blocks */
266	264
267		static void prg32( running_machine &machine, int bank )
	265	void nes_carts_state::prg32(int bank)
268	266	{
269		nes_state *state = machine.driver_data<nes_state>();
270
271	267	/* if there is only 16k PRG, return */
272		if (!(state->m_prg_chunks >> 1))
	268	if (!(m_prg_chunks >> 1))
273	269	return;
274	270
275	271	/* assumes that bank references a 32k chunk */
276		bank &= ((state->m_prg_chunks >> 1) - 1);
	272	bank &= ((m_prg_chunks >> 1) - 1);
277	273
278		state->m_prg_bank[0] = bank * 4 + 0;
279		state->m_prg_bank[1] = bank * 4 + 1;
280		state->m_prg_bank[2] = bank * 4 + 2;
281		state->m_prg_bank[3] = bank * 4 + 3;
282		prg_bank_refresh(machine);
	274	m_prg_bank[0] = bank * 4 + 0;
	275	m_prg_bank[1] = bank * 4 + 1;
	276	m_prg_bank[2] = bank * 4 + 2;
	277	m_prg_bank[3] = bank * 4 + 3;
	278	prg_bank_refresh(machine());
283	279	}
284	280
285		static void prg16_89ab( running_machine &machine, int bank )
	281	void nes_carts_state::prg16_89ab(int bank)
286	282	{
287		nes_state *state = machine.driver_data<nes_state>();
288
289	283	/* assumes that bank references a 16k chunk */
290		bank &= (state->m_prg_chunks - 1);
	284	bank &= (m_prg_chunks - 1);
291	285
292		state->m_prg_bank[0] = bank * 2 + 0;
293		state->m_prg_bank[1] = bank * 2 + 1;
294		prg_bank_refresh(machine);
	286	m_prg_bank[0] = bank * 2 + 0;
	287	m_prg_bank[1] = bank * 2 + 1;
	288	prg_bank_refresh(machine());
295	289	}
296	290
297		static void prg16_cdef( running_machine &machine, int bank )
	291	void nes_carts_state::prg16_cdef(int bank)
298	292	{
299		nes_state *state = machine.driver_data<nes_state>();
300
301	293	/* assumes that bank references a 16k chunk */
302		bank &= (state->m_prg_chunks - 1);
	294	bank &= (m_prg_chunks - 1);
303	295
304		state->m_prg_bank[2] = bank * 2 + 0;
305		state->m_prg_bank[3] = bank * 2 + 1;
306		prg_bank_refresh(machine);
	296	m_prg_bank[2] = bank * 2 + 0;
	297	m_prg_bank[3] = bank * 2 + 1;
	298	prg_bank_refresh(machine());
307	299	}
308	300
309		static void prg8_89( running_machine &machine, int bank )
	301	void nes_carts_state::prg8_89(int bank)
310	302	{
311		nes_state *state = machine.driver_data<nes_state>();
312
313	303	/* assumes that bank references an 8k chunk */
314		bank &= ((state->m_prg_chunks << 1) - 1);
	304	bank &= ((m_prg_chunks << 1) - 1);
315	305
316		state->m_prg_bank[0] = bank;
317		prg_bank_refresh(machine);
	306	m_prg_bank[0] = bank;
	307	prg_bank_refresh(machine());
318	308	}
319	309
320		static void prg8_ab( running_machine &machine, int bank )
	310	void nes_carts_state::prg8_ab(int bank)
321	311	{
322		nes_state *state = machine.driver_data<nes_state>();
323
324	312	/* assumes that bank references an 8k chunk */
325		bank &= ((state->m_prg_chunks << 1) - 1);
	313	bank &= ((m_prg_chunks << 1) - 1);
326	314
327		state->m_prg_bank[1] = bank;
328		prg_bank_refresh(machine);
	315	m_prg_bank[1] = bank;
	316	prg_bank_refresh(machine());
329	317	}
330	318
331		static void prg8_cd( running_machine &machine, int bank )
	319	void nes_carts_state::prg8_cd(int bank)
332	320	{
333		nes_state *state = machine.driver_data<nes_state>();
334
335	321	/* assumes that bank references an 8k chunk */
336		bank &= ((state->m_prg_chunks << 1) - 1);
	322	bank &= ((m_prg_chunks << 1) - 1);
337	323
338		state->m_prg_bank[2] = bank;
339		prg_bank_refresh(machine);
	324	m_prg_bank[2] = bank;
	325	prg_bank_refresh(machine());
340	326	}
341	327
342		static void prg8_ef( running_machine &machine, int bank )
	328	void nes_carts_state::prg8_ef(int bank)
343	329	{
344		nes_state *state = machine.driver_data<nes_state>();
345
346	330	/* assumes that bank references an 8k chunk */
347		bank &= ((state->m_prg_chunks << 1) - 1);
	331	bank &= ((m_prg_chunks << 1) - 1);
348	332
349		state->m_prg_bank[3] = bank;
350		prg_bank_refresh(machine);
	333	m_prg_bank[3] = bank;
	334	prg_bank_refresh(machine());
351	335	}
352	336
353	337	/* We define an additional helper to map PRG-ROM to 0x6000-0x7000 */
354	338	// TODO: are we implementing this correctly in the mappers which uses it? check!
355	339
356		static void prg8_67( running_machine &machine, int bank )
	340	void nes_carts_state::prg8_67(int bank)
357	341	{
358		nes_state *state = machine.driver_data<nes_state>();
359
360	342	/* assumes that bank references an 8k chunk */
361		bank &= ((state->m_prg_chunks << 1) - 1);
	343	bank &= ((m_prg_chunks << 1) - 1);
362	344
363		state->m_prg_bank[4] = bank;
364		state->membank("bank5")->set_entry(state->m_prg_bank[4]);
	345	m_prg_bank[4] = bank;
	346	membank("bank5")->set_entry(m_prg_bank[4]);
365	347	}
366	348
367	349	/* We also define an additional helper to map 8k PRG-ROM to one of the banks (passed as parameter) */
368		static void prg8_x( running_machine &machine, int start, int bank )
	350	void nes_carts_state::prg8_x(int start, int bank)
369	351	{
370		nes_state *state = machine.driver_data<nes_state>();
371
372	352	assert(start < 4);
373	353
374	354	/* assumes that bank references an 8k chunk */
375		bank &= ((state->m_prg_chunks << 1) - 1);
	355	bank &= ((m_prg_chunks << 1) - 1);
376	356
377		state->m_prg_bank[start] = bank;
378		prg_bank_refresh(machine);
	357	m_prg_bank[start] = bank;
	358	prg_bank_refresh(machine());
379	359	}
380	360
381	361	/* CHR ROM in 1K, 2K, 4K or 8K blocks */
r18084	r18085
392	372	fatalerror("CHRROM bankswitch with no VROM\n");
393	373	}
394	374
395		static void chr8( running_machine &machine, int bank, int source )
	375	void nes_carts_state::chr8(int bank, int source)
396	376	{
397		nes_state *state = machine.driver_data<nes_state>();
398		int i;
	377	chr_sanity_check(machine(), source);
399	378
400		chr_sanity_check(machine, source);
401
402	379	if (source == CHRRAM)
403	380	{
404		bank &= (state->m_vram_chunks - 1);
405		for (i = 0; i < 8; i++)
	381	bank &= (m_vram_chunks - 1);
	382	for (int i = 0; i < 8; i++)
406	383	{
407		state->m_chr_map[i].source = source;
408		state->m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
409		state->m_chr_map[i].access = &state->m_vram[state->m_chr_map[i].origin];
	384	m_chr_map[i].source = source;
	385	m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
	386	m_chr_map[i].access = &m_vram[m_chr_map[i].origin];
410	387	}
411	388	}
412	389	else
413	390	{
414		bank &= (state->m_chr_chunks - 1);
415		for (i = 0; i < 8; i++)
	391	bank &= (m_chr_chunks - 1);
	392	for (int i = 0; i < 8; i++)
416	393	{
417		state->m_chr_map[i].source = source;
418		state->m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
419		state->m_chr_map[i].access = &state->m_vrom[state->m_chr_map[i].origin];
	394	m_chr_map[i].source = source;
	395	m_chr_map[i].origin = (bank * 0x2000) + (i * 0x400); // for save state uses!
	396	m_chr_map[i].access = &m_vrom[m_chr_map[i].origin];
420	397	}
421	398	}
422	399	}
423	400
424		static void chr4_x( running_machine &machine, int start, int bank, int source )
	401	void nes_carts_state::chr4_x(int start, int bank, int source)
425	402	{
426		nes_state *state = machine.driver_data<nes_state>();
427		int i;
	403	chr_sanity_check(machine(), source);
428	404
429		chr_sanity_check(machine, source);
430
431	405	if (source == CHRRAM)
432	406	{
433		bank &= ((state->m_vram_chunks << 1) - 1);
434		for (i = 0; i < 4; i++)
	407	bank &= ((m_vram_chunks << 1) - 1);
	408	for (int i = 0; i < 4; i++)
435	409	{
436		state->m_chr_map[i + start].source = source;
437		state->m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
438		state->m_chr_map[i + start].access = &state->m_vram[state->m_chr_map[i + start].origin];
	410	m_chr_map[i + start].source = source;
	411	m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
	412	m_chr_map[i + start].access = &m_vram[m_chr_map[i + start].origin];
439	413	}
440	414	}
441	415	else
442	416	{
443		bank &= ((state->m_chr_chunks << 1) - 1);
444		for (i = 0; i < 4; i++)
	417	bank &= ((m_chr_chunks << 1) - 1);
	418	for (int i = 0; i < 4; i++)
445	419	{
446		state->m_chr_map[i + start].source = source;
447		state->m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
448		state->m_chr_map[i + start].access = &state->m_vrom[state->m_chr_map[i + start].origin];
	420	m_chr_map[i + start].source = source;
	421	m_chr_map[i + start].origin = (bank * 0x1000) + (i * 0x400); // for save state uses!
	422	m_chr_map[i + start].access = &m_vrom[m_chr_map[i + start].origin];
449	423	}
450	424	}
451	425	}
452	426
453		static void chr4_0( running_machine &machine, int bank, int source )
	427	void nes_carts_state::chr2_x(int start, int bank, int source)
454	428	{
455		chr4_x(machine, 0, bank, source);
456		}
	429	chr_sanity_check(machine(), source);
457	430
458		static void chr4_4( running_machine &machine, int bank, int source )
459		{
460		chr4_x(machine, 4, bank, source);
461		}
462
463		static void chr2_x( running_machine &machine, int start, int bank, int source )
464		{
465		nes_state *state = machine.driver_data<nes_state>();
466		int i;
467
468		chr_sanity_check(machine, source);
469
470	431	if (source == CHRRAM)
471	432	{
472		bank &= ((state->m_vram_chunks << 2) - 1);
473		for (i = 0; i < 2; i++)
	433	bank &= ((m_vram_chunks << 2) - 1);
	434	for (int i = 0; i < 2; i++)
474	435	{
475		state->m_chr_map[i + start].source = source;
476		state->m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
477		state->m_chr_map[i + start].access = &state->m_vram[state->m_chr_map[i + start].origin];
	436	m_chr_map[i + start].source = source;
	437	m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
	438	m_chr_map[i + start].access = &m_vram[m_chr_map[i + start].origin];
478	439	}
479	440	}
480	441	else
481	442	{
482		bank &= ((state->m_chr_chunks << 2) - 1);
483		for (i = 0; i < 2; i++)
	443	bank &= ((m_chr_chunks << 2) - 1);
	444	for (int i = 0; i < 2; i++)
484	445	{
485		state->m_chr_map[i + start].source = source;
486		state->m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
487		state->m_chr_map[i + start].access = &state->m_vrom[state->m_chr_map[i + start].origin];
	446	m_chr_map[i + start].source = source;
	447	m_chr_map[i + start].origin = (bank * 0x800) + (i * 0x400); // for save state uses!
	448	m_chr_map[i + start].access = &m_vrom[m_chr_map[i + start].origin];
488	449	}
489	450	}
490	451	}
491	452
492		static void chr2_0( running_machine &machine, int bank, int source )
	453	void nes_carts_state::chr1_x(int start, int bank, int source)
493	454	{
494		chr2_x(machine, 0, bank, source);
495		}
	455	chr_sanity_check(machine(), source);
496	456
497		static void chr2_2( running_machine &machine, int bank, int source )
498		{
499		chr2_x(machine, 2, bank, source);
500		}
501
502		static void chr2_4( running_machine &machine, int bank, int source )
503		{
504		chr2_x(machine, 4, bank, source);
505		}
506
507		static void chr2_6( running_machine &machine, int bank, int source )
508		{
509		chr2_x(machine, 6, bank, source);
510		}
511
512		static void chr1_x( running_machine &machine, int start, int bank, int source )
513		{
514		nes_state *state = machine.driver_data<nes_state>();
515
516		chr_sanity_check(machine, source);
517
518	457	if (source == CHRRAM)
519	458	{
520		bank &= ((state->m_vram_chunks << 3) - 1);
521		state->m_chr_map[start].source = source;
522		state->m_chr_map[start].origin = (bank * 0x400); // for save state uses!
523		state->m_chr_map[start].access = &state->m_vram[state->m_chr_map[start].origin];
	459	bank &= ((m_vram_chunks << 3) - 1);
	460	m_chr_map[start].source = source;
	461	m_chr_map[start].origin = (bank * 0x400); // for save state uses!
	462	m_chr_map[start].access = &m_vram[m_chr_map[start].origin];
524	463	}
525	464	else
526	465	{
527		bank &= ((state->m_chr_chunks << 3) - 1);
528		state->m_chr_map[start].source = source;
529		state->m_chr_map[start].origin = (bank * 0x400); // for save state uses!
530		state->m_chr_map[start].access = &state->m_vrom[state->m_chr_map[start].origin];
	466	bank &= ((m_chr_chunks << 3) - 1);
	467	m_chr_map[start].source = source;
	468	m_chr_map[start].origin = (bank * 0x400); // for save state uses!
	469	m_chr_map[start].access = &m_vrom[m_chr_map[start].origin];
531	470	}
532	471	}
533	472
534		static void chr1_0 (running_machine &machine, int bank, int source)
535		{
536		chr1_x(machine, 0, bank, source);
537		}
538	473
539		static void chr1_1( running_machine &machine, int bank, int source )
540		{
541		chr1_x(machine, 1, bank, source);
542		}
543
544		static void chr1_2( running_machine &machine, int bank, int source )
545		{
546		chr1_x(machine, 2, bank, source);
547		}
548
549		static void chr1_3( running_machine &machine, int bank, int source )
550		{
551		chr1_x(machine, 3, bank, source);
552		}
553
554		static void chr1_4( running_machine &machine, int bank, int source )
555		{
556		chr1_x(machine, 4, bank, source);
557		}
558
559		static void chr1_5( running_machine &machine, int bank, int source )
560		{
561		chr1_x(machine, 5, bank, source);
562		}
563
564		static void chr1_6( running_machine &machine, int bank, int source )
565		{
566		chr1_x(machine, 6, bank, source);
567		}
568
569		static void chr1_7( running_machine &machine, int bank, int source )
570		{
571		chr1_x(machine, 7, bank, source);
572		}
573
574
575	474	/* NameTable paging and mirroring */
576	475
577		static void set_nt_page( running_machine &machine, int page, int source, int bank, int writable )
	476	void nes_carts_state::set_nt_page(int page, int source, int bank, int writable)
578	477	{
579		nes_state *state = machine.driver_data<nes_state>();
580	478	UINT8* base_ptr;
581	479
582	480	switch (source)
583	481	{
584	482	case CART_NTRAM:
585		base_ptr = state->m_extended_ntram;
	483	base_ptr = m_extended_ntram;
586	484	break;
587	485	case MMC5FILL:
588	486	base_ptr = NULL;
589	487	break;
590	488	case ROM:
591		base_ptr = state->m_vrom;
	489	base_ptr = m_vrom;
592	490	break;
593	491	case EXRAM:
594		base_ptr = state->m_mapper_ram;
	492	base_ptr = m_mapper_ram;
595	493	break;
596	494	case CIRAM:
597	495	default:
598		base_ptr = state->m_ciram;
	496	base_ptr = m_ciram;
599	497	break;
600	498	}
601	499
602	500	page &= 3; /* mask down to the 4 logical pages */
603		state->m_nt_page[page].source = source;
	501	m_nt_page[page].source = source;
604	502
605	503	if (base_ptr != NULL)
606	504	{
607		state->m_nt_page[page].origin = bank * 0x400;
608		state->m_nt_page[page].access = base_ptr + state->m_nt_page[page].origin;
	505	m_nt_page[page].origin = bank * 0x400;
	506	m_nt_page[page].access = base_ptr + m_nt_page[page].origin;
609	507	}
610	508
611		state->m_nt_page[page].writable = writable;
	509	m_nt_page[page].writable = writable;
612	510	}
613	511
614		void set_nt_mirroring( running_machine &machine, int mirroring )
	512	void nes_carts_state::set_nt_mirroring(int mirroring)
615	513	{
616	514	/* setup our videomem handlers based on mirroring */
617	515	switch (mirroring)
618	516	{
619	517	case PPU_MIRROR_VERT:
620		set_nt_page(machine, 0, CIRAM, 0, 1);
621		set_nt_page(machine, 1, CIRAM, 1, 1);
622		set_nt_page(machine, 2, CIRAM, 0, 1);
623		set_nt_page(machine, 3, CIRAM, 1, 1);
	518	set_nt_page(0, CIRAM, 0, 1);
	519	set_nt_page(1, CIRAM, 1, 1);
	520	set_nt_page(2, CIRAM, 0, 1);
	521	set_nt_page(3, CIRAM, 1, 1);
624	522	break;
625	523
626	524	case PPU_MIRROR_HORZ:
627		set_nt_page(machine, 0, CIRAM, 0, 1);
628		set_nt_page(machine, 1, CIRAM, 0, 1);
629		set_nt_page(machine, 2, CIRAM, 1, 1);
630		set_nt_page(machine, 3, CIRAM, 1, 1);
	525	set_nt_page(0, CIRAM, 0, 1);
	526	set_nt_page(1, CIRAM, 0, 1);
	527	set_nt_page(2, CIRAM, 1, 1);
	528	set_nt_page(3, CIRAM, 1, 1);
631	529	break;
632	530
633	531	case PPU_MIRROR_HIGH:
634		set_nt_page(machine, 0, CIRAM, 1, 1);
635		set_nt_page(machine, 1, CIRAM, 1, 1);
636		set_nt_page(machine, 2, CIRAM, 1, 1);
637		set_nt_page(machine, 3, CIRAM, 1, 1);
	532	set_nt_page(0, CIRAM, 1, 1);
	533	set_nt_page(1, CIRAM, 1, 1);
	534	set_nt_page(2, CIRAM, 1, 1);
	535	set_nt_page(3, CIRAM, 1, 1);
638	536	break;
639	537
640	538	case PPU_MIRROR_LOW:
641		set_nt_page(machine, 0, CIRAM, 0, 1);
642		set_nt_page(machine, 1, CIRAM, 0, 1);
643		set_nt_page(machine, 2, CIRAM, 0, 1);
644		set_nt_page(machine, 3, CIRAM, 0, 1);
	539	set_nt_page(0, CIRAM, 0, 1);
	540	set_nt_page(1, CIRAM, 0, 1);
	541	set_nt_page(2, CIRAM, 0, 1);
	542	set_nt_page(3, CIRAM, 0, 1);
645	543	break;
646	544
647	545	case PPU_MIRROR_NONE:
r18084	r18085
653	551
654	552	logerror("Mapper set 4-screen mirroring without supplying external nametable memory!\n");
655	553
656		set_nt_page(machine, 0, CIRAM, 0, 1);
657		set_nt_page(machine, 1, CIRAM, 0, 1);
658		set_nt_page(machine, 2, CIRAM, 1, 1);
659		set_nt_page(machine, 3, CIRAM, 1, 1);
	554	set_nt_page(0, CIRAM, 0, 1);
	555	set_nt_page(1, CIRAM, 0, 1);
	556	set_nt_page(2, CIRAM, 1, 1);
	557	set_nt_page(3, CIRAM, 1, 1);
660	558	break;
661	559	}
662	560	}

trunk/src/mess/machine/nes.c

r18084	r18085
140	140	}
141	141
142	142	if (m_four_screen_vram)
143		set_nt_mirroring(machine(), PPU_MIRROR_4SCREEN);
	143	set_nt_mirroring(PPU_MIRROR_4SCREEN);
144	144	else
145	145	{
146	146	switch (m_hard_mirroring)
r18084	r18085
149	149	case PPU_MIRROR_VERT:
150	150	case PPU_MIRROR_HIGH:
151	151	case PPU_MIRROR_LOW:
152		set_nt_mirroring(machine(), m_hard_mirroring);
	152	set_nt_mirroring(m_hard_mirroring);
153	153	break;
154	154	default:
155		set_nt_mirroring(machine(), PPU_MIRROR_NONE);
	155	set_nt_mirroring(PPU_MIRROR_NONE);
156	156	break;
157	157	}
158	158	}
r18084	r18085
1633	1633	m_fds_head_position = 0;
1634	1634
1635	1635	m_fds_read_mode = BIT(data, 2);
1636		set_nt_mirroring(machine(), BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
	1636	set_nt_mirroring(BIT(data, 3) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
1637	1637
1638	1638	if ((!(data & 0x40)) && (m_fds_write_reg & 0x40))
1639	1639	m_fds_head_position -= 2; // ???

trunk/src/mess/includes/nes.h

r18084	r18085
67	67	void init_nes_core();
68	68	void pcb_handlers_setup();
69	69	int pcb_initialize(int idx);
70
	70
71	71	DECLARE_WRITE8_MEMBER(nes_chr_w);
72	72	DECLARE_READ8_MEMBER(nes_chr_r);
73	73	DECLARE_WRITE8_MEMBER(nes_nt_w);
r18084	r18085
82	82	read8_delegate    m_mmc_read_low;
83	83	read8_delegate    m_mmc_read_mid;
84	84	read8_delegate    m_mmc_read;
85
	85
86	86	/* devices */
87		//   cpu_device        *m_maincpu;
88		//   ppu2c0x_device    *m_ppu;
89		//   device_t          *m_sound;
	87	//  cpu_device        *m_maincpu;
	88	//  ppu2c0x_device    *m_ppu;
	89	//  device_t          *m_sound;
90	90	device_t          *m_cart;
91		//   emu_timer         *m_irq_timer;
92
93		/* misc region to be allocated at init */
94		// variables which don't change at run-time
95		UINT8      *m_rom;
96		UINT8      *m_prg;
97		UINT8      *m_vrom;
98		UINT8      *m_vram;
99		UINT8      *m_ciram; //PPU nametable RAM - external to PPU!
100
	91	//  emu_timer         *m_irq_timer;
	92
101	93	/***** FDS-floppy related *****/
102	94
103	95	int     m_disk_expansion;

trunk/src/mess/includes/nes_mmc.h

r18084	r18085
152	152	public:
153	153	nes_carts_state(const machine_config &mconfig, device_type type, const char *tag)
154	154	: driver_device(mconfig, type, tag) { }
155
	155
156	156	int           m_prg_bank[5];
157	157	chr_bank      m_chr_map[8];  //quick banking structure, because some of this changes multiple times per scanline!
158	158	name_table    m_nt_page[4];  //quick banking structure for a maximum of 4K of RAM/ROM/ExRAM
159
	159
160	160	nes_prg_callback    m_mmc3_prg_cb;   // these are used to simplify a lot emulation of some MMC3 pirate clones
161	161	nes_chr_callback    m_mmc3_chr_cb;
162
	162
	163	// mapper variables (to be sorted out at some point, to split more complex mappers as separate devices)
163	164	int m_chr_open_bus;
164	165	int m_prgram_bank5_start, m_battery_bank5_start, m_empty_bank5_start;
165
	166
166	167	UINT8 m_ce_mask, m_ce_state;
167	168	UINT8 m_vrc_ls_prg_a, m_vrc_ls_prg_b, m_vrc_ls_chr;
168
	169
169	170	int m_MMC5_floodtile;
170	171	int m_MMC5_floodattr;
171	172	int m_mmc5_vram_control;
172	173	UINT8 m_mmc5_high_chr;
173	174	UINT8 m_mmc5_split_scr;
174	175	UINT8 *m_extended_ntram;
175
	176
176	177	UINT8 m_mmc5_last_chr_a;
177	178	UINT16 m_mmc5_vrom_regA[8];
178	179	UINT16 m_mmc5_vrom_regB[4];
r18084	r18085
184	185	UINT8 m_mmc5_split_ctrl;
185	186	UINT8 m_mmc5_split_yst;
186	187	UINT8 m_mmc5_split_bank;
187
	188
188	189	/***** Mapper-related variables *****/
189
	190
190	191	// common ones
191	192	int        m_IRQ_enable, m_IRQ_enable_latch;
192	193	UINT16     m_IRQ_count, m_IRQ_count_latch;
r18084	r18085
196	197	UINT8      m_IRQ_mode;
197	198	UINT8      m_IRQ_clear;
198	199	int        m_mult1, m_mult2;
199
	200
200	201	UINT8 m_mmc_chr_source;         // This is set at init to CHRROM or CHRRAM. a few mappers can swap between
201	202	// the two (this is done in the specific handlers).
202
	203
203	204	UINT8 m_mmc_cmd1, m_mmc_cmd2;      // These represent registers where the mapper writes important values
204	205	UINT8 m_mmc_count;            // This is used as counter in mappers like 1 and 45
205
	206
206	207	int m_mmc_prg_base, m_mmc_prg_mask;   // MMC3 based multigame carts select a block of banks by using these (and then act like normal MMC3),
207	208	int m_mmc_chr_base, m_mmc_chr_mask;   // while MMC3 and clones (mapper 118 & 119) simply set them as 0 and 0xff resp.
208
	209
209	210	UINT8 m_mmc_prg_bank[6];            // Many mappers writes only some bits of the selected bank (for both PRG and CHR),
210	211	UINT8 m_mmc_vrom_bank[16];         // hence these are handy to latch bank values.
211
	212
212	213	UINT16 m_MMC5_vrom_bank[12];         // MMC5 has 10bit wide VROM regs!
213	214	UINT8 m_mmc_extra_bank[16];         // some MMC3 clone have 2 series of PRG/CHR banks...
214	215	// we collect them all here: first 4 elements PRG banks, then 6/8 CHR banks
215
	216
216	217	UINT8 m_mmc_latch1, m_mmc_latch2;
217	218	UINT8 m_mmc_reg[16];
218
	219
219	220	UINT8 m_mmc_dipsetting;
220
	221
221	222	// misc mapper related variables which should be merged with the above one, where possible
222	223	int m_mmc1_reg_write_enable;
223	224	int m_mmc1_latch;
224	225	int m_mmc1_count;
225
	226
226	227	int m_mmc3_latch;
227	228	int m_mmc3_wram_protect;
228	229	int m_mmc3_alt_irq;
229
	230
230	231	int m_MMC5_rom_bank_mode;
231	232	int m_MMC5_vrom_bank_mode;
232	233	int m_MMC5_vram_protect;
r18084	r18085
234	235	int m_vrom_page_a;
235	236	int m_vrom_page_b;
236	237	// int vrom_next[4];
237
	238
238	239	UINT8 m_mmc6_reg;
239
	240
240	241	// these might be unified in single mmc_reg[] array, together with state->m_mmc_cmd1 & state->m_mmc_cmd2
241	242	// but be careful that MMC3 clones often use state->m_mmc_cmd1/state->m_mmc_cmd2 (from base MMC3) AND additional regs below!
242	243	UINT8 m_mapper83_reg[10];
r18084	r18085
246	247	UINT8 m_sachen_reg[8];   // used by mappers 137, 138, 139 & 141
247	248	UINT8 m_map52_reg_written;
248	249	UINT8 m_map114_reg, m_map114_reg_enabled;
249
	250
250	251	// i/o handlers
251	252	DECLARE_WRITE8_MEMBER(mapper6_l_w);
252	253	DECLARE_WRITE8_MEMBER(mapper6_w);
r18084	r18085
522	523	DECLARE_WRITE8_MEMBER(dummy_w);
523	524	DECLARE_READ8_MEMBER(dummy_l_r);
524	525	DECLARE_READ8_MEMBER(dummy_m_r);
525		DECLARE_READ8_MEMBER(dummy_r);
526
	526	DECLARE_READ8_MEMBER(dummy_r);
	527
	528	/* misc region to be allocated at init */
	529	// variables which don't change at run-time
	530	UINT8      *m_rom;
	531	UINT8      *m_prg;
	532	UINT8      *m_vrom;
	533	UINT8      *m_vram;
	534	UINT8      *m_ciram; //PPU nametable RAM - external to PPU!
	535
527	536	UINT8      *m_wram;
528	537	UINT8      *m_battery_ram;
529	538	UINT8      *m_mapper_ram;
530	539	UINT8      *m_mapper_bram;
531	540	UINT32      m_mapper_ram_size;
532	541	UINT32      m_mapper_bram_size;
533
	542
534	543	/* load-time cart variables which remain constant */
535	544	UINT16 m_prg_chunks;      // iNES 2.0 allows for more chunks (a recently dumped multigame cart has 256 chunks of both PRG & CHR!)
536	545	UINT16 m_chr_chunks;
r18084	r18085
540	549	UINT32 m_battery_size;
541	550	UINT8 m_prg_ram;         // if there is PRG RAM with no backup
542	551	UINT32 m_wram_size;
543
	552
544	553	/* system variables which don't change at run-time */
545	554	UINT16 m_mapper;      // for iNES
546	555	UINT16 m_pcb_id;      // for UNIF & xml
r18084	r18085
556	565	cpu_device        *m_maincpu;
557	566	ppu2c0x_device    *m_ppu;
558	567	device_t          *m_sound;
559		emu_timer         *m_irq_timer;
	568	emu_timer         *m_irq_timer;
	569
	570	//private:
	571
	572	// banking helpers
	573	// WRAM bankswitch
	574	void wram_bank(int bank, int source);
	575	// PRG bankswitch
	576	void prg32(int bank);
	577	void prg16_89ab(int bank);
	578	void prg16_cdef(int bank);
	579	void prg8_89(int bank);
	580	void prg8_ab(int bank);
	581	void prg8_cd(int bank);
	582	void prg8_ef(int bank);
	583	void prg8_67(int bank);   // a bunch of pcbs can bank ROM in WRAM area!
	584	void prg8_x(int start, int bank);
	585	// CHR 8k bankswitch
	586	void chr8(int bank, int source);
	587	// CHR 4k bankswitch
	588	void chr4_x(int start, int bank, int source);
	589	void chr4_0(int bank, int source){ chr4_x(0, bank, source); };
	590	void chr4_4(int bank, int source){ chr4_x(4, bank, source); };
	591	// CHR 2k bankswitch
	592	void chr2_x(int start, int bank, int source);
	593	void chr2_0(int bank, int source) { chr2_x(0, bank, source); };
	594	void chr2_2(int bank, int source) { chr2_x(2, bank, source); };
	595	void chr2_4(int bank, int source) { chr2_x(4, bank, source); };
	596	void chr2_6(int bank, int source) { chr2_x(6, bank, source); };
	597	// CHR 1k bankswitch
	598	void chr1_x(int start, int bank, int source);
	599	void chr1_0(int bank, int source) { chr1_x(0, bank, source); };
	600	void chr1_1(int bank, int source) { chr1_x(1, bank, source); };
	601	void chr1_2(int bank, int source) { chr1_x(2, bank, source); };
	602	void chr1_3(int bank, int source) { chr1_x(3, bank, source); };
	603	void chr1_4(int bank, int source) { chr1_x(4, bank, source); };
	604	void chr1_5(int bank, int source) { chr1_x(5, bank, source); };
	605	void chr1_6(int bank, int source) { chr1_x(6, bank, source); };
	606	void chr1_7(int bank, int source) { chr1_x(7, bank, source); };
	607	// NT bankswitch
	608	void set_nt_page(int page, int source, int bank, int writable);
	609	void set_nt_mirroring(int mirroring);
	610
560	611	};
561	612
562	613

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