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r18046 Thursday 20th September, 2012 at 13:59:11 UTC by Miodrag Milanović
some hp48 cleanup (nw)

[src/mess/includes]	hp48.h
[src/mess/machine]	hp48.c

trunk/src/mess/machine/hp48.c

r18045	r18046
366	366	- perform some action on read / write
367	367	*/
368	368
369		static WRITE8_HANDLER ( hp48_io_w )
	369	WRITE8_MEMBER(hp48_state::hp48_io_w)
370	370	{
371		hp48_state *state = space.machine().driver_data<hp48_state>();
372	371	LOG(( "%05x %f hp48_io_w: off=%02x data=%x\n",
373	372	space.device().safe_pcbase(), space.machine().time().as_double(), offset, data ));
374	373
r18045	r18046
376	375	{
377	376
378	377	/* CRC register */
379		case 0x04: state->m_crc = (state->m_crc & 0xfff0) | data; break;
380		case 0x05: state->m_crc = (state->m_crc & 0xff0f) | (data << 4); break;
381		case 0x06: state->m_crc = (state->m_crc & 0xf0ff) | (data << 8); break;
382		case 0x07: state->m_crc = (state->m_crc & 0x0fff) | (data << 12); break;
	378	case 0x04: m_crc = (m_crc & 0xfff0) | data; break;
	379	case 0x05: m_crc = (m_crc & 0xff0f) | (data << 4); break;
	380	case 0x06: m_crc = (m_crc & 0xf0ff) | (data << 8); break;
	381	case 0x07: m_crc = (m_crc & 0x0fff) | (data << 12); break;
383	382
384	383	/* annunciators */
385	384	case 0x0b:
386	385	case 0x0c:
387		state->m_io[offset] = data;
388		hp48_update_annunciators(state);
	386	m_io[offset] = data;
	387	hp48_update_annunciators(this);
389	388	break;
390	389
391	390	/* cntrl ROM */
392	391	case 0x29:
393	392	{
394		int old_cntrl = state->m_io[offset] & 8;
395		state->m_io[offset] = data;
	393	int old_cntrl = m_io[offset] & 8;
	394	m_io[offset] = data;
396	395	if ( old_cntrl != (data & 8) )
397	396	{
398		hp48_apply_modules(state);
	397	hp48_apply_modules(this);
399	398	}
400	399	break;
401	400	}
402	401
403	402	/* timers */
404		case 0x37: state->m_timer1 = data; break;
405		case 0x38: state->m_timer2 = (state->m_timer2 & 0xfffffff0) | data; break;
406		case 0x39: state->m_timer2 = (state->m_timer2 & 0xffffff0f) | (data << 4); break;
407		case 0x3a: state->m_timer2 = (state->m_timer2 & 0xfffff0ff) | (data << 8); break;
408		case 0x3b: state->m_timer2 = (state->m_timer2 & 0xffff0fff) | (data << 12); break;
409		case 0x3c: state->m_timer2 = (state->m_timer2 & 0xfff0ffff) | (data << 16); break;
410		case 0x3d: state->m_timer2 = (state->m_timer2 & 0xff0fffff) | (data << 20); break;
411		case 0x3e: state->m_timer2 = (state->m_timer2 & 0xf0ffffff) | (data << 24); break;
412		case 0x3f: state->m_timer2 = (state->m_timer2 & 0x0fffffff) | (data << 28); break;
	403	case 0x37: m_timer1 = data; break;
	404	case 0x38: m_timer2 = (m_timer2 & 0xfffffff0) | data; break;
	405	case 0x39: m_timer2 = (m_timer2 & 0xffffff0f) | (data << 4); break;
	406	case 0x3a: m_timer2 = (m_timer2 & 0xfffff0ff) | (data << 8); break;
	407	case 0x3b: m_timer2 = (m_timer2 & 0xffff0fff) | (data << 12); break;
	408	case 0x3c: m_timer2 = (m_timer2 & 0xfff0ffff) | (data << 16); break;
	409	case 0x3d: m_timer2 = (m_timer2 & 0xff0fffff) | (data << 20); break;
	410	case 0x3e: m_timer2 = (m_timer2 & 0xf0ffffff) | (data << 24); break;
	411	case 0x3f: m_timer2 = (m_timer2 & 0x0fffffff) | (data << 28); break;
413	412
414	413	/* cards */
415	414	case 0x0e:
r18045	r18046
428	427	bit 1: card test?
429	428	*/
430	429
431		state->m_io[0x0e] = data;
	430	m_io[0x0e] = data;
432	431	break;
433	432
434	433	case 0x0f:
435	434	LOG(( "%05x: card info write %02x\n", space.device().safe_pcbase(), data ));
436		state->m_io[0x0f] = data;
	435	m_io[0x0f] = data;
437	436	break;
438	437
439	438	/* serial */
440	439	case 0x13:
441		state->m_io[0x11] &= ~4; /* clear error status */
	440	m_io[0x11] &= ~4; /* clear error status */
442	441	break;
443	442	case 0x16:
444	443	/* first nibble of sent data */
445		state->m_io[offset] = data;
	444	m_io[offset] = data;
446	445	break;
447	446	case 0x17:
448	447	/* second nibble of sent data */
449		state->m_io[offset] = data;
	448	m_io[offset] = data;
450	449	hp48_rs232_send_byte(space.machine());
451	450	break;
452	451
r18045	r18046
475	474	- 0x1d: I/R output buffer
476	475	*/
477	476
478		default: state->m_io[offset] = data;
	477	default: m_io[offset] = data;
479	478	}
480	479
481	480	}
482	481
483	482
484		static READ8_HANDLER ( hp48_io_r )
	483	READ8_MEMBER(hp48_state::hp48_io_r)
485	484	{
486		hp48_state *state = space.machine().driver_data<hp48_state>();
	485	hp48_state *state = machine().driver_data<hp48_state>();
487	486	UINT8 data = 0;
488	487
489	488	switch( offset )
490	489	{
491	490
492	491	/* CRC register */
493		case 0x04: data = state->m_crc & 0xf; break;
494		case 0x05: data = (state->m_crc >> 4) & 0xf; break;
495		case 0x06: data = (state->m_crc >> 8) & 0xf; break;
496		case 0x07: data = (state->m_crc >> 12) & 0xf; break;
	492	case 0x04: data = m_crc & 0xf; break;
	493	case 0x05: data = (m_crc >> 4) & 0xf; break;
	494	case 0x06: data = (m_crc >> 8) & 0xf; break;
	495	case 0x07: data = (m_crc >> 12) & 0xf; break;
497	496
498	497	/* battery test */
499	498	case 0x08:
500	499	data = 0;
501		if ( state->m_io[0x9] & 8 ) /* test enable */
	500	if ( m_io[0x9] & 8 ) /* test enable */
502	501	{
503	502	/* XXX not implemented:
504	503	bit 3: battery in port 2
505	504	bit 2: battery in port 1
506	505	*/
507		switch ( state->ioport( "BATTERY" )->read() )
	506	switch ( ioport( "BATTERY" )->read() )
508	507	{
509	508	case 1: data = 2; break; /* low */
510	509	case 2: data = 3; break; /* low | critical */
r18045	r18046
533	532	}
534	533
535	534	/* timers */
536		case 0x37: data = state->m_timer1; break;
537		case 0x38: data = state->m_timer2 & 0xf; break;
538		case 0x39: data = (state->m_timer2 >> 4) & 0xf; break;
539		case 0x3a: data = (state->m_timer2 >> 8) & 0xf; break;
540		case 0x3b: data = (state->m_timer2 >> 12) & 0xf; break;
541		case 0x3c: data = (state->m_timer2 >> 16) & 0xf; break;
542		case 0x3d: data = (state->m_timer2 >> 20) & 0xf; break;
543		case 0x3e: data = (state->m_timer2 >> 24) & 0xf; break;
544		case 0x3f: data = (state->m_timer2 >> 28) & 0xf; break;
	535	case 0x37: data = m_timer1; break;
	536	case 0x38: data = m_timer2 & 0xf; break;
	537	case 0x39: data = (m_timer2 >> 4) & 0xf; break;
	538	case 0x3a: data = (m_timer2 >> 8) & 0xf; break;
	539	case 0x3b: data = (m_timer2 >> 12) & 0xf; break;
	540	case 0x3c: data = (m_timer2 >> 16) & 0xf; break;
	541	case 0x3d: data = (m_timer2 >> 20) & 0xf; break;
	542	case 0x3e: data = (m_timer2 >> 24) & 0xf; break;
	543	case 0x3f: data = (m_timer2 >> 28) & 0xf; break;
545	544
546	545	/* serial */
547	546	case 0x15:
r18045	r18046
551	550	//device_image_interface *xmodem = dynamic_cast<device_image_interface *>(space.machine().device("rs232_x"));
552	551	//device_image_interface *kermit = dynamic_cast<device_image_interface *>(space.machine().device("rs232_k"));
553	552
554		state->m_io[0x11] &= ~1;  /* clear byte received */
555		data = state->m_io[offset];
	553	m_io[0x11] &= ~1;  /* clear byte received */
	554	data = m_io[offset];
556	555
557	556	/* protocol action */
558	557	//if ( xmodem && xmodem->exists() ) xmodem_byte_transmitted( &xmodem->device() );
r18045	r18046
562	561
563	562	/* cards */
564	563	case 0x0e: /* detection */
565		data = state->m_io[0x0e];
	564	data = m_io[0x0e];
566	565	LOG(( "%05x: card control read %02x\n", space.device().safe_pcbase(), data ));
567	566	break;
568	567	case 0x0f: /* card info */
569	568	data = 0;
570	569	if ( HP48_G_SERIES )
571	570	{
572		if ( state->m_port_size[1] ) data |= 1;
573		if ( state->m_port_size[0] ) data |= 2;
574		if ( state->m_port_size[1] && state->m_port_write[1] ) data |= 4;
575		if ( state->m_port_size[0] && state->m_port_write[0] ) data |= 8;
	571	if ( m_port_size[1] ) data |= 1;
	572	if ( m_port_size[0] ) data |= 2;
	573	if ( m_port_size[1] && m_port_write[1] ) data |= 4;
	574	if ( m_port_size[0] && m_port_write[0] ) data |= 8;
576	575	}
577	576	else
578	577	{
579		if ( state->m_port_size[0] ) data |= 1;
580		if ( state->m_port_size[1] ) data |= 2;
581		if ( state->m_port_size[0] && state->m_port_write[0] ) data |= 4;
582		if ( state->m_port_size[1] && state->m_port_write[1] ) data |= 8;
	578	if ( m_port_size[0] ) data |= 1;
	579	if ( m_port_size[1] ) data |= 2;
	580	if ( m_port_size[0] && m_port_write[0] ) data |= 4;
	581	if ( m_port_size[1] && m_port_write[1] ) data |= 8;
583	582	}
584	583	LOG(( "%05x: card info read %02x\n", space.device().safe_pcbase(), data ));
585	584	break;
586	585
587	586
588		default: data = state->m_io[offset];
	587	default: data = m_io[offset];
589	588	}
590	589
591	590	LOG(( "%05x %f hp48_io_r: off=%02x data=%x\n",
r18045	r18046
596	595
597	596	/* ---------- GX's bank switcher --------- */
598	597
599		static READ8_HANDLER ( hp48_bank_r )
	598	READ8_MEMBER(hp48_state::hp48_bank_r)
600	599	{
601		hp48_state *state = space.machine().driver_data<hp48_state>();
602	600	/* bit 0: ignored, bits 2-5: bank number, bit 6: enable */
603	601	offset &= 0x7e;
604		if ( state->m_bank_switch != offset )
	602	if ( m_bank_switch != offset )
605	603	{
606	604	LOG(( "%05x %f hp48_bank_r: off=%03x\n", space.device().safe_pcbase(), space.machine().time().as_double(), offset ));
607		state->m_bank_switch = offset;
608		hp48_apply_modules(state);
	605	m_bank_switch = offset;
	606	hp48_apply_modules(this);
609	607	}
610	608	return 0;
611	609	}
r18045	r18046
775	773	space.install_read_bank( base, end, 0, mirror, bank );
776	774	else
777	775	{
778		if (state->m_modules[i].read != NULL)
779		space.install_legacy_read_handler( base, end, 0, mirror, state->m_modules[i].read, state->m_modules[i].read_name);
	776	if (!state->m_modules[i].read.isnull())
	777	space.install_read_handler( base, end, 0, mirror, state->m_modules[i].read);
780	778	}
781	779
782	780	if (state->m_modules[i].isnop)
r18045	r18046
787	785	space.install_write_bank( base, end, 0, mirror, bank );
788	786	else
789	787	{
790		if (state->m_modules[i].write != NULL)
791		space.install_legacy_write_handler( base, end, 0, mirror, state->m_modules[i].write, state->m_modules[i].write_name );
	788	if (!state->m_modules[i].write.isnull())
	789	space.install_write_handler( base, end, 0, mirror, state->m_modules[i].write);
792	790	}
793	791	}
794	792
r18045	r18046
988	986	state->m_port_data[conf->port] = (UINT8*)malloc( 2 * size );
989	987	memset( state->m_port_data[conf->port], 0, 2 * size );
990	988	state->m_modules[conf->module].off_mask = 2 * (( size > 128 * 1024 ) ? 128 * 1024 : size) - 1;
991		state->m_modules[conf->module].read     = NULL;
992		state->m_modules[conf->module].write    = NULL;
	989	state->m_modules[conf->module].read     = read8_delegate();
	990	state->m_modules[conf->module].write    = write8_delegate();
993	991	state->m_modules[conf->module].isnop    = 0;
994	992	if (state->m_port_write[conf->port]) {
995	993	state->m_modules[conf->module].isnop    = 1;
r18045	r18046
1004	1002	hp48_state *state = machine().driver_data<hp48_state>();
1005	1003	struct hp48_port_interface* conf = (struct hp48_port_interface*) static_config();
1006	1004	state->m_modules[conf->module].off_mask = 0x00fff;  /* 2 KB */
1007		state->m_modules[conf->module].read     = NULL;
1008		state->m_modules[conf->module].write    = NULL;
	1005	state->m_modules[conf->module].read     = read8_delegate();
	1006	state->m_modules[conf->module].write    = write8_delegate();
1009	1007	state->m_modules[conf->module].data     = NULL;
1010	1008	}
1011	1009
r18045	r18046
1097	1095	for ( i = 0; i < 6; i++ )
1098	1096	{
1099	1097	m_modules[i].off_mask = 0x00fff;  /* 2 KB */
1100		m_modules[i].read     = NULL;
1101		m_modules[i].write    = NULL;
	1098	m_modules[i].read     = read8_delegate();
	1099	m_modules[i].write    = write8_delegate();
1102	1100	m_modules[i].data     = NULL;
1103	1101	}
1104	1102	m_port_size[0] = 0;
r18045	r18046
1112	1110	hp48_update_annunciators(this);
1113	1111	}
1114	1112
1115		static void hp48_machine_start( running_machine &machine, hp48_models model )
	1113	void hp48_state::hp48_machine_start( hp48_models model )
1116	1114	{
1117		hp48_state *state = machine.driver_data<hp48_state>();
	1115	hp48_state *state = machine().driver_data<hp48_state>();
1118	1116	UINT8* rom, *ram;
1119	1117	int ram_size, rom_size, i;
1120	1118
1121	1119	LOG(( "hp48_machine_start: model %i\n", model ));
1122	1120
1123		state->m_model = model;
	1121	m_model = model;
1124	1122
1125	1123	/* internal RAM */
1126	1124	ram_size = HP48_GX_MODEL ? (128 * 1024) : (32 * 1024);
1127	1125
1128		ram = auto_alloc_array(machine, UINT8, 2 * ram_size);
1129		machine.device<nvram_device>("nvram")->set_base(ram, 2 * ram_size);
	1126	ram = auto_alloc_array(machine(), UINT8, 2 * ram_size);
	1127	machine().device<nvram_device>("nvram")->set_base(ram, 2 * ram_size);
1130	1128
1131	1129
1132	1130	/* ROM load */
1133	1131	rom_size = HP48_S_SERIES ? (256 * 1024) : (512 * 1024);
1134		rom = auto_alloc_array(machine, UINT8, 2 * rom_size);
1135		hp48_decode_nibble( rom, state->memregion( "maincpu" )->base(), rom_size );
	1132	rom = auto_alloc_array(machine(), UINT8, 2 * rom_size);
	1133	hp48_decode_nibble( rom, memregion( "maincpu" )->base(), rom_size );
1136	1134
1137	1135	/* init state */
1138	1136	memset( ram, 0, 2 * ram_size );
1139		memset( state->m_io, 0, sizeof( state->m_io ) );
1140		state->m_out = 0;
1141		state->m_kdn = 0;
1142		state->m_crc = 0;
1143		state->m_timer1 = 0;
1144		state->m_timer2 = 0;
1145		state->m_bank_switch = 0;
	1137	memset( m_io, 0, sizeof( m_io ) );
	1138	m_out = 0;
	1139	m_kdn = 0;
	1140	m_crc = 0;
	1141	m_timer1 = 0;
	1142	m_timer2 = 0;
	1143	m_bank_switch = 0;
1146	1144
1147	1145	/* static module configuration */
1148		memset(state->m_modules,0,sizeof(state->m_modules)); // to put all on 0
	1146	memset(m_modules,0,sizeof(m_modules)); // to put all on 0
1149	1147	/* I/O RAM */
1150		state->m_modules[0].off_mask = 0x0003f;  /* 32 B */
1151		state->m_modules[0].read     = hp48_io_r;
1152		state->m_modules[0].read_name     = "hp48_io_r";
1153		state->m_modules[0].write    = hp48_io_w;
1154		state->m_modules[0].write_name    = "hp48_io_w";
	1148	m_modules[0].off_mask = 0x0003f;  /* 32 B */
	1149	m_modules[0].read     = read8_delegate(FUNC(hp48_state::hp48_io_r),this);
	1150	m_modules[0].write    = write8_delegate(FUNC(hp48_state::hp48_io_w),this);
1155	1151
1156	1152	/* internal RAM */
1157		state->m_modules[1].off_mask = 2 * ram_size - 1;
1158		state->m_modules[1].read    = NULL;
1159		state->m_modules[1].write    = NULL;
1160		state->m_modules[1].data     = ram;
	1153	m_modules[1].off_mask = 2 * ram_size - 1;
	1154	m_modules[1].read    = read8_delegate();
	1155	m_modules[1].write    = write8_delegate();
	1156	m_modules[1].data     = ram;
1161	1157
1162	1158	if ( HP48_G_SERIES )
1163	1159	{
1164	1160	/* bank switcher */
1165		state->m_modules[2].off_mask = 0x00fff;  /* 2 KB */
1166		state->m_modules[2].read     = hp48_bank_r;
1167		state->m_modules[2].read_name    = "hp48_bank_r";
1168		state->m_modules[2].write    = NULL;
	1161	m_modules[2].off_mask = 0x00fff;  /* 2 KB */
	1162	m_modules[2].read     = read8_delegate(FUNC(hp48_state::hp48_bank_r),this);
	1163	m_modules[2].write    = write8_delegate();
1169	1164	}
1170	1165
1171	1166	/* ROM */
1172		state->m_modules[5].off_mask = 2 * rom_size - 1;
1173		state->m_modules[5].read    = NULL;
1174		state->m_modules[5].write    = NULL;
1175		state->m_modules[5].isnop    = 1;
1176		state->m_modules[5].data     = rom;
	1167	m_modules[5].off_mask = 2 * rom_size - 1;
	1168	m_modules[5].read    = read8_delegate();
	1169	m_modules[5].write    = write8_delegate();
	1170	m_modules[5].isnop    = 1;
	1171	m_modules[5].data     = rom;
1177	1172
1178	1173	/* timers */
1179		machine.scheduler().timer_pulse(attotime::from_hz( 16 ), FUNC(hp48_timer1_cb));
1180		machine.scheduler().timer_pulse(attotime::from_hz( 8192 ), FUNC(hp48_timer2_cb));
	1174	machine().scheduler().timer_pulse(attotime::from_hz( 16 ), FUNC(hp48_timer1_cb));
	1175	machine().scheduler().timer_pulse(attotime::from_hz( 8192 ), FUNC(hp48_timer2_cb));
1181	1176
1182	1177	/* 1ms keyboard polling */
1183		machine.scheduler().timer_pulse(attotime::from_msec( 1 ), FUNC(hp48_kbd_cb));
	1178	machine().scheduler().timer_pulse(attotime::from_msec( 1 ), FUNC(hp48_kbd_cb));
1184	1179
1185	1180	/* save state */
1186		state->save_item(NAME(state->m_out) );
1187		state->save_item(NAME(state->m_kdn) );
1188		state->save_item(NAME(state->m_io_addr) );
1189		state->save_item(NAME(state->m_crc) );
1190		state->save_item(NAME(state->m_timer1) );
1191		state->save_item(NAME(state->m_timer2) );
1192		state->save_item(NAME(state->m_bank_switch) );
	1181	save_item(NAME(m_out) );
	1182	save_item(NAME(m_kdn) );
	1183	save_item(NAME(m_io_addr) );
	1184	save_item(NAME(m_crc) );
	1185	save_item(NAME(m_timer1) );
	1186	save_item(NAME(m_timer2) );
	1187	save_item(NAME(m_bank_switch) );
1193	1188	for ( i = 0; i < 6; i++ )
1194	1189	{
1195		state_save_register_item(machine, "globals", NULL, i, state->m_modules[i].state );
1196		state_save_register_item(machine, "globals", NULL, i, state->m_modules[i].base );
1197		state_save_register_item(machine, "globals", NULL, i, state->m_modules[i].mask );
	1190	state_save_register_item(machine(), "globals", NULL, i, m_modules[i].state );
	1191	state_save_register_item(machine(), "globals", NULL, i, m_modules[i].base );
	1192	state_save_register_item(machine(), "globals", NULL, i, m_modules[i].mask );
1198	1193	}
1199		state->save_item(NAME(state->m_io) );
	1194	save_item(NAME(m_io) );
1200	1195	//state_save_register_global_pointer(machine,  machine.generic.nvram.u8, machine.generic.nvram_size );
1201	1196
1202		machine.save().register_postload( save_prepost_delegate(FUNC(hp48_update_annunciators), state ));
1203		machine.save().register_postload( save_prepost_delegate(FUNC(hp48_apply_modules), state ));
	1197	machine().save().register_postload( save_prepost_delegate(FUNC(hp48_update_annunciators), state ));
	1198	machine().save().register_postload( save_prepost_delegate(FUNC(hp48_apply_modules), state ));
1204	1199
1205	1200	#ifdef CHARDEV
1206	1201	/* direct I/O */
1207		state->m_chardev = chardev_open_pty( machine, &hp48_chardev_iface );
	1202	m_chardev = chardev_open_pty( machine(), &hp48_chardev_iface );
1208	1203	#endif
1209	1204	}
1210	1205
1211	1206
1212	1207	MACHINE_START_MEMBER(hp48_state,hp48s)
1213	1208	{
1214		hp48_machine_start( machine(), HP48_S );
	1209	hp48_machine_start( HP48_S );
1215	1210	}
1216	1211
1217	1212
1218	1213	MACHINE_START_MEMBER(hp48_state,hp48sx)
1219	1214	{
1220		hp48_machine_start( machine(), HP48_SX );
	1215	hp48_machine_start( HP48_SX );
1221	1216	}
1222	1217
1223	1218
1224	1219	MACHINE_START_MEMBER(hp48_state,hp48g)
1225	1220	{
1226		hp48_machine_start( machine(), HP48_G );
	1221	hp48_machine_start( HP48_G );
1227	1222	}
1228	1223
1229	1224	MACHINE_START_MEMBER(hp48_state,hp48gx)
1230	1225	{
1231		hp48_machine_start( machine(), HP48_GX );
	1226	hp48_machine_start( HP48_GX );
1232	1227	}
1233	1228
1234	1229	MACHINE_START_MEMBER(hp48_state,hp48gp)
1235	1230	{
1236		hp48_machine_start( machine(), HP48_GP );
	1231	hp48_machine_start( HP48_GP );
1237	1232	}

trunk/src/mess/includes/hp48.h

r18045	r18046
24	24	{
25	25	/* static part */
26	26	UINT32 off_mask;             /* offset bit-mask, indicates the real size */
27		read8_space_func read;
28		const char *read_name;
29		write8_space_func write;
30		const char *write_name;
	27	read8_delegate read;
	28	write8_delegate write;
31	29	void* data;                  /* non-NULL for banks */
32	30	int isnop;
33	31
r18045	r18046
76	74	DECLARE_MACHINE_START(hp48sx);
77	75	DECLARE_MACHINE_START(hp48s);
78	76	UINT32 screen_update_hp48(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
	77	void hp48_machine_start(hp48_models model);
	78	DECLARE_WRITE8_MEMBER(hp48_io_w);
	79	DECLARE_READ8_MEMBER(hp48_io_r);
	80	DECLARE_READ8_MEMBER(hp48_bank_r);
79	81	};
80	82
81	83

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