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r18035 Thursday 20th September, 2012 at 08:36:19 UTC by Miodrag Milanović
Modernized archimedes (no whatsnew)

[src/mame/drivers]	aristmk5.c ertictac.c
[src/mame/includes]	archimds.h
[src/mame/machine]	archimds.c
[src/mame/video]	archimds.c
[src/mess/drivers]	a310.c

trunk/src/mame/machine/archimds.c

r18034	r18035
35	35	#include "machine/wd17xx.h"
36	36
37	37	static const int page_sizes[4] = { 4096, 8192, 16384, 32768 };
	38	static const UINT32 pixel_rate[4] = { 8000000, 12000000, 16000000, 24000000};
38	39
39	40	#define IOC_LOG 0
40	41
41		static UINT32 *archimedes_memc_physmem;
42		static UINT32 memc_pagesize;
43		static int memc_latchrom;
44		static UINT32 ioc_timercnt[4], ioc_timerout[4];
45		static UINT32 vidc_vidstart, vidc_vidend, vidc_vidinit,vidc_vidcur;
46		static UINT32 vidc_sndstart, vidc_sndend, vidc_sndcur;
47		static UINT8 video_dma_on,audio_dma_on;
48		UINT8 i2c_clk;
49		INT16 memc_pages[0x2000];   // the logical RAM area is 32 megs, and the smallest page size is 4k
50		UINT32 vidc_regs[256];
51		UINT8 ioc_regs[0x80/4];
52		UINT8 vidc_bpp_mode;
53		UINT8 vidc_interlace;
54		static UINT8 vidc_pixel_clk;
55		static const UINT32 pixel_rate[4] = { 8000000, 12000000, 16000000, 24000000};
56		static UINT8 vidc_stereo_reg[8];
57
58		static emu_timer *timer[4], *snd_timer, *vid_timer;
59		static emu_timer *vbl_timer;
60
61		void archimedes_request_irq_a(running_machine &machine, int mask)
	42	void archimedes_state::archimedes_request_irq_a(int mask)
62	43	{
63		ioc_regs[IRQ_STATUS_A] |= mask;
	44	m_ioc_regs[IRQ_STATUS_A] |= mask;
64	45
65		if (ioc_regs[IRQ_MASK_A] & mask)
	46	if (m_ioc_regs[IRQ_MASK_A] & mask)
66	47	{
67		machine.device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, ASSERT_LINE);
	48	machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, ASSERT_LINE);
68	49	}
69	50	}
70	51
71		void archimedes_request_irq_b(running_machine &machine, int mask)
	52	void archimedes_state::archimedes_request_irq_b(int mask)
72	53	{
73		ioc_regs[IRQ_STATUS_B] |= mask;
	54	m_ioc_regs[IRQ_STATUS_B] |= mask;
74	55
75		if (ioc_regs[IRQ_MASK_B] & mask)
	56	if (m_ioc_regs[IRQ_MASK_B] & mask)
76	57	{
77		generic_pulse_irq_line(machine.device("maincpu"), ARM_IRQ_LINE, 1);
	58	generic_pulse_irq_line(machine().device("maincpu")->execute(), ARM_IRQ_LINE, 1);
78	59	}
79	60	}
80	61
81		void archimedes_request_fiq(running_machine &machine, int mask)
	62	void archimedes_state::archimedes_request_fiq(int mask)
82	63	{
83		ioc_regs[FIQ_STATUS] |= mask;
	64	m_ioc_regs[FIQ_STATUS] |= mask;
84	65
85		if (ioc_regs[FIQ_MASK] & mask)
	66	if (m_ioc_regs[FIQ_MASK] & mask)
86	67	{
87		generic_pulse_irq_line(machine.device("maincpu"), ARM_FIRQ_LINE, 1);
	68	generic_pulse_irq_line(machine().device("maincpu")->execute(), ARM_FIRQ_LINE, 1);
88	69	}
89	70	}
90	71
91		void archimedes_clear_irq_a(running_machine &machine, int mask)
	72	void archimedes_state::archimedes_clear_irq_a(int mask)
92	73	{
93		ioc_regs[IRQ_STATUS_A] &= ~mask;
	74	m_ioc_regs[IRQ_STATUS_A] &= ~mask;
94	75	}
95	76
96		void archimedes_clear_irq_b(running_machine &machine, int mask)
	77	void archimedes_state::archimedes_clear_irq_b(int mask)
97	78	{
98		ioc_regs[IRQ_STATUS_B] &= ~mask;
	79	m_ioc_regs[IRQ_STATUS_B] &= ~mask;
99	80	}
100	81
101		void archimedes_clear_fiq(running_machine &machine, int mask)
	82	void archimedes_state::archimedes_clear_fiq(int mask)
102	83	{
103		ioc_regs[FIQ_STATUS] &= ~mask;
	84	m_ioc_regs[FIQ_STATUS] &= ~mask;
104	85	}
105	86
106		static TIMER_CALLBACK( vidc_vblank )
	87	void archimedes_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
107	88	{
108		archimedes_request_irq_a(machine, ARCHIMEDES_IRQA_VBL);
	89	switch (id)
	90	{
	91	case TIMER_VBLANK: vidc_vblank();break;
	92	case TIMER_VIDEO: vidc_video_tick(); break;
	93	case TIMER_AUDIO: vidc_audio_tick(); break;
	94	case TIMER_IOC: ioc_timer(param); break;
	95	}
	96	}
109	97
	98
	99	void archimedes_state::vidc_vblank()
	100	{
	101	archimedes_request_irq_a(ARCHIMEDES_IRQA_VBL);
	102
110	103	// set up for next vbl
111		vbl_timer->adjust(machine.primary_screen->time_until_pos(vidc_regs[0xb4]));
	104	m_vbl_timer->adjust(machine().primary_screen->time_until_pos(m_vidc_regs[0xb4]));
112	105	}
113	106
114	107	/* video DMA */
115	108	/* TODO: what type of DMA this is, burst or cycle steal? Docs doesn't explain it (4 usec is the DRAM refresh). */
116		static TIMER_CALLBACK( vidc_video_tick )
	109	void archimedes_state::vidc_video_tick()
117	110	{
118		address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
119		static UINT8 *vram = machine.root_device().memregion("vram")->base();
	111	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
	112	static UINT8 *vram = machine().root_device().memregion("vram")->base();
120	113	UINT32 size;
121	114
122		size = vidc_vidend-vidc_vidstart+0x10;
	115	size = m_vidc_vidend-m_vidc_vidstart+0x10;
123	116
124		for(vidc_vidcur = 0;vidc_vidcur < size;vidc_vidcur++)
125		vram[vidc_vidcur] = (space.read_byte(vidc_vidstart+vidc_vidcur));
	117	for(m_vidc_vidcur = 0;m_vidc_vidcur < size;m_vidc_vidcur++)
	118	vram[m_vidc_vidcur] = (space.read_byte(m_vidc_vidstart+m_vidc_vidcur));
126	119
127		if(video_dma_on)
128		vid_timer->adjust(space.machine().primary_screen->time_until_pos(vidc_regs[0xb4]));
	120	if(m_video_dma_on)
	121	m_vid_timer->adjust(machine().primary_screen->time_until_pos(m_vidc_regs[0xb4]));
129	122	else
130		vid_timer->adjust(attotime::never);
	123	m_vid_timer->adjust(attotime::never);
131	124	}
132	125
133	126	/* audio DMA */
134		static TIMER_CALLBACK( vidc_audio_tick )
	127	void archimedes_state::vidc_audio_tick()
135	128	{
136		address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
	129	address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
137	130	UINT8 ulaw_comp;
138	131	INT16 res;
139	132	UINT8 ch;
r18034	r18035
176	169
177	170	for(ch=0;ch<8;ch++)
178	171	{
179		UINT8 ulaw_temp = (space.read_byte(vidc_sndstart+vidc_sndcur + ch)) ^ 0xff;
	172	UINT8 ulaw_temp = (space.read_byte(m_vidc_sndstart+m_vidc_sndcur + ch)) ^ 0xff;
180	173
181	174	ulaw_comp = (ulaw_temp>>1) | ((ulaw_temp&1)<<7);
182	175
183	176	res = mulawTable[ulaw_comp];
184	177
185		space.machine().device<dac_device>(dac_port[ch & 7])->write_signed16(res^0x8000);
	178	machine().device<dac_device>(dac_port[ch & 7])->write_signed16(res^0x8000);
186	179	}
187	180
188		vidc_sndcur+=8;
	181	m_vidc_sndcur+=8;
189	182
190		if (vidc_sndcur >= (vidc_sndend-vidc_sndstart)+0x10)
	183	if (m_vidc_sndcur >= (m_vidc_sndend-m_vidc_sndstart)+0x10)
191	184	{
192		vidc_sndcur = 0;
193		archimedes_request_irq_b(machine, ARCHIMEDES_IRQB_SOUND_EMPTY);
	185	m_vidc_sndcur = 0;
	186	archimedes_request_irq_b(ARCHIMEDES_IRQB_SOUND_EMPTY);
194	187
195		if(!audio_dma_on)
	188	if(!m_audio_dma_on)
196	189	{
197		snd_timer->adjust(attotime::never);
	190	m_snd_timer->adjust(attotime::never);
198	191	for(ch=0;ch<8;ch++)
199		space.machine().device<dac_device>(dac_port[ch & 7])->write_signed16(0x8000);
	192	machine().device<dac_device>(dac_port[ch & 7])->write_signed16(0x8000);
200	193	}
201	194	}
202	195	}
203	196
204		static void a310_set_timer(int tmr)
	197	void archimedes_state::a310_set_timer(int tmr)
205	198	{
206	199	double freq;
207	200
r18034	r18035
209	202	{
210	203	case 0:
211	204	case 1:
212		timer[tmr]->adjust(attotime::from_usec(ioc_timercnt[tmr]/8), tmr); // TODO: ARM timings are quite off there, it should be latch and not latch/8
	205	m_timer[tmr]->adjust(attotime::from_usec(m_ioc_timercnt[tmr]/8), tmr); // TODO: ARM timings are quite off there, it should be latch and not latch/8
213	206	break;
214	207	case 2:
215		freq = 1000000.0 / (double)(ioc_timercnt[tmr]+1);
216		timer[tmr]->adjust(attotime::from_hz(freq), tmr);
	208	freq = 1000000.0 / (double)(m_ioc_timercnt[tmr]+1);
	209	m_timer[tmr]->adjust(attotime::from_hz(freq), tmr);
217	210	break;
218	211	case 3:
219		freq = 1000000.0 / (double)((ioc_timercnt[tmr]+1)*16);
220		timer[tmr]->adjust(attotime::from_hz(freq), tmr);
	212	freq = 1000000.0 / (double)((m_ioc_timercnt[tmr]+1)*16);
	213	m_timer[tmr]->adjust(attotime::from_hz(freq), tmr);
221	214	break;
222	215	}
223	216	}
224	217
225	218	// param
226		static TIMER_CALLBACK( ioc_timer )
	219	void archimedes_state::ioc_timer(int param)
227	220	{
228	221	// all timers always run
229	222	a310_set_timer(param);
r18034	r18035
232	225	switch (param)
233	226	{
234	227	case 0:
235		archimedes_request_irq_a(machine, ARCHIMEDES_IRQA_TIMER0);
	228	archimedes_request_irq_a(ARCHIMEDES_IRQA_TIMER0);
236	229	break;
237	230
238	231	case 1:
239		archimedes_request_irq_a(machine, ARCHIMEDES_IRQA_TIMER1);
	232	archimedes_request_irq_a(ARCHIMEDES_IRQA_TIMER1);
240	233	break;
241	234	}
242	235	}
243	236
244		void archimedes_reset(running_machine &machine)
	237	void archimedes_state::archimedes_reset()
245	238	{
246	239	int i;
247	240
248		memc_latchrom = 1;         // map in the boot ROM
	241	m_memc_latchrom = 1;         // map in the boot ROM
249	242
250	243	// kill all memc mappings
251	244	for (i = 0; i < (32*1024*1024)/(4096); i++)
252	245	{
253		memc_pages[i] = -1;      // indicate unmapped
	246	m_memc_pages[i] = -1;      // indicate unmapped
254	247	}
255	248
256		ioc_regs[IRQ_STATUS_A] = 0x10 | 0x80; //set up POR (Power On Reset) and Force IRQ at start-up
257		ioc_regs[IRQ_STATUS_B] = 0x02; //set up IL[1] On
258		ioc_regs[FIQ_STATUS] = 0x80;   //set up Force FIQ
259		ioc_regs[CONTROL] = 0xff;
	249	m_ioc_regs[IRQ_STATUS_A] = 0x10 | 0x80; //set up POR (Power On Reset) and Force IRQ at start-up
	250	m_ioc_regs[IRQ_STATUS_B] = 0x02; //set up IL[1] On
	251	m_ioc_regs[FIQ_STATUS] = 0x80;   //set up Force FIQ
	252	m_ioc_regs[CONTROL] = 0xff;
260	253	}
261	254
262		void archimedes_init(running_machine &machine)
	255	void archimedes_state::archimedes_init()
263	256	{
264		memc_pagesize = 0;
	257	m_memc_pagesize = 0;
265	258
266		vbl_timer = machine.scheduler().timer_alloc(FUNC(vidc_vblank));
267		vbl_timer->adjust(attotime::never);
	259	m_vbl_timer = timer_alloc(TIMER_VBLANK);
	260	m_vbl_timer->adjust(attotime::never);
268	261
269		timer[0] = machine.scheduler().timer_alloc(FUNC(ioc_timer));
270		timer[1] = machine.scheduler().timer_alloc(FUNC(ioc_timer));
271		timer[2] = machine.scheduler().timer_alloc(FUNC(ioc_timer));
272		timer[3] = machine.scheduler().timer_alloc(FUNC(ioc_timer));
273		timer[0]->adjust(attotime::never);
274		timer[1]->adjust(attotime::never);
275		timer[2]->adjust(attotime::never);
276		timer[3]->adjust(attotime::never);
	262	m_timer[0] = timer_alloc(TIMER_IOC);
	263	m_timer[1] = timer_alloc(TIMER_IOC);
	264	m_timer[2] = timer_alloc(TIMER_IOC);
	265	m_timer[3] = timer_alloc(TIMER_IOC);
	266	m_timer[0]->adjust(attotime::never);
	267	m_timer[1]->adjust(attotime::never);
	268	m_timer[2]->adjust(attotime::never);
	269	m_timer[3]->adjust(attotime::never);
277	270
278		vid_timer = machine.scheduler().timer_alloc(FUNC(vidc_video_tick));
279		snd_timer = machine.scheduler().timer_alloc(FUNC(vidc_audio_tick));
280		snd_timer->adjust(attotime::never);
	271	m_vid_timer = timer_alloc(TIMER_VIDEO);
	272	m_snd_timer = timer_alloc(TIMER_AUDIO);
	273	m_snd_timer->adjust(attotime::never);
281	274	}
282	275
283		READ32_HANDLER(archimedes_memc_logical_r)
	276	READ32_MEMBER(archimedes_state::archimedes_memc_logical_r)
284	277	{
285	278	UINT32 page, poffs;
286	279
287	280	// are we mapping in the boot ROM?
288		if (memc_latchrom)
	281	if (m_memc_latchrom)
289	282	{
290	283	UINT32 *rom;
291	284
292		rom = (UINT32 *)space.machine().root_device().memregion("maincpu")->base();
	285	rom = (UINT32 *)machine().root_device().memregion("maincpu")->base();
293	286
294	287	return rom[offset & 0x1fffff];
295	288	}
296	289	else
297	290	{
298	291	// figure out the page number and offset in the page
299		page = (offset<<2) / page_sizes[memc_pagesize];
300		poffs = (offset<<2) % page_sizes[memc_pagesize];
	292	page = (offset<<2) / page_sizes[m_memc_pagesize];
	293	poffs = (offset<<2) % page_sizes[m_memc_pagesize];
301	294
302	295	//      printf("Reading offset %x (addr %x): page %x (size %d %d) offset %x ==> %x %x\n", offset, offset<<2, page, memc_pagesize, page_sizes[memc_pagesize], poffs, memc_pages[page], memc_pages[page]*page_sizes[memc_pagesize]);
303	296
304		if (memc_pages[page] != -1)
	297	if (m_memc_pages[page] != -1)
305	298	{
306		return archimedes_memc_physmem[((memc_pages[page] * page_sizes[memc_pagesize]) + poffs)>>2];
	299	return m_archimedes_memc_physmem[((m_memc_pages[page] * page_sizes[m_memc_pagesize]) + poffs)>>2];
307	300	}
308	301	else
309	302	{
r18034	r18035
317	310
318	311
319	312
320		WRITE32_HANDLER(archimedes_memc_logical_w)
	313	WRITE32_MEMBER(archimedes_state::archimedes_memc_logical_w)
321	314	{
322	315	UINT32 page, poffs;
323	316
324	317	// if the boot ROM is mapped, ignore writes
325		if (memc_latchrom)
	318	if (m_memc_latchrom)
326	319	{
327	320	return;
328	321	}
329	322	else
330	323	{
331	324	// figure out the page number and offset in the page
332		page = (offset<<2) / page_sizes[memc_pagesize];
333		poffs = (offset<<2) % page_sizes[memc_pagesize];
	325	page = (offset<<2) / page_sizes[m_memc_pagesize];
	326	poffs = (offset<<2) % page_sizes[m_memc_pagesize];
334	327
335	328	//      printf("Writing offset %x (addr %x): page %x (size %d %d) offset %x ==> %x %x\n", offset, offset<<2, page, memc_pagesize, page_sizes[memc_pagesize], poffs, memc_pages[page], memc_pages[page]*page_sizes[memc_pagesize]);
336	329
337		if (memc_pages[page] != -1)
	330	if (m_memc_pages[page] != -1)
338	331	{
339		COMBINE_DATA(&archimedes_memc_physmem[((memc_pages[page] * page_sizes[memc_pagesize]) + poffs)>>2]);
	332	COMBINE_DATA(&m_archimedes_memc_physmem[((m_memc_pages[page] * page_sizes[m_memc_pagesize]) + poffs)>>2]);
340	333	}
341	334	else
342	335	{
r18034	r18035
346	339	}
347	340
348	341	/* Aristocrat Mark 5 - same as normal AA except with Dram emulator */
349		READ32_HANDLER(aristmk5_drame_memc_logical_r)
	342	READ32_MEMBER(archimedes_state::aristmk5_drame_memc_logical_r)
350	343	{
351	344	UINT32 page, poffs;
352	345
353	346	// are we mapping in the boot ROM?
354		if (memc_latchrom)
	347	if (m_memc_latchrom)
355	348	{
356	349	UINT32 *rom;
357	350
358		rom = (UINT32 *)space.machine().root_device().memregion("maincpu")->base();
	351	rom = (UINT32 *)machine().root_device().memregion("maincpu")->base();
359	352
360	353	return rom[offset & 0x1fffff];
361	354	}
362	355	else
363	356	{
364	357	// figure out the page number and offset in the page
365		page = (offset<<2) / page_sizes[memc_pagesize];
366		poffs = (offset<<2) % page_sizes[memc_pagesize];
	358	page = (offset<<2) / page_sizes[m_memc_pagesize];
	359	poffs = (offset<<2) % page_sizes[m_memc_pagesize];
367	360
368	361
369	362
370		if (memc_pages[page] != -1)
	363	if (m_memc_pages[page] != -1)
371	364	{
372	365	/******************* DRAM Emulator - gal20v - Aristocrat Mark 5 ************************
373	366	A Dynamic RAM emulator is provided which avoids the need to execute code
r18034	r18035
380	373	In this state, DRAM memory space is disabled.
381	374
382	375	****************************************************************************************/
383		if(!(memc_pages[page] & 0x10)  && (offset <= 0x3ff))
	376	if(!(m_memc_pages[page] & 0x10)  && (offset <= 0x3ff))
384	377	return 0xEAD0000A;
385		return archimedes_memc_physmem[((memc_pages[page] * page_sizes[memc_pagesize]) + poffs)>>2];
	378	return m_archimedes_memc_physmem[((m_memc_pages[page] * page_sizes[m_memc_pagesize]) + poffs)>>2];
386	379	}
387	380	else
388	381	{
r18034	r18035
394	387	return 0;
395	388	}
396	389
397		#if 0
398		DIRECT_UPDATE_HANDLER( a310_setopbase )
	390	void archimedes_state::archimedes_driver_init()
399	391	{
400		// if we're not in logical memory, MAME can do the right thing
401		if (address > 0x1ffffff)
402		{
403		return address;
404		}
405
406		// if the boot ROM is mapped in, do some trickery to make it show up
407		if (memc_latchrom)
408		{
409		direct.explicit_configure(0x000000, 0x1fffff, 0x1fffff, *direct.space().machine().root_device().memregion("maincpu"));
410		}
411		else   // executing from logical memory
412		{
413		offs_t pagesize = page_sizes[memc_pagesize];
414		UINT32 page = address / pagesize;
415
416		direct.explicit_configure(page * pagesize, page * pagesize - 1, pagesize - 1, &archimedes_memc_physmem[(memc_pages[page] * pagesize)>>2]);
417		}
418
419		return ~0;
420		}
421		#endif
422
423		void archimedes_driver_init(running_machine &machine)
424		{
425		archimedes_memc_physmem = reinterpret_cast<UINT32 *>(machine.root_device().memshare("physicalram")->ptr());
	392	m_archimedes_memc_physmem = reinterpret_cast<UINT32 *>(machine().root_device().memshare("physicalram")->ptr());
426	393	//  address_space &space = machine.device<arm_device>("maincpu")->space(AS_PROGRAM);
427	394	//  space.set_direct_update_handler(direct_update_delegate(FUNC(a310_setopbase), &machine));
428	395	}
r18034	r18035
463	430	"(write) Timer 3 latch command"               // 31
464	431	};
465	432
466		static void latch_timer_cnt(int tmr)
	433	void archimedes_state::latch_timer_cnt(int tmr)
467	434	{
468		double time = timer[tmr]->elapsed().as_double();
	435	double time = m_timer[tmr]->elapsed().as_double();
469	436	time *= 2000000.0;   // find out how many 2 MHz ticks have gone by
470		ioc_timerout[tmr] = ioc_timercnt[tmr] - (UINT32)time;
	437	m_ioc_timerout[tmr] = m_ioc_timercnt[tmr] - (UINT32)time;
471	438	}
472	439
473	440	/* TODO: should be a 8-bit handler */
474		static READ32_HANDLER( ioc_ctrl_r )
	441	READ32_MEMBER( archimedes_state::ioc_ctrl_r )
475	442	{
476	443	if(IOC_LOG)
477		logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], ioc_regs[offset&0x1f], space.device() .safe_pc( ),offset & 0x1f);
	444	logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], m_ioc_regs[offset&0x1f], space.device() .safe_pc( ),offset & 0x1f);
478	445
479	446	switch (offset & 0x1f)
480	447	{
r18034	r18035
484	451	static UINT8 flyback; //internal name for vblank here
485	452	int vert_pos;
486	453
487		vert_pos = space.machine().primary_screen->vpos();
488		flyback = (vert_pos <= vidc_regs[VIDC_VDSR] || vert_pos >= vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
	454	vert_pos = machine().primary_screen->vpos();
	455	flyback = (vert_pos <= m_vidc_regs[VIDC_VDSR] || vert_pos >= m_vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
489	456
490	457	i2c_data = (i2cmem_sda_read(space.machine().device("i2cmem")) & 1);
491	458
492		return (flyback) | (ioc_regs[CONTROL] & 0x7c) | (i2c_clk<<1) | i2c_data;
	459	return (flyback) | (m_ioc_regs[CONTROL] & 0x7c) | (m_i2c_clk<<1) | i2c_data;
493	460	}
494	461
495	462	case KART:   // keyboard read
496		archimedes_request_irq_b(space.machine(), ARCHIMEDES_IRQB_KBD_XMIT_EMPTY);
	463	archimedes_request_irq_b(ARCHIMEDES_IRQB_KBD_XMIT_EMPTY);
497	464	break;
498	465
499	466	case IRQ_STATUS_A:
500		return (ioc_regs[IRQ_STATUS_A] & 0x7f) | 0x80; // Force IRQ is always '1'
	467	return (m_ioc_regs[IRQ_STATUS_A] & 0x7f) | 0x80; // Force IRQ is always '1'
501	468
502	469	case IRQ_REQUEST_A:
503		return (ioc_regs[IRQ_STATUS_A] & ioc_regs[IRQ_MASK_A]);
	470	return (m_ioc_regs[IRQ_STATUS_A] & m_ioc_regs[IRQ_MASK_A]);
504	471
505	472	case IRQ_MASK_A:
506		return (ioc_regs[IRQ_MASK_A]);
	473	return (m_ioc_regs[IRQ_MASK_A]);
507	474
508	475	case IRQ_STATUS_B:
509		return (ioc_regs[IRQ_STATUS_B]);
	476	return (m_ioc_regs[IRQ_STATUS_B]);
510	477
511	478	case IRQ_REQUEST_B:
512		return (ioc_regs[IRQ_STATUS_B] & ioc_regs[IRQ_MASK_B]);
	479	return (m_ioc_regs[IRQ_STATUS_B] & m_ioc_regs[IRQ_MASK_B]);
513	480
514	481	case IRQ_MASK_B:
515		return (ioc_regs[IRQ_MASK_B]);
	482	return (m_ioc_regs[IRQ_MASK_B]);
516	483
517	484	case FIQ_STATUS:
518		return (ioc_regs[FIQ_STATUS] & 0x7f) | 0x80; // Force FIQ is always '1'
	485	return (m_ioc_regs[FIQ_STATUS] & 0x7f) | 0x80; // Force FIQ is always '1'
519	486
520	487	case FIQ_REQUEST:
521		return (ioc_regs[FIQ_STATUS] & ioc_regs[FIQ_MASK]);
	488	return (m_ioc_regs[FIQ_STATUS] & m_ioc_regs[FIQ_MASK]);
522	489
523	490	case FIQ_MASK:
524		return (ioc_regs[FIQ_MASK]);
	491	return (m_ioc_regs[FIQ_MASK]);
525	492
526		case T0_LATCH_LO: return ioc_timerout[0]&0xff;
527		case T0_LATCH_HI: return (ioc_timerout[0]>>8)&0xff;
	493	case T0_LATCH_LO: return m_ioc_timerout[0]&0xff;
	494	case T0_LATCH_HI: return (m_ioc_timerout[0]>>8)&0xff;
528	495
529		case T1_LATCH_LO: return ioc_timerout[1]&0xff;
530		case T1_LATCH_HI: return (ioc_timerout[1]>>8)&0xff;
	496	case T1_LATCH_LO: return m_ioc_timerout[1]&0xff;
	497	case T1_LATCH_HI: return (m_ioc_timerout[1]>>8)&0xff;
531	498
532		case T2_LATCH_LO: return ioc_timerout[2]&0xff;
533		case T2_LATCH_HI: return (ioc_timerout[2]>>8)&0xff;
	499	case T2_LATCH_LO: return m_ioc_timerout[2]&0xff;
	500	case T2_LATCH_HI: return (m_ioc_timerout[2]>>8)&0xff;
534	501
535		case T3_LATCH_LO: return ioc_timerout[3]&0xff;
536		case T3_LATCH_HI: return (ioc_timerout[3]>>8)&0xff;
	502	case T3_LATCH_LO: return m_ioc_timerout[3]&0xff;
	503	case T3_LATCH_HI: return (m_ioc_timerout[3]>>8)&0xff;
537	504	default:
538	505	if(!IOC_LOG)
539		logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], ioc_regs[offset&0x1f], space.device() .safe_pc( ),offset & 0x1f);
	506	logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], m_ioc_regs[offset&0x1f], space.device() .safe_pc( ),offset & 0x1f);
540	507	break;
541	508	}
542	509
543		return ioc_regs[offset&0x1f];
	510	return m_ioc_regs[offset&0x1f];
544	511	}
545	512
546	513	/* TODO: should be a 8-bit handler */
547		static WRITE32_HANDLER( ioc_ctrl_w )
	514	WRITE32_MEMBER( archimedes_state::ioc_ctrl_w )
548	515	{
549	516	if(IOC_LOG)
550	517	logerror("IOC: W %02x @ reg %s (PC=%x)\n", data&0xff, ioc_regnames[offset&0x1f], space.device() .safe_pc( ));
r18034	r18035
553	520	{
554	521	case CONTROL:   // I2C bus control
555	522	//logerror("IOC I2C: CLK %d DAT %d\n", (data>>1)&1, data&1);
556		i2cmem_sda_write(space.machine().device("i2cmem"), data & 0x01);
557		i2cmem_scl_write(space.machine().device("i2cmem"), (data & 0x02) >> 1);
558		i2c_clk = (data & 2) >> 1;
	523	i2cmem_sda_write(machine().device("i2cmem"), data & 0x01);
	524	i2cmem_scl_write(machine().device("i2cmem"), (data & 0x02) >> 1);
	525	m_i2c_clk = (data & 2) >> 1;
559	526	break;
560	527
561	528	case KART:
r18034	r18035
568	535	break;
569	536
570	537	case IRQ_MASK_A:
571		ioc_regs[IRQ_MASK_A] = data & 0xff;
	538	m_ioc_regs[IRQ_MASK_A] = data & 0xff;
572	539
573	540	if(data & 0x80) //force an IRQ
574		archimedes_request_irq_a(space.machine(),ARCHIMEDES_IRQA_FORCE);
	541	archimedes_request_irq_a(ARCHIMEDES_IRQA_FORCE);
575	542
576	543	if(data & 0x08) //set up the VBLANK timer
577		vbl_timer->adjust(space.machine().primary_screen->time_until_pos(vidc_regs[0xb4]));
	544	m_vbl_timer->adjust(machine().primary_screen->time_until_pos(m_vidc_regs[0xb4]));
578	545
579	546	break;
580	547
581	548	case FIQ_MASK:
582		ioc_regs[FIQ_MASK] = data & 0xff;
	549	m_ioc_regs[FIQ_MASK] = data & 0xff;
583	550
584	551	if(data & 0x80) //force a FIRQ
585		archimedes_request_fiq(space.machine(),ARCHIMEDES_FIQ_FORCE);
	552	archimedes_request_fiq(ARCHIMEDES_FIQ_FORCE);
586	553
587	554	break;
588	555
589	556	case IRQ_REQUEST_A:    // IRQ clear A
590		ioc_regs[IRQ_STATUS_A] &= ~(data&0xff);
	557	m_ioc_regs[IRQ_STATUS_A] &= ~(data&0xff);
591	558
592	559	// if that did it, clear the IRQ
593	560	//if (ioc_regs[IRQ_STATUS_A] == 0)
594	561	{
595	562	//printf("IRQ clear A\n");
596		space.machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, CLEAR_LINE);
	563	machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, CLEAR_LINE);
597	564	}
598	565	break;
599	566
600	567	case T0_LATCH_LO:
601	568	case T0_LATCH_HI:
602		ioc_regs[offset&0x1f] = data & 0xff;
	569	m_ioc_regs[offset&0x1f] = data & 0xff;
603	570	break;
604	571
605	572	case T1_LATCH_LO:
606	573	case T1_LATCH_HI:
607		ioc_regs[offset&0x1f] = data & 0xff;
	574	m_ioc_regs[offset&0x1f] = data & 0xff;
608	575	break;
609	576
610	577	case T2_LATCH_LO:
611	578	case T2_LATCH_HI:
612		ioc_regs[offset&0x1f] = data & 0xff;
	579	m_ioc_regs[offset&0x1f] = data & 0xff;
613	580	break;
614	581
615	582	case T3_LATCH_LO:
616	583	case T3_LATCH_HI:
617		ioc_regs[offset&0x1f] = data & 0xff;
	584	m_ioc_regs[offset&0x1f] = data & 0xff;
618	585	break;
619	586
620	587	case T0_LATCH:   // Timer 0 latch
r18034	r18035
634	601	break;
635	602
636	603	case T0_GO:   // Timer 0 start
637		ioc_timercnt[0] = ioc_regs[T0_LATCH_HI]<<8 | ioc_regs[T0_LATCH_LO];
	604	m_ioc_timercnt[0] = m_ioc_regs[T0_LATCH_HI]<<8 | m_ioc_regs[T0_LATCH_LO];
638	605	a310_set_timer(0);
639	606	break;
640	607
641	608	case T1_GO:   // Timer 1 start
642		ioc_timercnt[1] = ioc_regs[T1_LATCH_HI]<<8 | ioc_regs[T1_LATCH_LO];
	609	m_ioc_timercnt[1] = m_ioc_regs[T1_LATCH_HI]<<8 | m_ioc_regs[T1_LATCH_LO];
643	610	a310_set_timer(1);
644	611	break;
645	612
646	613	case T2_GO:   // Timer 2 start
647		ioc_timercnt[2] = ioc_regs[T2_LATCH_HI]<<8 | ioc_regs[T2_LATCH_LO];
	614	m_ioc_timercnt[2] = m_ioc_regs[T2_LATCH_HI]<<8 | m_ioc_regs[T2_LATCH_LO];
648	615	a310_set_timer(2);
649	616	break;
650	617
651	618	case T3_GO:   // Timer 3 start
652		ioc_timercnt[3] = ioc_regs[T3_LATCH_HI]<<8 | ioc_regs[T3_LATCH_LO];
	619	m_ioc_timercnt[3] = m_ioc_regs[T3_LATCH_HI]<<8 | m_ioc_regs[T3_LATCH_LO];
653	620	a310_set_timer(3);
654	621	break;
655	622
r18034	r18035
657	624	if(!IOC_LOG)
658	625	logerror("IOC: W %02x @ reg %s (PC=%x)\n", data&0xff, ioc_regnames[offset&0x1f], space.device() .safe_pc( ));
659	626
660		ioc_regs[offset&0x1f] = data & 0xff;
	627	m_ioc_regs[offset&0x1f] = data & 0xff;
661	628	break;
662	629	}
663	630	}
664	631
665		READ32_HANDLER(archimedes_ioc_r)
	632	READ32_MEMBER(archimedes_state::archimedes_ioc_r)
666	633	{
667	634	UINT32 ioc_addr;
668	635	device_t *fdc = (device_t *)space.machine().device("wd1772");
r18034	r18035
718	685	return 0;
719	686	}
720	687
721		WRITE32_HANDLER(archimedes_ioc_w)
	688	WRITE32_MEMBER(archimedes_state::archimedes_ioc_w)
722	689	{
723	690	UINT32 ioc_addr;
724	691	device_t *fdc = (device_t *)space.machine().device("wd1772");
r18034	r18035
782	749	logerror("(PC=%08x) I/O: W %x @ %x (mask %08x)\n", space.device().safe_pc(), data, (offset*4)+0x3000000, mem_mask);
783	750	}
784	751
785		READ32_HANDLER(archimedes_vidc_r)
	752	READ32_MEMBER(archimedes_state::archimedes_vidc_r)
786	753	{
787	754	return 0;
788	755	}
789	756
790		static void vidc_dynamic_res_change(running_machine &machine)
	757	void archimedes_state::vidc_dynamic_res_change()
791	758	{
792	759	/* sanity checks - first pass */
793	760	/*
794	761	total cycles + border end
795	762	*/
796		if(vidc_regs[VIDC_HCR] && vidc_regs[VIDC_HBER] &&
797		vidc_regs[VIDC_VCR] && vidc_regs[VIDC_VBER])
	763	if(m_vidc_regs[VIDC_HCR] && m_vidc_regs[VIDC_HBER] &&
	764	m_vidc_regs[VIDC_VCR] && m_vidc_regs[VIDC_VBER])
798	765	{
799	766	/* sanity checks - second pass */
800	767	/*
801	768	total cycles >= border end >= border start
802	769	*/
803		if((vidc_regs[VIDC_HCR] >= vidc_regs[VIDC_HBER]) &&
804		(vidc_regs[VIDC_HBER] >= vidc_regs[VIDC_HBSR]) &&
805		(vidc_regs[VIDC_VCR] >= vidc_regs[VIDC_VBER]) &&
806		(vidc_regs[VIDC_VBER] >= vidc_regs[VIDC_VBSR]))
	770	if((m_vidc_regs[VIDC_HCR] >= m_vidc_regs[VIDC_HBER]) &&
	771	(m_vidc_regs[VIDC_HBER] >= m_vidc_regs[VIDC_HBSR]) &&
	772	(m_vidc_regs[VIDC_VCR] >= m_vidc_regs[VIDC_VBER]) &&
	773	(m_vidc_regs[VIDC_VBER] >= m_vidc_regs[VIDC_VBSR]))
807	774	{
808	775	rectangle visarea;
809	776	attoseconds_t refresh;
810	777
811	778	visarea.min_x = 0;
812	779	visarea.min_y = 0;
813		visarea.max_x = vidc_regs[VIDC_HBER] - vidc_regs[VIDC_HBSR] - 1;
814		visarea.max_y = vidc_regs[VIDC_VBER] - vidc_regs[VIDC_VBSR];
	780	visarea.max_x = m_vidc_regs[VIDC_HBER] - m_vidc_regs[VIDC_HBSR] - 1;
	781	visarea.max_y = m_vidc_regs[VIDC_VBER] - m_vidc_regs[VIDC_VBSR];
815	782
816	783	logerror("Configuring: htotal %d vtotal %d border %d x %d display %d x %d\n",
817		vidc_regs[VIDC_HCR], vidc_regs[VIDC_VCR],
	784	m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR],
818	785	visarea.max_x, visarea.max_y,
819		vidc_regs[VIDC_HDER]-vidc_regs[VIDC_HDSR],vidc_regs[VIDC_VDER]-vidc_regs[VIDC_VDSR]+1);
	786	m_vidc_regs[VIDC_HDER]-m_vidc_regs[VIDC_HDSR],m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR]+1);
820	787
821	788	/* FIXME: pixel clock */
822		refresh = HZ_TO_ATTOSECONDS(pixel_rate[vidc_pixel_clk]*2) * vidc_regs[VIDC_HCR] * vidc_regs[VIDC_VCR];
	789	refresh = HZ_TO_ATTOSECONDS(pixel_rate[m_vidc_pixel_clk]*2) * m_vidc_regs[VIDC_HCR] * m_vidc_regs[VIDC_VCR];
823	790
824		machine.primary_screen->configure(vidc_regs[VIDC_HCR], vidc_regs[VIDC_VCR], visarea, refresh);
	791	machine().primary_screen->configure(m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR], visarea, refresh);
825	792	}
826	793	}
827	794	}
828	795
829		WRITE32_HANDLER(archimedes_vidc_w)
	796	WRITE32_MEMBER(archimedes_state::archimedes_vidc_w)
830	797	{
831	798	UINT32 reg = data>>24;
832	799	UINT32 val = data & 0xffffff;
r18034	r18035
868	835	if(reg == 0x40 && val & 0xfff)
869	836	logerror("WARNING: border color write here (PC=%08x)!\n",space.device().safe_pc());
870	837
871		palette_set_color_rgb(space.machine(), reg >> 2, pal4bit(r), pal4bit(g), pal4bit(b) );
	838	palette_set_color_rgb(machine(), reg >> 2, pal4bit(r), pal4bit(g), pal4bit(b) );
872	839
873	840	/* handle 8bpp colors here */
874	841	if(reg <= 0x3c)
r18034	r18035
881	848	g = ((val & 0x030) >> 4) | ((i & 0x20) >> 3) | ((i & 0x40) >> 3);
882	849	r = ((val & 0x007) >> 0) | ((i & 0x10) >> 1);
883	850
884		palette_set_color_rgb(space.machine(), (reg >> 2) + 0x100 + i, pal4bit(r), pal4bit(g), pal4bit(b) );
	851	palette_set_color_rgb(machine(), (reg >> 2) + 0x100 + i, pal4bit(r), pal4bit(g), pal4bit(b) );
885	852	}
886	853	}
887	854
888	855	}
889	856	else if (reg >= 0x60 && reg <= 0x7c)
890	857	{
891		vidc_stereo_reg[(reg >> 2) & 7] = val & 0x07;
	858	m_vidc_stereo_reg[(reg >> 2) & 7] = val & 0x07;
892	859
893	860	//      popmessage("%02x %02x %02x %02x %02x %02x %02x %02x",vidc_stereo_reg[0],vidc_stereo_reg[1],vidc_stereo_reg[2],vidc_stereo_reg[3]
894	861	//      ,vidc_stereo_reg[4],vidc_stereo_reg[5],vidc_stereo_reg[6],vidc_stereo_reg[7]);
r18034	r18035
897	864	{
898	865	switch(reg)
899	866	{
900		case VIDC_HCR:  vidc_regs[VIDC_HCR] =  ((val >> 14)<<1)+1;   break;
901		//          case VIDC_HSWR: vidc_regs[VIDC_HSWR] = (val >> 14)+1;   break;
902		case VIDC_HBSR: vidc_regs[VIDC_HBSR] = ((val >> 14)<<1)+1;   break;
903		case VIDC_HDSR: vidc_regs[VIDC_HDSR] = (val >> 14);    break;
904		case VIDC_HDER: vidc_regs[VIDC_HDER] = (val >> 14);    break;
905		case VIDC_HBER: vidc_regs[VIDC_HBER] = ((val >> 14)<<1)+1;   break;
	867	case VIDC_HCR:  m_vidc_regs[VIDC_HCR] =  ((val >> 14)<<1)+1;   break;
	868	//          case VIDC_HSWR: m_vidc_regs[VIDC_HSWR] = (val >> 14)+1;   break;
	869	case VIDC_HBSR: m_vidc_regs[VIDC_HBSR] = ((val >> 14)<<1)+1;   break;
	870	case VIDC_HDSR: m_vidc_regs[VIDC_HDSR] = (val >> 14);    break;
	871	case VIDC_HDER: m_vidc_regs[VIDC_HDER] = (val >> 14);    break;
	872	case VIDC_HBER: m_vidc_regs[VIDC_HBER] = ((val >> 14)<<1)+1;   break;
906	873	//          #define VIDC_HCSR       0x98
907	874	//          #define VIDC_HIR        0x9c
908	875
909		case VIDC_VCR:  vidc_regs[VIDC_VCR] = ((val >> 14)<<1)+1;   break;
	876	case VIDC_VCR:  m_vidc_regs[VIDC_VCR] = ((val >> 14)<<1)+1;   break;
910	877	//          #define VIDC_VSWR       0xa4
911		case VIDC_VBSR: vidc_regs[VIDC_VBSR] = (val >> 14)+1;   break;
912		case VIDC_VDSR: vidc_regs[VIDC_VDSR] = (val >> 14)+1;   break;
913		case VIDC_VDER: vidc_regs[VIDC_VDER] = (val >> 14)+1;   break;
914		case VIDC_VBER: vidc_regs[VIDC_VBER] = (val >> 14)+1;   break;
	878	case VIDC_VBSR: m_vidc_regs[VIDC_VBSR] = (val >> 14)+1;   break;
	879	case VIDC_VDSR: m_vidc_regs[VIDC_VDSR] = (val >> 14)+1;   break;
	880	case VIDC_VDER: m_vidc_regs[VIDC_VDER] = (val >> 14)+1;   break;
	881	case VIDC_VBER: m_vidc_regs[VIDC_VBER] = (val >> 14)+1;   break;
915	882	//          #define VIDC_VCSR       0xb8
916	883	//          #define VIDC_VCER       0xbc
917	884	}
918	885
919	886
920	887	//#ifdef DEBUG
921		logerror("VIDC: %s = %d\n", vrnames[(reg-0x80)/4], vidc_regs[reg]);
	888	logerror("VIDC: %s = %d\n", vrnames[(reg-0x80)/4], m_vidc_regs[reg]);
922	889	//#endif
923	890
924		vidc_dynamic_res_change(space.machine());
	891	vidc_dynamic_res_change();
925	892	}
926	893	else if(reg == 0xe0)
927	894	{
928		vidc_bpp_mode = ((val & 0x0c) >> 2);
929		vidc_interlace = ((val & 0x40) >> 6);
930		vidc_pixel_clk = (val & 0x03);
931		vidc_dynamic_res_change(space.machine());
	895	m_vidc_bpp_mode = ((val & 0x0c) >> 2);
	896	m_vidc_interlace = ((val & 0x40) >> 6);
	897	m_vidc_pixel_clk = (val & 0x03);
	898	vidc_dynamic_res_change();
932	899	}
933	900	else
934	901	{
935	902	logerror("VIDC: %x to register %x\n", val, reg);
936		vidc_regs[reg] = val&0xffff;
	903	m_vidc_regs[reg] = val&0xffff;
937	904	}
938	905	}
939	906
940		READ32_HANDLER(archimedes_memc_r)
	907	READ32_MEMBER(archimedes_state::archimedes_memc_r)
941	908	{
942	909	return 0;
943	910	}
944	911
945		WRITE32_HANDLER(archimedes_memc_w)
	912	WRITE32_MEMBER(archimedes_state::archimedes_memc_w)
946	913	{
947	914	// is it a register?
948	915	if ((data & 0x0fe00000) == 0x03600000)
r18034	r18035
950	917	switch ((data >> 17) & 7)
951	918	{
952	919	case 0: /* video init */
953		vidc_vidinit = ((data>>2)&0x7fff)*16;
	920	m_vidc_vidinit = ((data>>2)&0x7fff)*16;
954	921	//logerror("MEMC: VIDINIT %08x\n",vidc_vidinit);
955	922	break;
956	923
957	924	case 1: /* video start */
958		vidc_vidstart = 0x2000000 | (((data>>2)&0x7fff)*16);
	925	m_vidc_vidstart = 0x2000000 | (((data>>2)&0x7fff)*16);
959	926	//logerror("MEMC: VIDSTART %08x\n",vidc_vidstart);
960	927	break;
961	928
962	929	case 2: /* video end */
963		vidc_vidend = 0x2000000 | (((data>>2)&0x7fff)*16);
	930	m_vidc_vidend = 0x2000000 | (((data>>2)&0x7fff)*16);
964	931	//logerror("MEMC: VIDEND %08x\n",vidc_vidend);
965	932	break;
966	933
967	934	case 4:   /* sound start */
968	935	//logerror("MEMC: SNDSTART %08x\n",data);
969		vidc_sndstart = 0x2000000 | ((data>>2)&0x7fff)*16;
970		ioc_regs[IRQ_STATUS_B] &= ~ARCHIMEDES_IRQB_SOUND_EMPTY;
	936	m_vidc_sndstart = 0x2000000 | ((data>>2)&0x7fff)*16;
	937	m_ioc_regs[IRQ_STATUS_B] &= ~ARCHIMEDES_IRQB_SOUND_EMPTY;
971	938	break;
972	939
973	940	case 5: /* sound end */
974	941	//logerror("MEMC: SNDEND %08x\n",data);
975		vidc_sndend = 0x2000000 | ((data>>2)&0x7fff)*16;
	942	m_vidc_sndend = 0x2000000 | ((data>>2)&0x7fff)*16;
976	943	break;
977	944
978	945	case 6:
979		vidc_sndcur = 0;
980		archimedes_request_irq_b(space.machine(), ARCHIMEDES_IRQB_SOUND_EMPTY);
	946	m_vidc_sndcur = 0;
	947	archimedes_request_irq_b(ARCHIMEDES_IRQB_SOUND_EMPTY);
981	948	break;
982	949
983	950	case 7:   /* Control */
984		memc_pagesize = ((data>>2) & 3);
	951	m_memc_pagesize = ((data>>2) & 3);
985	952
986		logerror("(PC = %08x) MEMC: %x to Control (page size %d, %s, %s)\n", space.device().safe_pc(), data & 0x1ffc, page_sizes[memc_pagesize], ((data>>10)&1) ? "Video DMA on" : "Video DMA off", ((data>>11)&1) ? "Sound DMA on" : "Sound DMA off");
	953	logerror("(PC = %08x) MEMC: %x to Control (page size %d, %s, %s)\n", space.device().safe_pc(), data & 0x1ffc, page_sizes[m_memc_pagesize], ((data>>10)&1) ? "Video DMA on" : "Video DMA off", ((data>>11)&1) ? "Sound DMA on" : "Sound DMA off");
987	954
988		video_dma_on = ((data>>10)&1);
989		audio_dma_on = ((data>>11)&1);
	955	m_video_dma_on = ((data>>10)&1);
	956	m_audio_dma_on = ((data>>11)&1);
990	957
991	958	if ((data>>10)&1)
992	959	{
993		vidc_vidcur = 0;
994		vid_timer->adjust(space.machine().primary_screen->time_until_pos(vidc_regs[0xb4]));
	960	m_vidc_vidcur = 0;
	961	m_vid_timer->adjust(machine().primary_screen->time_until_pos(m_vidc_regs[0xb4]));
995	962	}
996	963
997	964	if ((data>>11)&1)
r18034	r18035
999	966	double sndhz;
1000	967
1001	968	/* FIXME: is the frequency correct? */
1002		sndhz = (250000.0 / 2) / (double)((vidc_regs[0xc0]&0xff)+2);
	969	sndhz = (250000.0 / 2) / (double)((m_vidc_regs[0xc0]&0xff)+2);
1003	970
1004		printf("MEMC: Starting audio DMA at %f Hz, buffer from %x to %x\n", sndhz, vidc_sndstart, vidc_sndend);
	971	printf("MEMC: Starting audio DMA at %f Hz, buffer from %x to %x\n", sndhz, m_vidc_sndstart, m_vidc_sndend);
1005	972
1006		snd_timer->adjust(attotime::zero, 0, attotime::from_hz(sndhz));
	973	m_snd_timer->adjust(attotime::zero, 0, attotime::from_hz(sndhz));
1007	974	}
1008	975
1009	976	break;
r18034	r18035
1045	1012	1 being bit 6
1046	1013	*/
1047	1014
1048		WRITE32_HANDLER(archimedes_memc_page_w)
	1015	WRITE32_MEMBER(archimedes_state::archimedes_memc_page_w)
1049	1016	{
1050	1017	UINT32 log, phys, memc;
1051	1018
1052	1019	//  perms = (data & 0x300)>>8;
1053	1020	log = phys = memc = 0;
1054	1021
1055		switch (memc_pagesize)
	1022	switch (m_memc_pagesize)
1056	1023	{
1057	1024	case 0:
1058	1025	phys = data & 0x7f;
r18034	r18035
1083	1050	//  log >>= (12 + memc_pagesize);
1084	1051
1085	1052	// always make sure ROM mode is disconnected when this occurs
1086		memc_latchrom = 0;
	1053	m_memc_latchrom = 0;
1087	1054
1088	1055	// now go ahead and set the mapping in the page table
1089		memc_pages[log] = phys + (memc*0x80);
	1056	m_memc_pages[log] = phys + (memc*0x80);
1090	1057
1091	1058	//  printf("PC=%08x = MEMC_PAGE(%d): W %08x: log %x to phys %x, MEMC %d, perms %d\n", space.device().safe_pc(),memc_pagesize, data, log, phys, memc, perms);
1092	1059	}

trunk/src/mame/includes/archimds.h

r18034	r18035
34	34	#define ARCHIMEDES_FIQ_PODULE        (0x40)
35	35	#define ARCHIMEDES_FIQ_FORCE         (0x80)
36	36
37		/*----------- defined in machine/archimds.c -----------*/
	37	class archimedes_state : public driver_device
	38	{
	39	public:
	40	archimedes_state(const machine_config &mconfig, device_type type, const char *tag)
	41	: driver_device(mconfig, type, tag) { }
38	42
39		void archimedes_init(running_machine &machine);         // call at MACHINE_INIT
40		void archimedes_reset(running_machine &machine);      // call at MACHINE_RESET
41		void archimedes_driver_init(running_machine &machine);      // call at DRIVER_INIT
	43	void archimedes_init();
	44	void archimedes_reset();
	45	void archimedes_driver_init();
42	46
43		void archimedes_request_irq_a(running_machine &machine, int mask);
44		void archimedes_request_irq_b(running_machine &machine, int mask);
45		void archimedes_request_fiq(running_machine &machine, int mask);
46		void archimedes_clear_irq_a(running_machine &machine, int mask);
47		void archimedes_clear_irq_b(running_machine &machine, int mask);
48		void archimedes_clear_fiq(running_machine &machine, int mask);
	47	void archimedes_request_irq_a(int mask);
	48	void archimedes_request_irq_b(int mask);
	49	void archimedes_request_fiq(int mask);
	50	void archimedes_clear_irq_a(int mask);
	51	void archimedes_clear_irq_b(int mask);
	52	void archimedes_clear_fiq(int mask);
49	53
50		extern DECLARE_READ32_HANDLER(aristmk5_drame_memc_logical_r);
51		extern DECLARE_READ32_HANDLER(archimedes_memc_logical_r);
52		extern DECLARE_WRITE32_HANDLER(archimedes_memc_logical_w);
53		extern DECLARE_READ32_HANDLER(archimedes_memc_r);
54		extern DECLARE_WRITE32_HANDLER(archimedes_memc_w);
55		extern DECLARE_WRITE32_HANDLER(archimedes_memc_page_w);
56		extern DECLARE_READ32_HANDLER(archimedes_ioc_r);
57		extern DECLARE_WRITE32_HANDLER(archimedes_ioc_w);
58		extern DECLARE_READ32_HANDLER(archimedes_vidc_r);
59		extern DECLARE_WRITE32_HANDLER(archimedes_vidc_w);
	54	DECLARE_READ32_MEMBER(aristmk5_drame_memc_logical_r);
	55	DECLARE_READ32_MEMBER(archimedes_memc_logical_r);
	56	DECLARE_WRITE32_MEMBER(archimedes_memc_logical_w);
	57	DECLARE_READ32_MEMBER(archimedes_memc_r);
	58	DECLARE_WRITE32_MEMBER(archimedes_memc_w);
	59	DECLARE_WRITE32_MEMBER(archimedes_memc_page_w);
	60	DECLARE_READ32_MEMBER(archimedes_ioc_r);
	61	DECLARE_WRITE32_MEMBER(archimedes_ioc_w);
	62	DECLARE_READ32_MEMBER(archimedes_vidc_r);
	63	DECLARE_WRITE32_MEMBER(archimedes_vidc_w);
60	64
61		extern UINT8 i2c_clk;
62		extern INT16 memc_pages[0x2000];   // the logical RAM area is 32 megs, and the smallest page size is 4k
63		extern UINT32 vidc_regs[256];
64		extern UINT8 ioc_regs[0x80/4];
65		extern UINT8 vidc_bpp_mode;
66		extern UINT8 vidc_interlace;
	65	UINT8 m_i2c_clk;
	66	INT16 m_memc_pages[0x2000];   // the logical RAM area is 32 megs, and the smallest page size is 4k
	67	UINT32 m_vidc_regs[256];
	68	UINT8 m_ioc_regs[0x80/4];
	69	UINT8 m_vidc_bpp_mode;
	70	UINT8 m_vidc_interlace;
	71
	72	UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	73	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	74	private:
67	75
	76	static const device_timer_id TIMER_VBLANK = 0;
	77	static const device_timer_id TIMER_VIDEO = 1;
	78	static const device_timer_id TIMER_AUDIO = 2;
	79	static const device_timer_id TIMER_IOC = 3;
	80
	81	void vidc_vblank();
	82	void vidc_video_tick();
	83	void vidc_audio_tick();
	84	void ioc_timer(int param);
	85
	86	void vidc_dynamic_res_change();
	87	void latch_timer_cnt(int tmr);
	88	void a310_set_timer(int tmr);
	89	READ32_MEMBER(ioc_ctrl_r);
	90	WRITE32_MEMBER(ioc_ctrl_w);
	91
	92	UINT32 *m_archimedes_memc_physmem;
	93	UINT32 m_memc_pagesize;
	94	int m_memc_latchrom;
	95	UINT32 m_ioc_timercnt[4], m_ioc_timerout[4];
	96	UINT32 m_vidc_vidstart, m_vidc_vidend, m_vidc_vidinit, m_vidc_vidcur;
	97	UINT32 m_vidc_sndstart, m_vidc_sndend, m_vidc_sndcur;
	98	UINT8 m_video_dma_on,m_audio_dma_on;
	99	UINT8 m_vidc_pixel_clk;
	100	UINT8 m_vidc_stereo_reg[8];
	101	emu_timer *m_timer[4], *m_snd_timer, *m_vid_timer;
	102	emu_timer *m_vbl_timer;
	103	};
	104
68	105	/* IOC registers */
69	106
70	107	#define CONTROL         0x00/4
r18034	r18035
101	138	#define T3_GO      0x78/4
102	139	#define T3_LATCH   0x7c/4
103	140
104
105		/*----------- defined in video/archimds.c -----------*/
106
107		extern VIDEO_START( archimds_vidc );
108		extern SCREEN_UPDATE_RGB32( archimds_vidc );
109
110	141	#define VIDC_HCR      0x80
111	142	#define VIDC_HSWR      0x84
112	143	#define VIDC_HBSR      0x88

trunk/src/mame/video/archimds.c

r18034	r18035
7	7	#include "emu.h"
8	8	#include "includes/archimds.h"
9	9
10		VIDEO_START( archimds_vidc )
	10	UINT32 archimedes_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
11	11	{
12		}
13
14		SCREEN_UPDATE_RGB32( archimds_vidc )
15		{
16	12	int xstart,ystart,xend,yend;
17	13	int res_x,res_y;
18	14	int xsize,ysize;
r18034	r18035
20	16	const UINT8 x_step[4] = { 5, 7, 11, 19 };
21	17
22	18	/* border color */
23		bitmap.fill(screen.machine().pens[0x10], cliprect);
	19	bitmap.fill(machine().pens[0x10], cliprect);
24	20
25	21	/* define X display area through BPP mode register */
26		calc_dxs = (vidc_regs[VIDC_HDSR]*2)+x_step[vidc_bpp_mode & 3];
27		calc_dxe = (vidc_regs[VIDC_HDER]*2)+x_step[vidc_bpp_mode & 3];
	22	calc_dxs = (m_vidc_regs[VIDC_HDSR]*2)+x_step[m_vidc_bpp_mode & 3];
	23	calc_dxe = (m_vidc_regs[VIDC_HDER]*2)+x_step[m_vidc_bpp_mode & 3];
28	24
29	25	/* now calculate display clip rectangle start/end areas */
30		xstart = (calc_dxs)-vidc_regs[VIDC_HBSR];
31		ystart = (vidc_regs[VIDC_VDSR])-vidc_regs[VIDC_VBSR];
	26	xstart = (calc_dxs)-m_vidc_regs[VIDC_HBSR];
	27	ystart = (m_vidc_regs[VIDC_VDSR])-m_vidc_regs[VIDC_VBSR];
32	28	xend = (calc_dxe)+xstart;
33		yend = vidc_regs[VIDC_VDER]+ystart;
	29	yend = m_vidc_regs[VIDC_VDER]+ystart;
34	30
35	31	/* disable the screen if display params are invalid */
36	32	if(xstart > xend || ystart > yend)
37	33	return 0;
38	34
39	35	xsize = calc_dxe-calc_dxs;
40		ysize = vidc_regs[VIDC_VDER]-vidc_regs[VIDC_VDSR];
	36	ysize = m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR];
41	37
42	38	{
43	39	int count;
44	40	int x,y,xi;
45	41	UINT8 pen;
46		static UINT8 *vram = screen.machine().root_device().memregion("vram")->base();
	42	static UINT8 *vram = machine().root_device().memregion("vram")->base();
47	43
48	44	count = (0);
49	45
50		switch(vidc_bpp_mode)
	46	switch(m_vidc_bpp_mode)
51	47	{
52	48	case 0: //1 bpp
53	49	{
r18034	r18035
60	56	for(xi=0;xi<8;xi++)
61	57	{
62	58	res_x = x+xi+xstart;
63		res_y = (y+ystart)*(vidc_interlace+1);
	59	res_y = (y+ystart)*(m_vidc_interlace+1);
64	60
65		if(vidc_interlace)
	61	if(m_vidc_interlace)
66	62	{
67	63	if (cliprect.contains(res_x, res_y) && (res_x) <= xend && (res_y) <= yend)
68		bitmap.pix32(res_y, res_x) = screen.machine().pens[(pen>>(xi))&0x1];
	64	bitmap.pix32(res_y, res_x) = machine().pens[(pen>>(xi))&0x1];
69	65	if (cliprect.contains(res_x, res_y+1) && (res_x) <= xend && (res_y+1) <= yend)
70		bitmap.pix32(res_y+1, res_x) = screen.machine().pens[(pen>>(xi))&0x1];
	66	bitmap.pix32(res_y+1, res_x) = machine().pens[(pen>>(xi))&0x1];
71	67	}
72	68	else
73	69	{
74	70	if (cliprect.contains(res_x, res_y) && (res_x) <= xend && (res_y) <= yend)
75		bitmap.pix32(res_y, res_x) = screen.machine().pens[(pen>>(xi))&0x1];
	71	bitmap.pix32(res_y, res_x) = machine().pens[(pen>>(xi))&0x1];
76	72	}
77	73	}
78	74
r18034	r18035
90	86	pen = vram[count];
91	87
92	88	res_x = x+xstart;
93		res_y = (y+ystart)*(vidc_interlace+1);
	89	res_y = (y+ystart)*(m_vidc_interlace+1);
94	90
95		if(vidc_interlace)
	91	if(m_vidc_interlace)
96	92	{
97	93	if (cliprect.contains(res_x, res_y) && (res_x) <= xend && (res_y) <= yend)
98		bitmap.pix32(res_y, res_x) = screen.machine().pens[(pen&0xff)+0x100];
	94	bitmap.pix32(res_y, res_x) = machine().pens[(pen&0xff)+0x100];
99	95	if (cliprect.contains(res_x, res_y) && (res_x) <= xend && (res_y+1) <= yend)
100		bitmap.pix32(res_y+1, res_x) = screen.machine().pens[(pen&0xff)+0x100];
	96	bitmap.pix32(res_y+1, res_x) = machine().pens[(pen&0xff)+0x100];
101	97	}
102	98	else
103	99	{
104	100	if (cliprect.contains(res_x, res_y) && (res_x) <= xend && (res_y) <= yend)
105		bitmap.pix32(res_y, res_x) = screen.machine().pens[(pen&0xff)+0x100];
	101	bitmap.pix32(res_y, res_x) = machine().pens[(pen&0xff)+0x100];
106	102	}
107	103
108	104	count++;

trunk/src/mame/drivers/ertictac.c

r18034	r18035
28	28	#include "machine/i2cmem.h"
29	29
30	30
31		class ertictac_state : public driver_device
	31	class ertictac_state : public archimedes_state
32	32	{
33	33	public:
34	34	ertictac_state(const machine_config &mconfig, device_type type, const char *tag)
35		: driver_device(mconfig, type, tag) { }
	35	: archimedes_state(mconfig, type, tag) { }
36	36
37	37	DECLARE_READ32_MEMBER(ertictac_podule_r);
38	38	DECLARE_DRIVER_INIT(ertictac);
r18034	r18035
44	44
45	45	READ32_MEMBER(ertictac_state::ertictac_podule_r)
46	46	{
47		ioc_regs[IRQ_STATUS_B] &= ~ARCHIMEDES_IRQB_PODULE_IRQ;
	47	m_ioc_regs[IRQ_STATUS_B] &= ~ARCHIMEDES_IRQB_PODULE_IRQ;
48	48
49	49	switch(offset)
50	50	{
r18034	r18035
59	59	}
60	60
61	61	static ADDRESS_MAP_START( ertictac_map, AS_PROGRAM, 32, ertictac_state )
62		AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
	62	AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE(archimedes_memc_logical_r, archimedes_memc_logical_w)
63	63	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
64	64
65	65	AM_RANGE(0x03340000, 0x0334001f) AM_READ(ertictac_podule_r)
66	66	AM_RANGE(0x033c0000, 0x033c001f) AM_READ(ertictac_podule_r)
67	67
68		AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE_LEGACY(archimedes_ioc_r, archimedes_ioc_w)
69		AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE_LEGACY(archimedes_vidc_r, archimedes_vidc_w)
70		AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)
71		AM_RANGE(0x03800000, 0x03ffffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE_LEGACY(archimedes_memc_page_w)
	68	AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE(archimedes_ioc_r, archimedes_ioc_w)
	69	AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE(archimedes_vidc_r, archimedes_vidc_w)
	70	AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE(archimedes_memc_r, archimedes_memc_w)
	71	AM_RANGE(0x03800000, 0x03ffffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE(archimedes_memc_page_w)
72	72	ADDRESS_MAP_END
73	73
74	74	static INPUT_PORTS_START( ertictac )
r18034	r18035
193	193
194	194	DRIVER_INIT_MEMBER(ertictac_state,ertictac)
195	195	{
196		archimedes_driver_init(machine());
	196	archimedes_driver_init();
197	197	}
198	198
199	199	void ertictac_state::machine_start()
200	200	{
201		archimedes_init(machine());
	201	archimedes_init();
202	202
203	203	// reset the DAC to centerline
204	204	//machine().device<dac_device>("dac")->write_signed8(0x80);
r18034	r18035
206	206
207	207	void ertictac_state::machine_reset()
208	208	{
209		archimedes_reset(machine());
	209	archimedes_reset();
210	210	}
211	211
212	212	INTERRUPT_GEN_MEMBER(ertictac_state::ertictac_podule_irq)
213	213	{
214		archimedes_request_irq_b(machine(), ARCHIMEDES_IRQB_PODULE_IRQ);
	214	archimedes_request_irq_b(ARCHIMEDES_IRQB_PODULE_IRQ);
215	215	}
216	216
217	217	/* TODO: Are we sure that this HW have I2C device? */
r18034	r18035
237	237	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
238	238	MCFG_SCREEN_SIZE(1280, 1024)
239	239	MCFG_SCREEN_VISIBLE_AREA(0, 1280-1, 0, 1024-1)
240		MCFG_SCREEN_UPDATE_STATIC(archimds_vidc)
	240	MCFG_SCREEN_UPDATE_DRIVER(archimedes_state, screen_update)
241	241
242	242	MCFG_PALETTE_LENGTH(0x200)
243	243
244		MCFG_VIDEO_START(archimds_vidc)
245
246	244	MCFG_SPEAKER_STANDARD_MONO("mono")
247	245	MCFG_DAC_ADD("dac0")
248	246	MCFG_SOUND_ROUTE(0, "mono", 0.05)

trunk/src/mame/drivers/aristmk5.c

r18034	r18035
64	64	//#include "machine/i2cmem.h"
65	65
66	66
67		class aristmk5_state : public driver_device
	67	class aristmk5_state : public archimedes_state
68	68	{
69	69	public:
70	70	aristmk5_state(const machine_config &mconfig, device_type type, const char *tag)
71		: driver_device(mconfig, type, tag) { }
	71	: archimedes_state(mconfig, type, tag) { }
72	72
73	73	emu_timer *m_mk5_2KHz_timer;
74	74	emu_timer *m_mk5_VSYNC_timer;
r18034	r18035
89	89	static TIMER_CALLBACK( mk5_VSYNC_callback )
90	90	{
91	91	aristmk5_state *state = machine.driver_data<aristmk5_state>();
92		ioc_regs[IRQ_STATUS_A] |= 0x08; //turn vsync bit on
	92	state->m_ioc_regs[IRQ_STATUS_A] |= 0x08; //turn vsync bit on
93	93	state->m_mk5_VSYNC_timer->adjust(attotime::never);
94	94	}
95	95
r18034	r18035
131	131	*/
132	132
133	133
134		ioc_regs[IRQ_STATUS_A] &= ~0x08;
	134	m_ioc_regs[IRQ_STATUS_A] &= ~0x08;
135	135
136	136	/*          bit 1              bit 0 */
137	137	if((data &~(0x02)) && (data & (0x01))) // external video crystal is enabled. 25 mhz
r18034	r18035
155	155	static TIMER_CALLBACK( mk5_2KHz_callback )
156	156	{
157	157	aristmk5_state *state = machine.driver_data<aristmk5_state>();
158		ioc_regs[IRQ_STATUS_A] |= 0x01;
	158	state->m_ioc_regs[IRQ_STATUS_A] |= 0x01;
159	159	state->m_mk5_2KHz_timer->adjust(attotime::never);
160	160
161	161	}
r18034	r18035
183	183
184	184	// reset 2KHz timer
185	185	m_mk5_2KHz_timer->adjust(attotime::from_hz(1953.125));
186		ioc_regs[IRQ_STATUS_A] &= ~0x01;
	186	m_ioc_regs[IRQ_STATUS_A] &= ~0x01;
187	187	machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, CLEAR_LINE);
188	188	return 0xffffffff;
189	189	}
r18034	r18035
202	202	int vert_pos;
203	203
204	204	vert_pos = machine().primary_screen->vpos();
205		m_flyback = (vert_pos <= vidc_regs[VIDC_VDSR] || vert_pos >= vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
	205	m_flyback = (vert_pos <= m_vidc_regs[VIDC_VDSR] || vert_pos >= m_vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
206	206
207	207	//i2c_data = (i2cmem_sda_read(machine().device("i2cmem")) & 1);
208	208
209		return (m_flyback) | (ioc_regs[CONTROL] & 0x7c) | (1<<1) | 1;
	209	return (m_flyback) | (m_ioc_regs[CONTROL] & 0x7c) | (1<<1) | 1;
210	210	}
211	211
212	212	return archimedes_ioc_r(space,offset,mem_mask);
r18034	r18035
224	224	{
225	225	if(((ioc_addr == 0x20) || (ioc_addr == 0x30)) && (offset & 0x1f) == 0)
226	226	{
227		ioc_regs[CONTROL] = data & 0x7c;
	227	m_ioc_regs[CONTROL] = data & 0x7c;
228	228	return;
229	229	}
230	230	else
r18034	r18035
298	298
299	299	/* U.S games have no dram emulator enabled */
300	300	static ADDRESS_MAP_START( aristmk5_map, AS_PROGRAM, 32, aristmk5_state )
301		AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
	301	AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE(archimedes_memc_logical_r, archimedes_memc_logical_w)
302	302	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
303	303
304	304	/* MK-5 overrides */
r18034	r18035
317	317
318	318	AM_RANGE(0x03000000, 0x0331ffff) AM_READWRITE(mk5_ioc_r, mk5_ioc_w)
319	319	AM_RANGE(0x03320000, 0x0333ffff) AM_RAMBANK("sram_bank_nz") // AM_BASE_SIZE_GENERIC(nvram) // nvram 32kbytes x 3 NZ
320		AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE_LEGACY(archimedes_vidc_w)
321		AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)
322		AM_RANGE(0x03800000, 0x039fffff) AM_WRITE_LEGACY(archimedes_memc_page_w)
	320	AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE(archimedes_vidc_w)
	321	AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE(archimedes_memc_r, archimedes_memc_w)
	322	AM_RANGE(0x03800000, 0x039fffff) AM_WRITE(archimedes_memc_page_w)
323	323	ADDRESS_MAP_END
324	324
325	325	/* with dram emulator enabled */
326	326	static ADDRESS_MAP_START( aristmk5_drame_map, AS_PROGRAM, 32, aristmk5_state )
327		AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(aristmk5_drame_memc_logical_r, archimedes_memc_logical_w)
	327	AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE(aristmk5_drame_memc_logical_r, archimedes_memc_logical_w)
328	328	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
329	329
330	330	/* MK-5 overrides */
r18034	r18035
344	344
345	345	AM_RANGE(0x03000000, 0x0331ffff) AM_READWRITE(mk5_ioc_r, mk5_ioc_w)
346	346	AM_RANGE(0x03320000, 0x0333ffff) AM_RAMBANK("sram_bank_nz") // AM_BASE_SIZE_GENERIC(nvram) // nvram 32kbytes x 3 NZ
347		AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE_LEGACY(archimedes_vidc_w)
348		AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)
349		AM_RANGE(0x03800000, 0x039fffff) AM_WRITE_LEGACY(archimedes_memc_page_w)
	347	AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE(archimedes_vidc_w)
	348	AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE(archimedes_memc_r, archimedes_memc_w)
	349	AM_RANGE(0x03800000, 0x039fffff) AM_WRITE(archimedes_memc_page_w)
350	350	ADDRESS_MAP_END
351	351
352	352
r18034	r18035
365	365	UINT8 *SRAM    = machine().root_device().memregion("sram")->base();
366	366	UINT8 *SRAM_NZ = machine().root_device().memregion("sram")->base();
367	367
368		archimedes_driver_init(machine());
	368	archimedes_driver_init();
369	369
370	370	machine().root_device().membank("sram_bank")->configure_entries(0, 4,    &SRAM[0],    0x20000);
371	371	machine().root_device().membank("sram_bank_nz")->configure_entries(0, 4, &SRAM_NZ[0], 0x20000);
r18034	r18035
374	374
375	375	void aristmk5_state::machine_start()
376	376	{
377		archimedes_init(machine());
	377	archimedes_init();
378	378
379	379	// reset the DAC to centerline
380	380	//machine().device<dac_device>("dac")->write_signed8(0x80);
r18034	r18035
385	385
386	386	void aristmk5_state::machine_reset()
387	387	{
388		archimedes_reset(machine());
	388	archimedes_reset();
389	389	m_mk5_2KHz_timer->adjust(attotime::from_hz(1953.125)); // 8MHz / 4096
390	390	m_mk5_VSYNC_timer->adjust(attotime::from_hz(50000)); // default bit 1 & bit 2 == 0
391	391
392		ioc_regs[IRQ_STATUS_B] |= 0x40; //hack, set keyboard irq empty to be ON
	392	m_ioc_regs[IRQ_STATUS_B] |= 0x40; //hack, set keyboard irq empty to be ON
393	393
394	394	/* load the roms according to what the operator wants */
395	395	{
r18034	r18035
435	435
436	436	MCFG_PALETTE_LENGTH(0x200)
437	437
438		MCFG_SCREEN_UPDATE_STATIC(archimds_vidc)
	438	MCFG_SCREEN_UPDATE_DRIVER(archimedes_state, screen_update)
439	439
440	440	MCFG_SPEAKER_STANDARD_MONO("mono")
441	441	MCFG_DAC_ADD("dac0")
r18034	r18035
478	478
479	479	MCFG_PALETTE_LENGTH(0x200)
480	480
481		MCFG_VIDEO_START(archimds_vidc)
482		MCFG_SCREEN_UPDATE_STATIC(archimds_vidc)
	481	MCFG_SCREEN_UPDATE_DRIVER(archimedes_state, screen_update)
483	482
484	483	MCFG_SPEAKER_STANDARD_MONO("mono")
485	484	MCFG_DAC_ADD("dac0")

trunk/src/mess/drivers/a310.c

r18034	r18035
65	65	#include "machine/ram.h"
66	66
67	67
68		class a310_state : public driver_device
	68	class a310_state : public archimedes_state
69	69	{
70	70	public:
71	71	a310_state(const machine_config &mconfig, device_type type, const char *tag)
72		: driver_device(mconfig, type, tag),
	72	: archimedes_state(mconfig, type, tag),
73	73	m_physram(*this, "physicalram") { }
74	74
75	75	required_shared_ptr<UINT32> m_physram;
76	76
77	77	DECLARE_READ32_MEMBER(a310_psy_wram_r);
78	78	DECLARE_WRITE32_MEMBER(a310_psy_wram_w);
	79	DECLARE_WRITE_LINE_MEMBER(a310_wd177x_intrq_w);
	80	DECLARE_WRITE_LINE_MEMBER(a310_wd177x_drq_w);
79	81	DECLARE_DRIVER_INIT(a310);
80	82	virtual void machine_start();
81	83	virtual void machine_reset();
82	84	};
83	85
84	86
85		static WRITE_LINE_DEVICE_HANDLER( a310_wd177x_intrq_w )
	87	WRITE_LINE_MEMBER(a310_state::a310_wd177x_intrq_w)
86	88	{
87	89	if (state)
88		archimedes_request_fiq(device->machine(), ARCHIMEDES_FIQ_FLOPPY);
	90	archimedes_request_fiq(ARCHIMEDES_FIQ_FLOPPY);
89	91	else
90		archimedes_clear_fiq(device->machine(), ARCHIMEDES_FIQ_FLOPPY);
	92	archimedes_clear_fiq(ARCHIMEDES_FIQ_FLOPPY);
91	93	}
92	94
93		static WRITE_LINE_DEVICE_HANDLER( a310_wd177x_drq_w )
	95	WRITE_LINE_MEMBER(a310_state::a310_wd177x_drq_w)
94	96	{
95	97	if (state)
96		archimedes_request_fiq(device->machine(), ARCHIMEDES_FIQ_FLOPPY_DRQ);
	98	archimedes_request_fiq(ARCHIMEDES_FIQ_FLOPPY_DRQ);
97	99	else
98		archimedes_clear_fiq(device->machine(), ARCHIMEDES_FIQ_FLOPPY_DRQ);
	100	archimedes_clear_fiq(ARCHIMEDES_FIQ_FLOPPY_DRQ);
99	101	}
100	102
101	103	READ32_MEMBER(a310_state::a310_psy_wram_r)
r18034	r18035
115	117
116	118	machine().device("maincpu")->memory().space(AS_PROGRAM).install_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), read32_delegate(FUNC(a310_state::a310_psy_wram_r), this), write32_delegate(FUNC(a310_state::a310_psy_wram_w), this));
117	119
118		archimedes_driver_init(machine());
	120	archimedes_driver_init();
119	121	}
120	122
121	123	void a310_state::machine_start()
122	124	{
123		archimedes_init(machine());
	125	archimedes_init();
124	126
125	127	// reset the DAC to centerline
126	128	//machine().device<dac_device>("dac")->write_signed8(0x80);
r18034	r18035
128	130
129	131	void a310_state::machine_reset()
130	132	{
131		archimedes_reset(machine());
	133	archimedes_reset();
132	134	}
133	135
134	136	static ADDRESS_MAP_START( a310_mem, AS_PROGRAM, 32, a310_state )
135		AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
	137	AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE(archimedes_memc_logical_r, archimedes_memc_logical_w)
136	138	AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
137		AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE_LEGACY(archimedes_ioc_r, archimedes_ioc_w)
138		AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE_LEGACY(archimedes_vidc_r, archimedes_vidc_w)
139		AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)
140		AM_RANGE(0x03800000, 0x03ffffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE_LEGACY(archimedes_memc_page_w)
	139	AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE(archimedes_ioc_r, archimedes_ioc_w)
	140	AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE(archimedes_vidc_r, archimedes_vidc_w)
	141	AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE(archimedes_memc_r, archimedes_memc_w)
	142	AM_RANGE(0x03800000, 0x03ffffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE(archimedes_memc_page_w)
141	143	ADDRESS_MAP_END
142	144
143	145
r18034	r18035
255	257	static const wd17xx_interface a310_wd17xx_interface =
256	258	{
257	259	DEVCB_NULL,
258		DEVCB_LINE(a310_wd177x_intrq_w),
259		DEVCB_LINE(a310_wd177x_drq_w),
	260	DEVCB_DRIVER_LINE_MEMBER(a310_state, a310_wd177x_intrq_w),
	261	DEVCB_DRIVER_LINE_MEMBER(a310_state, a310_wd177x_drq_w),
260	262	{FLOPPY_0, FLOPPY_1, FLOPPY_2, FLOPPY_3}
261	263	};
262	264
r18034	r18035
279	281	MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
280	282	MCFG_SCREEN_SIZE(1280, 1024) //TODO: default screen size
281	283	MCFG_SCREEN_VISIBLE_AREA(0*8, 1280 - 1, 0*16, 1024 - 1)
282		MCFG_SCREEN_UPDATE_STATIC(archimds_vidc)
	284	MCFG_SCREEN_UPDATE_DRIVER(archimedes_state, screen_update)
283	285
284	286	MCFG_PALETTE_LENGTH(32768)
285	287
286		MCFG_VIDEO_START(archimds_vidc)
287
288	288	MCFG_RAM_ADD(RAM_TAG)
289	289	MCFG_RAM_DEFAULT_SIZE("2M")
290	290	MCFG_RAM_EXTRA_OPTIONS("512K, 1M, 4M, 8M, 16M")

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