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r18019 Wednesday 19th September, 2012 at 13:56:56 UTC by Curt Coder
(MESS) p500: Rewrote the driver using the PLAs for address decoding. [Curt Coder]
[hash]cbm700_cart.xml
[src/emu/machine]6525tpi.c 6525tpi.h pla.c pla.h
[src/mess]mess.mak
[src/mess/drivers]cbm2.c* cbmb.c
[src/mess/includes]cbm2.h*
[src/mess/machine]cbm2_std.c* cbm2_std.h* cbm2exp.c* cbm2exp.h* cbmipt.c cbmipt.h

trunk/hash/cbm700_cart.xml
r18018r18019
99      <description>Calc Result</description>
1010      <year>198?</year>
1111      <publisher>Handic Software</publisher>
12      <part name="cart" interface="cbm700_cart">
13         <dataarea name="rom" size="0x2000">
12     
13      <part name="cart" interface="cbm2_cart">
14         <dataarea name="bank1" size="0x2000">
1415            <rom name="calc_result-bx700.bin" size="0x2000" crc="4775ebb3" sha1="5c6928a9cd8a3ce6a1d11221292b832295d6543e" offset="0x0000" />
1516         </dataarea>
1617      </part>
18
1719      <part name="flop" interface="floppy_5_25">
1820         <dataarea name="flop" size="1070662">
1921            <rom name="calc_result_700_bx_single_version_v1.0.d82" size="1070662" crc="244a2122" sha1="44661ed8e3307bb967f97ce1f5a247ca3cded0b3" offset="0" />
trunk/src/emu/machine/pla.c
r18018r18019
6464//  get_product -
6565//-------------------------------------------------
6666
67inline int pla_device::get_product(int term)
67inline bool pla_device::get_product(int term)
6868{
6969   UINT32 input_true = m_and_true[term] | m_i;
7070   UINT32 input_comp = m_and_comp[term] | ~m_i;
trunk/src/emu/machine/pla.h
r18018r18019
7272    virtual void device_start();
7373
7474   inline void parse_fusemap();
75   inline int get_product(int term);
75   inline bool get_product(int term);
7676   inline void update_outputs();
7777
7878    int m_inputs;
trunk/src/emu/machine/6525tpi.c
r18018r18019
318318   }
319319}
320320
321WRITE_LINE_MEMBER( tpi6525_device::i0_w ) { tpi6525_i0_w(this, state); }
322WRITE_LINE_MEMBER( tpi6525_device::i1_w ) { tpi6525_i1_w(this, state); }
323WRITE_LINE_MEMBER( tpi6525_device::i2_w ) { tpi6525_i2_w(this, state); }
324WRITE_LINE_MEMBER( tpi6525_device::i3_w ) { tpi6525_i3_w(this, state); }
325WRITE_LINE_MEMBER( tpi6525_device::i4_w ) { tpi6525_i4_w(this, state); }
321326
327
322328READ8_DEVICE_HANDLER( tpi6525_porta_r )
323329{
324330   tpi6525_state *tpi6525 = get_safe_token(device);
r18018r18019
500506   return data;
501507}
502508
509READ8_MEMBER( tpi6525_device::read )
510{
511   return tpi6525_r(this, space, offset);
512}
503513
514
504515WRITE8_DEVICE_HANDLER( tpi6525_w )
505516{
506517   tpi6525_state *tpi6525 = get_safe_token(device);
r18018r18019
574585   }
575586}
576587
588WRITE8_MEMBER( tpi6525_device::write )
589{
590   tpi6525_w(this, space, offset, data);
591}
577592
593
578594/* this should probably be done better, needed for amigacd.c */
579595
580596UINT8 tpi6525_get_ddr_a(device_t *device)
trunk/src/emu/machine/6525tpi.h
r18018r18019
6464
6565   // access to legacy token
6666   void *token() const { assert(m_token != NULL); return m_token; }
67
68   DECLARE_READ8_MEMBER( read );
69   DECLARE_WRITE8_MEMBER( write );
70
71   DECLARE_WRITE_LINE_MEMBER( i0_w );
72   DECLARE_WRITE_LINE_MEMBER( i1_w );
73   DECLARE_WRITE_LINE_MEMBER( i2_w );
74   DECLARE_WRITE_LINE_MEMBER( i3_w );
75   DECLARE_WRITE_LINE_MEMBER( i4_w );
76
6777protected:
6878   // device-level overrides
6979   virtual void device_config_complete();
trunk/src/mess/machine/cbmipt.c
r18018r18019
10431043INPUT_PORTS_END
10441044
10451045
1046SLOT_INTERFACE_START( cbm2_expansion_cards )
1047   SLOT_INTERFACE_INTERNAL("standard", CBM2_STD)
1048SLOT_INTERFACE_END
1049
10461050SLOT_INTERFACE_START( cbm_datassette_devices )
10471051   SLOT_INTERFACE("c1530", C1530)
10481052SLOT_INTERFACE_END
trunk/src/mess/machine/cbmipt.h
r18018r18019
6060#include "machine/c64_xl80.h"
6161#include "machine/c64_zaxxon.h"
6262#include "machine/c128_comal80.h"
63#include "machine/cbm2_std.h"
6364#include "machine/c1541.h"
6465#include "machine/c1551.h"
6566#include "machine/c1571.h"
r18018r18019
149150
150151
151152
153SLOT_INTERFACE_EXTERN( cbm2_expansion_cards );
152154SLOT_INTERFACE_EXTERN( cbm_datassette_devices );
153155SLOT_INTERFACE_EXTERN( cbm_iec_devices );
154156SLOT_INTERFACE_EXTERN( sx1541_iec_devices );
trunk/src/mess/machine/cbm2_std.c
r0r18019
1/**********************************************************************
2
3    Commodore CBM-II Standard cartridge emulation
4
5    Copyright MESS Team.
6    Visit http://mamedev.org for licensing and usage restrictions.
7
8**********************************************************************/
9
10#include "cbm2_std.h"
11
12
13
14//**************************************************************************
15//  DEVICE DEFINITIONS
16//**************************************************************************
17
18const device_type CBM2_STD = &device_creator<cbm2_standard_cartridge_device>;
19
20
21
22//**************************************************************************
23//  LIVE DEVICE
24//**************************************************************************
25
26//-------------------------------------------------
27//  cbm2_standard_cartridge_device - constructor
28//-------------------------------------------------
29
30cbm2_standard_cartridge_device::cbm2_standard_cartridge_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
31   device_t(mconfig, CBM2_STD, "CBM-II standard cartridge", tag, owner, clock),
32   device_cbm2_expansion_card_interface(mconfig, *this)
33{
34}
35
36
37//-------------------------------------------------
38//  device_start - device-specific startup
39//-------------------------------------------------
40
41void cbm2_standard_cartridge_device::device_start()
42{
43}
44
45
46//-------------------------------------------------
47//  cbm2_bd_r - cartridge data read
48//-------------------------------------------------
49
50UINT8 cbm2_standard_cartridge_device::cbm2_bd_r(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3)
51{
52   if (!csbank1 && m_bank1_mask)
53   {
54      data = m_bank1[offset & m_bank1_mask];
55   }
56   else if (!csbank2 && m_bank2_mask)
57   {
58      data = m_bank2[offset & m_bank2_mask];
59   }
60   else if (!csbank3 && m_bank3_mask)
61   {
62      data = m_bank3[offset & m_bank3_mask];
63   }
64
65   return data;
66}
trunk/src/mess/machine/cbm2_std.h
r0r18019
1/**********************************************************************
2
3    Commodore CBM-II Standard cartridge emulation
4
5    Copyright MESS Team.
6    Visit http://mamedev.org for licensing and usage restrictions.
7
8**********************************************************************/
9
10#pragma once
11
12#ifndef __CBM2_STANDARD_CARTRIDGE__
13#define __CBM2_STANDARD_CARTRIDGE__
14
15
16#include "emu.h"
17#include "imagedev/cartslot.h"
18#include "machine/cbm2exp.h"
19
20
21
22//**************************************************************************
23//  TYPE DEFINITIONS
24//**************************************************************************
25
26// ======================> cbm2_standard_cartridge_device
27
28class cbm2_standard_cartridge_device : public device_t,
29                              public device_cbm2_expansion_card_interface
30{
31public:
32   // construction/destruction
33   cbm2_standard_cartridge_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
34
35protected:
36   // device-level overrides
37   virtual void device_config_complete() { m_shortname = "cbm2_standard"; }
38   virtual void device_start();
39
40   // device_cbm2_expansion_card_interface overrides
41   virtual UINT8 cbm2_bd_r(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3);
42};
43
44
45// device type definition
46extern const device_type CBM2_STD;
47
48
49#endif
trunk/src/mess/machine/cbm2exp.c
r0r18019
1/**********************************************************************
2
3    Commodore CBM-II Expansion Port emulation
4
5    Copyright MESS Team.
6    Visit http://mamedev.org for licensing and usage restrictions.
7
8**********************************************************************/
9
10#include "machine/cbm2exp.h"
11
12
13
14//**************************************************************************
15//  MACROS/CONSTANTS
16//**************************************************************************
17
18#define LOG 0
19
20
21
22//**************************************************************************
23//  DEVICE DEFINITIONS
24//**************************************************************************
25
26const device_type CBM2_EXPANSION_SLOT = &device_creator<cbm2_expansion_slot_device>;
27
28
29
30//**************************************************************************
31//  DEVICE CBM2_EXPANSION CARD INTERFACE
32//**************************************************************************
33
34//-------------------------------------------------
35//  device_cbm2_expansion_card_interface - constructor
36//-------------------------------------------------
37
38device_cbm2_expansion_card_interface::device_cbm2_expansion_card_interface(const machine_config &mconfig, device_t &device)
39   : device_slot_card_interface(mconfig, device),
40     m_bank1(NULL),
41     m_bank2(NULL),
42     m_bank3(NULL),
43     m_ram(NULL),
44     m_nvram(NULL),
45     m_nvram_size(0),
46     m_bank1_mask(0),
47     m_bank2_mask(0),
48     m_bank3_mask(0),
49     m_ram_mask(0)
50{
51   m_slot = dynamic_cast<cbm2_expansion_slot_device *>(device.owner());
52}
53
54
55//-------------------------------------------------
56//  ~device_cbm2_expansion_card_interface - destructor
57//-------------------------------------------------
58
59device_cbm2_expansion_card_interface::~device_cbm2_expansion_card_interface()
60{
61}
62
63
64//-------------------------------------------------
65//  cbm2_bank1_pointer - get bank 1 pointer
66//-------------------------------------------------
67
68UINT8* device_cbm2_expansion_card_interface::cbm2_bank1_pointer(running_machine &machine, size_t size)
69{
70   if (m_bank1 == NULL)
71   {
72      m_bank1 = auto_alloc_array(machine, UINT8, size);
73
74      m_bank1_mask = size - 1;
75   }
76
77   return m_bank1;
78}
79
80
81//-------------------------------------------------
82//  cbm2_bank2_pointer - get bank 2 pointer
83//-------------------------------------------------
84
85UINT8* device_cbm2_expansion_card_interface::cbm2_bank2_pointer(running_machine &machine, size_t size)
86{
87   if (m_bank2 == NULL)
88   {
89      m_bank2 = auto_alloc_array(machine, UINT8, size);
90
91      m_bank2_mask = size - 1;
92   }
93
94   return m_bank2;
95}
96
97
98//-------------------------------------------------
99//  cbm2_bank3_pointer - get bank 3 pointer
100//-------------------------------------------------
101
102UINT8* device_cbm2_expansion_card_interface::cbm2_bank3_pointer(running_machine &machine, size_t size)
103{
104   if (m_bank3 == NULL)
105   {
106      m_bank3 = auto_alloc_array(machine, UINT8, size);
107
108      m_bank3_mask = size - 1;
109   }
110
111   return m_bank1;
112}
113
114
115//-------------------------------------------------
116//  cbm2_ram_pointer - get RAM pointer
117//-------------------------------------------------
118
119UINT8* device_cbm2_expansion_card_interface::cbm2_ram_pointer(running_machine &machine, size_t size)
120{
121   if (m_ram == NULL)
122   {
123      m_ram = auto_alloc_array(machine, UINT8, size);
124
125      m_ram_mask = size - 1;
126   }
127
128   return m_ram;
129}
130
131
132//-------------------------------------------------
133//  cbm2_ram_pointer - get NVRAM pointer
134//-------------------------------------------------
135
136UINT8* device_cbm2_expansion_card_interface::cbm2_nvram_pointer(running_machine &machine, size_t size)
137{
138   if (m_nvram == NULL)
139   {
140      m_nvram = auto_alloc_array(machine, UINT8, size);
141
142      m_nvram_mask = size - 1;
143      m_nvram_size = size;
144   }
145
146   return m_nvram;
147}
148
149
150
151//**************************************************************************
152//  LIVE DEVICE
153//**************************************************************************
154
155//-------------------------------------------------
156//  cbm2_expansion_slot_device - constructor
157//-------------------------------------------------
158
159cbm2_expansion_slot_device::cbm2_expansion_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
160        device_t(mconfig, CBM2_EXPANSION_SLOT, "PET-II expansion port", tag, owner, clock),
161      device_slot_interface(mconfig, *this),
162      device_image_interface(mconfig, *this)
163{
164}
165
166
167//-------------------------------------------------
168//  cbm2_expansion_slot_device - destructor
169//-------------------------------------------------
170
171cbm2_expansion_slot_device::~cbm2_expansion_slot_device()
172{
173}
174
175
176//-------------------------------------------------
177//  device_config_complete - perform any
178//  operations now that the configuration is
179//  complete
180//-------------------------------------------------
181
182void cbm2_expansion_slot_device::device_config_complete()
183{
184   // set brief and instance name
185   update_names();
186}
187
188
189//-------------------------------------------------
190//  device_start - device-specific startup
191//-------------------------------------------------
192
193void cbm2_expansion_slot_device::device_start()
194{
195   m_cart = dynamic_cast<device_cbm2_expansion_card_interface *>(get_card_device());
196
197   // inherit bus clock
198   if (clock() == 0)
199   {
200      cbm2_expansion_slot_device *root = machine().device<cbm2_expansion_slot_device>(CBM2_EXPANSION_SLOT_TAG);
201      assert(root);
202      set_unscaled_clock(root->clock());
203   }
204}
205
206
207//-------------------------------------------------
208//  device_reset - device-specific reset
209//-------------------------------------------------
210
211void cbm2_expansion_slot_device::device_reset()
212{
213}
214
215
216//-------------------------------------------------
217//  call_load -
218//-------------------------------------------------
219
220bool cbm2_expansion_slot_device::call_load()
221{
222   size_t size = 0;
223
224   if (m_cart)
225   {
226      if (software_entry() == NULL)
227      {
228         size = length();
229
230         if (!mame_stricmp(filetype(), "20"))
231         {
232            fread(m_cart->cbm2_bank1_pointer(machine(), size), size);
233         }
234         else if (!mame_stricmp(filetype(), "40"))
235         {
236            fread(m_cart->cbm2_bank2_pointer(machine(), size), size);
237         }
238         else if (!mame_stricmp(filetype(), "60"))
239         {
240            fread(m_cart->cbm2_bank3_pointer(machine(), size), size);
241         }
242      }
243      else
244      {
245         size = get_software_region_length("bank1");
246         if (size) memcpy(m_cart->cbm2_bank1_pointer(machine(), size), get_software_region("bank1"), size);
247
248         size = get_software_region_length("bank2");
249         if (size) memcpy(m_cart->cbm2_bank2_pointer(machine(), size), get_software_region("bank2"), size);
250
251         size = get_software_region_length("bank3");
252         if (size) memcpy(m_cart->cbm2_bank3_pointer(machine(), size), get_software_region("bank3"), size);
253
254         size = get_software_region_length("ram");
255         if (size) memset(m_cart->cbm2_ram_pointer(machine(), size), 0, size);
256
257         size = get_software_region_length("nvram");
258         if (size) memset(m_cart->cbm2_nvram_pointer(machine(), size), 0, size);
259      }
260   }
261
262   return IMAGE_INIT_PASS;
263}
264
265
266//-------------------------------------------------
267//  call_softlist_load -
268//-------------------------------------------------
269
270bool cbm2_expansion_slot_device::call_softlist_load(char *swlist, char *swname, rom_entry *start_entry)
271{
272   load_software_part_region(this, swlist, swname, start_entry);
273
274   return true;
275}
276
277
278//-------------------------------------------------
279//  get_default_card_software -
280//-------------------------------------------------
281
282const char * cbm2_expansion_slot_device::get_default_card_software(const machine_config &config, emu_options &options)
283{
284   return software_get_default_slot(config, options, this, "standard");
285}
286
287
288//-------------------------------------------------
289//  read - cartridge data read
290//-------------------------------------------------
291
292UINT8 cbm2_expansion_slot_device::read(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3)
293{
294   if (m_cart != NULL)
295   {
296      data = m_cart->cbm2_bd_r(space, offset, data, csbank1, csbank2, csbank3);
297   }
298
299   return data;
300}
301
302
303//-------------------------------------------------
304//  write - cartridge data write
305//-------------------------------------------------
306
307void cbm2_expansion_slot_device::write(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3)
308{
309   if (m_cart != NULL)
310   {
311      m_cart->cbm2_bd_w(space, offset, data, csbank1, csbank2, csbank3);
312   }
313}
314
315
316//-------------------------------------------------
317//  phi2 - system clock frequency
318//-------------------------------------------------
319
320int cbm2_expansion_slot_device::phi2()
321{
322   return clock();
323}
trunk/src/mess/machine/cbm2exp.h
r0r18019
1/**********************************************************************
2
3    Commodore CBM-II Expansion Port emulation
4
5    Copyright MESS Team.
6    Visit http://mamedev.org for licensing and usage restrictions.
7
8**********************************************************************
9
10                     A0       1      A       BD0
11                     A1       2      B       BD1
12                     A2       3      C       BD2
13                     A3       4      D       BD3
14                     A4       5      E       BD4
15                     A5       6      F       BD5
16                     A6       7      H       BD6
17                     A7       8      J       BD7
18                     A8       9      K       GND
19                     A9      10      L       GND
20                    A10      11      M       SR/_W
21                    A11      12      N       Sphi2
22                    A12      13      P       _CSBANK1
23                    +5V      14      R       _CSBANK2
24                    +5V      15      S       _CSBANK2
25
26**********************************************************************/
27
28#pragma once
29
30#ifndef __CBM2_EXPANSION_SLOT__
31#define __CBM2_EXPANSION_SLOT__
32
33#include "emu.h"
34
35
36
37//**************************************************************************
38//  CONSTANTS
39//**************************************************************************
40
41#define CBM2_EXPANSION_SLOT_TAG      "exp"
42
43
44
45//**************************************************************************
46//  INTERFACE CONFIGURATION MACROS
47//**************************************************************************
48
49#define CBM2_EXPANSION_INTERFACE(_name) \
50   const pet_expansion_slot_interface (_name) =
51
52
53#define MCFG_CBM2_EXPANSION_SLOT_ADD(_tag, _clock, _slot_intf, _def_slot, _def_inp) \
54    MCFG_DEVICE_ADD(_tag, CBM2_EXPANSION_SLOT, _clock) \
55   MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, _def_inp, false)
56
57
58
59//**************************************************************************
60//  TYPE DEFINITIONS
61//**************************************************************************
62
63// ======================> cbm2_expansion_slot_device
64
65class device_cbm2_expansion_card_interface;
66
67class cbm2_expansion_slot_device : public device_t,
68                           public device_slot_interface,
69                           public device_image_interface
70{
71public:
72   // construction/destruction
73   cbm2_expansion_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
74   virtual ~cbm2_expansion_slot_device();
75
76   // computer interface
77   UINT8 read(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3);
78   void write(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3);
79
80   // cartridge interface
81   int phi2();
82
83protected:
84   // device-level overrides
85   virtual void device_config_complete();
86   virtual void device_start();
87   virtual void device_reset();
88
89   // image-level overrides
90   virtual bool call_load();
91   virtual bool call_softlist_load(char *swlist, char *swname, rom_entry *start_entry);
92
93   virtual iodevice_t image_type() const { return IO_CARTSLOT; }
94
95   virtual bool is_readable()  const { return 1; }
96   virtual bool is_writeable() const { return 0; }
97   virtual bool is_creatable() const { return 0; }
98   virtual bool must_be_loaded() const { return 0; }
99   virtual bool is_reset_on_load() const { return 1; }
100   virtual const char *image_interface() const { return "cbm2_cart"; }
101   virtual const char *file_extensions() const { return "20,40,60"; }
102   virtual const option_guide *create_option_guide() const { return NULL; }
103
104   // slot interface overrides
105   virtual const char * get_default_card_software(const machine_config &config, emu_options &options);
106
107   device_cbm2_expansion_card_interface *m_cart;
108};
109
110
111// ======================> device_cbm2_expansion_card_interface
112
113class device_cbm2_expansion_card_interface : public device_slot_card_interface
114{
115   friend class cbm2_expansion_slot_device;
116
117public:
118   // construction/destruction
119   device_cbm2_expansion_card_interface(const machine_config &mconfig, device_t &device);
120   virtual ~device_cbm2_expansion_card_interface();
121
122protected:
123   // initialization
124   virtual UINT8* cbm2_bank1_pointer(running_machine &machine, size_t size);
125   virtual UINT8* cbm2_bank2_pointer(running_machine &machine, size_t size);
126   virtual UINT8* cbm2_bank3_pointer(running_machine &machine, size_t size);
127   virtual UINT8* cbm2_ram_pointer(running_machine &machine, size_t size);
128   virtual UINT8* cbm2_nvram_pointer(running_machine &machine, size_t size);
129
130   // runtime
131   virtual UINT8 cbm2_bd_r(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3) { return data; };
132   virtual void cbm2_bd_w(address_space &space, offs_t offset, UINT8 data, int csbank1, int csbank2, int csbank3) { };
133
134   cbm2_expansion_slot_device *m_slot;
135
136   UINT8 *m_bank1;
137   UINT8 *m_bank2;
138   UINT8 *m_bank3;
139   UINT8 *m_ram;
140   UINT8 *m_nvram;
141
142   size_t m_nvram_size;
143
144   size_t m_bank1_mask;
145   size_t m_bank2_mask;
146   size_t m_bank3_mask;
147   size_t m_ram_mask;
148   size_t m_nvram_mask;
149};
150
151
152// device type definition
153extern const device_type CBM2_EXPANSION_SLOT;
154
155
156
157#endif
trunk/src/mess/includes/cbm2.h
r0r18019
1#pragma once
2
3#ifndef __P500__
4#define __P500__
5
6#include "emu.h"
7#include "cpu/m6502/m6509.h"
8#include "formats/cbm_snqk.h"
9#include "includes/cbm.h"
10#include "machine/6525tpi.h"
11#include "machine/6526cia.h"
12#include "machine/6551acia.h"
13#include "machine/cbm2exp.h"
14#include "machine/cbmipt.h"
15#include "machine/ieee488.h"
16#include "machine/petcass.h"
17#include "machine/pla.h"
18#include "machine/ram.h"
19#include "machine/vcsctrl.h"
20#include "sound/dac.h"
21#include "sound/sid6581.h"
22#include "video/mos6566.h"
23
24#define M6509_TAG      "u13"
25#define PLA1_TAG      "u78"
26#define PLA2_TAG      "u88"
27#define MOS6567_TAG      "u23"
28#define MOS6569_TAG      "u23"
29#define MOS6851_TAG      "u4"
30#define MOS6525_1_TAG   "u20"
31#define MOS6525_2_TAG   "u102"
32#define MOS6551A_TAG   "u19"
33#define MOS6526_TAG      "u2"
34#define SCREEN_TAG      "screen"
35#define CONTROL1_TAG   "joy1"
36#define CONTROL2_TAG   "joy2"
37
38class p500_state : public driver_device
39{
40public:
41   p500_state(const machine_config &mconfig, device_type type, const char *tag)
42      : driver_device(mconfig, type, tag),
43        m_maincpu(*this, M6509_TAG),
44        m_pla1(*this, PLA1_TAG),
45        m_pla2(*this, PLA2_TAG),
46        m_vic(*this, MOS6569_TAG),
47        m_sid(*this, MOS6851_TAG),
48        m_tpi1(*this, MOS6525_1_TAG),
49        m_tpi2(*this, MOS6525_2_TAG),
50        m_acia(*this, MOS6551A_TAG),
51        m_cia(*this, MOS6526_TAG),
52        m_joy1(*this, CONTROL1_TAG),
53        m_joy2(*this, CONTROL2_TAG),
54        m_exp(*this, CBM2_EXPANSION_SLOT_TAG),
55        m_ram(*this, RAM_TAG),
56        m_cassette(*this, PET_DATASSETTE_PORT_TAG),
57        m_ieee(*this, IEEE488_TAG),
58        m_buffer_ram(*this, "buffer_ram"),
59        m_dramon(1),
60        m_video_ram(*this, "video_ram"),
61        m_color_ram(*this, "color_ram"),
62        m_statvid(1),
63        m_vicdotsel(1),
64        m_vicbnksel(0x03),
65        m_todclk(0),
66        m_vic_irq(CLEAR_LINE),
67        m_tpi1_irq(CLEAR_LINE),
68        m_cass_rd(1),
69        m_user_flag(0),
70        m_tpi2_pa(0),
71        m_tpi2_pb(0)
72   { }
73
74   required_device<cpu_device> m_maincpu;
75   required_device<pls100_device> m_pla1;
76   required_device<pls100_device> m_pla2;
77   required_device<mos6566_device> m_vic;
78   required_device<sid6581_device> m_sid;
79   required_device<tpi6525_device> m_tpi1;
80   required_device<tpi6525_device> m_tpi2;
81   required_device<acia6551_device> m_acia;
82   required_device<mos6526_device> m_cia;
83   required_device<vcs_control_port_device> m_joy1;
84   required_device<vcs_control_port_device> m_joy2;
85   required_device<cbm2_expansion_slot_device> m_exp;
86   required_device<ram_device> m_ram;
87   required_device<pet_datassette_port_device> m_cassette;
88   required_device<ieee488_device> m_ieee;
89
90   virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
91
92   virtual void machine_start();
93   virtual void machine_reset();
94
95   void check_interrupts();
96   void bankswitch(offs_t offset, offs_t va, int srw, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas, int busy2, int refen,
97      int *datxen, int *dramxen, int *clrniben, int *_64kcasen, int *casenb, int *viddaten, int *viddat_tr,
98      int *clrnibcs, int *extbufcs, int *discromcs, int *buframcs, int *charomcs, int *viccs, int *vidmatcs,
99      int *csbank1, int *csbank2, int *csbank3, int *basiclocs, int *basichics, int *kernalcs,
100      int *cs1, int *sidcs, int *extprtcs, int *ciacs, int *aciacs, int *tript1cs, int *tript2cs, int *aec, int *vsysaden);
101   UINT8 read_memory(address_space &space, offs_t offset, offs_t va, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas);
102   void write_memory(address_space &space, offs_t offset, UINT8 data, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas);
103
104   DECLARE_READ8_MEMBER( read );
105   DECLARE_WRITE8_MEMBER( write );
106
107   DECLARE_READ8_MEMBER( vic_videoram_r );
108   DECLARE_WRITE_LINE_MEMBER( vic_irq_w );
109
110   DECLARE_READ8_MEMBER( sid_potx_r );
111   DECLARE_READ8_MEMBER( sid_poty_r );
112
113   DECLARE_WRITE_LINE_MEMBER( tpi1_irq_w );
114   DECLARE_READ8_MEMBER( tpi1_pa_r );
115   DECLARE_WRITE8_MEMBER( tpi1_pa_w );
116   DECLARE_READ8_MEMBER( tpi1_pb_r );
117   DECLARE_WRITE8_MEMBER( tpi1_pb_w );
118   DECLARE_WRITE_LINE_MEMBER( tpi1_ca_w );
119   DECLARE_WRITE_LINE_MEMBER( tpi1_cb_w );
120
121   DECLARE_WRITE8_MEMBER( tpi2_pa_w );
122   DECLARE_WRITE8_MEMBER( tpi2_pb_w );
123   DECLARE_READ8_MEMBER( tpi2_pc_r );
124   DECLARE_WRITE8_MEMBER( tpi2_pc_w );
125
126   DECLARE_READ8_MEMBER( cia_pa_r );
127   DECLARE_WRITE8_MEMBER( cia_pa_w );
128   DECLARE_READ8_MEMBER( cia_pb_r );
129   DECLARE_WRITE8_MEMBER( cia_pb_w );
130
131   DECLARE_WRITE_LINE_MEMBER( tape_read_w );
132
133   // memory state
134   optional_shared_ptr<UINT8> m_buffer_ram;
135   UINT8 *m_basic;
136   UINT8 *m_kernal;
137   UINT8 *m_charom;
138   int m_dramon;
139
140   // video state
141   optional_shared_ptr<UINT8> m_video_ram;
142   optional_shared_ptr<UINT8> m_color_ram;
143   int m_statvid;
144   int m_vicdotsel;
145   int m_vicbnksel;
146
147   // interrupt state
148   int m_todclk;
149   int m_vic_irq;
150   int m_tpi1_irq;
151   int m_cass_rd;
152   int m_user_flag;
153
154   // keyboard state;
155   UINT8 m_tpi2_pa;
156   UINT8 m_tpi2_pb;
157   UINT8 m_cia_pa;
158
159   // timers
160   emu_timer *m_todclk_timer;
161};
162
163
164#endif
trunk/src/mess/drivers/cbmb.c
r18018r18019
146146   AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_SHARE("kernal")
147147ADDRESS_MAP_END
148148
149static ADDRESS_MAP_START(p500_mem , AS_PROGRAM, 8, cbmb_state )
150   AM_RANGE(0x00000, 0x1ffff) AM_RAM
151   AM_RANGE(0x20000, 0x2ffff) AM_READONLY AM_WRITENOP
152   AM_RANGE(0x30000, 0x7ffff) AM_RAM
153   AM_RANGE(0x80000, 0x8ffff) AM_READONLY AM_WRITENOP
154   AM_RANGE(0x90000, 0xf07ff) AM_RAM
155#if 0
156   AM_RANGE(0xf0800, 0xf0fff) AM_READ_LEGACY(SMH_ROM)
157#endif
158   AM_RANGE(0xf1000, 0xf1fff) AM_ROM   /* cartridges or ram */
159   AM_RANGE(0xf2000, 0xf3fff) AM_ROM   /* cartridges or ram */
160   AM_RANGE(0xf4000, 0xf5fff) AM_ROM
161   AM_RANGE(0xf6000, 0xf7fff) AM_ROM
162   AM_RANGE(0xf8000, 0xfbfff) AM_ROM AM_SHARE("basic")
163   AM_RANGE(0xfd000, 0xfd3ff) AM_RAM AM_SHARE("videoram")      /* videoram */
164   AM_RANGE(0xfd400, 0xfd7ff) AM_RAM_WRITE(cbmb_colorram_w) AM_SHARE("colorram")      /* colorram */
165   AM_RANGE(0xfd800, 0xfd8ff) AM_DEVREADWRITE("vic6567", mos6566_device, read, write)
166   /* disk units */
167   AM_RANGE(0xfda00, 0xfdaff) AM_DEVREADWRITE("sid6581", sid6581_device, read, write)
168   /* db00 coprocessor */
169   AM_RANGE(0xfdc00, 0xfdcff) AM_DEVREADWRITE_LEGACY("cia", mos6526_r, mos6526_w)
170   /* dd00 acia */
171   AM_RANGE(0xfde00, 0xfdeff) AM_DEVREADWRITE_LEGACY("tpi6525_0", tpi6525_r, tpi6525_w)
172   AM_RANGE(0xfdf00, 0xfdfff) AM_DEVREADWRITE_LEGACY("tpi6525_1", tpi6525_r, tpi6525_w)
173   AM_RANGE(0xfe000, 0xfffff) AM_ROM AM_SHARE("kernal")
174ADDRESS_MAP_END
175149
176
177150/*************************************
178151 *
179152 *  Input Ports
r18018r18019
311284   NULL
312285};
313286
314/* p500 uses a VIC II chip */
315
316READ8_MEMBER( cbmb_state::vic_lightpen_x_cb )
317{
318   return ioport("LIGHTX")->read() & ~0x01;
319}
320
321READ8_MEMBER( cbmb_state::vic_lightpen_y_cb )
322{
323   return ioport("LIGHTY")->read() & ~0x01;
324}
325
326READ8_MEMBER( cbmb_state::vic_lightpen_button_cb )
327{
328   return ioport("OTHER")->read() & 0x04;
329}
330
331READ8_MEMBER( cbmb_state::vic_dma_read )
332{
333   if (offset >= 0x1000)
334      return m_videoram[offset & 0x3ff];
335   else
336      return m_chargen[offset & 0xfff];
337}
338
339READ8_MEMBER( cbmb_state::vic_dma_read_color )
340{
341   return m_colorram[offset & 0x3ff];
342}
343
344READ8_MEMBER( cbmb_state::vic_rdy_cb )
345{
346   return ioport("CTRLSEL")->read() & 0x08;
347}
348
349static ADDRESS_MAP_START( vic_videoram_map, AS_0, 8, cbmb_state )
350   AM_RANGE(0x0000, 0x3fff) AM_READ(vic_dma_read)
351ADDRESS_MAP_END
352
353static ADDRESS_MAP_START( vic_colorram_map, AS_1, 8, cbmb_state )
354   AM_RANGE(0x000, 0x3ff) AM_READ(vic_dma_read_color)
355ADDRESS_MAP_END
356
357static MOS6567_INTERFACE( vic_intf )
358{
359   "screen",
360   "maincpu",
361   DEVCB_NULL,
362   DEVCB_NULL,
363   DEVCB_DRIVER_MEMBER(cbmb_state, vic_lightpen_x_cb),
364   DEVCB_DRIVER_MEMBER(cbmb_state, vic_lightpen_y_cb),
365   DEVCB_DRIVER_MEMBER(cbmb_state, vic_lightpen_button_cb),
366   DEVCB_DRIVER_MEMBER(cbmb_state, vic_rdy_cb)
367};
368
369287static const sid6581_interface sid_intf =
370288{
371289   DEVCB_NULL,
r18018r18019
494412MACHINE_CONFIG_END
495413
496414
497static MACHINE_CONFIG_START( p500, cbmb_state )
498   /* basic machine hardware */
499   MCFG_CPU_ADD("maincpu", M6509, VIC6567_CLOCK)        /* 7.8336 MHz */
500   MCFG_CPU_PROGRAM_MAP(p500_mem)
501   //MCFG_CPU_PERIODIC_INT_DRIVER(cbmb_state, vic2_raster_irq,  VIC6567_HRETRACERATE)
502
503   MCFG_MACHINE_RESET_OVERRIDE(cbmb_state, cbmb )
504
505   /* video hardware */
506   MCFG_MOS6567_ADD("vic6567", "screen", VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
507
508   /* sound hardware */
509   MCFG_SPEAKER_STANDARD_MONO("mono")
510   MCFG_SOUND_ADD("sid6581", SID6581, 1000000)
511   MCFG_SOUND_CONFIG(sid_intf)
512   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
513
514   /* devices */
515   MCFG_QUICKLOAD_ADD("quickload", p500, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
516
517   /* cia */
518   MCFG_MOS6526R1_ADD("cia", VIC6567_CLOCK, 60, cbmb_cia)
519
520   /* tpi */
521   MCFG_TPI6525_ADD("tpi6525_0", cbmb_tpi_0_intf)
522   MCFG_TPI6525_ADD("tpi6525_1", cbmb_tpi_1_intf)
523
524   /* IEEE bus */
525   MCFG_CBM_IEEE488_ADD(ieee488_intf, "c8250")
526
527   MCFG_FRAGMENT_ADD(cbmb_cartslot)
528MACHINE_CONFIG_END
529
530
531
532415/*************************************
533416 *
534417 *  ROM definition(s)
r18018r18019
678561   ROM_LOAD( "906114-05.bin", 0x00, 0xf5, CRC(ff6ba6b6) SHA1(45808c570eb2eda7091c51591b3dbd2db1ac646a) )
679562ROM_END
680563
681ROM_START( p500 )
682   ROM_REGION( 0x101000, "maincpu", 0 )
683   ROM_SYSTEM_BIOS(0, "default", "BASIC 4.0 new" )
684   ROMX_LOAD( "901236-02.bin", 0xf8000, 0x2000, CRC(c62ab16f) SHA1(f50240407bade901144f7e9f489fa9c607834eca), ROM_BIOS(1) )
685   ROMX_LOAD( "901235-02.bin", 0xfa000, 0x2000, CRC(20b7df33) SHA1(1b9a55f12f8cf025754d8029cc5324b474c35841), ROM_BIOS(1) )
686   ROMX_LOAD( "901234-02.bin", 0xfe000, 0x2000, CRC(f46bbd2b) SHA1(097197d4d08e0b82e0466a5f1fbd49a24f3d2523), ROM_BIOS(1) )
687   ROM_SYSTEM_BIOS(1, "old", "BASIC 4.0 old" )
688   ROMX_LOAD( "901236-01.bin", 0xf8000, 0x2000, CRC(33eb6aa2) SHA1(7e3497ae2edbb38c753bd31ed1bf3ae798c9a976), ROM_BIOS(2) )
689   ROMX_LOAD( "901235-01.bin", 0xfa000, 0x2000, CRC(18a27feb) SHA1(951b5370dd7db762b8504a141f9f26de345069bb), ROM_BIOS(2) )
690   ROMX_LOAD( "901234-01.bin", 0xfe000, 0x2000, CRC(67962025) SHA1(24b41b65c85bf30ab4e2911f677ce9843845b3b1), ROM_BIOS(2) )
691564
692   ROM_LOAD( "901225-01.bin", 0x100000, 0x1000, CRC(ec4272ee) SHA1(adc7c31e18c7c7413d54802ef2f4193da14711aa) )
693
694   ROM_REGION( 0xf5, "pla1", 0 )
695   ROM_LOAD( "906114-02.bin", 0x00, 0xf5, CRC(6436b20b) SHA1(57ebebe771791288051afd1abe9b7500bd2df847) )
696
697   ROM_REGION( 0xf5, "pla2", 0 )
698   ROM_LOAD( "906114-03.bin", 0x00, 0xf5, CRC(668c073e) SHA1(1115858bb2dc91ea9e2016ba2e23ec94239358b4) )
699ROM_END
700
701
702565/***************************************************************************
703566
704567  Game driver(s)
r18018r18019
720583COMP( 1983, cbm720se, cbm610, 0,      cbm700pal, cbm700, cbmb_state,    cbm700,    "Commodore Business Machines",  "CBM 720 (Sweden/Finland, 50Hz)",         GAME_NOT_WORKING )
721584
722585COMP( 1983,   bx256hp,  cbm610, 0,      bx256hp,   cbm700, cbmb_state,    cbm700,    "Commodore Business Machines",  "BX256-80HP (60Hz)",                      GAME_NOT_WORKING )
723
724COMP( 1983,   p500,     0,      0,      p500,      p500, cbmb_state,      p500,      "Commodore Business Machines",  "P500 (proto, a.k.a. B128-40 or Pet-II)", GAME_NOT_WORKING )
trunk/src/mess/drivers/cbm2.c
r0r18019
1/*
2
3    TODO:
4
5   - cbm600
6   - cbm700
7   - read VIC video RAM thru PLA
8   - read VIC color RAM thru PLA
9   - user port
10   - co-processor bus
11
12*/
13
14#include "includes/cbm2.h"
15
16
17
18//**************************************************************************
19//  MACROS / CONSTANTS
20//**************************************************************************
21
22#define P3 BIT(offset, 19)
23#define P2 BIT(offset, 18)
24#define P1 BIT(offset, 17)
25#define P0 BIT(offset, 16)
26#define A15 BIT(offset, 15)
27#define A14 BIT(offset, 14)
28#define A13 BIT(offset, 13)
29#define A12 BIT(offset, 12)
30#define A11 BIT(offset, 11)
31#define A10 BIT(offset, 10)
32#define VA12 BIT(va, 12)
33
34
35
36//**************************************************************************
37//  INTERRUPTS
38//**************************************************************************
39
40//-------------------------------------------------
41//  check_interrupts -
42//-------------------------------------------------
43
44void p500_state::check_interrupts()
45{
46   m_maincpu->set_input_line(INPUT_LINE_IRQ0, m_vic_irq || m_tpi1_irq);   
47
48   mos6526_flag_w(m_cia, m_cass_rd && m_user_flag);
49}
50
51
52
53//**************************************************************************
54//  MEMORY MANAGEMENT UNIT
55//**************************************************************************
56
57//-------------------------------------------------
58//  bankswitch -
59//-------------------------------------------------
60
61void p500_state::bankswitch(offs_t offset, offs_t va, int srw, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas, int busy2, int refen,
62   int *datxen, int *dramxen, int *clrniben, int *_64kcasen, int *casenb, int *viddaten, int *viddat_tr,
63   int *clrnibcs, int *extbufcs, int *discromcs, int *buframcs, int *charomcs, int *viccs, int *vidmatcs,
64   int *csbank1, int *csbank2, int *csbank3, int *basiclocs, int *basichics, int *kernalcs,
65   int *cs1, int *sidcs, int *extprtcs, int *ciacs, int *aciacs, int *tript1cs, int *tript2cs, int *aec, int *vsysaden)
66{
67   *aec = !((m_statvid || ae) && sphi2);
68
69   int clrnibcsb = 1;
70   int procvid = 1;
71
72   UINT32 input = P0 << 15 | P2 << 14 | bras << 13 | P1 << 12 | P3 << 11 | busy2 << 10 | m_statvid << 9 | sphi2 << 8 |
73               clrnibcsb << 7 | m_dramon << 6 | procvid << 5 | refen << 4 | m_vicdotsel << 3 | ba << 2 | *aec << 1 | srw;
74   UINT32 data = m_pla1->read(input);
75
76   int segf = BIT(data, 3);
77
78   int bank0 = 1, vicen = 1;
79
80   if (!*aec && !segf)
81   {
82      switch ((offset >> 13) & 0x07)
83      {
84      case 0: bank0 = 0; break;
85      case 1: *csbank1 = 0; break;
86      case 2: *csbank2 = 0; break;
87      case 3: *csbank3 = 0; break;
88      case 4: *basiclocs = 0; break;
89      case 5: *basichics = 0; break;
90      case 6:
91         if (A12 && A11)
92         {
93            switch ((offset >> 8) & 0x07)
94            {
95            case 0: vicen = 0; break;
96            case 1: *cs1 = 0; break;
97            case 2: *sidcs = 0; break;
98            case 3: *extprtcs = 0; break;
99            case 4: *ciacs = 0; break;
100            case 5: *aciacs = 0; break;
101            case 6: *tript1cs = 0; break;
102            case 7: *tript2cs = 0; break;
103            }
104         }
105         break;
106
107      case 7: *kernalcs = 0; break;
108      }
109   }
110
111   input = VA12 << 15 | ba << 14 | A13 << 13 | A15 << 12 | A14 << 11 | A11 << 10 | A10 << 9 | A12 << 8 |
112         sphi2 << 7 | vicen << 6 | m_statvid << 5 | m_vicdotsel << 4 | ae << 3 | segf << 2 | bcas << 1 | bank0;
113   data = m_pla2->read(input);
114
115   clrnibcsb = BIT(data, 0);
116   if (!bcas) *clrnibcs = clrnibcsb;
117   *extbufcs = BIT(data, 1);
118   *discromcs = BIT(data, 2);
119   *buframcs = BIT(data, 3);
120   *charomcs = BIT(data, 4);
121   procvid = BIT(data, 5);
122   *viccs = BIT(data, 6);
123   if (!bcas) *vidmatcs = BIT(data, 7);
124
125   input = P0 << 15 | P2 << 14 | bras << 13 | P1 << 12 | P3 << 11 | busy2 << 10 | m_statvid << 9 | sphi2 << 8 |
126         clrnibcsb << 7 | m_dramon << 6 | procvid << 5 | refen << 4 | m_vicdotsel << 3 | ba << 2 | *aec << 1 | srw;
127   data = m_pla1->read(input);
128
129   *datxen = BIT(data, 0);
130   *dramxen = BIT(data, 1);
131   *clrniben = BIT(data, 2);
132   //*segf = BIT(data, 3);
133   *_64kcasen = BIT(data, 4);
134   *casenb = BIT(data, 5);
135   *viddaten = BIT(data, 6);
136   *viddat_tr = BIT(data, 7);
137
138   *vsysaden = sphi1 || ba;
139}
140
141
142//-------------------------------------------------
143//  read_memory -
144//-------------------------------------------------
145
146UINT8 p500_state::read_memory(address_space &space, offs_t offset, offs_t va, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas)
147{
148   int srw = 1, busy2 = 1, refen = 0;
149   
150   int datxen = 1, dramxen = 1, clrniben = 1, _64kcasen = 1, casenb = 1, viddaten = 1, viddat_tr = 1;
151   int clrnibcs = 1, extbufcs = 1, discromcs = 1, buframcs = 1, charomcs = 1, viccs = 1, vidmatcs = 1;
152   int csbank1 = 1, csbank2 = 1, csbank3 = 1, basiclocs = 1, basichics = 1, kernalcs = 1;
153   int cs1 = 1, sidcs = 1, extprtcs = 1, ciacs = 1, aciacs = 1, tript1cs = 1, tript2cs = 1;
154   int aec = 1, vsysaden = 1;
155
156   bankswitch(offset, va, srw, sphi0, sphi1, sphi2, ba, ae, bras, bcas, busy2, refen,
157      &datxen, &dramxen, &clrniben, &_64kcasen, &casenb, &viddaten, &viddat_tr,
158      &clrnibcs, &extbufcs, &discromcs, &buframcs, &charomcs, &viccs, &vidmatcs,
159      &csbank1, &csbank2, &csbank3, &basiclocs, &basichics, &kernalcs,
160      &cs1, &sidcs, &extprtcs, &ciacs, &aciacs, &tript1cs, &tript2cs, &aec, &vsysaden);
161/*
162   if (!space.debugger_access() && !ae)
163   logerror("read  %05x %u %u %u %u %u %u %u - %u %u %u %u %u %u %u - %u %u %u %u %u %u - %u %u %u %u %u %u %u - %u %u : ",
164      offset, datxen, dramxen, clrniben, _64kcasen, casenb, viddaten, viddat_tr,
165      clrnibcs, extbufcs, discromcs, buframcs, charomcs, viccs, vidmatcs,
166      csbank1, csbank2, csbank3, basiclocs, basichics, kernalcs,
167      cs1, sidcs, extprtcs, ciacs, aciacs, tript1cs, tript2cs, aec, vsysaden);
168*/
169   UINT8 data = 0xff;
170
171   if (ae)
172   {
173      data = m_vic->bus_r();
174   }
175
176   if (aec && !datxen && !_64kcasen)
177   {
178      data = m_ram->pointer()[offset & 0xffff];
179      //if (!space.debugger_access() && !ae) logerror("64K\n");
180   }
181   else if (!aec && !viddaten && viddat_tr && !_64kcasen)
182   {
183      data = m_ram->pointer()[(m_vicbnksel << 14) | va];
184      //if (!space.debugger_access() && !ae) logerror("64K\n");
185   }
186   else if (!dramxen && casenb && !P3)
187   {
188      switch ((offset >> 15) & 0x07)
189      {
190      case 1: data = m_ram->pointer()[0x10000 + (offset & 0xffff)]; break;
191      case 2: if (m_ram->size() > 0x20000) data = m_ram->pointer()[0x20000 + (offset & 0xffff)]; break;
192      case 3: if (m_ram->size() > 0x30000) data = m_ram->pointer()[0x30000 + (offset & 0xffff)]; break;
193      }
194      //if (!space.debugger_access() && !ae) logerror("CASEN\n");
195   }
196   else if (!datxen && !buframcs)
197   {
198      data = m_buffer_ram[offset & 0x7ff];
199      //if (!space.debugger_access() && !ae) logerror("BUFRAM\n");
200   }
201   else if (!vsysaden && clrniben && !clrnibcs)
202   {
203      data = m_color_ram[offset & 0x3ff];
204      //if (!space.debugger_access() && !ae) logerror("CLRNIB\n");
205   }
206   else if (vsysaden && !clrnibcs)
207   {
208      data = m_color_ram[va & 0x3ff];
209      //if (!space.debugger_access() && !ae) logerror("CLRNIB\n");
210   }
211   else if (!datxen && !vsysaden && !viddaten && viddat_tr && !vidmatcs)
212   {
213      data = m_video_ram[offset & 0x3ff];
214      //if (!space.debugger_access() && !ae) logerror("VIDMAT\n");
215   }
216   else if (vsysaden && !vidmatcs)
217   {
218      data = m_video_ram[va & 0x3ff];
219      //if (!space.debugger_access() && !ae) logerror("VIDMAT\n");
220   }
221   else if (!datxen && (!basiclocs || !basichics))
222   {
223      data = m_basic[offset & 0x3fff];
224      //if (!space.debugger_access() && !ae) logerror("BASIC\n");
225   }
226   else if (!datxen && !kernalcs)
227   {
228      data = m_kernal[offset & 0x1fff];
229      //if (!space.debugger_access() && !ae) logerror("KERNAL\n");
230   }
231   else if (!datxen && !vsysaden && !viddaten && viddat_tr && !charomcs)
232   {
233      data = m_charom[offset & 0xfff];
234      //if (!space.debugger_access() && !ae) logerror("CHAROM\n");
235   }
236   else if (vsysaden && !charomcs)
237   {
238      data = m_charom[va & 0xfff];
239      //if (!space.debugger_access() && !ae) logerror("CHAROM\n");
240   }
241   else if (!datxen && !viddaten && viddat_tr && !viccs)
242   {
243      data = m_vic->read(space, offset & 0x3f);
244      //if (!space.debugger_access() && !ae) logerror("VIC\n");
245   }
246   else if (!datxen && !sidcs)
247   {
248      data = m_sid->read(space, offset & 0x1f);
249      //if (!space.debugger_access() && !ae) logerror("SID\n");
250   }
251   else if (!datxen && !ciacs)
252   {
253      data = m_cia->read(space, offset & 0x0f);
254      //if (!space.debugger_access() && !ae) logerror("CIA\n");
255   }
256   else if (!datxen && !aciacs)
257   {
258      data = m_acia->read(space, offset & 0x03);
259      //if (!space.debugger_access() && !ae) logerror("ACIA\n");
260   }
261   else if (!datxen && !tript1cs)
262   {
263      data = m_tpi1->read(space, offset & 0x07);
264      //if (!space.debugger_access() && !ae) logerror("TPI1\n");
265   }
266   else if (!datxen && !tript2cs)
267   {
268      data = m_tpi2->read(space, offset & 0x07);
269      //if (!space.debugger_access() && !ae) logerror("TPI2\n");
270   }
271   //else if (!space.debugger_access() && !ae) logerror("\n");
272
273   if (!datxen) data = m_exp->read(space, offset & 0x1fff, data, csbank1, csbank2, csbank3);
274
275   return data;
276}
277
278
279//-------------------------------------------------
280//  write_memory -
281//-------------------------------------------------
282
283void p500_state::write_memory(address_space &space, offs_t offset, UINT8 data, int sphi0, int sphi1, int sphi2, int ba, int ae, int bras, int bcas)
284{
285   int srw = 0, busy2 = 1, refen = 0;
286   offs_t va = 0xffff;
287   
288   int datxen = 1, dramxen = 1, clrniben = 1, _64kcasen = 1, casenb = 1, viddaten = 1, viddat_tr = 1;
289   int clrnibcs = 1, extbufcs = 1, discromcs = 1, buframcs = 1, charomcs = 1, viccs = 1, vidmatcs = 1;
290   int csbank1 = 1, csbank2 = 1, csbank3 = 1, basiclocs = 1, basichics = 1, kernalcs = 1;
291   int cs1 = 1, sidcs = 1, extprtcs = 1, ciacs = 1, aciacs = 1, tript1cs = 1, tript2cs = 1;
292   int aec = 1, vsysaden = 1;
293
294   bankswitch(offset, va, srw, sphi0, sphi1, sphi2, ba, ae, bras, bcas, busy2, refen,
295      &datxen, &dramxen, &clrniben, &_64kcasen, &casenb, &viddaten, &viddat_tr,
296      &clrnibcs, &extbufcs, &discromcs, &buframcs, &charomcs, &viccs, &vidmatcs,
297      &csbank1, &csbank2, &csbank3, &basiclocs, &basichics, &kernalcs,
298      &cs1, &sidcs, &extprtcs, &ciacs, &aciacs, &tript1cs, &tript2cs, &aec, &vsysaden);
299/*
300   if (!space.debugger_access())
301   logerror("write %05x %u %u %u %u %u %u %u - %u %u %u %u %u %u %u - %u %u %u %u %u %u - %u %u %u %u %u %u %u - %u %u: ",
302      offset, datxen, dramxen, clrniben, _64kcasen, casenb, viddaten, viddat_tr,
303      clrnibcs, extbufcs, discromcs, buframcs, charomcs, viccs, vidmatcs,
304      csbank1, csbank2, csbank3, basiclocs, basichics, kernalcs,
305      cs1, sidcs, extprtcs, ciacs, aciacs, tript1cs, tript2cs, aec, vsysaden);
306*/
307   if (!aec && !datxen && !_64kcasen)
308   {
309      //logerror("64K RAM\n");
310      m_ram->pointer()[offset & 0xffff] = data;
311   }
312   else if (!dramxen && casenb && !P3)
313   {
314      //logerror("CASENB\n");
315      switch ((offset >> 15) & 0x07)
316      {
317      case 1: m_ram->pointer()[0x10000 + (offset & 0xffff)] = data; break;
318      case 2: if (m_ram->size() > 0x20000) m_ram->pointer()[0x20000 + (offset & 0xffff)] = data; break;
319      case 3: if (m_ram->size() > 0x30000) m_ram->pointer()[0x30000 + (offset & 0xffff)] = data; break;
320      }
321   }
322   else if (!datxen && !buframcs)
323   {
324      //logerror("BUFRAM\n");
325      m_buffer_ram[offset & 0x7ff] = data;
326   }
327   else if (!vsysaden && clrniben && !clrnibcs)
328   {
329      //logerror("CLRNIB\n");
330      m_color_ram[offset & 0x3ff] = data;
331   }
332   else if (!datxen && !vsysaden && !viddaten && !viddat_tr && !vidmatcs)
333   {
334      //logerror("VIDMAT\n");
335      m_video_ram[offset & 0x3ff] = data;
336   }
337   else if (vsysaden && !vidmatcs)
338   {
339      //logerror("VIDMAT\n");
340      m_video_ram[va & 0x3ff] = data;
341   }
342   else if (!datxen && !viddaten && !viddat_tr && !viccs)
343   {
344      //logerror("VIC\n");
345      m_vic->write(space, offset & 0x3f, data);
346   }
347   else if (!datxen && !sidcs)
348   {
349      //logerror("SID\n");
350      m_sid->write(space, offset & 0x1f, data);
351   }
352   else if (!datxen && !ciacs)
353   {
354      //logerror("CIA\n");
355      m_cia->write(space, offset & 0x0f, data);
356   }
357   else if (!datxen && !aciacs)
358   {
359      //logerror("ACIA\n");
360      m_acia->write(space, offset & 0x03, data);
361   }
362   else if (!datxen && !tript1cs)
363   {
364      //logerror("TPI1\n");
365      m_tpi1->write(space, offset & 0x07, data);
366   }
367   else if (!datxen && !tript2cs)
368   {
369      //logerror("TPI2\n");
370      m_tpi2->write(space, offset & 0x07, data);
371   }
372   //else logerror("\n");
373
374   if (!datxen) m_exp->write(space, offset & 0x1fff, data, csbank1, csbank2, csbank3);
375}
376
377
378//-------------------------------------------------
379//  read -
380//-------------------------------------------------
381
382READ8_MEMBER( p500_state::read )
383{
384   int sphi0 = 1, sphi1 = 0, sphi2 = 1, ba = 0, ae = 1, bras = 1, bcas = 0;
385   offs_t va = 0xffff;
386
387   return read_memory(space, offset, va, sphi0, sphi1, sphi2, ba, ae, bras, bcas);
388}
389
390
391//-------------------------------------------------
392//  write -
393//-------------------------------------------------
394
395WRITE8_MEMBER( p500_state::write )
396{
397   int sphi0 = 1, sphi1 = 0, sphi2 = 1, ba = 0, ae = 1, bras = 1, bcas = 0;
398
399   write_memory(space, offset, data, sphi0, sphi1, sphi2, ba, ae, bras, bcas);
400}
401
402
403//-------------------------------------------------
404//  vic_videoram_r -
405//-------------------------------------------------
406
407READ8_MEMBER( p500_state::vic_videoram_r )
408{
409/*   int sphi0 = 0, sphi1 = 1, sphi2 = 0, ba = 1, ae = 0, bras = 0, bcas = 0;
410   offs_t va = offset;
411
412   return read_memory(space, 0, va, sphi0, sphi1, sphi2, ba, ae, bras, bcas);*/
413
414   if (offset < 0x1000)
415   {
416      return m_charom[offset & 0xfff];
417   }
418   else
419   {
420      return m_video_ram[offset & 0x3ff];
421   }
422}
423
424
425
426//**************************************************************************
427//  ADDRESS MAPS
428//**************************************************************************
429
430//-------------------------------------------------
431//  ADDRESS_MAP( p500_mem )
432//-------------------------------------------------
433
434static ADDRESS_MAP_START( p500_mem, AS_PROGRAM, 8, p500_state )
435   AM_RANGE(0x00000, 0xfffff) AM_READWRITE(read, write)
436ADDRESS_MAP_END
437
438
439//-------------------------------------------------
440//  ADDRESS_MAP( vic_videoram_map )
441//-------------------------------------------------
442
443static ADDRESS_MAP_START( vic_videoram_map, AS_0, 8, p500_state )
444   AM_RANGE(0x0000, 0x3fff) AM_READ(vic_videoram_r)
445ADDRESS_MAP_END
446
447
448//-------------------------------------------------
449//  ADDRESS_MAP( vic_colorram_map )
450//-------------------------------------------------
451
452static ADDRESS_MAP_START( vic_colorram_map, AS_1, 8, p500_state )
453   AM_RANGE(0x000, 0x3ff) AM_RAM AM_SHARE("color_ram")
454ADDRESS_MAP_END
455
456
457
458//**************************************************************************
459//  INPUT PORTS
460//**************************************************************************
461
462//-------------------------------------------------
463//  INPUT_PORTS( p500 )
464//-------------------------------------------------
465
466static INPUT_PORTS_START( p500 )
467   PORT_START("PB0")
468   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F1") PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1))
469   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC)
470   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')
471   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
472   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("SHIFT") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
473   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
474   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
475
476   PORT_START("PB1")
477   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F2") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2))
478   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
479   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
480   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
481   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
482   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
483   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
484
485   PORT_START("PB2")
486   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F3") PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F3))
487   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('@')
488   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
489   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
490   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
491   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
492   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
493
494   PORT_START("PB3")
495   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F4") PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4))
496   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
497   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
498   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
499   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
500   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
501   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
502
503   PORT_START("PB4")
504   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F5") PORT_CODE(KEYCODE_F5) PORT_CHAR(UCHAR_MAMEKEY(F5))
505   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
506   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
507   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
508   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
509   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
510   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
511
512   PORT_START("PB5")
513   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F6") PORT_CODE(KEYCODE_F6) PORT_CHAR(UCHAR_MAMEKEY(F6))
514   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
515   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('^')
516   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
517   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
518   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
519   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
520
521   PORT_START("PB6")
522   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F7") PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F7))
523   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
524   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
525   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
526   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
527   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
528   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
529
530   PORT_START("PB7")
531   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F8") PORT_CODE(KEYCODE_F8) PORT_CHAR(UCHAR_MAMEKEY(F8))
532   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
533   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
534   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
535   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
536   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
537   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
538
539   PORT_START("PA0")
540   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F9") PORT_CODE(KEYCODE_F9) PORT_CHAR(UCHAR_MAMEKEY(F9))
541   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
542   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
543   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
544   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR(':')
545   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
546   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
547
548   PORT_START("PA1")
549   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F10") PORT_CODE(KEYCODE_F10) PORT_CHAR(UCHAR_MAMEKEY(F10))
550   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR(')')
551   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-')
552   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
553   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('[')
554   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR('\'') PORT_CHAR('"')
555   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
556
557   PORT_START("PA2")
558   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_DOWN) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
559   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('=') PORT_CHAR('+')
560   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_LEFT" \xC2\xA3") PORT_CODE(KEYCODE_TILDE) PORT_CHAR(UCHAR_MAMEKEY(TILDE)) PORT_CHAR(0x00a3)
561   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR(']')
562   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RETURN") PORT_CODE(KEYCODE_ENTER) PORT_CHAR('\r')
563   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("\xCF\x80") PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR(0x03c0)
564   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
565
566   PORT_START("PA3")
567   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_UP) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
568   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_LEFT) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
569   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME(UTF8_RIGHT) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
570   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("INS/DEL") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
571   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("C=") PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
572   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
573   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
574
575   PORT_START("PA4")
576   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CLR/HOME") PORT_CODE(KEYCODE_HOME)
577   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad ?")
578   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 7") PORT_CODE(KEYCODE_7_PAD) PORT_CHAR(UCHAR_MAMEKEY(7_PAD))
579   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 4") PORT_CODE(KEYCODE_4_PAD) PORT_CHAR(UCHAR_MAMEKEY(4_PAD))
580   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 1") PORT_CODE(KEYCODE_1_PAD) PORT_CHAR(UCHAR_MAMEKEY(1_PAD))
581   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 0") PORT_CODE(KEYCODE_0_PAD) PORT_CHAR(UCHAR_MAMEKEY(0_PAD))
582   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
583
584   PORT_START("PA5")
585   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("OFF/RVS") PORT_CODE(KEYCODE_END)
586   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad CE")
587   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 8") PORT_CODE(KEYCODE_8_PAD) PORT_CHAR(UCHAR_MAMEKEY(8_PAD))
588   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 5") PORT_CODE(KEYCODE_5_PAD) PORT_CHAR(UCHAR_MAMEKEY(5_PAD))
589   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 2") PORT_CODE(KEYCODE_2_PAD) PORT_CHAR(UCHAR_MAMEKEY(2_PAD))
590   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad .") PORT_CODE(KEYCODE_DEL_PAD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD))
591   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
592
593   PORT_START("PA6")
594   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("NORM/GRAPH") PORT_CODE(KEYCODE_PGUP)
595   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad *") PORT_CODE(KEYCODE_ASTERISK) PORT_CHAR(UCHAR_MAMEKEY(ASTERISK))
596   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 9") PORT_CODE(KEYCODE_9_PAD) PORT_CHAR(UCHAR_MAMEKEY(9_PAD))
597   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 6") PORT_CODE(KEYCODE_6_PAD) PORT_CHAR(UCHAR_MAMEKEY(6_PAD))
598   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 3") PORT_CODE(KEYCODE_3_PAD) PORT_CHAR(UCHAR_MAMEKEY(3_PAD))
599   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad 00")
600   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
601
602   PORT_START("PA7")
603   PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("RUN/STOP") PORT_CODE(KEYCODE_PGDN)
604   PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad /") PORT_CODE(KEYCODE_SLASH_PAD) PORT_CHAR(UCHAR_MAMEKEY(SLASH_PAD))
605   PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad -") PORT_CODE(KEYCODE_MINUS_PAD) PORT_CHAR(UCHAR_MAMEKEY(MINUS_PAD))
606   PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad +") PORT_CODE(KEYCODE_PLUS_PAD) PORT_CHAR(UCHAR_MAMEKEY(PLUS_PAD))
607   PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Keypad ENTER") PORT_CODE(KEYCODE_ENTER_PAD) PORT_CHAR(UCHAR_MAMEKEY(ENTER_PAD))
608   PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
609   PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
610INPUT_PORTS_END
611
612
613
614//**************************************************************************
615//  DEVICE CONFIGURATION
616//**************************************************************************
617
618//-------------------------------------------------
619//  vic2_interface vic_intf
620//-------------------------------------------------
621
622WRITE_LINE_MEMBER( p500_state::vic_irq_w )
623{
624   m_vic_irq = state;
625
626   check_interrupts();
627}
628
629static MOS6567_INTERFACE( vic_intf )
630{
631   SCREEN_TAG,
632   M6509_TAG,
633   DEVCB_DRIVER_LINE_MEMBER(p500_state, vic_irq_w),
634   DEVCB_NULL, // RDY
635   DEVCB_NULL,
636   DEVCB_NULL,
637   DEVCB_NULL,
638   DEVCB_NULL
639};
640
641
642//-------------------------------------------------
643//  MOS6581_INTERFACE( sid_intf )
644//-------------------------------------------------
645
646READ8_MEMBER( p500_state::sid_potx_r )
647{
648   int sela = BIT(m_cia_pa, 6);
649   int selb = BIT(m_cia_pa, 7);
650
651   UINT8 data = 0;
652
653   if (sela) data = m_joy1->pot_x_r();
654   if (selb) data = m_joy2->pot_x_r();
655
656   return data;
657}
658
659READ8_MEMBER( p500_state::sid_poty_r )
660{
661   int sela = BIT(m_cia_pa, 6);
662   int selb = BIT(m_cia_pa, 7);
663
664   UINT8 data = 0;
665
666   if (sela) data = m_joy1->pot_y_r();
667   if (selb) data = m_joy2->pot_y_r();
668
669   return data;
670}
671
672static MOS6581_INTERFACE( sid_intf )
673{
674   DEVCB_DRIVER_MEMBER(p500_state, sid_potx_r),
675   DEVCB_DRIVER_MEMBER(p500_state, sid_poty_r)
676};
677
678
679//-------------------------------------------------
680//  tpi6525_interface tpi1_intf
681//-------------------------------------------------
682
683WRITE_LINE_MEMBER( p500_state::tpi1_irq_w )
684{
685   m_tpi1_irq = state;
686
687   check_interrupts();
688}
689
690READ8_MEMBER( p500_state::tpi1_pa_r )
691{
692   /*
693   
694       bit     description
695   
696       0       
697       1       
698       2       REN
699       3       ATN
700       4       DAV
701       5       EOI
702       6       NDAC
703       7       NRFD
704   
705   */
706
707   UINT8 data = 0;
708
709   // IEEE-488
710   data |= m_ieee->ren_r() << 2;
711   data |= m_ieee->atn_r() << 3;
712   data |= m_ieee->dav_r() << 4;
713   data |= m_ieee->eoi_r() << 5;
714   data |= m_ieee->ndac_r() << 6;
715   data |= m_ieee->nrfd_r() << 7;
716
717   return data;
718}
719
720WRITE8_MEMBER( p500_state::tpi1_pa_w )
721{
722   /*
723   
724       bit     description
725   
726       0       75161A DC
727       1       75161A TE
728       2       REN
729       3       ATN
730       4       DAV
731       5       EOI
732       6       NDAC
733       7       NRFD
734   
735   */
736
737   // IEEE-488
738   m_ieee->ren_w(BIT(data, 2));
739   m_ieee->atn_w(BIT(data, 3));
740   m_ieee->dav_w(BIT(data, 4));
741   m_ieee->eoi_w(BIT(data, 5));
742   m_ieee->ndac_w(BIT(data, 6));
743   m_ieee->nrfd_w(BIT(data, 7));
744}
745
746READ8_MEMBER( p500_state::tpi1_pb_r )
747{
748   /*
749   
750       bit     description
751   
752       0       IFC
753       1       SRQ
754       2       user port
755       3       user port
756       4       
757       5       
758       6       
759       7       CASS SW
760   
761   */
762
763   UINT8 data = 0;
764
765   // IEEE-488
766   data |= m_ieee->ifc_r();
767   data |= m_ieee->srq_r() << 1;
768
769   // cassette
770   data |= m_cassette->sense_r() << 7;
771
772   return data;
773}
774
775WRITE8_MEMBER( p500_state::tpi1_pb_w )
776{
777   /*
778   
779       bit     description
780   
781       0       IFC
782       1       SRQ
783       2       user port
784       3       user port
785       4       DRAMON
786       5       CASS WRT
787       6       CASS MTR
788       7       
789   
790   */
791
792   // IEEE-488
793   m_ieee->ifc_w(BIT(data, 0));
794   m_ieee->srq_w(BIT(data, 1));
795
796   // memory
797   m_dramon = BIT(data, 4);
798
799   // cassette
800   m_cassette->write(BIT(data, 5));
801   m_cassette->motor_w(BIT(data, 6));
802}
803
804WRITE_LINE_MEMBER( p500_state::tpi1_ca_w )
805{
806   //logerror("STATVID %u\n", state);
807
808   m_statvid = state;
809}
810
811WRITE_LINE_MEMBER( p500_state::tpi1_cb_w )
812{
813   //logerror("VICDOTSEL %u\n", state);
814
815   m_vicdotsel = state;
816}
817
818static const tpi6525_interface tpi1_intf =
819{
820   DEVCB_DRIVER_LINE_MEMBER(p500_state, tpi1_irq_w),
821   DEVCB_DRIVER_MEMBER(p500_state, tpi1_pa_r),
822   DEVCB_DRIVER_MEMBER(p500_state, tpi1_pa_w),
823   DEVCB_DRIVER_MEMBER(p500_state, tpi1_pb_r),
824   DEVCB_DRIVER_MEMBER(p500_state, tpi1_pb_w),
825   DEVCB_NULL,
826   DEVCB_NULL,
827   DEVCB_DRIVER_LINE_MEMBER(p500_state, tpi1_ca_w),
828   DEVCB_DRIVER_LINE_MEMBER(p500_state, tpi1_cb_w)
829};
830
831
832//-------------------------------------------------
833//  tpi6525_interface tpi2_intf
834//-------------------------------------------------
835
836WRITE8_MEMBER( p500_state::tpi2_pa_w )
837{
838   m_tpi2_pa = data;
839}
840
841WRITE8_MEMBER( p500_state::tpi2_pb_w )
842{
843   m_tpi2_pb = data;
844}
845
846READ8_MEMBER( p500_state::tpi2_pc_r )
847{
848   /*
849   
850       bit     description
851   
852       0       COLUMN 0
853       1       COLUMN 1
854       2       COLUMN 2
855       3       COLUMN 3
856       4       COLUMN 4
857       5       COLUMN 5
858       6       
859       7       
860   
861   */
862
863   UINT8 data = 0xff;
864
865   if (!BIT(m_tpi2_pa, 0)) data &= ioport("PA0")->read();
866   if (!BIT(m_tpi2_pa, 1)) data &= ioport("PA1")->read();
867   if (!BIT(m_tpi2_pa, 2)) data &= ioport("PA2")->read();
868   if (!BIT(m_tpi2_pa, 3)) data &= ioport("PA3")->read();
869   if (!BIT(m_tpi2_pa, 4)) data &= ioport("PA4")->read();
870   if (!BIT(m_tpi2_pa, 5)) data &= ioport("PA5")->read();
871   if (!BIT(m_tpi2_pa, 6)) data &= ioport("PA6")->read();
872   if (!BIT(m_tpi2_pa, 7)) data &= ioport("PA7")->read();
873   if (!BIT(m_tpi2_pb, 0)) data &= ioport("PB0")->read();
874   if (!BIT(m_tpi2_pb, 1)) data &= ioport("PB1")->read();
875   if (!BIT(m_tpi2_pb, 2)) data &= ioport("PB2")->read();
876   if (!BIT(m_tpi2_pb, 3)) data &= ioport("PB3")->read();
877   if (!BIT(m_tpi2_pb, 4)) data &= ioport("PB4")->read();
878   if (!BIT(m_tpi2_pb, 5)) data &= ioport("PB5")->read();
879   if (!BIT(m_tpi2_pb, 6)) data &= ioport("PB6")->read();
880   if (!BIT(m_tpi2_pb, 7)) data &= ioport("PB7")->read();
881
882   return data;
883}
884
885WRITE8_MEMBER( p500_state::tpi2_pc_w )
886{
887   /*
888   
889       bit     description
890   
891       0       
892       1       
893       2       
894       3       
895       4       
896       5       
897       6       VICBNKSEL0
898       7       VICBNKSEL1
899   
900   */
901
902   m_vicbnksel = data >> 6;
903}
904
905static const tpi6525_interface tpi2_intf =
906{
907   DEVCB_NULL,
908   DEVCB_NULL,
909   DEVCB_DRIVER_MEMBER(p500_state, tpi2_pa_w),
910   DEVCB_NULL,
911   DEVCB_DRIVER_MEMBER(p500_state, tpi2_pb_w),
912   DEVCB_DRIVER_MEMBER(p500_state, tpi2_pc_r),
913   DEVCB_DRIVER_MEMBER(p500_state, tpi2_pc_w),
914   DEVCB_NULL,
915   DEVCB_NULL
916};
917
918
919//-------------------------------------------------
920//  mos6526_interface cia_intf
921//-------------------------------------------------
922
923READ8_MEMBER( p500_state::cia_pa_r )
924{
925   /*
926   
927       bit     description
928   
929       0       user port
930       1       user port
931       2       user port
932       3       user port
933       4       user port
934       5       user port
935       6       LTPN, user port
936       7       GAME TRIGGER 24, user port
937   
938   */
939
940   UINT8 data = 0;
941
942   // joystick
943   data |= BIT(m_joy1->joy_r(), 5) << 6;
944   data |= BIT(m_joy2->joy_r(), 5) << 7;
945
946   return data;
947}
948
949WRITE8_MEMBER( p500_state::cia_pa_w )
950{
951   /*
952   
953       bit     description
954   
955       0       user port
956       1       user port
957       2       user port
958       3       user port
959       4       user port
960       5       user port
961       6       user port
962       7       user port
963   
964   */
965
966   m_cia_pa = data;
967}
968
969READ8_MEMBER( p500_state::cia_pb_r )
970{
971   /*
972   
973       bit     description
974   
975       0       GAME 10, user port
976       1       GAME 11, user port
977       2       GAME 12, user port
978       3       GAME 13, user port
979       4       GAME 20, user port
980       5       GAME 21, user port
981       6       GAME 22, user port
982       7       GAME 23, user port
983   
984   */
985
986   UINT8 data = 0;
987
988   // joystick
989   data |= m_joy1->joy_r() & 0x0f;
990   data |= (m_joy2->joy_r() & 0x0f) << 4;
991
992   return data;
993}
994
995WRITE8_MEMBER( p500_state::cia_pb_w )
996{
997   /*
998   
999       bit     description
1000   
1001       0       user port
1002       1       user port
1003       2       user port
1004       3       user port
1005       4       user port
1006       5       user port
1007       6       user port
1008       7       user port
1009   
1010   */
1011}
1012
1013static const mos6526_interface cia_intf =
1014{
1015   DEVCB_DEVICE_LINE_MEMBER(MOS6525_1_TAG, tpi6525_device, i2_w),
1016   DEVCB_NULL, // user port
1017   DEVCB_NULL, // user port
1018   DEVCB_NULL, // user port
1019   DEVCB_DRIVER_MEMBER(p500_state, cia_pa_r),
1020   DEVCB_DRIVER_MEMBER(p500_state, cia_pa_w),
1021   DEVCB_DRIVER_MEMBER(p500_state, cia_pb_r),
1022   DEVCB_DRIVER_MEMBER(p500_state, cia_pb_w),
1023};
1024
1025
1026//-------------------------------------------------
1027//  PET_DATASSETTE_PORT_INTERFACE( datassette_intf )
1028//-------------------------------------------------
1029
1030WRITE_LINE_MEMBER( p500_state::tape_read_w )
1031{
1032   m_cass_rd = state;
1033
1034   check_interrupts();
1035}
1036
1037static PET_DATASSETTE_PORT_INTERFACE( datassette_intf )
1038{
1039   DEVCB_DRIVER_LINE_MEMBER(p500_state, tape_read_w)
1040};
1041
1042
1043//-------------------------------------------------
1044//  IEEE488_INTERFACE( ieee488_intf )
1045//-------------------------------------------------
1046
1047static IEEE488_INTERFACE( ieee488_intf )
1048{
1049   DEVCB_NULL,
1050   DEVCB_NULL,
1051   DEVCB_NULL,
1052   DEVCB_NULL,
1053   DEVCB_NULL,
1054   DEVCB_DEVICE_LINE_MEMBER(MOS6525_1_TAG, tpi6525_device, i1_w),
1055   DEVCB_NULL,
1056   DEVCB_NULL
1057};
1058
1059
1060
1061//**************************************************************************
1062//  MACHINE INITIALIZATION
1063//**************************************************************************
1064
1065//-------------------------------------------------
1066//  device_timer - handler timer events
1067//-------------------------------------------------
1068
1069void p500_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
1070{
1071   m_tpi1->i0_w(m_todclk);
1072
1073   m_todclk = !m_todclk;
1074}
1075
1076
1077//-------------------------------------------------
1078//  MACHINE_START( p500 )
1079//-------------------------------------------------
1080
1081void p500_state::machine_start()
1082{
1083   // find memory regions
1084   m_basic = memregion("basic")->base();
1085   m_kernal = memregion("kernal")->base();
1086   m_charom = memregion("charom")->base();
1087
1088   // allocate memory
1089   m_video_ram.allocate(0x400);
1090   m_buffer_ram.allocate(0x800);
1091
1092   // allocate timer
1093   m_todclk_timer = timer_alloc();
1094   m_todclk_timer->adjust(attotime::from_hz(60 * 2), 0, attotime::from_hz(60 * 2));
1095
1096   // state saving
1097   save_item(NAME(m_dramon));
1098   save_item(NAME(m_statvid));
1099   save_item(NAME(m_vicdotsel));
1100   save_item(NAME(m_vicbnksel));
1101   save_item(NAME(m_todclk));
1102   save_item(NAME(m_vic_irq));
1103   save_item(NAME(m_tpi1_irq));
1104   save_item(NAME(m_cass_rd));
1105   save_item(NAME(m_user_flag));
1106   save_item(NAME(m_tpi2_pa));
1107   save_item(NAME(m_tpi2_pb));
1108   save_item(NAME(m_cia_pa));
1109}
1110
1111
1112//-------------------------------------------------
1113//  MACHINE_RESET( p500 )
1114//-------------------------------------------------
1115
1116void p500_state::machine_reset()
1117{
1118   m_dramon = 1;
1119   m_statvid = 1;
1120   m_vicdotsel = 1;
1121   m_vicbnksel = 0x03;
1122   m_vic_irq = CLEAR_LINE;
1123   m_tpi1_irq = CLEAR_LINE;
1124   m_cass_rd = 1;
1125
1126   m_maincpu->reset();
1127
1128   m_tpi1->reset();
1129   m_tpi2->reset();
1130   m_acia->reset();
1131   m_cia->reset();
1132
1133   m_ieee->reset();
1134}
1135
1136
1137
1138//**************************************************************************
1139//  MACHINE DRIVERS
1140//**************************************************************************
1141
1142//-------------------------------------------------
1143//  MACHINE_CONFIG( p500 )
1144//-------------------------------------------------
1145
1146static MACHINE_CONFIG_START( p500, p500_state )
1147   // basic hardware
1148   MCFG_CPU_ADD(M6509_TAG, M6509, VIC6567_CLOCK)
1149   MCFG_CPU_PROGRAM_MAP(p500_mem)
1150   MCFG_QUANTUM_PERFECT_CPU(M6509_TAG)
1151
1152   // video hardware
1153   MCFG_MOS6567_ADD(MOS6567_TAG, SCREEN_TAG, VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
1154
1155   // sound hardware
1156   MCFG_SPEAKER_STANDARD_MONO("mono")
1157   MCFG_SOUND_ADD(MOS6851_TAG, SID6581, VIC6567_CLOCK)
1158   MCFG_SOUND_CONFIG(sid_intf)
1159   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
1160   MCFG_SOUND_ADD("dac", DAC, 0)
1161   MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
1162
1163   // devices
1164   MCFG_PLS100_ADD(PLA1_TAG)
1165   MCFG_PLS100_ADD(PLA2_TAG)
1166   MCFG_TPI6525_ADD(MOS6525_1_TAG, tpi1_intf)
1167   MCFG_TPI6525_ADD(MOS6525_2_TAG, tpi2_intf)
1168   MCFG_ACIA6551_ADD(MOS6551A_TAG)
1169   MCFG_MOS6526R1_ADD(MOS6526_TAG, VIC6567_CLOCK, 60, cia_intf)
1170   //MCFG_QUICKLOAD_ADD("quickload", cbm_p500, "p00,prg,t64", CBM_QUICKLOAD_DELAY_SECONDS)
1171   MCFG_CBM_IEEE488_ADD(ieee488_intf, NULL)
1172   MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, NULL, NULL)
1173   MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
1174   MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
1175   MCFG_CBM2_EXPANSION_SLOT_ADD(CBM2_EXPANSION_SLOT_TAG, VIC6567_CLOCK, cbm2_expansion_cards, NULL, NULL)
1176   //MCFG_CBM2_USER_PORT_ADD(CBM2_USER_PORT_TAG, user_intf, cbm2_user_port_cards, NULL, NULL)
1177   //MCFG_CBM2_SYSTEM_PORT_ADD(CBM2_SYSTEM_PORT_TAG, system_intf, cbm2_system_port_cards, NULL, NULL)
1178
1179   // software list
1180
1181   // internal ram
1182   MCFG_RAM_ADD(RAM_TAG)
1183   MCFG_RAM_DEFAULT_SIZE("128K")
1184   MCFG_RAM_EXTRA_OPTIONS("256K")
1185MACHINE_CONFIG_END
1186
1187
1188
1189//**************************************************************************
1190//  ROMS
1191//**************************************************************************
1192
1193//-------------------------------------------------
1194//  ROM( p500 )
1195//-------------------------------------------------
1196
1197ROM_START( p500 )
1198   ROM_REGION( 0x4000, "basic", 0 )
1199   ROM_DEFAULT_BIOS("r2")
1200   ROM_SYSTEM_BIOS( 0, "r1", "Revision 1" )
1201   ROMX_LOAD( "901236-01.u84", 0x0000, 0x2000, CRC(33eb6aa2) SHA1(7e3497ae2edbb38c753bd31ed1bf3ae798c9a976), ROM_BIOS(1) )
1202   ROMX_LOAD( "901235-01.u83", 0x2000, 0x2000, CRC(18a27feb) SHA1(951b5370dd7db762b8504a141f9f26de345069bb), ROM_BIOS(1) )
1203   ROM_SYSTEM_BIOS( 1, "r2", "Revision 2" )
1204   ROMX_LOAD( "901236-02.u84", 0x0000, 0x2000, CRC(c62ab16f) SHA1(f50240407bade901144f7e9f489fa9c607834eca), ROM_BIOS(2) )
1205   ROMX_LOAD( "901235-02.u83", 0x2000, 0x2000, CRC(20b7df33) SHA1(1b9a55f12f8cf025754d8029cc5324b474c35841), ROM_BIOS(2) )
1206
1207   ROM_REGION( 0x2000, "kernal", 0 )
1208   ROMX_LOAD( "901234-01.u82", 0x0000, 0x2000, CRC(67962025) SHA1(24b41b65c85bf30ab4e2911f677ce9843845b3b1), ROM_BIOS(1) )
1209   ROMX_LOAD( "901234-02.u82", 0x0000, 0x2000, CRC(f46bbd2b) SHA1(097197d4d08e0b82e0466a5f1fbd49a24f3d2523), ROM_BIOS(2) )
1210
1211   ROM_REGION( 0x1000, "charom", 0 )
1212   ROM_LOAD( "901225-01.u76", 0x0000, 0x1000, CRC(ec4272ee) SHA1(adc7c31e18c7c7413d54802ef2f4193da14711aa) )
1213
1214   ROM_REGION( 0xf5, PLA1_TAG, 0 )
1215   ROM_LOAD( "906114-02.u78", 0x00, 0xf5, CRC(6436b20b) SHA1(57ebebe771791288051afd1abe9b7500bd2df847) )
1216
1217   ROM_REGION( 0xf5, PLA2_TAG, 0 )
1218   ROM_LOAD( "906114-03.u88", 0x00, 0xf5, CRC(668c073e) SHA1(1115858bb2dc91ea9e2016ba2e23ec94239358b4) )
1219ROM_END
1220
1221
1222
1223//**************************************************************************
1224//  SYSTEM DRIVERS
1225//**************************************************************************
1226
1227//    YEAR  NAME    PARENT  COMPAT  MACHINE     INPUT   INIT                        COMPANY                         FULLNAME                            FLAGS
1228COMP( 1983,   p500,   0,      0,      p500,      p500,   driver_device,      0,      "Commodore Business Machines",   "P500 ~ B128-40 ~ PET-II (NTSC)",   GAME_NOT_WORKING )
trunk/src/mess/mess.mak
r18018r18019
888888   $(MESS_DRIVERS)/cbmb.o      \
889889   $(MESS_MACHINE)/cbmb.o      \
890890   $(MESS_VIDEO)/cbmb.o      \
891   $(MESS_DRIVERS)/cbm2.o      \
892   $(MESS_MACHINE)/cbm2exp.o   \
893   $(MESS_MACHINE)/cbm2_std.o   \
891894   $(MESS_DRIVERS)/c65.o      \
892895   $(MESS_MACHINE)/c65.o      \
893896   $(MESS_DRIVERS)/c128.o      \

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