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r17960 Monday 17th September, 2012 at 06:49:13 UTC by Miodrag Milanović |
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Clean-ups and version bump note: hoarded dump removed too from coco_cart.xml, this will not be tolerated |
[hash] | coco_cart.xml fm7_disk.xml mz2000_cass.xml neogeo.xml snes.xml stv.xml |
[src] | version.c |
[src/emu] | devcpu.h distate.c distate.h drawgfx.c drawgfx.h emuopts.c romload.c sprite.c sprite.h |
[src/emu/cpu] | drcbec.c |
[src/emu/cpu/am29000] | am29000.c am29ops.h |
[src/emu/cpu/apexc] | apexcdsm.c |
[src/emu/cpu/arm] | arm.c |
[src/emu/cpu/arm7] | arm7core.h |
[src/emu/cpu/cosmac] | cosdasm.c |
[src/emu/cpu/cubeqcpu] | cubeqcpu.c |
[src/emu/cpu/dsp56k] | dsp56k.h dsp56pcu.c |
[src/emu/cpu/esrip] | esrip.c |
[src/emu/cpu/g65816] | g65816ds.c |
[src/emu/cpu/h6280] | h6280.h |
[src/emu/cpu/h83002] | h8priv.h h8speriph.c |
[src/emu/cpu/hcd62121] | hcd62121d.c |
[src/emu/cpu/hd61700] | hd61700d.c |
[src/emu/cpu/hd6309] | 6309dasm.c |
[src/emu/cpu/i386] | cycles.h i386priv.h |
[src/emu/cpu/i86] | i286.c |
[src/emu/cpu/i860] | i860dis.c |
[src/emu/cpu/i960] | i960dis.c |
[src/emu/cpu/lh5801] | 5801dasm.c |
[src/emu/cpu/m37710] | m7700ds.c |
[src/emu/cpu/m6502] | m6502.c m6502.h m6509.c |
[src/emu/cpu/m68000] | m68k_in.c m68kdasm.c m68kmake.c |
[src/emu/cpu/m6805] | m6805.c |
[src/emu/cpu/m6809] | 6809dasm.c |
[src/emu/cpu/mb86233] | mb86233.c |
[src/emu/cpu/mips] | mips3.c |
[src/emu/cpu/nec] | necpriv.h v25priv.h |
[src/emu/cpu/powerpc] | ppc_dasm.c ppccom.c |
[src/emu/cpu/rsp] | rsp.h |
[src/emu/cpu/saturn] | saturnds.c |
[src/emu/cpu/sc61860] | scdasm.c |
[src/emu/cpu/sh2] | sh2comn.h |
[src/emu/cpu/sh4] | sh4comn.h |
[src/emu/cpu/sharc] | sharc.c sharc.h sharcdma.c sharcdsm.h sharcops.h |
[src/emu/cpu/spc700] | spc700.c spc700ds.c |
[src/emu/cpu/superfx] | superfx.c |
[src/emu/cpu/tlcs900] | 900tbl.c dasm900.c |
[src/emu/cpu/tms32051] | tms32051.c |
[src/emu/cpu/tms9900] | 9900dasm.c 99xxcore.h tms9900.h tms9900l.h tms9995.h |
[src/emu/cpu/upd7810] | upd7810.h |
[src/emu/imagedev] | floppy.c |
[src/emu/machine] | 53c810.c 6526cia.h 68681.c 8042kbdc.h latch8.h m6m80011ap.h matsucd.c msm6242.h net_lib.c net_lib.h netlist.c netlist.h pc16552d.c pckeybrd.h pic8259.c pit8253.c rp5h01.c rtc9701.h s3520cf.c s3520cf.h s3c2400.c s3c2400.h s3c2410.c s3c2410.h s3c2440.c s3c2440.h scsibus.c scsibus.h seibu_cop.c tms9901.h tms9902.h v3021.h wd33c93.c |
[src/emu/sound] | c140.c c352.h discrete.c discrete.h es5503.h fm.c fm2612.c fmopl.c i5000.h k005289.c k007232.c k051649.c mos6560.c n63701x.c namco.c nes_defs.h s14001a.c sid6581.c sid6581.h sn76496.h tms5220.h upd7759.c ym2151.c ym2413.c ymf262.c ymf271.c ymf278b.c ymz770.h |
[src/emu/video] | cdp1862.c huc6272.c m50458.c m50458.h mb90082.c mc6845.c pc_vga.c saa5050.c saa5050.h tlc34076.c vector.c |
[src/lib/formats] | ace_tap.h d88_dsk.c flopimg.c xdf_dsk.h |
[src/lib/util] | bitmap.h opresolv.h options.c |
[src/mame/audio] | cage.c exidy440.c flower.c gomoku.c micro3d.c snk6502.c taito_en.c wiping.c |
[src/mame/drivers] | atlantis.c boogwing.c calchase.c carpolo.c chihiro.c circusc.c cobra.c cyclemb.c ddenlovr.c djmain.c finalizr.c firebeat.c funkball.c g627.c galaga.c galaxold.c gamecstl.c gberet.c glass.c goldstar.c gticlub.c guab.c hankin.c homedata.c homerun.c hornet.c jaguar.c jpmmps.c kinst.c konamigx.c konamim2.c lasso.c littlerb.c magictg.c majorpkr.c maygayv1.c mcr.c mediagx.c meritm.c midqslvr.c midvunit.c mrdo.c mrjong.c namcoic.c namcos2.c namcos23.c naomi.c nbmj9195.c nss.c nwk-tr.c pachifev.c panicr.c peplus.c pingpong.c polepos.c pong.c qdrmfgp.c queen.c retofinv.c savquest.c sbugger.c seattle.c segag80r.c segas16b.c segas32.c senjyo.c sfcbox.c sg1000a.c spaceg.c spectra.c sprcros2.c subsino2.c suna8.c taitogn.c taitotz.c taitowlf.c techno.c ttchamp.c tumbleb.c twinkle.c vegas.c vertigo.c viper.c voyager.c xtom3d.c zaxxon.c zn.c |
[src/mame/includes] | armedf.h asuka.h dec0.h deco32.h galaga.h gberet.h gstriker.h homerun.h irobot.h jaguar.h megadriv.h micro3d.h midtunit.h namcoic.h namcos1.h namcos2.h playch10.h qix.h segag80r.h segahang.h snes.h spcforce.h suna8.h suprnova.h vectrex.h vertigo.h zodiack.h |
[src/mame/machine] | atarigen.c cdi070.h decoprot.c kaneko_calc3.c kaneko_calc3.h kaneko_hit.h md_cart.c mega32x.c mega32x.h megacd.c megacd.h megavdp.c pckeybrd.c pxa255.h qix.c segaic16.c segaic16.h seicop.c snes.c snes7110.c snescx4.h snessdd1.c steppers.c stvcd.c |
[src/mame/video] | armedf.c bfm_dm01.c bwing.c dc.c deco16ic.h galaxian.c gp9001.h hng64.c homerun.c jaguar.c kaneko_spr.h konamigx.c konicdev.h legionna.c madalien.c mcd212.h midzeus2.c model2.c model3.c namcona1.c namcos21.c namcos22.c sega16sp.c sega16sp.h segahang.c system16.c taitoic.h vdc.c |
[src/mess/audio] | mea8000.c mos7360.c socrates.c spchroms.h svision.c |
[src/mess/devices] | sonydriv.c |
[src/mess/drivers] | a2600.c aim65.c apollo.c apricot.c apricotp.c bebox.c c128.c c64.c cgenie.c cybiko.c gba.c geneve.c hp49gp.c ht68k.c ip20.c ip22.c juicebox.c mycom.c mz2000.c mz700.c ng_aes.c pc.c pc8801.c pc88va.c pc9801.c pcfx.c pcw16.c pockstat.c psx.c pv1000.c pv2000.c rvoice.c sgi_ip6.c sitcom.c smc777.c ti99_4x.c ti99_8.c vboy.c vic10.c vic20.c vk100.c |
[src/mess/formats] | spec_snqk.h timex_dck.h |
[src/mess/includes] | amstrad.h apple1.h apple2.h apple2gs.h bebox.h c65.h cgenie.h channelf.h compis.h concept.h cxhumax.h cybiko.h dgn_beta.h electron.h fm7.h gamecom.h gb.h gmaster.h gp32.h hp48.h intv.h kyocera.h lisa.h lynx.h mac.h macpci.h mbc55x.h nascom1.h nes.h odyssey2.h oric.h p2000t.h pc8401a.h pce.h pdp1.h pet.h pokemini.h rmnimbus.h spectrum.h ssystem3.h svi318.h svision.h tx0.h vc4000.h vic20.h wswan.h x07.h x1.h z80ne.h |
[src/mess/machine] | 990_hd.c 990_tap.c a2cffa.c amigacrt.c amigakbd.c apollo_net.c applefdc.c at45dbxx.c ay31015.c ay31015.h c128.c c1541.c c64_ide64.c cbmiec.c coco_fdc.h diag264_lb_iec.h diag264_lb_user.h ds1315.c i8271.c i8271.h isa_ide.c isa_sblaster.c isa_stereo_fx.c kay_kbd.c kc_d004.c kr2376.h mc68328.h mc6843.c mc6846.c mc6854.c mos8722.c nes_unif.c petcass.h rmnimbus.c s3c44b0.h sgi.c smartmed.c smc92x4.h strata.c thomson.c upd765.c upd765.h vp620.c wangpc_mvc.c |
[src/mess/machine/ti99] | datamux.h genboard.h grom.h gromport.h joyport.h mapper8.h peribox.h speech8.h ti99_hd.h tn_ide.c videowrp.h |
[src/mess/tools/imgtool] | charconv.h imgterrs.h library.h stream.c |
[src/mess/tools/imgtool/modules] | amiga.c concept.c fat.c mac.c macutil.h os9.c prodos.c ti99.c ti990hd.c vzdos.c |
[src/mess/video] | 733_asr.c 733_asr.h 911_chr.h 911_vdt.c 911_vdt.h apollo.c apple1.c crt.c dl1416.c epnick.c isa_vga_ati.c isa_vga_ati.h mos6566.c newport.c vic4567.h vic6567.h |
[src/osd] | osdnet.h |
[src/tools] | jedutil.c |
r17959 | r17960 | |
---|---|---|
52 | 52 | --> |
53 | 53 | <softwarelist name="coco_cart" description="Tandy Radio Shack Color Computer cartridges"> |
54 | 54 | |
55 | <software name="alphazoo"> | |
55 | <!--software name="alphazoo"> | |
56 | 56 | <description>Alphabet Zoo</description> |
57 | 57 | <year>1984</year> |
58 | 58 | <publisher>Tandy</publisher> |
r17959 | r17960 | |
64 | 64 | <rom name="alphabet zoo (1984)(26-3170)(spinnaker).rom" size="32768" crc="a8a83f53" sha1="b6c8048549c60909c6a9e8e808df342d6491eae2" status="baddump" offset="0" /> |
65 | 65 | </dataarea> |
66 | 66 | </part> |
67 | </software> | |
67 | </software--> | |
68 | 68 | |
69 | 69 | <software name="amazing"> |
70 | 70 | <description>A Mazing World of Malcom Mortar</description> |
r17959 | r17960 | |
---|---|---|
1550 | 1550 | タイトル:メイガス |
1551 | 1551 | メーカー:ソフトプロ 機 種 :FM-7 |
1552 | 1552 | ジャンル:TBL 備 考 :RUN"MAGUS"で起動 |
1553 | ||
1553 | ||
1554 | 1554 | タイトル:リザード |
1555 | 1555 | メーカー:マイクロキャビン 機 種 :FM-7 |
1556 | 1556 | ジャンル:RPG 備 考 :RUN"LIZARD"で起動 |
r17959 | r17960 | |
---|---|---|
7 | 7 | --> |
8 | 8 | |
9 | 9 | <softwarelist name="stv" description="Sega Titan Video cartridges"> |
10 | ||
10 | ||
11 | 11 | <!-- Game: Astra SuperStars --> |
12 | 12 | <software name="astrass" supported="no" > |
13 | 13 | <description>Astra SuperStars (J 980514 V1.002)</description> |
r17959 | r17960 | |
27 | 27 | </dataarea> |
28 | 28 | </part> |
29 | 29 | </software> |
30 | ||
30 | ||
31 | 31 | <!-- Game: Baku Baku Animal --> |
32 | 32 | <software name="bakubaku"> |
33 | 33 | <description>Baku Baku Animal (J 950407 V1.000)</description> |
r17959 | r17960 | |
43 | 43 | </dataarea> |
44 | 44 | </part> |
45 | 45 | </software> |
46 | ||
46 | ||
47 | 47 | <!-- Game: Batman Forever --> |
48 | 48 | <software name="batmanfr" supported="no" > |
49 | 49 | <description>Batman Forever (JUE 960507 V1.000)</description> |
r17959 | r17960 | |
68 | 68 | </dataarea> |
69 | 69 | </part> |
70 | 70 | </software> |
71 | ||
71 | ||
72 | 72 | <!-- Game: Columns '97 --> |
73 | 73 | <software name="colmns97" supported="no"> |
74 | 74 | <description>Columns '97 (JET 961209 V1.000)</description> |
r17959 | r17960 | |
82 | 82 | </dataarea> |
83 | 83 | </part> |
84 | 84 | </software> |
85 | ||
85 | ||
86 | 86 | <!-- Game: Cotton 2 --> |
87 | 87 | <software name="cotton2"> |
88 | 88 | <description>Cotton 2 (JUET 970902 V1.000)</description> |
r17959 | r17960 | |
101 | 101 | </dataarea> |
102 | 102 | </part> |
103 | 103 | </software> |
104 | ||
104 | ||
105 | 105 | <!-- Game: Cotton Boomerang --> |
106 | 106 | <software name="cottonbm" supported="no"> |
107 | 107 | <description>Cotton Boomerang (JUET 980709 V1.000)</description> |
r17959 | r17960 | |
119 | 119 | </dataarea> |
120 | 120 | </part> |
121 | 121 | </software> |
122 | ||
122 | ||
123 | 123 | <!-- Game: Critter Crusher --> |
124 | 124 | <software name="critcrsh" supported="no" > |
125 | 125 | <description>Critter Crusher (EA 951204 V1.000)</description> |
r17959 | r17960 | |
134 | 134 | </dataarea> |
135 | 135 | </part> |
136 | 136 | </software> |
137 | ||
137 | ||
138 | 138 | <!-- Game: Danchi de Hanafuda --> |
139 | 139 | <software name="danchih" supported="no"> |
140 | 140 | <description>Danchi de Hanafuda (J 990607 V1.400)</description> |
r17959 | r17960 | |
150 | 150 | </dataarea> |
151 | 151 | </part> |
152 | 152 | </software> |
153 | ||
153 | ||
154 | 154 | <!-- Game: Danchi de Quiz Okusan Yontaku Desuyo! --> |
155 | 155 | <software name="danchiq" supported="no"> |
156 | 156 | <description>Danchi de Quiz Okusan Yontaku Desuyo! (J 001128 V1.200)</description> |
r17959 | r17960 | |
171 | 171 | </dataarea> |
172 | 172 | </part> |
173 | 173 | </software> |
174 | ||
174 | ||
175 | 175 | <!-- Game: Decathlete --> |
176 | 176 | <software name="decathlt" supported="no"> |
177 | 177 | <description>Decathlete (JUET 960709 V1.001)</description> |
r17959 | r17960 | |
188 | 188 | </dataarea> |
189 | 189 | </part> |
190 | 190 | </software> |
191 | ||
191 | ||
192 | 192 | <!-- Game: Decathlete --> |
193 | 193 | <software name="decathlto" cloneof="decathlt" supported="no"> |
194 | 194 | <description>Decathlete (JUET 960424 V1.000)</description> |
r17959 | r17960 | |
205 | 205 | </dataarea> |
206 | 206 | </part> |
207 | 207 | </software> |
208 | ||
208 | ||
209 | 209 | <!-- Game: Die Hard Arcade --> |
210 | 210 | <software name="diehard"> |
211 | 211 | <description>Die Hard Arcade (UET 960515 V1.000)</description> |
r17959 | r17960 | |
221 | 221 | </dataarea> |
222 | 222 | </part> |
223 | 223 | </software> |
224 | ||
224 | ||
225 | 225 | <!-- Game: Dynamite Deka --> |
226 | 226 | <software name="dnmtdeka" cloneof="diehard"> |
227 | 227 | <description>Dynamite Deka (J 960515 V1.000)</description> |
r17959 | r17960 | |
237 | 237 | </dataarea> |
238 | 238 | </part> |
239 | 239 | </software> |
240 | ||
240 | ||
241 | 241 | <!-- Game: Ejihon Tantei Jimusyo --> |
242 | 242 | <software name="ejihon"> |
243 | 243 | <description>Ejihon Tantei Jimusyo (J 950613 V1.000)</description> |
r17959 | r17960 | |
255 | 255 | </dataarea> |
256 | 256 | </part> |
257 | 257 | </software> |
258 | ||
258 | ||
259 | 259 | <!-- Game: Touryuu Densetsu Elan-Doree / Elan Doree - Legend of Dragoon --> |
260 | 260 | <software name="elandore" supported="no"> |
261 | 261 | <description>Touryuu Densetsu Elan-Doree / Elan Doree - Legend of Dragoon (JUET 980922 V1.006)</description> |
r17959 | r17960 | |
274 | 274 | </dataarea> |
275 | 275 | </part> |
276 | 276 | </software> |
277 | ||
277 | ||
278 | 278 | <!-- Game: Final Fight Revenge --> |
279 | 279 | <software name="ffreveng" supported="no"> |
280 | 280 | <description>Final Fight Revenge (JUET 990714 V1.000)</description> |
r17959 | r17960 | |
292 | 292 | </dataarea> |
293 | 293 | </part> |
294 | 294 | </software> |
295 | ||
295 | ||
296 | 296 | <!-- Game: Funky Head Boxers --> |
297 | 297 | <software name="fhboxers" supported="no" > |
298 | 298 | <description>Funky Head Boxers (JUETBKAL 951218 V1.000)</description> |
r17959 | r17960 | |
313 | 313 | </dataarea> |
314 | 314 | </part> |
315 | 315 | </software> |
316 | ||
316 | ||
317 | 317 | <!-- Game: Find Love --> |
318 | 318 | <software name="findlove" supported="no" > |
319 | 319 | <description>Find Love (J 971212 V1.000)</description> |
r17959 | r17960 | |
337 | 337 | </dataarea> |
338 | 338 | </part> |
339 | 339 | </software> |
340 | ||
340 | ||
341 | 341 | <!-- Game: Final Arch --> |
342 | 342 | <software name="finlarch" cloneof="smleague"> |
343 | 343 | <description>Final Arch (J 950714 V1.001)</description> |
r17959 | r17960 | |
359 | 359 | </dataarea> |
360 | 360 | </part> |
361 | 361 | </software> |
362 | ||
362 | ||
363 | 363 | <!-- Game: Golden Axe - The Duel --> |
364 | 364 | <software name="gaxeduel"> |
365 | 365 | <description>Golden Axe - The Duel (JUETL 950117 V1.000)</description> |
r17959 | r17960 | |
378 | 378 | </dataarea> |
379 | 379 | </part> |
380 | 380 | </software> |
381 | ||
381 | ||
382 | 382 | <!-- Game: Guardian Force --> |
383 | 383 | <software name="grdforce" supported="no"> |
384 | 384 | <description>Guardian Force (JUET 980318 V0.105)</description> |
r17959 | r17960 | |
395 | 395 | </dataarea> |
396 | 396 | </part> |
397 | 397 | </software> |
398 | ||
398 | ||
399 | 399 | <!-- Game: Groove on Fight - Gouketsuji Ichizoku 3 --> |
400 | 400 | <software name="groovef" supported="no"> |
401 | 401 | <description>Groove on Fight - Gouketsuji Ichizoku 3 (J 970416 V1.001)</description> |
r17959 | r17960 | |
415 | 415 | </dataarea> |
416 | 416 | </part> |
417 | 417 | </software> |
418 | ||
418 | ||
419 | 419 | <!-- Game: Hanagumi Taisen Columns - Sakura Wars --> |
420 | 420 | <software name="hanagumi" supported="no"> |
421 | 421 | <description>Hanagumi Taisen Columns - Sakura Wars (J 971007 V1.010)</description> |
r17959 | r17960 | |
438 | 438 | </dataarea> |
439 | 439 | </part> |
440 | 440 | </software> |
441 | ||
441 | ||
442 | 442 | <!-- Game: Karaoke Quiz Intro Don Don! --> |
443 | 443 | <software name="introdon" supported="no"> |
444 | 444 | <description>Karaoke Quiz Intro Don Don! (J 960213 V1.000)</description> |
r17959 | r17960 | |
458 | 458 | </dataarea> |
459 | 459 | </part> |
460 | 460 | </software> |
461 | ||
461 | ||
462 | 462 | <!-- Game: Pro Mahjong Kiwame S --> |
463 | 463 | <!-- Note: you have to init it manually via test mode --> |
464 | 464 | <software name="kiwames"> |
r17959 | r17960 | |
475 | 475 | </dataarea> |
476 | 476 | </part> |
477 | 477 | </software> |
478 | ||
478 | ||
479 | 479 | <!-- Game: Magical Zunou Power --> |
480 | 480 | <software name="magzun" supported="no" > |
481 | 481 | <description>Magical Zunou Power (J 961031 V1.000)</description> |
r17959 | r17960 | |
493 | 493 | </dataarea> |
494 | 494 | </part> |
495 | 495 | </software> |
496 | ||
496 | ||
497 | 497 | <!-- Game: Maru-Chan de Goo! --> |
498 | 498 | <software name="maruchan"> |
499 | 499 | <description>Maru-Chan de Goo! (J 971216 V1.000)</description> |
r17959 | r17960 | |
513 | 513 | </dataarea> |
514 | 514 | </part> |
515 | 515 | </software> |
516 | ||
516 | ||
517 | 517 | <!-- Game: Mausuke no Ojama the World --> |
518 | 518 | <software name="mausuke"> |
519 | 519 | <description>Mausuke no Ojama the World (J 960314 V1.000)</description> |
r17959 | r17960 | |
534 | 534 | </dataarea> |
535 | 535 | </part> |
536 | 536 | </software> |
537 | ||
537 | ||
538 | 538 | <!-- Game: Microman Battle Charge --> |
539 | 539 | <software name="micrombc" supported="no" > |
540 | 540 | <description>Microman Battle Charge (J 990326 V1.000)</description> |
r17959 | r17960 | |
553 | 553 | </dataarea> |
554 | 554 | </part> |
555 | 555 | </software> |
556 | ||
556 | ||
557 | 557 | <!-- Game: Virtual Mahjong 2 - My Fair Lady --> |
558 | 558 | <software name="myfairld" supported="no" > |
559 | 559 | <description>Virtual Mahjong 2 - My Fair Lady (J 980608 V1.000)</description> |
r17959 | r17960 | |
572 | 572 | </dataarea> |
573 | 573 | </part> |
574 | 574 | </software> |
575 | ||
575 | ||
576 | 576 | <!-- Game: Name Club Ver.3 --> |
577 | 577 | <software name="nclubv3" supported="no" > |
578 | 578 | <description>Name Club Ver.3 (J 970723 V1.000)</description> |
r17959 | r17960 | |
593 | 593 | </dataarea> |
594 | 594 | </part> |
595 | 595 | </software> |
596 | ||
596 | ||
597 | 597 | <!-- Game: Othello Shiyouyo --> |
598 | 598 | <software name="othellos" supported="no"> |
599 | 599 | <description>Othello Shiyouyo (J 980423 V1.002)</description> |
r17959 | r17960 | |
609 | 609 | </dataarea> |
610 | 610 | </part> |
611 | 611 | </software> |
612 | ||
612 | ||
613 | 613 | <!-- Game: Pebble Beach - The Great Shot --> |
614 | 614 | <software name="pblbeach"> |
615 | 615 | <description>Pebble Beach - The Great Shot (JUE 950913 V0.990)</description> |
r17959 | r17960 | |
626 | 626 | </dataarea> |
627 | 627 | </part> |
628 | 628 | </software> |
629 | ||
629 | ||
630 | 630 | <!-- Game: Print Club 2 --> |
631 | 631 | <software name="pclub2" supported="no"> |
632 | 632 | <description>Print Club 2 (U 970921 V1.000)</description> |
r17959 | r17960 | |
642 | 642 | </dataarea> |
643 | 643 | </part> |
644 | 644 | </software> |
645 | ||
645 | ||
646 | 646 | <!-- Game: Print Club 2 Vol. 3 --> |
647 | 647 | <software name="pclub2v3" cloneof="pclub2" supported="no"> |
648 | 648 | <description>Print Club 2 Vol. 3 (U 990310 V1.000)</description> |
r17959 | r17960 | |
658 | 658 | </dataarea> |
659 | 659 | </part> |
660 | 660 | </software> |
661 | ||
661 | ||
662 | 662 | <!-- Game: Print Club Pokemon B --> |
663 | 663 | <software name="pclubpok" supported="no"> |
664 | 664 | <description>Print Club Pokemon B (U 991126 V1.000)</description> |
r17959 | r17960 | |
674 | 674 | </dataarea> |
675 | 675 | </part> |
676 | 676 | </software> |
677 | ||
677 | ||
678 | 678 | <!-- Game: Princess Clara Daisakusen --> |
679 | 679 | <software name="prikura"> |
680 | 680 | <description>Princess Clara Daisakusen (J 960910 V1.000)</description> |
r17959 | r17960 | |
690 | 690 | </dataarea> |
691 | 691 | </part> |
692 | 692 | </software> |
693 | ||
693 | ||
694 | 694 | <!-- Game: Puyo Puyo Sun --> |
695 | 695 | <software name="puyosun" supported="no"> |
696 | 696 | <description>Puyo Puyo Sun (J 961115 V0.001)</description> |
r17959 | r17960 | |
711 | 711 | </dataarea> |
712 | 712 | </part> |
713 | 713 | </software> |
714 | ||
714 | ||
715 | 715 | <!-- Game: Radiant Silvergun --> |
716 | 716 | <software name="rsgun" supported="no"> |
717 | 717 | <description>Radiant Silvergun (JUET 980523 V1.000)</description> |
r17959 | r17960 | |
727 | 727 | </dataarea> |
728 | 728 | </part> |
729 | 729 | </software> |
730 | ||
730 | ||
731 | 731 | <!-- Game: Puzzle & Action: Sando-R --> |
732 | 732 | <software name="sandor"> |
733 | 733 | <description>Puzzle & Action: Sando-R (J 951114 V1.000)</description> |
r17959 | r17960 | |
747 | 747 | </dataarea> |
748 | 748 | </part> |
749 | 749 | </software> |
750 | ||
750 | ||
751 | 751 | <!-- Game: DaeJeon! SanJeon SuJeon --> |
752 | 752 | <software name="sanjeon" cloneof="sasissu" supported="no" > |
753 | 753 | <description>DaeJeon! SanJeon SuJeon (AJTUE 990412 V1.000)</description> |
r17959 | r17960 | |
770 | 770 | </dataarea> |
771 | 771 | </part> |
772 | 772 | </software> |
773 | ||
773 | ||
774 | 774 | <!-- Game: Taisen Tanto-R Sashissu!! --> |
775 | 775 | <software name="sasissu" supported="no"> |
776 | 776 | <description>Taisen Tanto-R Sashissu!! (J 980216 V1.000)</description> |
r17959 | r17960 | |
788 | 788 | </dataarea> |
789 | 789 | </part> |
790 | 790 | </software> |
791 | ||
791 | ||
792 | 792 | <!-- Game: Sea Bass Fishing --> |
793 | 793 | <software name="seabass" supported="no" > |
794 | 794 | <description>Sea Bass Fishing (JUET 971110 V0.001)</description> |
r17959 | r17960 | |
808 | 808 | </dataarea> |
809 | 809 | </part> |
810 | 810 | </software> |
811 | ||
811 | ||
812 | 812 | <!-- Game: Shanghai - The Great Wall / Shanghai Triple Threat --> |
813 | 813 | <software name="shanhigw"> |
814 | 814 | <description>Shanghai - The Great Wall / Shanghai Triple Threat (JUE 950623 V1.005)</description> |
r17959 | r17960 | |
821 | 821 | </dataarea> |
822 | 822 | </part> |
823 | 823 | </software> |
824 | ||
824 | ||
825 | 825 | <!-- Game: Shienryu --> |
826 | 826 | <software name="shienryu" supported="no" > |
827 | 827 | <description>Shienryu (JUET 961226 V1.000)</description> |
r17959 | r17960 | |
836 | 836 | </dataarea> |
837 | 837 | </part> |
838 | 838 | </software> |
839 | ||
839 | ||
840 | 840 | <!-- Game: Super Major League --> |
841 | 841 | <software name="smleague"> |
842 | 842 | <description>Super Major League (U 960108 V1.000)</description> |
r17959 | r17960 | |
854 | 854 | </dataarea> |
855 | 855 | </part> |
856 | 856 | </software> |
857 | ||
857 | ||
858 | 858 | <!-- Game: Soukyugurentai / Terra Diver --> |
859 | 859 | <software name="sokyugrt" supported="no" > |
860 | 860 | <description>Soukyugurentai / Terra Diver (JUET 960821 V1.000)</description> |
r17959 | r17960 | |
870 | 870 | </dataarea> |
871 | 871 | </part> |
872 | 872 | </software> |
873 | ||
873 | ||
874 | 874 | <!-- Game: Steep Slope Sliders --> |
875 | 875 | <software name="sss" supported="no" > |
876 | 876 | <description>Steep Slope Sliders (JUET 981110 V1.000)</description> |
r17959 | r17960 | |
888 | 888 | </dataarea> |
889 | 889 | </part> |
890 | 890 | </software> |
891 | ||
891 | ||
892 | 892 | <!-- Game: Stress Busters --> |
893 | 893 | <software name="stress" supported="no" > |
894 | 894 | <description>Stress Busters (J 981020 V1.000)</description> |
r17959 | r17960 | |
910 | 910 | </dataarea> |
911 | 911 | </part> |
912 | 912 | </software> |
913 | ||
913 | ||
914 | 914 | <!-- Game: Suikoenbu / Outlaws of the Lost Dynasty --> |
915 | 915 | <software name="suikoenb"> |
916 | 916 | <description>Suikoenbu / Outlaws of the Lost Dynasty (JUETL 950314 V2.001)</description> |
r17959 | r17960 | |
930 | 930 | </dataarea> |
931 | 931 | </part> |
932 | 932 | </software> |
933 | ||
933 | ||
934 | 934 | <!-- Game: Technical Bowling --> |
935 | 935 | <software name="techbowl" supported="no" > |
936 | 936 | <description>Technical Bowling (J 971212 V1.000)</description> |
r17959 | r17960 | |
946 | 946 | </dataarea> |
947 | 947 | </part> |
948 | 948 | </software> |
949 | ||
949 | ||
950 | 950 | <!-- Game: Puzzle & Action: Treasure Hunt --> |
951 | 951 | <software name="thunt" supported="no" cloneof="sandor"> |
952 | 952 | <description>Puzzle & Action: Treasure Hunt (JUET 970901 V2.00E)</description> |
r17959 | r17960 | |
963 | 963 | </dataarea> |
964 | 964 | </part> |
965 | 965 | </software> |
966 | ||
966 | ||
967 | 967 | <!-- Game: Puzzle & Action: BoMulEul Chajara --> |
968 | 968 | <software name="thuntk" supported="no" cloneof="sandor"> |
969 | 969 | <description>Puzzle & Action: BoMulEul Chajara (JUET 970125 V2.00K)</description> |
r17959 | r17960 | |
984 | 984 | </dataarea> |
985 | 985 | </part> |
986 | 986 | </software> |
987 | ||
987 | ||
988 | 988 | <!-- Game: Tecmo World Cup '98 --> |
989 | 989 | <software name="twcup98" supported="no" > |
990 | 990 | <description>Tecmo World Cup '98 (JUET 980410 V1.000)</description> |
r17959 | r17960 | |
1000 | 1000 | </dataarea> |
1001 | 1001 | </part> |
1002 | 1002 | </software> |
1003 | ||
1003 | ||
1004 | 1004 | <!-- Game: Virtua Fighter Kids --> |
1005 | 1005 | <software name="vfkids" supported="no" > |
1006 | 1006 | <description>Virtua Fighter Kids (JUET 960319 V0.000)</description> |
r17959 | r17960 | |
1021 | 1021 | </dataarea> |
1022 | 1022 | </part> |
1023 | 1023 | </software> |
1024 | ||
1024 | ||
1025 | 1025 | <!-- Game: Virtua Fighter Remix --> |
1026 | 1026 | <software name="vfremix"> |
1027 | 1027 | <description>Virtua Fighter Remix (JUETBKAL 950428 V1.000)</description> |
r17959 | r17960 | |
1039 | 1039 | </dataarea> |
1040 | 1040 | </part> |
1041 | 1041 | </software> |
1042 | ||
1042 | ||
1043 | 1043 | <!-- Game: Virtual Mahjong --> |
1044 | 1044 | <software name="vmahjong" supported="no" > |
1045 | 1045 | <description>Virtual Mahjong (J 961214 V1.000)</description> |
r17959 | r17960 | |
1058 | 1058 | </dataarea> |
1059 | 1059 | </part> |
1060 | 1060 | </software> |
1061 | ||
1061 | ||
1062 | 1062 | <!-- Game: Winter Heat --> |
1063 | 1063 | <software name="winterht" supported="no" > |
1064 | 1064 | <description>Winter Heat (JUET 971012 V1.000)</description> |
r17959 | r17960 | |
1077 | 1077 | </dataarea> |
1078 | 1078 | </part> |
1079 | 1079 | </software> |
1080 | ||
1080 | ||
1081 | 1081 | <!-- Game: Zen Nippon Pro-Wrestling Featuring Virtua --> |
1082 | 1082 | <software name="znpwfv" supported="no" > |
1083 | 1083 | <description>Zen Nippon Pro-Wrestling Featuring Virtua (J 971123 V1.000)</description> |
r17959 | r17960 | |
---|---|---|
6294 | 6294 | <rom name="242-v3.v3" offset="0x800000" size="0x400000" crc="044ea4e1" sha1="062a2f2e52098d73bc31c9ad66f5db8080395ce8" /> <!-- TC5332204 --> |
6295 | 6295 | <rom name="242-v4.v4" offset="0xc00000" size="0x400000" crc="7985ea30" sha1="54ed5f0324de6164ea81943ebccb3e8d298368ec" /> <!-- TC5332204 --> |
6296 | 6296 | </dataarea> |
6297 | ||
6297 | ||
6298 | 6298 | <rom loadflag="load16_byte" name="242-c1.c1" offset="0x000000" size="0x800000" crc="e564ecd6" sha1="78f22787a204f26bae9b2b1c945ddbc27143352f" /> <!-- Plane 0,1 --> <!-- TC5364205 --> |
6299 | 6299 | <rom loadflag="load16_byte" name="242-c2.c2" offset="0x000001" size="0x800000" crc="bd959b60" sha1="2c97c59e77c9a3fe7d664e741d37944f3d56c10b" /> <!-- Plane 2,3 --> <!-- TC5364205 --> |
6300 | 6300 | <rom loadflag="load16_byte" name="242-c3.c3" offset="0x1000000" size="0x800000" crc="22127b4f" sha1="bd0d00f889d9da7c6ac48f287d9ed8c605ae22cf" /> <!-- Plane 0,1 --> <!-- TC5364205 --> |
r17959 | r17960 | |
---|---|---|
48 | 48 | </part> |
49 | 49 | </software> |
50 | 50 | |
51 | <!-- This was was obtained by removing the MTW header from the available jelda.mtw. | |
51 | <!-- This was was obtained by removing the MTW header from the available jelda.mtw. | |
52 | 52 | was any info lost? i.e. was the wav inside the mtw the complete content of the MZ tape? --> |
53 | 53 | <software name="jelda" supported="no"> |
54 | 54 | <description>Jelda</description> |
r17959 | r17960 | |
61 | 61 | </part> |
62 | 62 | </software> |
63 | 63 | |
64 | <!-- This was was obtained by removing the MTW header from the available jelda.mtw. | |
64 | <!-- This was was obtained by removing the MTW header from the available jelda.mtw. | |
65 | 65 | was any info lost? i.e. was the wav inside the mtw the complete content of the MZ tape? --> |
66 | 66 | <software name="jelda2" supported="no"> |
67 | 67 | <description>Jelda 2</description> |
r17959 | r17960 | |
---|---|---|
24730 | 24730 | <!-- End of verified prototypes --> |
24731 | 24731 | |
24732 | 24732 | |
24733 | <!-- Unconfirmed prototypes | |
24733 | <!-- Unconfirmed prototypes | |
24734 | 24734 | ROMs labeled as prototypes without documentation or with doubts on their legitimacy --> |
24735 | 24735 | |
24736 | 24736 | <software name="arcus"> |
r17959 | r17960 | |
---|---|---|
20 | 20 | * |
21 | 21 | *************************************/ |
22 | 22 | |
23 | struct biquad | |
23 | struct biquad | |
24 | 24 | { |
25 | 25 | double a0, a1, a2; /* Numerator coefficients */ |
26 | 26 | double b0, b1, b2; /* Denominator coefficients */ |
27 | 27 | }; |
28 | 28 | |
29 | struct lp_filter | |
29 | struct lp_filter | |
30 | 30 | { |
31 | 31 | float *history; |
32 | 32 | float *coef; |
r17959 | r17960 | |
---|---|---|
34 | 34 | *************************************/ |
35 | 35 | |
36 | 36 | |
37 | struct cage_t | |
37 | struct cage_t | |
38 | 38 | { |
39 | 39 | cpu_device *cpu; |
40 | 40 | attotime cpu_h1_clock_period; |
r17959 | r17960 | |
---|---|---|
19 | 19 | |
20 | 20 | |
21 | 21 | /* this structure defines the parameters for a channel */ |
22 | struct sound_channel | |
22 | struct sound_channel | |
23 | 23 | { |
24 | 24 | int frequency; |
25 | 25 | int counter; |
r17959 | r17960 | |
---|---|---|
19 | 19 | |
20 | 20 | |
21 | 21 | /* this structure defines the parameters for a channel */ |
22 | struct sound_channel | |
22 | struct sound_channel | |
23 | 23 | { |
24 | 24 | int channel; |
25 | 25 | int frequency; |
r17959 | r17960 | |
---|---|---|
284 | 284 | *************************************/ |
285 | 285 | |
286 | 286 | /* |
287 | 68681 I/O pin assignments | |
288 | (according to Gun Buster schematics): | |
287 | 68681 I/O pin assignments | |
288 | (according to Gun Buster schematics): | |
289 | 289 | |
290 | IP0: 5V OP0-OP5: N/C | |
291 | IP1: 5V OP6: ESPHALT | |
292 | IP2: 1MHz OP7: N/C | |
293 | IP3: 0.5MHz | |
294 | IP4: 0.5MHz | |
295 | IP5: 1MHz | |
290 | IP0: 5V OP0-OP5: N/C | |
291 | IP1: 5V OP6: ESPHALT | |
292 | IP2: 1MHz OP7: N/C | |
293 | IP3: 0.5MHz | |
294 | IP4: 0.5MHz | |
295 | IP5: 1MHz | |
296 | 296 | */ |
297 | 297 | static const duart68681_config taito_en_duart68681_config = |
298 | 298 | { |
r17959 | r17960 | |
---|---|---|
20 | 20 | |
21 | 21 | |
22 | 22 | /* this structure defines the parameters for a channel */ |
23 | struct sound_channel | |
23 | struct sound_channel | |
24 | 24 | { |
25 | 25 | UINT32 start; |
26 | 26 | UINT32 pos; |
r17959 | r17960 | |
---|---|---|
29 | 29 | #define FRAC_ONE (1 << FRAC_BITS) |
30 | 30 | #define FRAC_MASK (FRAC_ONE - 1) |
31 | 31 | |
32 | struct TONE | |
32 | struct TONE | |
33 | 33 | { |
34 | 34 | int mute; |
35 | 35 | int offset; |
r17959 | r17960 | |
---|---|---|
38 | 38 | |
39 | 39 | |
40 | 40 | /* channel_data structure holds info about each 6844 DMA channel */ |
41 | struct m6844_channel_data | |
41 | struct m6844_channel_data | |
42 | 42 | { |
43 | 43 | int active; |
44 | 44 | int address; |
r17959 | r17960 | |
50 | 50 | |
51 | 51 | |
52 | 52 | /* channel_data structure holds info about each active sound channel */ |
53 | struct sound_channel_data | |
53 | struct sound_channel_data | |
54 | 54 | { |
55 | 55 | INT16 *base; |
56 | 56 | int offset; |
r17959 | r17960 | |
59 | 59 | |
60 | 60 | |
61 | 61 | /* sound_cache_entry structure contains info on each decoded sample */ |
62 | struct sound_cache_entry | |
62 | struct sound_cache_entry | |
63 | 63 | { |
64 | 64 | struct sound_cache_entry *next; |
65 | 65 | int address; |
r17959 | r17960 | |
71 | 71 | |
72 | 72 | |
73 | 73 | |
74 | struct exidy440_audio_state | |
74 | struct exidy440_audio_state | |
75 | 75 | { |
76 | 76 | UINT8 sound_command; |
77 | 77 | UINT8 sound_command_ack; |
r17959 | r17960 | |
---|---|---|
788 | 788 | |
789 | 789 | static const UINT32 spc7110_months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; |
790 | 790 | |
791 | struct snes_spc7110_t | |
791 | struct snes_spc7110_t | |
792 | 792 | { |
793 | 793 | //================== |
794 | 794 | //decompression unit |
r17959 | r17960 | |
---|---|---|
1 | 1 | /* Kaneko Hit protection */ |
2 | 2 | |
3 | 3 | |
4 | struct calc1_hit_t | |
4 | struct calc1_hit_t | |
5 | 5 | { |
6 | 6 | UINT16 x1p, y1p, x1s, y1s; |
7 | 7 | UINT16 x2p, y2p, x2s, y2s; |
r17959 | r17960 | |
11 | 11 | UINT16 mult_a, mult_b; |
12 | 12 | }; |
13 | 13 | |
14 | struct calc3_hit_t | |
14 | struct calc3_hit_t | |
15 | 15 | { |
16 | 16 | int x1p, y1p, z1p, x1s, y1s, z1s; |
17 | 17 | int x2p, y2p, z2p, x2s, y2s, z2s; |
r17959 | r17960 | |
---|---|---|
224 | 224 | m_lch_pwm(*this, "lch_pwm"), |
225 | 225 | m_rch_pwm(*this, "rch_pwm") |
226 | 226 | { |
227 | ||
227 | ||
228 | 228 | } |
229 | 229 | |
230 | 230 | sega_32x_ntsc_device::sega_32x_ntsc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
231 | 231 | : sega_32x_device(mconfig, tag, owner, clock, SEGA_32X_NTSC) |
232 | 232 | { |
233 | ||
233 | ||
234 | 234 | } |
235 | 235 | |
236 | 236 | sega_32x_pal_device::sega_32x_pal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
237 | 237 | : sega_32x_device(mconfig, tag, owner, clock, SEGA_32X_PAL) |
238 | 238 | { |
239 | ||
239 | ||
240 | 240 | } |
241 | 241 | |
242 | 242 | TIMER_CALLBACK( _32x_pwm_callback ); |
r17959 | r17960 | |
1520 | 1520 | |
1521 | 1521 | AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff) |
1522 | 1522 | AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE16(_32x_68k_palette_r, _32x_68k_palette_w, 0xffffffff) |
1523 | ||
1523 | ||
1524 | 1524 | AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE16(_32x_68k_dram_r, _32x_68k_dram_w, 0xffffffff) |
1525 | 1525 | AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE16(_32x_68k_dram_overwrite_r, _32x_68k_dram_overwrite_w, 0xffffffff) |
1526 | 1526 | |
r17959 | r17960 | |
1735 | 1735 | |
1736 | 1736 | #if 0 |
1737 | 1737 | // for now we just use the regular loading because we have 2 different BIOS roms, and you can't use -bios within a device for obvious reasons |
1738 | ROM_START( 32x ) | |
1738 | ROM_START( 32x ) | |
1739 | 1739 | ROM_REGION( 0x400000, "32x_master_sh2", 0 ) |
1740 | 1740 | ROM_REGION( 0x400000, "32x_slave_sh2", 0 ) |
1741 | 1741 | ROM_END |
r17959 | r17960 | |
1778 | 1778 | MCFG_CPU_PROGRAM_MAP(sh2_main_map) |
1779 | 1779 | MCFG_CPU_CONFIG(sh2_conf_master) |
1780 | 1780 | #endif |
1781 | ||
1781 | ||
1782 | 1782 | MCFG_DAC_ADD("lch_pwm") |
1783 | 1783 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":lspeaker", 0.40) |
1784 | 1784 | |
r17959 | r17960 | |
1805 | 1805 | MCFG_CPU_PROGRAM_MAP(sh2_main_map) |
1806 | 1806 | MCFG_CPU_CONFIG(sh2_conf_master) |
1807 | 1807 | #endif |
1808 | ||
1808 | ||
1809 | 1809 | MCFG_DAC_ADD("lch_pwm") |
1810 | 1810 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":lspeaker", 0.40) |
1811 | 1811 | |
r17959 | r17960 | |
1900 | 1900 | machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15104, 0xa15105, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15104_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15104_w),this)); // 68k BANK rom set |
1901 | 1901 | machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15106, 0xa15107, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15106_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15106_w),this)); // dreq stuff |
1902 | 1902 | machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15108, 0xa15113, read16_delegate(FUNC(sega_32x_device::_32x_dreq_common_r),this), write16_delegate(FUNC(sega_32x_device::_32x_dreq_common_w),this)); // dreq src / dst / length /fifo |
1903 | ||
1903 | ||
1904 | 1904 | machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa1511a, 0xa1511b, read16_delegate(FUNC(sega_32x_device::_32x_68k_a1511a_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a1511a_w),this)); // SEGA TV |
1905 | 1905 | |
1906 | 1906 | machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15120, 0xa1512f, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_commsram_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_commsram_w),this)); // comms reg 0-7 |
r17959 | r17960 | |
---|---|---|
33 | 33 | |
34 | 34 | required_device<dac_device> m_lch_pwm; |
35 | 35 | required_device<dac_device> m_rch_pwm; |
36 | ||
36 | ||
37 | 37 | DECLARE_READ32_MEMBER( _32x_sh2_master_4000_common_4002_r ); |
38 | 38 | DECLARE_READ32_MEMBER( _32x_sh2_slave_4000_common_4002_r ); |
39 | 39 | DECLARE_READ32_MEMBER( _32x_sh2_common_4004_common_4006_r ); |
r17959 | r17960 | |
46 | 46 | DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4014_slave_4016_w ); |
47 | 47 | DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4018_slave_401a_w ); |
48 | 48 | DECLARE_WRITE32_MEMBER( _32x_sh2_slave_401c_slave_401e_w ); |
49 | ||
50 | 49 | |
50 | ||
51 | 51 | DECLARE_READ16_MEMBER( _32x_68k_palette_r ); |
52 | 52 | DECLARE_WRITE16_MEMBER( _32x_68k_palette_w ); |
53 | 53 | DECLARE_READ16_MEMBER( _32x_68k_dram_r ); |
r17959 | r17960 | |
98 | 98 | DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401c_w ); |
99 | 99 | DECLARE_WRITE16_MEMBER( _32x_sh2_master_401e_w ); |
100 | 100 | DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401e_w ); |
101 | ||
101 | ||
102 | 102 | UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline); |
103 | 103 | int sh2_master_pwmint_enable, sh2_slave_pwmint_enable; |
104 | 104 | |
r17959 | r17960 | |
138 | 138 | virtual void device_reset(); |
139 | 139 | |
140 | 140 | // optional information overrides |
141 | // | |
141 | // virtual const rom_entry *device_rom_region() const; | |
142 | 142 | virtual machine_config_constructor device_mconfig_additions() const; |
143 | 143 | private: |
144 | // | |
144 | // virtual void device_config_complete(); | |
145 | 145 | int m_32x_adapter_enabled; |
146 | 146 | int m_32x_access_auth; |
147 | 147 | int m_32x_screenshift; |
r17959 | r17960 | |
---|---|---|
46 | 46 | #define MAX_BLOCKS (200) |
47 | 47 | #define MAX_DIR_SIZE (256*1024) |
48 | 48 | |
49 | struct direntryT | |
49 | struct direntryT | |
50 | 50 | { |
51 | 51 | UINT8 record_size; |
52 | 52 | UINT8 xa_record_size; |
r17959 | r17960 | |
66 | 66 | UINT8 name[128]; |
67 | 67 | }; |
68 | 68 | |
69 | struct filterT | |
69 | struct filterT | |
70 | 70 | { |
71 | 71 | UINT8 mode; |
72 | 72 | UINT8 chan; |
r17959 | r17960 | |
81 | 81 | UINT32 range; |
82 | 82 | }; |
83 | 83 | |
84 | struct blockT | |
84 | struct blockT | |
85 | 85 | { |
86 | 86 | INT32 size; // size of block |
87 | 87 | INT32 FAD; // FAD on disc |
r17959 | r17960 | |
92 | 92 | UINT8 cinf; // coding information |
93 | 93 | }; |
94 | 94 | |
95 | struct partitionT | |
95 | struct partitionT | |
96 | 96 | { |
97 | 97 | INT32 size; |
98 | 98 | blockT *blocks[MAX_BLOCKS]; |
r17959 | r17960 | |
101 | 101 | }; |
102 | 102 | |
103 | 103 | // 16-bit transfer types |
104 | enum transT | |
104 | enum transT | |
105 | 105 | { |
106 | 106 | XFERTYPE_INVALID, |
107 | 107 | XFERTYPE_TOC, |
r17959 | r17960 | |
112 | 112 | }; |
113 | 113 | |
114 | 114 | // 32-bit transfer types |
115 | enum trans32T | |
115 | enum trans32T | |
116 | 116 | { |
117 | 117 | XFERTYPE32_INVALID, |
118 | 118 | XFERTYPE32_GETSECTOR, |
r17959 | r17960 | |
---|---|---|
167 | 167 | |
168 | 168 | #define AT_KEYBOARD_QUEUE_MAXSIZE 256 |
169 | 169 | |
170 | struct at_keyboard | |
170 | struct at_keyboard | |
171 | 171 | { |
172 | 172 | AT_KEYBOARD_TYPE type; |
173 | 173 | int on; |
r17959 | r17960 | |
188 | 188 | |
189 | 189 | static at_keyboard keyboard; |
190 | 190 | |
191 | struct extended_keyboard_code | |
191 | struct extended_keyboard_code | |
192 | 192 | { |
193 | 193 | const char *pressed; |
194 | 194 | const char *released; |
r17959 | r17960 | |
---|---|---|
94 | 94 | deco16_mask=0xffff; |
95 | 95 | decoprot_last_write=decoprot_last_write_val=0; |
96 | 96 | decoprot_buffer_ram_selected=0; |
97 | ||
97 | ||
98 | 98 | deco16_prot_ram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("prot16ram")->ptr()); |
99 | 99 | deco32_prot_ram = reinterpret_cast<UINT32 *>(machine.root_device().memshare("prot32ram")->ptr()); |
100 | 100 |
r17959 | r17960 | |
---|---|---|
19 | 19 | sega_segacd_device::sega_segacd_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type) |
20 | 20 | : device_t(mconfig, type, "sega_segacd_device", tag, owner, clock) |
21 | 21 | { |
22 | ||
22 | ||
23 | 23 | } |
24 | 24 | |
25 | 25 | sega_segacd_us_device::sega_segacd_us_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
26 | 26 | : sega_segacd_device(mconfig, tag, owner, clock, SEGA_SEGACD_US) |
27 | 27 | { |
28 | ||
28 | ||
29 | 29 | } |
30 | 30 | |
31 | 31 | sega_segacd_japan_device::sega_segacd_japan_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
32 | 32 | : sega_segacd_device(mconfig, tag, owner, clock, SEGA_SEGACD_JAPAN) |
33 | 33 | { |
34 | ||
34 | ||
35 | 35 | } |
36 | 36 | |
37 | 37 | sega_segacd_europe_device::sega_segacd_europe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
38 | 38 | : sega_segacd_device(mconfig, tag, owner, clock, SEGA_SEGACD_EUROPE) |
39 | 39 | { |
40 | ||
40 | ||
41 | 41 | } |
42 | 42 | |
43 | 43 | |
r17959 | r17960 | |
2305 | 2305 | void segacd_init_main_cpu( running_machine& machine ) |
2306 | 2306 | { |
2307 | 2307 | address_space* space = machine.device("maincpu")->memory().space(AS_PROGRAM); |
2308 | ||
2308 | ||
2309 | 2309 | segacd_font_bits = reinterpret_cast<UINT16 *>(machine.root_device().memshare(":segacd:segacd_font")->ptr()); |
2310 | 2310 | segacd_backupram = reinterpret_cast<UINT16 *>(machine.root_device().memshare(":segacd:backupram")->ptr()); |
2311 | 2311 | segacd_dataram = reinterpret_cast<UINT16 *>(machine.root_device().memshare(":segacd:dataram")->ptr()); |
2312 | 2312 | segacd_dataram2 = reinterpret_cast<UINT16 *>(machine.root_device().memshare(":segacd:dataram2")->ptr()); |
2313 | 2313 | segacd_4meg_prgram = reinterpret_cast<UINT16 *>(machine.root_device().memshare(":segacd:segacd_program")->ptr()); |
2314 | ||
2314 | ||
2315 | 2315 | segacd_4meg_prgbank = 0; |
2316 | 2316 | |
2317 | 2317 |
r17959 | r17960 | |
---|---|---|
13 | 13 | virtual void device_reset(); |
14 | 14 | |
15 | 15 | // optional information overrides |
16 | // | |
16 | // virtual const rom_entry *device_rom_region() const; | |
17 | 17 | virtual machine_config_constructor device_mconfig_additions() const; |
18 | 18 | private: |
19 | // | |
19 | // virtual void device_config_complete(); | |
20 | 20 | |
21 | 21 | }; |
22 | 22 | |
r17959 | r17960 | |
34 | 34 | public: |
35 | 35 | sega_segacd_japan_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
36 | 36 | protected: |
37 | // | |
37 | // virtual machine_config_constructor device_mconfig_additions() const; | |
38 | 38 | }; |
39 | 39 | |
40 | 40 | class sega_segacd_europe_device : public sega_segacd_device |
r17959 | r17960 | |
42 | 42 | public: |
43 | 43 | sega_segacd_europe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
44 | 44 | protected: |
45 | // | |
45 | // virtual machine_config_constructor device_mconfig_additions() const; | |
46 | 46 | }; |
47 | 47 | |
48 | 48 |
r17959 | r17960 | |
---|---|---|
2657 | 2657 | } |
2658 | 2658 | } |
2659 | 2659 | } |
2660 | ||
2660 | ||
2661 | 2661 | if (!(dat&0x20000)) |
2662 | 2662 | m_render_line_raw[x] = 0x100; |
2663 | 2663 | else |
r17959 | r17960 | |
2819 | 2819 | |
2820 | 2820 | //if (genesis_get_scanline_counter(machine)==0) irq4_on_timer->adjust(attotime::from_usec(2)); |
2821 | 2821 | |
2822 | ||
2822 | ||
2823 | 2823 | if (_32xdev) _32xdev->_32x_scanline_cb1(); |
2824 | 2824 | |
2825 | 2825 |
r17959 | r17960 | |
---|---|---|
163 | 163 | #define PXA255_DCMD_WIDTH_2 (0x00008000) |
164 | 164 | #define PXA255_DCMD_WIDTH_4 (0x0000c000) |
165 | 165 | |
166 | struct PXA255_DMA_Regs | |
166 | struct PXA255_DMA_Regs | |
167 | 167 | { |
168 | 168 | UINT32 dcsr[16]; |
169 | 169 | |
r17959 | r17960 | |
230 | 230 | #define PXA255_SADIV (PXA255_I2S_BASE_ADDR + 0x00000060) |
231 | 231 | #define PXA255_SADR (PXA255_I2S_BASE_ADDR + 0x00000080) |
232 | 232 | |
233 | struct PXA255_I2S_Regs | |
233 | struct PXA255_I2S_Regs | |
234 | 234 | { |
235 | 235 | UINT32 sacr0; |
236 | 236 | UINT32 sacr1; |
r17959 | r17960 | |
279 | 279 | #define PXA255_OIER_E2 (0x00000004) |
280 | 280 | #define PXA255_OIER_E3 (0x00000008) |
281 | 281 | |
282 | struct PXA255_OSTMR_Regs | |
282 | struct PXA255_OSTMR_Regs | |
283 | 283 | { |
284 | 284 | UINT32 osmr[4]; |
285 | 285 | UINT32 oscr; |
r17959 | r17960 | |
331 | 331 | #define PXA255_INT_RTC_HZ (1 << 30) |
332 | 332 | #define PXA255_INT_RTC_ALARM (1 << 31) |
333 | 333 | |
334 | struct PXA255_INTC_Regs | |
334 | struct PXA255_INTC_Regs | |
335 | 335 | { |
336 | 336 | UINT32 icip; |
337 | 337 | UINT32 icmr; |
r17959 | r17960 | |
378 | 378 | #define PXA255_GAFR2_L (PXA255_GPIO_BASE_ADDR + 0x00000064) |
379 | 379 | #define PXA255_GAFR2_U (PXA255_GPIO_BASE_ADDR + 0x00000068) |
380 | 380 | |
381 | struct PXA255_GPIO_Regs | |
381 | struct PXA255_GPIO_Regs | |
382 | 382 | { |
383 | 383 | UINT32 gplr0; // GPIO Pin-Leve |
384 | 384 | UINT32 gplr1; |
r17959 | r17960 | |
476 | 476 | #define PXA255_FIDR1 (PXA255_LCD_BASE_ADDR + 0x00000218) |
477 | 477 | #define PXA255_LDCMD1 (PXA255_LCD_BASE_ADDR + 0x0000021c) |
478 | 478 | |
479 | struct PXA255_LCD_DMA_Regs | |
479 | struct PXA255_LCD_DMA_Regs | |
480 | 480 | { |
481 | 481 | UINT32 fdadr; |
482 | 482 | UINT32 fsadr; |
r17959 | r17960 | |
485 | 485 | emu_timer *eof; |
486 | 486 | }; |
487 | 487 | |
488 | struct PXA255_LCD_Regs | |
488 | struct PXA255_LCD_Regs | |
489 | 489 | { |
490 | 490 | UINT32 lccr0; |
491 | 491 | UINT32 lccr1; |
r17959 | r17960 | |
---|---|---|
1044 | 1044 | /* ST M95320 32Kbit serial EEPROM implementation */ |
1045 | 1045 | |
1046 | 1046 | #define M95320_SIZE 0x1000 |
1047 | enum STMSTATE | |
1047 | enum STMSTATE | |
1048 | 1048 | { |
1049 | 1049 | IDLE = 0, |
1050 | 1050 | CMD_WRSR, |
r17959 | r17960 | |
---|---|---|
70 | 70 | |
71 | 71 | |
72 | 72 | |
73 | struct calc3_t | |
73 | struct calc3_t | |
74 | 74 | { |
75 | 75 | |
76 | 76 | int data_header[2]; |
r17959 | r17960 | |
---|---|---|
3 | 3 | #define CALC3_VERBOSE_OUTPUT 0 |
4 | 4 | |
5 | 5 | |
6 | struct calc3_t | |
6 | struct calc3_t | |
7 | 7 | { |
8 | 8 | int mcu_status; |
9 | 9 | int mcu_command_offset; |
r17959 | r17960 | |
---|---|---|
178 | 178 | } |
179 | 179 | |
180 | 180 | |
181 | struct SDD1_PEM_state | |
181 | struct SDD1_PEM_state | |
182 | 182 | { |
183 | 183 | UINT8 code_num; |
184 | 184 | UINT8 nextIfMPS; |
r17959 | r17960 | |
222 | 222 | { 7,24,22} |
223 | 223 | }; |
224 | 224 | |
225 | struct SDD1_PEM_ContextInfo | |
225 | struct SDD1_PEM_ContextInfo | |
226 | 226 | { |
227 | 227 | UINT8 status; |
228 | 228 | UINT8 MPS; |
r17959 | r17960 | |
---|---|---|
83 | 83 | |
84 | 84 | //------------------------------------------------- |
85 | 85 | // open_bus_r - return value from reading an |
86 | // | |
86 | // unmapped address | |
87 | 87 | //------------------------------------------------- |
88 | 88 | |
89 | 89 | READ16_MEMBER( sega_16bit_common_base::open_bus_r ) |
r17959 | r17960 | |
110 | 110 | |
111 | 111 | //------------------------------------------------- |
112 | 112 | // palette_init - precompute weighted RGB values |
113 | // | |
113 | // for each input value 0-31 | |
114 | 114 | //------------------------------------------------- |
115 | 115 | |
116 | 116 | void sega_16bit_common_base::palette_init() |
117 | 117 | { |
118 | 118 | // |
119 | // | |
119 | // Color generation details | |
120 | 120 | // |
121 | // | |
121 | // Each color is made up of 5 bits, connected through one or more resistors like so: | |
122 | 122 | // |
123 | // Bit 0 = 1 x 3.9K ohm | |
124 | // Bit 1 = 1 x 2.0K ohm | |
125 | // Bit 2 = 1 x 1.0K ohm | |
126 | // Bit 3 = 2 x 1.0K ohm | |
127 | // Bit 4 = 4 x 1.0K ohm | |
123 | // Bit 0 = 1 x 3.9K ohm | |
124 | // Bit 1 = 1 x 2.0K ohm | |
125 | // Bit 2 = 1 x 1.0K ohm | |
126 | // Bit 3 = 2 x 1.0K ohm | |
127 | // Bit 4 = 4 x 1.0K ohm | |
128 | 128 | // |
129 | // Another data bit is connected by a tristate buffer to the color output through a | |
130 | // 470 ohm resistor. The buffer allows the resistor to have no effect (tristate), | |
131 | // halve brightness (pull-down) or double brightness (pull-up). The data bit source | |
132 | // is bit 15 of each color RAM entry. | |
129 | // Another data bit is connected by a tristate buffer to the color output through a | |
130 | // 470 ohm resistor. The buffer allows the resistor to have no effect (tristate), | |
131 | // halve brightness (pull-down) or double brightness (pull-up). The data bit source | |
132 | // is bit 15 of each color RAM entry. | |
133 | 133 | // |
134 | ||
134 | ||
135 | 135 | // compute weight table for regular palette entries |
136 | 136 | static const int resistances_normal[6] = { 3900, 2000, 1000, 1000/2, 1000/4, 0 }; |
137 | 137 | double weights_normal[6]; |
r17959 | r17960 | |
---|---|---|
90 | 90 | |
91 | 91 | // open bus read helpers |
92 | 92 | DECLARE_READ16_MEMBER( open_bus_r ); |
93 | ||
93 | ||
94 | 94 | // palette helpers |
95 | 95 | DECLARE_WRITE16_MEMBER( paletteram_w ); |
96 | 96 | |
r17959 | r17960 | |
102 | 102 | // memory pointers |
103 | 103 | required_shared_ptr<UINT16> m_paletteram; |
104 | 104 | protected: |
105 | ||
105 | ||
106 | 106 | // internal state |
107 | 107 | bool m_open_bus_recurse; // flag to track recursion through open_bus_r |
108 | 108 | UINT32 m_palette_entries; // number of palette entries |
r17959 | r17960 | |
---|---|---|
8 | 8 | |
9 | 9 | ***************************************************************************/ |
10 | 10 | |
11 | struct CX4 | |
11 | struct CX4 | |
12 | 12 | { |
13 | 13 | UINT8 ram[0x0c00]; |
14 | 14 | UINT8 reg[0x0100]; |
r17959 | r17960 | |
---|---|---|
14 | 14 | |
15 | 15 | |
16 | 16 | |
17 | ||
18 | ||
17 | ||
18 | ||
19 | 19 | /************************************* |
20 | 20 | * |
21 | 21 | * Static function prototypes |
r17959 | r17960 | |
501 | 501 | static WRITE8_DEVICE_HANDLER( slither_76489_0_w ) |
502 | 502 | { |
503 | 503 | qix_state *state = device->machine().driver_data<qix_state>(); |
504 | ||
504 | ||
505 | 505 | /* write to the sound chip */ |
506 | 506 | state->m_sn1->write(*device->machine().device<legacy_cpu_device>("maincpu")->space(), 0, data); |
507 | 507 | |
r17959 | r17960 | |
515 | 515 | static WRITE8_DEVICE_HANDLER( slither_76489_1_w ) |
516 | 516 | { |
517 | 517 | qix_state *state = device->machine().driver_data<qix_state>(); |
518 | ||
518 | ||
519 | 519 | /* write to the sound chip */ |
520 | 520 | state->m_sn2->write(*device->machine().device<legacy_cpu_device>("maincpu")->space(), 0, data); |
521 | 521 |
r17959 | r17960 | |
---|---|---|
47 | 47 | |
48 | 48 | /* local vars */ |
49 | 49 | |
50 | struct stepper | |
50 | struct stepper | |
51 | 51 | { |
52 | 52 | const stepper_interface *intf; |
53 | 53 | UINT8 pattern, /* coil pattern */ |
r17959 | r17960 | |
---|---|---|
577 | 577 | break; |
578 | 578 | } |
579 | 579 | |
580 | // | |
580 | // printf("unsupported read: offset == %08x\n", offset); | |
581 | 581 | |
582 | 582 | /* Unsupported reads returns open bus */ |
583 | 583 | // printf("%02x %02x\n",offset,snes_open_bus_r(space, 0)); |
r17959 | r17960 | |
735 | 735 | case MPYM: /* Multiplication result (mid) */ |
736 | 736 | case MPYH: /* Multiplication result (high) */ |
737 | 737 | case RDIO: |
738 | // case RDDIVL: | |
739 | // case RDDIVH: | |
740 | // case RDMPYL: | |
741 | // case RDMPYH: | |
738 | // case RDDIVL: | |
739 | // case RDDIVH: | |
740 | // case RDMPYL: | |
741 | // case RDMPYH: | |
742 | 742 | case JOY1L: |
743 | 743 | case JOY1H: |
744 | 744 | case JOY2L: |
r17959 | r17960 | |
1681 | 1681 | state->m_superfx = machine.device<cpu_device>("superfx"); |
1682 | 1682 | |
1683 | 1683 | state->m_maincpu->space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(snes_state::snes_direct), state)); |
1684 | // | |
1684 | // state->m_soundcpu->space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(snes_state::snes_spc_direct), state)); | |
1685 | 1685 | |
1686 | 1686 | // power-on sets these registers like this |
1687 | 1687 | snes_ram[WRIO] = 0xff; |
1688 | // snes_ram[WRMPYA] = 0xff; | |
1689 | // snes_ram[WRDIVL] = 0xff; | |
1690 | // snes_ram[WRDIVH] = 0xff; | |
1688 | // snes_ram[WRMPYA] = 0xff; | |
1689 | // snes_ram[WRDIVL] = 0xff; | |
1690 | // snes_ram[WRDIVH] = 0xff; | |
1691 | 1691 | |
1692 | 1692 | switch (state->m_has_addon_chip) |
1693 | 1693 | { |
r17959 | r17960 | |
---|---|---|
1537 | 1537 | c1base += gx1->rowbytes(); |
1538 | 1538 | } |
1539 | 1539 | } |
1540 | ||
1541 | // int newdepth = gx0->depth() * gx1->depth(); | |
1540 | ||
1541 | // int newdepth = gx0->depth() * gx1->depth(); | |
1542 | 1542 | int granularity = gx0->granularity(); |
1543 | 1543 | gx0->set_raw_layout(srcdata, gx0->width(), gx0->height(), gx0->elements(), 8 * gx0->width(), 8 * gx0->width() * gx0->height()); |
1544 | 1544 | gx0->set_granularity(granularity); |
r17959 | r17960 | |
---|---|---|
1408 | 1408 | status always 0x8007 (doesn't seem to care) |
1409 | 1409 | raw | amp | scale | sin | cos | |
1410 | 1410 | ------------------------------------------ |
1411 | y | |
1411 | y 0x00 x 0x00000000 0x00000000 (i.e. if amp is 0 then sin/cos are zero too) | |
1412 | 1412 | 0 0x40 0 0x00000000 0x00020000 |
1413 | 1413 | 0 0x40 1 0x00000000 0x00040000 |
1414 | 1414 | 0 0x40 2 0x00000000 0x00080000 |
r17959 | r17960 | |
2058 | 2058 | case (0x03c/2): { cop_43c = data; break; } |
2059 | 2059 | case (0x03e/2): |
2060 | 2060 | /* |
2061 | 0 in all 68k based games | |
2062 | 0xffff in raiden2 / raidendx | |
2063 | 0x2000 in zeroteam / xsedae | |
2064 | it's always setted up just before the 0x474 register | |
2065 | */ | |
2061 | 0 in all 68k based games | |
2062 | 0xffff in raiden2 / raidendx | |
2063 | 0x2000 in zeroteam / xsedae | |
2064 | it's always setted up just before the 0x474 register | |
2065 | */ | |
2066 | 2066 | break; |
2067 | 2067 | |
2068 | 2068 | /* brightness control */ |
r17959 | r17960 | |
2072 | 2072 | /* DMA / layer clearing section */ |
2073 | 2073 | case (0x074/2): |
2074 | 2074 | /* |
2075 | This sets up a DMA mode of some sort | |
2076 | 0x0e00: grainbow, cupsoc | |
2077 | 0x0a00: legionna, godzilla, denjinmk | |
2078 | 0x0600: heatbrl | |
2079 | 0x1e00: zeroteam, xsedae | |
2080 | raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs | |
2081 | (both only uses 0x14 and 0x15 as DMAs) | |
2082 | */ | |
2075 | This sets up a DMA mode of some sort | |
2076 | 0x0e00: grainbow, cupsoc | |
2077 | 0x0a00: legionna, godzilla, denjinmk | |
2078 | 0x0600: heatbrl | |
2079 | 0x1e00: zeroteam, xsedae | |
2080 | raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs | |
2081 | (both only uses 0x14 and 0x15 as DMAs) | |
2082 | */ | |
2083 | 2083 | break; |
2084 | 2084 | |
2085 | 2085 | /* used in palette DMAs, for fading effects */ |
r17959 | r17960 | |
---|---|---|
24 | 24 | |
25 | 25 | #include "emu.h" |
26 | 26 | |
27 | struct scc68070_i2c_regs_t | |
27 | struct scc68070_i2c_regs_t | |
28 | 28 | { |
29 | 29 | UINT8 reserved0; |
30 | 30 | UINT8 data_register; |
r17959 | r17960 | |
47 | 47 | #define ISR_AD0 0x02 // Address Zero |
48 | 48 | #define ISR_LRB 0x01 // Last Received Bit |
49 | 49 | |
50 | struct scc68070_uart_regs_t | |
50 | struct scc68070_uart_regs_t | |
51 | 51 | { |
52 | 52 | UINT8 reserved0; |
53 | 53 | UINT8 mode_register; |
r17959 | r17960 | |
90 | 90 | #define USR_TXRDY 0x04 |
91 | 91 | #define USR_RXRDY 0x01 |
92 | 92 | |
93 | struct scc68070_timer_regs_t | |
93 | struct scc68070_timer_regs_t | |
94 | 94 | { |
95 | 95 | UINT8 timer_status_register; |
96 | 96 | UINT8 timer_control_register; |
r17959 | r17960 | |
130 | 130 | #define TCR_M2_CAPTURE 0x02 |
131 | 131 | #define TCR_M2_COUNT 0x03 |
132 | 132 | |
133 | struct scc68070_dma_channel_t | |
133 | struct scc68070_dma_channel_t | |
134 | 134 | { |
135 | 135 | UINT8 channel_status; |
136 | 136 | UINT8 channel_error; |
r17959 | r17960 | |
193 | 193 | #define CCR_INE 0x08 |
194 | 194 | #define CCR_IPL 0x07 |
195 | 195 | |
196 | struct scc68070_dma_regs_t | |
196 | struct scc68070_dma_regs_t | |
197 | 197 | { |
198 | 198 | scc68070_dma_channel_t channel[2]; |
199 | 199 | }; |
200 | 200 | |
201 | struct scc68070_mmu_desc_t | |
201 | struct scc68070_mmu_desc_t | |
202 | 202 | { |
203 | 203 | UINT16 attr; |
204 | 204 | UINT16 length; |
r17959 | r17960 | |
207 | 207 | UINT16 base; |
208 | 208 | }; |
209 | 209 | |
210 | struct scc68070_mmu_regs_t | |
210 | struct scc68070_mmu_regs_t | |
211 | 211 | { |
212 | 212 | UINT8 status; |
213 | 213 | UINT8 control; |
r17959 | r17960 | |
217 | 217 | scc68070_mmu_desc_t desc[8]; |
218 | 218 | }; |
219 | 219 | |
220 | struct scc68070_regs_t | |
220 | struct scc68070_regs_t | |
221 | 221 | { |
222 | 222 | UINT16 lir; |
223 | 223 | UINT8 picr1; |
r17959 | r17960 | |
---|---|---|
21 | 21 | required_memory_region m_gfxrom; |
22 | 22 | optional_device<williams_cvsd_sound_device> m_cvsd_sound; |
23 | 23 | optional_device<williams_adpcm_sound_device> m_adpcm_sound; |
24 | ||
24 | ||
25 | 25 | DECLARE_WRITE16_MEMBER(midtunit_cmos_enable_w); |
26 | 26 | DECLARE_WRITE16_MEMBER(midtunit_cmos_w); |
27 | 27 | DECLARE_READ16_MEMBER(midtunit_cmos_r); |
r17959 | r17960 | |
---|---|---|
1 | struct hit_t | |
1 | struct hit_t | |
2 | 2 | { |
3 | 3 | UINT16 x1p, y1p, z1p, x1s, y1s, z1s; |
4 | 4 | UINT16 x2p, y2p, z2p, x2s, y2s, z2s; |
r17959 | r17960 | |
---|---|---|
117 | 117 | DECLARE_DRIVER_INIT(megadriv); |
118 | 118 | DECLARE_DRIVER_INIT(megadrij); |
119 | 119 | DECLARE_DRIVER_INIT(mpnew); |
120 | ||
120 | ||
121 | 121 | TILE_GET_INFO_MEMBER( get_stampmap_16x16_1x1_tile_info ); |
122 | 122 | TILE_GET_INFO_MEMBER( get_stampmap_32x32_1x1_tile_info ); |
123 | 123 | TILE_GET_INFO_MEMBER( get_stampmap_16x16_16x16_tile_info ); |
r17959 | r17960 | |
449 | 449 | segacd_state(const machine_config &mconfig, device_type type, const char *tag) |
450 | 450 | : _32x_state(mconfig, type, tag), |
451 | 451 | m_font_bits(*this,"segacd_font") { } |
452 | ||
452 | ||
453 | 453 | required_shared_ptr<UINT16> m_font_bits; |
454 | 454 | }; |
455 | 455 |
r17959 | r17960 | |
---|---|---|
130 | 130 | DECLARE_DRIVER_INIT(dragngun); |
131 | 131 | DECLARE_DRIVER_INIT(lockload); |
132 | 132 | DECLARE_VIDEO_START(dragngun); |
133 | DECLARE_VIDEO_START(lockload); | |
133 | DECLARE_VIDEO_START(lockload); | |
134 | 134 | }; |
135 | 135 | |
136 | 136 |
r17959 | r17960 | |
---|---|---|
12 | 12 | |
13 | 13 | #define MC_LENGTH 512 |
14 | 14 | |
15 | struct am2901 | |
15 | struct am2901 | |
16 | 16 | { |
17 | 17 | UINT32 ram[16]; /* internal ram */ |
18 | 18 | UINT32 d; /* direct data D input */ |
r17959 | r17960 | |
50 | 50 | running_machine *m_machine; |
51 | 51 | }; |
52 | 52 | |
53 | struct microcode | |
53 | struct microcode | |
54 | 54 | { |
55 | 55 | UINT32 x; |
56 | 56 | UINT32 a; |
r17959 | r17960 | |
70 | 70 | UINT32 ma; |
71 | 71 | }; |
72 | 72 | |
73 | struct vproc | |
73 | struct vproc | |
74 | 74 | { |
75 | 75 | UINT16 sram[64]; /* external sram */ |
76 | 76 | UINT16 ramlatch; /* latch between 2901 and sram */ |
r17959 | r17960 | |
---|---|---|
100 | 100 | DECLARE_READ16_MEMBER(sharedram_r); |
101 | 101 | DECLARE_DRIVER_INIT(bigfghtr); |
102 | 102 | DECLARE_MACHINE_START(bigfghtr); |
103 | DECLARE_MACHINE_RESET(bigfghtr); | |
103 | DECLARE_MACHINE_RESET(bigfghtr); | |
104 | 104 | }; |
105 | 105 | |
106 | 106 | /*----------- defined in video/armedf.c -----------*/ |
r17959 | r17960 | |
---|---|---|
39 | 39 | int m_trombank; |
40 | 40 | int m_page; |
41 | 41 | |
42 | TILE_GET_INFO_MEMBER(get_tile_info); | |
42 | TILE_GET_INFO_MEMBER(get_tile_info); | |
43 | 43 | #endif |
44 | 44 | |
45 | 45 | INT16 *m_samplebuf; |
r17959 | r17960 | |
---|---|---|
5 | 5 | |
6 | 6 | #define MAX_VS920A 2 |
7 | 7 | |
8 | struct sVS920A | |
8 | struct sVS920A | |
9 | 9 | { |
10 | 10 | tilemap_t* tmap; |
11 | 11 | UINT16* vram; |
r17959 | r17960 | |
18 | 18 | |
19 | 19 | #define MAX_MB60553 2 |
20 | 20 | |
21 | struct tMB60553 | |
21 | struct tMB60553 | |
22 | 22 | { |
23 | 23 | tilemap_t* tmap; |
24 | 24 | UINT16* vram; |
r17959 | r17960 | |
33 | 33 | |
34 | 34 | #define MAX_CG10103 2 |
35 | 35 | |
36 | struct tCG10103 | |
36 | struct tCG10103 | |
37 | 37 | { |
38 | 38 | UINT16* vram; |
39 | 39 | UINT16 pal_base; |
r17959 | r17960 | |
---|---|---|
16 | 16 | m_videoram(*this, "videoram"), |
17 | 17 | m_sn1(*this, "sn1"), |
18 | 18 | m_sn2(*this, "sn2"){ } |
19 | ||
19 | ||
20 | 20 | required_shared_ptr<UINT8> m_mainram; |
21 | 21 | required_shared_ptr<UINT8> m_videoram; |
22 | ||
22 | ||
23 | 23 | optional_device<sn76496_new_device> m_sn1; |
24 | 24 | optional_device<sn76496_new_device> m_sn2; |
25 | 25 |
r17959 | r17960 | |
---|---|---|
63 | 63 | virtual void machine_start(); |
64 | 64 | virtual void machine_reset(); |
65 | 65 | public: |
66 | virtual void video_start(); | |
66 | virtual void video_start(); | |
67 | 67 | TILE_GET_INFO_MEMBER(get_bg_tile_info); |
68 | 68 | TILE_GET_INFO_MEMBER(get_fg_tile_info); |
69 | 69 | DECLARE_PALETTE_INIT(zodiack); |
r17959 | r17960 | |
---|---|---|
38 | 38 | /* devices */ |
39 | 39 | optional_device<sn76489_new_device> m_sn1; |
40 | 40 | optional_device<sn76489_new_device> m_sn2; |
41 | ||
41 | ||
42 | 42 | /* machine state */ |
43 | 43 | optional_shared_ptr<UINT8> m_68705_port_out; |
44 | 44 | optional_shared_ptr<UINT8> m_68705_ddr; |
r17959 | r17960 | |
---|---|---|
439 | 439 | emu_timer *m_hblank_timer; |
440 | 440 | emu_timer *m_nmi_timer; |
441 | 441 | emu_timer *m_hirq_timer; |
442 | // emu_timer *m_div_timer; | |
443 | // emu_timer *m_mult_timer; | |
442 | // emu_timer *m_div_timer; | |
443 | // emu_timer *m_mult_timer; | |
444 | 444 | emu_timer *m_io_timer; |
445 | 445 | |
446 | 446 | /* DMA/HDMA-related */ |
r17959 | r17960 | |
---|---|---|
94 | 94 | COMBINE_DATA(&m_automat_scroll_regs[offset]); |
95 | 95 | } |
96 | 96 | UINT16 m_automat_scroll_regs[4]; |
97 | ||
97 | ||
98 | 98 | DECLARE_VIDEO_START(automat); |
99 | 99 | }; |
100 | 100 |
r17959 | r17960 | |
---|---|---|
98 | 98 | UINT16 m_serial_frequency; |
99 | 99 | UINT8 m_gpu_irq_state; |
100 | 100 | emu_timer *m_serial_timer; |
101 | ||
101 | ||
102 | 102 | // blitter variables |
103 | 103 | UINT32 m_blitter_regs[40]; |
104 | 104 | UINT16 m_gpu_regs[0x100/2]; |
r17959 | r17960 | |
114 | 114 | static void (jaguar_state::*const bitmap8[8])(UINT16 *, INT32, INT32, UINT32 *, INT32, UINT16 *); |
115 | 115 | static void (jaguar_state::*const bitmap16[8])(UINT16 *, INT32, INT32, UINT32 *, INT32); |
116 | 116 | static void (jaguar_state::*const bitmap32[8])(UINT16 *, INT32, INT32, UINT32 *, INT32); |
117 | ||
117 | ||
118 | 118 | DECLARE_WRITE32_MEMBER(eeprom_w); |
119 | 119 | DECLARE_READ32_MEMBER(eeprom_clk); |
120 | 120 | DECLARE_READ32_MEMBER(eeprom_cs); |
r17959 | r17960 | |
---|---|---|
1 | 1 | #define NAMCOS1_MAX_BANK 0x400 |
2 | 2 | |
3 | 3 | /* Bank handler definitions */ |
4 | struct bankhandler | |
4 | struct bankhandler | |
5 | 5 | { |
6 | 6 | read8_space_func bank_handler_r; |
7 | 7 | write8_space_func bank_handler_w; |
r17959 | r17960 | |
---|---|---|
89 | 89 | DECLARE_PALETTE_INIT(xevious); |
90 | 90 | DECLARE_MACHINE_RESET(xevios); |
91 | 91 | DECLARE_PALETTE_INIT(battles); |
92 | DECLARE_MACHINE_RESET(battles); | |
92 | DECLARE_MACHINE_RESET(battles); | |
93 | 93 | }; |
94 | 94 | |
95 | 95 | |
r17959 | r17960 | |
118 | 118 | TILE_GET_INFO_MEMBER(bg_get_tile_info); |
119 | 119 | TILE_GET_INFO_MEMBER(fg_get_tile_info); |
120 | 120 | DECLARE_VIDEO_START(bosco); |
121 | DECLARE_PALETTE_INIT(bosco); | |
121 | DECLARE_PALETTE_INIT(bosco); | |
122 | 122 | }; |
123 | 123 | |
124 | 124 | class digdug_state : public galaga_state |
r17959 | r17960 | |
143 | 143 | TILE_GET_INFO_MEMBER(bg_get_tile_info); |
144 | 144 | TILE_GET_INFO_MEMBER(tx_get_tile_info); |
145 | 145 | DECLARE_VIDEO_START(digdug); |
146 | DECLARE_PALETTE_INIT(digdug); | |
146 | DECLARE_PALETTE_INIT(digdug); | |
147 | 147 | }; |
148 | 148 | |
149 | 149 |
r17959 | r17960 | |
---|---|---|
101 | 101 | m_c355_obj_gfxbank(0), |
102 | 102 | m_c355_obj_palxor(0) |
103 | 103 | { } |
104 | ||
104 | ||
105 | 105 | // game type helpers |
106 | 106 | bool is_system21(); |
107 | 107 | int m_gametype; |
r17959 | r17960 | |
231 | 231 | DECLARE_DRIVER_INIT(ordyne); |
232 | 232 | DECLARE_DRIVER_INIT(marvland); |
233 | 233 | DECLARE_DRIVER_INIT(rthun2); |
234 | ||
234 | ||
235 | 235 | virtual void video_start(); |
236 | 236 | void video_start_finallap(); |
237 | 237 | void video_start_luckywld(); |
r17959 | r17960 | |
245 | 245 | UINT32 screen_update_sgunner(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); |
246 | 246 | |
247 | 247 | TILE_GET_INFO_MEMBER( roz_tile_info ); |
248 | ||
248 | ||
249 | 249 | DECLARE_READ16_MEMBER( paletteram_word_r ); |
250 | 250 | DECLARE_WRITE16_MEMBER( paletteram_word_w ); |
251 | 251 | DECLARE_WRITE16_MEMBER( rozram_word_w ); |
r17959 | r17960 | |
---|---|---|
17 | 17 | required_shared_ptr<UINT8> m_videoram; |
18 | 18 | required_shared_ptr<UINT8> m_colorram; |
19 | 19 | |
20 | required_device<sn76496_new_device> m_sn1; | |
20 | required_device<sn76496_new_device> m_sn1; | |
21 | 21 | required_device<sn76496_new_device> m_sn2; |
22 | 22 | required_device<sn76496_new_device> m_sn3; |
23 | 23 |
r17959 | r17960 | |
---|---|---|
116 | 116 | virtual void video_reset(); |
117 | 117 | }; |
118 | 118 | |
119 | struct micro3d_vtx | |
119 | struct micro3d_vtx | |
120 | 120 | { |
121 | 121 | INT32 x, y, z; |
122 | 122 | }; |
r17959 | r17960 | |
---|---|---|
1 | struct chr_bank | |
1 | struct chr_bank | |
2 | 2 | { |
3 | 3 | int writable; // 1 for RAM, 0 for ROM |
4 | 4 | UINT8* chr; // direct access to the memory |
r17959 | r17960 | |
---|---|---|
6 | 6 | |
7 | 7 | #define IR_TIMING 1 /* try to emulate MB and VG running time */ |
8 | 8 | |
9 | struct irmb_ops | |
9 | struct irmb_ops | |
10 | 10 | { |
11 | 11 | const struct irmb_ops *nxtop; |
12 | 12 | UINT32 func; |
r17959 | r17960 | |
---|---|---|
142 | 142 | TILE_GET_INFO_MEMBER( get_road_info ); |
143 | 143 | |
144 | 144 | // internal state |
145 | pen_t | |
145 | pen_t | |
146 | 146 | gfx_element * m_gfx; |
147 | 147 | tilemap_t * m_tilemap; |
148 | 148 | UINT16 m_ram[0x20000/2]; // at 0x880000 in Final Lap; at 0xa00000 in Lucky&Wild |
r17959 | r17960 | |
---|---|---|
89 | 89 | DECLARE_DRIVER_INIT(enduror); |
90 | 90 | DECLARE_DRIVER_INIT(endurobl); |
91 | 91 | DECLARE_DRIVER_INIT(endurob2); |
92 | ||
92 | ||
93 | 93 | // video updates |
94 | 94 | UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); |
95 | 95 | |
r17959 | r17960 | |
120 | 120 | required_device<i8255_device> m_i8255_1; |
121 | 121 | required_device<i8255_device> m_i8255_2; |
122 | 122 | required_device<sega_16bit_sprite_device> m_sprites; |
123 | ||
123 | ||
124 | 124 | // memory pointers |
125 | 125 | required_shared_ptr<UINT16> m_workram; |
126 | 126 |
r17959 | r17960 | |
---|---|---|
11 | 11 | |
12 | 12 | #define NVECT 10000 |
13 | 13 | |
14 | struct vectrex_point | |
14 | struct vectrex_point | |
15 | 15 | { |
16 | 16 | int x; int y; |
17 | 17 | rgb_t col; |
r17959 | r17960 | |
---|---|---|
26 | 26 | required_shared_ptr<UINT8> m_spriteram; |
27 | 27 | optional_shared_ptr<UINT8> m_scrollram; |
28 | 28 | optional_shared_ptr<UINT8> m_soundlatch; |
29 | ||
29 | ||
30 | 30 | /* devices */ |
31 | 31 | required_device<sn76489a_new_device> m_sn; |
32 | 32 |
r17959 | r17960 | |
---|---|---|
34 | 34 | int m_gfx_ctrl; |
35 | 35 | int m_scrollx; |
36 | 36 | int m_scrolly; |
37 | ||
37 | ||
38 | 38 | DECLARE_WRITE8_MEMBER(homerun_control_w); |
39 | 39 | DECLARE_WRITE8_MEMBER(homerun_d7756_sample_w); |
40 | 40 | DECLARE_WRITE8_MEMBER(homerun_videoram_w); |
r17959 | r17960 | |
---|---|---|
29 | 29 | /* misc */ |
30 | 30 | int m_adpcm_pos; |
31 | 31 | int m_adpcm_data; |
32 | ||
32 | ||
33 | 33 | optional_shared_ptr<UINT8> m_cadash_shared_ram; |
34 | 34 | |
35 | 35 | /* devices */ |
r17959 | r17960 | |
---|---|---|
24 | 24 | |
25 | 25 | #include "emu.h" |
26 | 26 | |
27 | struct mcd212_channel_t | |
27 | struct mcd212_channel_t | |
28 | 28 | { |
29 | 29 | UINT8 csrr; |
30 | 30 | UINT16 csrw; |
r17959 | r17960 | |
---|---|---|
277 | 277 | |
278 | 278 | void namcona1_state::video_start() |
279 | 279 | { |
280 | static const tilemap_get_info_delegate get_info[4] = { | |
281 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info0),this), | |
282 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info1),this), | |
283 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info2),this), | |
284 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info3),this) | |
280 | static const tilemap_get_info_delegate get_info[4] = { | |
281 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info0),this), | |
282 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info1),this), | |
283 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info2),this), | |
284 | tilemap_get_info_delegate(FUNC(namcona1_state::tilemap_get_info3),this) | |
285 | 285 | }; |
286 | 286 | int i; |
287 | 287 |
r17959 | r17960 | |
---|---|---|
121 | 121 | m_bg_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(armedf_state::get_bg_tile_info),this), TILEMAP_SCAN_COLS, 16, 16, 64, 32); |
122 | 122 | m_fg_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(armedf_state::get_fg_tile_info),this), TILEMAP_SCAN_COLS, 16, 16, 64, 32); |
123 | 123 | |
124 | m_tx_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(armedf_state::get_nb1414m4_tx_tile_info),this), | |
124 | m_tx_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(armedf_state::get_nb1414m4_tx_tile_info),this), | |
125 | 125 | (m_scroll_type == 2) ? tilemap_mapper_delegate(FUNC(armedf_state::armedf_scan_type3),this) : tilemap_mapper_delegate(FUNC(armedf_state::armedf_scan_type2),this), 8, 8, 64, 32); |
126 | 126 | |
127 | 127 | m_bg_tilemap->set_transparent_pen(0xf); |
r17959 | r17960 | |
---|---|---|
20 | 20 | |
21 | 21 | /* the VDC context */ |
22 | 22 | |
23 | struct VDC | |
23 | struct VDC | |
24 | 24 | { |
25 | 25 | int dvssr_write; /* Set when the DVSSR register has been written to */ |
26 | 26 | int physical_width; /* Width of the display */ |
r17959 | r17960 | |
---|---|---|
665 | 665 | { |
666 | 666 | UINT16 *dest = &bitmap.pix(y); |
667 | 667 | UINT16 *src = &sprites.pix(y); |
668 | // | |
668 | // UINT8 *pri = &screen.machine().priority_bitmap.pix(y); | |
669 | 669 | for (int x = rect->min_x; x <= rect->max_x; x++) |
670 | 670 | { |
671 | 671 | // only process written pixels |
r17959 | r17960 | |
673 | 673 | if (pix != 0xffff) |
674 | 674 | { |
675 | 675 | // compare sprite priority against tilemap priority |
676 | // | |
676 | // int priority = (pix >> 12) & 3; | |
677 | 677 | if (1) |
678 | 678 | { |
679 | 679 | // if the color is set to maximum, shadow pixels underneath us |
r17959 | r17960 | |
737 | 737 | { |
738 | 738 | UINT16 *dest = &bitmap.pix(y); |
739 | 739 | UINT16 *src = &sprites.pix(y); |
740 | // | |
740 | // UINT8 *pri = &screen.machine().priority_bitmap.pix(y); | |
741 | 741 | for (int x = rect->min_x; x <= rect->max_x; x++) |
742 | 742 | { |
743 | 743 | // only process written pixels |
r17959 | r17960 | |
745 | 745 | if (pix != 0xffff) |
746 | 746 | { |
747 | 747 | // compare sprite priority against tilemap priority |
748 | // | |
748 | // int priority = (pix >> 12) & 3; | |
749 | 749 | if (1) |
750 | 750 | { |
751 | 751 | // if the color is set to maximum, shadow pixels underneath us |
r17959 | r17960 | |
818 | 818 | { |
819 | 819 | UINT16 *dest = &bitmap.pix(y); |
820 | 820 | UINT16 *src = &sprites.pix(y); |
821 | // | |
821 | // UINT8 *pri = &screen.machine().priority_bitmap.pix(y); | |
822 | 822 | for (int x = rect->min_x; x <= rect->max_x; x++) |
823 | 823 | { |
824 | 824 | // only process written pixels |
r17959 | r17960 | |
826 | 826 | if (pix != 0xffff) |
827 | 827 | { |
828 | 828 | // compare sprite priority against tilemap priority |
829 | // | |
829 | // int priority = (pix >> 12) & 3; | |
830 | 830 | if (1) |
831 | 831 | { |
832 | 832 | // if the color is set to maximum, shadow pixels underneath us |
r17959 | r17960 | |
883 | 883 | { |
884 | 884 | UINT16 *dest = &bitmap.pix(y); |
885 | 885 | UINT16 *src = &sprites.pix(y); |
886 | // | |
886 | // UINT8 *pri = &screen.machine().priority_bitmap.pix(y); | |
887 | 887 | for (int x = rect->min_x; x <= rect->max_x; x++) |
888 | 888 | { |
889 | 889 | // only process written pixels |
r17959 | r17960 | |
891 | 891 | if (pix != 0xffff) |
892 | 892 | { |
893 | 893 | // compare sprite priority against tilemap priority |
894 | // | |
894 | // int priority = (pix >> 12) & 3; | |
895 | 895 | if (1) |
896 | 896 | { |
897 | 897 | // if the color is set to maximum, shadow pixels underneath us |
r17959 | r17960 | |
---|---|---|
112 | 112 | private: |
113 | 113 | // internal state |
114 | 114 | void *m_token; |
115 | ||
115 | ||
116 | 116 | TILE_GET_INFO_MEMBER(pc080sn_get_bg_tile_info); |
117 | 117 | TILE_GET_INFO_MEMBER(pc080sn_get_fg_tile_info); |
118 | 118 | }; |
r17959 | r17960 | |
154 | 154 | private: |
155 | 155 | // internal state |
156 | 156 | void *m_token; |
157 | ||
157 | ||
158 | 158 | TILE_GET_INFO_MEMBER(tc0080vco_get_bg0_tile_info); |
159 | 159 | TILE_GET_INFO_MEMBER(tc0080vco_get_bg1_tile_info); |
160 | TILE_GET_INFO_MEMBER(tc0080vco_get_tx_tile_info); | |
160 | TILE_GET_INFO_MEMBER(tc0080vco_get_tx_tile_info); | |
161 | 161 | }; |
162 | 162 | |
163 | 163 | extern const device_type TC0080VCO; |
r17959 | r17960 | |
178 | 178 | private: |
179 | 179 | // internal state |
180 | 180 | void *m_token; |
181 | ||
181 | ||
182 | 182 | TILE_GET_INFO_MEMBER(tc0100scn_get_bg_tile_info); |
183 | 183 | TILE_GET_INFO_MEMBER(tc0100scn_get_fg_tile_info); |
184 | TILE_GET_INFO_MEMBER(tc0100scn_get_tx_tile_info); | |
184 | TILE_GET_INFO_MEMBER(tc0100scn_get_tx_tile_info); | |
185 | 185 | }; |
186 | 186 | |
187 | 187 | extern const device_type TC0100SCN; |
r17959 | r17960 | |
202 | 202 | private: |
203 | 203 | // internal state |
204 | 204 | void *m_token; |
205 | ||
205 | ||
206 | 206 | TILE_GET_INFO_MEMBER(tc0280grd_get_tile_info); |
207 | 207 | }; |
208 | 208 | |
r17959 | r17960 | |
245 | 245 | private: |
246 | 246 | // internal state |
247 | 247 | void *m_token; |
248 | ||
248 | ||
249 | 249 | TILE_GET_INFO_MEMBER(tc0480scp_get_bg0_tile_info); |
250 | 250 | TILE_GET_INFO_MEMBER(tc0480scp_get_bg1_tile_info); |
251 | 251 | TILE_GET_INFO_MEMBER(tc0480scp_get_bg2_tile_info); |
252 | 252 | TILE_GET_INFO_MEMBER(tc0480scp_get_bg3_tile_info); |
253 | TILE_GET_INFO_MEMBER(tc0480scp_get_tx_tile_info); | |
253 | TILE_GET_INFO_MEMBER(tc0480scp_get_tx_tile_info); | |
254 | 254 | }; |
255 | 255 | |
256 | 256 | extern const device_type TC0480SCP; |
r17959 | r17960 | |
310 | 310 | private: |
311 | 311 | // internal state |
312 | 312 | void *m_token; |
313 | ||
313 | ||
314 | 314 | TILE_GET_INFO_MEMBER(get_bg_tile_info); |
315 | 315 | TILE_GET_INFO_MEMBER(get_fg_tile_info); |
316 | TILE_GET_INFO_MEMBER(get_tx_tile_info); | |
316 | TILE_GET_INFO_MEMBER(get_tx_tile_info); | |
317 | 317 | }; |
318 | 318 | |
319 | 319 | extern const device_type TC0180VCU; |
r17959 | r17960 | |
---|---|---|
554 | 554 | |
555 | 555 | /* the existence of +1 (sprite vs tile layer) is supported by a LOT of games */ |
556 | 556 | const int hoffset = 1; |
557 | ||
557 | ||
558 | 558 | /* 16 of the 256 pixels of the sprites are hard-clipped at the line buffer */ |
559 | 559 | /* according to the schematics, it should be the first 16 pixels */ |
560 | 560 | clip.min_x = MAX(clip.min_x, (!state->m_flipscreen_x) * (16 + hoffset) * GALAXIAN_XSCALE); |
r17959 | r17960 | |
---|---|---|
104 | 104 | * |
105 | 105 | *******************************************/ |
106 | 106 | |
107 | struct plane | |
107 | struct plane | |
108 | 108 | { |
109 | 109 | poly_vertex normal; |
110 | 110 | float distance; |
111 | 111 | }; |
112 | 112 | |
113 | struct texture_parameter | |
113 | struct texture_parameter | |
114 | 114 | { |
115 | 115 | float diffuse; |
116 | 116 | float ambient; |
r17959 | r17960 | |
118 | 118 | float specular_scale; |
119 | 119 | }; |
120 | 120 | |
121 | struct triangle | |
121 | struct triangle | |
122 | 122 | { |
123 | 123 | void * next; |
124 | 124 | poly_vertex v[3]; |
r17959 | r17960 | |
129 | 129 | INT16 center[2]; |
130 | 130 | }; |
131 | 131 | |
132 | struct quad_m2 | |
132 | struct quad_m2 | |
133 | 133 | { |
134 | 134 | poly_vertex v[4]; |
135 | 135 | UINT16 z; |
r17959 | r17960 | |
---|---|---|
150 | 150 | float x, y, w, u, v; |
151 | 151 | } vert; |
152 | 152 | |
153 | struct strip | |
153 | struct strip | |
154 | 154 | { |
155 | 155 | int svert, evert; |
156 | 156 | texinfo ti; |
r17959 | r17960 | |
---|---|---|
77 | 77 | static float zbase; |
78 | 78 | |
79 | 79 | #if TRACK_REG_USAGE |
80 | struct reg_info | |
80 | struct reg_info | |
81 | 81 | { |
82 | 82 | struct reg_info *next; |
83 | 83 | UINT32 value; |
r17959 | r17960 | |
---|---|---|
233 | 233 | |
234 | 234 | /*********************************************************************************************/ |
235 | 235 | |
236 | struct vertex | |
236 | struct vertex | |
237 | 237 | { |
238 | 238 | double x,y; |
239 | 239 | double z; |
240 | 240 | }; |
241 | 241 | |
242 | struct edge | |
242 | struct edge | |
243 | 243 | { |
244 | 244 | double x; |
245 | 245 | double z; |
r17959 | r17960 | |
---|---|---|
12 | 12 | |
13 | 13 | |
14 | 14 | |
15 | struct TRIANGLE | |
15 | struct TRIANGLE | |
16 | 16 | { |
17 | 17 | poly_vertex v[3]; |
18 | 18 | UINT8 texture_x, texture_y; |
r17959 | r17960 | |
---|---|---|
317 | 317 | mClip.scissor.set(0, 639, 0, 479); |
318 | 318 | } |
319 | 319 | |
320 | struct Poly3dVertex | |
320 | struct Poly3dVertex | |
321 | 321 | { |
322 | 322 | float x,y,z; |
323 | 323 | int u,v; /* 0..0xfff */ |
r17959 | r17960 | |
953 | 953 | int power; /* 0.0..1.0 */ |
954 | 954 | } mCamera; |
955 | 955 | |
956 | enum SceneNodeType | |
956 | enum SceneNodeType | |
957 | 957 | { |
958 | 958 | eSCENENODE_NONLEAF, |
959 | 959 | eSCENENODE_QUAD3D, |
r17959 | r17960 | |
---|---|---|
151 | 151 | #define LOG_UNHANDLED_BLITS 0 |
152 | 152 | |
153 | 153 | |
154 | // FIXME: this should be 1, but then MAME performance will be s*** with this | |
154 | // FIXME: this should be 1, but then MAME performance will be s*** with this | |
155 | 155 | // (i.e. it drops the performance from 400% to 6% on an i5 machine). |
156 | // But the PIT irq is definitely needed by some games (for example Pitfall refuses | |
156 | // But the PIT irq is definitely needed by some games (for example Pitfall refuses | |
157 | 157 | // to enter into gameplay without this enabled). |
158 | 158 | const int PIT_MULT_DBG_HACK = 64; |
159 | 159 | |
r17959 | r17960 | |
715 | 715 | case TID_SCANLINE: |
716 | 716 | scanline_update(param); |
717 | 717 | break; |
718 | ||
718 | ||
719 | 719 | case TID_BLITTER_DONE: |
720 | 720 | m_blitter_status = 1; |
721 | 721 | break; |
722 | ||
722 | ||
723 | 723 | case TID_PIT: |
724 | 724 | m_cpu_irq_state |= 4; |
725 | 725 | update_cpu_irq(); |
r17959 | r17960 | |
729 | 729 | timer_set(sample_period, TID_PIT); |
730 | 730 | } |
731 | 731 | break; |
732 | ||
732 | ||
733 | 733 | case TID_SERIAL: |
734 | 734 | serial_update(); |
735 | 735 | break; |
736 | ||
736 | ||
737 | 737 | case TID_GPU_SYNC: |
738 | 738 | // if a command is still pending, and we haven't maxed out our timer, set a new one |
739 | 739 | if (m_gpu_command_pending && param < 1000) |
r17959 | r17960 | |
---|---|---|
41 | 41 | ~deco16ic_device() { global_free(m_token); } |
42 | 42 | |
43 | 43 | // access to legacy token |
44 | void *token() const { assert(m_token != NULL); return m_token; } | |
44 | void *token() const { assert(m_token != NULL); return m_token; } | |
45 | 45 | protected: |
46 | 46 | // device-level overrides |
47 | 47 | virtual void device_config_complete(); |
r17959 | r17960 | |
55 | 55 | TILE_GET_INFO_MEMBER(get_pf2_tile_info); |
56 | 56 | TILE_GET_INFO_MEMBER(get_pf1_tile_info); |
57 | 57 | TILE_GET_INFO_MEMBER(get_pf2_tile_info_b); |
58 | TILE_GET_INFO_MEMBER(get_pf1_tile_info_b); | |
58 | TILE_GET_INFO_MEMBER(get_pf1_tile_info_b); | |
59 | 59 | }; |
60 | 60 | |
61 | 61 | extern const device_type DECO16IC; |
r17959 | r17960 | |
---|---|---|
123 | 123 | |
124 | 124 | static const tilemap_mapper_delegate scan_functions[4] = |
125 | 125 | { |
126 | tilemap_mapper_delegate(FUNC(madalien_state::scan_mode0),this), | |
127 | tilemap_mapper_delegate(FUNC(madalien_state::scan_mode1),this), | |
126 | tilemap_mapper_delegate(FUNC(madalien_state::scan_mode0),this), | |
127 | tilemap_mapper_delegate(FUNC(madalien_state::scan_mode1),this), | |
128 | 128 | tilemap_mapper_delegate(FUNC(madalien_state::scan_mode2),this), |
129 | 129 | tilemap_mapper_delegate(FUNC(madalien_state::scan_mode3),this) |
130 | 130 | }; |
r17959 | r17960 | |
---|---|---|
2 | 2 | |
3 | 3 | Legionnaire / Heated Barrel video hardware (derived from D-Con) |
4 | 4 | |
5 | priority test (preliminary): | |
6 | - OBJ 0 | |
7 | - TXT | |
8 | - OBJ 1 | |
9 | - BK3 | |
10 | - OBJ 2 | |
11 | - MBK | |
12 | - OBJ 3 | |
13 | - LBK | |
5 | priority test (preliminary): | |
6 | - OBJ 0 | |
7 | - TXT | |
8 | - OBJ 1 | |
9 | - BK3 | |
10 | - OBJ 2 | |
11 | - MBK | |
12 | - OBJ 3 | |
13 | - LBK | |
14 | 14 | |
15 | 15 | ***************************************************************************/ |
16 | 16 | |
r17959 | r17960 | |
175 | 175 | m_has_extended_banking = 1; |
176 | 176 | m_has_extended_priority = 0; |
177 | 177 | |
178 | // | |
178 | // m_background_layer->set_transparent_pen(15); | |
179 | 179 | m_midground_layer->set_transparent_pen(15); |
180 | 180 | m_foreground_layer->set_transparent_pen(15); |
181 | 181 | m_text_layer->set_transparent_pen(7);//? |
r17959 | r17960 | |
---|---|---|
52 | 52 | |
53 | 53 | #define LOG(x) do { if (VERBOSE) logerror x; } while (0) |
54 | 54 | |
55 | struct bfmdm01 | |
55 | struct bfmdm01 | |
56 | 56 | { |
57 | 57 | const bfmdm01_interface *intf; |
58 | 58 | int data_avail, |
r17959 | r17960 | |
---|---|---|
137 | 137 | void sega_hangon_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
138 | 138 | { |
139 | 139 | // |
140 | // | |
140 | // Hang On-style sprites | |
141 | 141 | // |
142 | // Offs Bits Usage | |
143 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
144 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
145 | // +2 bbbb---- -------- Sprite bank | |
146 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
147 | // +4 pppppppp pppppppp Signed 16-bit pitch value between scanlines | |
148 | // +6 -ooooooo oooooooo Offset within selected sprite bank | |
149 | // +6 f------- -------- Horizontal flip: read the data backwards if set | |
150 | // +8 --cccccc -------- Sprite color palette | |
151 | // +8 -------- zzzzzz-- Zoom factor | |
152 | // +8 -------- ------pp Sprite priority | |
153 | // +E dddddddd dddddddd Scratch space for current address | |
142 | // Offs Bits Usage | |
143 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
144 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
145 | // +2 bbbb---- -------- Sprite bank | |
146 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
147 | // +4 pppppppp pppppppp Signed 16-bit pitch value between scanlines | |
148 | // +6 -ooooooo oooooooo Offset within selected sprite bank | |
149 | // +6 f------- -------- Horizontal flip: read the data backwards if set | |
150 | // +8 --cccccc -------- Sprite color palette | |
151 | // +8 -------- zzzzzz-- Zoom factor | |
152 | // +8 -------- ------pp Sprite priority | |
153 | // +E dddddddd dddddddd Scratch space for current address | |
154 | 154 | // |
155 | // | |
155 | // Final bitmap format: | |
156 | 156 | // |
157 | // ----pp-- -------- Sprite priority | |
158 | // ------cc cccc---- Sprite color palette | |
159 | // -------- ----llll 4-bit pixel data | |
157 | // ----pp-- -------- Sprite priority | |
158 | // ------cc cccc---- Sprite color palette | |
159 | // -------- ----llll 4-bit pixel data | |
160 | 160 | // |
161 | // | |
161 | // Special notes: | |
162 | 162 | // |
163 | // There is an interaction between the horizonal flip bit and the offset. | |
164 | // The offset is maintained as a 16-bit value, even though only the lower | |
165 | // 15 bits are used for the address. The top bit is used to control flipping. | |
166 | // This means that if the low 15 bits overflow during rendering, the sprite | |
167 | // data will be read backwards after the overflow. This is important to | |
168 | // emulate correctly as many games make use of this feature to render sprites | |
169 | // at the beginning of a bank. | |
163 | // There is an interaction between the horizonal flip bit and the offset. | |
164 | // The offset is maintained as a 16-bit value, even though only the lower | |
165 | // 15 bits are used for the address. The top bit is used to control flipping. | |
166 | // This means that if the low 15 bits overflow during rendering, the sprite | |
167 | // data will be read backwards after the overflow. This is important to | |
168 | // emulate correctly as many games make use of this feature to render sprites | |
169 | // at the beginning of a bank. | |
170 | 170 | // |
171 | 171 | |
172 | 172 | // render the sprites in order |
r17959 | r17960 | |
275 | 275 | break; |
276 | 276 | } |
277 | 277 | } |
278 | ||
278 | ||
279 | 279 | // update bounds |
280 | 280 | if (x > maxx) maxx = x; |
281 | 281 | if (miny == -1) miny = y; |
282 | 282 | maxy = y; |
283 | 283 | } |
284 | 284 | } |
285 | ||
285 | ||
286 | 286 | // mark dirty |
287 | 287 | if (miny != -1) |
288 | 288 | mark_dirty(minx, maxx, miny, maxy); |
r17959 | r17960 | |
313 | 313 | void sega_sharrier_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
314 | 314 | { |
315 | 315 | // |
316 | // | |
316 | // Space Harrier-style sprites | |
317 | 317 | // |
318 | // Offs Bits Usage | |
319 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
320 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
321 | // +2 bbbb---- -------- Sprite bank | |
322 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
323 | // +4 s------- -------- Sprite shadow disable (0=enable, 1=disable) | |
324 | // +4 -p------ -------- Sprite priority | |
325 | // +4 --cccccc -------- Sprite color palette | |
326 | // +4 -------- -ppppppp Signed 7-bit pitch value between scanlines | |
327 | // +6 f------- -------- Horizontal flip: read the data backwards if set | |
328 | // +6 -ooooooo oooooooo Offset within selected sprite bank | |
329 | // +8 --zzzzzz -------- Horizontal zoom factor | |
330 | // +8 -------- --zzzzzz Vertical zoom factor | |
331 | // +E dddddddd dddddddd Scratch space for current address | |
318 | // Offs Bits Usage | |
319 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
320 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
321 | // +2 bbbb---- -------- Sprite bank | |
322 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
323 | // +4 s------- -------- Sprite shadow disable (0=enable, 1=disable) | |
324 | // +4 -p------ -------- Sprite priority | |
325 | // +4 --cccccc -------- Sprite color palette | |
326 | // +4 -------- -ppppppp Signed 7-bit pitch value between scanlines | |
327 | // +6 f------- -------- Horizontal flip: read the data backwards if set | |
328 | // +6 -ooooooo oooooooo Offset within selected sprite bank | |
329 | // +8 --zzzzzz -------- Horizontal zoom factor | |
330 | // +8 -------- --zzzzzz Vertical zoom factor | |
331 | // +E dddddddd dddddddd Scratch space for current address | |
332 | 332 | // |
333 | // | |
333 | // Final bitmap format: | |
334 | 334 | // |
335 | // ----s--- -------- Sprite shadow disable | |
336 | // -----p-- -------- Sprite priority | |
337 | // ------cc cccc---- Sprite color palette | |
338 | // -------- ----llll 4-bit pixel data | |
335 | // ----s--- -------- Sprite shadow disable | |
336 | // -----p-- -------- Sprite priority | |
337 | // ------cc cccc---- Sprite color palette | |
338 | // -------- ----llll 4-bit pixel data | |
339 | 339 | // |
340 | // | |
340 | // Special notes: | |
341 | 341 | // |
342 | // There is an interaction between the horizonal flip bit and the offset. | |
343 | // The offset is maintained as a 16-bit value, even though only the lower | |
344 | // 15 bits are used for the address. The top bit is used to control flipping. | |
345 | // This means that if the low 15 bits overflow during rendering, the sprite | |
346 | // data will be read backwards after the overflow. This is important to | |
347 | // emulate correctly as many games make use of this feature to render sprites | |
348 | // at the beginning of a bank. | |
342 | // There is an interaction between the horizonal flip bit and the offset. | |
343 | // The offset is maintained as a 16-bit value, even though only the lower | |
344 | // 15 bits are used for the address. The top bit is used to control flipping. | |
345 | // This means that if the low 15 bits overflow during rendering, the sprite | |
346 | // data will be read backwards after the overflow. This is important to | |
347 | // emulate correctly as many games make use of this feature to render sprites | |
348 | // at the beginning of a bank. | |
349 | 349 | // |
350 | ||
350 | ||
351 | 351 | // render the sprites in order |
352 | 352 | const UINT32 *spritebase = reinterpret_cast<const UINT32 *>(region()->base()); |
353 | 353 | UINT8 numbanks = region()->bytes() / 0x20000; |
r17959 | r17960 | |
462 | 462 | break; |
463 | 463 | } |
464 | 464 | } |
465 | ||
465 | ||
466 | 466 | // update bounds |
467 | 467 | if (x > maxx) maxx = x; |
468 | 468 | if (miny == -1) miny = y; |
469 | 469 | maxy = y; |
470 | 470 | } |
471 | 471 | } |
472 | ||
472 | ||
473 | 473 | // mark dirty |
474 | 474 | if (miny != -1) |
475 | 475 | mark_dirty(minx, maxx, miny, maxy); |
r17959 | r17960 | |
500 | 500 | void sega_sys16a_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
501 | 501 | { |
502 | 502 | // |
503 | // | |
503 | // System 16A-style sprites | |
504 | 504 | // |
505 | // Offs Bits Usage | |
506 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
507 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
508 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
509 | // +4 pppppppp pppppppp Signed 16-bit pitch value between scanlines | |
510 | // +6 -ooooooo oooooooo Offset within selected sprite bank | |
511 | // +6 f------- -------- Horizontal flip: read the data backwards if set | |
512 | // +8 --cccccc -------- Sprite color palette | |
513 | // +8 -------- -bbb---- Sprite bank | |
514 | // +8 -------- ------pp Sprite priority | |
515 | // +E dddddddd dddddddd Scratch space for current address | |
505 | // Offs Bits Usage | |
506 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
507 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
508 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
509 | // +4 pppppppp pppppppp Signed 16-bit pitch value between scanlines | |
510 | // +6 -ooooooo oooooooo Offset within selected sprite bank | |
511 | // +6 f------- -------- Horizontal flip: read the data backwards if set | |
512 | // +8 --cccccc -------- Sprite color palette | |
513 | // +8 -------- -bbb---- Sprite bank | |
514 | // +8 -------- ------pp Sprite priority | |
515 | // +E dddddddd dddddddd Scratch space for current address | |
516 | 516 | // |
517 | // | |
517 | // Final bitmap format: | |
518 | 518 | // |
519 | // ----pp-- -------- Sprite priority | |
520 | // ------cc cccc---- Sprite color palette | |
521 | // -------- ----llll 4-bit pixel data | |
519 | // ----pp-- -------- Sprite priority | |
520 | // ------cc cccc---- Sprite color palette | |
521 | // -------- ----llll 4-bit pixel data | |
522 | 522 | // |
523 | // | |
523 | // Special notes: | |
524 | 524 | // |
525 | // There is an interaction between the horizonal flip bit and the offset. | |
526 | // The offset is maintained as a 16-bit value, even though only the lower | |
527 | // 15 bits are used for the address. The top bit is used to control flipping. | |
528 | // This means that if the low 15 bits overflow during rendering, the sprite | |
529 | // data will be read backwards after the overflow. This is important to | |
530 | // emulate correctly as many games make use of this feature to render sprites | |
531 | // at the beginning of a bank. | |
525 | // There is an interaction between the horizonal flip bit and the offset. | |
526 | // The offset is maintained as a 16-bit value, even though only the lower | |
527 | // 15 bits are used for the address. The top bit is used to control flipping. | |
528 | // This means that if the low 15 bits overflow during rendering, the sprite | |
529 | // data will be read backwards after the overflow. This is important to | |
530 | // emulate correctly as many games make use of this feature to render sprites | |
531 | // at the beginning of a bank. | |
532 | 532 | // |
533 | 533 | |
534 | 534 | // render the sprites in order |
r17959 | r17960 | |
636 | 636 | break; |
637 | 637 | } |
638 | 638 | } |
639 | ||
639 | ||
640 | 640 | // update bounds |
641 | 641 | if (x > maxx) maxx = x; |
642 | 642 | if (x < minx) minx = x; |
r17959 | r17960 | |
644 | 644 | maxy = y; |
645 | 645 | } |
646 | 646 | } |
647 | ||
647 | ||
648 | 648 | // mark dirty |
649 | 649 | if (miny != -1) |
650 | 650 | mark_dirty(minx, maxx, miny, maxy); |
r17959 | r17960 | |
677 | 677 | |
678 | 678 | //------------------------------------------------- |
679 | 679 | // static_set_remap -- configure sprite address |
680 | // | |
680 | // remapping | |
681 | 681 | //------------------------------------------------- |
682 | 682 | |
683 | 683 | void bootleg_sys16a_sprite_device::static_set_remap(device_t &device, UINT8 offs0, UINT8 offs1, UINT8 offs2, UINT8 offs3, UINT8 offs4, UINT8 offs5, UINT8 offs6, UINT8 offs7) |
r17959 | r17960 | |
701 | 701 | void bootleg_sys16a_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
702 | 702 | { |
703 | 703 | // |
704 | // | |
704 | // Bootleg System 16A-style sprites | |
705 | 705 | // |
706 | // | |
706 | // These are identical to regular System 16A sprites (see above), with two exceptions: | |
707 | 707 | // |
708 | // 1. Addresses within each sprite entry are generally shuffled relative | |
709 | // to the original, and | |
708 | // 1. Addresses within each sprite entry are generally shuffled relative | |
709 | // to the original, and | |
710 | 710 | // |
711 | // 2. The pitch increment happens at the end, not at the beginning of | |
712 | // the loop. | |
711 | // 2. The pitch increment happens at the end, not at the beginning of | |
712 | // the loop. | |
713 | 713 | // |
714 | 714 | |
715 | 715 | // render the sprites in order |
r17959 | r17960 | |
815 | 815 | break; |
816 | 816 | } |
817 | 817 | } |
818 | ||
818 | ||
819 | 819 | // update bounds |
820 | 820 | if (x > maxx) maxx = x; |
821 | 821 | if (x < minx) minx = x; |
r17959 | r17960 | |
826 | 826 | // advance a row - must be done at the end on the bootlegs! |
827 | 827 | addr += pitch; |
828 | 828 | } |
829 | ||
829 | ||
830 | 830 | // mark dirty |
831 | 831 | if (miny != -1) |
832 | 832 | mark_dirty(minx, maxx, miny, maxy); |
r17959 | r17960 | |
848 | 848 | { |
849 | 849 | set_origin(184, 0x00); |
850 | 850 | } |
851 | ||
852 | 851 | |
852 | ||
853 | 853 | //------------------------------------------------- |
854 | 854 | // draw -- render the sprites within the cliprect |
855 | 855 | //------------------------------------------------- |
r17959 | r17960 | |
857 | 857 | void sega_sys16b_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
858 | 858 | { |
859 | 859 | // |
860 | // | |
860 | // System 16B-style sprites | |
861 | 861 | // |
862 | // Offs Bits Usage | |
863 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
864 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
865 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
866 | // +2 ---iiii- -------- Sprite/sprite priority for Y-board | |
867 | // +4 e------- -------- Signify end of sprite list | |
868 | // +4 -h------ -------- Hide this sprite | |
869 | // +4 -------f -------- Horizontal flip: read the data backwards if set | |
870 | // +4 -------- pppppppp Signed 8-bit pitch value between scanlines | |
871 | // +6 oooooooo oooooooo Offset within selected sprite bank | |
872 | // +8 ----bbbb -------- Sprite bank | |
873 | // +8 -------- pp------ Sprite priority, relative to tilemaps | |
874 | // +8 -------- --cccccc Sprite color palette | |
875 | // +A ------vv vvv----- Vertical zoom factor (0 = full size, 0x10 = half size) | |
876 | // +A -------- ---hhhhh Horizontal zoom factor (0 = full size, 0x10 = half size) | |
877 | // +E dddddddd dddddddd Scratch space for current address | |
862 | // Offs Bits Usage | |
863 | // +0 bbbbbbbb -------- Bottom scanline of sprite - 1 | |
864 | // +0 -------- tttttttt Top scanline of sprite - 1 | |
865 | // +2 -------x xxxxxxxx X position of sprite (position $BD is screen position 0) | |
866 | // +2 ---iiii- -------- Sprite/sprite priority for Y-board | |
867 | // +4 e------- -------- Signify end of sprite list | |
868 | // +4 -h------ -------- Hide this sprite | |
869 | // +4 -------f -------- Horizontal flip: read the data backwards if set | |
870 | // +4 -------- pppppppp Signed 8-bit pitch value between scanlines | |
871 | // +6 oooooooo oooooooo Offset within selected sprite bank | |
872 | // +8 ----bbbb -------- Sprite bank | |
873 | // +8 -------- pp------ Sprite priority, relative to tilemaps | |
874 | // +8 -------- --cccccc Sprite color palette | |
875 | // +A ------vv vvv----- Vertical zoom factor (0 = full size, 0x10 = half size) | |
876 | // +A -------- ---hhhhh Horizontal zoom factor (0 = full size, 0x10 = half size) | |
877 | // +E dddddddd dddddddd Scratch space for current address | |
878 | 878 | // |
879 | // | |
879 | // Final bitmap format: | |
880 | 880 | // |
881 | // iiii---- -------- Sprite/sprite priority for Y-board | |
882 | // ----pp-- -------- Sprite priority | |
883 | // ------cc cccc---- Sprite color palette | |
884 | // -------- ----llll 4-bit pixel data | |
881 | // iiii---- -------- Sprite/sprite priority for Y-board | |
882 | // ----pp-- -------- Sprite priority | |
883 | // ------cc cccc---- Sprite color palette | |
884 | // -------- ----llll 4-bit pixel data | |
885 | 885 | // |
886 | // | |
886 | // Note that the zooming described below is 100% accurate to the real board. | |
887 | 887 | // |
888 | 888 | |
889 | 889 | // render the sprites in order |
r17959 | r17960 | |
1008 | 1008 | break; |
1009 | 1009 | } |
1010 | 1010 | } |
1011 | ||
1011 | ||
1012 | 1012 | // update bounds |
1013 | 1013 | if (x > maxx) maxx = x; |
1014 | 1014 | if (x < minx) minx = x; |
r17959 | r17960 | |
1016 | 1016 | maxy = y; |
1017 | 1017 | } |
1018 | 1018 | } |
1019 | ||
1019 | ||
1020 | 1020 | // mark dirty |
1021 | 1021 | if (miny != -1) |
1022 | 1022 | mark_dirty(minx, maxx, miny, maxy); |
r17959 | r17960 | |
1065 | 1065 | void sega_outrun_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
1066 | 1066 | { |
1067 | 1067 | // |
1068 | // | |
1068 | // Out Run/X-Board-style sprites | |
1069 | 1069 | // |
1070 | // Offs Bits Usage | |
1071 | // +0 e------- -------- Signify end of sprite list | |
1072 | // +0 -h-h---- -------- Hide this sprite if either bit is set | |
1073 | // +0 ----bbb- -------- Sprite bank | |
1074 | // +0 -------t tttttttt Top scanline of sprite + 256 | |
1075 | // +2 oooooooo oooooooo Offset within selected sprite bank | |
1076 | // +4 ppppppp- -------- Signed 7-bit pitch value between scanlines | |
1077 | // +4 -------x xxxxxxxx X position of sprite (position $BE is screen position 0) | |
1078 | // +6 -s------ -------- Enable shadows | |
1079 | // +6 --pp---- -------- Sprite priority, relative to tilemaps | |
1080 | // +6 ------vv vvvvvvvv Vertical zoom factor (0x200 = full size, 0x100 = half size, 0x300 = 2x size) | |
1081 | // +8 y------- -------- Render from top-to-bottom (1) or bottom-to-top (0) on screen | |
1082 | // +8 -f------ -------- Horizontal flip: read the data backwards if set | |
1083 | // +8 --x----- -------- Render from left-to-right (1) or right-to-left (0) on screen | |
1084 | // +8 ------hh hhhhhhhh Horizontal zoom factor (0x200 = full size, 0x100 = half size, 0x300 = 2x size) | |
1085 | // +E dddddddd dddddddd Scratch space for current address | |
1070 | // Offs Bits Usage | |
1071 | // +0 e------- -------- Signify end of sprite list | |
1072 | // +0 -h-h---- -------- Hide this sprite if either bit is set | |
1073 | // +0 ----bbb- -------- Sprite bank | |
1074 | // +0 -------t tttttttt Top scanline of sprite + 256 | |
1075 | // +2 oooooooo oooooooo Offset within selected sprite bank | |
1076 | // +4 ppppppp- -------- Signed 7-bit pitch value between scanlines | |
1077 | // +4 -------x xxxxxxxx X position of sprite (position $BE is screen position 0) | |
1078 | // +6 -s------ -------- Enable shadows | |
1079 | // +6 --pp---- -------- Sprite priority, relative to tilemaps | |
1080 | // +6 ------vv vvvvvvvv Vertical zoom factor (0x200 = full size, 0x100 = half size, 0x300 = 2x size) | |
1081 | // +8 y------- -------- Render from top-to-bottom (1) or bottom-to-top (0) on screen | |
1082 | // +8 -f------ -------- Horizontal flip: read the data backwards if set | |
1083 | // +8 --x----- -------- Render from left-to-right (1) or right-to-left (0) on screen | |
1084 | // +8 ------hh hhhhhhhh Horizontal zoom factor (0x200 = full size, 0x100 = half size, 0x300 = 2x size) | |
1085 | // +E dddddddd dddddddd Scratch space for current address | |
1086 | 1086 | // |
1087 | // Out Run only: | |
1088 | // +A hhhhhhhh -------- Height in scanlines - 1 | |
1089 | // +A -------- -ccccccc Sprite color palette | |
1087 | // Out Run only: | |
1088 | // +A hhhhhhhh -------- Height in scanlines - 1 | |
1089 | // +A -------- -ccccccc Sprite color palette | |
1090 | 1090 | // |
1091 | 1091 | // X-Board only: |
1092 | // +A ----hhhh hhhhhhhh Height in scanlines - 1 | |
1093 | // +C -------- cccccccc Sprite color palette | |
1092 | // +A ----hhhh hhhhhhhh Height in scanlines - 1 | |
1093 | // +C -------- cccccccc Sprite color palette | |
1094 | 1094 | // |
1095 | // | |
1095 | // Final bitmap format: | |
1096 | 1096 | // |
1097 | // -s------ -------- Shadow control | |
1098 | // --pp---- -------- Sprite priority | |
1099 | // ----cccc cccc---- Sprite color palette | |
1100 | // -------- ----llll 4-bit pixel data | |
1097 | // -s------ -------- Shadow control | |
1098 | // --pp---- -------- Sprite priority | |
1099 | // ----cccc cccc---- Sprite color palette | |
1100 | // -------- ----llll 4-bit pixel data | |
1101 | 1101 | // |
1102 | 1102 | |
1103 | 1103 | // render the sprites in order |
r17959 | r17960 | |
1214 | 1214 | break; |
1215 | 1215 | } |
1216 | 1216 | } |
1217 | ||
1217 | ||
1218 | 1218 | // update bounds |
1219 | 1219 | if (x > maxx) maxx = x; |
1220 | 1220 | if (x < minx) minx = x; |
r17959 | r17960 | |
1227 | 1227 | addr += pitch * (yacc >> 9); |
1228 | 1228 | yacc &= 0x1ff; |
1229 | 1229 | } |
1230 | ||
1230 | ||
1231 | 1231 | // mark dirty |
1232 | 1232 | if (miny != -1) |
1233 | 1233 | mark_dirty(minx, maxx, miny, maxy); |
r17959 | r17960 | |
1258 | 1258 | void sega_yboard_sprite_device::draw(bitmap_ind16 &bitmap, const rectangle &cliprect) |
1259 | 1259 | { |
1260 | 1260 | // |
1261 | // | |
1261 | // Y-Board-style sprites | |
1262 | 1262 | // |
1263 | // Offs Bits Usage | |
1264 | // +0 e------- -------- Signify end of sprite list | |
1265 | // +0 -----iii iiiiiiii Address of indirection table (/16) | |
1266 | // +2 bbbb---- -------- Upper 4 bits of bank index | |
1267 | // +2 ----xxxx xxxxxxxx X position of sprite (position $600 is screen position 0) | |
1268 | // +4 bbbb---- -------- Lower 4 bits of bank index | |
1269 | // +4 ----yyyy yyyyyyyy Y position of sprite (position $600 is screen position 0) | |
1270 | // +6 oooooooo oooooooo Offset within selected sprite bank | |
1271 | // +8 hhhhhhhh hhhhhhhh Height of sprite | |
1272 | // +A -y------ -------- Render from top-to-bottom (1) or bottom-to-top (0) on screen | |
1273 | // +A --f----- -------- Horizontal flip: read the data backwards if set | |
1274 | // +A ---x---- -------- Render from left-to-right (1) or right-to-left (0) on screen | |
1275 | // +A -----zzz zzzzzzzz Zoom factor | |
1276 | // +C -ccc---- -------- Sprite color | |
1277 | // +C ----rrrr -------- Sprite priority | |
1278 | // +C -------- pppppppp Signed 8-bit pitch value between scanlines | |
1279 | // +E ----nnnn nnnnnnnn Index of next sprite | |
1263 | // Offs Bits Usage | |
1264 | // +0 e------- -------- Signify end of sprite list | |
1265 | // +0 -----iii iiiiiiii Address of indirection table (/16) | |
1266 | // +2 bbbb---- -------- Upper 4 bits of bank index | |
1267 | // +2 ----xxxx xxxxxxxx X position of sprite (position $600 is screen position 0) | |
1268 | // +4 bbbb---- -------- Lower 4 bits of bank index | |
1269 | // +4 ----yyyy yyyyyyyy Y position of sprite (position $600 is screen position 0) | |
1270 | // +6 oooooooo oooooooo Offset within selected sprite bank | |
1271 | // +8 hhhhhhhh hhhhhhhh Height of sprite | |
1272 | // +A -y------ -------- Render from top-to-bottom (1) or bottom-to-top (0) on screen | |
1273 | // +A --f----- -------- Horizontal flip: read the data backwards if set | |
1274 | // +A ---x---- -------- Render from left-to-right (1) or right-to-left (0) on screen | |
1275 | // +A -----zzz zzzzzzzz Zoom factor | |
1276 | // +C -ccc---- -------- Sprite color | |
1277 | // +C ----rrrr -------- Sprite priority | |
1278 | // +C -------- pppppppp Signed 8-bit pitch value between scanlines | |
1279 | // +E ----nnnn nnnnnnnn Index of next sprite | |
1280 | 1280 | // |
1281 | // | |
1281 | // Final bitmap format: | |
1282 | 1282 | // |
1283 | // ccc----- -------- Sprite color | |
1284 | // ---rrrr- -------- Sprite priority | |
1285 | // -------i iiiiiiii Indirected color data | |
1283 | // ccc----- -------- Sprite color | |
1284 | // ---rrrr- -------- Sprite priority | |
1285 | // -------i iiiiiiii Indirected color data | |
1286 | 1286 | // |
1287 | // In addition to these parameters, the sprite area is clipped using scanline extents | |
1288 | // stored for every pair of scanlines in the rotation RAM. It's a bit of a cheat for us | |
1289 | // to poke our nose into the rotation structure, but there are no known cases of Y-board | |
1290 | // sprites without rotation RAM. | |
1287 | // In addition to these parameters, the sprite area is clipped using scanline extents | |
1288 | // stored for every pair of scanlines in the rotation RAM. It's a bit of a cheat for us | |
1289 | // to poke our nose into the rotation structure, but there are no known cases of Y-board | |
1290 | // sprites without rotation RAM. | |
1291 | 1291 | // |
1292 | 1292 | |
1293 | 1293 | // clear out any scanlines we might be using |
r17959 | r17960 | |
1439 | 1439 | break; |
1440 | 1440 | } |
1441 | 1441 | } |
1442 | ||
1442 | ||
1443 | 1443 | // update bounds |
1444 | 1444 | if (x > dmaxx) dmaxx = x; |
1445 | 1445 | if (x < dminx) dminx = x; |
r17959 | r17960 | |
1453 | 1453 | addr += pitch * (yacc >> 9); |
1454 | 1454 | yacc &= 0x1ff; |
1455 | 1455 | } |
1456 | ||
1456 | ||
1457 | 1457 | // mark dirty |
1458 | 1458 | if (dminy != -1) |
1459 | 1459 | mark_dirty(dminx, dmaxx, dminy, dmaxy); |
r17959 | r17960 | |
---|---|---|
72 | 72 | |
73 | 73 | #define MCFG_BOOTLEG_SYS16A_SPRITES_ADD(_tag) \ |
74 | 74 | MCFG_DEVICE_ADD(_tag, BOOTLEG_SYS16A_SPRITES, 0) \ |
75 | ||
75 | ||
76 | 76 | #define MCFG_BOOTLEG_SYS16A_SPRITES_REMAP(_0,_1,_2,_3,_4,_5,_6,_7) \ |
77 | 77 | bootleg_sys16a_sprite_device::static_set_remap(*device, _0,_1,_2,_3,_4,_5,_6,_7); |
78 | ||
78 | ||
79 | 79 | #define MCFG_BOOTLEG_SYS16A_SPRITES_XORIGIN(_xorigin) \ |
80 | 80 | bootleg_sys16a_sprite_device::static_set_xorigin(*device, _xorigin); |
81 | 81 | |
r17959 | r17960 | |
85 | 85 | |
86 | 86 | #define MCFG_BOOTLEG_SYS16B_SPRITES_ADD(_tag) \ |
87 | 87 | MCFG_DEVICE_ADD(_tag, SEGA_SYS16B_SPRITES, 0) \ |
88 | ||
88 | ||
89 | 89 | #define MCFG_BOOTLEG_SYS16B_SPRITES_XORIGIN(_xorigin) \ |
90 | 90 | bootleg_sys16a_sprite_device::static_set_xorigin(*device, _xorigin); |
91 | 91 | |
r17959 | r17960 | |
129 | 129 | public: |
130 | 130 | // construction/destruction |
131 | 131 | sega_hangon_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
132 | ||
132 | ||
133 | 133 | protected: |
134 | 134 | // subclass overrides |
135 | 135 | virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect); |
r17959 | r17960 | |
143 | 143 | public: |
144 | 144 | // construction/destruction |
145 | 145 | sega_sharrier_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
146 | ||
146 | ||
147 | 147 | protected: |
148 | 148 | // subclass overrides |
149 | 149 | virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect); |
r17959 | r17960 | |
162 | 162 | |
163 | 163 | // subclass overrides |
164 | 164 | virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect); |
165 | ||
165 | ||
166 | 166 | // configuration |
167 | 167 | bool m_is_xboard; |
168 | 168 | }; |
r17959 | r17960 | |
196 | 196 | public: |
197 | 197 | // construction/destruction |
198 | 198 | bootleg_sys16a_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
199 | ||
199 | ||
200 | 200 | // configuration |
201 | 201 | static void static_set_remap(device_t &device, UINT8 offs0, UINT8 offs1, UINT8 offs2, UINT8 offs3, UINT8 offs4, UINT8 offs5, UINT8 offs6, UINT8 offs7); |
202 | 202 | |
203 | 203 | protected: |
204 | 204 | // subclass overrides |
205 | 205 | virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect); |
206 | ||
206 | ||
207 | 207 | // internal state |
208 | 208 | UINT8 m_addrmap[8]; |
209 | 209 | }; |
r17959 | r17960 | |
216 | 216 | public: |
217 | 217 | // construction/destruction |
218 | 218 | sega_sys16b_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
219 | ||
219 | ||
220 | 220 | protected: |
221 | 221 | // subclass overrides |
222 | 222 | virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect); |
r17959 | r17960 | |
230 | 230 | public: |
231 | 231 | // construction/destruction |
232 | 232 | sega_yboard_sprite_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
233 | ||
233 | ||
234 | 234 | protected: |
235 | 235 | // subclass overrides |
236 | 236 | virtual void draw(bitmap_ind16 &bitmap, const rectangle &cliprect); |
r17959 | r17960 | |
---|---|---|
180 | 180 | private: |
181 | 181 | // internal state |
182 | 182 | void *m_token; |
183 | ||
183 | ||
184 | 184 | TILEMAP_MAPPER_MEMBER(k007342_scan); |
185 | 185 | TILE_GET_INFO_MEMBER(k007342_get_tile_info0); |
186 | 186 | TILE_GET_INFO_MEMBER(k007342_get_tile_info1); |
r17959 | r17960 | |
224 | 224 | private: |
225 | 225 | // internal state |
226 | 226 | void *m_token; |
227 | ||
227 | ||
228 | 228 | TILE_GET_INFO_MEMBER(k052109_get_tile_info0); |
229 | 229 | TILE_GET_INFO_MEMBER(k052109_get_tile_info1); |
230 | 230 | TILE_GET_INFO_MEMBER(k052109_get_tile_info2); |
r17959 | r17960 | |
330 | 330 | private: |
331 | 331 | // internal state |
332 | 332 | void *m_token; |
333 | ||
333 | ||
334 | 334 | TILE_GET_INFO_MEMBER(k051316_get_tile_info0); |
335 | 335 | }; |
336 | 336 | |
r17959 | r17960 | |
549 | 549 | private: |
550 | 550 | // internal state |
551 | 551 | void *m_token; |
552 | ||
552 | ||
553 | 553 | TILEMAP_MAPPER_MEMBER(k001604_scan_layer_8x8_0_size0); |
554 | 554 | TILEMAP_MAPPER_MEMBER(k001604_scan_layer_8x8_0_size1); |
555 | 555 | TILEMAP_MAPPER_MEMBER(k001604_scan_layer_8x8_1_size0); |
r17959 | r17960 | |
582 | 582 | private: |
583 | 583 | // internal state |
584 | 584 | void *m_token; |
585 | ||
585 | ||
586 | 586 | TILE_GET_INFO_MEMBER(k037122_tile_info_layer0); |
587 | 587 | TILE_GET_INFO_MEMBER(k037122_tile_info_layer1); |
588 | 588 | }; |
r17959 | r17960 | |
---|---|---|
355 | 355 | static void K053936GP_1_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect, |
356 | 356 | tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output) |
357 | 357 | { |
358 | // konamigx_state *state = machine.driver_data<konamigx_state>(); | |
359 | // K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output); | |
358 | // konamigx_state *state = machine.driver_data<konamigx_state>(); | |
359 | // K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output); | |
360 | 360 | } |
361 | 361 | |
362 | 362 |
r17959 | r17960 | |
---|---|---|
101 | 101 | UINT16 *dest = &bitmap.pix(y); |
102 | 102 | UINT16 *src = &sprites.pix(y); |
103 | 103 | UINT8 *pri = &machine().priority_bitmap.pix(y); |
104 | ||
104 | ||
105 | 105 | // hangon mixing |
106 | 106 | if (!m_sharrier_video) |
107 | 107 | { |
r17959 | r17960 | |
126 | 126 | } |
127 | 127 | } |
128 | 128 | } |
129 | ||
129 | ||
130 | 130 | // sharrier mixing |
131 | 131 | else |
132 | 132 | { |
r17959 | r17960 | |
---|---|---|
681 | 681 | } |
682 | 682 | |
683 | 683 | /* internal set of transparency states for rendering */ |
684 | enum hng64trans_t | |
684 | enum hng64trans_t | |
685 | 685 | { |
686 | 686 | HNG64_TILEMAP_NORMAL = 1, |
687 | 687 | HNG64_TILEMAP_ADDITIVE, |
r17959 | r17960 | |
---|---|---|
32 | 32 | WRITE8_DEVICE_HANDLER(homerun_banking_w) |
33 | 33 | { |
34 | 34 | homerun_state *state = device->machine().driver_data<homerun_state>(); |
35 | ||
35 | ||
36 | 36 | // games do mid-screen gfx bank switching |
37 | 37 | int vpos = device->machine().primary_screen->vpos(); |
38 | 38 | device->machine().primary_screen->update_partial(vpos); |
39 | ||
39 | ||
40 | 40 | // d0-d1: gfx bank |
41 | 41 | // d2-d4: ? |
42 | 42 | // d5-d7: prg bank |
r17959 | r17960 | |
56 | 56 | m_colorram[offset] = data; |
57 | 57 | |
58 | 58 | /* from PCB photo: |
59 | bit 7: 470 ohm resistor \ | |
60 | bit 6: 220 ohm resistor - --> 470 ohm resistor --> blue | |
61 | bit 5: 470 ohm resistor \ | |
62 | bit 4: 220 ohm resistor - --> 470 ohm resistor --> green | |
63 | bit 3: 1 kohm resistor / | |
64 | bit 2: 470 ohm resistor \ | |
65 | bit 1: 220 ohm resistor - --> 470 ohm resistor --> red | |
66 | bit 0: 1 kohm resistor / | |
67 | */ | |
59 | bit 7: 470 ohm resistor \ | |
60 | bit 6: 220 ohm resistor - --> 470 ohm resistor --> blue | |
61 | bit 5: 470 ohm resistor \ | |
62 | bit 4: 220 ohm resistor - --> 470 ohm resistor --> green | |
63 | bit 3: 1 kohm resistor / | |
64 | bit 2: 470 ohm resistor \ | |
65 | bit 1: 220 ohm resistor - --> 470 ohm resistor --> red | |
66 | bit 0: 1 kohm resistor / | |
67 | */ | |
68 | 68 | |
69 | 69 | // let's implement it the old fashioned way until it's found out how exactly the resnet is hooked up |
70 | 70 | int r, g, b; |
r17959 | r17960 | |
124 | 124 | color, |
125 | 125 | flipx,flipy, |
126 | 126 | sx,sy,0); |
127 | ||
127 | ||
128 | 128 | // wraparound |
129 | 129 | drawgfx_transpen(bitmap, cliprect, machine.gfx[1], |
130 | 130 | code, |
r17959 | r17960 | |
---|---|---|
195 | 195 | |
196 | 196 | void bwing_state::video_start() |
197 | 197 | { |
198 | // | |
198 | // UINT32 *dwptr; | |
199 | 199 | int i; |
200 | 200 | |
201 | 201 | m_charmap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(bwing_state::get_charinfo),this), TILEMAP_SCAN_COLS, 8, 8, 32, 32); |
r17959 | r17960 | |
225 | 225 | // m_bgfx = machine().gfx[3]; |
226 | 226 | machine().gfx[3]->set_source(m_srbase[1] + 0x1000); |
227 | 227 | /* |
228 | WTF?? | |
229 | ||
230 | dwptr = machine().gfx[2]->pen_usage(); | |
231 | if (dwptr) | |
232 | { | |
233 | dwptr[0] = 0; | |
234 | for(i = 1; i < BW_NTILES; i++) | |
235 | dwptr[i] = -1; | |
236 | } | |
228 | WTF?? | |
229 | ||
230 | dwptr = machine().gfx[2]->pen_usage(); | |
231 | if (dwptr) | |
232 | { | |
233 | dwptr[0] = 0; | |
234 | for(i = 1; i < BW_NTILES; i++) | |
235 | dwptr[i] = -1; | |
236 | } | |
237 | 237 | */ |
238 | 238 | } |
239 | 239 |
r17959 | r17960 | |
---|---|---|
11 | 11 | |
12 | 12 | |
13 | 13 | |
14 | struct kaneko16_priority_t | |
14 | struct kaneko16_priority_t | |
15 | 15 | { |
16 | 16 | int sprite[4]; |
17 | 17 | }; |
r17959 | r17960 | |
---|---|---|
72 | 72 | |
73 | 73 | address_space_config m_space_config; |
74 | 74 | UINT8 m_gfxregion; |
75 | ||
75 | ||
76 | 76 | TILE_GET_INFO_MEMBER(get_top0_tile_info); |
77 | 77 | TILE_GET_INFO_MEMBER(get_fg0_tile_info); |
78 | TILE_GET_INFO_MEMBER(get_bg0_tile_info); | |
78 | TILE_GET_INFO_MEMBER(get_bg0_tile_info); | |
79 | 79 | }; |
80 | 80 | |
81 | 81 | extern const device_type GP9001_VDP; |
r17959 | r17960 | |
---|---|---|
228 | 228 | * Sound interface |
229 | 229 | * |
230 | 230 | *************************************/ |
231 | ||
232 | ||
231 | ||
232 | ||
233 | 233 | //------------------------------------------------- |
234 | 234 | // sn76496_config psg_intf |
235 | 235 | //------------------------------------------------- |
r17959 | r17960 | |
265 | 265 | MCFG_SOUND_ADD("sn76489.1", SN76489_NEW, 3000000) |
266 | 266 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
267 | 267 | MCFG_SOUND_CONFIG(psg_intf) |
268 | ||
268 | ||
269 | 269 | MCFG_SOUND_ADD("sn76489.2", SN76489_NEW, 3000000) |
270 | 270 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
271 | 271 | MCFG_SOUND_CONFIG(psg_intf) |
r17959 | r17960 | |
---|---|---|
1177 | 1177 | static ADDRESS_MAP_START( shabdama_map, AS_PROGRAM, 8, nbmj9195_state ) |
1178 | 1178 | AM_RANGE(0x0000, 0x7fff) AM_ROM |
1179 | 1179 | AM_RANGE(0xe000, 0xe7ff) AM_RAM |
1180 | // AM_RANGE(0xd000, 0xd1ff) AM_READWRITE(nbmj9195_palette_r,nbmj9195_palette_w) | |
1181 | // AM_RANGE(0xd800, 0xdfff) AM_RAM | |
1180 | // AM_RANGE(0xd000, 0xd1ff) AM_READWRITE(nbmj9195_palette_r,nbmj9195_palette_w) | |
1181 | // AM_RANGE(0xd800, 0xdfff) AM_RAM | |
1182 | 1182 | ADDRESS_MAP_END |
1183 | 1183 | |
1184 | 1184 | static ADDRESS_MAP_START( shabdama_io_map, AS_IO, 8, nbmj9195_state ) |
1185 | // | |
1185 | // ADDRESS_MAP_UNMAP_HIGH | |
1186 | 1186 | ADDRESS_MAP_GLOBAL_MASK(0xff) |
1187 | 1187 | AM_IMPORT_FROM( tmpz84c011_regs ) |
1188 | 1188 | |
1189 | // AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r) | |
1190 | // AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w) | |
1191 | // AM_RANGE(0x70, 0x7f) AM_WRITE(nbmj9195_clut_0_w) | |
1189 | // AM_RANGE(0x60, 0x61) AM_READ(nbmj9195_blitter_0_r) | |
1190 | // AM_RANGE(0x60, 0x6f) AM_WRITE(nbmj9195_blitter_0_w) | |
1191 | // AM_RANGE(0x70, 0x7f) AM_WRITE(nbmj9195_clut_0_w) | |
1192 | 1192 | ADDRESS_MAP_END |
1193 | 1193 | |
1194 | 1194 | /******************************************************************************** |
r17959 | r17960 | |
---|---|---|
979 | 979 | |
980 | 980 | static const voodoo_config hornet_voodoo_intf = |
981 | 981 | { |
982 | 2, // fbmem; | |
983 | 4,// tmumem0; | |
984 | 0,// tmumem1; | |
985 | "screen",// screen; | |
986 | "dsp",// cputag; | |
987 | voodoo_vblank_0,// vblank; | |
988 | NULL,// stall; | |
982 | 2, // fbmem; | |
983 | 4,// tmumem0; | |
984 | 0,// tmumem1; | |
985 | "screen",// screen; | |
986 | "dsp",// cputag; | |
987 | voodoo_vblank_0,// vblank; | |
988 | NULL,// stall; | |
989 | 989 | }; |
990 | 990 | |
991 | 991 | static MACHINE_CONFIG_START( hornet, hornet_state ) |
r17959 | r17960 | |
1058 | 1058 | |
1059 | 1059 | static const voodoo_config voodoo_l_intf = |
1060 | 1060 | { |
1061 | 2, // fbmem; | |
1062 | 4,// tmumem0; | |
1063 | 0,// tmumem1; | |
1064 | "lscreen",// screen; | |
1065 | "dsp",// cputag; | |
1066 | voodoo_vblank_0,// vblank; | |
1067 | NULL,// stall; | |
1061 | 2, // fbmem; | |
1062 | 4,// tmumem0; | |
1063 | 0,// tmumem1; | |
1064 | "lscreen",// screen; | |
1065 | "dsp",// cputag; | |
1066 | voodoo_vblank_0,// vblank; | |
1067 | NULL,// stall; | |
1068 | 1068 | }; |
1069 | 1069 | |
1070 | 1070 | static const voodoo_config voodoo_r_intf = |
1071 | 1071 | { |
1072 | 2, // fbmem; | |
1073 | 4,// tmumem0; | |
1074 | 0,// tmumem1; | |
1075 | "rscreen",// screen; | |
1076 | "dsp2",// cputag; | |
1077 | voodoo_vblank_1,// vblank; | |
1078 | NULL,// stall; | |
1072 | 2, // fbmem; | |
1073 | 4,// tmumem0; | |
1074 | 0,// tmumem1; | |
1075 | "rscreen",// screen; | |
1076 | "dsp2",// cputag; | |
1077 | voodoo_vblank_1,// vblank; | |
1078 | NULL,// stall; | |
1079 | 1079 | }; |
1080 | 1080 | |
1081 | 1081 | static MACHINE_CONFIG_DERIVED( hornet_2board, hornet ) |
r17959 | r17960 | |
---|---|---|
1151 | 1151 | 0 |
1152 | 1152 | }; |
1153 | 1153 | |
1154 | static const ide_config ide_intf = | |
1154 | static const ide_config ide_intf = | |
1155 | 1155 | { |
1156 | ide_interrupt, | |
1157 | NULL, | |
1156 | ide_interrupt, | |
1157 | NULL, | |
1158 | 1158 | 0 |
1159 | 1159 | }; |
1160 | 1160 |
r17959 | r17960 | |
---|---|---|
223 | 223 | GFXDECODE_ENTRY( "gfx3", 0, alphalayout, 12*2+2*16, 4 ) |
224 | 224 | GFXDECODE_END |
225 | 225 | |
226 | static const ttl74148_config carpolo_ttl74148_intf = | |
226 | static const ttl74148_config carpolo_ttl74148_intf = | |
227 | 227 | { |
228 | 228 | carpolo_74148_3s_cb |
229 | 229 | }; |
230 | 230 | |
231 | static const ttl74153_config carpolo_ttl74153_intf = | |
231 | static const ttl74153_config carpolo_ttl74153_intf = | |
232 | 232 | { |
233 | 233 | NULL |
234 | 234 | }; |
r17959 | r17960 | |
---|---|---|
196 | 196 | WRITE8_MEMBER( sfcbox_state::port_80_w ) |
197 | 197 | { |
198 | 198 | /* |
199 | x--- ---- (often same as bit5) | |
200 | -x-- ---- Unknown/unused | |
201 | --x- ---- ?? PLENTY used (often same as bit7) | |
202 | ---x ---- ?? pulsed while [C094] is nonzero (0370h timer0 steps) | |
203 | ---- x--- Unknown/unused | |
204 | ---- -x-- SNES Transfer DATA to SNES (Bit1 of WRIO/RDIO on SNES side) | |
205 | ---- --x- SNES Transfer CLOCK to SNES (Bit5 of WRIO/RDIO on SNES side) | |
206 | ---- ---x SNES Transfer STAT to SNES (Bit2 of WRIO/RDIO on SNES side) | |
199 | x--- ---- (often same as bit5) | |
200 | -x-- ---- Unknown/unused | |
201 | --x- ---- ?? PLENTY used (often same as bit7) | |
202 | ---x ---- ?? pulsed while [C094] is nonzero (0370h timer0 steps) | |
203 | ---- x--- Unknown/unused | |
204 | ---- -x-- SNES Transfer DATA to SNES (Bit1 of WRIO/RDIO on SNES side) | |
205 | ---- --x- SNES Transfer CLOCK to SNES (Bit5 of WRIO/RDIO on SNES side) | |
206 | ---- ---x SNES Transfer STAT to SNES (Bit2 of WRIO/RDIO on SNES side) | |
207 | 207 | */ |
208 | 208 | snes_ram[WRIO] = ((data & 4) >> 1) | (snes_ram[WRIO] & ~0x02); // DATA |
209 | 209 | snes_ram[WRIO] = ((data & 2) << 4) | (snes_ram[WRIO] & ~0x20); // CLOCK |
r17959 | r17960 | |
214 | 214 | READ8_MEMBER( sfcbox_state::port_81_r ) |
215 | 215 | { |
216 | 216 | /* |
217 | x--- ---- Vblank, Vsync, or Whatever flag (must toggle on/off at whatever speed) | |
218 | -x-- ---- Int1 Request (Joypad is/was accessed by SNES or so?) (0=IRQ, 1=No) | |
219 | --x- ---- Unknown/unused ;/(for "joy2/slot1" or so, use [A0].4-5) | |
220 | ---x ---- Unknown/unused ;\joy1/slot0 or so, used by an UNUSED function (08A0h) | |
221 | ---- x--- Boot mode or so (maybe a jumper, or watchdog-flag, or Bit0 of WRIO/RDIO?) | |
222 | ---- -x-- SNES Transfer DATA from SNES (Bit4 of WRIO/RDIO on SNES side) | |
223 | ---- --x- SNES Transfer ACK from SNES (Bit3 of WRIO/RDIO on SNES side) | |
224 | ---- ---x Int0 Request (Coin-Input, Low for 44ms..80ms) (0=IRQ, 1=No) | |
217 | x--- ---- Vblank, Vsync, or Whatever flag (must toggle on/off at whatever speed) | |
218 | -x-- ---- Int1 Request (Joypad is/was accessed by SNES or so?) (0=IRQ, 1=No) | |
219 | --x- ---- Unknown/unused ;/(for "joy2/slot1" or so, use [A0].4-5) | |
220 | ---x ---- Unknown/unused ;\joy1/slot0 or so, used by an UNUSED function (08A0h) | |
221 | ---- x--- Boot mode or so (maybe a jumper, or watchdog-flag, or Bit0 of WRIO/RDIO?) | |
222 | ---- -x-- SNES Transfer DATA from SNES (Bit4 of WRIO/RDIO on SNES side) | |
223 | ---- --x- SNES Transfer ACK from SNES (Bit3 of WRIO/RDIO on SNES side) | |
224 | ---- ---x Int0 Request (Coin-Input, Low for 44ms..80ms) (0=IRQ, 1=No) | |
225 | 225 | */ |
226 | 226 | UINT8 res; |
227 | 227 | |
r17959 | r17960 | |
285 | 285 | AM_RANGE(0x00, 0x3f) AM_RAM // internal i/o |
286 | 286 | AM_RANGE(0x80, 0x80) AM_READ_PORT("KEY") AM_WRITE(port_80_w) // Keyswitch and Button Inputs / SNES Transfer and Misc Output |
287 | 287 | AM_RANGE(0x81, 0x81) AM_READWRITE(port_81_r,port_81_w) // SNES Transfer and Misc Input / Misc Output |
288 | // | |
288 | // AM_RANGE(0x82, 0x82) // Unknown/unused | |
289 | 289 | AM_RANGE(0x83, 0x83) AM_READWRITE(port_83_r,port_83_w) // Joypad Input/Status / Joypad Output/Control |
290 | // AM_RANGE(0x84, 0x84) // Joypad 1, MSB (1st 8 bits) (eg. Bit7=ButtonB, 0=Low=Pressed) | |
291 | // AM_RANGE(0x85, 0x85) // Joypad 1, LSB (2nd 8 bits) (eg. Bit0=LSB of ID, 0=Low=One) | |
292 | // AM_RANGE(0x86, 0x86) // Joypad 2, MSB (1st 8 bits) (eg. Bit7=ButtonB, 0=Low=Pressed) | |
290 | // AM_RANGE(0x84, 0x84) // Joypad 1, MSB (1st 8 bits) (eg. Bit7=ButtonB, 0=Low=Pressed) | |
291 | // AM_RANGE(0x85, 0x85) // Joypad 1, LSB (2nd 8 bits) (eg. Bit0=LSB of ID, 0=Low=One) | |
292 | // AM_RANGE(0x86, 0x86) // Joypad 2, MSB (1st 8 bits) (eg. Bit7=ButtonB, 0=Low=Pressed) | |
293 | 293 | // AM_RANGE(0x87, 0x87) // Joypad 2, LSB (2nd 8 bits) (eg. Bit0=LSB of ID, 0=Low=One) |
294 | 294 | AM_RANGE(0xa0, 0xa0) AM_READ_PORT("RTC_R") AM_WRITE_PORT("RTC_W") // Real Time Clock |
295 | 295 | AM_RANGE(0xc0, 0xc0) AM_WRITE(snes_map_0_w) // SNES Mapping Register 0 |
r17959 | r17960 | |
500 | 500 | MCFG_SCREEN_ADD("osd", RASTER) |
501 | 501 | MCFG_SCREEN_REFRESH_RATE(60) |
502 | 502 | MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) |
503 | // MCFG_SCREEN_SIZE(24*12+22, 12*18+22) | |
504 | // MCFG_SCREEN_VISIBLE_AREA(0*8, 24*12-1, 0*8, 12*18-1) | |
503 | // MCFG_SCREEN_SIZE(24*12+22, 12*18+22) | |
504 | // MCFG_SCREEN_VISIBLE_AREA(0*8, 24*12-1, 0*8, 12*18-1) | |
505 | 505 | MCFG_SCREEN_SIZE(24*16+22, 12*16+22) |
506 | 506 | MCFG_SCREEN_VISIBLE_AREA(0*8, 24*16-1, 0*8, 12*16-1) |
507 | 507 | MCFG_SCREEN_UPDATE_DRIVER(sfcbox_state,screen_update) |
r17959 | r17960 | |
---|---|---|
1532 | 1532 | machine().device("ide")->reset(); |
1533 | 1533 | } |
1534 | 1534 | |
1535 | static const ide_config ide_intf = | |
1535 | static const ide_config ide_intf = | |
1536 | 1536 | { |
1537 | atpsx_interrupt, | |
1538 | NULL, | |
1537 | atpsx_interrupt, | |
1538 | NULL, | |
1539 | 1539 | 0 |
1540 | 1540 | }; |
1541 | 1541 | |
r17959 | r17960 | |
2213 | 2213 | MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1000a ) |
2214 | 2214 | MACHINE_CONFIG_END |
2215 | 2215 | |
2216 | static const ide_config jdredd_ide_intf = | |
2216 | static const ide_config jdredd_ide_intf = | |
2217 | 2217 | { |
2218 | jdredd_ide_interrupt, | |
2219 | NULL, | |
2218 | jdredd_ide_interrupt, | |
2219 | NULL, | |
2220 | 2220 | 0 |
2221 | 2221 | }; |
2222 | 2222 |
r17959 | r17960 | |
---|---|---|
110 | 110 | INPUT_PORTS_END |
111 | 111 | |
112 | 112 | |
113 | static const ttl74148_config vertigo_ttl74148_intf = | |
113 | static const ttl74148_config vertigo_ttl74148_intf = | |
114 | 114 | { |
115 | 115 | vertigo_update_irq |
116 | 116 | }; |
r17959 | r17960 | |
---|---|---|
939 | 939 | * Sound interface |
940 | 940 | * |
941 | 941 | *************************************/ |
942 | ||
943 | ||
942 | ||
943 | ||
944 | 944 | //------------------------------------------------- |
945 | 945 | // sn76496_config psg_intf |
946 | 946 | //------------------------------------------------- |
r17959 | r17960 | |
1040 | 1040 | MCFG_SOUND_ADD("sn1", SN76496_NEW, SOUND_CLOCK) |
1041 | 1041 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
1042 | 1042 | MCFG_SOUND_CONFIG(psg_intf) |
1043 | ||
1043 | ||
1044 | 1044 | MCFG_SOUND_ADD("sn2", SN76496_NEW, SOUND_CLOCK/4) |
1045 | 1045 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
1046 | 1046 | MCFG_SOUND_CONFIG(psg_intf) |
r17959 | r17960 | |
---|---|---|
1981 | 1981 | AM_RANGE(0x6000, 0x6fff) AM_RAM // RAM |
1982 | 1982 | AM_RANGE(0x7000, 0x7fff) AM_RAMBANK("bank2") // RAM (Banked) |
1983 | 1983 | AM_RANGE(0x8000, 0xffff) AM_ROMBANK("bank1") // ROM (Banked) |
1984 | AM_RANGE(0x8000, 0x81ff) AM_WRITE(rongrong_palette_w) | |
1984 | AM_RANGE(0x8000, 0x81ff) AM_WRITE(rongrong_palette_w) | |
1985 | 1985 | ADDRESS_MAP_END |
1986 | 1986 | |
1987 | 1987 | static ADDRESS_MAP_START( quizchq_portmap, AS_IO, 8, dynax_state ) |
r17959 | r17960 | |
---|---|---|
141 | 141 | 16384 /* data cache size */ |
142 | 142 | }; |
143 | 143 | |
144 | static const ide_config ide_intf = | |
144 | static const ide_config ide_intf = | |
145 | 145 | { |
146 | ide_interrupt, | |
147 | NULL, | |
146 | ide_interrupt, | |
147 | NULL, | |
148 | 148 | 0 |
149 | 149 | }; |
150 | 150 |
r17959 | r17960 | |
---|---|---|
69 | 69 | |
70 | 70 | //static ADDRESS_MAP_START( techno_sub_map, AS_IO, 8, techno_state ) |
71 | 71 | // no ram here, must be internal to the cpu |
72 | // AM_RANGE(0x0000, 0x3fff) AM_READ(rd_r) // to TKY2016A audio processor which has its own 3.58MHz clock | |
73 | // AM_RANGE(0x4000, 0x7fff) AM_WRITE(wr_w) // A11=LED;A12=WR2 (DAC) ;A13=WR1 (TKY2016A as above) | |
74 | // AM_RANGE(0x4000, 0xbfff) AM_ROM // 4000-7FFF is same as 8000-BFFF; 4x 16k ROMS bankswitched | |
75 | // AM_RANGE(0xc000, 0xffff) AM_ROM // another 16k ROM | |
72 | // AM_RANGE(0x0000, 0x3fff) AM_READ(rd_r) // to TKY2016A audio processor which has its own 3.58MHz clock | |
73 | // AM_RANGE(0x4000, 0x7fff) AM_WRITE(wr_w) // A11=LED;A12=WR2 (DAC) ;A13=WR1 (TKY2016A as above) | |
74 | // AM_RANGE(0x4000, 0xbfff) AM_ROM // 4000-7FFF is same as 8000-BFFF; 4x 16k ROMS bankswitched | |
75 | // AM_RANGE(0xc000, 0xffff) AM_ROM // another 16k ROM | |
76 | 76 | //ADDRESS_MAP_END |
77 | 77 | |
78 | 78 | WRITE16_MEMBER( techno_state::disp1_w ) |
r17959 | r17960 | |
---|---|---|
447 | 447 | #define I2C_STATE_DATA_TRANSFER 2 |
448 | 448 | |
449 | 449 | |
450 | struct MPC8240_IRQ | |
450 | struct MPC8240_IRQ | |
451 | 451 | { |
452 | 452 | UINT32 vector; |
453 | 453 | int priority; |
r17959 | r17960 | |
457 | 457 | int mask; |
458 | 458 | }; |
459 | 459 | |
460 | struct MPC8240_GLOBAL_TIMER | |
460 | struct MPC8240_GLOBAL_TIMER | |
461 | 461 | { |
462 | 462 | UINT32 base_count; |
463 | 463 | int enable; |
r17959 | r17960 | |
466 | 466 | |
467 | 467 | |
468 | 468 | |
469 | struct MPC8240_EPIC | |
469 | struct MPC8240_EPIC | |
470 | 470 | { |
471 | 471 | UINT32 iack; |
472 | 472 | UINT32 eicr; |
r17959 | r17960 | |
1968 | 1968 | ide_features[67*2+1] = 0x00; |
1969 | 1969 | } |
1970 | 1970 | |
1971 | static const ide_config ide_intf = | |
1971 | static const ide_config ide_intf = | |
1972 | 1972 | { |
1973 | ide_interrupt, | |
1974 | NULL, | |
1973 | ide_interrupt, | |
1974 | NULL, | |
1975 | 1975 | 0 |
1976 | 1976 | }; |
1977 | 1977 | |
1978 | 1978 | static const voodoo_config voodoo_intf = |
1979 | 1979 | { |
1980 | 8, // fbmem; | |
1981 | 0,// tmumem0; | |
1982 | 0,// tmumem1; | |
1983 | "screen",// screen; | |
1984 | "maincpu",// cputag; | |
1985 | voodoo_vblank,// vblank; | |
1986 | NULL,// stall; | |
1980 | 8, // fbmem; | |
1981 | 0,// tmumem0; | |
1982 | 0,// tmumem1; | |
1983 | "screen",// screen; | |
1984 | "maincpu",// cputag; | |
1985 | voodoo_vblank,// vblank; | |
1986 | NULL,// stall; | |
1987 | 1987 | }; |
1988 | 1988 | |
1989 | 1989 | static MACHINE_CONFIG_START( viper, viper_state ) |
r17959 | r17960 | |
---|---|---|
706 | 706 | m_spritebank = (data >> 1) & 1; |
707 | 707 | |
708 | 708 | logerror("CPU #0 - PC %04X: protection_val = %02X\n",space.device().safe_pc(),data); |
709 | // | |
709 | // if (data & ~0x03) logerror("CPU #0 - PC %04X: unknown spritebank bits: %02X\n",space.device().safe_pc(),data); | |
710 | 710 | } |
711 | 711 | |
712 | 712 | /* |
r17959 | r17960 | |
---|---|---|
461 | 461 | { |
462 | 462 | public: |
463 | 463 | majorpkr_state(const machine_config &mconfig, device_type type, const char *tag) |
464 | : driver_device(mconfig, type, tag), | |
464 | : driver_device(mconfig, type, tag), | |
465 | 465 | oki(*this, "oki") { } |
466 | 466 | |
467 | 467 | int m_mux_data; |
r17959 | r17960 | |
---|---|---|
662 | 662 | 16384 /* data cache size */ |
663 | 663 | }; |
664 | 664 | |
665 | static const ide_config ide_intf = | |
665 | static const ide_config ide_intf = | |
666 | 666 | { |
667 | ide_interrupt, | |
668 | NULL, | |
667 | ide_interrupt, | |
668 | NULL, | |
669 | 669 | 0 |
670 | 670 | }; |
671 | 671 |
r17959 | r17960 | |
---|---|---|
68 | 68 | ROM_REGION(0x10000, "maincpu", 0) |
69 | 69 | ROM_LOAD( "fj_ic2.mpu", 0x1000, 0x0800, CRC(b47bc2c7) SHA1(42c985d83a9454fcd08b87e572e5563ebea0d052)) |
70 | 70 | ROM_LOAD( "fj_ic3.mpu", 0x1800, 0x0800, CRC(ceaeb7d3) SHA1(9e479b985f8500983e71d6ff33ee94160e99650d)) |
71 | ||
71 | ||
72 | 72 | ROM_REGION(0x10000, "cpu2", 0) |
73 | 73 | ROM_LOAD("fj_ic14.snd", 0x1000, 0x0800, CRC(34fe3587) SHA1(132714675a23c101ceb5a4d544818650ae5ccea2)) |
74 | 74 | ROM_RELOAD( 0xf800, 0x0800) |
r17959 | r17960 | |
---|---|---|
764 | 764 | pic8259_ir1_w(drvstate->m_pic8259_1, state); |
765 | 765 | } |
766 | 766 | |
767 | static const ide_config ide_intf = | |
767 | static const ide_config ide_intf = | |
768 | 768 | { |
769 | ide_interrupt, | |
770 | NULL, | |
769 | ide_interrupt, | |
770 | NULL, | |
771 | 771 | 0 |
772 | 772 | }; |
773 | 773 |
r17959 | r17960 | |
---|---|---|
193 | 193 | |
194 | 194 | #define DRAM_BANK_SEL (banks[(VREG(DSBA) >> 7) & 3]) |
195 | 195 | |
196 | struct i82716_t | |
196 | struct i82716_t | |
197 | 197 | { |
198 | 198 | UINT16 r[16]; |
199 | 199 | UINT16 *dram; |
r17959 | r17960 | |
202 | 202 | }; |
203 | 203 | |
204 | 204 | |
205 | struct i8279_t | |
205 | struct i8279_t | |
206 | 206 | { |
207 | 207 | UINT8 command; |
208 | 208 | UINT8 mode; |
r17959 | r17960 | |
---|---|---|
594 | 594 | |
595 | 595 | void littlerb_state::video_start() |
596 | 596 | { |
597 | // machine().primary_screen->register_screen_bitmap(m_temp_bitmap_sprites_back); | |
598 | // machine().primary_screen->register_screen_bitmap(m_temp_bitmap_sprites); | |
597 | // machine().primary_screen->register_screen_bitmap(m_temp_bitmap_sprites_back); | |
598 | // machine().primary_screen->register_screen_bitmap(m_temp_bitmap_sprites); | |
599 | 599 | |
600 | 600 | m_temp_bitmap_sprites_back = auto_bitmap_ind16_alloc(machine(),512,512); |
601 | 601 | m_temp_bitmap_sprites = auto_bitmap_ind16_alloc(machine(),512,512); |
r17959 | r17960 | |
---|---|---|
1822 | 1822 | SLOT_INTERFACE("bb", IDE_BASEBOARD) |
1823 | 1823 | SLOT_INTERFACE_END |
1824 | 1824 | |
1825 | static const ide_config ide_intf = | |
1825 | static const ide_config ide_intf = | |
1826 | 1826 | { |
1827 | ide_interrupt, | |
1828 | "maincpu", | |
1827 | ide_interrupt, | |
1828 | "maincpu", | |
1829 | 1829 | AS_PROGRAM |
1830 | 1830 | }; |
1831 | 1831 |
r17959 | r17960 | |
---|---|---|
1269 | 1269 | enum { RENDER_MAX_ENTRIES = 1000, POLY_MAX_ENTRIES = 10000 }; |
1270 | 1270 | |
1271 | 1271 | |
1272 | struct c417_t | |
1272 | struct c417_t | |
1273 | 1273 | { |
1274 | 1274 | UINT16 ram[0x10000]; |
1275 | 1275 | UINT16 adr; |
1276 | 1276 | UINT32 pointrom_adr; |
1277 | 1277 | }; |
1278 | 1278 | |
1279 | struct c412_t | |
1279 | struct c412_t | |
1280 | 1280 | { |
1281 | 1281 | UINT16 sdram_a[0x100000]; // Framebuffers, probably |
1282 | 1282 | UINT16 sdram_b[0x100000]; |
r17959 | r17960 | |
1285 | 1285 | UINT32 adr; |
1286 | 1286 | }; |
1287 | 1287 | |
1288 | struct c421_t | |
1288 | struct c421_t | |
1289 | 1289 | { |
1290 | 1290 | UINT16 dram_a[0x40000]; |
1291 | 1291 | UINT16 dram_b[0x40000]; |
r17959 | r17960 | |
1293 | 1293 | UINT32 adr; |
1294 | 1294 | }; |
1295 | 1295 | |
1296 | struct c422_t | |
1296 | struct c422_t | |
1297 | 1297 | { |
1298 | 1298 | INT16 regs[0x10]; |
1299 | 1299 | }; |
1300 | 1300 | |
1301 | struct c361_t | |
1301 | struct c361_t | |
1302 | 1302 | { |
1303 | 1303 | emu_timer *timer; |
1304 | 1304 | int scanline; |
1305 | 1305 | }; |
1306 | 1306 | |
1307 | struct render_t | |
1307 | struct render_t | |
1308 | 1308 | { |
1309 | 1309 | poly_manager *polymgr; |
1310 | 1310 | int cur; |
r17959 | r17960 | |
---|---|---|
1564 | 1564 | &jaguar_state::dsp_cpu_int |
1565 | 1565 | }; |
1566 | 1566 | |
1567 | static const ide_config ide_intf = | |
1567 | static const ide_config ide_intf = | |
1568 | 1568 | { |
1569 | &jaguar_state::external_int, | |
1570 | NULL, | |
1569 | &jaguar_state::external_int, | |
1570 | NULL, | |
1571 | 1571 | 0 |
1572 | 1572 | }; |
1573 | 1573 |
r17959 | r17960 | |
---|---|---|
7862 | 7862 | AW_BIOS |
7863 | 7863 | |
7864 | 7864 | ROM_REGION( 0x8000100, "rom_board", ROMREGION_ERASE) |
7865 | ROM_LOAD( "u3.bin", 0x0000000, 0x1000100, CRC(5bb65194) SHA1(5fa8c38e6aadf5d999e260da24b001c0c7805d48) ) | |
7866 | ROM_LOAD( "u1.bin", 0x1000000, 0x1000100, CRC(526fc1af) SHA1(dd8a37fa73a9ef193b6f4fb962345bdfc4854b5d) ) | |
7867 | ROM_LOAD( "u4.bin", 0x2000000, 0x1000100, CRC(55f4e762) SHA1(a11f7d69458e647dd2b8d86c98a54f309b1f1bbc) ) | |
7868 | ROM_LOAD( "u2.bin", 0x3000000, 0x1000100, CRC(c40dae68) SHA1(29ec47c76373eeaa686684f10907d551de7d9c59) ) | |
7869 | ROM_LOAD( "u15.bin", 0x4000000, 0x1000100, CRC(b82dcb0a) SHA1(36dc89a388ac0c7e0a0e72428c8149cbda12805a) ) | |
7870 | ROM_LOAD( "u17.bin", 0x5000000, 0x1000100, CRC(2f973eb4) SHA1(45409b5517cda119315f198892224889ac3a0f53) ) | |
7871 | ROM_LOAD( "u14.bin", 0x6000000, 0x1000100, CRC(2e7d966f) SHA1(3304fd0c5140a13f6fe2ea9aaa74d7885e1505e1) ) | |
7872 | ROM_LOAD( "u16.bin", 0x7000000, 0x1000100, CRC(14f8ca87) SHA1(778c048da9434ffda600e35ad5aca29e02cc98c0) ) | |
7865 | ROM_LOAD( "u3.bin", 0x0000000, 0x1000100, CRC(5bb65194) SHA1(5fa8c38e6aadf5d999e260da24b001c0c7805d48) ) | |
7866 | ROM_LOAD( "u1.bin", 0x1000000, 0x1000100, CRC(526fc1af) SHA1(dd8a37fa73a9ef193b6f4fb962345bdfc4854b5d) ) | |
7867 | ROM_LOAD( "u4.bin", 0x2000000, 0x1000100, CRC(55f4e762) SHA1(a11f7d69458e647dd2b8d86c98a54f309b1f1bbc) ) | |
7868 | ROM_LOAD( "u2.bin", 0x3000000, 0x1000100, CRC(c40dae68) SHA1(29ec47c76373eeaa686684f10907d551de7d9c59) ) | |
7869 | ROM_LOAD( "u15.bin", 0x4000000, 0x1000100, CRC(b82dcb0a) SHA1(36dc89a388ac0c7e0a0e72428c8149cbda12805a) ) | |
7870 | ROM_LOAD( "u17.bin", 0x5000000, 0x1000100, CRC(2f973eb4) SHA1(45409b5517cda119315f198892224889ac3a0f53) ) | |
7871 | ROM_LOAD( "u14.bin", 0x6000000, 0x1000100, CRC(2e7d966f) SHA1(3304fd0c5140a13f6fe2ea9aaa74d7885e1505e1) ) | |
7872 | ROM_LOAD( "u16.bin", 0x7000000, 0x1000100, CRC(14f8ca87) SHA1(778c048da9434ffda600e35ad5aca29e02cc98c0) ) | |
7873 | 7873 | |
7874 | 7874 | ROM_REGION( 4, "rom_key", 0 ) |
7875 | ROM_LOAD( "cckey.bin", 0x000000, 0x000004, CRC(553dd361) SHA1(a60a26b5ee786cf0bb3d09bb6f00374598fbd7cc) ) | |
7875 | ROM_LOAD( "cckey.bin", 0x000000, 0x000004, CRC(553dd361) SHA1(a60a26b5ee786cf0bb3d09bb6f00374598fbd7cc) ) | |
7876 | 7876 | ROM_END |
7877 | 7877 | |
7878 | 7878 | /* All games have the regional titles at the start of the IC22 rom in the following order |
r17959 | r17960 | |
---|---|---|
672 | 672 | |
673 | 673 | |
674 | 674 | |
675 | static const ide_config ide_intf = | |
675 | static const ide_config ide_intf = | |
676 | 676 | { |
677 | ide_interrupt, | |
678 | NULL, | |
677 | ide_interrupt, | |
678 | NULL, | |
679 | 679 | 0 |
680 | 680 | }; |
681 | 681 |
r17959 | r17960 | |
---|---|---|
169 | 169 | * Sound interface |
170 | 170 | * |
171 | 171 | *************************************/ |
172 | ||
173 | ||
172 | ||
173 | ||
174 | 174 | //------------------------------------------------- |
175 | 175 | // sn76496_config psg_intf |
176 | 176 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
177 | 177 | * Sound interface |
178 | 178 | * |
179 | 179 | *************************************/ |
180 | ||
181 | ||
180 | ||
181 | ||
182 | 182 | //------------------------------------------------- |
183 | 183 | // sn76496_config psg_intf |
184 | 184 | //------------------------------------------------- |
r17959 | r17960 | |
221 | 221 | MCFG_SOUND_ADD("sn1", SN76489_NEW, 15468000/6) |
222 | 222 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
223 | 223 | MCFG_SOUND_CONFIG(psg_intf) |
224 | ||
224 | ||
225 | 225 | MCFG_SOUND_ADD("sn2", SN76489_NEW, 15468000/6) |
226 | 226 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
227 | 227 | MCFG_SOUND_CONFIG(psg_intf) |
r17959 | r17960 | |
---|---|---|
164 | 164 | #include "machine/nvram.h" |
165 | 165 | |
166 | 166 | |
167 | struct ds1204_t | |
167 | struct ds1204_t | |
168 | 168 | { |
169 | 169 | int state; |
170 | 170 | int read_ptr; |
r17959 | r17960 | |
---|---|---|
900 | 900 | WRITE16_MEMBER(subsino2_state::bishjan_sel_w) |
901 | 901 | { |
902 | 902 | /* |
903 | sound writes in service mode: | |
904 | 01 88 04 00 (coin in) | |
905 | 02 89 04 0v (v = voice = 0..3) | |
906 | */ | |
903 | sound writes in service mode: | |
904 | 01 88 04 00 (coin in) | |
905 | 02 89 04 0v (v = voice = 0..3) | |
906 | */ | |
907 | 907 | if (ACCESSING_BITS_8_15) |
908 | 908 | m_bishjan_sel = data >> 8; |
909 | 909 | } |
r17959 | r17960 | |
---|---|---|
3377 | 3377 | GAME( 1996, fncywld, 0, fncywld, fncywld, tumbleb_state, fncywld, ROT0, "Unico", "Fancy World - Earth of Crisis" , GAME_SUPPORTS_SAVE ) // game says 1996, testmode 1995? |
3378 | 3378 | // Unico - Magic Purple almost certainly goes here |
3379 | 3379 | |
3380 | /* First Amusement / Mijin / SemiCom hardware (MCU protected) */ | |
3380 | /* First Amusement / Mijin / SemiCom hardware (MCU protected) */ | |
3381 | 3381 | GAME( 1994, metlsavr, 0, metlsavr, metlsavr, tumbleb_state, chokchok, ROT0, "First Amusement", "Metal Saver", GAME_SUPPORTS_SAVE ) |
3382 | 3382 | GAME( 1994, magicbal, 0, metlsavr, magicbal, tumbleb_state, chokchok, ROT0, "SemiCom", "Magicball Fighting (Korea)", GAME_SUPPORTS_SAVE) // also still has the Metal Saver (c)1994 First Amusement tiles in the GFX |
3383 | 3383 | GAME( 1995, chokchok, 0, cookbib, chokchok, tumbleb_state, chokchok, ROT0, "SemiCom", "Choky! Choky!", GAME_IMPERFECT_GRAPHICS | GAME_SUPPORTS_SAVE ) |
r17959 | r17960 | |
---|---|---|
373 | 373 | int specular_r, specular_g, specular_b; |
374 | 374 | }; |
375 | 375 | |
376 | struct PLANE | |
376 | struct PLANE | |
377 | 377 | { |
378 | 378 | float x, y, z, d; |
379 | 379 | }; |
r17959 | r17960 | |
2470 | 2470 | DEVCB_DRIVER_MEMBER(taitotz_state, tlcs900_port_write), |
2471 | 2471 | }; |
2472 | 2472 | |
2473 | static const ide_config ide_intf = | |
2473 | static const ide_config ide_intf = | |
2474 | 2474 | { |
2475 | ide_interrupt, | |
2476 | NULL, | |
2475 | ide_interrupt, | |
2476 | NULL, | |
2477 | 2477 | 0 |
2478 | 2478 | }; |
2479 | 2479 |
r17959 | r17960 | |
---|---|---|
405 | 405 | * Sound interface |
406 | 406 | * |
407 | 407 | *************************************/ |
408 | ||
409 | ||
408 | ||
409 | ||
410 | 410 | //------------------------------------------------- |
411 | 411 | // sn76496_config psg_intf |
412 | 412 | //------------------------------------------------- |
r17959 | r17960 | |
445 | 445 | |
446 | 446 | // MCFG_SOUND_ADD("sn1", SN76496_NEW, 15468480/4) |
447 | 447 | // MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
448 | // | |
448 | // MCFG_SOUND_CONFIG(psg_intf) | |
449 | 449 | |
450 | 450 | // MCFG_SOUND_ADD("sn2", SN76496_NEW, 15468480/4) |
451 | 451 | // MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
452 | // | |
452 | // MCFG_SOUND_CONFIG(psg_intf) | |
453 | 453 | |
454 | 454 | // MCFG_SOUND_ADD("sn3", SN76496_NEW, 15468480/4) |
455 | 455 | // MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
456 | // | |
456 | // MCFG_SOUND_CONFIG(psg_intf) | |
457 | 457 | |
458 | 458 | // MCFG_DAC_ADD("dac") |
459 | 459 | // MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0) |
r17959 | r17960 | |
---|---|---|
4292 | 4292 | machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x800000, 0x800fff, read16_delegate(FUNC(segas32_state::dual_pcb_comms_r),this), write16_delegate(FUNC(segas32_state::dual_pcb_comms_w),this)); |
4293 | 4293 | machine().device("maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x801000, 0x801003, read16_delegate(FUNC(segas32_state::dual_pcb_masterslave),this)); |
4294 | 4294 | |
4295 | // | |
4295 | // machine().device("maincpu")->memory().space(AS_PROGRAM)->install_write_handler(0x800048, 0x800049, write16_delegate(FUNC(segas32_state::f1en_comms_echo_w),this)); | |
4296 | 4296 | m_system32_prot_vblank = f1lap_fd1149_vblank; |
4297 | 4297 | |
4298 | 4298 | m_sw1_output = f1lap_sw1_output; |
r17959 | r17960 | |
---|---|---|
580 | 580 | deco56_remap_gfx(machine(), "gfx6"); |
581 | 581 | deco102_decrypt_cpu(machine(), "maincpu", 0x42ba, 0x00, 0x18); |
582 | 582 | memcpy(dst, src, 0x100000); |
583 | ||
583 | ||
584 | 584 | decoprot_reset(machine()); |
585 | 585 | } |
586 | 586 |
r17959 | r17960 | |
---|---|---|
1446 | 1446 | djmain_tile_callback, "none" |
1447 | 1447 | }; |
1448 | 1448 | |
1449 | static const ide_config ide_intf = | |
1449 | static const ide_config ide_intf = | |
1450 | 1450 | { |
1451 | ide_interrupt, | |
1452 | NULL, | |
1451 | ide_interrupt, | |
1452 | NULL, | |
1453 | 1453 | 0 |
1454 | 1454 | }; |
1455 | 1455 |
r17959 | r17960 | |
---|---|---|
911 | 911 | if (pri == 0) |
912 | 912 | machine().priority_bitmap.fill(0, cliprect); |
913 | 913 | |
914 | // if (offs == 0) | |
914 | // if (offs == 0) // boot | |
915 | 915 | c355_obj_draw_list(bitmap, cliprect, pri, &m_c355_obj_ram[0x02000/2], &m_c355_obj_ram[0x00000/2]); |
916 | 916 | // else |
917 | 917 | c355_obj_draw_list(bitmap, cliprect, pri, &m_c355_obj_ram[0x14000/2], &m_c355_obj_ram[0x10000/2]); |
r17959 | r17960 | |
923 | 923 | if (pri == 0) |
924 | 924 | machine().priority_bitmap.fill(0, cliprect); |
925 | 925 | |
926 | // if (offs == 0) | |
926 | // if (offs == 0) // boot | |
927 | 927 | c355_obj_draw_list(bitmap, cliprect, pri, &m_c355_obj_ram[0x02000/2], &m_c355_obj_ram[0x00000/2]); |
928 | 928 | // else |
929 | 929 | c355_obj_draw_list(bitmap, cliprect, pri, &m_c355_obj_ram[0x14000/2], &m_c355_obj_ram[0x10000/2]); |
r17959 | r17960 | |
1167 | 1167 | int row = line / 8; |
1168 | 1168 | int offs = row * 0x100 + (line & 7) * 0x10 + 0xe080; |
1169 | 1169 | UINT16 *source = &m_c169_roz_videoram[offs / 2]; |
1170 | ||
1170 | ||
1171 | 1171 | // if enabled |
1172 | 1172 | if ((source[1] & 0x8000) == 0) |
1173 | 1173 | { |
1174 | 1174 | roz_parameters params; |
1175 | 1175 | c169_roz_unpack_params(source, params); |
1176 | ||
1176 | ||
1177 | 1177 | // check priority |
1178 | 1178 | if (pri == params.priority) |
1179 | 1179 | { |
r17959 | r17960 | |
1194 | 1194 | { |
1195 | 1195 | const UINT16 *source = &m_c169_roz_control[which * 8]; |
1196 | 1196 | UINT16 attrs = source[1]; |
1197 | ||
1197 | ||
1198 | 1198 | // if enabled |
1199 | 1199 | if ((attrs & 0x8000) == 0) |
1200 | 1200 | { |
r17959 | r17960 | |
1212 | 1212 | c169_roz_draw_helper(bitmap, *m_c169_roz_tilemap[which], cliprect, params); |
1213 | 1213 | } |
1214 | 1214 | } |
1215 | } | |
1215 | } | |
1216 | 1216 | } |
1217 | 1217 | |
1218 | 1218 | READ16_MEMBER( namcos2_shared_state::c169_roz_control_r ) |
r17959 | r17960 | |
1334 | 1334 | WRITE16_MEMBER( namco_c45_road_device::write ) |
1335 | 1335 | { |
1336 | 1336 | COMBINE_DATA(&m_ram[offset]); |
1337 | ||
1337 | ||
1338 | 1338 | // first half maps to the tilemap |
1339 | 1339 | if (offset < 0x10000/2) |
1340 | 1340 | m_tilemap->mark_tile_dirty(offset); |
1341 | ||
1341 | ||
1342 | 1342 | // second half maps to the gfx elements |
1343 | 1343 | else |
1344 | 1344 | { |
r17959 | r17960 | |
1379 | 1379 | continue; |
1380 | 1380 | |
1381 | 1381 | // mask off priority bits and sign-extend |
1382 | screenx &= 0x0fff; | |
1382 | screenx &= 0x0fff; | |
1383 | 1383 | if (screenx & 0x0800) |
1384 | 1384 | screenx |= ~0x7ff; |
1385 | 1385 | |
r17959 | r17960 | |
1388 | 1388 | |
1389 | 1389 | int numpixels = (44 * ROAD_TILE_SIZE << 16) / dsourcex; |
1390 | 1390 | unsigned sourcex = 0; |
1391 | ||
1391 | ||
1392 | 1392 | // crop left |
1393 | 1393 | int clip_pixels = cliprect.min_x - screenx; |
1394 | 1394 | if (clip_pixels > 0) |
r17959 | r17960 | |
1449 | 1449 | // create a tilemap for the road |
1450 | 1450 | m_tilemap = &machine().tilemap().create(tilemap_get_info_delegate(FUNC(namco_c45_road_device::get_road_info), this), |
1451 | 1451 | TILEMAP_SCAN_ROWS, ROAD_TILE_SIZE, ROAD_TILE_SIZE, ROAD_COLS, ROAD_ROWS); |
1452 | } | |
1452 | } | |
1453 | 1453 | |
1454 | 1454 | |
1455 | 1455 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
73 | 73 | { |
74 | 74 | return m_peno_mainram[offset]; |
75 | 75 | } |
76 | ||
76 | ||
77 | 77 | DECLARE_WRITE16_MEMBER( penocup_mainram_w ) |
78 | 78 | { |
79 | 79 | offset &=0x7fff; |
80 | 80 | COMBINE_DATA(&m_peno_mainram[offset]); |
81 | // | |
81 | // COMBINE_DATA(&m_peno_vram[offset]); | |
82 | 82 | } |
83 | 83 | |
84 | 84 | |
r17959 | r17960 | |
93 | 93 | m_peno_vram = (UINT16*)auto_alloc_array_clear(machine(), UINT16, 0x10000/2); |
94 | 94 | m_peno_mainram = (UINT16*)auto_alloc_array_clear(machine(), UINT16, 0x10000/2); |
95 | 95 | |
96 | ||
97 | 96 | |
97 | ||
98 | 98 | } |
99 | 99 | |
100 | 100 | static SCREEN_UPDATE_IND16(ttchamp) |
r17959 | r17960 | |
173 | 173 | /* 0x10000 - 0x1ffff is where it writes most image stuff, but other address get written to 0 where the left edge of 'sprites' would be? why? bad code execution, or some kind of write address based blitter? |
174 | 174 | see for example the lines written down the side of where the (not displayed) CREDIT text would go, as well as beside the actual credit number.. also ingame if you can get it to start |
175 | 175 | */ |
176 | ||
176 | ||
177 | 177 | AM_RANGE(0x10000, 0xfffff) AM_WRITE(penocup_vid_w) |
178 | 178 | |
179 | 179 | // how are these banked? what are the bank sizes? data needed for startup is at 0x20000-0x2ffff (strings) and 0x30000-0x3ffff (code) the rest seems to be graphics.. |
r17959 | r17960 | |
---|---|---|
12 | 12 | - sound (controlled by three i8741); |
13 | 13 | - add flipscreen; |
14 | 14 | - color prom resistor network is guessed, cyclemb yellows are more reddish on pcb video and photos; |
15 | ||
15 | ||
16 | 16 | BTANB verified on pcb: cyclemb standing cones are reddish-yellow/black instead of red/white |
17 | 17 | |
18 | 18 | ===================================================================================================== |
r17959 | r17960 | |
---|---|---|
78 | 78 | guab_state(const machine_config &mconfig, device_type type, const char *tag) |
79 | 79 | : driver_device(mconfig, type, tag) , |
80 | 80 | m_sn(*this, "snsnd") { } |
81 | ||
81 | ||
82 | 82 | /* devices */ |
83 | 83 | required_device<sn76489_new_device> m_sn; |
84 | ||
84 | ||
85 | 85 | struct ef9369 m_pal; |
86 | 86 | emu_timer *m_fdc_timer; |
87 | 87 | struct wd1770 m_fdc; |
r17959 | r17960 | |
784 | 784 | * Sound interface |
785 | 785 | * |
786 | 786 | *************************************/ |
787 | ||
788 | ||
787 | ||
788 | ||
789 | 789 | //------------------------------------------------- |
790 | 790 | // sn76496_config psg_intf |
791 | 791 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
391 | 391 | { |
392 | 392 | dpoker_coin_status &= ~8; |
393 | 393 | } |
394 | ||
394 | ||
395 | 395 | coin_counter_w(timer.machine(), 3, dpoker_coin_status & 8); |
396 | 396 | } |
397 | 397 | |
r17959 | r17960 | |
443 | 443 | { |
444 | 444 | // d5: button lamp: service or change |
445 | 445 | output_set_lamp_value(8, data >> 5 & 1); |
446 | ||
446 | ||
447 | 447 | // d0-d4: marquee lamps: coin 1 to 5 --> output lamps 9 to 13 |
448 | 448 | for (int i = 0; i < 5; i++) |
449 | 449 | output_set_lamp_value(9 + i, data >> i & 1); |
450 | ||
450 | ||
451 | 451 | // d6, d7: unused? |
452 | 452 | } |
453 | 453 | |
r17959 | r17960 | |
456 | 456 | // d0: ? coin return |
457 | 457 | // d1: ? divertor (active low) |
458 | 458 | // d3: coin counter? |
459 | ||
459 | ||
460 | 460 | // d6: assume hopper coin flow |
461 | 461 | // d7: assume hopper motor |
462 | 462 | if (data & 0x40 & ~dpoker_output) |
463 | 463 | m_dpoker_hopper_timer->adjust(attotime::from_msec(500)); |
464 | ||
464 | ||
465 | 465 | // other bits: unused? |
466 | 466 | |
467 | 467 | dpoker_output = data; |
r17959 | r17960 | |
1051 | 1051 | PORT_DIPNAME( 0x80, 0x00, "Background Color" ) PORT_DIPLOCATION("B3:8") |
1052 | 1052 | PORT_DIPSETTING( 0x80, "Green" ) |
1053 | 1053 | PORT_DIPSETTING( 0x00, "Blue" ) |
1054 | // PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("B3:9") | |
1055 | // PORT_DIPSETTING( 0x01, DEF_STR( On ) ) | |
1056 | // PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) | |
1057 | // PORT_DIPNAME( 0x01, 0x00, "Freeze" ) PORT_DIPLOCATION("B3:10") | |
1058 | // PORT_DIPSETTING( 0x01, DEF_STR( On ) ) | |
1059 | // PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) | |
1054 | // PORT_DIPNAME( 0x01, 0x00, DEF_STR( Unused ) ) PORT_DIPLOCATION("B3:9") | |
1055 | // PORT_DIPSETTING( 0x01, DEF_STR( On ) ) | |
1056 | // PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) | |
1057 | // PORT_DIPNAME( 0x01, 0x00, "Freeze" ) PORT_DIPLOCATION("B3:10") | |
1058 | // PORT_DIPSETTING( 0x01, DEF_STR( On ) ) | |
1059 | // PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) | |
1060 | 1060 | |
1061 | 1061 | PORT_START("ssio:IP4") |
1062 | 1062 | PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED ) |
r17959 | r17960 | |
2811 | 2811 | machine().device("maincpu")->memory().space(AS_IO)->install_write_handler(0x30, 0x30, write8_delegate(FUNC(mcr_state::dpoker_lamps2_w),this)); |
2812 | 2812 | machine().device("maincpu")->memory().space(AS_IO)->install_write_handler(0x34, 0x34, write8_delegate(FUNC(mcr_state::dpoker_output_w),this)); |
2813 | 2813 | machine().device("maincpu")->memory().space(AS_IO)->install_write_handler(0x3f, 0x3f, write8_delegate(FUNC(mcr_state::dpoker_meters_w),this)); |
2814 | ||
2814 | ||
2815 | 2815 | dpoker_coin_status = 0; |
2816 | 2816 | dpoker_output = 0; |
2817 | 2817 |
r17959 | r17960 | |
---|---|---|
537 | 537 | machine().root_device().membank("bank1")->set_base(machine().root_device().memregion("bios")->base() + 0x20000); |
538 | 538 | } |
539 | 539 | |
540 | static const ide_config ide_intf = | |
540 | static const ide_config ide_intf = | |
541 | 541 | { |
542 | ide_interrupt, | |
543 | NULL, | |
542 | ide_interrupt, | |
543 | NULL, | |
544 | 544 | 0 |
545 | 545 | }; |
546 | 546 |
r17959 | r17960 | |
---|---|---|
1 | 1 | /* Konami Cobra System |
2 | 2 | |
3 | ||
3 | Driver by Ville Linde | |
4 | 4 | |
5 | 5 | |
6 | 6 | Games on this hardware |
r17959 | r17960 | |
160 | 160 | |
161 | 161 | 0x0011c: Same as above? |
162 | 162 | |
163 | ||
163 | 0x00454: (mask 0xff) 0x80000000 Tex related | |
164 | 164 | |
165 | 165 | 0x00458: Set to 0x02100000 (0xff) by texselect() |
166 | 166 | |
167 | ------xx -------- -------- -------- Texture select (0-3) | |
168 | -------- ---x---- -------- -------- ? | |
167 | ------xx -------- -------- -------- Texture select (0-3) | |
168 | -------- ---x---- -------- -------- ? | |
169 | 169 | |
170 | ||
170 | 0x02900: -------- -------- -------- -------- Texture[0] ? | |
171 | 171 | |
172 | 172 | 0x02904: -------- ------xx xx------ -------- Texture[0] mag filter? |
173 | 173 | -------- -------- --xxxx-- -------- Texture[0] min filter? |
r17959 | r17960 | |
184 | 184 | |
185 | 185 | 0x02914: xxxxxxxx xxxxxxxx xxxx---- -------- Texture[0] address |
186 | 186 | |
187 | 0x02980: Texture[1] ? | |
188 | 0x02984: Texture[1] min/mag filter | |
189 | 0x02988: Texture[1] wrap | |
190 | 0x02990: Texture[1] width/height/format | |
191 | 0x02994: Texture[1] address | |
187 | 0x02980: Texture[1] ? | |
188 | 0x02984: Texture[1] min/mag filter | |
189 | 0x02988: Texture[1] wrap | |
190 | 0x02990: Texture[1] width/height/format | |
191 | 0x02994: Texture[1] address | |
192 | 192 | |
193 | 0x02a00: Texture[2] ? | |
194 | 0x02a04: Texture[2] min/mag filter | |
195 | 0x02a08: Texture[2] wrap | |
196 | 0x02a10: Texture[2] width/height/format | |
197 | 0x02a14: Texture[2] address | |
193 | 0x02a00: Texture[2] ? | |
194 | 0x02a04: Texture[2] min/mag filter | |
195 | 0x02a08: Texture[2] wrap | |
196 | 0x02a10: Texture[2] width/height/format | |
197 | 0x02a14: Texture[2] address | |
198 | 198 | |
199 | 0x02a80: Texture[3] ? | |
200 | 0x02a84: Texture[3] min/mag filter | |
201 | 0x02a88: Texture[3] wrap | |
202 | 0x02a90: Texture[3] width/height/format | |
203 | 0x02a94: Texture[3] address | |
199 | 0x02a80: Texture[3] ? | |
200 | 0x02a84: Texture[3] min/mag filter | |
201 | 0x02a88: Texture[3] wrap | |
202 | 0x02a90: Texture[3] width/height/format | |
203 | 0x02a94: Texture[3] address | |
204 | 204 | |
205 | 205 | 0x40018: Set to 0x0001040a (0xc0) by mode_stipple() (bits 24..27 = stipple pattern?) |
206 | 206 | 0x400d0: Set to 0x80000000 (0x80) by mode_stipple() |
207 | 207 | |
208 | 0x400f4: xxx----- -------- -------- -------- | |
208 | 0x400f4: xxx----- -------- -------- -------- Texture select (0-3) | |
209 | 209 | |
210 | 210 | 0x40114: -------- ----x--- -------- -------- Scissor enable |
211 | 211 | |
r17959 | r17960 | |
226 | 226 | 0x40198: x------- -------- -------- -------- Alpha test enable? |
227 | 227 | -------- xxx----- -------- -------- Alpha test function (0 = never, 1 = less, 2 = lequal, 3 = greater, |
228 | 228 | 4 = gequal, 5 = equal, 6 = notequal, 7 = always) |
229 | ||
229 | -------- -------- xxxxxxxx xxxxxxxx Alpha test reference value? | |
230 | 230 | |
231 | 231 | 0x4019c: x------- -------- -------- -------- Fog enable |
232 | 232 | ----x--- -------- -------- -------- 0 = table fog, 1 = linear fog |
233 | 233 | |
234 | 0x401a8: (mask 0xff): 0x2CAB34FD ? | |
235 | 0x401ac: (mask 0xf0): 0x48C70000 ? | |
236 | 0x401b8: (mask 0x20): 0x00400000 ? | |
234 | 0x401a8: (mask 0xff): 0x2CAB34FD ? | |
235 | 0x401ac: (mask 0xf0): 0x48C70000 ? | |
236 | 0x401b8: (mask 0x20): 0x00400000 ? | |
237 | 237 | |
238 | 238 | 0x401bc: Texture env mode |
239 | 239 | xxx----- -------- -------- -------- ? |
r17959 | r17960 | |
249 | 249 | 0xa92b0100 = (equal, 16) |
250 | 250 | |
251 | 251 | -------- -------- xxxxxxxx xxxx---- Stencil reference value? |
252 | ||
252 | ----xxxx xxxxxxxx -------- -------- Stencil fill value? | |
253 | 253 | xxx----- -------- -------- -------- Stencil function? |
254 | 254 | |
255 | 255 | |
256 | 256 | 0x80020: -------- ----xxx- -------- -------- Depth test function (7 = always?) |
257 | 257 | |
258 | 0x80040: (mask 0x0f) 0x00002CAB (same value as 0x401a8) | |
259 | 0x80044: (mask 0x0f) 0x000034FD (same value as 0x401a8) | |
260 | 0x80048: (mask 0x0f) 0x000048C7 (same value as 0x401ac) | |
258 | 0x80040: (mask 0x0f) 0x00002CAB (same value as 0x401a8) | |
259 | 0x80044: (mask 0x0f) 0x000034FD (same value as 0x401a8) | |
260 | 0x80048: (mask 0x0f) 0x000048C7 (same value as 0x401ac) | |
261 | 261 | |
262 | 262 | 0x80050: (mask 0x7c) 0x04445500 = (As, 1-As) Blend register |
263 | 263 | 0x04111100 = (1, 1) |
r17959 | r17960 | |
407 | 407 | |
408 | 408 | UINT32 *m_gfx_gram; |
409 | 409 | UINT32 *m_gfx_regmask; |
410 | ||
410 | ||
411 | 411 | UINT32 m_gfx_register_select; |
412 | 412 | UINT64 *m_gfx_register; |
413 | 413 | |
r17959 | r17960 | |
582 | 582 | commit_encoded(); |
583 | 583 | |
584 | 584 | get_encoded_reply(rec_data, rec_size); |
585 | ||
585 | ||
586 | 586 | m_send_ptr = 0; |
587 | 587 | return; |
588 | 588 | } |
r17959 | r17960 | |
882 | 882 | UINT32 gour = (int)(gr); |
883 | 883 | UINT32 goug = (int)(gg); |
884 | 884 | UINT32 goub = (int)(gb); |
885 | ||
885 | ||
886 | 886 | int r = (RGB_RED(texel) * gour) >> 8; |
887 | 887 | int g = (RGB_GREEN(texel) * goug) >> 8; |
888 | 888 | int b = (RGB_BLUE(texel) * goub) >> 8; |
r17959 | r17960 | |
1926 | 1926 | //printf("DMA write to unknown: size %d, data %08X\n", width, data); |
1927 | 1927 | |
1928 | 1928 | /* |
1929 | static FILE *out; | |
1930 | if (out == NULL) | |
1931 | out = fopen("sound.bin", "wb"); | |
1929 | static FILE *out; | |
1930 | if (out == NULL) | |
1931 | out = fopen("sound.bin", "wb"); | |
1932 | 1932 | |
1933 | fputc((data >> 24) & 0xff, out); | |
1934 | fputc((data >> 16) & 0xff, out); | |
1935 | fputc((data >> 8) & 0xff, out); | |
1936 | fputc((data >> 0) & 0xff, out); | |
1937 | */ | |
1933 | fputc((data >> 24) & 0xff, out); | |
1934 | fputc((data >> 16) & 0xff, out); | |
1935 | fputc((data >> 8) & 0xff, out); | |
1936 | fputc((data >> 0) & 0xff, out); | |
1937 | */ | |
1938 | 1938 | |
1939 | 1939 | cobra_state *cobra = device->machine().driver_data<cobra_state>(); |
1940 | 1940 | |
r17959 | r17960 | |
1948 | 1948 | if (cobra->m_sound_dma_ptr >= DMA_SOUND_BUFFER_SIZE) |
1949 | 1949 | { |
1950 | 1950 | cobra->m_sound_dma_ptr = 0; |
1951 | ||
1951 | ||
1952 | 1952 | dmadac_transfer(&cobra->m_dmadac[0], 1, 0, 1, DMA_SOUND_BUFFER_SIZE, cobra->m_sound_dma_buffer_l); |
1953 | 1953 | dmadac_transfer(&cobra->m_dmadac[1], 1, 0, 1, DMA_SOUND_BUFFER_SIZE, cobra->m_sound_dma_buffer_r); |
1954 | 1954 | } |
r17959 | r17960 | |
2077 | 2077 | fputc((UINT8)(m_texture_ram[i] >> 0), file); |
2078 | 2078 | } |
2079 | 2079 | fclose(file); |
2080 | ||
2080 | */ | |
2081 | 2081 | } |
2082 | 2082 | |
2083 | 2083 | void cobra_renderer::gfx_reset(running_machine &machine) |
r17959 | r17960 | |
2367 | 2367 | } |
2368 | 2368 | |
2369 | 2369 | |
2370 | ||
2370 | ||
2371 | 2371 | float vp_width = u2f(m_gfx_gram[0x00090/4]); |
2372 | 2372 | float vp_height = u2f(m_gfx_gram[0x000a4/4]); |
2373 | 2373 | float vp_center_x = u2f(m_gfx_gram[0x0009c/4]); |
r17959 | r17960 | |
2382 | 2382 | #if LOG_DRAW_COMMANDS |
2383 | 2383 | printf("--- Draw command %08X %08X ---\n", w1, w2); |
2384 | 2384 | #endif |
2385 | ||
2386 | 2385 | |
2386 | ||
2387 | 2387 | // extract vertex data |
2388 | 2388 | for (int i=0; i < units; i++) |
2389 | 2389 | { |
r17959 | r17960 | |
3223 | 3223 | dmadac_set_frequency(&m_dmadac[1], 1, 44100); |
3224 | 3224 | } |
3225 | 3225 | |
3226 | static const ide_config ide_intf = | |
3226 | static const ide_config ide_intf = | |
3227 | 3227 | { |
3228 | ide_interrupt, | |
3229 | NULL, | |
3228 | ide_interrupt, | |
3229 | NULL, | |
3230 | 3230 | 0 |
3231 | 3231 | }; |
3232 | 3232 | |
r17959 | r17960 | |
3383 | 3383 | { |
3384 | 3384 | UINT8 *rom = (UINT8*)machine().root_device().memregion("m48t58")->base(); |
3385 | 3385 | rom[0x00] = 0x47; // G |
3386 | rom[0x01] = 0x4e; // N | |
3386 | rom[0x01] = 0x4e; // N // N = 2-player, Q = 1-player? | |
3387 | 3387 | rom[0x02] = 0x36; // 6 |
3388 | 3388 | rom[0x03] = 0x34; // 4 |
3389 | 3389 | rom[0x04] = 0x35; // 5 |
r17959 | r17960 | |
3412 | 3412 | |
3413 | 3413 | // hd patches |
3414 | 3414 | // (gfx) |
3415 | // 0x18932c = 0x38600000 | |
3415 | // 0x18932c = 0x38600000 skips check_one_scene() | |
3416 | 3416 | |
3417 | 3417 | // (sub) |
3418 | // 0x2d3568 = 0x60000000 [0x4082001c] | |
3418 | // 0x2d3568 = 0x60000000 [0x4082001c] skip IRQ fail | |
3419 | 3419 | |
3420 | 3420 | // (main) |
3421 | // 0x5025ac = 0x60000000 [0x4082055c] | |
3421 | // 0x5025ac = 0x60000000 [0x4082055c] skip IRQ fail... | |
3422 | 3422 | // 0x503ec4 = 0x60000000 [0x4186fff8] |
3423 | 3423 | // 0x503f00 = 0x60000000 [0x4186fff8] |
3424 | 3424 | |
r17959 | r17960 | |
3503 | 3503 | |
3504 | 3504 | // hd patches |
3505 | 3505 | // (gfx) |
3506 | // 0x144354 = 0x38600000 [0x4bfffb91] | |
3506 | // 0x144354 = 0x38600000 [0x4bfffb91] skips check_one_scene() | |
3507 | 3507 | |
3508 | 3508 | // (sub) |
3509 | // 0x2a5394 = 0x4800001c [0x4182001c] sound chip check? | |
3510 | // 0x2a53f4 = 0x4800001c [0x4082001c] ? | |
3511 | // 0x2a546c = 0x60000000 [0x48001a0d] ? | |
3512 | // 0x2a5510 = 0x48000014 [0x419e0014] ? | |
3509 | // 0x2a5394 = 0x4800001c [0x4182001c] sound chip check? | |
3510 | // 0x2a53f4 = 0x4800001c [0x4082001c] ? | |
3511 | // 0x2a546c = 0x60000000 [0x48001a0d] ? | |
3512 | // 0x2a5510 = 0x48000014 [0x419e0014] ? | |
3513 | 3513 | |
3514 | 3514 | // (main) |
3515 | // 0x14aa48 = 0x60000000 [0x4182fff4] | |
3515 | // 0x14aa48 = 0x60000000 [0x4182fff4] ? | |
3516 | 3516 | |
3517 | 3517 | m_has_psac = true; |
3518 | 3518 | } |
r17959 | r17960 | |
---|---|---|
555 | 555 | * Sound interface |
556 | 556 | * |
557 | 557 | *************************************/ |
558 | ||
559 | ||
558 | ||
559 | ||
560 | 560 | //------------------------------------------------- |
561 | 561 | // sn76496_config psg_intf |
562 | 562 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
898 | 898 | DEVCB_NULL |
899 | 899 | }; |
900 | 900 | |
901 | static const ide_config ide_intf = | |
901 | static const ide_config ide_intf = | |
902 | 902 | { |
903 | ide_interrupt, | |
904 | NULL, | |
903 | ide_interrupt, | |
904 | NULL, | |
905 | 905 | 0 |
906 | 906 | }; |
907 | 907 |
r17959 | r17960 | |
---|---|---|
686 | 686 | machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000); |
687 | 687 | } |
688 | 688 | |
689 | static const ide_config ide_intf = | |
689 | static const ide_config ide_intf = | |
690 | 690 | { |
691 | ide_interrupt, | |
692 | NULL, | |
691 | ide_interrupt, | |
692 | NULL, | |
693 | 693 | 0 |
694 | 694 | }; |
695 | 695 |
r17959 | r17960 | |
---|---|---|
131 | 131 | NET_ALIAS(256H, ic_f6b.Q) |
132 | 132 | NET_ALIAS(256HQ, ic_f6b.QQ) |
133 | 133 | |
134 | // vertical counter | |
134 | // vertical counter | |
135 | 135 | TTL_7493(ic_e8, hreset, ic_e8.QA, ic_e7a.QQ, ic_e7a.QQ) // e8, e9, d9b |
136 | 136 | TTL_7493(ic_e9, ic_e8.QD,ic_e9.QA, ic_e7a.QQ, ic_e7a.QQ) // e8, e9, d9b |
137 | 137 | TTL_74107(ic_d9b, ic_e9.QD, high, high, ic_e7a.Q) |
r17959 | r17960 | |
149 | 149 | NET_ALIAS(256VQ, ic_d9b.QQ) |
150 | 150 | |
151 | 151 | |
152 | // hblank flip flop | |
152 | // hblank flip flop | |
153 | 153 | |
154 | 154 | TTL_7400_NAND(ic_g5b, 16H, 64H) |
155 | 155 | |
156 | // the time critical one | |
156 | // the time critical one | |
157 | 157 | TTL_7400_NAND(ic_h5c, ic_h5b.Q, hresetQ) |
158 | 158 | TTL_7400_NAND(ic_h5b, ic_h5c.Q, ic_g5b.Q) |
159 | 159 | |
r17959 | r17960 | |
161 | 161 | NET_ALIAS(hblankQ, ic_h5b.Q) |
162 | 162 | TTL_7400_NAND(hsyncQ, hblank, 32H) |
163 | 163 | |
164 | // vblank flip flop | |
164 | // vblank flip flop | |
165 | 165 | TTL_7402_NOR(ic_f5c, ic_f5d.Q, vreset) |
166 | 166 | TTL_7402_NOR(ic_f5d, ic_f5c.Q, 16V) |
167 | 167 | |
r17959 | r17960 | |
172 | 172 | TTL_7410_NAND(ic_g5a, vblank, 4V, ic_h5a.Q) |
173 | 173 | NET_ALIAS(vsyncQ, ic_g5a.Q) |
174 | 174 | |
175 | // move logic | |
175 | // move logic | |
176 | 176 | |
177 | 177 | TTL_7400_NAND(ic_e1d, hit_sound, ic_e1c.Q) |
178 | 178 | TTL_7400_NAND(ic_e1c, ic_f1.QC, ic_f1.QD) |
r17959 | r17960 | |
201 | 201 | NET_ALIAS(Aa, ic_h4c.Q) |
202 | 202 | NET_ALIAS(Ba, ic_h4b.Q) |
203 | 203 | |
204 | // hvid circuit | |
204 | // hvid circuit | |
205 | 205 | |
206 | 206 | TTL_7400_NAND(hball_resetQ, Serve, attractQ) |
207 | 207 | |
r17959 | r17960 | |
212 | 212 | TTL_7420_NAND(ic_h6b, ic_g6b.Q, ic_h7.RC, ic_g7.QC, ic_g7.QD) |
213 | 213 | NET_ALIAS(hvidQ, ic_h6b.Q) |
214 | 214 | |
215 | // vvid circuit | |
215 | // vvid circuit | |
216 | 216 | |
217 | 217 | TTL_9316(ic_b3, hsyncQ, high, vblankQ, high, ic_b2b.Q, a6, b6, c6, d6) |
218 | 218 | TTL_9316(ic_a3, hsyncQ, ic_b3.RC, high, high, ic_b2b.Q, low, low, low, low) |
219 | 219 | TTL_7400_NAND(ic_b2b, ic_a3.RC, ic_b3.RC) |
220 | 220 | TTL_7410_NAND(ic_e2b, ic_a3.RC, ic_b3.QC, ic_b3.QD) |
221 | 221 | NET_ALIAS(vvidQ, ic_e2b.Q) |
222 | TTL_7404_INVERT(vvid, vvidQ) // D2D | |
222 | TTL_7404_INVERT(vvid, vvidQ) // D2D | |
223 | 223 | NET_ALIAS(vpos256, ic_a3.RC) |
224 | 224 | NET_ALIAS(vpos32, ic_a3.QB) |
225 | 225 | NET_ALIAS(vpos16, ic_a3.QA) |
226 | 226 | |
227 | // vball ctrl circuit | |
227 | // vball ctrl circuit | |
228 | 228 | |
229 | 229 | TTL_7450_ANDORINVERT(ic_a6a, b1, 256HQ, b2, 256H) |
230 | 230 | TTL_7450_ANDORINVERT(ic_a6b, c1, 256HQ, c2, 256H) |
r17959 | r17960 | |
233 | 233 | TTL_7474(ic_a5b, hit, ic_a6a, attractQ, high) |
234 | 234 | TTL_7474(ic_a5a, hit, ic_a6b, attractQ, high) |
235 | 235 | TTL_7474(ic_b5a, hit, ic_b6b, attractQ, high) |
236 | TTL_74107(ic_h2x, vblank, vvid, vvid, hitQ) // two marked at position h2a ==> this h2x | |
236 | TTL_74107(ic_h2x, vblank, vvid, vvid, hitQ) // two marked at position h2a ==> this h2x | |
237 | 237 | |
238 | 238 | TTL_7486_XOR(ic_a4c, ic_a5b.Q, ic_h2x.Q) |
239 | 239 | TTL_7486_XOR(ic_a4b, ic_a5a.Q, ic_h2x.Q) |
r17959 | r17960 | |
248 | 248 | NET_ALIAS(c6, ic_b4.SC) |
249 | 249 | NET_ALIAS(d6, ic_b4.SD) |
250 | 250 | |
251 | // serve monoflop | |
251 | // serve monoflop | |
252 | 252 | TTL_7404_INVERT(f4_trig, rstspeed) |
253 | 253 | NE555N_MSTABLE(ic_f4_serve, f4_trig, NC) |
254 | 254 | NETDEV_PARAM(ic_f4_serve.R, RES_K(330)) |
r17959 | r17960 | |
260 | 260 | NET_ALIAS(Serve, ic_b5b_serve.QQ) |
261 | 261 | NET_ALIAS(ServeQ, ic_b5b_serve.Q) |
262 | 262 | |
263 | // score logic | |
263 | // score logic | |
264 | 264 | |
265 | 265 | TTL_7474(ic_h3a, 4H, 128H, high, attractQ) |
266 | 266 | |
267 | // sound logic | |
267 | // sound logic | |
268 | 268 | TTL_7474(ic_c2a, vpos256, high, hitQ, high) |
269 | 269 | TTL_74107(ic_f3_topbot, vblank, vvid, vvidQ, ServeQ) |
270 | 270 | NE555N_MSTABLE(ic_g4_sc, MissQ, NC) |
271 | NET_ALIAS(SC, ic_g4_sc.Q) // monoflop with NE555 determines score sound | |
271 | NET_ALIAS(SC, ic_g4_sc.Q) // monoflop with NE555 determines score sound | |
272 | 272 | NETDEV_PARAM(ic_g4_sc.R, RES_K(220)) |
273 | 273 | NETDEV_PARAM(ic_g4_sc.C, CAP_U(1)) |
274 | 274 | |
r17959 | r17960 | |
282 | 282 | NET_ALIAS(sound, ic_c1b.Q) |
283 | 283 | |
284 | 284 | |
285 | // paddle1 logic 1 | |
285 | // paddle1 logic 1 | |
286 | 286 | |
287 | 287 | NE555N_MSTABLE(ic_b9, 256VQ, P1) |
288 | 288 | NETDEV_PARAM(ic_b9.R, RES_K(90)) |
r17959 | r17960 | |
299 | 299 | NET_ALIAS(c1, ic_b8.QC) |
300 | 300 | NET_ALIAS(d1, ic_b8.QD) |
301 | 301 | |
302 | // paddle1 logic 2 | |
302 | // paddle1 logic 2 | |
303 | 303 | |
304 | 304 | NE555N_MSTABLE(ic_a9, 256VQ, P2) |
305 | 305 | NETDEV_PARAM(ic_a9.R, RES_K(90)) |
r17959 | r17960 | |
316 | 316 | NET_ALIAS(c2, ic_a8.QC) |
317 | 317 | NET_ALIAS(d2, ic_a8.QD) |
318 | 318 | |
319 | // C5-EN Logic | |
319 | // C5-EN Logic | |
320 | 320 | |
321 | 321 | TTL_7404_INVERT(ic_e3a, 128H) |
322 | 322 | TTL_7427_NOR( ic_e3b, 256H, 64H, ic_e3a.Q) |
r17959 | r17960 | |
327 | 327 | TTL_7425_NOR(ic_f2a, ic_g1a.Q, 64V, 128V, ic_d2c.Q) |
328 | 328 | NET_ALIAS(c5-en, ic_f2a.Q) |
329 | 329 | |
330 | // Score logic ... | |
330 | // Score logic ... | |
331 | 331 | |
332 | 332 | TTL_7402_NOR(ic_f5b, L, Missed) |
333 | 333 | TTL_7490(ic_c7, ic_f5b, SRST, SRST, low, low) |
334 | 334 | TTL_74107(ic_c8a, ic_c7.QD, high, high, SRSTQ) |
335 | 335 | NETDEV_SWITCH2(sw1a, high, ic_c7.QC) |
336 | 336 | NETDEV_PARAM(sw1a.POS, 0) |
337 | TTL_7410_NAND(ic_d8a, ic_c7.QA, sw1a.Q, ic_c8a.Q) // would be nand2 for 11 instead of 15 points, need a switch dev! | |
337 | TTL_7410_NAND(ic_d8a, ic_c7.QA, sw1a.Q, ic_c8a.Q) // would be nand2 for 11 instead of 15 points, need a switch dev! | |
338 | 338 | |
339 | 339 | NET_ALIAS(StopG1Q, ic_d8a.Q) |
340 | 340 | NET_ALIAS(score1_1, ic_c7.QA) |
r17959 | r17960 | |
349 | 349 | TTL_74107(ic_c8b, ic_d7.QD, high, high, SRSTQ) |
350 | 350 | NETDEV_SWITCH2(sw1b, high, ic_d7.QC) |
351 | 351 | NETDEV_PARAM(sw1b.POS, 0) |
352 | TTL_7410_NAND(ic_d8b, ic_d7.QA, sw1b.Q, ic_c8b.Q) // would be nand2 for 11 instead of 15 points, need a switch dev! | |
352 | TTL_7410_NAND(ic_d8b, ic_d7.QA, sw1b.Q, ic_c8b.Q) // would be nand2 for 11 instead of 15 points, need a switch dev! | |
353 | 353 | |
354 | 354 | NET_ALIAS(StopG2Q, ic_d8b.Q) |
355 | 355 | NET_ALIAS(score2_1, ic_d7.QA) |
r17959 | r17960 | |
359 | 359 | NET_ALIAS(score2_10, ic_c8b.Q) |
360 | 360 | NET_ALIAS(score2_10Q, ic_c8b.QQ) |
361 | 361 | |
362 | // Score display | |
362 | // Score display | |
363 | 363 | |
364 | 364 | TTL_74153(ic_d6a, score1_10Q, score1_4, score2_10Q, score2_4, 32H, 64H, low) |
365 | 365 | TTL_74153(ic_d6b, score1_10Q, score1_8, score2_10Q, score2_8, 32H, 64H, low) |
r17959 | r17960 | |
397 | 397 | TTL_7430_NAND(ic_d3, ic_d4a, ic_d5c, ic_c4c, ic_d5a, ic_d4c, ic_d4b, ic_d5b, high) |
398 | 398 | NET_ALIAS(score, ic_d3.Q) //FIXME |
399 | 399 | |
400 | // net | |
400 | // net | |
401 | 401 | TTL_74107(ic_f3b, clk, 256H, 256HQ, high) |
402 | 402 | TTL_7400_NAND(ic_g3b, ic_f3b.QQ, 256H) |
403 | 403 | TTL_7427_NOR(ic_g2b, ic_g3b.Q, vblank, 4V) |
404 | 404 | NET_ALIAS(net, ic_g2b.Q) |
405 | 405 | |
406 | // video | |
406 | // video | |
407 | 407 | TTL_7402_NOR(ic_g1b, hvidQ, vvidQ) |
408 | 408 | TTL_7425_NOR(ic_f2b, ic_g1b.Q, pad1, pad2, net) |
409 | 409 | TTL_7404_INVERT(ic_e4e, ic_f2b.Q) |
r17959 | r17960 | |
675 | 675 | PORT_START("VR2") |
676 | 676 | PORT_ADJUSTER( 63, "VR2 - 50k, Paddle 2 adjustment" ) PORT_CHANGED_MEMBER(DEVICE_SELF, pong_state, input_changed, IC_VR2) |
677 | 677 | //PORT_START("GATESPEED") |
678 | //PORT_ADJUSTER( 100, "Logic Gate Delay" ) PORT_MINMAX(10, 200) | |
678 | //PORT_ADJUSTER( 100, "Logic Gate Delay" ) PORT_MINMAX(10, 200) PORT_CHANGED_MEMBER(DEVICE_SELF, pong_state, input_changed, IC_GATEDELAY) | |
679 | 679 | |
680 | 680 | INPUT_PORTS_END |
681 | 681 |
r17959 | r17960 | |
---|---|---|
918 | 918 | pic8259_ir1_w(drvstate->m_pic8259_1, state); |
919 | 919 | } |
920 | 920 | |
921 | static const ide_config ide_intf = | |
921 | static const ide_config ide_intf = | |
922 | 922 | { |
923 | ide_interrupt, | |
924 | NULL, | |
923 | ide_interrupt, | |
924 | NULL, | |
925 | 925 | 0 |
926 | 926 | }; |
927 | 927 |
r17959 | r17960 | |
---|---|---|
442 | 442 | |
443 | 443 | |
444 | 444 | |
445 | struct dynamic_address | |
445 | struct dynamic_address | |
446 | 446 | { |
447 | 447 | offs_t start; |
448 | 448 | offs_t end; |
r17959 | r17960 | |
2222 | 2222 | SYSTEM_CLOCK /* system clock rate */ |
2223 | 2223 | }; |
2224 | 2224 | |
2225 | static const ide_config ide_intf = | |
2225 | static const ide_config ide_intf = | |
2226 | 2226 | { |
2227 | ide_interrupt, | |
2228 | "maincpu", | |
2227 | ide_interrupt, | |
2228 | "maincpu", | |
2229 | 2229 | AS_PROGRAM |
2230 | 2230 | }; |
2231 | 2231 | |
2232 | static const smc91c9x_config ethernet_intf = | |
2232 | static const smc91c9x_config ethernet_intf = | |
2233 | 2233 | { |
2234 | 2234 | ethernet_interrupt |
2235 | 2235 | }; |
2236 | 2236 | |
2237 | 2237 | static const voodoo_config voodoo_intf = |
2238 | 2238 | { |
2239 | 2, // fbmem; | |
2240 | 4,// tmumem0; | |
2241 | 4,// tmumem1; | |
2242 | "screen",// screen; | |
2243 | "maincpu",// cputag; | |
2244 | vblank_assert,// vblank; | |
2245 | NULL,// stall; | |
2239 | 2, // fbmem; | |
2240 | 4,// tmumem0; | |
2241 | 4,// tmumem1; | |
2242 | "screen",// screen; | |
2243 | "maincpu",// cputag; | |
2244 | vblank_assert,// vblank; | |
2245 | NULL,// stall; | |
2246 | 2246 | }; |
2247 | 2247 | |
2248 | 2248 | static MACHINE_CONFIG_START( vegascore, vegas_state ) |
r17959 | r17960 | |
2292 | 2292 | |
2293 | 2293 | static const voodoo_config vegasban_voodoo_intf = |
2294 | 2294 | { |
2295 | 16, // fbmem; | |
2296 | 0,// tmumem0; | |
2297 | 0,// tmumem1; | |
2298 | "screen",// screen; | |
2299 | "maincpu",// cputag; | |
2300 | vblank_assert,// vblank; | |
2301 | NULL,// stall; | |
2295 | 16, // fbmem; | |
2296 | 0,// tmumem0; | |
2297 | 0,// tmumem1; | |
2298 | "screen",// screen; | |
2299 | "maincpu",// cputag; | |
2300 | vblank_assert,// vblank; | |
2301 | NULL,// stall; | |
2302 | 2302 | }; |
2303 | 2303 | static MACHINE_CONFIG_DERIVED( vegasban, vegascore ) |
2304 | 2304 | MCFG_FRAGMENT_ADD(dcs2_audio_2104) |
r17959 | r17960 | |
2307 | 2307 | MCFG_CPU_PROGRAM_MAP(vegas_map_32mb) |
2308 | 2308 | |
2309 | 2309 | MCFG_DEVICE_REMOVE("voodoo") |
2310 | MCFG_3DFX_VOODOO_BANSHEE_ADD("voodoo", STD_VOODOO_BANSHEE_CLOCK, vegasban_voodoo_intf) | |
2310 | MCFG_3DFX_VOODOO_BANSHEE_ADD("voodoo", STD_VOODOO_BANSHEE_CLOCK, vegasban_voodoo_intf) | |
2311 | 2311 | MACHINE_CONFIG_END |
2312 | 2312 | |
2313 | 2313 |
r17959 | r17960 | |
---|---|---|
901 | 901 | |
902 | 902 | static const voodoo_config voodoo_1_intf = |
903 | 903 | { |
904 | 2, // fbmem; | |
905 | 4,// tmumem0; | |
906 | 0,// tmumem1; | |
907 | "screen",// screen; | |
908 | "mips",// cputag; | |
909 | NULL,// vblank; | |
910 | NULL,// stall; | |
904 | 2, // fbmem; | |
905 | 4,// tmumem0; | |
906 | 0,// tmumem1; | |
907 | "screen",// screen; | |
908 | "mips",// cputag; | |
909 | NULL,// vblank; | |
910 | NULL,// stall; | |
911 | 911 | }; |
912 | 912 | |
913 | 913 | static const voodoo_config voodoo_2_intf = |
914 | 914 | { |
915 | 2, // fbmem; | |
916 | 4,// tmumem0; | |
917 | 0,// tmumem1; | |
918 | "screen",// screen; | |
919 | "mips",// cputag; | |
920 | NULL,//vblank_assert vblank; | |
921 | NULL,// voodoo_stall stall; | |
915 | 2, // fbmem; | |
916 | 4,// tmumem0; | |
917 | 0,// tmumem1; | |
918 | "screen",// screen; | |
919 | "mips",// cputag; | |
920 | NULL,//vblank_assert vblank; | |
921 | NULL,// voodoo_stall stall; | |
922 | 922 | }; |
923 | 923 | /************************************* |
924 | 924 | * |
r17959 | r17960 | |
---|---|---|
240 | 240 | * Sound interface |
241 | 241 | * |
242 | 242 | *************************************/ |
243 | ||
244 | ||
243 | ||
244 | ||
245 | 245 | //------------------------------------------------- |
246 | 246 | // sn76496_config psg_intf |
247 | 247 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
678 | 678 | machine().root_device().membank("video_bank2")->set_base(machine().root_device().memregion("video_bios")->base() + 0x4000); |
679 | 679 | } |
680 | 680 | |
681 | static const ide_config ide_intf = | |
681 | static const ide_config ide_intf = | |
682 | 682 | { |
683 | ide_interrupt, | |
684 | NULL, | |
683 | ide_interrupt, | |
684 | NULL, | |
685 | 685 | 0 |
686 | 686 | }; |
687 | 687 |
r17959 | r17960 | |
---|---|---|
885 | 885 | |
886 | 886 | static const voodoo_config voodoo_l_intf = |
887 | 887 | { |
888 | 2, // fbmem; | |
889 | 2,// tmumem0; | |
890 | 2,// tmumem1; | |
891 | "lscreen",// screen; | |
892 | "dsp",// cputag; | |
893 | voodoo_vblank_0,// vblank; | |
894 | NULL,// stall; | |
888 | 2, // fbmem; | |
889 | 2,// tmumem0; | |
890 | 2,// tmumem1; | |
891 | "lscreen",// screen; | |
892 | "dsp",// cputag; | |
893 | voodoo_vblank_0,// vblank; | |
894 | NULL,// stall; | |
895 | 895 | }; |
896 | 896 | |
897 | 897 | static const voodoo_config voodoo_r_intf = |
898 | 898 | { |
899 | 2, // fbmem; | |
900 | 2,// tmumem0; | |
901 | 2,// tmumem1; | |
902 | "rscreen",// screen; | |
903 | "dsp2",// cputag; | |
904 | voodoo_vblank_1,// vblank; | |
905 | NULL,// stall; | |
899 | 2, // fbmem; | |
900 | 2,// tmumem0; | |
901 | 2,// tmumem1; | |
902 | "rscreen",// screen; | |
903 | "dsp2",// cputag; | |
904 | voodoo_vblank_1,// vblank; | |
905 | NULL,// stall; | |
906 | 906 | }; |
907 | 907 | |
908 | 908 | static MACHINE_CONFIG_START( hangplt, gticlub_state ) |
r17959 | r17960 | |
---|---|---|
6046 | 6046 | MCFG_SOUND_ADD("snsnd", SN76489_NEW, PSG_CLOCK) |
6047 | 6047 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) |
6048 | 6048 | MCFG_SOUND_CONFIG(psg_intf) |
6049 | ||
6049 | ||
6050 | 6050 | MCFG_SOUND_ADD("aysnd", AY8910, AY_CLOCK) |
6051 | 6051 | MCFG_SOUND_CONFIG(ay8910_config) |
6052 | 6052 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50) |
r17959 | r17960 | |
---|---|---|
1 | 1 | /****************************************************************************************** |
2 | Pinball | |
2 | Pinball | |
3 | 3 | Valley Spectra IV |
4 | 4 | ----------------- |
5 | 5 | Rotating game, like Midway's "Rotation VIII". |
r17959 | r17960 | |
---|---|---|
862 | 862 | 1 /* stereo */ |
863 | 863 | }; |
864 | 864 | |
865 | const namco_06xx_config polepos_namco_06xx_intf = | |
865 | const namco_06xx_config polepos_namco_06xx_intf = | |
866 | 866 | { |
867 | 867 | "maincpu", "51xx", "53xx", "52xx", "54xx" |
868 | 868 | }; |
869 | 869 | |
870 | const namco_54xx_config polepos_namco_54xx_intf = | |
870 | const namco_54xx_config polepos_namco_54xx_intf = | |
871 | 871 | { |
872 | 872 | "discrete", NODE_01 |
873 | 873 | }; |
r17959 | r17960 | |
953 | 953 | } |
954 | 954 | }; |
955 | 955 | |
956 | const namco_06xx_config topracern_namco_06xx_intf = | |
956 | const namco_06xx_config topracern_namco_06xx_intf = | |
957 | 957 | { |
958 | 958 | "maincpu", "51xx", NULL, NULL, NULL |
959 | 959 | }; |
r17959 | r17960 | |
---|---|---|
665 | 665 | * Machine driver |
666 | 666 | * |
667 | 667 | *************************************/ |
668 | static const ide_config ide_intf = | |
668 | static const ide_config ide_intf = | |
669 | 669 | { |
670 | ide_interrupt, | |
671 | NULL, | |
670 | ide_interrupt, | |
671 | NULL, | |
672 | 672 | 0 |
673 | 673 | }; |
674 | 674 | |
r17959 | r17960 | |
707 | 707 | MCFG_SOUND_ROUTE(1, "rspeaker", 1.0) |
708 | 708 | MACHINE_CONFIG_END |
709 | 709 | |
710 | static const ide_config qdrmfgp2_ide_intf = | |
710 | static const ide_config qdrmfgp2_ide_intf = | |
711 | 711 | { |
712 | gp2_ide_interrupt, | |
713 | NULL, | |
712 | gp2_ide_interrupt, | |
713 | NULL, | |
714 | 714 | 0 |
715 | 715 | }; |
716 | 716 | static MACHINE_CONFIG_START( qdrmfgp2, qdrmfgp_state ) |
r17959 | r17960 | |
---|---|---|
253 | 253 | * Sound interface |
254 | 254 | * |
255 | 255 | *************************************/ |
256 | ||
257 | ||
256 | ||
257 | ||
258 | 258 | //------------------------------------------------- |
259 | 259 | // sn76496_config psg_intf |
260 | 260 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
819 | 819 | * Sound interface |
820 | 820 | * |
821 | 821 | *************************************/ |
822 | ||
823 | ||
822 | ||
823 | ||
824 | 824 | //------------------------------------------------- |
825 | 825 | // sn76496_config psg_intf |
826 | 826 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
308 | 308 | /* How does the protection work? |
309 | 309 | |
310 | 310 | We know in World Rally it shares the whole of main RAM with the Dallas, with subtle reads and writes / values being checked.. so I guess this will be similar at least |
311 | and thus very hard to figure out if done properly | |
311 | and thus very hard to figure out if done properly | |
312 | 312 | |
313 | 313 | */ |
314 | 314 | |
r17959 | r17960 | |
323 | 323 | |
324 | 324 | // there are also various code segments like the one below |
325 | 325 | /* |
326 | start: | |
327 | tst.b this address | |
328 | bne end | |
329 | tst.b $fede1d.l | |
330 | nop << why? | |
331 | bne start | |
332 | end: | |
333 | */ | |
326 | start: | |
327 | tst.b this address | |
328 | bne end | |
329 | tst.b $fede1d.l | |
330 | nop << why? | |
331 | bne start | |
332 | end: | |
333 | */ | |
334 | 334 | return 0x0000; |
335 | 335 | //printf("%06x read %06x - %04x %04x\n", pc , (offset*2 + 0xfec000), ret, mem_mask); |
336 | 336 | } |
r17959 | r17960 | |
354 | 354 | |
355 | 355 | if (offset == (0xfede02 - 0xfec000)>>1) |
356 | 356 | { |
357 | // | |
357 | // printf("%06x write %06x - %04x %04x\n", pc, (offset*2 + 0xfec000), data, mem_mask); | |
358 | 358 | // several checks write here then expect it to appear mirrored, might be some kind of command + command ack |
359 | 359 | if (mem_mask & 0xff00) // sometimes mask 0xff00, but not in cases which poll for change |
360 | 360 | { |
r17959 | r17960 | |
390 | 390 | } |
391 | 391 | |
392 | 392 | } |
393 | ||
394 | 393 | |
394 | ||
395 | 395 | DRIVER_INIT_MEMBER(glass_state,glass) |
396 | 396 | { |
397 | 397 | /* |
r17959 | r17960 | |
---|---|---|
2520 | 2520 | SYSTEM_CLOCK /* system clock rate */ |
2521 | 2521 | }; |
2522 | 2522 | |
2523 | static const ide_config ide_intf = | |
2523 | static const ide_config ide_intf = | |
2524 | 2524 | { |
2525 | ide_interrupt, | |
2526 | "maincpu", | |
2525 | ide_interrupt, | |
2526 | "maincpu", | |
2527 | 2527 | AS_PROGRAM |
2528 | 2528 | }; |
2529 | 2529 | |
2530 | 2530 | static const voodoo_config voodoo_intf = |
2531 | 2531 | { |
2532 | 2, // fbmem; | |
2533 | 4,// tmumem0; | |
2534 | 0,// tmumem1; | |
2535 | "screen",// screen; | |
2536 | "maincpu",// cputag; | |
2537 | vblank_assert,// vblank; | |
2538 | voodoo_stall,// stall; | |
2532 | 2, // fbmem; | |
2533 | 4,// tmumem0; | |
2534 | 0,// tmumem1; | |
2535 | "screen",// screen; | |
2536 | "maincpu",// cputag; | |
2537 | vblank_assert,// vblank; | |
2538 | voodoo_stall,// stall; | |
2539 | 2539 | }; |
2540 | 2540 | |
2541 | 2541 | static MACHINE_CONFIG_START( seattle_common, seattle_state ) |
r17959 | r17960 | |
2579 | 2579 | MCFG_CPU_PROGRAM_MAP(seattle_map) |
2580 | 2580 | MACHINE_CONFIG_END |
2581 | 2581 | |
2582 | static const smc91c9x_config ethernet_intf = | |
2582 | static const smc91c9x_config ethernet_intf = | |
2583 | 2583 | { |
2584 | 2584 | ethernet_interrupt |
2585 | 2585 | }; |
r17959 | r17960 | |
2604 | 2604 | |
2605 | 2605 | static const voodoo_config voodoo_2_intf = |
2606 | 2606 | { |
2607 | 2, // fbmem; | |
2608 | 4,// tmumem0; | |
2609 | 4,// tmumem1; | |
2610 | "screen",// screen; | |
2611 | "maincpu",// cputag; | |
2612 | vblank_assert,// vblank; | |
2613 | voodoo_stall,// stall; | |
2607 | 2, // fbmem; | |
2608 | 4,// tmumem0; | |
2609 | 4,// tmumem1; | |
2610 | "screen",// screen; | |
2611 | "maincpu",// cputag; | |
2612 | vblank_assert,// vblank; | |
2613 | voodoo_stall,// stall; | |
2614 | 2614 | }; |
2615 | 2615 | |
2616 | 2616 | static MACHINE_CONFIG_DERIVED( flagstaff, seattle_common ) |
r17959 | r17960 | |
---|---|---|
2145 | 2145 | * Sound interface |
2146 | 2146 | * |
2147 | 2147 | *************************************/ |
2148 | ||
2149 | ||
2148 | ||
2149 | ||
2150 | 2150 | //------------------------------------------------- |
2151 | 2151 | // sn76496_config psg_intf |
2152 | 2152 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
303 | 303 | * Sound interface |
304 | 304 | * |
305 | 305 | *************************************/ |
306 | ||
307 | ||
306 | ||
307 | ||
308 | 308 | //------------------------------------------------- |
309 | 309 | // sn76496_config psg_intf |
310 | 310 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
1037 | 1037 | MCFG_FRAGMENT_ADD(dcs_audio_2k) |
1038 | 1038 | MACHINE_CONFIG_END |
1039 | 1039 | |
1040 | static const ide_config ide_intf = | |
1040 | static const ide_config ide_intf = | |
1041 | 1041 | { |
1042 | NULL, | |
1043 | NULL, | |
1042 | NULL, | |
1043 | NULL, | |
1044 | 1044 | 0 |
1045 | 1045 | }; |
1046 | 1046 |
r17959 | r17960 | |
---|---|---|
121 | 121 | #include "firebeat.lh" |
122 | 122 | |
123 | 123 | |
124 | struct GCU_REGS | |
124 | struct GCU_REGS | |
125 | 125 | { |
126 | 126 | UINT32 *vram; |
127 | 127 | UINT32 vram_read_address; |
r17959 | r17960 | |
129 | 129 | UINT32 visible_area; |
130 | 130 | }; |
131 | 131 | |
132 | struct IBUTTON_SUBKEY | |
132 | struct IBUTTON_SUBKEY | |
133 | 133 | { |
134 | 134 | UINT8 identifier[8]; |
135 | 135 | UINT8 password[8]; |
136 | 136 | UINT8 data[0x30]; |
137 | 137 | }; |
138 | 138 | |
139 | struct IBUTTON | |
139 | struct IBUTTON | |
140 | 140 | { |
141 | 141 | IBUTTON_SUBKEY subkey[3]; |
142 | 142 | }; |
r17959 | r17960 | |
---|---|---|
271 | 271 | * Sound interface |
272 | 272 | * |
273 | 273 | *************************************/ |
274 | ||
275 | ||
274 | ||
275 | ||
276 | 276 | //------------------------------------------------- |
277 | 277 | // sn76496_config psg_intf |
278 | 278 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
304 | 304 | // d6, d7: play counter? (it only triggers on 1st coin) |
305 | 305 | coin_counter_w(machine(), 0, (data & 0x40) ? 1 : 0); |
306 | 306 | coin_counter_w(machine(), 1, (data & 0x80) ? 1 : 0); |
307 | ||
307 | ||
308 | 308 | // other bits: ? |
309 | 309 | } |
310 | 310 |
r17959 | r17960 | |
---|---|---|
1653 | 1653 | device->execute().set_input_line(0, ASSERT_LINE); |
1654 | 1654 | } |
1655 | 1655 | |
1656 | const namco_06xx_config bosco_namco_06xx_0_intf = | |
1656 | const namco_06xx_config bosco_namco_06xx_0_intf = | |
1657 | 1657 | { |
1658 | 1658 | "maincpu", "51xx", NULL, "50xx_1", "54xx" |
1659 | 1659 | }; |
1660 | 1660 | |
1661 | const namco_06xx_config bosco_namco_06xx_1_intf = | |
1661 | const namco_06xx_config bosco_namco_06xx_1_intf = | |
1662 | 1662 | { |
1663 | 1663 | "sub", "50xx_2", "52xx", NULL, NULL |
1664 | 1664 | }; |
1665 | 1665 | |
1666 | const namco_54xx_config namco_54xx_intf = | |
1666 | const namco_54xx_config namco_54xx_intf = | |
1667 | 1667 | { |
1668 | 1668 | "discrete", NODE_01 |
1669 | 1669 | }; |
r17959 | r17960 | |
1723 | 1723 | MACHINE_CONFIG_END |
1724 | 1724 | |
1725 | 1725 | |
1726 | const namco_06xx_config galaga_namco_06xx_intf = | |
1726 | const namco_06xx_config galaga_namco_06xx_intf = | |
1727 | 1727 | { |
1728 | 1728 | "maincpu", "51xx", NULL, NULL, "54xx" |
1729 | 1729 | }; |
r17959 | r17960 | |
1778 | 1778 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90) |
1779 | 1779 | MACHINE_CONFIG_END |
1780 | 1780 | |
1781 | const namco_06xx_config galagab_namco_06xx_intf = | |
1781 | const namco_06xx_config galagab_namco_06xx_intf = | |
1782 | 1782 | { |
1783 | 1783 | "maincpu", "51xx", NULL, NULL, NULL |
1784 | 1784 | }; |
r17959 | r17960 | |
1800 | 1800 | MCFG_DEVICE_REMOVE("discrete") |
1801 | 1801 | MACHINE_CONFIG_END |
1802 | 1802 | |
1803 | const namco_06xx_config xevious_namco_06xx_intf = | |
1803 | const namco_06xx_config xevious_namco_06xx_intf = | |
1804 | 1804 | { |
1805 | 1805 | "maincpu", "51xx", NULL, "50xx", "54xx" |
1806 | 1806 | }; |
r17959 | r17960 | |
1855 | 1855 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90) |
1856 | 1856 | MACHINE_CONFIG_END |
1857 | 1857 | |
1858 | const namco_06xx_config battles_namco_06xx_intf = | |
1858 | const namco_06xx_config battles_namco_06xx_intf = | |
1859 | 1859 | { |
1860 | 1860 | "maincpu", "51xx", NULL, NULL, NULL |
1861 | 1861 | }; |
r17959 | r17960 | |
1889 | 1889 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) |
1890 | 1890 | MACHINE_CONFIG_END |
1891 | 1891 | |
1892 | const namco_06xx_config digdug_namco_06xx_intf = | |
1892 | const namco_06xx_config digdug_namco_06xx_intf = | |
1893 | 1893 | { |
1894 | 1894 | "maincpu", "51xx", "53xx", NULL, NULL |
1895 | 1895 | }; |
r17959 | r17960 | |
---|---|---|
463 | 463 | * Sound interface |
464 | 464 | * |
465 | 465 | *************************************/ |
466 | ||
467 | ||
466 | ||
467 | ||
468 | 468 | //------------------------------------------------- |
469 | 469 | // sn76496_config psg_intf |
470 | 470 | //------------------------------------------------- |
r17959 | r17960 | |
480 | 480 | |
481 | 481 | m_maincpu = machine().device<cpu_device>("maincpu"); |
482 | 482 | m_audiocpu = machine().device<cpu_device>("audiocpu"); |
483 | ||
483 | ||
484 | 484 | save_item(NAME(m_gfxbank)); |
485 | 485 | } |
486 | 486 |
r17959 | r17960 | |
---|---|---|
1 | 1 | /*************************************************************************** |
2 | 2 | |
3 | ||
3 | Nintendo Super System | |
4 | 4 | |
5 | ||
5 | driver by Angelo Salese, based off info from Noca$h | |
6 | 6 | |
7 | TODO: | |
8 | - EEPROM doesn't save? | |
9 | - Fix sound CPU halt / reset lines, particularly needed by this to work | |
10 | correctly; | |
11 | - Fix continue behaviour, might be the same issue as the one above. | |
12 | - Various M50458 bits | |
13 | - OSD should actually super-impose with the SNES video somehow; | |
7 | TODO: | |
8 | - EEPROM doesn't save? | |
9 | - Fix sound CPU halt / reset lines, particularly needed by this to work | |
10 | correctly; | |
11 | - Fix continue behaviour, might be the same issue as the one above. | |
12 | - Various M50458 bits | |
13 | - OSD should actually super-impose with the SNES video somehow; | |
14 | 14 | |
15 | Notes: | |
16 | - Multi-Cart BIOS works only with F-Zero, Super Tennis and Super Mario | |
17 | World; | |
15 | Notes: | |
16 | - Multi-Cart BIOS works only with F-Zero, Super Tennis and Super Mario | |
17 | World; | |
18 | 18 | |
19 | 19 | *************************************************************************** |
20 | 20 | |
r17959 | r17960 | |
505 | 505 | READ8_MEMBER(nss_state::port_00_r) |
506 | 506 | { |
507 | 507 | /* |
508 | x--- ---- SNES Watchdog (0=SNES did read Joypads, 1=Didn't do so) (ack via 07h.W) | |
509 | -x-- ---- Vblank or Vsync or so (0=What, 1=What?) | |
510 | --x- ---- Button "Joypad Button B?" (0=Released, 1=Pressed) | |
511 | ---x ---- Button "Joypad Button A" (0=Released, 1=Pressed) | |
512 | ---- x--- Button "Joypad Down" (0=Released, 1=Pressed) | |
513 | ---- -x-- Button "Joypad Up" (0=Released, 1=Pressed) | |
514 | ---- --x- Button "Joypad Left" (0=Released, 1=Pressed) | |
515 | ---- ---x Button "Joypad Right" (0=Released, 1=Pressed) | |
508 | x--- ---- SNES Watchdog (0=SNES did read Joypads, 1=Didn't do so) (ack via 07h.W) | |
509 | -x-- ---- Vblank or Vsync or so (0=What, 1=What?) | |
510 | --x- ---- Button "Joypad Button B?" (0=Released, 1=Pressed) | |
511 | ---x ---- Button "Joypad Button A" (0=Released, 1=Pressed) | |
512 | ---- x--- Button "Joypad Down" (0=Released, 1=Pressed) | |
513 | ---- -x-- Button "Joypad Up" (0=Released, 1=Pressed) | |
514 | ---- --x- Button "Joypad Left" (0=Released, 1=Pressed) | |
515 | ---- ---x Button "Joypad Right" (0=Released, 1=Pressed) | |
516 | 516 | */ |
517 | 517 | UINT8 res; |
518 | 518 | |
r17959 | r17960 | |
531 | 531 | WRITE8_MEMBER(nss_state::port_00_w) |
532 | 532 | { |
533 | 533 | /* |
534 | xxxx ---- Unknown/unused (should be always 0) | |
535 | ---- x--- Maybe SNES CPU/PPU reset (usually same as Port 01h.W.Bit1) | |
536 | ---- -x-- RAM at 9000h-9FFFh (0=Disable/Protect, 1=Enable/Unlock) | |
537 | ---- --x- Looks like maybe somehow NMI Related ? ;\or one of these is PC10-style | |
538 | ---- ---x Looks like NMI Enable ;/hardware-watchdog reload? | |
534 | xxxx ---- Unknown/unused (should be always 0) | |
535 | ---- x--- Maybe SNES CPU/PPU reset (usually same as Port 01h.W.Bit1) | |
536 | ---- -x-- RAM at 9000h-9FFFh (0=Disable/Protect, 1=Enable/Unlock) | |
537 | ---- --x- Looks like maybe somehow NMI Related ? ;\or one of these is PC10-style | |
538 | ---- ---x Looks like NMI Enable ;/hardware-watchdog reload? | |
539 | 539 | */ |
540 | 540 | m_wram_wp_flag = (data & 4) >> 2; |
541 | 541 | m_nmi_enable = data & 1; |
r17959 | r17960 | |
545 | 545 | WRITE8_MEMBER(nss_state::port_01_w) |
546 | 546 | { |
547 | 547 | /* |
548 | x--- ---- Maybe SNES Joypad Enable? (0=Disable/Demo, 1=Enable/Game) | |
549 | -x-- ---- Unknown/unused (should be always 0) | |
550 | --x- ---- SNES Sound Mute (0=Normal, 1=Mute) (for optional mute in demo mode) | |
551 | ---x ---- Unknown ;from INST-ROM flag! (Lo/HiROM, 2-player, zapper, volume or so?) | |
552 | ---- xx-- Slot Select (0..2 for Slot 1..3) (mapping to both SNES and Z80) | |
553 | ---- --x- Maybe SNES CPU pause? (cleared on deposit coin to continue) (1=Run) | |
554 | ---- ---x Maybe SNES CPU/PPU reset? (0=Reset, 1=Run) | |
548 | x--- ---- Maybe SNES Joypad Enable? (0=Disable/Demo, 1=Enable/Game) | |
549 | -x-- ---- Unknown/unused (should be always 0) | |
550 | --x- ---- SNES Sound Mute (0=Normal, 1=Mute) (for optional mute in demo mode) | |
551 | ---x ---- Unknown ;from INST-ROM flag! (Lo/HiROM, 2-player, zapper, volume or so?) | |
552 | ---- xx-- Slot Select (0..2 for Slot 1..3) (mapping to both SNES and Z80) | |
553 | ---- --x- Maybe SNES CPU pause? (cleared on deposit coin to continue) (1=Run) | |
554 | ---- ---x Maybe SNES CPU/PPU reset? (0=Reset, 1=Run) | |
555 | 555 | */ |
556 | 556 | m_input_disabled = ((data & 0x80) >> 7) ^ 1; |
557 | 557 | spc700_set_volume(machine().device("spc700"),data & 0x20 ? 0.0 : 100.0); |
r17959 | r17960 | |
570 | 570 | WRITE8_MEMBER(nss_state::port_02_w) |
571 | 571 | { |
572 | 572 | /* |
573 | x--- ---- OSD Clock ? (usually same as Bit6) ;\Chip Select when Bit6=Bit7 ? | |
574 | -x-- ---- OSD Clock ? (usually same as Bit7) ;/ | |
575 | --x- ---- OSD Data Out (0=Low=Zero, 1=High=One) | |
576 | ---x ---- OSD Special (?) ... or just /CS ? (or software index DC3F/DD3F?) | |
577 | ---- x--- RTC /CLK (0=Low=Clock, 1=High=Idle) ;S-3520 | |
578 | ---- -x-- RTC Data Out (0=Low=Zero, 1=High=One) | |
579 | ---- --x- RTC Direction (0=Low=Write, 1=High=Read) | |
580 | ---- ---x RTC /CS (0=Low/Select, 1=High/No) | |
573 | x--- ---- OSD Clock ? (usually same as Bit6) ;\Chip Select when Bit6=Bit7 ? | |
574 | -x-- ---- OSD Clock ? (usually same as Bit7) ;/ | |
575 | --x- ---- OSD Data Out (0=Low=Zero, 1=High=One) | |
576 | ---x ---- OSD Special (?) ... or just /CS ? (or software index DC3F/DD3F?) | |
577 | ---- x--- RTC /CLK (0=Low=Clock, 1=High=Idle) ;S-3520 | |
578 | ---- -x-- RTC Data Out (0=Low=Zero, 1=High=One) | |
579 | ---- --x- RTC Direction (0=Low=Write, 1=High=Read) | |
580 | ---- ---x RTC /CS (0=Low/Select, 1=High/No) | |
581 | 581 | */ |
582 | // | |
582 | // printf("%02x\n",data & 0xf); | |
583 | 583 | ioport("RTC_OSD")->write(data, 0xff); |
584 | 584 | } |
585 | 585 | |
586 | 586 | WRITE8_MEMBER(nss_state::port_03_w) |
587 | 587 | { |
588 | 588 | /* |
589 | x--- ---- Layer SNES Enable? (used by token proc, see 7A46h) SNES? | |
590 | -x-- ---- Layer OSD Enable? | |
591 | --xx ---- Unknown/unused (should be always 0) | |
592 | ---- x--- LED Instructions (0=Off, 1=On) ;-glows in demo (prompt for INST button) | |
593 | ---- -x-- LED Game 3 (0=Off, 1=On) ;\ | |
594 | ---- --x- LED Game 2 (0=Off, 1=On) ; blinked when enough credits inserted | |
595 | ---- ---x LED Game 1 (0=Off, 1=On) ;/ | |
589 | x--- ---- Layer SNES Enable? (used by token proc, see 7A46h) SNES? | |
590 | -x-- ---- Layer OSD Enable? | |
591 | --xx ---- Unknown/unused (should be always 0) | |
592 | ---- x--- LED Instructions (0=Off, 1=On) ;-glows in demo (prompt for INST button) | |
593 | ---- -x-- LED Game 3 (0=Off, 1=On) ;\ | |
594 | ---- --x- LED Game 2 (0=Off, 1=On) ; blinked when enough credits inserted | |
595 | ---- ---x LED Game 1 (0=Off, 1=On) ;/ | |
596 | 596 | |
597 | 597 | */ |
598 | // | |
598 | // popmessage("%02x",data); | |
599 | 599 | } |
600 | 600 | |
601 | 601 | WRITE8_MEMBER(nss_state::port_04_w) |
r17959 | r17960 | |
---|---|---|
1760 | 1760 | MCFG_PALETTE_LENGTH(0x2000) |
1761 | 1761 | |
1762 | 1762 | MCFG_VIDEO_START_OVERRIDE(namcos2_state, finallap) |
1763 | ||
1763 | ||
1764 | 1764 | MCFG_NAMCO_C45_ROAD_ADD("c45_road") |
1765 | 1765 | |
1766 | 1766 | MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") |
r17959 | r17960 | |
---|---|---|
447 | 447 | * Sound interface |
448 | 448 | * |
449 | 449 | *************************************/ |
450 | ||
451 | ||
450 | ||
451 | ||
452 | 452 | //------------------------------------------------- |
453 | 453 | // sn76496_config psg_intf |
454 | 454 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
350 | 350 | * Sound interface |
351 | 351 | * |
352 | 352 | *************************************/ |
353 | ||
354 | ||
353 | ||
354 | ||
355 | 355 | //------------------------------------------------- |
356 | 356 | // sn76496_config psg_intf |
357 | 357 | //------------------------------------------------- |
r17959 | r17960 | |
400 | 400 | MCFG_SOUND_ADD("sn1", SN76496_NEW, 18432000/6) |
401 | 401 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) |
402 | 402 | MCFG_SOUND_CONFIG(psg_intf) |
403 | ||
403 | ||
404 | 404 | MCFG_SOUND_ADD("sn2", SN76496_NEW, 18432000/6) |
405 | 405 | MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) |
406 | 406 | MCFG_SOUND_CONFIG(psg_intf) |
r17959 | r17960 | |
---|---|---|
618 | 618 | } |
619 | 619 | #endif |
620 | 620 | |
621 | static const ide_config ide_intf = | |
621 | static const ide_config ide_intf = | |
622 | 622 | { |
623 | ide_interrupt, | |
624 | NULL, | |
623 | ide_interrupt, | |
624 | NULL, | |
625 | 625 | 0 |
626 | 626 | }; |
627 | 627 |
r17959 | r17960 | |
---|---|---|
938 | 938 | } |
939 | 939 | } |
940 | 940 | |
941 | static const ide_config ide_intf = | |
941 | static const ide_config ide_intf = | |
942 | 942 | { |
943 | NULL, | |
944 | NULL, | |
943 | NULL, | |
944 | NULL, | |
945 | 945 | 0 |
946 | 946 | }; |
947 | 947 |
r17959 | r17960 | |
---|---|---|
152 | 152 | * Sound interface |
153 | 153 | * |
154 | 154 | *************************************/ |
155 | ||
156 | ||
155 | ||
156 | ||
157 | 157 | //------------------------------------------------- |
158 | 158 | // sn76496_config psg_intf |
159 | 159 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
1140 | 1140 | return 0; |
1141 | 1141 | } |
1142 | 1142 | |
1143 | static const ide_config ide_intf = | |
1143 | static const ide_config ide_intf = | |
1144 | 1144 | { |
1145 | ide_interrupt, | |
1146 | NULL, | |
1145 | ide_interrupt, | |
1146 | NULL, | |
1147 | 1147 | 0 |
1148 | 1148 | }; |
1149 | 1149 | |
1150 | 1150 | static const voodoo_config voodoo_intf = |
1151 | 1151 | { |
1152 | 2, // fbmem; | |
1153 | 4,// tmumem0; | |
1154 | 0,// tmumem1; | |
1155 | "screen",// screen; | |
1156 | "maincpu",// cputag; | |
1157 | NULL,// vblank; | |
1158 | NULL,// stall; | |
1152 | 2, // fbmem; | |
1153 | 4,// tmumem0; | |
1154 | 0,// tmumem1; | |
1155 | "screen",// screen; | |
1156 | "maincpu",// cputag; | |
1157 | NULL,// vblank; | |
1158 | NULL,// stall; | |
1159 | 1159 | }; |
1160 | 1160 | |
1161 | 1161 | static MACHINE_CONFIG_START( funkball, funkball_state ) |
r17959 | r17960 | |
---|---|---|
167 | 167 | PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test 4") PORT_CODE(KEYCODE_N) |
168 | 168 | PORT_START("Y5") |
169 | 169 | PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("END") PORT_CODE(KEYCODE_END) |
170 | PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test 10") | |
171 | PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test 9") | |
170 | PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test 10") | |
171 | PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test 9") | |
172 | 172 | PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Test 8") PORT_CODE(KEYCODE_STOP) |
173 | 173 | INPUT_PORTS_END |
174 | 174 |
r17959 | r17960 | |
---|---|---|
583 | 583 | READ8_MEMBER(peplus_state::peplus_input0_r) |
584 | 584 | { |
585 | 585 | /* |
586 | ||
586 | PE+ bill validators have a dip switch setting to switch between ID-022 and ID-023 protocols. | |
587 | 587 | |
588 | 588 | Emulating IGT IDO22 Pulse Protocol (IGT Smoke 2.2) |
589 | ID022 protocol requires a 20ms on/off pulse x times for denomination followed by a 50ms stop pulse. | |
590 | The DBV then waits for at least 3 toggling (ACK) pulses of alternating 20ms each from the game. | |
591 | If no toggling received within 200ms, the bill was rejected by the game (e.g. Max Credits reached). | |
592 | Once toggling received, the DBV stacks the bill and sends a 10ms stacked pulses. | |
589 | ID022 protocol requires a 20ms on/off pulse x times for denomination followed by a 50ms stop pulse. | |
590 | The DBV then waits for at least 3 toggling (ACK) pulses of alternating 20ms each from the game. | |
591 | If no toggling received within 200ms, the bill was rejected by the game (e.g. Max Credits reached). | |
592 | Once toggling received, the DBV stacks the bill and sends a 10ms stacked pulses. | |
593 | 593 | |
594 | 594 | Emulating IGT IDO23 Pulse Protocol (IGT 2.5) |
595 | ID023 protocol requires a start pulse of 50ms ON followed by a 20ms pause. Next a 15-bit data stream | |
596 | is sent based on the country code and denomination (see table below). And finally a 90ms stop pulse. | |
597 | There is then a 200ms pause and the entire sequence is transmitted again two more times. | |
598 | The DBV then waits for the toggling much like the ID-022 protocol above, however ends with two 10ms | |
599 | stack pulses instead of one. | |
595 | ID023 protocol requires a start pulse of 50ms ON followed by a 20ms pause. Next a 15-bit data stream | |
596 | is sent based on the country code and denomination (see table below). And finally a 90ms stop pulse. | |
597 | There is then a 200ms pause and the entire sequence is transmitted again two more times. | |
598 | The DBV then waits for the toggling much like the ID-022 protocol above, however ends with two 10ms | |
599 | stack pulses instead of one. | |
600 | 600 | |
601 | ||
601 | Ticket handling has not been emulated. | |
602 | 602 | |
603 | ||
603 | IDO23 Country Codes | |
604 | 604 | ------------------- |
605 | ||
605 | 0x07 = Canada | |
606 | 606 | 0x25 = USA |
607 | 607 | |
608 | 608 | IDO23 USA 15-bit Data Samples: |
609 | ---------+--------------+--------------+-----------+ | |
610 | Bill Amt | Country Code | Denom Code | Checksum | | |
611 | 609 | ---------+--------------+--------------+-----------+ |
610 | Bill Amt | Country Code | Denom Code | Checksum | | |
611 | ---------+--------------+--------------+-----------+ | |
612 | 612 | $1 | 1 0 0 1 0 1 | 0 0 1 1 0 | 1 1 0 0 | |
613 | ||
613 | $2 | 1 0 0 1 0 1 | 0 0 1 1 1 | 1 0 1 1 | | |
614 | 614 | $5 | 1 0 0 1 0 1 | 0 0 1 0 0 | 1 0 1 1 | |
615 | 615 | $10 | 1 0 0 1 0 1 | 0 0 1 0 1 | 1 0 1 0 | |
616 | 616 | $20 | 1 0 0 1 0 1 | 0 0 0 1 0 | 1 0 1 1 | |
617 | 617 | $50 | 1 0 0 1 0 1 | 0 0 0 0 0 | 1 0 1 0 | |
618 | 618 | $100 | 1 0 0 1 0 1 | 0 0 0 0 1 | 1 0 0 1 | |
619 | Ticket | 1 0 0 1 0 1 | 0 0 0 1 1 | 1 0 1 0 | | |
620 | ---------+--------------+--------------+-----------+ | |
619 | Ticket | 1 0 0 1 0 1 | 0 0 0 1 1 | 1 0 1 0 | | |
620 | ---------+--------------+--------------+-----------+ | |
621 | 621 | |
622 | 622 | Direction Data |
623 | 623 | -------------- |
r17959 | r17960 | |
643 | 643 | if (m_bv_protocol == 0) { |
644 | 644 | // ID-022 |
645 | 645 | m_bv_denomination = id_022[m_bv_denomination]; |
646 | ||
646 | ||
647 | 647 | if (m_bv_denomination == 0) |
648 | 648 | m_bv_state = 0x03; // $1 So Skip Credit Pulse |
649 | 649 | else |
r17959 | r17960 | |
657 | 657 | |
658 | 658 | m_bv_state = 0x11; |
659 | 659 | } |
660 | ||
661 | m_bv_cycles = curr_cycles; | |
660 | ||
661 | m_bv_cycles = curr_cycles; | |
662 | 662 | m_bv_pulse = 1; |
663 | 663 | m_bv_enable_count = 0; |
664 | 664 | } |
r17959 | r17960 | |
682 | 682 | m_bv_pulse = 1; |
683 | 683 | |
684 | 684 | m_bv_denomination--; |
685 | ||
685 | ||
686 | 686 | if (m_bv_denomination == 0) |
687 | 687 | m_bv_state++; // Done with Credit Pulse |
688 | 688 | else |
r17959 | r17960 | |
1130 | 1130 | PORT_CONFSETTING( 0x04, "$20" ) |
1131 | 1131 | PORT_CONFSETTING( 0x05, "$50" ) |
1132 | 1132 | PORT_CONFSETTING( 0x06, "$100" ) |
1133 | ||
1133 | ||
1134 | 1134 | PORT_START("BP") |
1135 | 1135 | PORT_CONFNAME( 0x1f, 0x00, "Bill Protocol" ) |
1136 | 1136 | PORT_CONFSETTING( 0x00, "ID-022" ) |
r17959 | r17960 | |
---|---|---|
233 | 233 | * Sound interface |
234 | 234 | * |
235 | 235 | *************************************/ |
236 | ||
237 | ||
236 | ||
237 | ||
238 | 238 | //------------------------------------------------- |
239 | 239 | // sn76496_config psg_intf |
240 | 240 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
3660 | 3660 | } |
3661 | 3661 | } |
3662 | 3662 | |
3663 | struct GXGameInfoT | |
3663 | struct GXGameInfoT | |
3664 | 3664 | { |
3665 | 3665 | const char *romname; |
3666 | 3666 | UINT32 cfgport; |
r17959 | r17960 | |
---|---|---|
384 | 384 | * Sound interface |
385 | 385 | * |
386 | 386 | *************************************/ |
387 | ||
388 | ||
387 | ||
388 | ||
389 | 389 | //------------------------------------------------- |
390 | 390 | // sn76496_config psg_intf |
391 | 391 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
1128 | 1128 | * Sound interface |
1129 | 1129 | * |
1130 | 1130 | *************************************/ |
1131 | ||
1132 | ||
1131 | ||
1132 | ||
1133 | 1133 | //------------------------------------------------- |
1134 | 1134 | // sn76496_config psg_intf |
1135 | 1135 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
687 | 687 | } |
688 | 688 | }; |
689 | 689 | |
690 | static const ide_config ide_intf = | |
690 | static const ide_config ide_intf = | |
691 | 691 | { |
692 | ide_interrupt, | |
693 | NULL, | |
692 | ide_interrupt, | |
693 | NULL, | |
694 | 694 | 0 |
695 | 695 | }; |
696 | 696 |
r17959 | r17960 | |
---|---|---|
7123 | 7123 | MCFG_CPU_ADD("maincpu", M68000, 16000000) // no obvious CPU, but seems to be clocked faster than an original system16 based on the boot times |
7124 | 7124 | MCFG_CPU_PROGRAM_MAP(isgsm_map) |
7125 | 7125 | MCFG_CPU_VBLANK_INT("screen", irq4_line_hold) |
7126 | ||
7126 | ||
7127 | 7127 | MACHINE_CONFIG_END |
7128 | 7128 | |
7129 | 7129 | DRIVER_INIT_MEMBER(isgsm_state,isgsm) |
r17959 | r17960 | |
---|---|---|
711 | 711 | |
712 | 712 | static const voodoo_config voodoo_intf = |
713 | 713 | { |
714 | 2, // fbmem; | |
715 | 2,// tmumem0; | |
716 | 2,// tmumem1; | |
717 | "screen",// screen; | |
718 | "dsp",// cputag; | |
719 | voodoo_vblank_0,// vblank; | |
720 | NULL,// stall; | |
714 | 2, // fbmem; | |
715 | 2,// tmumem0; | |
716 | 2,// tmumem1; | |
717 | "screen",// screen; | |
718 | "dsp",// cputag; | |
719 | voodoo_vblank_0,// vblank; | |
720 | NULL,// stall; | |
721 | 721 | }; |
722 | 722 | |
723 | 723 | static MACHINE_CONFIG_START( nwktr, nwktr_state ) |
r17959 | r17960 | |
---|---|---|
10 | 10 | *weird* hardware - based on NES version |
11 | 11 | (gfx bank changed in the middle of screen, |
12 | 12 | sprites in NES format etc) |
13 | ||
13 | ||
14 | 14 | homerun and ganjaja use an extra soundchip for playing voice/samples |
15 | ||
15 | ||
16 | 16 | Todo : |
17 | 17 | - dump homerun sample rom |
18 | 18 | - improve controls/dips |
r17959 | r17960 | |
---|---|---|
191 | 191 | #include "cpu/powerpc/ppc.h" |
192 | 192 | |
193 | 193 | |
194 | struct CDE_DMA | |
194 | struct CDE_DMA | |
195 | 195 | { |
196 | 196 | UINT32 dst_addr; |
197 | 197 | int length; |
r17959 | r17960 | |
498 | 498 | memcpy(&state->m_cde_toc, toc, sizeof(cdrom_toc)); |
499 | 499 | |
500 | 500 | /* |
501 | printf("%d tracks\n", toc->numtrks); | |
502 | for (int i=0; i < toc->numtrks; i++) | |
503 | { | |
504 | const cdrom_track_info *track = &toc->tracks[i]; | |
505 | printf("Track %d: type %d, subtype %d, datasize %d, subsize %d, frames %d, extraframes %d, physframeofs %d\n", | |
506 | i, track->trktype, track->subtype, track->datasize, track->subsize,track->frames, track->extraframes, track->physframeofs); | |
507 | } | |
508 | */ | |
501 | printf("%d tracks\n", toc->numtrks); | |
502 | for (int i=0; i < toc->numtrks; i++) | |
503 | { | |
504 | const cdrom_track_info *track = &toc->tracks[i]; | |
505 | printf("Track %d: type %d, subtype %d, datasize %d, subsize %d, frames %d, extraframes %d, physframeofs %d\n", | |
506 | i, track->trktype, track->subtype, track->datasize, track->subsize,track->frames, track->extraframes, track->physframeofs); | |
507 | } | |
508 | */ | |
509 | 509 | |
510 | 510 | cdrom_close(cdfile); |
511 | 511 | } |
r17959 | r17960 | |
---|---|---|
227 | 227 | {14, CNoOutputEnableFuseRow, 240, 264}, |
228 | 228 | {15, CNoOutputEnableFuseRow, 192, 216}, |
229 | 229 | {16, CNoOutputEnableFuseRow, 144, 168}, |
230 | {17, CNoOutputEnableFuseRow, 96, 120}, | |
230 | {17, CNoOutputEnableFuseRow, 96, 120}, | |
231 | 231 | {18, CNoOutputEnableFuseRow, 0, 72}}; |
232 | 232 | |
233 | 233 | static pin_fuse_rows pal12h6pinfuserows[] = { |
r17959 | r17960 | |
235 | 235 | {14, CNoOutputEnableFuseRow, 240, 264}, |
236 | 236 | {15, CNoOutputEnableFuseRow, 192, 216}, |
237 | 237 | {16, CNoOutputEnableFuseRow, 144, 168}, |
238 | {17, CNoOutputEnableFuseRow, 96, 120}, | |
238 | {17, CNoOutputEnableFuseRow, 96, 120}, | |
239 | 239 | {18, CNoOutputEnableFuseRow, 0, 72}}; |
240 | 240 | |
241 | 241 | static pin_fuse_rows pal14l4pinfuserows[] = { |
r17959 | r17960 | |
529 | 529 | {5, 13, 12}, |
530 | 530 | {6, 17, 16}, |
531 | 531 | {7, 21, 20}, |
532 | {8, 25, 24}, | |
532 | {8, 25, 24}, | |
533 | 533 | {9, 29, 28}, |
534 | 534 | {12, 31, 30}, |
535 | 535 | {13, 27, 26}, |
r17959 | r17960 | |
1702 | 1702 | else |
1703 | 1703 | { |
1704 | 1704 | fprintf(stderr, "Viewing product terms not supported for this pal type."); |
1705 | ||
1705 | ||
1706 | 1706 | return 1; |
1707 | 1707 | } |
1708 | 1708 |
r17959 | r17960 | |
---|---|---|
8 | 8 | #define CREATE_NETDEV(name) class netdev *name(const char *ifname, class device_network_interface *ifdev, int rate) |
9 | 9 | typedef class netdev *(*create_netdev)(const char *ifname, class device_network_interface *ifdev, int rate); |
10 | 10 | |
11 | struct netdev_entry_t | |
11 | struct netdev_entry_t | |
12 | 12 | { |
13 | 13 | int id; |
14 | 14 | char name[256]; |
r17959 | r17960 | |
---|---|---|
38 | 38 | ***************************************************************************/ |
39 | 39 | |
40 | 40 | extern const char build_version[]; |
41 | const char build_version[] = "0.14 | |
41 | const char build_version[] = "0.147 |
r17959 | r17960 | |
---|---|---|
446 | 446 | { |
447 | 447 | int size = io_generic_size(io); |
448 | 448 | UINT8 h[32]; |
449 | ||
449 | ||
450 | 450 | io_generic_read(io, h, 0, 32); |
451 | 451 | if((LITTLE_ENDIANIZE_INT32(*(UINT32 *)(h+0x1c)) == size) && |
452 | 452 | (h[0x1b] == 0x00 || h[0x1b] == 0x10 || h[0x1b] == 0x20 || h[0x1b] == 0x30 || h[0x1b] == 0x40)) |
r17959 | r17960 | |
458 | 458 | bool d88_format::load(io_generic *io, UINT32 form_factor, floppy_image *image) |
459 | 459 | { |
460 | 460 | UINT8 h[32]; |
461 | ||
461 | ||
462 | 462 | io_generic_read(io, h, 0, 32); |
463 | 463 | |
464 | 464 | int cell_count = 0; |
r17959 | r17960 | |
---|---|---|
2449 | 2449 | } else |
2450 | 2450 | memset(sd, 0, sector_size); |
2451 | 2451 | } |
2452 | } | |
No newline at end of file | ||
2452 | } |
r17959 | r17960 | |
---|---|---|
11 | 11 | |
12 | 12 | #include "cassimg.h" |
13 | 13 | |
14 | struct ace_tape_t | |
14 | struct ace_tape_t | |
15 | 15 | { |
16 | 16 | UINT8 hdr_type; |
17 | 17 | UINT8 hdr_name[10]; |
r17959 | r17960 | |
---|---|---|
1 | 1 | /********************************************************************* |
2 | 2 | |
3 | ||
3 | formats/xdf_dsk.h | |
4 | 4 | |
5 | ||
5 | x68k bare-bones formats | |
6 | 6 | |
7 | 7 | *********************************************************************/ |
8 | 8 |
r17959 | r17960 | |
---|---|---|
91 | 91 | #define OPTION_ENUM_END |
92 | 92 | |
93 | 93 | |
94 | enum optreserr_t | |
94 | enum optreserr_t | |
95 | 95 | { |
96 | 96 | OPTIONRESOLUTION_ERROR_SUCCESS, |
97 | 97 | OPTIONRESOLUTION_ERROR_OUTOFMEMORY, |
r17959 | r17960 | |
---|---|---|
76 | 76 | rectangle() { } |
77 | 77 | rectangle(INT32 minx, INT32 maxx, INT32 miny, INT32 maxy) |
78 | 78 | : min_x(minx), max_x(maxx), min_y(miny), max_y(maxy) { } |
79 | ||
79 | ||
80 | 80 | // getters |
81 | 81 | INT32 left() const { return min_x; } |
82 | 82 | INT32 right() const { return max_x; } |
r17959 | r17960 | |
102 | 102 | if (src.max_y > max_y) max_y = src.max_y; |
103 | 103 | return *this; |
104 | 104 | } |
105 | ||
105 | ||
106 | 106 | // comparisons |
107 | 107 | bool operator==(const rectangle &rhs) const { return min_x == rhs.min_x && max_x == rhs.max_x && min_y == rhs.min_y && max_y == rhs.max_y; } |
108 | 108 | bool operator!=(const rectangle &rhs) const { return min_x != rhs.min_x || max_x != rhs.max_x || min_y != rhs.min_y || max_y != rhs.max_y; } |
r17959 | r17960 | |
128 | 128 | void set_height(INT32 height) { max_y = min_y + height - 1; } |
129 | 129 | void set_origin(INT32 x, INT32 y) { max_x += x - min_x; max_y += y - min_y; min_x = x; min_y = y; } |
130 | 130 | void set_size(INT32 width, INT32 height) { set_width(width); set_height(height); } |
131 | ||
131 | ||
132 | 132 | // offset helpers |
133 | 133 | void offset(INT32 xdelta, INT32 ydelta) { min_x += xdelta; max_x += xdelta; min_y += ydelta; max_y += ydelta; } |
134 | 134 | void offsetx(INT32 delta) { min_x += delta; max_x += delta; } |
r17959 | r17960 | |
---|---|---|
813 | 813 | } |
814 | 814 | |
815 | 815 | //------------------------------------------------- |
816 | // options_count - take number of existing | |
816 | // options_count - take number of existing | |
817 | 817 | // number of options in structure |
818 | 818 | //------------------------------------------------- |
819 | 819 | |
r17959 | r17960 | |
822 | 822 | int number = 0; |
823 | 823 | for (entry *curentry = m_entrylist; curentry != NULL; curentry = curentry->next()) number++; |
824 | 824 | return number; |
825 | } | |
No newline at end of file | ||
825 | } |
r17959 | r17960 | |
---|---|---|
71 | 71 | // compute a rectangle in dirty space, and fill it with 1 |
72 | 72 | rectangle rect(left >> m_granularity, right >> m_granularity, top >> m_granularity, bottom >> m_granularity); |
73 | 73 | m_bitmap.fill(1, rect); |
74 | ||
74 | ||
75 | 75 | // invalidate existing rect list |
76 | 76 | invalidate_rect_list(); |
77 | 77 | } |
r17959 | r17960 | |
93 | 93 | // compute a rectangle in dirty space, and fill it with 0 |
94 | 94 | rectangle rect((left + round) >> m_granularity, (right - round) >> m_granularity, (top + round) >> m_granularity, (bottom - round) >> m_granularity); |
95 | 95 | m_bitmap.fill(0, rect); |
96 | ||
96 | ||
97 | 97 | // invalidate existing rect list |
98 | 98 | invalidate_rect_list(); |
99 | 99 | } |
r17959 | r17960 | |
108 | 108 | // set new size |
109 | 109 | m_width = width; |
110 | 110 | m_height = height; |
111 | ||
111 | ||
112 | 112 | // resize the bitmap |
113 | 113 | int round = (1 << m_granularity) - 1; |
114 | 114 | m_bitmap.resize((width + round) >> m_granularity, (height + round) >> m_granularity); |
115 | ||
115 | ||
116 | 116 | // reset everything |
117 | 117 | dirty_all(); |
118 | 118 | } |
r17959 | r17960 | |
120 | 120 | |
121 | 121 | //------------------------------------------------- |
122 | 122 | // first_dirty_rect -- return the first dirty |
123 | // | |
123 | // rectangle in the list | |
124 | 124 | //------------------------------------------------- |
125 | 125 | |
126 | 126 | sparse_dirty_rect *sparse_dirty_bitmap::first_dirty_rect(const rectangle &cliprect) |
r17959 | r17960 | |
128 | 128 | // if what we have is valid, just return it again |
129 | 129 | if (m_rect_list_bounds == cliprect) |
130 | 130 | return m_rect_list.first(); |
131 | ||
131 | ||
132 | 132 | // reclaim the dirty list and start over |
133 | 133 | m_rect_allocator.reclaim_all(m_rect_list); |
134 | ||
134 | ||
135 | 135 | // compute dirty space rectangle coordinates |
136 | 136 | int sx = cliprect.min_x >> m_granularity; |
137 | 137 | int ex = cliprect.max_x >> m_granularity; |
r17959 | r17960 | |
156 | 156 | currect = NULL; |
157 | 157 | continue; |
158 | 158 | } |
159 | ||
159 | ||
160 | 160 | // if we can't add to an existing rect, create a new one |
161 | 161 | if (currect == NULL) |
162 | 162 | { |
r17959 | r17960 | |
---|---|---|
45 | 45 | }; |
46 | 46 | |
47 | 47 | /* 6805 Registers */ |
48 | struct m6805_Regs | |
48 | struct m6805_Regs | |
49 | 49 | { |
50 | 50 | /* Pre-pointerafied public globals */ |
51 | 51 | int iCount; |
r17959 | r17960 | |
---|---|---|
24 | 24 | |
25 | 25 | #include "lh5801.h" |
26 | 26 | |
27 | enum Adr | |
27 | enum Adr | |
28 | 28 | { |
29 | 29 | Imp, |
30 | 30 | Reg, |
r17959 | r17960 | |
46 | 46 | RelM |
47 | 47 | }; |
48 | 48 | |
49 | enum Regs | |
49 | enum Regs | |
50 | 50 | { |
51 | 51 | RegNone, |
52 | 52 | A, |
r17959 | r17960 | |
64 | 64 | #undef SEC |
65 | 65 | #endif |
66 | 66 | |
67 | enum Ins | |
67 | enum Ins | |
68 | 68 | { |
69 | 69 | ILL, ILL2, PREFD, NOP, |
70 | 70 |
r17959 | r17960 | |
---|---|---|
20 | 20 | #include "m6809.h" |
21 | 21 | |
22 | 22 | // Opcode structure |
23 | struct opcodeinfo | |
23 | struct opcodeinfo | |
24 | 24 | { |
25 | 25 | UINT8 opcode; // 8-bit opcode value |
26 | 26 | UINT8 length; // Opcode length in bytes |
r17959 | r17960 | |
---|---|---|
11 | 11 | |
12 | 12 | #define H8_MAX_PORTS (16) // number of I/O ports defined architecturally (1-9 and A-G = 16) |
13 | 13 | |
14 | struct H8S2XXX_TPU_ITEM | |
14 | struct H8S2XXX_TPU_ITEM | |
15 | 15 | { |
16 | 16 | UINT32 tgr, irq, out; |
17 | 17 | }; |
18 | 18 | |
19 | struct H8S2XXX_TPU | |
19 | struct H8S2XXX_TPU | |
20 | 20 | { |
21 | 21 | emu_timer *timer; |
22 | 22 | int cycles_per_tick; |
23 | 23 | UINT64 timer_cycles; |
24 | 24 | }; |
25 | 25 | |
26 | struct H8S2XXX_SCI | |
26 | struct H8S2XXX_SCI | |
27 | 27 | { |
28 | 28 | emu_timer *timer; |
29 | 29 | UINT32 bitrate; |
30 | 30 | }; |
31 | 31 | |
32 | struct H8S2XXX_TMR | |
32 | struct H8S2XXX_TMR | |
33 | 33 | { |
34 | 34 | emu_timer *timer; |
35 | 35 | int cycles_per_tick; |
r17959 | r17960 | |
---|---|---|
1158 | 1158 | // SERIAL CONTROLLER INTERFACE // |
1159 | 1159 | ///////////////////////////////// |
1160 | 1160 | |
1161 | struct H8S_SCI_ENTRY | |
1161 | struct H8S_SCI_ENTRY | |
1162 | 1162 | { |
1163 | 1163 | UINT32 reg_smr, reg_brr, reg_scr, reg_tdr, reg_ssr, reg_rdr; |
1164 | 1164 | UINT32 reg_pdr, reg_port; |
r17959 | r17960 | |
---|---|---|
61 | 61 | STRUCTS |
62 | 62 | ***************************************************************************/ |
63 | 63 | |
64 | struct op_info | |
64 | struct op_info | |
65 | 65 | { |
66 | 66 | void (*opcode)(am29000_state *); |
67 | 67 | UINT32 flags; |
r17959 | r17960 | |
---|---|---|
75 | 75 | STRUCTURES & TYPEDEFS |
76 | 76 | ***************************************************************************/ |
77 | 77 | |
78 | struct am29000_state | |
78 | struct am29000_state | |
79 | 79 | { |
80 | 80 | INT32 icount; |
81 | 81 | UINT32 pc; |
r17959 | r17960 | |
---|---|---|
128 | 128 | unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ |
129 | 129 | |
130 | 130 | /* This is used to generate the opcode handler jump table */ |
131 | struct opcode_handler_struct | |
131 | struct opcode_handler_struct | |
132 | 132 | { |
133 | 133 | void (*opcode_handler)(m68ki_cpu_core *m68k); /* handler function */ |
134 | 134 | unsigned int mask; /* mask on opcode */ |
r17959 | r17960 | |
---|---|---|
175 | 175 | |
176 | 176 | |
177 | 177 | /* Everything we need to know about an opcode */ |
178 | struct opcode_struct | |
178 | struct opcode_struct | |
179 | 179 | { |
180 | 180 | char name[MAX_NAME_LENGTH]; /* opcode handler name */ |
181 | 181 | unsigned char size; /* Size of operation */ |
r17959 | r17960 | |
192 | 192 | |
193 | 193 | |
194 | 194 | /* All modifications necessary for a specific EA mode of an instruction */ |
195 | struct ea_info_struct | |
195 | struct ea_info_struct | |
196 | 196 | { |
197 | 197 | const char* fname_add; |
198 | 198 | const char* ea_add; |
r17959 | r17960 | |
202 | 202 | |
203 | 203 | |
204 | 204 | /* Holds the body of a function */ |
205 | struct body_struct | |
205 | struct body_struct | |
206 | 206 | { |
207 | 207 | char body[MAX_BODY_LENGTH][MAX_LINE_LENGTH+1]; |
208 | 208 | int length; |
r17959 | r17960 | |
210 | 210 | |
211 | 211 | |
212 | 212 | /* Holds a sequence of search / replace strings */ |
213 | struct replace_struct | |
213 | struct replace_struct | |
214 | 214 | { |
215 | 215 | char replace[MAX_REPLACE_LENGTH][2][MAX_LINE_LENGTH+1]; |
216 | 216 | int length; |
r17959 | r17960 | |
---|---|---|
174 | 174 | static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr); |
175 | 175 | |
176 | 176 | /* used to build opcode handler jump table */ |
177 | struct opcode_struct | |
177 | struct opcode_struct | |
178 | 178 | { |
179 | 179 | void (*opcode_handler)(void); /* handler function */ |
180 | 180 | UINT32 mask; /* mask on opcode */ |
r17959 | r17960 | |
---|---|---|
2 | 2 | #include "debugger.h" |
3 | 3 | #include "superfx.h" |
4 | 4 | |
5 | struct pixelcache_t | |
5 | struct pixelcache_t | |
6 | 6 | { |
7 | 7 | UINT16 offset; |
8 | 8 | UINT8 bitpend; |
9 | 9 | UINT8 data[8]; |
10 | 10 | }; |
11 | 11 | |
12 | struct cache_t | |
12 | struct cache_t | |
13 | 13 | { |
14 | 14 | UINT8 buffer[0x200]; |
15 | 15 | UINT8 valid[0x20]; |
r17959 | r17960 | |
---|---|---|
16 | 16 | |
17 | 17 | #define ADDRESS_24BIT(A) ((A)&0xffffff) |
18 | 18 | |
19 | struct opcode_struct | |
19 | struct opcode_struct | |
20 | 20 | { |
21 | 21 | unsigned char name; |
22 | 22 | unsigned char flag; |
r17959 | r17960 | |
---|---|---|
39 | 39 | SHARC_B12, SHARC_B13, SHARC_B14, SHARC_B15, |
40 | 40 | }; |
41 | 41 | |
42 | struct SHARC_DAG | |
42 | struct SHARC_DAG | |
43 | 43 | { |
44 | 44 | UINT32 i[8]; |
45 | 45 | UINT32 m[8]; |
r17959 | r17960 | |
47 | 47 | UINT32 l[8]; |
48 | 48 | }; |
49 | 49 | |
50 | union SHARC_REG | |
50 | union SHARC_REG | |
51 | 51 | { |
52 | 52 | INT32 r; |
53 | 53 | float f; |
54 | 54 | }; |
55 | 55 | |
56 | struct DMA_REGS | |
56 | struct DMA_REGS | |
57 | 57 | { |
58 | 58 | UINT32 control; |
59 | 59 | UINT32 int_index; |
r17959 | r17960 | |
66 | 66 | UINT32 ext_count; |
67 | 67 | }; |
68 | 68 | |
69 | struct LADDR | |
69 | struct LADDR | |
70 | 70 | { |
71 | 71 | UINT32 addr; |
72 | 72 | UINT32 code; |
73 | 73 | UINT32 loop_type; |
74 | 74 | }; |
75 | 75 | |
76 | struct DMA_OP | |
76 | struct DMA_OP | |
77 | 77 | { |
78 | 78 | UINT32 src; |
79 | 79 | UINT32 dst; |
r17959 | r17960 | |
580 | 580 | |
581 | 581 | sharc_dma_exec(cpustate, 6); |
582 | 582 | dma_op(cpustate, 6); |
583 | ||
583 | ||
584 | 584 | cpustate->dma_op[6].timer->adjust(attotime::never, 0); |
585 | 585 | break; |
586 | 586 | } |
r17959 | r17960 | |
766 | 766 | } |
767 | 767 | } |
768 | 768 | } |
769 | ||
769 | ||
770 | 770 | sharc_op[(cpustate->opcode >> 39) & 0x1ff](cpustate); |
771 | 771 | |
772 | 772 |
r17959 | r17960 | |
---|---|---|
35 | 35 | } |
36 | 36 | else // Receive from external |
37 | 37 | { |
38 | cpustate->dma_op[channel].src | |
38 | cpustate->dma_op[channel].src | |
39 | 39 | cpustate->dma_op[channel].src_modifier = ext_modifier; |
40 | 40 | cpustate->dma_op[channel].src_count = ext_count; |
41 | 41 | cpustate->dma_op[channel].dst = int_index; |
r17959 | r17960 | |
89 | 89 | int src_modifier = cpustate->dma_op[channel].src_modifier; |
90 | 90 | int dst_modifier = cpustate->dma_op[channel].dst_modifier; |
91 | 91 | int src_count = cpustate->dma_op[channel].src_count; |
92 | //int dst_count | |
92 | //int dst_count = cpustate->dma_op[channel].dst_count; | |
93 | 93 | int pmode = cpustate->dma_op[channel].pmode; |
94 | 94 | |
95 | 95 | //printf("dma_op: %08X, %08X, %08X, %08X, %08X, %08X, %d\n", src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); |
r17959 | r17960 | |
---|---|---|
9 | 9 | #define SHARC_INPUT_FLAG2 5 |
10 | 10 | #define SHARC_INPUT_FLAG3 6 |
11 | 11 | |
12 | enum SHARC_BOOT_MODE | |
12 | enum SHARC_BOOT_MODE | |
13 | 13 | { |
14 | 14 | BOOT_MODE_EPROM, |
15 | 15 | BOOT_MODE_HOST, |
r17959 | r17960 | |
---|---|---|
1 | struct SHARC_OP | |
1 | struct SHARC_OP | |
2 | 2 | { |
3 | 3 | UINT32 op_mask; |
4 | 4 | UINT32 op_bits; |
r17959 | r17960 | |
---|---|---|
69 | 69 | "???", "???", "???", "???", "???", "???", "???", "???" |
70 | 70 | }; |
71 | 71 | |
72 | struct SHARC_DASM_OP | |
72 | struct SHARC_DASM_OP | |
73 | 73 | { |
74 | 74 | UINT32 op_mask; |
75 | 75 | UINT32 op_bits; |
r17959 | r17960 | |
---|---|---|
26 | 26 | /* cpu state */ |
27 | 27 | /***************************************************************************/ |
28 | 28 | /* I86 registers */ |
29 | union i80286basicregs | |
29 | union i80286basicregs | |
30 | 30 | { /* eight general registers */ |
31 | 31 | UINT16 w[8]; /* viewed as 16 bits registers */ |
32 | 32 | UINT8 b[16]; /* or as 8 bit registers */ |
r17959 | r17960 | |
---|---|---|
71 | 71 | STRUCTURES & TYPEDEFS |
72 | 72 | ***************************************************************************/ |
73 | 73 | |
74 | struct cquestsnd_state | |
74 | struct cquestsnd_state | |
75 | 75 | { |
76 | 76 | /* AM2901 internals */ |
77 | 77 | UINT16 ram[16]; |
r17959 | r17960 | |
104 | 104 | }; |
105 | 105 | |
106 | 106 | |
107 | struct cquestrot_state | |
107 | struct cquestrot_state | |
108 | 108 | { |
109 | 109 | /* AM2901 internals */ |
110 | 110 | UINT16 ram[16]; |
r17959 | r17960 | |
146 | 146 | }; |
147 | 147 | |
148 | 148 | |
149 | struct cquestlin_state | |
149 | struct cquestlin_state | |
150 | 150 | { |
151 | 151 | /* 12-bit AM2901 internals */ |
152 | 152 | UINT16 ram[16]; |
r17959 | r17960 | |
---|---|---|
11 | 11 | */ |
12 | 12 | |
13 | 13 | // unfortunatly memory configuration differs with internal rom size |
14 | enum UPD7810_TYPE | |
14 | enum UPD7810_TYPE | |
15 | 15 | { |
16 | 16 | TYPE_7801, |
17 | 17 | TYPE_78C05, |
r17959 | r17960 | |
---|---|---|
79 | 79 | */ |
80 | 80 | |
81 | 81 | |
82 | enum Adr | |
82 | enum Adr | |
83 | 83 | { |
84 | 84 | Ill, |
85 | 85 | Imp, |
r17959 | r17960 | |
---|---|---|
20 | 20 | |
21 | 21 | |
22 | 22 | |
23 | struct opcode_struct | |
23 | struct opcode_struct | |
24 | 24 | { |
25 | 25 | unsigned char name; |
26 | 26 | unsigned char args[2]; |
r17959 | r17960 | |
---|---|---|
66 | 66 | #include "spc700.h" |
67 | 67 | |
68 | 68 | /* CPU Structure */ |
69 | struct spc700i_cpu | |
69 | struct spc700i_cpu | |
70 | 70 | { |
71 | 71 | uint a; /* Accumulator */ |
72 | 72 | uint x; /* Index Register X */ |
r17959 | r17960 | |
---|---|---|
236 | 236 | /*************************************************************************** |
237 | 237 | INTERRUPT HANDLING |
238 | 238 | ***************************************************************************/ |
239 | struct dsp56k_irq_data | |
239 | struct dsp56k_irq_data | |
240 | 240 | { |
241 | 241 | UINT16 irq_vector; |
242 | 242 | char irq_source[128]; |
r17959 | r17960 | |
---|---|---|
30 | 30 | STRUCTURES & TYPEDEFS |
31 | 31 | ***************************************************************************/ |
32 | 32 | // 5-4 Host Interface |
33 | struct dsp56k_host_interface | |
33 | struct dsp56k_host_interface | |
34 | 34 | { |
35 | 35 | // **** Dsp56k side **** // |
36 | 36 | // Host Control Register |
r17959 | r17960 | |
65 | 65 | }; |
66 | 66 | |
67 | 67 | // 1-9 ALU |
68 | struct dsp56k_data_alu | |
68 | struct dsp56k_data_alu | |
69 | 69 | { |
70 | 70 | // Four 16-bit input registers (can be accessed as 2 32-bit registers) |
71 | 71 | PAIR x; |
r17959 | r17960 | |
82 | 82 | }; |
83 | 83 | |
84 | 84 | // 1-10 Address Generation Unit (AGU) |
85 | struct dsp56k_agu | |
85 | struct dsp56k_agu | |
86 | 86 | { |
87 | 87 | // Four address registers |
88 | 88 | UINT16 r0; |
r17959 | r17960 | |
112 | 112 | }; |
113 | 113 | |
114 | 114 | // 1-11 Program Control Unit (PCU) |
115 | struct dsp56k_pcu | |
115 | struct dsp56k_pcu | |
116 | 116 | { |
117 | 117 | // Program Counter |
118 | 118 | UINT16 pc; |
r17959 | r17960 | |
149 | 149 | }; |
150 | 150 | |
151 | 151 | // 1-8 The dsp56156 CORE |
152 | struct dsp56k_core | |
152 | struct dsp56k_core | |
153 | 153 | { |
154 | 154 | // PROGRAM CONTROLLER |
155 | 155 | dsp56k_pcu PCU; |
r17959 | r17960 | |
---|---|---|
25 | 25 | #include "hd6309.h" |
26 | 26 | |
27 | 27 | // Opcode structure |
28 | struct opcodeinfo | |
28 | struct opcodeinfo | |
29 | 29 | { |
30 | 30 | UINT8 opcode; // 8-bit opcode value |
31 | 31 | UINT8 length; // Opcode length in bytes |
r17959 | r17960 | |
---|---|---|
374 | 374 | }; |
375 | 375 | |
376 | 376 | |
377 | struct decode_tbl_t | |
377 | struct decode_tbl_t | |
378 | 378 | { |
379 | 379 | /* Disassembly function for this opcode. |
380 | 380 | Call with buffer, mnemonic, pc, insn. */ |
r17959 | r17960 | |
---|---|---|
19 | 19 | |
20 | 20 | enum SREGS { ES, CS, SS, DS, FS, GS }; |
21 | 21 | |
22 | enum BREGS | |
22 | enum BREGS | |
23 | 23 | { |
24 | 24 | AL = NATIVE_ENDIAN_VALUE_LE_BE(0,3), |
25 | 25 | AH = NATIVE_ENDIAN_VALUE_LE_BE(1,2), |
r17959 | r17960 | |
31 | 31 | BH = NATIVE_ENDIAN_VALUE_LE_BE(13,14) |
32 | 32 | }; |
33 | 33 | |
34 | enum WREGS | |
34 | enum WREGS | |
35 | 35 | { |
36 | 36 | AX = NATIVE_ENDIAN_VALUE_LE_BE(0,1), |
37 | 37 | CX = NATIVE_ENDIAN_VALUE_LE_BE(2,3), |
r17959 | r17960 | |
206 | 206 | bool valid; |
207 | 207 | }; |
208 | 208 | |
209 | struct I386_CALL_GATE | |
209 | struct I386_CALL_GATE | |
210 | 210 | { |
211 | 211 | UINT16 segment; |
212 | 212 | UINT16 selector; |
r17959 | r17960 | |
---|---|---|
3 | 3 | #ifndef __CYCLES_H__ |
4 | 4 | #define __CYCLES_H__ |
5 | 5 | |
6 | enum X86_CYCLES | |
6 | enum X86_CYCLES | |
7 | 7 | { |
8 | 8 | CYCLES_MOV_REG_REG, |
9 | 9 | CYCLES_MOV_REG_MEM, |
r17959 | r17960 | |
337 | 337 | #define CPU_CYCLES_MEDIAGX 3 |
338 | 338 | |
339 | 339 | |
340 | struct X86_CYCLE_TABLE | |
340 | struct X86_CYCLE_TABLE | |
341 | 341 | { |
342 | 342 | X86_CYCLES op; |
343 | 343 | UINT8 cpu_cycles[X86_NUM_CPUS][2]; |
r17959 | r17960 | |
---|---|---|
32 | 32 | _4, /* for nibble shifts */ |
33 | 33 | }; |
34 | 34 | |
35 | struct hcd62121_dasm | |
35 | struct hcd62121_dasm | |
36 | 36 | { |
37 | 37 | const char *str; |
38 | 38 | UINT8 arg1; |
r17959 | r17960 | |
---|---|---|
3852 | 3852 | } |
3853 | 3853 | |
3854 | 3854 | |
3855 | struct tlcs900inst | |
3855 | struct tlcs900inst | |
3856 | 3856 | { |
3857 | 3857 | void (*opfunc)(tlcs900_state *cpustate); |
3858 | 3858 | int operand1; |
r17959 | r17960 | |
---|---|---|
88 | 88 | }; |
89 | 89 | |
90 | 90 | |
91 | struct tlcs900inst | |
91 | struct tlcs900inst | |
92 | 92 | { |
93 | 93 | e_mnemonics mnemonic; |
94 | 94 | e_operand operand1; |
r17959 | r17960 | |
---|---|---|
1121 | 1121 | case MAKE_OPCODE_SHORT(OP_SHL, 4, 1): |
1122 | 1122 | shift = PARAM2 & 31; |
1123 | 1123 | temp32 = PARAM1 << shift; |
1124 | if (shift != 0) | |
1124 | if (shift != 0) | |
1125 | 1125 | { |
1126 | 1126 | flags = FLAGS32_NZ(temp32); |
1127 | 1127 | flags |= ((PARAM1 << (shift - 1)) >> 31) & FLAG_C; |
r17959 | r17960 | |
1136 | 1136 | case MAKE_OPCODE_SHORT(OP_SHR, 4, 1): |
1137 | 1137 | shift = PARAM2 & 31; |
1138 | 1138 | temp32 = PARAM1 >> shift; |
1139 | if (shift != 0) | |
1139 | if (shift != 0) | |
1140 | 1140 | { |
1141 | 1141 | flags = FLAGS32_NZ(temp32); |
1142 | 1142 | flags |= (PARAM1 >> (shift - 1)) & FLAG_C; |
r17959 | r17960 | |
1167 | 1167 | case MAKE_OPCODE_SHORT(OP_ROL, 4, 1): |
1168 | 1168 | shift = PARAM2 & 31; |
1169 | 1169 | temp32 = (PARAM1 << shift) | (PARAM1 >> ((32 - shift) & 31)); |
1170 | if (shift != 0) | |
1170 | if (shift != 0) | |
1171 | 1171 | { |
1172 | 1172 | flags = FLAGS32_NZ(temp32); |
1173 | 1173 | flags |= ((PARAM1 << (shift - 1)) >> 31) & FLAG_C; |
r17959 | r17960 | |
---|---|---|
138 | 138 | |
139 | 139 | #define RSPDRC_STRICT_VERIFY 0x0001 /* verify all instructions */ |
140 | 140 | |
141 | union VECTOR_REG | |
141 | union VECTOR_REG | |
142 | 142 | { |
143 | 143 | UINT64 d[2]; |
144 | 144 | UINT32 l[4]; |
r17959 | r17960 | |
146 | 146 | UINT8 b[16]; |
147 | 147 | }; |
148 | 148 | |
149 | union ACCUMULATOR_REG | |
149 | union ACCUMULATOR_REG | |
150 | 150 | { |
151 | 151 | INT64 q; |
152 | 152 | INT32 l[2]; |
r17959 | r17960 | |
---|---|---|
147 | 147 | cpustate->wrmem_id.resolve(intf->write_indexed_func, *device); |
148 | 148 | cpustate->in_port_func.resolve(intf->in_port_func, *device); |
149 | 149 | cpustate->out_port_func.resolve(intf->out_port_func, *device); |
150 | ||
150 | ||
151 | 151 | cpustate->pullup = intf->external_port_pullup; |
152 | 152 | cpustate->pulldown = intf->external_port_pulldown; |
153 | 153 | } |
r17959 | r17960 | |
---|---|---|
54 | 54 | |
55 | 55 | /* Optional interface to set callbacks */ |
56 | 56 | #define M6510_INTERFACE(name) \ |
57 | ||
57 | ||
58 | 58 | |
59 | 59 | struct m6502_interface |
60 | 60 | { |
r17959 | r17960 | |
---|---|---|
155 | 155 | devcb_write8 nullwcb = DEVCB_NULL; |
156 | 156 | |
157 | 157 | cpustate->rdmem_id.resolve(nullrcb, *device); |
158 | cpustate->wrmem_id.resolve(nullwcb, *device); | |
158 | cpustate->wrmem_id.resolve(nullwcb, *device); | |
159 | 159 | } |
160 | 160 | } |
161 | 161 |
r17959 | r17960 | |
---|---|---|
227 | 227 | /* Private Data */ |
228 | 228 | |
229 | 229 | /* sArmRegister defines the CPU state */ |
230 | struct ARM_REGS | |
230 | struct ARM_REGS | |
231 | 231 | { |
232 | 232 | int icount; |
233 | 233 | UINT32 sArmRegister[kNumRegisters]; |
r17959 | r17960 | |
---|---|---|
1828 | 1828 | ppc->dcr[DCR4XX_DMASR] |= 1 << (7 - dmachan); |
1829 | 1829 | break; |
1830 | 1830 | } |
1831 | ||
1831 | ||
1832 | 1832 | ppc4xx_dma_update_irq_states(ppc); |
1833 | 1833 | |
1834 | 1834 | INT64 numdata = dmaregs[DCR4XX_DMACT0]; |
r17959 | r17960 | |
1952 | 1952 | dmaregs[DCR4XX_DMADA0] += destinc; |
1953 | 1953 | } while (!ppc4xx_dma_decrement_count(ppc, dmachan)); |
1954 | 1954 | break; |
1955 | } | |
1955 | } | |
1956 | 1956 | } |
1957 | 1957 | } |
1958 | 1958 |
r17959 | r17960 | |
---|---|---|
102 | 102 | * Describes the layout of an instruction. |
103 | 103 | */ |
104 | 104 | |
105 | struct IDESCR | |
105 | struct IDESCR | |
106 | 106 | { |
107 | 107 | char mnem[32]; // mnemonic |
108 | 108 | UINT32 match; // bit pattern of instruction after it has been masked |
r17959 | r17960 | |
---|---|---|
90 | 90 | sh2_exception(sh2,message,irq); \ |
91 | 91 | } while(0) |
92 | 92 | |
93 | struct sh2_state | |
93 | struct sh2_state | |
94 | 94 | { |
95 | 95 | UINT32 ppc; |
96 | 96 | UINT32 pc; |
r17959 | r17960 | |
---|---|---|
46 | 46 | TMS32051_AR7, |
47 | 47 | }; |
48 | 48 | |
49 | struct PMST | |
49 | struct PMST | |
50 | 50 | { |
51 | 51 | UINT16 iptr; |
52 | 52 | UINT16 avis; |
r17959 | r17960 | |
58 | 58 | UINT16 braf; |
59 | 59 | }; |
60 | 60 | |
61 | struct ST0 | |
61 | struct ST0 | |
62 | 62 | { |
63 | 63 | UINT16 dp; |
64 | 64 | UINT16 intm; |
r17959 | r17960 | |
67 | 67 | UINT16 arp; |
68 | 68 | }; |
69 | 69 | |
70 | struct ST1 | |
70 | struct ST1 | |
71 | 71 | { |
72 | 72 | UINT16 arb; |
73 | 73 | UINT16 cnf; |
r17959 | r17960 | |
---|---|---|
49 | 49 | #endif |
50 | 50 | |
51 | 51 | |
52 | struct sh4_state | |
52 | struct sh4_state | |
53 | 53 | { |
54 | 54 | UINT32 ppc; |
55 | 55 | UINT32 pc, spc; |
r17959 | r17960 | |
---|---|---|
26 | 26 | #define ADDRESS_65816(A) ((A)&0xffffff) |
27 | 27 | |
28 | 28 | |
29 | struct opcode_struct | |
29 | struct opcode_struct | |
30 | 30 | { |
31 | 31 | unsigned char name; |
32 | 32 | unsigned char flag; |
r17959 | r17960 | |
---|---|---|
63 | 63 | */ |
64 | 64 | enum format_type {branch, shiftl, shiftr, multiply, store, swap, one_address, two_address}; |
65 | 65 | |
66 | struct instr_desc | |
66 | struct instr_desc | |
67 | 67 | { |
68 | 68 | const char *mnemonic; |
69 | 69 | format_type format; /* -> X and Y are format */ |
r17959 | r17960 | |
---|---|---|
35 | 35 | }; |
36 | 36 | |
37 | 37 | /* interrupt sources */ |
38 | enum INTSOURCES | |
38 | enum INTSOURCES | |
39 | 39 | { |
40 | 40 | BRK = 0, |
41 | 41 | INT_IRQ = 1, |
r17959 | r17960 | |
60 | 60 | }; |
61 | 61 | |
62 | 62 | /* internal RAM and register banks */ |
63 | union internalram | |
63 | union internalram | |
64 | 64 | { |
65 | 65 | UINT16 w[128]; |
66 | 66 | UINT8 b[256]; |
r17959 | r17960 | |
---|---|---|
19 | 19 | }; |
20 | 20 | |
21 | 21 | /* interrupt sources */ |
22 | enum INTSOURCES | |
22 | enum INTSOURCES | |
23 | 23 | { |
24 | 24 | BRK = 0, |
25 | 25 | INT_IRQ = 1, |
r17959 | r17960 | |
27 | 27 | }; |
28 | 28 | |
29 | 29 | /* NEC registers */ |
30 | union necbasicregs | |
30 | union necbasicregs | |
31 | 31 | { /* eight general registers */ |
32 | 32 | UINT16 w[8]; /* viewed as 16 bits registers */ |
33 | 33 | UINT8 b[16]; /* or as 8 bit registers */ |
r17959 | r17960 | |
---|---|---|
24 | 24 | |
25 | 25 | #include "cosmac.h" |
26 | 26 | |
27 | enum Adr | |
27 | enum Adr | |
28 | 28 | { |
29 | 29 | Ill, |
30 | 30 | Imm, |
r17959 | r17960 | |
---|---|---|
86 | 86 | ***************************************************************************/ |
87 | 87 | |
88 | 88 | /* MIPS3 Registers */ |
89 | struct mips3_regs | |
89 | struct mips3_regs | |
90 | 90 | { |
91 | 91 | /* core state */ |
92 | 92 | mips3_state core; |
r17959 | r17960 | |
---|---|---|
61 | 61 | STRUCTURES & TYPEDEFS |
62 | 62 | ***************************************************************************/ |
63 | 63 | |
64 | struct esrip_state | |
64 | struct esrip_state | |
65 | 65 | { |
66 | 66 | UINT16 ram[32]; |
67 | 67 | UINT16 acc; |
r17959 | r17960 | |
---|---|---|
394 | 394 | #define R14 28 |
395 | 395 | #define R15 30 |
396 | 396 | |
397 | struct map_file_t | |
397 | struct map_file_t | |
398 | 398 | { |
399 | 399 | UINT16 L[3], B[3]; /* actual registers */ |
400 | 400 | UINT32 limit[3], bias[3]; /* equivalent in a more convenient form */ |
r17959 | r17960 | |
1993 | 1993 | |
1994 | 1994 | #endif |
1995 | 1995 | |
1996 | enum cru_error_code | |
1996 | enum cru_error_code | |
1997 | 1997 | { |
1998 | 1998 | CRU_OK = 0, |
1999 | 1999 | CRU_PRIVILEGE_VIOLATION = -1 |
r17959 | r17960 | |
---|---|---|
61 | 61 | structure with the parameters ti990_10_reset wants. |
62 | 62 | */ |
63 | 63 | |
64 | struct ti990_10reset_param | |
64 | struct ti990_10reset_param | |
65 | 65 | { |
66 | 66 | ti99xx_idle_func idle_callback; |
67 | 67 | ti99xx_rset_func rset_callback; |
r17959 | r17960 | |
87 | 87 | /* |
88 | 88 | structure with optional parameters for tms9900_reset. |
89 | 89 | */ |
90 | struct tms9900reset_param | |
90 | struct tms9900reset_param | |
91 | 91 | { |
92 | 92 | ti99xx_idle_func idle_callback; |
93 | 93 | }; |
r17959 | r17960 | |
99 | 99 | /* |
100 | 100 | structure with optional parameters for tms9940_reset. |
101 | 101 | */ |
102 | struct tms9940reset_param | |
102 | struct tms9940reset_param | |
103 | 103 | { |
104 | 104 | ti99xx_idle_func idle_callback; |
105 | 105 | }; |
r17959 | r17960 | |
111 | 111 | /* |
112 | 112 | structure with optional parameters for tms9980a_reset. |
113 | 113 | */ |
114 | struct tms9980areset_param | |
114 | struct tms9980areset_param | |
115 | 115 | { |
116 | 116 | ti99xx_idle_func idle_callback; |
117 | 117 | }; |
r17959 | r17960 | |
123 | 123 | /*// |
124 | 124 | structure with optional parameters for tms9985_reset. |
125 | 125 | */ |
126 | struct tms9985reset_param | |
126 | struct tms9985reset_param | |
127 | 127 | { |
128 | 128 | ti99xx_idle_func idle_callback; |
129 | 129 | }; |
r17959 | r17960 | |
135 | 135 | /* |
136 | 136 | structure with optional parameters for tms9989_reset. |
137 | 137 | */ |
138 | struct tms9989reset_param | |
138 | struct tms9989reset_param | |
139 | 139 | { |
140 | 140 | ti99xx_idle_func idle_callback; |
141 | 141 | }; |
r17959 | r17960 | |
147 | 147 | /* |
148 | 148 | structure with the parameters tms9995_reset wants. |
149 | 149 | */ |
150 | struct tms9995reset_param | |
150 | struct tms9995reset_param | |
151 | 151 | { |
152 | 152 | /* auto_wait_state : a non-zero value makes tms9995 generate a wait state automatically on each |
153 | 153 | memory access */ |
r17959 | r17960 | |
175 | 175 | /* |
176 | 176 | structure with optional parameters for tms99000_reset. |
177 | 177 | */ |
178 | struct tms99000reset_param | |
178 | struct tms99000reset_param | |
179 | 179 | { |
180 | 180 | ti99xx_idle_func idle_callback; |
181 | 181 | }; |
r17959 | r17960 | |
187 | 187 | /* |
188 | 188 | structure with optional parameters for tms99105a_reset. |
189 | 189 | */ |
190 | struct tms99105areset_param | |
190 | struct tms99105areset_param | |
191 | 191 | { |
192 | 192 | ti99xx_idle_func idle_callback; |
193 | 193 | }; |
r17959 | r17960 | |
199 | 199 | /* |
200 | 200 | structure with optional parameters for tms99110a_reset. |
201 | 201 | */ |
202 | struct tms99110areset_param | |
202 | struct tms99110areset_param | |
203 | 203 | { |
204 | 204 | ti99xx_idle_func idle_callback; |
205 | 205 | }; |
r17959 | r17960 | |
---|---|---|
27 | 27 | #define MASK 0x0000ffff |
28 | 28 | #define BITS(val,n1,n2) ((val>>(15-(n2))) & (MASK>>(15-((n2)-(n1))))) |
29 | 29 | |
30 | enum format_t | |
30 | enum format_t | |
31 | 31 | { |
32 | 32 | format_1, /* 2 address instructions */ |
33 | 33 | format_2a, /* jump instructions */ |
r17959 | r17960 | |
73 | 73 | sd_11_15 = 0x200 /* bits 11-15 should be cleared in lwpi, limi, idle, rset, rtwp, ckon, ckof, lrex */ |
74 | 74 | }; |
75 | 75 | |
76 | struct description_t | |
76 | struct description_t | |
77 | 77 | { |
78 | 78 | const char *mnemonic; |
79 | 79 | format_t format; |
r17959 | r17960 | |
---|---|---|
60 | 60 | Configuration for the TMS9995. The connections are provided by the |
61 | 61 | main board which contains the processor. |
62 | 62 | */ |
63 | struct tms9995_config | |
63 | struct tms9995_config | |
64 | 64 | { |
65 | 65 | devcb_write8 external_callback; |
66 | 66 | devcb_write_line iaq_line; |
r17959 | r17960 | |
---|---|---|
109 | 109 | "*int" |
110 | 110 | }; |
111 | 111 | |
112 | struct tms99xx_config | |
112 | struct tms99xx_config | |
113 | 113 | { |
114 | 114 | devcb_write8 external_callback; |
115 | 115 | devcb_read8 irq_level; |
r17959 | r17960 | |
---|---|---|
8 | 8 | #include "i960.h" |
9 | 9 | #include "i960dis.h" |
10 | 10 | |
11 | struct mnemonic_t | |
11 | struct mnemonic_t | |
12 | 12 | { |
13 | 13 | const char *mnem; |
14 | 14 | unsigned short type; |
r17959 | r17960 | |
---|---|---|
39 | 39 | OP_RSIR, |
40 | 40 | }; |
41 | 41 | |
42 | struct hd61700_dasm | |
42 | struct hd61700_dasm | |
43 | 43 | { |
44 | 44 | const char *str; |
45 | 45 | UINT8 arg1; |
r17959 | r17960 | |
---|---|---|
23 | 23 | STRUCTURES & TYPEDEFS |
24 | 24 | ***************************************************************************/ |
25 | 25 | |
26 | union MB86233_REG | |
26 | union MB86233_REG | |
27 | 27 | { |
28 | 28 | INT32 i; |
29 | 29 | UINT32 u; |
r17959 | r17960 | |
---|---|---|
185 | 185 | |
186 | 186 | |
187 | 187 | /* CPU state struct */ |
188 | struct arm_state | |
188 | struct arm_state | |
189 | 189 | { |
190 | 190 | ARM7CORE_REGS // these must be included in your cpu specific register implementation |
191 | 191 | ARM7COPRO_REGS |
r17959 | r17960 | |
---|---|---|
37 | 37 | /**************************************************************************** |
38 | 38 | * The 6280 registers. |
39 | 39 | ****************************************************************************/ |
40 | struct h6280_Regs | |
40 | struct h6280_Regs | |
41 | 41 | { |
42 | 42 | int ICount; |
43 | 43 |
r17959 | r17960 | |
---|---|---|
71 | 71 | |
72 | 72 | |
73 | 73 | // don't split branch and return, source relies on this ordering |
74 | enum MNEMONICS | |
74 | enum MNEMONICS | |
75 | 75 | { |
76 | 76 | Return, ReturnSetXM, ReturnSetCarry, ReturnClearCarry, ReturnFromInterrupt, |
77 | 77 | jump3,jump4,jump, |
r17959 | r17960 | |
584 | 584 | AdrImmCount |
585 | 585 | }; |
586 | 586 | |
587 | struct OPCODE | |
587 | struct OPCODE | |
588 | 588 | { |
589 | 589 | opcode_sel sel; |
590 | 590 | opcode_adr adr; |
r17959 | r17960 | |
---|---|---|
55 | 55 | public: |
56 | 56 | // getters |
57 | 57 | const sparse_dirty_rect *next() const { return m_next; } |
58 | ||
58 | ||
59 | 59 | private: |
60 | 60 | // internal state |
61 | 61 | sparse_dirty_rect * m_next; |
r17959 | r17960 | |
75 | 75 | void dirty(const rectangle &rect) { dirty(rect.left(), rect.right(), rect.top(), rect.bottom()); } |
76 | 76 | void dirty(INT32 left, INT32 right, INT32 top, INT32 bottom); |
77 | 77 | void dirty_all() { dirty(0, m_width - 1, 0, m_height - 1); } |
78 | ||
78 | ||
79 | 79 | // cleaning operations - partially intersecting tiles are NOT cleaned |
80 | 80 | void clean(const rectangle &rect) { clean(rect.left(), rect.right(), rect.top(), rect.bottom()); } |
81 | 81 | void clean(INT32 left, INT32 right, INT32 top, INT32 bottom); |
r17959 | r17960 | |
85 | 85 | sparse_dirty_rect *first_dirty_rect() { rectangle fullrect(0, m_width - 1, 0, m_height - 1); return first_dirty_rect(fullrect); } |
86 | 86 | sparse_dirty_rect *first_dirty_rect(const rectangle &cliprect); |
87 | 87 | |
88 | // dynamic resizing | |
88 | // dynamic resizing | |
89 | 89 | void resize(int width, int height); |
90 | ||
90 | ||
91 | 91 | private: |
92 | 92 | // invalidate cached rect list |
93 | 93 | void invalidate_rect_list() { m_rect_list_bounds.set(0, -1, 0, -1); } |
r17959 | r17960 | |
135 | 135 | UINT32 spriteram_bytes() const { return m_spriteram_bytes; } |
136 | 136 | UINT32 spriteram_elements() const { return m_spriteram_bytes / sizeof(_SpriteRAMType); } |
137 | 137 | _SpriteRAMType *buffer() { return &m_buffer[0]; } |
138 | ||
138 | ||
139 | 139 | // static configuration |
140 | 140 | static void static_set_xorigin(device_t &device, int origin) { downcast<sprite_device &>(device).m_xorigin = origin; } |
141 | 141 | static void static_set_yorigin(device_t &device, int origin) { downcast<sprite_device &>(device).m_yorigin = origin; } |
142 | 142 | static void static_set_origin(device_t &device, int xorigin, int yorigin) { static_set_xorigin(device, xorigin); static_set_yorigin(device, yorigin); } |
143 | ||
143 | ||
144 | 144 | // configuration |
145 | 145 | void set_origin(INT32 xorigin = 0, INT32 yorigin = 0) { m_xorigin = xorigin; m_yorigin = yorigin; } |
146 | ||
146 | ||
147 | 147 | // buffering |
148 | 148 | void copy_to_buffer() { memcpy(m_buffer, m_spriteram, m_spriteram_bytes); } |
149 | ||
149 | ||
150 | 150 | // clearing |
151 | 151 | void clear() { clear(m_bitmap.cliprect()); } |
152 | 152 | void clear(const rectangle &cliprect) |
r17959 | r17960 | |
155 | 155 | m_bitmap.fill(~0, *rect); |
156 | 156 | m_dirty.clean(cliprect); |
157 | 157 | } |
158 | ||
158 | ||
159 | 159 | // force clear (don't use dirty rects) |
160 | 160 | void force_clear() |
161 | 161 | { |
r17959 | r17960 | |
174 | 174 | m_bitmap.resize(new_width, new_height, BITMAP_SLOP, BITMAP_SLOP); |
175 | 175 | m_dirty.resize(new_width, new_height); |
176 | 176 | } |
177 | ||
177 | ||
178 | 178 | // clear out the region |
179 | 179 | if (clearit) |
180 | 180 | clear(cliprect); |
181 | ||
181 | ||
182 | 182 | // wrap the bitmap, adjusting for x/y origins |
183 | 183 | _BitmapType wrapped(&m_bitmap.pix(0) - m_xorigin - m_yorigin * m_bitmap.rowpixels(), m_xorigin + cliprect.right() + 1, m_yorigin + cliprect.bottom() + 1, m_bitmap.rowpixels()); |
184 | 184 | |
185 | 185 | // compute adjusted cliprect in source space |
186 | 186 | rectangle adjusted = cliprect; |
187 | 187 | adjusted.offset(m_xorigin, m_yorigin); |
188 | ||
188 | ||
189 | 189 | // render |
190 | 190 | draw(wrapped, adjusted); |
191 | 191 | } |
r17959 | r17960 | |
202 | 202 | // set up pointers |
203 | 203 | m_spriteram = reinterpret_cast<_SpriteRAMType *>(spriteram->ptr()); |
204 | 204 | m_spriteram_bytes = spriteram->bytes(); |
205 | ||
205 | ||
206 | 206 | // allocate the double buffer to match the RAM size |
207 | 207 | m_buffer.resize(m_spriteram_bytes / sizeof(_SpriteRAMType)); |
208 | 208 | |
209 | 209 | // save states |
210 | 210 | save_item(NAME(m_buffer)); |
211 | 211 | } |
212 | ||
212 | ||
213 | 213 | // subclass overrides |
214 | 214 | virtual void draw(_BitmapType &bitmap, const rectangle &cliprect) = 0; |
215 | 215 | |
216 | 216 | // subclass helpers |
217 | 217 | void mark_dirty(const rectangle &rect) { mark_dirty(rect.left(), rect.right(), rect.top(), rect.bottom()); } |
218 | 218 | void mark_dirty(INT32 left, INT32 right, INT32 top, INT32 bottom) { m_dirty.dirty(left - m_xorigin, right - m_xorigin, top - m_yorigin, bottom - m_yorigin); } |
219 | ||
219 | ||
220 | 220 | private: |
221 | 221 | // configuration |
222 | 222 | INT32 m_xorigin; // X origin for drawing |
r17959 | r17960 | |
226 | 226 | _SpriteRAMType * m_spriteram; // pointer to spriteram pointer |
227 | 227 | INT32 m_spriteram_bytes; // size of sprite RAM in bytes |
228 | 228 | dynamic_array<_SpriteRAMType> m_buffer; // buffered spriteram for those that use it |
229 | ||
229 | ||
230 | 230 | // bitmaps |
231 | 231 | _BitmapType m_bitmap; // live bitmap |
232 | 232 | sparse_dirty_bitmap m_dirty; // dirty bitmap |
r17959 | r17960 | |
---|---|---|
24 | 24 | |
25 | 25 | /* |
26 | 26 | |
27 | ||
27 | TODO: | |
28 | 28 | |
29 | ||
29 | - mos8563 | |
30 | 30 | |
31 | - horizontal scroll | |
32 | - vertical scroll | |
33 | - pixel double width | |
34 | - bitmap modes | |
35 | - display enable begin/end | |
31 | - horizontal scroll | |
32 | - vertical scroll | |
33 | - pixel double width | |
34 | - bitmap modes | |
35 | - display enable begin/end | |
36 | 36 | |
37 | 37 | */ |
38 | 38 | |
r17959 | r17960 | |
77 | 77 | #define HSS_ATTR BIT(m_horiz_scroll, 6) |
78 | 78 | #define HSS_TEXT BIT(m_horiz_scroll, 7) |
79 | 79 | |
80 | #define ATTR_COLOR (attr & 0x0f) | |
81 | #define ATTR_BLINK BIT(attr, 4) | |
82 | #define ATTR_UNDERLINE BIT(attr, 5) | |
83 | #define ATTR_REVERSE BIT(attr, 6) | |
80 | #define ATTR_COLOR (attr & 0x0f) | |
81 | #define ATTR_BLINK BIT(attr, 4) | |
82 | #define ATTR_UNDERLINE BIT(attr, 5) | |
83 | #define ATTR_REVERSE BIT(attr, 6) | |
84 | 84 | #define ATTR_ALTERNATE_CHARSET BIT(attr, 7) |
85 | 85 | |
86 | 86 | |
r17959 | r17960 | |
377 | 377 | case 0x0f: m_cursor_addr = ((data & 0xff) << 0) | (m_cursor_addr & 0xff00); break; |
378 | 378 | case 0x10: /* read-only */ break; |
379 | 379 | case 0x11: /* read-only */ break; |
380 | case 0x12: m_update_addr = ((data & 0xff) << 8) | (m_update_addr & 0x00ff); break; | |
381 | case 0x13: m_update_addr = ((data & 0xff) << 0) | (m_update_addr & 0xff00); break; | |
380 | case 0x12: m_update_addr = ((data & 0xff) << 8) | (m_update_addr & 0x00ff); break; | |
381 | case 0x13: m_update_addr = ((data & 0xff) << 0) | (m_update_addr & 0xff00); break; | |
382 | 382 | case 0x14: m_attribute_addr = ((data & 0xff) << 8) | (m_attribute_addr & 0x00ff); break; |
383 | 383 | case 0x15: m_attribute_addr = ((data & 0xff) << 0) | (m_attribute_addr & 0xff00); break; |
384 | case 0x16: | |
384 | case 0x16: | |
385 | 385 | case 0x17: m_vert_char_disp = data & 0x1f; break; |
386 | 386 | case 0x18: m_vert_scroll = data & 0xff; break; |
387 | 387 | case 0x19: m_horiz_scroll = data & 0xff; break; |
388 | case 0x1a: m_color | |
388 | case 0x1a: m_color | |
389 | 389 | case 0x1b: m_row_addr_incr = data & 0xff; break; |
390 | 390 | case 0x1c: m_char_base_addr = data & 0xf0; break; |
391 | 391 | case 0x1d: m_underline_ras = data & 0x1f; break; |
392 | 392 | case 0x1e: |
393 | 393 | m_word_count = data & 0xff; |
394 | ||
394 | ||
395 | 395 | do |
396 | 396 | { |
397 | 397 | UINT8 byte = VSS_COPY ? read_videoram(m_block_addr++) : m_data; |
r17959 | r17960 | |
404 | 404 | |
405 | 405 | write_videoram(m_update_addr++, m_data); |
406 | 406 | break; |
407 | case 0x20: m_block_addr = ((data & 0xff) << 8) | (m_block_addr & 0x00ff); break; | |
408 | case 0x21: m_block_addr = ((data & 0xff) << 0) | (m_block_addr & 0xff00); break; | |
409 | case 0x22: m_de_begin = ((data & 0xff) << 8) | (m_de_begin & 0x00ff); break; | |
410 | case 0x23: m_de_begin = ((data & 0xff) << 0) | (m_de_begin & 0xff00); break; | |
407 | case 0x20: m_block_addr = ((data & 0xff) << 8) | (m_block_addr & 0x00ff); break; | |
408 | case 0x21: m_block_addr = ((data & 0xff) << 0) | (m_block_addr & 0xff00); break; | |
409 | case 0x22: m_de_begin = ((data & 0xff) << 8) | (m_de_begin & 0x00ff); break; | |
410 | case 0x23: m_de_begin = ((data & 0xff) << 0) | (m_de_begin & 0xff00); break; | |
411 | 411 | case 0x24: m_dram_refresh = data & 0x0f; break; |
412 | 412 | case 0x25: m_sync_polarity = data & 0xc0; break; |
413 | 413 | } |
r17959 | r17960 | |
---|---|---|
34 | 34 | rgb_t pens[0x100]; |
35 | 35 | }; |
36 | 36 | |
37 | const tlc34076_config tlc34076_6_bit_intf = | |
37 | const tlc34076_config tlc34076_6_bit_intf = | |
38 | 38 | { |
39 | 39 | TLC34076_6_BIT |
40 | 40 | }; |
r17959 | r17960 | |
---|---|---|
1 | 1 | /*************************************************************************** |
2 | 2 | |
3 | ||
3 | Fujitsu MB90082 OSD | |
4 | 4 | |
5 | ||
5 | preliminary device by Angelo Salese | |
6 | 6 | |
7 | TODO: | |
8 | - get a real charset ROM; | |
7 | TODO: | |
8 | - get a real charset ROM; | |
9 | 9 | |
10 | 10 | ***************************************************************************/ |
11 | 11 | |
r17959 | r17960 | |
24 | 24 | static ADDRESS_MAP_START( mb90082_vram, AS_0, 16, mb90082_device ) |
25 | 25 | AM_RANGE(0x0000, 0x023f) AM_RAM // main screen vram |
26 | 26 | AM_RANGE(0x0400, 0x063f) AM_RAM // main screen attr |
27 | // AM_RANGE(0x0800, 0x0a3f) AM_RAM // sub screen vram | |
28 | // AM_RANGE(0x0c00, 0x0e3f) AM_RAM // sub screen attr | |
27 | // AM_RANGE(0x0800, 0x0a3f) AM_RAM // sub screen vram | |
28 | // AM_RANGE(0x0c00, 0x0e3f) AM_RAM // sub screen attr | |
29 | 29 | ADDRESS_MAP_END |
30 | 30 | |
31 | 31 | /* charset is undumped, but apparently a normal ASCII one is enough for the time being (for example "fnt0808.x1" in Sharp X1) */ |
r17959 | r17960 | |
---|---|---|
218 | 218 | copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, cliprect); |
219 | 219 | |
220 | 220 | m_bitmap.fill(m_palette[CDP1862_BACKGROUND_COLOR_SEQUENCE[m_bgcolor] + 8], cliprect); |
221 | ||
221 | ||
222 | 222 | return 0; |
223 | 223 | } |
r17959 | r17960 | |
---|---|---|
992 | 992 | return 0; // cursor only works in VGA or SVGA modes |
993 | 993 | |
994 | 994 | src = s3.cursor_start_addr * 1024; // start address is in units of 1024 bytes |
995 | // for(x=0;x<64;x++) | |
996 | // printf("%08x: %02x %02x %02x %02x\n",src+x*4,vga.memory[src+x*4],vga.memory[src+x*4+1],vga.memory[src+x*4+2],vga.memory[src+x*4+3]); | |
995 | // for(x=0;x<64;x++) | |
996 | // printf("%08x: %02x %02x %02x %02x\n",src+x*4,vga.memory[src+x*4],vga.memory[src+x*4+1],vga.memory[src+x*4+2],vga.memory[src+x*4+3]); | |
997 | 997 | for(y=0;y<64;y++) |
998 | 998 | { |
999 | 999 | dst = &bitmap.pix32(cy + y, cx); |
r17959 | r17960 | |
4940 | 4940 | clock = XTAL_42_9545MHz; |
4941 | 4941 | logerror("Invalid dot clock %i selected.\n",clock_type); |
4942 | 4942 | } |
4943 | // | |
4943 | // logerror("ATI: Clock select type %i (%iHz / %i)\n",clock_type,clock,div); | |
4944 | 4944 | recompute_params_clock(machine,divisor,clock / div); |
4945 | 4945 | } |
4946 | 4946 | |
r17959 | r17960 | |
5138 | 5138 | { |
5139 | 5139 | ibm8514.subctrl = data; |
5140 | 5140 | ibm8514.substatus &= ~(data & 0x0f); // reset interrupts |
5141 | // | |
5141 | // logerror("8514/A: Subsystem control write %04x\n",data); | |
5142 | 5142 | } |
5143 | 5143 | |
5144 | 5144 | READ16_HANDLER(mach8_subcontrol_r) |
r17959 | r17960 | |
5159 | 5159 | WRITE16_HANDLER(mach8_vtotal_w) |
5160 | 5160 | { |
5161 | 5161 | ibm8514.vtotal = data; |
5162 | // | |
5162 | // vga.crtc.vert_total = data; | |
5163 | 5163 | logerror("8514/A: Vertical total write %04x\n",data); |
5164 | 5164 | } |
5165 | 5165 | |
r17959 | r17960 | |
5171 | 5171 | WRITE16_HANDLER(mach8_vdisp_w) |
5172 | 5172 | { |
5173 | 5173 | ibm8514.vdisp = data; |
5174 | // | |
5174 | // vga.crtc.vert_disp_end = data >> 3; | |
5175 | 5175 | logerror("8514/A: Vertical Displayed write %04x\n",data); |
5176 | 5176 | } |
5177 | 5177 |
r17959 | r17960 | |
---|---|---|
1 | 1 | /*************************************************************************** |
2 | 2 | |
3 | ||
3 | Mitsubishi M50458 OSD chip | |
4 | 4 | |
5 | ||
5 | device by Angelo Salese | |
6 | 6 | |
7 | TODO: | |
8 | - vertical scrolling needs references (might work differently and/or in | |
9 | "worse" ways, the one currently implemented guesses that the screen is | |
10 | masked at the top and the end when in scrolling mode). | |
11 | - Understand what the "vertical start position" really does (vblank?) | |
12 | - Check if the ROM source is actually 2bpp once that a redump is made | |
13 | (the shadow ROM copy doesn't convince me 100%); | |
7 | TODO: | |
8 | - vertical scrolling needs references (might work differently and/or in | |
9 | "worse" ways, the one currently implemented guesses that the screen is | |
10 | masked at the top and the end when in scrolling mode). | |
11 | - Understand what the "vertical start position" really does (vblank?) | |
12 | - Check if the ROM source is actually 2bpp once that a redump is made | |
13 | (the shadow ROM copy doesn't convince me 100%); | |
14 | 14 | |
15 | 15 | ***************************************************************************/ |
16 | 16 | |
r17959 | r17960 | |
46 | 46 | |
47 | 47 | WRITE16_MEMBER( m50458_device::vreg_120_w) |
48 | 48 | { |
49 | // | |
49 | // printf("%04x\n",data); | |
50 | 50 | } |
51 | 51 | |
52 | 52 | WRITE16_MEMBER( m50458_device::vreg_121_w) |
r17959 | r17960 | |
85 | 85 | /* char part of vertical scrolling */ |
86 | 86 | m_scrr = (data & 0x0f00) >> 8; |
87 | 87 | |
88 | // | |
88 | // printf("%02x %02x %02x\n",m_scrr,m_scrf,m_space); | |
89 | 89 | } |
90 | 90 | |
91 | 91 | WRITE16_MEMBER( m50458_device::vreg_124_w) |
r17959 | r17960 | |
---|---|---|
28 | 28 | // TYPE DEFINITIONS |
29 | 29 | //************************************************************************** |
30 | 30 | |
31 | enum m50458_state_t | |
31 | enum m50458_state_t | |
32 | 32 | { |
33 | 33 | OSD_SET_ADDRESS = 0, |
34 | 34 | OSD_SET_DATA |
r17959 | r17960 | |
---|---|---|
112 | 112 | if((offset & 1) == 0) |
113 | 113 | { |
114 | 114 | /* |
115 | xxxx xxxx ---- ---- ---- ---- ---- ---- Sub Channel Buffer | |
116 | ---- ---- x--- ---- ---- ---- ---- ---- SCSI RST flag | |
117 | ---- ---- -x-- ---- ---- ---- ---- ---- SCSI BUSY flag | |
118 | ---- ---- --x- ---- ---- ---- ---- ---- SCSI REQ flag | |
119 | ---- ---- ---x ---- ---- ---- ---- ---- SCSI MSG flag | |
120 | ---- ---- ---- x--- ---- ---- ---- ---- SCSI CD flag | |
121 | ---- ---- ---- -x-- ---- ---- ---- ---- SCSI IO flag | |
122 | ---- ---- ---- --x- ---- ---- ---- ---- SCSI SEL flag | |
123 | ---- ---- ---- ---- -x-- ---- ---- ---- SCSI IRQ pending | |
124 | ---- ---- ---- ---- --x- ---- ---- ---- DMA IRQ pending | |
125 | ---- ---- ---- ---- ---x ---- ---- ---- CD Sub Channel IRQ pending | |
126 | ---- ---- ---- ---- ---- x--- ---- ---- Raster IRQ pending | |
127 | ---- ---- ---- ---- ---- -x-- ---- ---- ADPCM IRQ pending | |
128 | ---- ---- ---- ---- ---- ---- -xxx xxxx register read-back | |
129 | */ | |
115 | xxxx xxxx ---- ---- ---- ---- ---- ---- Sub Channel Buffer | |
116 | ---- ---- x--- ---- ---- ---- ---- ---- SCSI RST flag | |
117 | ---- ---- -x-- ---- ---- ---- ---- ---- SCSI BUSY flag | |
118 | ---- ---- --x- ---- ---- ---- ---- ---- SCSI REQ flag | |
119 | ---- ---- ---x ---- ---- ---- ---- ---- SCSI MSG flag | |
120 | ---- ---- ---- x--- ---- ---- ---- ---- SCSI CD flag | |
121 | ---- ---- ---- -x-- ---- ---- ---- ---- SCSI IO flag | |
122 | ---- ---- ---- --x- ---- ---- ---- ---- SCSI SEL flag | |
123 | ---- ---- ---- ---- -x-- ---- ---- ---- SCSI IRQ pending | |
124 | ---- ---- ---- ---- --x- ---- ---- ---- DMA IRQ pending | |
125 | ---- ---- ---- ---- ---x ---- ---- ---- CD Sub Channel IRQ pending | |
126 | ---- ---- ---- ---- ---- x--- ---- ---- Raster IRQ pending | |
127 | ---- ---- ---- ---- ---- -x-- ---- ---- ADPCM IRQ pending | |
128 | ---- ---- ---- ---- ---- ---- -xxx xxxx register read-back | |
129 | */ | |
130 | 130 | res = m_register & 0x7f; |
131 | 131 | res |= (0) << 16; |
132 | 132 | } |
r17959 | r17960 | |
135 | 135 | switch(m_register) |
136 | 136 | { |
137 | 137 | /* |
138 | x--- ---- ---- ---- ---- | |
139 | */ | |
138 | x--- ---- ---- ---- ---- | |
139 | */ | |
140 | 140 | case 0x0c: // KRAM load address |
141 | 141 | res = (m_kram_addr_r & 0x3ffff) | ((m_kram_inc_r & 0x1ff) << 18) | ((m_kram_page_r & 1) << 31); |
142 | 142 | break; |
r17959 | r17960 | |
179 | 179 | //printf("%08x DMA STATUS\n",data); |
180 | 180 | break; |
181 | 181 | /* |
182 | ---- ---- ---- ---- ---- | |
183 | */ | |
182 | ---- ---- ---- ---- ---- | |
183 | */ | |
184 | 184 | case 0x0c: // KRAM load address |
185 | 185 | m_kram_addr_r = (data & 0x0003ffff); |
186 | 186 | m_kram_inc_r = (data & 0x07fc0000) >> 18; |
r17959 | r17960 | |
199 | 199 | break; |
200 | 200 | |
201 | 201 | /* |
202 | ---x ---- ---- ---- ADPCM page setting | |
203 | ---- ---x ---- ---- RAINBOW page setting | |
204 | ---- ---- ---x ---- BG page setting | |
205 | ---- ---- ---- ---x SCSI page setting | |
206 | */ | |
202 | ---x ---- ---- ---- ADPCM page setting | |
203 | ---- ---x ---- ---- RAINBOW page setting | |
204 | ---- ---- ---x ---- BG page setting | |
205 | ---- ---- ---- ---x SCSI page setting | |
206 | */ | |
207 | 207 | case 0x0f: |
208 | 208 | m_page_setting = data; |
209 | 209 | break; |
r17959 | r17960 | |
---|---|---|
127 | 127 | #define VCLIP 2 |
128 | 128 | |
129 | 129 | /* The vertices are buffered here */ |
130 | struct point | |
130 | struct point | |
131 | 131 | { |
132 | 132 | int x; int y; |
133 | 133 | rgb_t col; |
r17959 | r17960 | |
---|---|---|
13 | 13 | |
14 | 14 | TODO: |
15 | 15 | |
16 | - character rounding | |
17 | - remote controller input | |
18 | - boxing | |
16 | - character rounding | |
17 | - remote controller input | |
18 | - boxing | |
19 | 19 | |
20 | 20 | */ |
21 | 21 | |
r17959 | r17960 | |
237 | 237 | case STEADY: |
238 | 238 | m_flash = false; |
239 | 239 | break; |
240 | ||
240 | ||
241 | 241 | case END_BOX: |
242 | 242 | case START_BOX: |
243 | 243 | // TODO |
r17959 | r17960 | |
336 | 336 | { |
337 | 337 | m_ra = 19; |
338 | 338 | m_double_height_top_row = false; |
339 | ||
339 | ||
340 | 340 | m_frame_count++; |
341 | 341 | if (m_frame_count > 50) m_frame_count = 0; |
342 | 342 | } |
r17959 | r17960 | |
---|---|---|
89 | 89 | |
90 | 90 | // NOTE: the following are provided for convenience only, SAA5050 is not a display controller |
91 | 91 | // this emulates the common setup where bit 7 of data inverts the display, and the |
92 | // bottom half of a double height row gets the same character data as the top half | |
92 | // bottom half of a double height row gets the same character data as the top half | |
93 | 93 | UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); |
94 | 94 | |
95 | 95 | protected: |
r17959 | r17960 | |
---|---|---|
518 | 518 | add_device_options(true); |
519 | 519 | int num = 0; |
520 | 520 | do { |
521 | num = options_count(); | |
521 | num = options_count(); | |
522 | 522 | update_slot_options(); |
523 | 523 | while (add_slot_options(false)); |
524 | 524 | add_device_options(false); |
r17959 | r17960 | |
568 | 568 | |
569 | 569 | |
570 | 570 | const char *emu_options::main_value(astring &buffer, const char *name) const |
571 | { | |
571 | { | |
572 | 572 | buffer = value(name); |
573 | 573 | int pos = buffer.chr(0,','); |
574 | 574 | if (pos!=-1) { |
r17959 | r17960 | |
578 | 578 | } |
579 | 579 | |
580 | 580 | const char *emu_options::sub_value(astring &buffer, const char *name, const char *subname) const |
581 | { | |
581 | { | |
582 | 582 | astring tmp = ","; |
583 | 583 | tmp.cat(subname); |
584 | 584 | tmp.cat("="); |
r17959 | r17960 | |
---|---|---|
464 | 464 | |
465 | 465 | |
466 | 466 | //------------------------------------------------- |
467 | // set_state_int - set the value of the given | |
468 | // piece of indexed state from a UINT64 | |
467 | // set_state_int - set the value of the given | |
468 | // piece of indexed state from a UINT64 | |
469 | 469 | //------------------------------------------------- |
470 | 470 | |
471 | 471 | void device_state_interface::set_state_int(int index, UINT64 value) |
r17959 | r17960 | |
---|---|---|
163 | 163 | void set_state_int(int index, UINT64 value); |
164 | 164 | void set_state_string(int index, const char *string); |
165 | 165 | void set_pc(offs_t pc) { set_state_int(STATE_GENPC, pc); } |
166 | ||
166 | ||
167 | 167 | // deliberately ambiguous functions; if you have the state interface |
168 | 168 | // just use it or pc() and pcbase() directly |
169 | 169 | device_state_interface &state() { return *this; } |
r17959 | r17960 | |
213 | 213 | |
214 | 214 | //------------------------------------------------- |
215 | 215 | // device_t::safe_pc - return the current PC |
216 | // | |
216 | // or 0 if no state object exists | |
217 | 217 | //------------------------------------------------- |
218 | 218 | |
219 | 219 | inline offs_t device_t::safe_pc() |
r17959 | r17960 | |
223 | 223 | |
224 | 224 | |
225 | 225 | //------------------------------------------------- |
226 | // device_t::safe_pcbase - return the current PC | |
227 | // base or 0 if no state object exists | |
226 | // device_t::safe_pcbase - return the current PC | |
227 | // base or 0 if no state object exists | |
228 | 228 | //------------------------------------------------- |
229 | 229 | |
230 | 230 | inline offs_t device_t::safe_pcbase() |
r17959 | r17960 | |
---|---|---|
164 | 164 | |
165 | 165 | |
166 | 166 | |
167 | struct OPLL_SLOT | |
167 | struct OPLL_SLOT | |
168 | 168 | { |
169 | 169 | UINT32 ar; /* attack rate: AR<<2 */ |
170 | 170 | UINT32 dr; /* decay rate: DR<<2 */ |
r17959 | r17960 | |
209 | 209 | unsigned int wavetable; |
210 | 210 | }; |
211 | 211 | |
212 | struct OPLL_CH | |
212 | struct OPLL_CH | |
213 | 213 | { |
214 | 214 | OPLL_SLOT SLOT[2]; |
215 | 215 | /* phase generator state */ |
r17959 | r17960 | |
221 | 221 | }; |
222 | 222 | |
223 | 223 | /* chip state */ |
224 | struct YM2413 | |
224 | struct YM2413 | |
225 | 225 | { |
226 | 226 | OPLL_CH P_CH[9]; /* OPLL chips have 9 channels*/ |
227 | 227 | UINT8 instvol_r[9]; /* instrument/volume (or volume/volume in percussive mode)*/ |
r17959 | r17960 | |
---|---|---|
531 | 531 | |
532 | 532 | |
533 | 533 | /* struct describing a single operator (SLOT) */ |
534 | struct FM_SLOT | |
534 | struct FM_SLOT | |
535 | 535 | { |
536 | 536 | INT32 *DT; /* detune :dt_tab[DT] */ |
537 | 537 | UINT8 KSR; /* key scale rate :3-KSR */ |
r17959 | r17960 | |
572 | 572 | |
573 | 573 | }; |
574 | 574 | |
575 | struct FM_CH | |
575 | struct FM_CH | |
576 | 576 | { |
577 | 577 | FM_SLOT SLOT[4]; /* four SLOTs (operators) */ |
578 | 578 | |
r17959 | r17960 | |
597 | 597 | }; |
598 | 598 | |
599 | 599 | |
600 | struct FM_ST | |
600 | struct FM_ST | |
601 | 601 | { |
602 | 602 | device_t *device; |
603 | 603 | void * param; /* this chip parameter */ |
r17959 | r17960 | |
634 | 634 | /***********************************************************/ |
635 | 635 | |
636 | 636 | /* OPN 3slot struct */ |
637 | struct FM_3SLOT | |
637 | struct FM_3SLOT | |
638 | 638 | { |
639 | 639 | UINT32 fc[3]; /* fnum3,blk3: calculated */ |
640 | 640 | UINT8 fn_h; /* freq3 latch */ |
r17959 | r17960 | |
644 | 644 | }; |
645 | 645 | |
646 | 646 | /* OPN/A/B common state */ |
647 | struct FM_OPN | |
647 | struct FM_OPN | |
648 | 648 | { |
649 | 649 | UINT8 type; /* chip type */ |
650 | 650 | FM_ST ST; /* general state */ |
r17959 | r17960 | |
678 | 678 | }; |
679 | 679 | |
680 | 680 | /* here's the virtual YM2612 */ |
681 | struct YM2612 | |
681 | struct YM2612 | |
682 | 682 | { |
683 | 683 | UINT8 REGS[512]; /* registers */ |
684 | 684 | FM_OPN OPN; /* OPN state */ |
r17959 | r17960 | |
---|---|---|
63 | 63 | C352_FLG_REVERSE = 0x0001, // play sample backwards |
64 | 64 | }; |
65 | 65 | |
66 | struct c352_ch_t | |
66 | struct c352_ch_t | |
67 | 67 | { |
68 | 68 | UINT8 vol_l; |
69 | 69 | UINT8 vol_r; |
r17959 | r17960 | |
---|---|---|
30 | 30 | |
31 | 31 | |
32 | 32 | /* this structure defines the parameters for a channel */ |
33 | struct k051649_sound_channel | |
33 | struct k051649_sound_channel | |
34 | 34 | { |
35 | 35 | unsigned long counter; |
36 | 36 | int frequency; |
r17959 | r17960 | |
---|---|---|
65 | 65 | UINT8 reserved[4]; |
66 | 66 | }; |
67 | 67 | |
68 | struct VOICE | |
68 | struct VOICE | |
69 | 69 | { |
70 | 70 | long ptoffset; |
71 | 71 | long pos; |
r17959 | r17960 | |
---|---|---|
48 | 48 | #define QUEUE_SIZE 0x2000 |
49 | 49 | #define QUEUE_MAX (QUEUE_SIZE-1) |
50 | 50 | |
51 | struct queue_t | |
51 | struct queue_t | |
52 | 52 | { |
53 | 53 | int pos; |
54 | 54 | unsigned char reg,val; |
r17959 | r17960 | |
84 | 84 | /* CHANNEL TYPE DEFINITIONS */ |
85 | 85 | |
86 | 86 | /* Square Wave */ |
87 | struct square_t | |
87 | struct square_t | |
88 | 88 | { |
89 | 89 | uint8 regs[4]; |
90 | 90 | int vbl_length; |
r17959 | r17960 | |
99 | 99 | }; |
100 | 100 | |
101 | 101 | /* Triangle Wave */ |
102 | struct triangle_t | |
102 | struct triangle_t | |
103 | 103 | { |
104 | 104 | uint8 regs[4]; /* regs[1] unused */ |
105 | 105 | int linear_length; |
r17959 | r17960 | |
113 | 113 | }; |
114 | 114 | |
115 | 115 | /* Noise Wave */ |
116 | struct noise_t | |
116 | struct noise_t | |
117 | 117 | { |
118 | 118 | uint8 regs[4]; /* regs[1] unused */ |
119 | 119 | int cur_pos; |
r17959 | r17960 | |
126 | 126 | }; |
127 | 127 | |
128 | 128 | /* DPCM Wave */ |
129 | struct dpcm_t | |
129 | struct dpcm_t | |
130 | 130 | { |
131 | 131 | uint8 regs[4]; |
132 | 132 | uint32 address; |
r17959 | r17960 | |
142 | 142 | }; |
143 | 143 | |
144 | 144 | /* APU type */ |
145 | struct apu_t | |
145 | struct apu_t | |
146 | 146 | { |
147 | 147 | /* Sound channels */ |
148 | 148 | square_t squ[2]; |
r17959 | r17960 | |
---|---|---|
156 | 156 | inline UINT8 mos6560_device::read_videoram(offs_t offset) |
157 | 157 | { |
158 | 158 | m_last_data = space(AS_0)->read_byte(offset & 0x3fff); |
159 | ||
159 | ||
160 | 160 | return m_last_data; |
161 | 161 | } |
162 | 162 |
r17959 | r17960 | |
---|---|---|
34 | 34 | |
35 | 35 | class ymz770_device : public device_t, public device_sound_interface |
36 | 36 | { |
37 | struct ymz_channel | |
37 | struct ymz_channel | |
38 | 38 | { |
39 | 39 | UINT8 phrase; |
40 | 40 | UINT8 pan; |
r17959 | r17960 | |
---|---|---|
31 | 31 | #define FREQBASEBITS 16 |
32 | 32 | |
33 | 33 | /* this structure defines the parameters for a channel */ |
34 | struct k005289_sound_channel | |
34 | struct k005289_sound_channel | |
35 | 35 | { |
36 | 36 | int frequency; |
37 | 37 | int counter; |
r17959 | r17960 | |
---|---|---|
141 | 141 | #define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */ |
142 | 142 | |
143 | 143 | |
144 | struct OPL3_SLOT | |
144 | struct OPL3_SLOT | |
145 | 145 | { |
146 | 146 | UINT32 ar; /* attack rate: AR<<2 */ |
147 | 147 | UINT32 dr; /* decay rate: DR<<2 */ |
r17959 | r17960 | |
192 | 192 | |
193 | 193 | }; |
194 | 194 | |
195 | struct OPL3_CH | |
195 | struct OPL3_CH | |
196 | 196 | { |
197 | 197 | OPL3_SLOT SLOT[2]; |
198 | 198 | |
r17959 | r17960 | |
218 | 218 | }; |
219 | 219 | |
220 | 220 | /* OPL3 state */ |
221 | struct OPL3 | |
221 | struct OPL3 | |
222 | 222 | { |
223 | 223 | OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */ |
224 | 224 |
r17959 | r17960 | |
---|---|---|
47 | 47 | virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples); |
48 | 48 | |
49 | 49 | private: |
50 | struct channel_t | |
50 | struct channel_t | |
51 | 51 | { |
52 | 52 | bool is_playing; |
53 | 53 | oki_adpcm_state m_adpcm; |
r17959 | r17960 | |
---|---|---|
176 | 176 | extern const device_type GAMEGEAR_NEW; |
177 | 177 | extern const device_type SEGAPSG_NEW; |
178 | 178 | |
179 | struct sn76496_config | |
179 | struct sn76496_config | |
180 | 180 | { |
181 | 181 | devcb_write_line ready; |
182 | 182 | }; |
r17959 | r17960 | |
---|---|---|
107 | 107 | |
108 | 108 | The other chip models don't support slave mode, and have an internal ROM. |
109 | 109 | Other than that, they are thought to be nearly identical to uPD7759. |
110 | ||
110 | ||
111 | 111 | 55C 18-pin DIP 96 Kbit ROM |
112 | 112 | 55G 24-pin SOP 96 Kbit ROM |
113 | 113 | 56C 18-pin DIP 256 Kbit ROM |
r17959 | r17960 | |
174 | 174 | |
175 | 175 | /* chip configuration */ |
176 | 176 | UINT8 sample_offset_shift; /* header sample address shift (access data > 0xffff) */ |
177 | ||
177 | ||
178 | 178 | /* internal clock to output sample rate mapping */ |
179 | 179 | UINT32 pos; /* current output sample position */ |
180 | 180 | UINT32 step; /* step value per output sample */ |
r17959 | r17960 | |
670 | 670 | |
671 | 671 | /* chip configuration */ |
672 | 672 | chip->sample_offset_shift = (device->type() == UPD7759) ? 1 : 0; |
673 | ||
673 | ||
674 | 674 | /* allocate a stream channel */ |
675 | 675 | chip->channel = device->machine().sound().stream_alloc(*device, 0, 1, device->clock()/4, chip, upd7759_update); |
676 | 676 |
r17959 | r17960 | |
---|---|---|
33 | 33 | |
34 | 34 | //#define log2(n) (log((float) n)/log((float) 2)) |
35 | 35 | |
36 | struct YMF271Slot | |
36 | struct YMF271Slot | |
37 | 37 | { |
38 | 38 | INT8 extout; |
39 | 39 | UINT8 lfoFreq; |
r17959 | r17960 | |
82 | 82 | double lfo_phasemod; |
83 | 83 | }; |
84 | 84 | |
85 | struct YMF271Group | |
85 | struct YMF271Group | |
86 | 86 | { |
87 | 87 | INT8 sync, pfm; |
88 | 88 | }; |
89 | 89 | |
90 | struct YMF271Chip | |
90 | struct YMF271Chip | |
91 | 91 | { |
92 | 92 | YMF271Slot slots[48]; |
93 | 93 | YMF271Group groups[12]; |
r17959 | r17960 | |
---|---|---|
17 | 17 | #include "n63701x.h" |
18 | 18 | |
19 | 19 | |
20 | struct voice | |
20 | struct voice | |
21 | 21 | { |
22 | 22 | int select; |
23 | 23 | int playing; |
r17959 | r17960 | |
---|---|---|
23 | 23 | |
24 | 24 | |
25 | 25 | /* struct describing a single operator */ |
26 | struct YM2151Operator | |
26 | struct YM2151Operator | |
27 | 27 | { |
28 | 28 | UINT32 phase; /* accumulated operator phase */ |
29 | 29 | UINT32 freq; /* operator frequency count */ |
r17959 | r17960 | |
76 | 76 | }; |
77 | 77 | |
78 | 78 | |
79 | struct YM2151 | |
79 | struct YM2151 | |
80 | 80 | { |
81 | 81 | signed int chanout[8]; |
82 | 82 | signed int m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */ |
r17959 | r17960 | |
---|---|---|
83 | 83 | * |
84 | 84 | *************************************/ |
85 | 85 | |
86 | struct output_buffer | |
86 | struct output_buffer | |
87 | 87 | { |
88 | 88 | double *node_buf; |
89 | 89 | const double *source; |
r17959 | r17960 | |
91 | 91 | int node_num; |
92 | 92 | }; |
93 | 93 | |
94 | struct input_buffer | |
94 | struct input_buffer | |
95 | 95 | { |
96 | 96 | volatile const double *ptr; /* pointer into linked_outbuf.nodebuf */ |
97 | 97 | output_buffer * linked_outbuf; /* what output are we connected to ? */ |
r17959 | r17960 | |
---|---|---|
4139 | 4139 | * |
4140 | 4140 | *************************************/ |
4141 | 4141 | |
4142 | enum discrete_node_type | |
4142 | enum discrete_node_type | |
4143 | 4143 | { |
4144 | 4144 | DSS_NULL, /* Nothing, nill, zippo, only to be used as terminating node */ |
4145 | 4145 | DSS_NOP, /* just do nothing, placeholder for potential DISCRETE_REPLACE in parent block */ |
r17959 | r17960 | |
---|---|---|
198 | 198 | |
199 | 199 | |
200 | 200 | |
201 | struct OPL_SLOT | |
201 | struct OPL_SLOT | |
202 | 202 | { |
203 | 203 | UINT32 ar; /* attack rate: AR<<2 */ |
204 | 204 | UINT32 dr; /* decay rate: DR<<2 */ |
r17959 | r17960 | |
239 | 239 | UINT16 wavetable; |
240 | 240 | }; |
241 | 241 | |
242 | struct OPL_CH | |
242 | struct OPL_CH | |
243 | 243 | { |
244 | 244 | OPL_SLOT SLOT[2]; |
245 | 245 | /* phase generator state */ |
r17959 | r17960 | |
250 | 250 | }; |
251 | 251 | |
252 | 252 | /* OPL state */ |
253 | struct FM_OPL | |
253 | struct FM_OPL | |
254 | 254 | { |
255 | 255 | /* FM channel slots */ |
256 | 256 | OPL_CH P_CH[9]; /* OPL/OPL2 chips have 9 channels*/ |
r17959 | r17960 | |
---|---|---|
237 | 237 | #include "emu.h" |
238 | 238 | #include "s14001a.h" |
239 | 239 | |
240 | struct S14001AChip | |
240 | struct S14001AChip | |
241 | 241 | { |
242 | 242 | sound_stream * stream; |
243 | 243 |
r17959 | r17960 | |
---|---|---|
519 | 519 | |
520 | 520 | |
521 | 521 | /* struct describing a single operator (SLOT) */ |
522 | struct FM_SLOT | |
522 | struct FM_SLOT | |
523 | 523 | { |
524 | 524 | INT32 *DT; /* detune :dt_tab[DT] */ |
525 | 525 | UINT8 KSR; /* key scale rate :3-KSR */ |
r17959 | r17960 | |
560 | 560 | |
561 | 561 | }; |
562 | 562 | |
563 | struct FM_CH | |
563 | struct FM_CH | |
564 | 564 | { |
565 | 565 | FM_SLOT SLOT[4]; /* four SLOTs (operators) */ |
566 | 566 | |
r17959 | r17960 | |
585 | 585 | }; |
586 | 586 | |
587 | 587 | |
588 | struct FM_ST | |
588 | struct FM_ST | |
589 | 589 | { |
590 | 590 | device_t *device; |
591 | 591 | void * param; /* this chip parameter */ |
r17959 | r17960 | |
622 | 622 | /***********************************************************/ |
623 | 623 | |
624 | 624 | /* OPN 3slot struct */ |
625 | struct FM_3SLOT | |
625 | struct FM_3SLOT | |
626 | 626 | { |
627 | 627 | UINT32 fc[3]; /* fnum3,blk3: calculated */ |
628 | 628 | UINT8 fn_h; /* freq3 latch */ |
r17959 | r17960 | |
631 | 631 | }; |
632 | 632 | |
633 | 633 | /* OPN/A/B common state */ |
634 | struct FM_OPN | |
634 | struct FM_OPN | |
635 | 635 | { |
636 | 636 | UINT8 type; /* chip type */ |
637 | 637 | FM_ST ST; /* general state */ |
r17959 | r17960 | |
2089 | 2089 | /*****************************************************************************/ |
2090 | 2090 | |
2091 | 2091 | /* here's the virtual YM2203(OPN) */ |
2092 | struct YM2203 | |
2092 | struct YM2203 | |
2093 | 2093 | { |
2094 | 2094 | UINT8 REGS[256]; /* registers */ |
2095 | 2095 | FM_OPN OPN; /* OPN state */ |
r17959 | r17960 | |
2385 | 2385 | #if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B) |
2386 | 2386 | |
2387 | 2387 | /* ADPCM type A channel struct */ |
2388 | struct ADPCM_CH | |
2388 | struct ADPCM_CH | |
2389 | 2389 | { |
2390 | 2390 | UINT8 flag; /* port state */ |
2391 | 2391 | UINT8 flagMask; /* arrived flag mask */ |
r17959 | r17960 | |
2405 | 2405 | }; |
2406 | 2406 | |
2407 | 2407 | /* here's the virtual YM2610 */ |
2408 | struct YM2610 | |
2408 | struct YM2610 | |
2409 | 2409 | { |
2410 | 2410 | UINT8 REGS[512]; /* registers */ |
2411 | 2411 | FM_OPN OPN; /* OPN state */ |
r17959 | r17960 | |
---|---|---|
73 | 73 | |
74 | 74 | struct YMF278BChip; |
75 | 75 | |
76 | struct YMF278BSlot | |
76 | struct YMF278BSlot | |
77 | 77 | { |
78 | 78 | INT16 wave; /* wavetable number */ |
79 | 79 | INT16 F_NUMBER; /* frequency */ |
r17959 | r17960 | |
115 | 115 | YMF278BChip *chip; /* pointer back to parent chip */ |
116 | 116 | }; |
117 | 117 | |
118 | struct YMF278BChip | |
118 | struct YMF278BChip | |
119 | 119 | { |
120 | 120 | UINT8 pcmregs[256]; |
121 | 121 | YMF278BSlot slots[24]; |
r17959 | r17960 | |
---|---|---|
34 | 34 | SID6581_t *sid = get_sid(device); |
35 | 35 | const sid6581_interface *iface = (const sid6581_interface*) device->static_config(); |
36 | 36 | assert(iface); |
37 | ||
37 | ||
38 | 38 | // resolve callbacks |
39 | 39 | sid->in_potx_func.resolve(iface->in_potx_cb, *device); |
40 | 40 | sid->in_poty_func.resolve(iface->in_poty_cb, *device); |
r17959 | r17960 | |
---|---|---|
14 | 14 | #include "devlegcy.h" |
15 | 15 | |
16 | 16 | |
17 | enum SIDTYPE | |
17 | enum SIDTYPE | |
18 | 18 | { |
19 | 19 | MOS6581, |
20 | 20 | MOS8580 |
r17959 | r17960 | |
---|---|---|
36 | 36 | |
37 | 37 | |
38 | 38 | /* this structure defines the parameters for a channel */ |
39 | struct sound_channel | |
39 | struct sound_channel | |
40 | 40 | { |
41 | 41 | UINT32 frequency; |
42 | 42 | UINT32 counter; |
r17959 | r17960 | |
---|---|---|
30 | 30 | #define KDAC_A_PCM_MAX (2) /* Channels per chip */ |
31 | 31 | |
32 | 32 | |
33 | struct KDAC_A_PCM | |
33 | struct KDAC_A_PCM | |
34 | 34 | { |
35 | 35 | UINT8 vol[KDAC_A_PCM_MAX][2]; /* volume for the left and right channel */ |
36 | 36 | UINT32 addr[KDAC_A_PCM_MAX]; |
r17959 | r17960 | |
---|---|---|
121 | 121 | extern const device_type TMS5200N; |
122 | 122 | |
123 | 123 | |
124 | struct tms52xx_config | |
124 | struct tms52xx_config | |
125 | 125 | { |
126 | 126 | devcb_write_line irq_func; // IRQ callback function, active low, i.e. state=0 (TODO: change to ASSERT/CLEAR) |
127 | 127 | devcb_write_line readyq_func; // Ready callback function, active low, i.e. state=0 |
r17959 | r17960 | |
---|---|---|
67 | 67 | MODE_SWAP = 3 |
68 | 68 | }; |
69 | 69 | |
70 | struct ES5503Osc | |
70 | struct ES5503Osc | |
71 | 71 | { |
72 | 72 | UINT16 freq; |
73 | 73 | UINT16 wtsize; |
r17959 | r17960 | |
---|---|---|
1454 | 1454 | |
1455 | 1455 | /* figure out which BIOS we are using */ |
1456 | 1456 | device_iterator deviter(romdata->machine().config().root_device()); |
1457 | for (device_t *device = deviter.first(); device != NULL; device = deviter.next()) { | |
1457 | for (device_t *device = deviter.first(); device != NULL; device = deviter.next()) { | |
1458 | 1458 | if (device->rom_region()) { |
1459 | 1459 | const char *specbios; |
1460 | 1460 | astring temp; |
1461 | 1461 | if (strcmp(device->tag(),":")==0) { |
1462 | 1462 | specbios = romdata->machine().options().bios(); |
1463 | 1463 | } else { |
1464 | specbios = romdata->machine().options().sub_value(temp,device->owner()->tag()+1,"bios"); | |
1464 | specbios = romdata->machine().options().sub_value(temp,device->owner()->tag()+1,"bios"); | |
1465 | 1465 | } |
1466 | 1466 | determine_bios_rom(romdata, device, specbios); |
1467 | 1467 | } |
r17959 | r17960 | |
---|---|---|
444 | 444 | else |
445 | 445 | next_position = 200000000 + (buf[1] & floppy_image::TIME_MASK); |
446 | 446 | |
447 | // | |
447 | // logerror("Floppy: cuspos=%d nextpos=%d\n", position, next_position); | |
448 | 448 | return base + attotime::from_nsec(UINT64(next_position)*300/rpm); |
449 | 449 | } |
450 | 450 |
r17959 | r17960 | |
---|---|---|
78 | 78 | CPUINFO_INT_ADDRBUS_SHIFT_2 = CPUINFO_INT_ADDRBUS_SHIFT + 2, |
79 | 79 | CPUINFO_INT_ADDRBUS_SHIFT_3 = CPUINFO_INT_ADDRBUS_SHIFT + 3, |
80 | 80 | CPUINFO_INT_ADDRBUS_SHIFT_LAST = CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACES - 1, |
81 | ||
81 | ||
82 | 82 | // CPU-specific additionsg |
83 | 83 | CPUINFO_INT_CONTEXT_SIZE = 0x04000, // R/O: size of CPU context in bytes |
84 | 84 | CPUINFO_INT_INPUT_LINES, // R/O: number of input lines |
r17959 | r17960 | |
129 | 129 | CPUINFO_PTR_DEFAULT_MEMORY_MAP_2 = CPUINFO_PTR_DEFAULT_MEMORY_MAP + 2, |
130 | 130 | CPUINFO_PTR_DEFAULT_MEMORY_MAP_3 = CPUINFO_PTR_DEFAULT_MEMORY_MAP + 3, |
131 | 131 | CPUINFO_PTR_DEFAULT_MEMORY_MAP_LAST = CPUINFO_PTR_DEFAULT_MEMORY_MAP + ADDRESS_SPACES - 1, |
132 | ||
132 | ||
133 | 133 | // CPU-specific additions |
134 | 134 | CPUINFO_PTR_INSTRUCTION_COUNTER = 0x14000, |
135 | 135 | // R/O: int *icount |
r17959 | r17960 | |
---|---|---|
34 | 34 | #define INT_ENABLE_RX_LINE_STATUS 0x04 |
35 | 35 | #define INT_ENABLE_MODEM_STATUS 0x08 |
36 | 36 | |
37 | struct PC16552D_CHANNEL | |
37 | struct PC16552D_CHANNEL | |
38 | 38 | { |
39 | 39 | UINT16 divisor; |
40 | 40 | UINT8 reg[8]; |
r17959 | r17960 | |
50 | 50 | emu_timer *tx_fifo_timer; |
51 | 51 | }; |
52 | 52 | |
53 | struct PC16552D_REGS | |
53 | struct PC16552D_REGS | |
54 | 54 | { |
55 | 55 | PC16552D_CHANNEL ch[2]; |
56 | 56 | int frequency; |
r17959 | r17960 | |
---|---|---|
1 | 1 | /*************************************************************************** |
2 | 2 | |
3 | ||
3 | Seibu COP protection device | |
4 | 4 | |
5 | ||
5 | (this header needs expanding) | |
6 | 6 | |
7 | 7 | ***************************************************************************/ |
8 | 8 | |
r17959 | r17960 | |
116 | 116 | |
117 | 117 | case 0x074/2: |
118 | 118 | /* |
119 | This sets up a DMA mode of some sort | |
120 | 0x0e00: grainbow, cupsoc | |
121 | 0x0a00: legionna, godzilla, denjinmk | |
122 | 0x0600: heatbrl | |
123 | 0x1e00: zeroteam, xsedae | |
124 | raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs | |
125 | (both only uses 0x14 and 0x15 as DMAs) | |
126 | */ | |
119 | This sets up a DMA mode of some sort | |
120 | 0x0e00: grainbow, cupsoc | |
121 | 0x0a00: legionna, godzilla, denjinmk | |
122 | 0x0600: heatbrl | |
123 | 0x1e00: zeroteam, xsedae | |
124 | raiden2 and raidendx doesn't set this up, this could indicate that this is related to the non-private buffer DMAs | |
125 | (both only uses 0x14 and 0x15 as DMAs) | |
126 | */ | |
127 | 127 | COMBINE_DATA(&m_dma_unk_param); |
128 | 128 | break; |
129 | 129 |
r17959 | r17960 | |
---|---|---|
12 | 12 | #ifndef PCKEYBRD_H |
13 | 13 | #define PCKEYBRD_H |
14 | 14 | |
15 | enum AT_KEYBOARD_TYPE | |
15 | enum AT_KEYBOARD_TYPE | |
16 | 16 | { |
17 | 17 | AT_KEYBOARD_TYPE_PC, |
18 | 18 | AT_KEYBOARD_TYPE_AT, |
r17959 | r17960 | |
---|---|---|
1 | 1 | /* |
2 | ||
2 | SCSIBus.c | |
3 | 3 | |
4 | Implementation of a raw SCSI/SASI bus for machines that don't use a SCSI | |
5 | controler chip such as the RM Nimbus, which implements it as a bunch of | |
6 | 74LS series chips. | |
4 | Implementation of a raw SCSI/SASI bus for machines that don't use a SCSI | |
5 | controler chip such as the RM Nimbus, which implements it as a bunch of | |
6 | 74LS series chips. | |
7 | 7 | |
8 | 8 | */ |
9 | 9 |
r17959 | r17960 | |
---|---|---|
100 | 100 | |
101 | 101 | #define SCSI_SENSE_SIZE 4 |
102 | 102 | |
103 | struct adaptec_sense_t | |
103 | struct adaptec_sense_t | |
104 | 104 | { |
105 | 105 | // parameter list |
106 | 106 | UINT8 reserved1[3]; |
r17959 | r17960 | |
---|---|---|
50 | 50 | CLASS DEFINITION |
51 | 51 | ***************************************************************************/ |
52 | 52 | |
53 | struct tms9901_interface | |
53 | struct tms9901_interface | |
54 | 54 | { |
55 | 55 | int interrupt_mask; // a bit for each input pin whose state is always notified to the TMS9901 core |
56 | 56 | devcb_read8 read_handler; // 4*8 bits, to be selected using the offset (0-3) |
r17959 | r17960 | |
---|---|---|
30 | 30 | devcb_write_line m_out_int_cb; |
31 | 31 | }; |
32 | 32 | |
33 | struct rtc_regs_t | |
33 | struct rtc_regs_t | |
34 | 34 | { |
35 | 35 | UINT8 sec, min, hour, day, wday, month; |
36 | 36 | UINT16 year; |
r17959 | r17960 | |
---|---|---|
393 | 393 | |
394 | 394 | UINT8 lsi53c810_device::lsi53c810_reg_r( int offset ) |
395 | 395 | { |
396 | // | |
396 | // logerror("53c810: read reg %d:0x%x (PC=%x)\n", offset, offset, space->device().safe_pc()); | |
397 | 397 | switch(offset) |
398 | 398 | { |
399 | 399 | case 0x00: /* SCNTL0 */ |
r17959 | r17960 | |
476 | 476 | |
477 | 477 | void lsi53c810_device::lsi53c810_reg_w(int offset, UINT8 data) |
478 | 478 | { |
479 | // | |
479 | // logerror("53c810: %02x to reg %d:0x%x (PC=%x)\n", data, offset, offset, space->device().safe_pc()); | |
480 | 480 | switch(offset) |
481 | 481 | { |
482 | 482 | case 0x00: /* SCNTL0 */ |
r17959 | r17960 | |
---|---|---|
419 | 419 | case WD_CMD_RESET: |
420 | 420 | reset_cmd(); |
421 | 421 | break; |
422 | ||
422 | ||
423 | 423 | case WD_CMD_ABORT: |
424 | 424 | abort_cmd(); |
425 | 425 | break; |
426 | ||
426 | ||
427 | 427 | case WD_CMD_NEGATE_ACK: |
428 | 428 | negate_ack(); |
429 | 429 | break; |
r17959 | r17960 | |
---|---|---|
27 | 27 | #define MATSU_STATUS_MEDIA ( 1 << 6 ) /* media present (in caddy or tray) */ |
28 | 28 | #define MATSU_STATUS_DOORCLOSED ( 1 << 7 ) /* tray status */ |
29 | 29 | |
30 | struct matsucd | |
30 | struct matsucd | |
31 | 31 | { |
32 | 32 | UINT8 enabled; /* /ENABLE - Unit enabled */ |
33 | 33 | UINT8 cmd_signal; /* /CMD - Command mode */ |
r17959 | r17960 | |
---|---|---|
20 | 20 | #define LOG_OCW 0 |
21 | 21 | #define LOG_GENERAL 0 |
22 | 22 | |
23 | enum pic8259_state_t | |
23 | enum pic8259_state_t | |
24 | 24 | { |
25 | 25 | STATE_ICW1, |
26 | 26 | STATE_ICW2, |
r17959 | r17960 | |
---|---|---|
24 | 24 | // TYPE DEFINITIONS |
25 | 25 | //************************************************************************** |
26 | 26 | |
27 | enum eeprom_cmd_t | |
27 | enum eeprom_cmd_t | |
28 | 28 | { |
29 | 29 | EEPROM_GET_CMD = 0, |
30 | 30 | EEPROM_READ, |
r17959 | r17960 | |
---|---|---|
42 | 42 | |
43 | 43 | extern const device_type TMS9902; |
44 | 44 | |
45 | struct tms9902_interface | |
45 | struct tms9902_interface | |
46 | 46 | { |
47 | 47 | devcb_write_line int_callback; |
48 | 48 | devcb_write_line rcv_callback; |
r17959 | r17960 | |
---|---|---|
67 | 67 | space->install_legacy_readwrite_handler( *device, 0x5a000000, 0x5a000043, FUNC(s3c24xx_sdi_r), FUNC(s3c24xx_sdi_w)); |
68 | 68 | space->install_legacy_readwrite_handler( *device, 0x5b000000, 0x5b00001f, FUNC(s3c24xx_ac97_r), FUNC(s3c24xx_ac97_w)); |
69 | 69 | DEVICE_START_CALL(s3c24xx); |
70 | ||
70 | ||
71 | 71 | s3c24xx_video_start( device, device->machine()); |
72 | 72 | } |
73 | 73 |
r17959 | r17960 | |
---|---|---|
45 | 45 | public: |
46 | 46 | s3c2440_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
47 | 47 | ~s3c2440_device() { global_free(m_token); } |
48 | ||
48 | ||
49 | 49 | // access to legacy token |
50 | 50 | void *token() const { assert(m_token != NULL); return m_token; } |
51 | 51 | protected: |
r17959 | r17960 | |
56 | 56 | private: |
57 | 57 | // internal state |
58 | 58 | void *m_token; |
59 | public: | |
59 | public: | |
60 | 60 | UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); |
61 | 61 | }; |
62 | 62 | |
r17959 | r17960 | |
527 | 527 | TYPE DEFINITIONS |
528 | 528 | *******************************************************************************/ |
529 | 529 | |
530 | struct s3c24xx_memcon_regs_t | |
530 | struct s3c24xx_memcon_regs_t | |
531 | 531 | { |
532 | 532 | UINT32 data[0x34/4]; |
533 | 533 | }; |
534 | 534 | |
535 | struct s3c24xx_usbhost_regs_t | |
535 | struct s3c24xx_usbhost_regs_t | |
536 | 536 | { |
537 | 537 | UINT32 data[0x5C/4]; |
538 | 538 | }; |
539 | 539 | |
540 | struct s3c24xx_irq_regs_t | |
540 | struct s3c24xx_irq_regs_t | |
541 | 541 | { |
542 | 542 | UINT32 srcpnd; |
543 | 543 | UINT32 intmod; |
r17959 | r17960 | |
549 | 549 | UINT32 intsubmsk; |
550 | 550 | }; |
551 | 551 | |
552 | struct s3c24xx_dma_regs_t | |
552 | struct s3c24xx_dma_regs_t | |
553 | 553 | { |
554 | 554 | UINT32 disrc; |
555 | 555 | UINT32 disrcc; |
r17959 | r17960 | |
562 | 562 | UINT32 dmasktrig; |
563 | 563 | }; |
564 | 564 | |
565 | struct s3c24xx_clkpow_regs_t | |
565 | struct s3c24xx_clkpow_regs_t | |
566 | 566 | { |
567 | 567 | UINT32 locktime; |
568 | 568 | UINT32 mpllcon; |
r17959 | r17960 | |
573 | 573 | UINT32 camdivn; |
574 | 574 | }; |
575 | 575 | |
576 | struct s3c24xx_lcd_regs_t | |
576 | struct s3c24xx_lcd_regs_t | |
577 | 577 | { |
578 | 578 | UINT32 lcdcon1; |
579 | 579 | UINT32 lcdcon2; |
r17959 | r17960 | |
595 | 595 | UINT32 tconsel; |
596 | 596 | }; |
597 | 597 | |
598 | struct s3c24xx_lcdpal_regs_t | |
598 | struct s3c24xx_lcdpal_regs_t | |
599 | 599 | { |
600 | 600 | UINT32 data[0x400/4]; |
601 | 601 | }; |
602 | 602 | |
603 | struct s3c24xx_nand_regs_t | |
603 | struct s3c24xx_nand_regs_t | |
604 | 604 | { |
605 | 605 | UINT32 nfconf; |
606 | 606 | UINT32 nfcont; |
r17959 | r17960 | |
620 | 620 | UINT32 nfeblk; |
621 | 621 | }; |
622 | 622 | |
623 | struct s3c24xx_cam_regs_t | |
623 | struct s3c24xx_cam_regs_t | |
624 | 624 | { |
625 | 625 | UINT32 data[0xA4/4]; |
626 | 626 | }; |
627 | 627 | |
628 | struct s3c24xx_uart_regs_t | |
628 | struct s3c24xx_uart_regs_t | |
629 | 629 | { |
630 | 630 | UINT32 ulcon; |
631 | 631 | UINT32 ucon; |
r17959 | r17960 | |
640 | 640 | UINT32 ubrdiv; |
641 | 641 | }; |
642 | 642 | |
643 | struct s3c24xx_pwm_regs_t | |
643 | struct s3c24xx_pwm_regs_t | |
644 | 644 | { |
645 | 645 | UINT32 tcfg0; |
646 | 646 | UINT32 tcfg1; |
r17959 | r17960 | |
661 | 661 | UINT32 tcnto4; |
662 | 662 | }; |
663 | 663 | |
664 | struct s3c24xx_usbdev_regs_t | |
664 | struct s3c24xx_usbdev_regs_t | |
665 | 665 | { |
666 | 666 | UINT32 data[0x130/4]; |
667 | 667 | }; |
668 | 668 | |
669 | struct s3c24xx_wdt_regs_t | |
669 | struct s3c24xx_wdt_regs_t | |
670 | 670 | { |
671 | 671 | UINT32 wtcon; |
672 | 672 | UINT32 wtdat; |
673 | 673 | UINT32 wtcnt; |
674 | 674 | }; |
675 | 675 | |
676 | struct s3c24xx_iic_regs_t | |
676 | struct s3c24xx_iic_regs_t | |
677 | 677 | { |
678 | 678 | UINT32 iiccon; |
679 | 679 | UINT32 iicstat; |
r17959 | r17960 | |
682 | 682 | UINT32 iiclc; |
683 | 683 | }; |
684 | 684 | |
685 | struct s3c24xx_iis_regs_t | |
685 | struct s3c24xx_iis_regs_t | |
686 | 686 | { |
687 | 687 | UINT32 iiscon; |
688 | 688 | UINT32 iismod; |
r17959 | r17960 | |
691 | 691 | UINT32 iisfifo; |
692 | 692 | }; |
693 | 693 | |
694 | struct s3c24xx_gpio_regs_t | |
694 | struct s3c24xx_gpio_regs_t | |
695 | 695 | { |
696 | 696 | UINT32 gpacon; |
697 | 697 | UINT32 gpadat; |
r17959 | r17960 | |
750 | 750 | UINT32 gpjup; |
751 | 751 | }; |
752 | 752 | |
753 | struct s3c24xx_rtc_regs_t | |
753 | struct s3c24xx_rtc_regs_t | |
754 | 754 | { |
755 | 755 | UINT32 rtccon; |
756 | 756 | UINT32 ticnt; |
r17959 | r17960 | |
772 | 772 | UINT32 bcdyear; |
773 | 773 | }; |
774 | 774 | |
775 | struct s3c24xx_adc_regs_t | |
775 | struct s3c24xx_adc_regs_t | |
776 | 776 | { |
777 | 777 | UINT32 adccon; |
778 | 778 | UINT32 adctsc; |
r17959 | r17960 | |
782 | 782 | UINT32 adcupdn; |
783 | 783 | }; |
784 | 784 | |
785 | struct s3c24xx_spi_regs_t | |
785 | struct s3c24xx_spi_regs_t | |
786 | 786 | { |
787 | 787 | UINT32 spcon; |
788 | 788 | UINT32 spsta; |
r17959 | r17960 | |
792 | 792 | UINT32 sprdat; |
793 | 793 | }; |
794 | 794 | |
795 | struct s3c24xx_sdi_regs_t | |
795 | struct s3c24xx_sdi_regs_t | |
796 | 796 | { |
797 | 797 | UINT32 data[0x44/4]; |
798 | 798 | }; |
799 | 799 | |
800 | struct s3c24xx_ac97_regs_t | |
800 | struct s3c24xx_ac97_regs_t | |
801 | 801 | { |
802 | 802 | UINT32 data[0x20/4]; |
803 | 803 | }; |
804 | 804 | |
805 | struct s3c24xx_memcon_t | |
805 | struct s3c24xx_memcon_t | |
806 | 806 | { |
807 | 807 | s3c24xx_memcon_regs_t regs; |
808 | 808 | }; |
809 | 809 | |
810 | struct s3c24xx_usbhost_t | |
810 | struct s3c24xx_usbhost_t | |
811 | 811 | { |
812 | 812 | s3c24xx_usbhost_regs_t regs; |
813 | 813 | }; |
814 | 814 | |
815 | struct s3c24xx_irq_t | |
815 | struct s3c24xx_irq_t | |
816 | 816 | { |
817 | 817 | s3c24xx_irq_regs_t regs; |
818 | 818 | int line_irq, line_fiq; |
819 | 819 | }; |
820 | 820 | |
821 | struct s3c24xx_dma_t | |
821 | struct s3c24xx_dma_t | |
822 | 822 | { |
823 | 823 | s3c24xx_dma_regs_t regs; |
824 | 824 | emu_timer *timer; |
825 | 825 | }; |
826 | 826 | |
827 | struct s3c24xx_clkpow_t | |
827 | struct s3c24xx_clkpow_t | |
828 | 828 | { |
829 | 829 | s3c24xx_clkpow_regs_t regs; |
830 | 830 | }; |
831 | 831 | |
832 | struct s3c24xx_lcd_t | |
832 | struct s3c24xx_lcd_t | |
833 | 833 | { |
834 | 834 | s3c24xx_lcd_regs_t regs; |
835 | 835 | emu_timer *timer; |
r17959 | r17960 | |
848 | 848 | UINT32 dma_data, dma_bits; |
849 | 849 | }; |
850 | 850 | |
851 | struct s3c24xx_lcdpal_t | |
851 | struct s3c24xx_lcdpal_t | |
852 | 852 | { |
853 | 853 | s3c24xx_lcdpal_regs_t regs; |
854 | 854 | }; |
855 | 855 | |
856 | struct s3c24xx_nand_t | |
856 | struct s3c24xx_nand_t | |
857 | 857 | { |
858 | 858 | s3c24xx_nand_regs_t regs; |
859 | 859 | UINT8 mecc[4]; |
r17959 | r17960 | |
861 | 861 | int ecc_pos, data_count; |
862 | 862 | }; |
863 | 863 | |
864 | struct s3c24xx_cam_t | |
864 | struct s3c24xx_cam_t | |
865 | 865 | { |
866 | 866 | s3c24xx_cam_regs_t regs; |
867 | 867 | }; |
868 | 868 | |
869 | struct s3c24xx_uart_t | |
869 | struct s3c24xx_uart_t | |
870 | 870 | { |
871 | 871 | s3c24xx_uart_regs_t regs; |
872 | 872 | }; |
873 | 873 | |
874 | struct s3c24xx_pwm_t | |
874 | struct s3c24xx_pwm_t | |
875 | 875 | { |
876 | 876 | s3c24xx_pwm_regs_t regs; |
877 | 877 | emu_timer *timer[5]; |
r17959 | r17960 | |
880 | 880 | UINT32 freq[5]; |
881 | 881 | }; |
882 | 882 | |
883 | struct s3c24xx_usbdev_t | |
883 | struct s3c24xx_usbdev_t | |
884 | 884 | { |
885 | 885 | s3c24xx_usbdev_regs_t regs; |
886 | 886 | }; |
887 | 887 | |
888 | struct s3c24xx_wdt_t | |
888 | struct s3c24xx_wdt_t | |
889 | 889 | { |
890 | 890 | s3c24xx_wdt_regs_t regs; |
891 | 891 | emu_timer *timer; |
892 | 892 | }; |
893 | 893 | |
894 | struct s3c24xx_iic_t | |
894 | struct s3c24xx_iic_t | |
895 | 895 | { |
896 | 896 | s3c24xx_iic_regs_t regs; |
897 | 897 | emu_timer *timer; |
898 | 898 | int count; |
899 | 899 | }; |
900 | 900 | |
901 | struct s3c24xx_iis_t | |
901 | struct s3c24xx_iis_t | |
902 | 902 | { |
903 | 903 | s3c24xx_iis_regs_t regs; |
904 | 904 | emu_timer *timer; |
r17959 | r17960 | |
906 | 906 | int fifo_index; |
907 | 907 | }; |
908 | 908 | |
909 | struct s3c24xx_gpio_t | |
909 | struct s3c24xx_gpio_t | |
910 | 910 | { |
911 | 911 | s3c24xx_gpio_regs_t regs; |
912 | 912 | }; |
913 | 913 | |
914 | struct s3c24xx_rtc_t | |
914 | struct s3c24xx_rtc_t | |
915 | 915 | { |
916 | 916 | s3c24xx_rtc_regs_t regs; |
917 | 917 | emu_timer *timer_tick_count; |
918 | 918 | emu_timer *timer_update; |
919 | 919 | }; |
920 | 920 | |
921 | struct s3c24xx_adc_t | |
921 | struct s3c24xx_adc_t | |
922 | 922 | { |
923 | 923 | s3c24xx_adc_regs_t regs; |
924 | 924 | }; |
925 | 925 | |
926 | struct s3c24xx_spi_t | |
926 | struct s3c24xx_spi_t | |
927 | 927 | { |
928 | 928 | s3c24xx_spi_regs_t regs; |
929 | 929 | }; |
930 | 930 | |
931 | struct s3c24xx_sdi_t | |
931 | struct s3c24xx_sdi_t | |
932 | 932 | { |
933 | 933 | s3c24xx_sdi_regs_t regs; |
934 | 934 | }; |
935 | 935 | |
936 | struct s3c24xx_ac97_t | |
936 | struct s3c24xx_ac97_t | |
937 | 937 | { |
938 | 938 | s3c24xx_ac97_regs_t regs; |
939 | 939 | }; |
940 | 940 | |
941 | struct s3c24xx_t | |
941 | struct s3c24xx_t | |
942 | 942 | { |
943 | 943 | const s3c2440_interface *iface; |
944 | 944 | UINT8 steppingstone[4*1024]; |
r17959 | r17960 | |
---|---|---|
68 | 68 | #if KEEP_STATISTICS |
69 | 69 | #define add_to_stat(v,x) do { v += (x); } while (0) |
70 | 70 | #define inc_stat(v) add_to_stat(v, 1) |
71 | #define begin_timing(v) | |
71 | #define begin_timing(v) | |
72 | 72 | #define end_timing(v) do { (v) += get_profile_ticks(); } while (0) |
73 | 73 | #else |
74 | 74 | #define add_to_stat(v,x) do { } while (0) |
r17959 | r17960 | |
386 | 386 | while ( (atime > 0) && (m_queue.is_not_empty())) |
387 | 387 | { |
388 | 388 | queue_t::entry_t e = m_queue.pop(); |
389 | ||
389 | ||
390 | 390 | |
391 | 391 | atime -= divu_64x32_rem(delta.as_raw(), m_div, &m_rem); |
392 | 392 | m_time_ps = e.time(); |
r17959 | r17960 | |
583 | 583 | if (out.object_type(net_output_t::SIGNAL_MASK) == net_output_t::SIGNAL_ANALOG |
584 | 584 | && in->object_type(net_output_t::SIGNAL_MASK) == net_output_t::SIGNAL_DIGITAL) |
585 | 585 | { |
586 | // fatalerror("connecting analog output %s with %s\n", out.netdev()->name(), in->netdev()->name()); | |
587 | // fatalerror("connecting analog output %s with %s\n", out.netdev()->name(), in->netdev()->name()); | |
586 | // fatalerror("connecting analog output %s with %s\n", out.netdev()->name(), in->netdev()->name()); | |
587 | // fatalerror("connecting analog output %s with %s\n", out.netdev()->name(), in->netdev()->name()); | |
588 | 588 | netdev_a_to_d_proxy *proxy = new netdev_a_to_d_proxy(*in); |
589 | 589 | proxy->init(this, "abc"); |
590 | 590 | proxy->start(); |
r17959 | r17960 | |
933 | 933 | void netlist_mame_device::device_stop() |
934 | 934 | { |
935 | 935 | m_setup->print_stats(); |
936 | ||
936 | ||
937 | 937 | global_free(m_setup); |
938 | 938 | global_free(m_netlist); |
939 | 939 | } |
r17959 | r17960 | |
972 | 972 | //bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0); |
973 | 973 | |
974 | 974 | // debugging |
975 | //m_ppc = m_pc; | |
975 | //m_ppc = m_pc; // copy PC to previous PC | |
976 | 976 | //if (check_debugger) |
977 | // | |
977 | // debugger_instruction_hook(this, 0); //m_pc); | |
978 | 978 | |
979 | 979 | m_netlist->process_list(m_icount); |
980 | 980 |
r17959 | r17960 | |
---|---|---|
10 | 10 | #ifndef KBDC8042_H |
11 | 11 | #define KBDC8042_H |
12 | 12 | |
13 | enum kbdc8042_type_t | |
13 | enum kbdc8042_type_t | |
14 | 14 | { |
15 | 15 | KBDC8042_STANDARD, |
16 | 16 | KBDC8042_PS2, /* another timing of integrated controller */ |
r17959 | r17960 | |
---|---|---|
58 | 58 | #define USE_DELEGATES (1) |
59 | 59 | #define USE_DELEGATES_A (0) |
60 | 60 | |
61 | #define NETLIST_CLOCK | |
61 | #define NETLIST_CLOCK | |
62 | 62 | |
63 | 63 | #define NLTIME_FROM_NS(_t) netlist_time::from_ns(_t) |
64 | 64 | #define NLTIME_FROM_US(_t) netlist_time::from_us(_t) |
r17959 | r17960 | |
100 | 100 | |
101 | 101 | #define NETLIST_END } |
102 | 102 | |
103 | #define NETLIST_INCLUDE(_name) | |
103 | #define NETLIST_INCLUDE(_name) | |
104 | 104 | NETLIST_NAME(_name)(netlist); \ |
105 | 105 | |
106 | 106 | |
107 | #define NETLIST_MEMREGION(_name) | |
107 | #define NETLIST_MEMREGION(_name) | |
108 | 108 | netlist.parse((char *)downcast<netlist_t &>(netlist.netlist()).machine().root_device().memregion(_name)->base()); \ |
109 | 109 | |
110 | 110 | #if defined(__GNUC__) && (__GNUC__ >= 3) |
r17959 | r17960 | |
129 | 129 | #define NETLIB_SIGNAL(_name, _num_input, _check) \ |
130 | 130 | class _name : public net_signal_t<_num_input, _check> \ |
131 | 131 | { \ |
132 | public: | |
132 | public: | |
133 | 133 | _name () : net_signal_t<_num_input, _check>() { } \ |
134 | 134 | }; \ |
135 | 135 | |
r17959 | r17960 | |
168 | 168 | |
169 | 169 | // MAME specific |
170 | 170 | |
171 | #define MCFG_NETLIST_ADD(_tag, _setup ) \ | |
172 | MCFG_DEVICE_ADD(_tag, NETLIST, NETLIST_CLOCK) \ | |
173 | MCFG_NETLIST_SETUP(_setup) \ | |
171 | #define MCFG_NETLIST_ADD(_tag, _setup ) \ | |
172 | MCFG_DEVICE_ADD(_tag, NETLIST, NETLIST_CLOCK) \ | |
173 | MCFG_NETLIST_SETUP(_setup) \ | |
174 | 174 | |
175 | #define MCFG_NETLIST_REPLACE(_tag, _setup) | |
175 | #define MCFG_NETLIST_REPLACE(_tag, _setup) | |
176 | 176 | MCFG_DEVICE_REPLACE(_tag, NETLIST, NETLIST_CLOCK) \ |
177 | MCFG_NETLIST_SETUP(_setup) | |
177 | MCFG_NETLIST_SETUP(_setup) | |
178 | 178 | |
179 | #define MCFG_NETLIST_SETUP(_setup) | |
179 | #define MCFG_NETLIST_SETUP(_setup) | |
180 | 180 | netlist_mame_device::static_set_constructor(*device, NETLIST_NAME(_setup)); \ |
181 | 181 | |
182 | 182 | |
r17959 | r17960 | |
402 | 402 | TYPE_MASK = 0x03, |
403 | 403 | SIGNAL_DIGITAL = 0x00, |
404 | 404 | SIGNAL_ANALOG = 0x10, |
405 | SIGNAL_MASK = | |
405 | SIGNAL_MASK = | |
406 | 406 | }; |
407 | 407 | |
408 | 408 | net_object_t(int atype) |
r17959 | r17960 | |
510 | 510 | |
511 | 511 | friend net_sig_t logic_input_t::Q() const; |
512 | 512 | |
513 | ATTR_HOT inline const net_sig_t last_Q() const { return m_last_Q; } | |
514 | ATTR_HOT inline const net_sig_t new_Q() const { return m_new_Q; } | |
513 | ATTR_HOT inline const net_sig_t last_Q() const { return m_last_Q; } | |
514 | ATTR_HOT inline const net_sig_t new_Q() const { return m_new_Q; } | |
515 | 515 | |
516 | 516 | ATTR_HOT inline const double Q_Analog() const |
517 | 517 | { |
r17959 | r17960 | |
519 | 519 | { |
520 | 520 | case SIGNAL_DIGITAL: return m_Q ? m_high_V : m_low_V; |
521 | 521 | case SIGNAL_ANALOG: return m_Q_analog; |
522 | default: | |
522 | default: | |
523 | 523 | } |
524 | 524 | |
525 | 525 | return 0; |
526 | 526 | } |
527 | 527 | |
528 | 528 | inline net_sig_t *Q_ptr() { return &m_Q; } |
529 | inline net_sig_t *new_Q_ptr() | |
529 | inline net_sig_t *new_Q_ptr() | |
530 | 530 | |
531 | 531 | ATTR_COLD void register_con(net_input_t &inp); |
532 | 532 | |
r17959 | r17960 | |
544 | 544 | protected: |
545 | 545 | |
546 | 546 | /* prohibit use in device functions |
547 | * current (pending) state can be inquired using new_Q() | |
548 | */ | |
549 | ATTR_HOT inline const net_sig_t Q() const { return m_Q; } | |
547 | * current (pending) state can be inquired using new_Q() | |
548 | */ | |
549 | ATTR_HOT inline const net_sig_t Q() const { return m_Q; } | |
550 | 550 | |
551 | 551 | ATTR_HOT inline void register_in_listPS(const netlist_time &delay_ps); |
552 | 552 | |
r17959 | r17960 | |
612 | 612 | } |
613 | 613 | |
614 | 614 | ATTR_COLD void initial(const net_sig_t val) { m_Q = val; m_new_Q = val; m_last_Q = !val; } |
615 | ATTR_HOT inline void clear() { set_Q_PS(0, netlist_time::zero); } | |
616 | ATTR_HOT inline void set() { set_Q_PS(1, netlist_time::zero); } | |
615 | ATTR_HOT inline void clear() { set_Q_PS(0, netlist_time::zero); } | |
616 | ATTR_HOT inline void set() { set_Q_PS(1, netlist_time::zero); } | |
617 | 617 | ATTR_HOT inline void setToPS(const UINT8 val, const netlist_time &delay_ps) { set_Q_PS(val, delay_ps); } |
618 | 618 | ATTR_HOT inline void setToNoCheckPS(const UINT8 val, const netlist_time &delay_ps) { set_Q_NoCheckPS(val, delay_ps); } |
619 | 619 | ATTR_COLD inline void set_levels(const double low, const double high) |
r17959 | r17960 | |
768 | 768 | inline void initial(const double val) { m_param = val; } |
769 | 769 | inline void initial(const int val) { m_param = val; } |
770 | 770 | |
771 | ATTR_HOT inline double Value() const { return m_param; | |
771 | ATTR_HOT inline double Value() const { return m_param; | |
772 | 772 | ATTR_HOT inline int ValueInt() const { return (int) m_param; } |
773 | 773 | |
774 | 774 | ATTR_HOT inline net_core_device_t &netdev() const { return *m_netdev; } |
r17959 | r17960 | |
922 | 922 | protected: |
923 | 923 | netlist_time m_time_ps; |
924 | 924 | UINT32 m_rem; |
925 | UINT32 | |
925 | UINT32 | |
926 | 926 | |
927 | 927 | queue_t m_queue; |
928 | 928 |
r17959 | r17960 | |
---|---|---|
46 | 46 | public: |
47 | 47 | latch8_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
48 | 48 | ~latch8_device() { global_free(m_token); } |
49 | ||
49 | ||
50 | 50 | // access to legacy token |
51 | 51 | void *token() const { assert(m_token != NULL); return m_token; } |
52 | 52 | latch8_config m_inline_config; |
53 | ||
54 | void set_maskout(UINT32 maskout) { m_inline_config.maskout = maskout; } | |
55 | void set_xorvalue(UINT32 xorvalue) { m_inline_config.xorvalue = xorvalue; } | |
56 | void set_nosync(UINT32 nosync) { m_inline_config.nosync = nosync; } | |
57 | ||
58 | void set_discrete_node(const char *dev_tag, int bit, UINT32 node) { m_inline_config.node_device[bit] = dev_tag; m_inline_config.node_map[bit] = node; } | |
59 | void set_devread(int bit, const char *tag, read8_device_func handler, int from_bit) | |
53 | ||
54 | void set_maskout(UINT32 maskout) { m_inline_config.maskout = maskout; } | |
55 | void set_xorvalue(UINT32 xorvalue) { m_inline_config.xorvalue = xorvalue; } | |
56 | void set_nosync(UINT32 nosync) { m_inline_config.nosync = nosync; } | |
57 | ||
58 | void set_discrete_node(const char *dev_tag, int bit, UINT32 node) { m_inline_config.node_device[bit] = dev_tag; m_inline_config.node_map[bit] = node; } | |
59 | void set_devread(int bit, const char *tag, read8_device_func handler, int from_bit) | |
60 | 60 | { |
61 | m_inline_config.devread[bit].from_bit = from_bit; | |
62 | m_inline_config.devread[bit].tag = tag; | |
63 | m_inline_config.devread[bit].devread_handler = handler; | |
61 | m_inline_config.devread[bit].from_bit = from_bit; | |
62 | m_inline_config.devread[bit].tag = tag; | |
63 | m_inline_config.devread[bit].devread_handler = handler; | |
64 | 64 | } |
65 | void set_read(int bit, read8_space_func handler, int from_bit) | |
65 | void set_read(int bit, read8_space_func handler, int from_bit) | |
66 | 66 | { |
67 | m_inline_config.devread[bit].from_bit = from_bit; | |
68 | m_inline_config.devread[bit].read_handler = handler; | |
69 | } | |
67 | m_inline_config.devread[bit].from_bit = from_bit; | |
68 | m_inline_config.devread[bit].read_handler = handler; | |
69 | } | |
70 | 70 | protected: |
71 | 71 | // device-level overrides |
72 | 72 | virtual void device_config_complete(); |
r17959 | r17960 | |
88 | 88 | |
89 | 89 | /* Bit mask specifying bits to be masked *out* */ |
90 | 90 | #define MCFG_LATCH8_MASKOUT(_maskout) \ |
91 | static_cast<latch8_device *>(device)->set_maskout(_maskout); | |
91 | static_cast<latch8_device *>(device)->set_maskout(_maskout); | |
92 | 92 | |
93 | 93 | /* Bit mask specifying bits to be inverted */ |
94 | 94 | #define MCFG_LATCH8_INVERT(_xor) \ |
r17959 | r17960 | |
---|---|---|
27 | 27 | // TYPE DEFINITIONS |
28 | 28 | //************************************************************************** |
29 | 29 | |
30 | struct rtc_regs_t | |
30 | struct rtc_regs_t | |
31 | 31 | { |
32 | 32 | UINT8 sec, min, hour, day, wday, month, year; |
33 | 33 | }; |
r17959 | r17960 | |
---|---|---|
113 | 113 | |
114 | 114 | DECLARE_READ8_MEMBER( read ); |
115 | 115 | DECLARE_WRITE8_MEMBER( write ); |
116 | ||
116 | ||
117 | 117 | UINT8 reg_r(UINT8 offset); |
118 | 118 | void reg_w(UINT8 offset, UINT8 data); |
119 | 119 |
r17959 | r17960 | |
---|---|---|
44 | 44 | |
45 | 45 | #define RX_FIFO_SIZE 3 |
46 | 46 | |
47 | struct DUART68681_CHANNEL | |
47 | struct DUART68681_CHANNEL | |
48 | 48 | { |
49 | 49 | /* Registers */ |
50 | 50 | UINT8 CR; /* Command register */ |
r17959 | r17960 | |
72 | 72 | |
73 | 73 | }; |
74 | 74 | |
75 | struct duart68681_state | |
75 | struct duart68681_state | |
76 | 76 | { |
77 | 77 | /* device */ |
78 | 78 | device_t *device; |
r17959 | r17960 | |
---|---|---|
62 | 62 | space->install_legacy_readwrite_handler( *device, 0x15800000, 0x15800007, FUNC(s3c24xx_adc_r), FUNC(s3c24xx_adc_w)); |
63 | 63 | space->install_legacy_readwrite_handler( *device, 0x15900000, 0x15900017, FUNC(s3c24xx_spi_0_r), FUNC(s3c24xx_spi_0_w)); |
64 | 64 | space->install_legacy_readwrite_handler( *device, 0x15a00000, 0x15a0003f, FUNC(s3c24xx_mmc_r), FUNC(s3c24xx_mmc_w)); |
65 | ||
65 | ||
66 | 66 | s3c24xx_video_start( device, device->machine()); |
67 | 67 | } |
68 | 68 |
r17959 | r17960 | |
---|---|---|
38 | 38 | public: |
39 | 39 | s3c2400_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
40 | 40 | ~s3c2400_device() { global_free(m_token); } |
41 | ||
41 | ||
42 | 42 | // access to legacy token |
43 | 43 | void *token() const { assert(m_token != NULL); return m_token; } |
44 | ||
44 | ||
45 | 45 | // device-level overrides |
46 | 46 | virtual void device_config_complete(); |
47 | 47 | virtual void device_start(); |
r17959 | r17960 | |
49 | 49 | private: |
50 | 50 | // internal state |
51 | 51 | void *m_token; |
52 | public: | |
52 | public: | |
53 | 53 | UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); |
54 | 54 | }; |
55 | 55 | |
r17959 | r17960 | |
407 | 407 | TYPE DEFINITIONS |
408 | 408 | *******************************************************************************/ |
409 | 409 | |
410 | struct s3c24xx_memcon_regs_t | |
410 | struct s3c24xx_memcon_regs_t | |
411 | 411 | { |
412 | 412 | UINT32 data[0x34/4]; |
413 | 413 | }; |
414 | 414 | |
415 | struct s3c24xx_usbhost_regs_t | |
415 | struct s3c24xx_usbhost_regs_t | |
416 | 416 | { |
417 | 417 | UINT32 data[0x5C/4]; |
418 | 418 | }; |
419 | 419 | |
420 | struct s3c24xx_irq_regs_t | |
420 | struct s3c24xx_irq_regs_t | |
421 | 421 | { |
422 | 422 | UINT32 srcpnd; |
423 | 423 | UINT32 intmod; |
r17959 | r17960 | |
427 | 427 | UINT32 intoffset; |
428 | 428 | }; |
429 | 429 | |
430 | struct s3c24xx_dma_regs_t | |
430 | struct s3c24xx_dma_regs_t | |
431 | 431 | { |
432 | 432 | UINT32 disrc; |
433 | 433 | UINT32 didst; |
r17959 | r17960 | |
438 | 438 | UINT32 dmasktrig; |
439 | 439 | }; |
440 | 440 | |
441 | struct s3c24xx_clkpow_regs_t | |
441 | struct s3c24xx_clkpow_regs_t | |
442 | 442 | { |
443 | 443 | UINT32 locktime; |
444 | 444 | UINT32 mpllcon; |
r17959 | r17960 | |
448 | 448 | UINT32 clkdivn; |
449 | 449 | }; |
450 | 450 | |
451 | struct s3c24xx_lcd_regs_t | |
451 | struct s3c24xx_lcd_regs_t | |
452 | 452 | { |
453 | 453 | UINT32 lcdcon1; |
454 | 454 | UINT32 lcdcon2; |
r17959 | r17960 | |
466 | 466 | UINT32 tpal; |
467 | 467 | }; |
468 | 468 | |
469 | struct s3c24xx_lcdpal_regs_t | |
469 | struct s3c24xx_lcdpal_regs_t | |
470 | 470 | { |
471 | 471 | UINT32 data[0x400/4]; |
472 | 472 | }; |
473 | 473 | |
474 | struct s3c24xx_uart_regs_t | |
474 | struct s3c24xx_uart_regs_t | |
475 | 475 | { |
476 | 476 | UINT32 ulcon; |
477 | 477 | UINT32 ucon; |
r17959 | r17960 | |
486 | 486 | UINT32 ubrdiv; |
487 | 487 | }; |
488 | 488 | |
489 | struct s3c24xx_pwm_regs_t | |
489 | struct s3c24xx_pwm_regs_t | |
490 | 490 | { |
491 | 491 | UINT32 tcfg0; |
492 | 492 | UINT32 tcfg1; |
r17959 | r17960 | |
507 | 507 | UINT32 tcnto4; |
508 | 508 | }; |
509 | 509 | |
510 | struct s3c24xx_usbdev_regs_t | |
510 | struct s3c24xx_usbdev_regs_t | |
511 | 511 | { |
512 | 512 | UINT32 data[0xBC/4]; |
513 | 513 | }; |
514 | 514 | |
515 | struct s3c24xx_wdt_regs_t | |
515 | struct s3c24xx_wdt_regs_t | |
516 | 516 | { |
517 | 517 | UINT32 wtcon; |
518 | 518 | UINT32 wtdat; |
519 | 519 | UINT32 wtcnt; |
520 | 520 | }; |
521 | 521 | |
522 | struct s3c24xx_iic_regs_t | |
522 | struct s3c24xx_iic_regs_t | |
523 | 523 | { |
524 | 524 | UINT32 iiccon; |
525 | 525 | UINT32 iicstat; |
r17959 | r17960 | |
527 | 527 | UINT32 iicds; |
528 | 528 | }; |
529 | 529 | |
530 | struct s3c24xx_iis_regs_t | |
530 | struct s3c24xx_iis_regs_t | |
531 | 531 | { |
532 | 532 | UINT32 iiscon; |
533 | 533 | UINT32 iismod; |
r17959 | r17960 | |
536 | 536 | UINT32 iisfifo; |
537 | 537 | }; |
538 | 538 | |
539 | struct s3c24xx_gpio_regs_t | |
539 | struct s3c24xx_gpio_regs_t | |
540 | 540 | { |
541 | 541 | UINT32 gpacon; |
542 | 542 | UINT32 gpadat; |
r17959 | r17960 | |
563 | 563 | UINT32 extint; |
564 | 564 | }; |
565 | 565 | |
566 | struct s3c24xx_rtc_regs_t | |
566 | struct s3c24xx_rtc_regs_t | |
567 | 567 | { |
568 | 568 | UINT32 rtccon; |
569 | 569 | UINT32 ticnt; |
r17959 | r17960 | |
585 | 585 | UINT32 bcdyear; |
586 | 586 | }; |
587 | 587 | |
588 | struct s3c24xx_adc_regs_t | |
588 | struct s3c24xx_adc_regs_t | |
589 | 589 | { |
590 | 590 | UINT32 adccon; |
591 | 591 | UINT32 adcdat; |
592 | 592 | }; |
593 | 593 | |
594 | struct s3c24xx_spi_regs_t | |
594 | struct s3c24xx_spi_regs_t | |
595 | 595 | { |
596 | 596 | UINT32 spcon; |
597 | 597 | UINT32 spsta; |
r17959 | r17960 | |
601 | 601 | UINT32 sprdat; |
602 | 602 | }; |
603 | 603 | |
604 | struct s3c24xx_mmc_regs_t | |
604 | struct s3c24xx_mmc_regs_t | |
605 | 605 | { |
606 | 606 | UINT32 data[0x40/4]; |
607 | 607 | }; |
608 | 608 | |
609 | struct s3c24xx_memcon_t | |
609 | struct s3c24xx_memcon_t | |
610 | 610 | { |
611 | 611 | s3c24xx_memcon_regs_t regs; |
612 | 612 | }; |
613 | 613 | |
614 | struct s3c24xx_usbhost_t | |
614 | struct s3c24xx_usbhost_t | |
615 | 615 | { |
616 | 616 | s3c24xx_usbhost_regs_t regs; |
617 | 617 | }; |
618 | 618 | |
619 | struct s3c24xx_irq_t | |
619 | struct s3c24xx_irq_t | |
620 | 620 | { |
621 | 621 | s3c24xx_irq_regs_t regs; |
622 | 622 | int line_irq, line_fiq; |
623 | 623 | }; |
624 | 624 | |
625 | struct s3c24xx_dma_t | |
625 | struct s3c24xx_dma_t | |
626 | 626 | { |
627 | 627 | s3c24xx_dma_regs_t regs; |
628 | 628 | emu_timer *timer; |
629 | 629 | }; |
630 | 630 | |
631 | struct s3c24xx_clkpow_t | |
631 | struct s3c24xx_clkpow_t | |
632 | 632 | { |
633 | 633 | s3c24xx_clkpow_regs_t regs; |
634 | 634 | }; |
635 | 635 | |
636 | struct s3c24xx_lcd_t | |
636 | struct s3c24xx_lcd_t | |
637 | 637 | { |
638 | 638 | s3c24xx_lcd_regs_t regs; |
639 | 639 | emu_timer *timer; |
r17959 | r17960 | |
652 | 652 | UINT32 dma_data, dma_bits; |
653 | 653 | }; |
654 | 654 | |
655 | struct s3c24xx_lcdpal_t | |
655 | struct s3c24xx_lcdpal_t | |
656 | 656 | { |
657 | 657 | s3c24xx_lcdpal_regs_t regs; |
658 | 658 | }; |
659 | 659 | |
660 | struct s3c24xx_uart_t | |
660 | struct s3c24xx_uart_t | |
661 | 661 | { |
662 | 662 | s3c24xx_uart_regs_t regs; |
663 | 663 | }; |
664 | 664 | |
665 | struct s3c24xx_pwm_t | |
665 | struct s3c24xx_pwm_t | |
666 | 666 | { |
667 | 667 | s3c24xx_pwm_regs_t regs; |
668 | 668 | emu_timer *timer[5]; |
r17959 | r17960 | |
671 | 671 | UINT32 freq[5]; |
672 | 672 | }; |
673 | 673 | |
674 | struct s3c24xx_usbdev_t | |
674 | struct s3c24xx_usbdev_t | |
675 | 675 | { |
676 | 676 | s3c24xx_usbdev_regs_t regs; |
677 | 677 | }; |
678 | 678 | |
679 | struct s3c24xx_wdt_t | |
679 | struct s3c24xx_wdt_t | |
680 | 680 | { |
681 | 681 | s3c24xx_wdt_regs_t regs; |
682 | 682 | emu_timer *timer; |
683 | 683 | }; |
684 | 684 | |
685 | struct s3c24xx_iic_t | |
685 | struct s3c24xx_iic_t | |
686 | 686 | { |
687 | 687 | s3c24xx_iic_regs_t regs; |
688 | 688 | emu_timer *timer; |
689 | 689 | int count; |
690 | 690 | }; |
691 | 691 | |
692 | struct s3c24xx_iis_t | |
692 | struct s3c24xx_iis_t | |
693 | 693 | { |
694 | 694 | s3c24xx_iis_regs_t regs; |
695 | 695 | emu_timer *timer; |
r17959 | r17960 | |
697 | 697 | int fifo_index; |
698 | 698 | }; |
699 | 699 | |
700 | struct s3c24xx_gpio_t | |
700 | struct s3c24xx_gpio_t | |
701 | 701 | { |
702 | 702 | s3c24xx_gpio_regs_t regs; |
703 | 703 | }; |
704 | 704 | |
705 | struct s3c24xx_rtc_t | |
705 | struct s3c24xx_rtc_t | |
706 | 706 | { |
707 | 707 | s3c24xx_rtc_regs_t regs; |
708 | 708 | emu_timer *timer_tick_count; |
709 | 709 | emu_timer *timer_update; |
710 | 710 | }; |
711 | 711 | |
712 | struct s3c24xx_adc_t | |
712 | struct s3c24xx_adc_t | |
713 | 713 | { |
714 | 714 | s3c24xx_adc_regs_t regs; |
715 | 715 | }; |
716 | 716 | |
717 | struct s3c24xx_spi_t | |
717 | struct s3c24xx_spi_t | |
718 | 718 | { |
719 | 719 | s3c24xx_spi_regs_t regs; |
720 | 720 | }; |
721 | 721 | |
722 | struct s3c24xx_mmc_t | |
722 | struct s3c24xx_mmc_t | |
723 | 723 | { |
724 | 724 | s3c24xx_mmc_regs_t regs; |
725 | 725 | }; |
726 | 726 | |
727 | struct s3c24xx_t | |
727 | struct s3c24xx_t | |
728 | 728 | { |
729 | 729 | const s3c2400_interface *iface; |
730 | 730 | s3c24xx_memcon_t memcon; |
r17959 | r17960 | |
---|---|---|
2 | 2 | |
3 | 3 | RP5H01 |
4 | 4 | |
5 | TODO: | |
6 | - convert to modern and follow the datasheet better (all dumps | |
7 | presumably needs to be redone from scratch?) | |
5 | TODO: | |
6 | - convert to modern and follow the datasheet better (all dumps | |
7 | presumably needs to be redone from scratch?) | |
8 | 8 | |
9 | 9 | 2009-06 Converted to be a device |
10 | 10 |
r17959 | r17960 | |
---|---|---|
26 | 26 | //************************************************************************** |
27 | 27 | |
28 | 28 | |
29 | enum rtc9701_state_t | |
29 | enum rtc9701_state_t | |
30 | 30 | { |
31 | 31 | RTC9701_CMD_WAIT = 0, |
32 | 32 | RTC9701_RTC_READ, |
r17959 | r17960 | |
37 | 37 | |
38 | 38 | }; |
39 | 39 | |
40 | struct rtc_regs_t | |
40 | struct rtc_regs_t | |
41 | 41 | { |
42 | 42 | UINT8 sec, min, hour, day, wday, month, year; |
43 | 43 | }; |
r17959 | r17960 | |
---|---|---|
210 | 210 | WRITE_LINE_MEMBER( s3520cf_device::write_bit ) |
211 | 211 | { |
212 | 212 | m_latch = state; |
213 | // | |
213 | // printf("%d LATCH LINE\n",state); | |
214 | 214 | } |
215 | 215 | |
216 | 216 | WRITE_LINE_MEMBER( s3520cf_device::set_clock_line ) |
r17959 | r17960 | |
---|---|---|
23 | 23 | // TYPE DEFINITIONS |
24 | 24 | //************************************************************************** |
25 | 25 | |
26 | enum s3520cf_state_t | |
26 | enum s3520cf_state_t | |
27 | 27 | { |
28 | 28 | RTC_SET_ADDRESS = 0, |
29 | 29 | RTC_SET_DATA |
30 | 30 | }; |
31 | 31 | |
32 | struct rtc_regs_t | |
32 | struct rtc_regs_t | |
33 | 33 | { |
34 | 34 | UINT8 sec, min, hour, day, wday, month, year; |
35 | 35 | }; |
r17959 | r17960 | |
---|---|---|
65 | 65 | space->install_legacy_readwrite_handler( *device, 0x59000000, 0x59000017, FUNC(s3c24xx_spi_0_r), FUNC(s3c24xx_spi_0_w)); |
66 | 66 | space->install_legacy_readwrite_handler( *device, 0x59000020, 0x59000037, FUNC(s3c24xx_spi_1_r), FUNC(s3c24xx_spi_1_w)); |
67 | 67 | space->install_legacy_readwrite_handler( *device, 0x5a000000, 0x5a000043, FUNC(s3c24xx_sdi_r), FUNC(s3c24xx_sdi_w)); |
68 | ||
68 | ||
69 | 69 | s3c24xx_video_start( device, device->machine()); |
70 | 70 | } |
71 | 71 |
r17959 | r17960 | |
---|---|---|
46 | 46 | public: |
47 | 47 | s3c2410_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
48 | 48 | ~s3c2410_device() { global_free(m_token); } |
49 | ||
49 | ||
50 | 50 | // access to legacy token |
51 | 51 | void *token() const { assert(m_token != NULL); return m_token; } |
52 | 52 | // device-level overrides |
r17959 | r17960 | |
56 | 56 | private: |
57 | 57 | // internal state |
58 | 58 | void *m_token; |
59 | public: | |
59 | public: | |
60 | 60 | UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); |
61 | 61 | }; |
62 | 62 | |
r17959 | r17960 | |
498 | 498 | TYPE DEFINITIONS |
499 | 499 | *******************************************************************************/ |
500 | 500 | |
501 | struct s3c24xx_memcon_regs_t | |
501 | struct s3c24xx_memcon_regs_t | |
502 | 502 | { |
503 | 503 | UINT32 data[0x34/4]; |
504 | 504 | }; |
505 | 505 | |
506 | struct s3c24xx_usbhost_regs_t | |
506 | struct s3c24xx_usbhost_regs_t | |
507 | 507 | { |
508 | 508 | UINT32 data[0x5C/4]; |
509 | 509 | }; |
510 | 510 | |
511 | struct s3c24xx_irq_regs_t | |
511 | struct s3c24xx_irq_regs_t | |
512 | 512 | { |
513 | 513 | UINT32 srcpnd; |
514 | 514 | UINT32 intmod; |
r17959 | r17960 | |
520 | 520 | UINT32 intsubmsk; |
521 | 521 | }; |
522 | 522 | |
523 | struct s3c24xx_dma_regs_t | |
523 | struct s3c24xx_dma_regs_t | |
524 | 524 | { |
525 | 525 | UINT32 disrc; |
526 | 526 | UINT32 disrcc; |
r17959 | r17960 | |
533 | 533 | UINT32 dmasktrig; |
534 | 534 | }; |
535 | 535 | |
536 | struct s3c24xx_clkpow_regs_t | |
536 | struct s3c24xx_clkpow_regs_t | |
537 | 537 | { |
538 | 538 | UINT32 locktime; |
539 | 539 | UINT32 mpllcon; |
r17959 | r17960 | |
543 | 543 | UINT32 clkdivn; |
544 | 544 | }; |
545 | 545 | |
546 | struct s3c24xx_lcd_regs_t | |
546 | struct s3c24xx_lcd_regs_t | |
547 | 547 | { |
548 | 548 | UINT32 lcdcon1; |
549 | 549 | UINT32 lcdcon2; |
r17959 | r17960 | |
565 | 565 | UINT32 lpcsel; |
566 | 566 | }; |
567 | 567 | |
568 | struct s3c24xx_lcdpal_regs_t | |
568 | struct s3c24xx_lcdpal_regs_t | |
569 | 569 | { |
570 | 570 | UINT32 data[0x400/4]; |
571 | 571 | }; |
572 | 572 | |
573 | struct s3c24xx_nand_regs_t | |
573 | struct s3c24xx_nand_regs_t | |
574 | 574 | { |
575 | 575 | UINT32 nfconf; |
576 | 576 | UINT32 nfcmd; |
r17959 | r17960 | |
580 | 580 | UINT32 nfecc; |
581 | 581 | }; |
582 | 582 | |
583 | struct s3c24xx_uart_regs_t | |
583 | struct s3c24xx_uart_regs_t | |
584 | 584 | { |
585 | 585 | UINT32 ulcon; |
586 | 586 | UINT32 ucon; |
r17959 | r17960 | |
595 | 595 | UINT32 ubrdiv; |
596 | 596 | }; |
597 | 597 | |
598 | struct s3c24xx_pwm_regs_t | |
598 | struct s3c24xx_pwm_regs_t | |
599 | 599 | { |
600 | 600 | UINT32 tcfg0; |
601 | 601 | UINT32 tcfg1; |
r17959 | r17960 | |
616 | 616 | UINT32 tcnto4; |
617 | 617 | }; |
618 | 618 | |
619 | struct s3c24xx_usbdev_regs_t | |
619 | struct s3c24xx_usbdev_regs_t | |
620 | 620 | { |
621 | 621 | UINT32 data[0x130/4]; |
622 | 622 | }; |
623 | 623 | |
624 | struct s3c24xx_wdt_regs_t | |
624 | struct s3c24xx_wdt_regs_t | |
625 | 625 | { |
626 | 626 | UINT32 wtcon; |
627 | 627 | UINT32 wtdat; |
628 | 628 | UINT32 wtcnt; |
629 | 629 | }; |
630 | 630 | |
631 | struct s3c24xx_iic_regs_t | |
631 | struct s3c24xx_iic_regs_t | |
632 | 632 | { |
633 | 633 | UINT32 iiccon; |
634 | 634 | UINT32 iicstat; |
r17959 | r17960 | |
636 | 636 | UINT32 iicds; |
637 | 637 | }; |
638 | 638 | |
639 | struct s3c24xx_iis_regs_t | |
639 | struct s3c24xx_iis_regs_t | |
640 | 640 | { |
641 | 641 | UINT32 iiscon; |
642 | 642 | UINT32 iismod; |
r17959 | r17960 | |
645 | 645 | UINT32 iisfifo; |
646 | 646 | }; |
647 | 647 | |
648 | struct s3c24xx_gpio_regs_t | |
648 | struct s3c24xx_gpio_regs_t | |
649 | 649 | { |
650 | 650 | UINT32 gpacon; |
651 | 651 | UINT32 gpadat; |
r17959 | r17960 | |
697 | 697 | UINT32 gstatus4; |
698 | 698 | }; |
699 | 699 | |
700 | struct s3c24xx_rtc_regs_t | |
700 | struct s3c24xx_rtc_regs_t | |
701 | 701 | { |
702 | 702 | UINT32 rtccon; |
703 | 703 | UINT32 ticnt; |
r17959 | r17960 | |
719 | 719 | UINT32 bcdyear; |
720 | 720 | }; |
721 | 721 | |
722 | struct s3c24xx_adc_regs_t | |
722 | struct s3c24xx_adc_regs_t | |
723 | 723 | { |
724 | 724 | UINT32 adccon; |
725 | 725 | UINT32 adctsc; |
r17959 | r17960 | |
728 | 728 | UINT32 adcdat1; |
729 | 729 | }; |
730 | 730 | |
731 | struct s3c24xx_spi_regs_t | |
731 | struct s3c24xx_spi_regs_t | |
732 | 732 | { |
733 | 733 | UINT32 spcon; |
734 | 734 | UINT32 spsta; |
r17959 | r17960 | |
738 | 738 | UINT32 sprdat; |
739 | 739 | }; |
740 | 740 | |
741 | struct s3c24xx_sdi_regs_t | |
741 | struct s3c24xx_sdi_regs_t | |
742 | 742 | { |
743 | 743 | UINT32 data[0x44/4]; |
744 | 744 | }; |
745 | 745 | |
746 | struct s3c24xx_memcon_t | |
746 | struct s3c24xx_memcon_t | |
747 | 747 | { |
748 | 748 | s3c24xx_memcon_regs_t regs; |
749 | 749 | }; |
750 | 750 | |
751 | struct s3c24xx_usbhost_t | |
751 | struct s3c24xx_usbhost_t | |
752 | 752 | { |
753 | 753 | s3c24xx_usbhost_regs_t regs; |
754 | 754 | }; |
755 | 755 | |
756 | struct s3c24xx_irq_t | |
756 | struct s3c24xx_irq_t | |
757 | 757 | { |
758 | 758 | s3c24xx_irq_regs_t regs; |
759 | 759 | int line_irq, line_fiq; |
760 | 760 | }; |
761 | 761 | |
762 | struct s3c24xx_dma_t | |
762 | struct s3c24xx_dma_t | |
763 | 763 | { |
764 | 764 | s3c24xx_dma_regs_t regs; |
765 | 765 | emu_timer *timer; |
766 | 766 | }; |
767 | 767 | |
768 | struct s3c24xx_clkpow_t | |
768 | struct s3c24xx_clkpow_t | |
769 | 769 | { |
770 | 770 | s3c24xx_clkpow_regs_t regs; |
771 | 771 | }; |
772 | 772 | |
773 | struct s3c24xx_lcd_t | |
773 | struct s3c24xx_lcd_t | |
774 | 774 | { |
775 | 775 | s3c24xx_lcd_regs_t regs; |
776 | 776 | emu_timer *timer; |
r17959 | r17960 | |
789 | 789 | UINT32 dma_data, dma_bits; |
790 | 790 | }; |
791 | 791 | |
792 | struct s3c24xx_lcdpal_t | |
792 | struct s3c24xx_lcdpal_t | |
793 | 793 | { |
794 | 794 | s3c24xx_lcdpal_regs_t regs; |
795 | 795 | }; |
796 | 796 | |
797 | struct s3c24xx_nand_t | |
797 | struct s3c24xx_nand_t | |
798 | 798 | { |
799 | 799 | s3c24xx_nand_regs_t regs; |
800 | 800 | UINT8 mecc[3]; |
801 | 801 | int ecc_pos, data_count; |
802 | 802 | }; |
803 | 803 | |
804 | struct s3c24xx_uart_t | |
804 | struct s3c24xx_uart_t | |
805 | 805 | { |
806 | 806 | s3c24xx_uart_regs_t regs; |
807 | 807 | }; |
808 | 808 | |
809 | struct s3c24xx_pwm_t | |
809 | struct s3c24xx_pwm_t | |
810 | 810 | { |
811 | 811 | s3c24xx_pwm_regs_t regs; |
812 | 812 | emu_timer *timer[5]; |
r17959 | r17960 | |
815 | 815 | UINT32 freq[5]; |
816 | 816 | }; |
817 | 817 | |
818 | struct s3c24xx_usbdev_t | |
818 | struct s3c24xx_usbdev_t | |
819 | 819 | { |
820 | 820 | s3c24xx_usbdev_regs_t regs; |
821 | 821 | }; |
822 | 822 | |
823 | struct s3c24xx_wdt_t | |
823 | struct s3c24xx_wdt_t | |
824 | 824 | { |
825 | 825 | s3c24xx_wdt_regs_t regs; |
826 | 826 | emu_timer *timer; |
827 | 827 | UINT32 freq, cnt; |
828 | 828 | }; |
829 | 829 | |
830 | struct s3c24xx_iic_t | |
830 | struct s3c24xx_iic_t | |
831 | 831 | { |
832 | 832 | s3c24xx_iic_regs_t regs; |
833 | 833 | emu_timer *timer; |
834 | 834 | int count; |
835 | 835 | }; |
836 | 836 | |
837 | struct s3c24xx_iis_t | |
837 | struct s3c24xx_iis_t | |
838 | 838 | { |
839 | 839 | s3c24xx_iis_regs_t regs; |
840 | 840 | emu_timer *timer; |
r17959 | r17960 | |
842 | 842 | int fifo_index; |
843 | 843 | }; |
844 | 844 | |
845 | struct s3c24xx_gpio_t | |
845 | struct s3c24xx_gpio_t | |
846 | 846 | { |
847 | 847 | s3c24xx_gpio_regs_t regs; |
848 | 848 | }; |
849 | 849 | |
850 | struct s3c24xx_rtc_t | |
850 | struct s3c24xx_rtc_t | |
851 | 851 | { |
852 | 852 | s3c24xx_rtc_regs_t regs; |
853 | 853 | emu_timer *timer_tick_count; |
854 | 854 | emu_timer *timer_update; |
855 | 855 | }; |
856 | 856 | |
857 | struct s3c24xx_adc_t | |
857 | struct s3c24xx_adc_t | |
858 | 858 | { |
859 | 859 | s3c24xx_adc_regs_t regs; |
860 | 860 | }; |
861 | 861 | |
862 | struct s3c24xx_spi_t | |
862 | struct s3c24xx_spi_t | |
863 | 863 | { |
864 | 864 | s3c24xx_spi_regs_t regs; |
865 | 865 | }; |
866 | 866 | |
867 | struct s3c24xx_sdi_t | |
867 | struct s3c24xx_sdi_t | |
868 | 868 | { |
869 | 869 | s3c24xx_sdi_regs_t regs; |
870 | 870 | }; |
871 | 871 | |
872 | struct s3c24xx_t | |
872 | struct s3c24xx_t | |
873 | 873 | { |
874 | 874 | const s3c2410_interface *iface; |
875 | 875 | UINT8 steppingstone[4*1024]; |
r17959 | r17960 | |
---|---|---|
910 | 910 | { |
911 | 911 | ENTRY(netdev_ttl_const, NETDEV_TTL_CONST) |
912 | 912 | ENTRY(netdev_analog_const, NETDEV_ANALOG_CONST) |
913 | ENTRY(netdev_logic_input, | |
913 | ENTRY(netdev_logic_input, | |
914 | 914 | ENTRY(netdev_analog_input, NETDEV_ANALOG_INPUT) |
915 | 915 | ENTRY(netdev_clock, NETDEV_CLOCK) |
916 | ENTRY(netdev_callback, NETDEV_CALLBACK) | |
917 | ENTRY(nicMultiSwitch, NETDEV_SWITCH2) | |
916 | ENTRY(netdev_callback, NETDEV_CALLBACK) | |
917 | ENTRY(nicMultiSwitch, NETDEV_SWITCH2) | |
918 | 918 | ENTRY(nicRSFF, NETDEV_RSFF) |
919 | 919 | ENTRY(nicMixer8, NETDEV_MIXER) |
920 | 920 | ENTRY(nic7400, TTL_7400_NAND) |
r17959 | r17960 | |
---|---|---|
94 | 94 | |
95 | 95 | #define TTL_7402_NOR(_name, _I1, _I2) \ |
96 | 96 | NET_REGISTER_DEV(nic7402, _name) \ |
97 | NET_CONNECT(_name, I1, _I1) | |
97 | NET_CONNECT(_name, I1, _I1) | |
98 | 98 | NET_CONNECT(_name, I2, _I2) \ |
99 | 99 | |
100 | 100 | #define TTL_7404_INVERT(_name, _I1) \ |
r17959 | r17960 | |
147 | 147 | |
148 | 148 | #define TTL_7486_XOR(_name, _I1, _I2) \ |
149 | 149 | NET_REGISTER_DEV(nic7486, _name) \ |
150 | NET_CONNECT(_name, I1, _I1) | |
150 | NET_CONNECT(_name, I1, _I1) | |
151 | 151 | NET_CONNECT(_name, I2, _I2) \ |
152 | 152 | |
153 | 153 | #define TTL_7448(_name, _A0, _A1, _A2, _A3, _LTQ, _BIQ, _RBIQ) \ |
r17959 | r17960 | |
201 | 201 | NET_CONNECT(_name, K, _K) \ |
202 | 202 | NET_CONNECT(_name, CLRQ, _CLRQ) \ |
203 | 203 | |
204 | #define TTL_74107(_name, _CLK, _J, _K, _CLRQ) | |
204 | #define TTL_74107(_name, _CLK, _J, _K, _CLRQ) | |
205 | 205 | TTL_74107A(_name, _CLK, _J, _K, _CLRQ) |
206 | 206 | |
207 | 207 | #define TTL_74153(_name, _A1, _A2, _A3, _A4, _A, _B, _GA) \ |
r17959 | r17960 | |
408 | 408 | { |
409 | 409 | public: |
410 | 410 | nic74107() |
411 | : | |
411 | : | |
412 | 412 | |
413 | 413 | }; |
414 | 414 |
r17959 | r17960 | |
---|---|---|
82 | 82 | UINT32 cycles_to_output; /* cycles until output callback called */ |
83 | 83 | }; |
84 | 84 | |
85 | struct | |
85 | struct | |
86 | 86 | { |
87 | 87 | const pit8253_config *config; |
88 | 88 | int device_type; |
r17959 | r17960 | |
---|---|---|
348 | 348 | m_pen_usage.resize(m_total_elements); |
349 | 349 | else |
350 | 350 | m_pen_usage.reset(); |
351 | ||
351 | ||
352 | 352 | // set the source |
353 | 353 | set_source(srcdata); |
354 | 354 | } |
r17959 | r17960 | |
402 | 402 | // zap the data to 0 |
403 | 403 | UINT8 *decode_base = m_gfxdata + code * m_char_modulo; |
404 | 404 | memset(decode_base, 0, m_char_modulo); |
405 | ||
405 | ||
406 | 406 | // iterate over planes |
407 | 407 | for (int plane = 0; plane < m_layout_planes; plane++) |
408 | 408 | { |
r17959 | r17960 | |
414 | 414 | { |
415 | 415 | int yoffs = planeoffs + m_layout_yoffset[y]; |
416 | 416 | UINT8 *dp = decode_base + y * rowbytes(); |
417 | ||
417 | ||
418 | 418 | // iterate over columns |
419 | 419 | for (int x = 0; x < m_origwidth; x++) |
420 | 420 | if (readbit(m_srcdata, yoffs + m_layout_xoffset[x])) |
r17959 | r17960 | |
---|---|---|
133 | 133 | UINT32 colors() const { return m_total_colors; } |
134 | 134 | UINT32 rowbytes() const { return m_line_modulo; } |
135 | 135 | bool has_pen_usage() const { return (m_pen_usage.count() > 0); } |
136 | ||
136 | ||
137 | 137 | // a bit gross that people muck with this stuff... |
138 | 138 | const UINT8 *srcdata() const { return m_srcdata; } |
139 | 139 | UINT32 dirtyseq() const { return m_dirtyseq; } |
r17959 | r17960 | |
156 | 156 | const UINT8 *get_data(UINT32 code) |
157 | 157 | { |
158 | 158 | assert(code < elements()); |
159 | if (code < m_dirty.count() && m_dirty[code]) decode(code); | |
159 | if (code < m_dirty.count() && m_dirty[code]) decode(code); | |
160 | 160 | return m_gfxdata + code * m_char_modulo + m_starty * m_line_modulo + m_startx; |
161 | 161 | } |
162 | ||
162 | ||
163 | 163 | UINT32 pen_usage(UINT32 code) |
164 | 164 | { |
165 | 165 | assert(code < m_pen_usage.count()); |
166 | if (m_dirty[code]) decode(code); | |
166 | if (m_dirty[code]) decode(code); | |
167 | 167 | return m_pen_usage[code]; |
168 | 168 | } |
169 | ||
169 | ||
170 | 170 | private: |
171 | 171 | // internal state |
172 | 172 | UINT16 m_width; // current pixel width of each element (changeble with source clipping) |
r17959 | r17960 | |
---|---|---|
60 | 60 | Structure that describes the state of a floppy drive, and the associated |
61 | 61 | disk image |
62 | 62 | */ |
63 | struct floppy_t | |
63 | struct floppy_t | |
64 | 64 | { |
65 | 65 | device_t *img; |
66 | 66 | emu_file *fd; |
r17959 | r17960 | |
80 | 80 | int is_400k; /* drive is single-sided, which means 400K */ |
81 | 81 | }; |
82 | 82 | |
83 | struct sonydriv_t | |
83 | struct sonydriv_t | |
84 | 84 | { |
85 | 85 | int lines; /* four lines SONY_CA0 - SONY_LSTRB */ |
86 | 86 |
r17959 | r17960 | |
---|---|---|
10 | 10 | #define IMGTERRS_H |
11 | 11 | |
12 | 12 | /* Error codes */ |
13 | enum imgtoolerr_t | |
13 | enum imgtoolerr_t | |
14 | 14 | { |
15 | 15 | IMGTOOLERR_SUCCESS, |
16 | 16 | IMGTOOLERR_OUTOFMEMORY, |
r17959 | r17960 | |
---|---|---|
12 | 12 | |
13 | 13 | |
14 | 14 | /* Supported character sets */ |
15 | enum imgtool_charset | |
15 | enum imgtool_charset | |
16 | 16 | { |
17 | 17 | IMGTOOL_CHARSET_UTF8, |
18 | 18 | IMGTOOL_CHARSET_ISO_8859_1, |
r17959 | r17960 | |
---|---|---|
30 | 30 | struct imgtool_directory; |
31 | 31 | struct imgtool_library; |
32 | 32 | |
33 | enum imgtool_suggestion_viability_t | |
33 | enum imgtool_suggestion_viability_t | |
34 | 34 | { |
35 | 35 | SUGGESTION_END, |
36 | 36 | SUGGESTION_POSSIBLE, |
r17959 | r17960 | |
51 | 51 | |
52 | 52 | typedef void (*filter_getinfoproc)(UINT32 state, union filterinfo *info); |
53 | 53 | |
54 | enum imgtool_libsort_t | |
54 | enum imgtool_libsort_t | |
55 | 55 | { |
56 | 56 | ITLS_NAME, |
57 | 57 | ITLS_DESCRIPTION |
58 | 58 | }; |
59 | 59 | |
60 | struct imgtool_dirent | |
60 | struct imgtool_dirent | |
61 | 61 | { |
62 | 62 | char filename[1024]; |
63 | 63 | char attr[64]; |
r17959 | r17960 | |
77 | 77 | unsigned int hardlink : 1; |
78 | 78 | }; |
79 | 79 | |
80 | struct imgtool_chainent | |
80 | struct imgtool_chainent | |
81 | 81 | { |
82 | 82 | UINT8 level; |
83 | 83 | UINT64 block; |
84 | 84 | }; |
85 | 85 | |
86 | enum imgtool_forktype_t | |
86 | enum imgtool_forktype_t | |
87 | 87 | { |
88 | 88 | FORK_END, |
89 | 89 | FORK_DATA, |
r17959 | r17960 | |
91 | 91 | FORK_ALTERNATE |
92 | 92 | }; |
93 | 93 | |
94 | struct imgtool_forkent | |
94 | struct imgtool_forkent | |
95 | 95 | { |
96 | 96 | imgtool_forktype_t type; |
97 | 97 | UINT64 size; |
98 | 98 | char forkname[64]; |
99 | 99 | }; |
100 | 100 | |
101 | struct imgtool_transfer_suggestion | |
101 | struct imgtool_transfer_suggestion | |
102 | 102 | { |
103 | 103 | imgtool_suggestion_viability_t viability; |
104 | 104 | filter_getinfoproc filter; |
r17959 | r17960 | |
134 | 134 | IMGTOOLATTR_TIME_LASTMODIFIED |
135 | 135 | }; |
136 | 136 | |
137 | union imgtool_attribute | |
137 | union imgtool_attribute | |
138 | 138 | { |
139 | 139 | INT64 i; |
140 | 140 | time_t t; |
141 | 141 | }; |
142 | 142 | |
143 | struct imgtool_iconinfo | |
143 | struct imgtool_iconinfo | |
144 | 144 | { |
145 | 145 | unsigned icon16x16_specified : 1; |
146 | 146 | unsigned icon32x32_specified : 1; |
r17959 | r17960 | |
---|---|---|
266 | 266 | Miscellaneous utilities that are used to handle TI data types |
267 | 267 | */ |
268 | 268 | |
269 | struct UINT16BE | |
269 | struct UINT16BE | |
270 | 270 | { |
271 | 271 | UINT8 bytes[2]; |
272 | 272 | }; |
273 | 273 | |
274 | struct UINT16LE | |
274 | struct UINT16LE | |
275 | 275 | { |
276 | 276 | UINT8 bytes[2]; |
277 | 277 | }; |
r17959 | r17960 | |
456 | 456 | /* |
457 | 457 | Disk geometry |
458 | 458 | */ |
459 | struct ti99_geometry | |
459 | struct ti99_geometry | |
460 | 460 | { |
461 | 461 | int secspertrack; |
462 | 462 | int cylinders; |
r17959 | r17960 | |
466 | 466 | /* |
467 | 467 | Physical sector address |
468 | 468 | */ |
469 | struct ti99_sector_address | |
469 | struct ti99_sector_address | |
470 | 470 | { |
471 | 471 | int sector; |
472 | 472 | int cylinder; |
r17959 | r17960 | |
476 | 476 | /* |
477 | 477 | Time stamp (used in fdr, and WIN VIB/DDR) |
478 | 478 | */ |
479 | struct ti99_date_time | |
479 | struct ti99_date_time | |
480 | 480 | { |
481 | 481 | UINT8 time_MSB, time_LSB;/* 0-4: hour, 5-10: minutes, 11-15: seconds/2 */ |
482 | 482 | UINT8 date_MSB, date_LSB;/* 0-6: year, 7-10: month, 11-15: day */ |
r17959 | r17960 | |
487 | 487 | |
488 | 488 | The HFDC supports up to 3 subdirectories. |
489 | 489 | */ |
490 | struct dsk_subdir | |
490 | struct dsk_subdir | |
491 | 491 | { |
492 | 492 | char name[10]; /* subdirectory name (10 characters, pad with spaces) */ |
493 | 493 | UINT16BE fdir_aphysrec; /* aphysrec address of fdir record for this subdirectory */ |
r17959 | r17960 | |
499 | 499 | Most fields in this record are only revelant to level 2 routines, but level |
500 | 500 | 1 routines need the disk geometry information extracted from the VIB. |
501 | 501 | */ |
502 | struct dsk_vib | |
502 | struct dsk_vib | |
503 | 503 | { |
504 | 504 | char name[10]; /* disk volume name (10 characters, pad with spaces) */ |
505 | 505 | UINT16BE totphysrecs; /* total number of physrecs on disk (usually 360, */ |
r17959 | r17960 | |
528 | 528 | /* of byte 1, etc.) */ |
529 | 529 | }; |
530 | 530 | |
531 | enum ti99_img_format | |
531 | enum ti99_img_format | |
532 | 532 | { |
533 | 533 | if_mess, |
534 | 534 | if_v9t9, |
r17959 | r17960 | |
540 | 540 | /* |
541 | 541 | level-1 disk image descriptor |
542 | 542 | */ |
543 | struct ti99_lvl1_imgref | |
543 | struct ti99_lvl1_imgref | |
544 | 544 | { |
545 | 545 | ti99_img_format img_format; /* tells the image format */ |
546 | 546 | imgtool_stream *file_handle; /* imgtool file handle */ |
r17959 | r17960 | |
1442 | 1442 | /* |
1443 | 1443 | AU format |
1444 | 1444 | */ |
1445 | struct ti99_AUformat | |
1445 | struct ti99_AUformat | |
1446 | 1446 | { |
1447 | 1447 | int totAUs; /* total number of AUs */ |
1448 | 1448 | int physrecsperAU; /* number of 256-byte physical records per AU */ |
r17959 | r17960 | |
1457 | 1457 | /* |
1458 | 1458 | catalog entry (used for in-memory catalog) |
1459 | 1459 | */ |
1460 | struct dir_entry | |
1460 | struct dir_entry | |
1461 | 1461 | { |
1462 | 1462 | UINT16 dir_ptr; /* DSK: unused */ |
1463 | 1463 | /* WIN: AU address of the DDR for this directory */ |
1464 | 1464 | char name[10]; /* name of this directory (copied from the VIB for DSK, DDR for WIN) */ |
1465 | 1465 | }; |
1466 | 1466 | |
1467 | struct file_entry | |
1467 | struct file_entry | |
1468 | 1468 | { |
1469 | 1469 | UINT16 fdr_ptr; /* DSK: aphysrec address of the FDR for this file */ |
1470 | 1470 | /* WIN: AU address of the FDR for this file */ |
1471 | 1471 | char name[10]; /* name of this file (copied from FDR) */ |
1472 | 1472 | }; |
1473 | 1473 | |
1474 | struct ti99_catalog | |
1474 | struct ti99_catalog | |
1475 | 1475 | { |
1476 | 1476 | int num_subdirs; /* number of subdirectories */ |
1477 | 1477 | int num_files; /* number of files */ |
r17959 | r17960 | |
1482 | 1482 | /* |
1483 | 1483 | level-2 disk image descriptor |
1484 | 1484 | */ |
1485 | struct ti99_lvl2_imgref_dsk | |
1485 | struct ti99_lvl2_imgref_dsk | |
1486 | 1486 | { |
1487 | 1487 | UINT16 totphysrecs; /* total number of aphysrecs (extracted from vib record in aphysrec 0) */ |
1488 | 1488 | ti99_catalog catalogs[4]; /* catalog of root directory and up to 3 subdirectories */ |
r17959 | r17960 | |
1495 | 1495 | win_vib_v1, |
1496 | 1496 | win_vib_v2 |
1497 | 1497 | }; |
1498 | struct ti99_lvl2_imgref_win | |
1498 | struct ti99_lvl2_imgref_win | |
1499 | 1499 | { |
1500 | 1500 | win_vib_t vib_version; /* version of the vib record in aphysrec 0 (see win_vib_ddr) */ |
1501 | 1501 | }; |
r17959 | r17960 | |
1555 | 1555 | /* |
1556 | 1556 | DSK FDR record |
1557 | 1557 | */ |
1558 | struct dsk_fdr | |
1558 | struct dsk_fdr | |
1559 | 1559 | { |
1560 | 1560 | char name[10]; /* file name (10 characters, pad with spaces) */ |
1561 | 1561 | UINT16BE xreclen; /* extended record len: if record len is >= 256, */ |
r17959 | r17960 | |
1601 | 1601 | /* |
1602 | 1602 | WIN FDR record |
1603 | 1603 | */ |
1604 | struct win_fdr | |
1604 | struct win_fdr | |
1605 | 1605 | { |
1606 | 1606 | char name[10]; /* file name (10 characters, pad with spaces) */ |
1607 | 1607 | UINT16BE xreclen; /* extended record len: if record len is >= 256, */ |
r17959 | r17960 | |
1663 | 1663 | /* |
1664 | 1664 | tifile header: stand-alone file |
1665 | 1665 | */ |
1666 | struct tifile_header | |
1666 | struct tifile_header | |
1667 | 1667 | { |
1668 | 1668 | char tifiles[8]; /* always '\7TIFILES' */ |
1669 | 1669 | UINT16BE fphysrecs; /* file length in physrecs */ |
r17959 | r17960 | |
1703 | 1703 | /* |
1704 | 1704 | level-2 file descriptor |
1705 | 1705 | */ |
1706 | struct ti99_lvl2_fileref_dsk | |
1706 | struct ti99_lvl2_fileref_dsk | |
1707 | 1707 | { |
1708 | 1708 | struct ti99_lvl2_imgref *l2_img; |
1709 | 1709 | int fdr_aphysrec; |
1710 | 1710 | dsk_fdr fdr; |
1711 | 1711 | }; |
1712 | 1712 | |
1713 | struct ti99_lvl2_fileref_win | |
1713 | struct ti99_lvl2_fileref_win | |
1714 | 1714 | { |
1715 | 1715 | struct ti99_lvl2_imgref *l2_img; |
1716 | 1716 | unsigned fphysrecs; /* copy of field in the eldest FDR */ |
r17959 | r17960 | |
1719 | 1719 | win_fdr curfdr; /* buffer with currently open sibling FDR */ |
1720 | 1720 | }; |
1721 | 1721 | |
1722 | struct ti99_lvl2_fileref_tifiles | |
1722 | struct ti99_lvl2_fileref_tifiles | |
1723 | 1723 | { |
1724 | 1724 | imgtool_stream *file_handle; |
1725 | 1725 | tifile_header hdr; |
r17959 | r17960 | |
3696 | 3696 | * files with variable-size records (sequential-access) |
3697 | 3697 | */ |
3698 | 3698 | |
3699 | struct ti99_lvl3_fileref | |
3699 | struct ti99_lvl3_fileref | |
3700 | 3700 | { |
3701 | 3701 | ti99_lvl2_fileref l2_file; |
3702 | 3702 | |
r17959 | r17960 | |
3827 | 3827 | /* |
3828 | 3828 | ti99 catalog iterator, used when imgtool reads the catalog |
3829 | 3829 | */ |
3830 | struct dsk_iterator | |
3830 | struct dsk_iterator | |
3831 | 3831 | { |
3832 | 3832 | struct ti99_lvl2_imgref *image; |
3833 | 3833 | int level; |
r17959 | r17960 | |
3836 | 3836 | ti99_catalog *cur_catalog; /* current catalog */ |
3837 | 3837 | }; |
3838 | 3838 | |
3839 | struct win_iterator | |
3839 | struct win_iterator | |
3840 | 3840 | { |
3841 | 3841 | struct ti99_lvl2_imgref *image; |
3842 | 3842 | int level; |
r17959 | r17960 | |
---|---|---|
114 | 114 | #pragma mark MISCELLANEOUS UTILITIES |
115 | 115 | #endif |
116 | 116 | |
117 | struct UINT16BE | |
117 | struct UINT16BE | |
118 | 118 | { |
119 | 119 | UINT8 bytes[2]; |
120 | 120 | }; |
121 | 121 | |
122 | struct UINT24BE | |
122 | struct UINT24BE | |
123 | 123 | { |
124 | 124 | UINT8 bytes[3]; |
125 | 125 | }; |
126 | 126 | |
127 | struct UINT32BE | |
127 | struct UINT32BE | |
128 | 128 | { |
129 | 129 | UINT8 bytes[4]; |
130 | 130 | }; |
r17959 | r17960 | |
181 | 181 | /* |
182 | 182 | point record, with the y and x coordinates |
183 | 183 | */ |
184 | struct mac_point | |
184 | struct mac_point | |
185 | 185 | { |
186 | 186 | UINT16BE v; /* actually signed */ |
187 | 187 | UINT16BE h; /* actually signed */ |
r17959 | r17960 | |
190 | 190 | /* |
191 | 191 | rect record, with the corner coordinates |
192 | 192 | */ |
193 | struct mac_rect | |
193 | struct mac_rect | |
194 | 194 | { |
195 | 195 | UINT16BE top; /* actually signed */ |
196 | 196 | UINT16BE left; /* actually signed */ |
r17959 | r17960 | |
226 | 226 | /* |
227 | 227 | FXInfo (Finder extended file info) record -- not found in MFS |
228 | 228 | */ |
229 | struct mac_FXInfo | |
229 | struct mac_FXInfo | |
230 | 230 | { |
231 | 231 | UINT16BE iconID; /* System 7: An ID number for the file???s icon; the |
232 | 232 | numbers that identify icons are assigned by the |
r17959 | r17960 | |
264 | 264 | /* |
265 | 265 | DXInfo (Finder extended folder info) record -- not found in MFS |
266 | 266 | */ |
267 | struct mac_DXInfo | |
267 | struct mac_DXInfo | |
268 | 268 | { |
269 | 269 | mac_point scroll; /* Scroll position */ |
270 | 270 | UINT32BE openChain; /* System 7: chain of directory IDs for open folders */ |
r17959 | r17960 | |
609 | 609 | /* |
610 | 610 | disk image reference |
611 | 611 | */ |
612 | struct mac_l1_imgref | |
612 | struct mac_l1_imgref | |
613 | 613 | { |
614 | 614 | imgtool_image *image; |
615 | 615 | UINT32 heads; |
r17959 | r17960 | |
744 | 744 | #pragma mark MFS/HFS WRAPPERS |
745 | 745 | #endif |
746 | 746 | |
747 | enum mac_format | |
747 | enum mac_format | |
748 | 748 | { |
749 | 749 | L2I_MFS, |
750 | 750 | L2I_HFS |
r17959 | r17960 | |
755 | 755 | /* |
756 | 756 | MFS image ref |
757 | 757 | */ |
758 | struct mfs_l2_imgref | |
758 | struct mfs_l2_imgref | |
759 | 759 | { |
760 | 760 | UINT16 dir_num_files; |
761 | 761 | UINT16 dir_start; |
r17959 | r17960 | |
772 | 772 | /* |
773 | 773 | HFS extent descriptor |
774 | 774 | */ |
775 | struct hfs_extent | |
775 | struct hfs_extent | |
776 | 776 | { |
777 | 777 | UINT16BE stABN; /* first allocation block */ |
778 | 778 | UINT16BE numABlks; /* number of allocation blocks */ |
r17959 | r17960 | |
787 | 787 | /* |
788 | 788 | MFS open file ref |
789 | 789 | */ |
790 | struct mfs_fileref | |
790 | struct mfs_fileref | |
791 | 791 | { |
792 | 792 | UINT16 stBlk; /* first allocation block of file */ |
793 | 793 | }; |
r17959 | r17960 | |
795 | 795 | /* |
796 | 796 | HFS open file ref |
797 | 797 | */ |
798 | struct hfs_fileref | |
798 | struct hfs_fileref | |
799 | 799 | { |
800 | 800 | hfs_extent_3 extents; /* first 3 file extents */ |
801 | 801 | |
r17959 | r17960 | |
834 | 834 | /* |
835 | 835 | open BT ref |
836 | 836 | */ |
837 | struct mac_BTref | |
837 | struct mac_BTref | |
838 | 838 | { |
839 | 839 | struct mac_fileref fileref; /* open B-tree file ref */ |
840 | 840 | |
r17959 | r17960 | |
864 | 864 | /* |
865 | 865 | HFS image ref |
866 | 866 | */ |
867 | struct hfs_l2_imgref | |
867 | struct hfs_l2_imgref | |
868 | 868 | { |
869 | 869 | UINT16 VBM_start; |
870 | 870 | |
r17959 | r17960 | |
998 | 998 | }; |
999 | 999 | |
1000 | 1000 | /* to save a little stack space, we use the same buffer for MDB and next blocks */ |
1001 | union img_open_buf | |
1001 | union img_open_buf | |
1002 | 1002 | { |
1003 | 1003 | struct mfs_mdb mfs_mdb; |
1004 | 1004 | struct hfs_mdb hfs_mdb; |
r17959 | r17960 | |
1008 | 1008 | /* |
1009 | 1009 | Information extracted from catalog/directory |
1010 | 1010 | */ |
1011 | struct mac_dirent | |
1011 | struct mac_dirent | |
1012 | 1012 | { |
1013 | 1013 | UINT16 dataRecType; /* type of data record */ |
1014 | 1014 | |
r17959 | r17960 | |
1033 | 1033 | |
1034 | 1034 | And, no, I don't know the format of the 20-byte tag record of the HD20 |
1035 | 1035 | */ |
1036 | struct floppy_tag_record | |
1036 | struct floppy_tag_record | |
1037 | 1037 | { |
1038 | 1038 | UINT32BE fileID; /* a.k.a. CNID */ |
1039 | 1039 | /* a value of 1 seems to be the default for non-AB blocks, but this is not consistent */ |
r17959 | r17960 | |
1452 | 1452 | files appear does not match file names, and it does not always match file |
1453 | 1453 | IDs. |
1454 | 1454 | */ |
1455 | struct mfs_dir_entry | |
1455 | struct mfs_dir_entry | |
1456 | 1456 | { |
1457 | 1457 | UINT8 flags; /* bit 7=1 if entry used, bit 0=1 if file locked */ |
1458 | 1458 | /* 0x00 means end of block: if we are not done |
r17959 | r17960 | |
1527 | 1527 | /* |
1528 | 1528 | MFS open dir ref |
1529 | 1529 | */ |
1530 | struct mfs_dirref | |
1530 | struct mfs_dirref | |
1531 | 1531 | { |
1532 | 1532 | struct mac_l2_imgref *l2_img; /* image pointer */ |
1533 | 1533 | UINT16 index; /* current file index in the disk directory */ |
r17959 | r17960 | |
2770 | 2770 | /* |
2771 | 2771 | HFS extents B-tree key |
2772 | 2772 | */ |
2773 | struct hfs_extentKey | |
2773 | struct hfs_extentKey | |
2774 | 2774 | { |
2775 | 2775 | UINT8 keyLength; /* length of key, excluding this field */ |
2776 | 2776 | UINT8 forkType; /* 0 = data fork, FF = resource fork */ |
r17959 | r17960 | |
2785 | 2785 | /* |
2786 | 2786 | HFS catalog B-tree key |
2787 | 2787 | */ |
2788 | struct hfs_catKey | |
2788 | struct hfs_catKey | |
2789 | 2789 | { |
2790 | 2790 | UINT8 keyLen; /* key length */ |
2791 | 2791 | UINT8 resrv1; /* reserved */ |
r17959 | r17960 | |
2798 | 2798 | /* |
2799 | 2799 | HFS catalog data record for a folder - 70 bytes |
2800 | 2800 | */ |
2801 | struct hfs_catFolderData | |
2801 | struct hfs_catFolderData | |
2802 | 2802 | { |
2803 | 2803 | UINT16BE recordType; /* record type */ |
2804 | 2804 | UINT16BE flags; /* folder flags */ |
r17959 | r17960 | |
2815 | 2815 | /* |
2816 | 2816 | HFS catalog data record for a file - 102 bytes |
2817 | 2817 | */ |
2818 | struct hfs_catFileData | |
2818 | struct hfs_catFileData | |
2819 | 2819 | { |
2820 | 2820 | UINT16BE recordType; /* record type */ |
2821 | 2821 | UINT8 flags; /* file flags */ |
r17959 | r17960 | |
2844 | 2844 | The key for a thread record features the CNID of the item and an empty |
2845 | 2845 | name, instead of the CNID of the parent and the item name. |
2846 | 2846 | */ |
2847 | struct hfs_catThreadData | |
2847 | struct hfs_catThreadData | |
2848 | 2848 | { |
2849 | 2849 | UINT16BE recordType; /* record type */ |
2850 | 2850 | UINT32BE reserved[2]; /* reserved - set to zero */ |
r17959 | r17960 | |
2855 | 2855 | /* |
2856 | 2856 | union for all types at once |
2857 | 2857 | */ |
2858 | union hfs_catData | |
2858 | union hfs_catData | |
2859 | 2859 | { |
2860 | 2860 | UINT16BE dataType; |
2861 | 2861 | hfs_catFolderData folder; |
r17959 | r17960 | |
2890 | 2890 | /* |
2891 | 2891 | BT functions used by HFS functions |
2892 | 2892 | */ |
2893 | struct BT_leaf_rec_enumerator | |
2893 | struct BT_leaf_rec_enumerator | |
2894 | 2894 | { |
2895 | 2895 | mac_BTref *BTref; |
2896 | 2896 | UINT32 cur_node; |
r17959 | r17960 | |
2907 | 2907 | static imgtoolerr_t BT_leaf_rec_enumerator_open(mac_BTref *BTref, BT_leaf_rec_enumerator *enumerator); |
2908 | 2908 | static imgtoolerr_t BT_leaf_rec_enumerator_read(BT_leaf_rec_enumerator *enumerator, void **record_ptr, int *rec_len); |
2909 | 2909 | |
2910 | struct hfs_cat_enumerator | |
2910 | struct hfs_cat_enumerator | |
2911 | 2911 | { |
2912 | 2912 | struct mac_l2_imgref *l2_img; |
2913 | 2913 | BT_leaf_rec_enumerator BT_enumerator; |
r17959 | r17960 | |
3640 | 3640 | |
3641 | 3641 | Header of a node record |
3642 | 3642 | */ |
3643 | struct BTNodeHeader | |
3643 | struct BTNodeHeader | |
3644 | 3644 | { |
3645 | 3645 | UINT32BE fLink; /* (index of) next node at this level */ |
3646 | 3646 | UINT32BE bLink; /* (index of) previous node at this level */ |
r17959 | r17960 | |
3672 | 3672 | BTHeaderRecord: first record of a B-tree header node (second record is |
3673 | 3673 | unused, and third is node allocation bitmap). |
3674 | 3674 | */ |
3675 | struct BTHeaderRecord | |
3675 | struct BTHeaderRecord | |
3676 | 3676 | { |
3677 | 3677 | UINT16BE treeDepth; /* maximum height (usually leaf nodes) */ |
3678 | 3678 | UINT32BE rootNode; /* node number of root node */ |
r17959 | r17960 | |
3955 | 3955 | |
3956 | 3956 | Return imgtool error code |
3957 | 3957 | */ |
3958 | struct data_nodes_t | |
3958 | struct data_nodes_t | |
3959 | 3959 | { |
3960 | 3960 | void *buf; |
3961 | 3961 | UINT32 node_num; |
r17959 | r17960 | |
4842 | 4842 | /* |
4843 | 4843 | Resource header |
4844 | 4844 | */ |
4845 | struct rsrc_header | |
4845 | struct rsrc_header | |
4846 | 4846 | { |
4847 | 4847 | UINT32BE data_offs; /* Offset from beginning of resource fork to resource data */ |
4848 | 4848 | UINT32BE map_offs; /* Offset from beginning of resource fork to resource map */ |
r17959 | r17960 | |
4858 | 4858 | /* |
4859 | 4859 | Resource map: |
4860 | 4860 | */ |
4861 | struct rsrc_map_header | |
4861 | struct rsrc_map_header | |
4862 | 4862 | { |
4863 | 4863 | rsrc_header reserved0; /* Reserved for copy of resource header */ |
4864 | 4864 | UINT32BE reserved1; /* Reserved for handle to next resource map */ |
r17959 | r17960 | |
4874 | 4874 | /* |
4875 | 4875 | Resource type list entry |
4876 | 4876 | */ |
4877 | struct rsrc_type_entry | |
4877 | struct rsrc_type_entry | |
4878 | 4878 | { |
4879 | 4879 | UINT32BE type; /* Resource type */ |
4880 | 4880 | UINT16BE ref_count; /* Number of resources of this type in map minus 1 */ |
r17959 | r17960 | |
4884 | 4884 | /* |
4885 | 4885 | Resource reference list entry |
4886 | 4886 | */ |
4887 | struct rsrc_ref_entry | |
4887 | struct rsrc_ref_entry | |
4888 | 4888 | { |
4889 | 4889 | UINT16BE id; /* Resource ID */ |
4890 | 4890 | UINT16BE name_offs; /* Offset from beginning of resource name list to resource name */ |
r17959 | r17960 | |
4898 | 4898 | Resource name list entry: this is just a standard macintosh string |
4899 | 4899 | */ |
4900 | 4900 | |
4901 | struct mac_resfileref | |
4901 | struct mac_resfileref | |
4902 | 4902 | { |
4903 | 4903 | mac_fileref fileref; /* open resource fork ref (you may open resources |
4904 | 4904 | files in data fork, too, if you ever need to, |
r17959 | r17960 | |
---|---|---|
12 | 12 | |
13 | 13 | #include "imgtool.h" |
14 | 14 | |
15 | enum mac_fork_t | |
15 | enum mac_fork_t | |
16 | 16 | { |
17 | 17 | MAC_FORK_DATA, |
18 | 18 | MAC_FORK_RESOURCE |
19 | 19 | }; |
20 | 20 | |
21 | enum mac_filecategory_t | |
21 | enum mac_filecategory_t | |
22 | 22 | { |
23 | 23 | MAC_FILECATEGORY_DATA, |
24 | 24 | MAC_FILECATEGORY_TEXT, |
r17959 | r17960 | |
---|---|---|
40 | 40 | #define MAX_DIRENTS (15*8) |
41 | 41 | |
42 | 42 | /* vzdos directry entry */ |
43 | struct vzdos_dirent | |
43 | struct vzdos_dirent | |
44 | 44 | { |
45 | 45 | char ftype; |
46 | 46 | char delimitor; |
r17959 | r17960 | |
51 | 51 | UINT16 end_address; |
52 | 52 | }; |
53 | 53 | |
54 | struct vz_iterator | |
54 | struct vz_iterator | |
55 | 55 | { |
56 | 56 | int index; |
57 | 57 | int eof; |
r17959 | r17960 | |
---|---|---|
175 | 175 | UINT32 putaway_directory; |
176 | 176 | }; |
177 | 177 | |
178 | enum creation_policy_t | |
178 | enum creation_policy_t | |
179 | 179 | { |
180 | 180 | CREATE_NONE, |
181 | 181 | CREATE_FILE, |
r17959 | r17960 | |
---|---|---|
13 | 13 | #include "formats/coco_dsk.h" |
14 | 14 | #include "iflopimg.h" |
15 | 15 | |
16 | enum creation_policy_t | |
16 | enum creation_policy_t | |
17 | 17 | { |
18 | 18 | CREATE_NONE, |
19 | 19 | CREATE_FILE, |
r17959 | r17960 | |
---|---|---|
201 | 201 | UINT8 sectors; |
202 | 202 | }; |
203 | 203 | |
204 | enum creation_policy_t | |
204 | enum creation_policy_t | |
205 | 205 | { |
206 | 206 | CREATE_NONE, |
207 | 207 | CREATE_FILE, |
r17959 | r17960 | |
1395 | 1395 | |
1396 | 1396 | |
1397 | 1397 | |
1398 | enum sfn_disposition_t | |
1398 | enum sfn_disposition_t | |
1399 | 1399 | { |
1400 | 1400 | SFN_SUFFICIENT, /* name fully representable in short file name */ |
1401 | 1401 | SFN_DERIVATIVE, /* name not fully representable in short file name, but no need to tildize */ |
r17959 | r17960 | |
---|---|---|
33 | 33 | #define MSIZE ((BSIZE/4) - 1) /* Size of bitmaps */ |
34 | 34 | |
35 | 35 | |
36 | enum disk_type | |
36 | enum disk_type | |
37 | 37 | { |
38 | 38 | DT_UNKNOWN = -1, |
39 | 39 | DT_OFS = 0, |
r17959 | r17960 | |
55 | 55 | }; |
56 | 56 | |
57 | 57 | |
58 | enum sec_type | |
58 | enum sec_type | |
59 | 59 | { |
60 | 60 | ST_INVALID = 0, |
61 | 61 | ST_ROOT = 1, |
r17959 | r17960 | |
---|---|---|
35 | 35 | #define MAX_DIR_LEVEL 25 /* We need to put a recursion limit to avoid endless recursion hazard */ |
36 | 36 | |
37 | 37 | |
38 | struct UINT16BE | |
38 | struct UINT16BE | |
39 | 39 | { |
40 | 40 | UINT8 bytes[2]; |
41 | 41 | }; |
42 | 42 | |
43 | struct UINT32BE | |
43 | struct UINT32BE | |
44 | 44 | { |
45 | 45 | UINT8 bytes[4]; |
46 | 46 | }; |
r17959 | r17960 | |
72 | 72 | /* |
73 | 73 | disk image header |
74 | 74 | */ |
75 | struct disk_image_header | |
75 | struct disk_image_header | |
76 | 76 | { |
77 | 77 | UINT32BE cylinders; /* number of cylinders on hard disk (big-endian) */ |
78 | 78 | UINT32BE heads; /* number of heads on hard disk (big-endian) */ |
r17959 | r17960 | |
101 | 101 | /* |
102 | 102 | SC0 record (Disk sector 0) |
103 | 103 | */ |
104 | struct ti990_sc0 | |
104 | struct ti990_sc0 | |
105 | 105 | { |
106 | 106 | char vnm[8]; /* volume name */ |
107 | 107 | UINT16BE tna; /* total number of ADUs */ |
r17959 | r17960 | |
153 | 153 | /* |
154 | 154 | DOR (Directory Overhead Record) |
155 | 155 | */ |
156 | struct ti990_dor | |
156 | struct ti990_dor | |
157 | 157 | { |
158 | 158 | UINT16BE nrc; /* # records in directory (minus DOR) nrc = nfl + nar (+ tfc???) */ |
159 | 159 | UINT16BE nfl; /* # files currently in directory */ |
r17959 | r17960 | |
198 | 198 | /* |
199 | 199 | ACE subrecord found in FDR |
200 | 200 | */ |
201 | struct ti990_ace | |
201 | struct ti990_ace | |
202 | 202 | { |
203 | 203 | char agn[8]; /* access group name */ |
204 | 204 | UINT16BE flg; /* flags */ |
r17959 | r17960 | |
207 | 207 | /* |
208 | 208 | FDR record |
209 | 209 | */ |
210 | struct ti990_fdr | |
210 | struct ti990_fdr | |
211 | 211 | { |
212 | 212 | UINT16BE hkc; /* hask key count: the number of file descriptor records that are present in the directory that hashed to this record number */ |
213 | 213 | UINT16BE hkv; /* hask key value: the result of the hash algorithm for the file name actually covered in this record */ |
r17959 | r17960 | |
251 | 251 | The fields marked here with *** are in the ADR template to maintain |
252 | 252 | compatability with the FDR template. |
253 | 253 | */ |
254 | struct ti990_adr | |
254 | struct ti990_adr | |
255 | 255 | { |
256 | 256 | UINT16BE hkc; /* hask key count */ |
257 | 257 | UINT16BE hkv; /* hask key value */ |
r17959 | r17960 | |
274 | 274 | The CDR is the permanent record of a channel. It is carried as an alias |
275 | 275 | of the program file in which the channel owner task resides. |
276 | 276 | */ |
277 | struct ti990_cdr | |
277 | struct ti990_cdr | |
278 | 278 | { |
279 | 279 | UINT16BE hkc; /* hask key count */ |
280 | 280 | UINT16BE hkv; /* hask key value */ |
r17959 | r17960 | |
305 | 305 | field starts at offset 4, and therefore if we try to interpret a KDR as an |
306 | 306 | FDR (or ADR, CDR), we will find fnm[0] and assume the FDR is empty. |
307 | 307 | */ |
308 | union directory_entry | |
308 | union directory_entry | |
309 | 309 | { |
310 | 310 | ti990_fdr fdr; |
311 | 311 | ti990_adr adr; |
r17959 | r17960 | |
317 | 317 | /* |
318 | 318 | tifile header: stand-alone file |
319 | 319 | */ |
320 | struct tifile_header | |
320 | struct tifile_header | |
321 | 321 | { |
322 | 322 | char tifiles[8]; /* always '\7TIFILES' */ |
323 | 323 | UINT8 secsused_MSB; /* file length in sectors (big-endian) */ |
r17959 | r17960 | |
335 | 335 | /* |
336 | 336 | catalog entry (used for in-memory catalog) |
337 | 337 | */ |
338 | struct catalog_entry | |
338 | struct catalog_entry | |
339 | 339 | { |
340 | 340 | UINT16 fdr_secnum; |
341 | 341 | char filename[10]; |
r17959 | r17960 | |
346 | 346 | /* |
347 | 347 | Disk geometry |
348 | 348 | */ |
349 | struct ti990_geometry | |
349 | struct ti990_geometry | |
350 | 350 | { |
351 | 351 | unsigned int cylinders, heads, sectors_per_track, bytes_per_sector; |
352 | 352 | }; |
r17959 | r17960 | |
354 | 354 | /* |
355 | 355 | Physical sector address |
356 | 356 | */ |
357 | struct ti990_phys_sec_address | |
357 | struct ti990_phys_sec_address | |
358 | 358 | { |
359 | 359 | int cylinder; |
360 | 360 | int head; |
r17959 | r17960 | |
364 | 364 | /* |
365 | 365 | ti99 disk image descriptor |
366 | 366 | */ |
367 | struct ti990_image | |
367 | struct ti990_image | |
368 | 368 | { |
369 | 369 | imgtool_stream *file_handle; /* imgtool file handle */ |
370 | 370 | ti990_geometry geometry; /* geometry */ |
r17959 | r17960 | |
374 | 374 | /* |
375 | 375 | ti990 catalog iterator, used when imgtool reads the catalog |
376 | 376 | */ |
377 | struct ti990_iterator | |
377 | struct ti990_iterator | |
378 | 378 | { |
379 | 379 | ti990_image *image; |
380 | 380 | int level; /* current recursion level */ |
r17959 | r17960 | |
---|---|---|
12 | 12 | #include <limits.h> |
13 | 13 | #include "imgtool.h" |
14 | 14 | |
15 | struct UINT16xE | |
15 | struct UINT16xE | |
16 | 16 | { |
17 | 17 | UINT8 bytes[2]; |
18 | 18 | }; |
r17959 | r17960 | |
69 | 69 | device directory record (Disk sector 2-5) |
70 | 70 | */ |
71 | 71 | |
72 | struct concept_vol_hdr_entry | |
72 | struct concept_vol_hdr_entry | |
73 | 73 | { |
74 | 74 | UINT16xE first_block; |
75 | 75 | UINT16xE next_block; |
r17959 | r17960 | |
85 | 85 | UINT16xE unused; |
86 | 86 | }; |
87 | 87 | |
88 | struct concept_file_dir_entry | |
88 | struct concept_file_dir_entry | |
89 | 89 | { |
90 | 90 | UINT16xE first_block; |
91 | 91 | UINT16xE next_block; |
r17959 | r17960 | |
96 | 96 | UINT16xE last_access; |
97 | 97 | }; |
98 | 98 | |
99 | struct concept_dev_dir | |
99 | struct concept_dev_dir | |
100 | 100 | { |
101 | 101 | concept_vol_hdr_entry vol_hdr; |
102 | 102 | concept_file_dir_entry file_dir[77]; |
r17959 | r17960 | |
106 | 106 | /* |
107 | 107 | concept disk image descriptor |
108 | 108 | */ |
109 | struct concept_image | |
109 | struct concept_image | |
110 | 110 | { |
111 | 111 | imgtool_stream *file_handle; /* imgtool file handle */ |
112 | 112 | concept_dev_dir dev_dir; /* cached copy of device directory */ |
r17959 | r17960 | |
115 | 115 | /* |
116 | 116 | concept catalog iterator, used when imgtool reads the catalog |
117 | 117 | */ |
118 | struct concept_iterator | |
118 | struct concept_iterator | |
119 | 119 | { |
120 | 120 | concept_image *image; |
121 | 121 | int index; /* current index */ |
r17959 | r17960 | |
---|---|---|
14 | 14 | #include "osdcore.h" |
15 | 15 | #include "imgtool.h" |
16 | 16 | |
17 | enum imgtype_t | |
17 | enum imgtype_t | |
18 | 18 | { |
19 | 19 | IMG_FILE, |
20 | 20 | IMG_MEM |
r17959 | r17960 | |
---|---|---|
1 | 1 | #ifndef __SPCHROMS_H |
2 | 2 | #define __SPCHROMS_H |
3 | 3 | |
4 | struct spchroms_interface | |
4 | struct spchroms_interface | |
5 | 5 | { |
6 | 6 | const char *memory_region; /* memory region where the speech ROM is. NULL means no speech ROM */ |
7 | 7 | }; |
r17959 | r17960 | |
---|---|---|
44 | 44 | |
45 | 45 | |
46 | 46 | /* finite machine state controling frames */ |
47 | enum mea8000_state | |
47 | enum mea8000_state | |
48 | 48 | { |
49 | 49 | MEA8000_STOPPED, /* nothing to do, timer disabled */ |
50 | 50 | MEA8000_WAIT_FIRST, /* received pitch, wait for first full trame, timer disabled */ |
r17959 | r17960 | |
55 | 55 | ALLOW_SAVE_TYPE( mea8000_state ); |
56 | 56 | |
57 | 57 | |
58 | struct filter_t | |
58 | struct filter_t | |
59 | 59 | { |
60 | 60 | #ifdef FLOAT_MODE |
61 | 61 | double fm, last_fm; /* frequency, in Hz */ |
r17959 | r17960 | |
70 | 70 | |
71 | 71 | |
72 | 72 | |
73 | struct mea8000_t | |
73 | struct mea8000_t | |
74 | 74 | { |
75 | 75 | |
76 | 76 | /* configuration parameters */ |
r17959 | r17960 | |
---|---|---|
240 | 240 | m_last_data = space(AS_0)->read_byte(offset); |
241 | 241 | |
242 | 242 | m_rom = rom; |
243 | ||
243 | ||
244 | 244 | return m_last_data; |
245 | 245 | } |
246 | 246 | |
r17959 | r17960 | |
252 | 252 | m_last_data = space(AS_0)->read_byte(offset); |
253 | 253 | |
254 | 254 | m_rom = rom; |
255 | ||
255 | ||
256 | 256 | return m_last_data; |
257 | 257 | } |
258 | 258 | |
r17959 | r17960 | |
550 | 550 | for (y = ybegin; y <= yend; y++) |
551 | 551 | { |
552 | 552 | code = read_ram(m_bitmapaddr + ch * 8 + y); |
553 | ||
553 | ||
554 | 554 | m_bitmap.pix32(y + yoff, 0 + xoff) = PALETTE[m_c16_bitmap[code >> 7]]; |
555 | 555 | m_bitmap.pix32(y + yoff, 1 + xoff) = PALETTE[m_c16_bitmap[(code >> 6) & 1]]; |
556 | 556 | m_bitmap.pix32(y + yoff, 2 + xoff) = PALETTE[m_c16_bitmap[(code >> 5) & 1]]; |
r17959 | r17960 | |
569 | 569 | for (y = ybegin; y <= yend; y++) |
570 | 570 | { |
571 | 571 | code = read_ram(m_bitmapaddr + ch * 8 + y); |
572 | ||
572 | ||
573 | 573 | m_bitmap.pix32(y + yoff, 0 + xoff) = |
574 | 574 | m_bitmap.pix32(y + yoff, 1 + xoff) = PALETTE[m_bitmapmulti[code >> 6]]; |
575 | 575 | m_bitmap.pix32(y + yoff, 2 + xoff) = |
r17959 | r17960 | |
589 | 589 | { |
590 | 590 | for (int x = 0; x < 8; x++) |
591 | 591 | { |
592 | m_bitmap.pix32(y + yoff, x + xoff) = PALETTE[color]; | |
592 | m_bitmap.pix32(y + yoff, x + xoff) = PALETTE[color]; | |
593 | 593 | } |
594 | 594 | } |
595 | 595 | } |
r17959 | r17960 | |
617 | 617 | { |
618 | 618 | for (int x = 0; x < m_bitmap.width(); x++) |
619 | 619 | { |
620 | m_bitmap.pix32(line, x) = PALETTE[0]; | |
620 | m_bitmap.pix32(line, x) = PALETTE[0]; | |
621 | 621 | } |
622 | 622 | } |
623 | 623 | return; |
r17959 | r17960 | |
637 | 637 | { |
638 | 638 | for (int x = 0; x < m_bitmap.width(); x++) |
639 | 639 | { |
640 | m_bitmap.pix32(line, x) = PALETTE[FRAMECOLOR]; | |
640 | m_bitmap.pix32(line, x) = PALETTE[FRAMECOLOR]; | |
641 | 641 | } |
642 | 642 | } |
643 | 643 | } |
r17959 | r17960 | |
733 | 733 | { |
734 | 734 | for (int x = 0; x < xbegin; x++) |
735 | 735 | { |
736 | m_bitmap.pix32(yoff + i, x) = PALETTE[FRAMECOLOR]; | |
736 | m_bitmap.pix32(yoff + i, x) = PALETTE[FRAMECOLOR]; | |
737 | 737 | } |
738 | 738 | |
739 | 739 | for (int x = xend; x < m_bitmap.width(); x++) |
r17959 | r17960 | |
752 | 752 | { |
753 | 753 | for (int x = 0; x < m_bitmap.width(); x++) |
754 | 754 | { |
755 | m_bitmap.pix32(line, x) = PALETTE[FRAMECOLOR]; | |
755 | m_bitmap.pix32(line, x) = PALETTE[FRAMECOLOR]; | |
756 | 756 | } |
757 | 757 | } |
758 | 758 | } |
r17959 | r17960 | |
---|---|---|
10 | 10 | #include "emu.h" |
11 | 11 | #include "socrates.h" |
12 | 12 | |
13 | struct SocratesASIC | |
13 | struct SocratesASIC | |
14 | 14 | { |
15 | 15 | sound_stream *stream; |
16 | 16 | UINT8 freq[2]; /* channel 1,2 frequencies */ |
r17959 | r17960 | |
---|---|---|
7 | 7 | #include "emu.h" |
8 | 8 | #include "includes/svision.h" |
9 | 9 | |
10 | enum SVISION_NOISE_Type | |
10 | enum SVISION_NOISE_Type | |
11 | 11 | { |
12 | 12 | SVISION_NOISE_Type7Bit, |
13 | 13 | SVISION_NOISE_Type14Bit |
14 | 14 | }; |
15 | 15 | |
16 | struct SVISION_NOISE | |
16 | struct SVISION_NOISE | |
17 | 17 | { |
18 | 18 | UINT8 reg[3]; |
19 | 19 | int on, right, left, play; |
r17959 | r17960 | |
25 | 25 | int value; // currently simple random function |
26 | 26 | }; |
27 | 27 | |
28 | struct SVISION_DMA | |
28 | struct SVISION_DMA | |
29 | 29 | { |
30 | 30 | UINT8 reg[5]; |
31 | 31 | int on, right, left; |
r17959 | r17960 | |
35 | 35 | int finished; |
36 | 36 | }; |
37 | 37 | |
38 | struct SVISION_CHANNEL | |
38 | struct SVISION_CHANNEL | |
39 | 39 | { |
40 | 40 | UINT8 reg[4]; |
41 | 41 | int on; |
r17959 | r17960 | |
---|---|---|
44 | 44 | FM_CONFPART1, // first half of configuration, awaiting second |
45 | 45 | FM_WRPROTPART1 // first half of protection program, awaiting second |
46 | 46 | }; |
47 | struct strata_t | |
47 | struct strata_t | |
48 | 48 | { |
49 | 49 | fm_mode_t mode; // current operation mode |
50 | 50 | int hard_unlock; // 1 if RP* pin is at Vhh (not fully implemented) |
r17959 | r17960 | |
229 | 229 | } |
230 | 230 | |
231 | 231 | /* bus width for 8/16-bit handlers */ |
232 | enum bus_width_t | |
232 | enum bus_width_t | |
233 | 233 | { |
234 | 234 | bw_8, |
235 | 235 | bw_16 |
r17959 | r17960 | |
---|---|---|
25 | 25 | WRITE8_MEMBER( vp620_device::kb_w ) |
26 | 26 | { |
27 | 27 | m_keydata = data; |
28 | ||
28 | ||
29 | 29 | m_slot->inst_w(0); |
30 | 30 | m_slot->inst_w(1); |
31 | ||
31 | ||
32 | 32 | m_keystb = ASSERT_LINE; |
33 | 33 | } |
34 | 34 |
r17959 | r17960 | |
---|---|---|
192 | 192 | |
193 | 193 | /* |
194 | 194 | |
195 | ||
195 | TODO: | |
196 | 196 | |
197 | ||
197 | - refactor into an actual daisy chain instead of this convenient hack | |
198 | 198 | |
199 | 199 | */ |
200 | 200 |
r17959 | r17960 | |
---|---|---|
57 | 57 | /******************* internal chip data structure ******************/ |
58 | 58 | |
59 | 59 | |
60 | struct mc6854_t | |
60 | struct mc6854_t | |
61 | 61 | { |
62 | 62 | devcb_resolved_write_line out_irq_func; |
63 | 63 | devcb_resolved_read_line in_rxd_func; |
r17959 | r17960 | |
---|---|---|
27 | 27 | #define MAX_SMARTMEDIA 1 |
28 | 28 | |
29 | 29 | /* machine-independent big-endian 32-bit integer */ |
30 | struct UINT32BE | |
30 | struct UINT32BE | |
31 | 31 | { |
32 | 32 | UINT8 bytes[4]; |
33 | 33 | }; |
r17959 | r17960 | |
48 | 48 | #endif |
49 | 49 | |
50 | 50 | /* SmartMedia image header */ |
51 | struct disk_image_header | |
51 | struct disk_image_header | |
52 | 52 | { |
53 | 53 | UINT8 version; |
54 | 54 | UINT32BE page_data_size; |
r17959 | r17960 | |
57 | 57 | UINT32BE log2_pages_per_block; |
58 | 58 | }; |
59 | 59 | |
60 | struct disk_image_format_2_header | |
60 | struct disk_image_format_2_header | |
61 | 61 | { |
62 | 62 | UINT8 data1[3]; |
63 | 63 | UINT8 padding1[256-3]; |
r17959 | r17960 | |
---|---|---|
28 | 28 | /******************* internal chip data structure ******************/ |
29 | 29 | |
30 | 30 | |
31 | struct mc6846_t | |
31 | struct mc6846_t | |
32 | 32 | { |
33 | 33 | |
34 | 34 | const mc6846_interface* iface; |
r17959 | r17960 | |
---|---|---|
13 | 13 | |
14 | 14 | #define KEYBOARD_BUFFER_SIZE 256 |
15 | 15 | |
16 | struct amigakbd_t | |
16 | struct amigakbd_t | |
17 | 17 | { |
18 | 18 | UINT8 *buf; |
19 | 19 | int buf_pos; |
r17959 | r17960 | |
---|---|---|
25 | 25 | // ======================> diag264_user_port_loopback_device |
26 | 26 | |
27 | 27 | class diag264_user_port_loopback_device : public device_t, |
28 | | |
28 | | |
29 | 29 | { |
30 | 30 | public: |
31 | 31 | // construction/destruction |
r17959 | r17960 | |
---|---|---|
47 | 47 | #define ATTR_SUBSCRIPT BIT(attr, 6) |
48 | 48 | #define ATTR_SUPERSCRIPT BIT(attr, 7) |
49 | 49 | |
50 | static const rgb_t PALETTE[] = | |
50 | static const rgb_t PALETTE[] = | |
51 | 51 | { |
52 | 52 | RGB_BLACK, |
53 | 53 | MAKE_RGB(0x00, 0x80, 0x00), |
r17959 | r17960 | |
---|---|---|
36 | 36 | |
37 | 37 | #define MAX_TAPE_UNIT 4 |
38 | 38 | |
39 | struct tape_unit_t | |
39 | struct tape_unit_t | |
40 | 40 | { |
41 | 41 | device_image_interface *img; /* image descriptor */ |
42 | 42 | unsigned int bot : 1; /* TRUE if we are at the beginning of tape */ |
r17959 | r17960 | |
---|---|---|
497 | 497 | m_dsp.dma_throttled = false; |
498 | 498 | drq_w(1); |
499 | 499 | m_dsp.flags = ADPCM3; |
500 | break; | |
500 | break; | |
501 | 501 | case 0xda: // stop 8-bit autoinit |
502 | 502 | m_dsp.dma_autoinit = 0; |
503 | 503 | break; |
r17959 | r17960 | |
911 | 911 | m_dsp.fifo_r_ptr = 0; |
912 | 912 | m_dsp.wbuf_status = 0; |
913 | 913 | m_dsp.rbuf_status = 0; |
914 | m_dsp.frequency = 8000; // per stereo-fx | |
914 | m_dsp.frequency = 8000; // per stereo-fx | |
915 | 915 | m_dsp.irq_active = 0; |
916 | 916 | m_mixer_index = 0; |
917 | 917 | m_dsp.dma_no_irq = false; |
r17959 | r17960 | |
919 | 919 | |
920 | 920 | UINT8 sb_device::dack_r(int line) |
921 | 921 | { |
922 | ||
922 | ||
923 | 923 | if(m_dsp.adc_transferred >= m_dsp.adc_length) |
924 | 924 | { |
925 | 925 | drq_w(0); |
r17959 | r17960 | |
1057 | 1057 | case 0: // 8-bit unsigned mono |
1058 | 1058 | m_dacl->write_unsigned8(m_dsp.data[m_dsp.d_rptr]); |
1059 | 1059 | m_dacr->write_unsigned8(m_dsp.data[m_dsp.d_rptr]); |
1060 | ||
1060 | ||
1061 | 1061 | break; |
1062 | 1062 | case SIGNED: // 8-bit signed mono |
1063 | 1063 | m_dacl->write_unsigned8(m_dsp.data[m_dsp.d_rptr] + 128); |
1064 | 1064 | m_dacr->write_unsigned8(m_dsp.data[m_dsp.d_rptr] + 128); |
1065 | ||
1065 | ||
1066 | 1066 | break; |
1067 | 1067 | case STEREO: // 8-bit unsigned stereo |
1068 | 1068 | m_dacl->write_unsigned8(m_dsp.data[m_dsp.d_rptr]); |
r17959 | r17960 | |
1078 | 1078 | break; |
1079 | 1079 | case SIXTEENBIT: // 16-bit unsigned mono |
1080 | 1080 | lsample = m_dsp.data[m_dsp.d_rptr] | (m_dsp.data[m_dsp.d_rptr+1] << 8); |
1081 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1082 | m_dsp.data[m_dsp.d_rptr++] = 0x80; | |
1081 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1082 | m_dsp.data[m_dsp.d_rptr++] = 0x80; | |
1083 | 1083 | m_dacl->write_unsigned16(lsample); |
1084 | 1084 | m_dacr->write_unsigned16(lsample); |
1085 | 1085 | break; |
1086 | 1086 | case SIXTEENBIT | SIGNED: // 16-bit signed mono |
1087 | 1087 | lsample = m_dsp.data[m_dsp.d_rptr] | (m_dsp.data[m_dsp.d_rptr+1] << 8); |
1088 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1089 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1088 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1089 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1090 | 1090 | m_dacl->write_unsigned16(lsample + 32768); |
1091 | 1091 | m_dacr->write_unsigned16(lsample + 32768); |
1092 | 1092 | break; |
1093 | 1093 | case SIXTEENBIT | STEREO: // 16-bit unsigned stereo |
1094 | 1094 | lsample = m_dsp.data[m_dsp.d_rptr] | (m_dsp.data[m_dsp.d_rptr+1] << 8); |
1095 | 1095 | m_dsp.data[m_dsp.d_rptr++] = 0x00; |
1096 | ||
1096 | ||
1097 | 1097 | m_dsp.d_rptr %= 128; |
1098 | 1098 | rsample = m_dsp.data[m_dsp.d_rptr] | (m_dsp.data[m_dsp.d_rptr+1] << 8); |
1099 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1100 | m_dsp.data[m_dsp.d_rptr++] = 0x80; | |
1099 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1100 | m_dsp.data[m_dsp.d_rptr++] = 0x80; | |
1101 | 1101 | m_dacl->write_unsigned16(lsample); |
1102 | 1102 | m_dacr->write_unsigned16(rsample); |
1103 | 1103 | break; |
1104 | case SIXTEENBIT | SIGNED | STEREO: // 16-bit signed stereo | |
1104 | case SIXTEENBIT | SIGNED | STEREO: // 16-bit signed stereo | |
1105 | 1105 | lsample = m_dsp.data[m_dsp.d_rptr] | (m_dsp.data[m_dsp.d_rptr+1] << 8); |
1106 | 1106 | m_dsp.data[m_dsp.d_rptr++] = 0x00; |
1107 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1108 | m_dsp.d_rptr %= 128; | |
1107 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1108 | m_dsp.d_rptr %= 128; | |
1109 | 1109 | rsample = m_dsp.data[m_dsp.d_rptr] | (m_dsp.data[m_dsp.d_rptr+1] << 8); |
1110 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1111 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1110 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1111 | m_dsp.data[m_dsp.d_rptr++] = 0x00; | |
1112 | 1112 | m_dacl->write_unsigned16(lsample + 32768); |
1113 | 1113 | m_dacr->write_unsigned16(rsample + 32768); |
1114 | 1114 | break; |
r17959 | r17960 | |
1148 | 1148 | m_dacl->write_unsigned8(m_dsp.adpcm_ref); |
1149 | 1149 | m_dacr->write_unsigned8(m_dsp.adpcm_ref); |
1150 | 1150 | break; |
1151 | } | |
1151 | } | |
1152 | 1152 | lsample = m_dsp.data[m_dsp.d_rptr]; |
1153 | 1153 | switch(m_dsp.adpcm_count++) |
1154 | 1154 | { |
r17959 | r17960 | |
1173 | 1173 | m_dacl->write_unsigned8(m_dsp.adpcm_ref); |
1174 | 1174 | m_dacr->write_unsigned8(m_dsp.adpcm_ref); |
1175 | 1175 | break; |
1176 | } | |
1176 | } | |
1177 | 1177 | lsample = m_dsp.data[m_dsp.d_rptr]; |
1178 | 1178 | switch(m_dsp.adpcm_count++) |
1179 | 1179 | { |
r17959 | r17960 | |
---|---|---|
15 | 15 | TYPE DEFINITIONS |
16 | 16 | ***************************************************************************/ |
17 | 17 | |
18 | enum ds1315_mode_t | |
18 | enum ds1315_mode_t | |
19 | 19 | { |
20 | 20 | DS_SEEK_MATCHING, |
21 | 21 | DS_CALENDAR_IO |
r17959 | r17960 | |
---|---|---|
373 | 373 | TYPE DEFINITIONS |
374 | 374 | *******************************************************************************/ |
375 | 375 | |
376 | struct s3c44b0_memcon_regs_t | |
376 | struct s3c44b0_memcon_regs_t | |
377 | 377 | { |
378 | 378 | UINT32 data[0x34/4]; |
379 | 379 | }; |
380 | 380 | |
381 | struct s3c44b0_irq_regs_t | |
381 | struct s3c44b0_irq_regs_t | |
382 | 382 | { |
383 | 383 | UINT32 intcon; |
384 | 384 | UINT32 intpnd; |
r17959 | r17960 | |
395 | 395 | UINT32 f_ispc; |
396 | 396 | }; |
397 | 397 | |
398 | struct s3c44b0_dma_regs_t | |
398 | struct s3c44b0_dma_regs_t | |
399 | 399 | { |
400 | 400 | UINT32 dcon; |
401 | 401 | UINT32 disrc; |
r17959 | r17960 | |
406 | 406 | UINT32 dccnt; |
407 | 407 | }; |
408 | 408 | |
409 | struct s3c44b0_clkpow_regs_t | |
409 | struct s3c44b0_clkpow_regs_t | |
410 | 410 | { |
411 | 411 | UINT32 pllcon; |
412 | 412 | UINT32 clkcon; |
r17959 | r17960 | |
414 | 414 | UINT32 locktime; |
415 | 415 | }; |
416 | 416 | |
417 | struct s3c44b0_lcd_regs_t | |
417 | struct s3c44b0_lcd_regs_t | |
418 | 418 | { |
419 | 419 | UINT32 lcdcon1; |
420 | 420 | UINT32 lcdcon2; |
r17959 | r17960 | |
429 | 429 | UINT32 dithmode; |
430 | 430 | }; |
431 | 431 | |
432 | struct s3c44b0_uart_regs_t | |
432 | struct s3c44b0_uart_regs_t | |
433 | 433 | { |
434 | 434 | UINT32 ulcon; |
435 | 435 | UINT32 ucon; |
r17959 | r17960 | |
444 | 444 | UINT32 ubrdiv; |
445 | 445 | }; |
446 | 446 | |
447 | struct s3c44b0_sio_regs_t | |
447 | struct s3c44b0_sio_regs_t | |
448 | 448 | { |
449 | 449 | UINT32 siocon; |
450 | 450 | UINT32 siodat; |
r17959 | r17960 | |
453 | 453 | UINT32 dcntz; |
454 | 454 | }; |
455 | 455 | |
456 | struct s3c44b0_pwm_regs_t | |
456 | struct s3c44b0_pwm_regs_t | |
457 | 457 | { |
458 | 458 | UINT32 tcfg0; |
459 | 459 | UINT32 tcfg1; |
r17959 | r17960 | |
477 | 477 | UINT32 tcnto5; |
478 | 478 | }; |
479 | 479 | |
480 | struct s3c44b0_wdt_regs_t | |
480 | struct s3c44b0_wdt_regs_t | |
481 | 481 | { |
482 | 482 | UINT32 wtcon; |
483 | 483 | UINT32 wtdat; |
484 | 484 | UINT32 wtcnt; |
485 | 485 | }; |
486 | 486 | |
487 | struct s3c44b0_iic_regs_t | |
487 | struct s3c44b0_iic_regs_t | |
488 | 488 | { |
489 | 489 | UINT32 iiccon; |
490 | 490 | UINT32 iicstat; |
r17959 | r17960 | |
492 | 492 | UINT32 iicds; |
493 | 493 | }; |
494 | 494 | |
495 | struct s3c44b0_iis_regs_t | |
495 | struct s3c44b0_iis_regs_t | |
496 | 496 | { |
497 | 497 | UINT32 iiscon; |
498 | 498 | UINT32 iismod; |
r17959 | r17960 | |
501 | 501 | UINT32 iisfifo; |
502 | 502 | }; |
503 | 503 | |
504 | struct s3c44b0_gpio_regs_t | |
504 | struct s3c44b0_gpio_regs_t | |
505 | 505 | { |
506 | 506 | UINT32 gpacon; |
507 | 507 | UINT32 gpadat; |
r17959 | r17960 | |
527 | 527 | UINT32 extintpnd; |
528 | 528 | }; |
529 | 529 | |
530 | struct s3c44b0_rtc_regs_t | |
530 | struct s3c44b0_rtc_regs_t | |
531 | 531 | { |
532 | 532 | UINT32 rtccon; |
533 | 533 | UINT32 reserved[3]; |
r17959 | r17960 | |
549 | 549 | UINT32 ticnt; |
550 | 550 | }; |
551 | 551 | |
552 | struct s3c44b0_adc_regs_t | |
552 | struct s3c44b0_adc_regs_t | |
553 | 553 | { |
554 | 554 | UINT32 adccon; |
555 | 555 | UINT32 adcpsr; |
556 | 556 | UINT32 adcdat; |
557 | 557 | }; |
558 | 558 | |
559 | struct s3c44b0_cpuwrap_regs_t | |
559 | struct s3c44b0_cpuwrap_regs_t | |
560 | 560 | { |
561 | 561 | UINT32 syscfg; |
562 | 562 | UINT32 ncachbe0; |
563 | 563 | UINT32 ncachbe1; |
564 | 564 | }; |
565 | 565 | |
566 | struct s3c44b0_memcon_t | |
566 | struct s3c44b0_memcon_t | |
567 | 567 | { |
568 | 568 | s3c44b0_memcon_regs_t regs; |
569 | 569 | }; |
570 | 570 | |
571 | struct s3c44b0_irq_t | |
571 | struct s3c44b0_irq_t | |
572 | 572 | { |
573 | 573 | s3c44b0_irq_regs_t regs; |
574 | 574 | int line_irq, line_fiq; |
575 | 575 | }; |
576 | 576 | |
577 | struct s3c44b0_dma_t | |
577 | struct s3c44b0_dma_t | |
578 | 578 | { |
579 | 579 | s3c44b0_dma_regs_t regs; |
580 | 580 | emu_timer *timer; |
581 | 581 | }; |
582 | 582 | |
583 | struct s3c44b0_clkpow_t | |
583 | struct s3c44b0_clkpow_t | |
584 | 584 | { |
585 | 585 | s3c44b0_clkpow_regs_t regs; |
586 | 586 | }; |
587 | 587 | |
588 | struct rectangle_t | |
588 | struct rectangle_t | |
589 | 589 | { |
590 | 590 | int x1, y1, x2, y2; |
591 | 591 | }; |
592 | 592 | |
593 | struct s3c44b0_lcd_t | |
593 | struct s3c44b0_lcd_t | |
594 | 594 | { |
595 | 595 | s3c44b0_lcd_regs_t regs; |
596 | 596 | emu_timer *timer; |
r17959 | r17960 | |
609 | 609 | attoseconds_t frame_period, pixeltime, scantime; |
610 | 610 | }; |
611 | 611 | |
612 | struct s3c44b0_uart_t | |
612 | struct s3c44b0_uart_t | |
613 | 613 | { |
614 | 614 | s3c44b0_uart_regs_t regs; |
615 | 615 | emu_timer *timer; |
616 | 616 | }; |
617 | 617 | |
618 | struct s3c44b0_sio_t | |
618 | struct s3c44b0_sio_t | |
619 | 619 | { |
620 | 620 | s3c44b0_sio_regs_t regs; |
621 | 621 | emu_timer *timer; |
622 | 622 | }; |
623 | 623 | |
624 | struct s3c44b0_pwm_t | |
624 | struct s3c44b0_pwm_t | |
625 | 625 | { |
626 | 626 | s3c44b0_pwm_regs_t regs; |
627 | 627 | emu_timer *timer[6]; |
r17959 | r17960 | |
630 | 630 | UINT32 freq[6]; |
631 | 631 | }; |
632 | 632 | |
633 | struct s3c44b0_wdt_t | |
633 | struct s3c44b0_wdt_t | |
634 | 634 | { |
635 | 635 | s3c44b0_wdt_regs_t regs; |
636 | 636 | emu_timer *timer; |
637 | 637 | }; |
638 | 638 | |
639 | struct s3c44b0_iic_t | |
639 | struct s3c44b0_iic_t | |
640 | 640 | { |
641 | 641 | s3c44b0_iic_regs_t regs; |
642 | 642 | emu_timer *timer; |
643 | 643 | int count; |
644 | 644 | }; |
645 | 645 | |
646 | struct s3c44b0_iis_t | |
646 | struct s3c44b0_iis_t | |
647 | 647 | { |
648 | 648 | s3c44b0_iis_regs_t regs; |
649 | 649 | emu_timer *timer; |
r17959 | r17960 | |
651 | 651 | int fifo_index; |
652 | 652 | }; |
653 | 653 | |
654 | struct s3c44b0_gpio_t | |
654 | struct s3c44b0_gpio_t | |
655 | 655 | { |
656 | 656 | s3c44b0_gpio_regs_t regs; |
657 | 657 | }; |
658 | 658 | |
659 | struct s3c44b0_rtc_t | |
659 | struct s3c44b0_rtc_t | |
660 | 660 | { |
661 | 661 | s3c44b0_rtc_regs_t regs; |
662 | 662 | emu_timer *timer_tick_count; |
663 | 663 | emu_timer *timer_update; |
664 | 664 | }; |
665 | 665 | |
666 | struct s3c44b0_adc_t | |
666 | struct s3c44b0_adc_t | |
667 | 667 | { |
668 | 668 | s3c44b0_adc_regs_t regs; |
669 | 669 | emu_timer *timer; |
670 | 670 | }; |
671 | 671 | |
672 | struct s3c44b0_cpuwrap_t | |
672 | struct s3c44b0_cpuwrap_t | |
673 | 673 | { |
674 | 674 | s3c44b0_cpuwrap_regs_t regs; |
675 | 675 | }; |
676 | 676 | |
677 | struct s3c44b0_t | |
677 | struct s3c44b0_t | |
678 | 678 | { |
679 | 679 | const s3c44b0_interface *iface; |
680 | 680 | address_space* space; |
r17959 | r17960 | |
---|---|---|
10 | 10 | #ifndef __MC68328_PRIVATE_H_ |
11 | 11 | #define __MC68328_PRIVATE_H_ |
12 | 12 | |
13 | struct mc68328_regs_t | |
13 | struct mc68328_regs_t | |
14 | 14 | { |
15 | 15 | // $(FF)FFF000 |
16 | 16 | UINT8 scr; // System Control Register |
r17959 | r17960 | |
203 | 203 | UINT8 unused42[1260]; |
204 | 204 | }; |
205 | 205 | |
206 | struct mc68328_t | |
206 | struct mc68328_t | |
207 | 207 | { |
208 | 208 | const mc68328_interface* iface; |
209 | 209 |
r17959 | r17960 | |
---|---|---|
45 | 45 | //------------------------------------------------- |
46 | 46 | // MACHINE_CONFIG_FRAGMENT( c64_ide64 ) |
47 | 47 | //------------------------------------------------- |
48 | static const ide_config ide_intf = | |
48 | static const ide_config ide_intf = | |
49 | 49 | { |
50 | NULL, | |
51 | NULL, | |
50 | NULL, | |
51 | NULL, | |
52 | 52 | 0 |
53 | 53 | }; |
54 | 54 |
r17959 | r17960 | |
---|---|---|
24 | 24 | } |
25 | 25 | } |
26 | 26 | |
27 | struct MC_t | |
27 | struct MC_t | |
28 | 28 | { |
29 | 29 | emu_timer *tUpdateTimer; |
30 | 30 | UINT32 nCPUControl0; |
r17959 | r17960 | |
---|---|---|
66 | 66 | /* |
67 | 67 | * Input pins |
68 | 68 | */ |
69 | enum kr2376_input_pin_t | |
69 | enum kr2376_input_pin_t | |
70 | 70 | { |
71 | 71 | KR2376_DSII=20, /* DSII - Pin 20 - Data & Strobe Invert Input */ |
72 | 72 | KR2376_PII=6 /* PII - Pin 6 - Parity Invert Input */ |
73 | 73 | }; |
74 | 74 | |
75 | enum kr2376_output_pin_t | |
75 | enum kr2376_output_pin_t | |
76 | 76 | { |
77 | 77 | KR2376_SO=16, /* SO - Pin 16 - Strobe Output */ |
78 | 78 | KR2376_PO=7 /* PO - Pin 7 - Parity Output */ |
r17959 | r17960 | |
---|---|---|
58 | 58 | #define IWM_Q6 0x40 |
59 | 59 | #define IWM_Q7 0x80 |
60 | 60 | |
61 | enum applefdc_t | |
61 | enum applefdc_t | |
62 | 62 | { |
63 | 63 | APPLEFDC_APPLE2, /* classic Apple II disk controller (pre-IWM) */ |
64 | 64 | APPLEFDC_IWM, /* Integrated Woz Machine */ |
r17959 | r17960 | |
---|---|---|
30 | 30 | #include "machine/upd765.h" |
31 | 31 | |
32 | 32 | |
33 | enum UPD765_PHASE | |
33 | enum UPD765_PHASE | |
34 | 34 | { |
35 | 35 | UPD765_COMMAND_PHASE_FIRST_BYTE, |
36 | 36 | UPD765_COMMAND_PHASE_BYTES, |
r17959 | r17960 | |
40 | 40 | }; |
41 | 41 | |
42 | 42 | /* supported versions */ |
43 | enum UPD765_VERSION | |
43 | enum UPD765_VERSION | |
44 | 44 | { |
45 | 45 | TYPE_UPD765A = 0, |
46 | 46 | TYPE_UPD765B = 1, |
r17959 | r17960 | |
---|---|---|
40 | 40 | } |
41 | 41 | } |
42 | 42 | |
43 | static const ide_config ide_intf = | |
43 | static const ide_config ide_intf = | |
44 | 44 | { |
45 | ide_interrupt, | |
46 | NULL, | |
45 | ide_interrupt, | |
46 | NULL, | |
47 | 47 | 0 |
48 | 48 | }; |
49 | 49 |
r17959 | r17960 | |
---|---|---|
78 | 78 | ***************************************************************************/ |
79 | 79 | |
80 | 80 | /* RDY pin connected state */ |
81 | enum UPD765_RDY_PIN | |
81 | enum UPD765_RDY_PIN | |
82 | 82 | { |
83 | 83 | UPD765_RDY_PIN_NOT_CONNECTED = 0, |
84 | 84 | UPD765_RDY_PIN_CONNECTED = 1 |
r17959 | r17960 | |
91 | 91 | #define UPD765_GET_IMAGE(name) device_t *name(device_t *device, int floppy_index ) |
92 | 92 | |
93 | 93 | |
94 | struct upd765_interface | |
94 | struct upd765_interface | |
95 | 95 | { |
96 | 96 | /* interrupt issued */ |
97 | 97 | devcb_write_line out_int_func; |
r17959 | r17960 | |
---|---|---|
36 | 36 | TYPE DEFINITIONS |
37 | 37 | ***************************************************************************/ |
38 | 38 | |
39 | struct AT45DBXX_PINS | |
39 | struct AT45DBXX_PINS | |
40 | 40 | { |
41 | 41 | int cs; // chip select |
42 | 42 | int sck; // serial clock |
r17959 | r17960 | |
47 | 47 | int busy; // busy |
48 | 48 | }; |
49 | 49 | |
50 | struct AT45DBXX_CMD | |
50 | struct AT45DBXX_CMD | |
51 | 51 | { |
52 | 52 | UINT8 data[8], size; |
53 | 53 | }; |
54 | 54 | |
55 | struct AT45DBXX_IO | |
55 | struct AT45DBXX_IO | |
56 | 56 | { |
57 | 57 | UINT8 *data; |
58 | 58 | UINT32 size, pos; |
r17959 | r17960 | |
---|---|---|
13 | 13 | |
14 | 14 | #include "ti99defs.h" |
15 | 15 | |
16 | struct ti99grom_config | |
16 | struct ti99grom_config | |
17 | 17 | { |
18 | 18 | bool writable; |
19 | 19 | int ident; |
r17959 | r17960 | |
---|---|---|
22 | 22 | |
23 | 23 | extern const device_type JOYPORT; |
24 | 24 | |
25 | struct joyport_config | |
25 | struct joyport_config | |
26 | 26 | { |
27 | 27 | devcb_write_line interrupt; |
28 | 28 | int vdp_clock; |
r17959 | r17960 | |
---|---|---|
25 | 25 | Needed to adapt to higher cylinder numbers. Floppies do not have such |
26 | 26 | high numbers. |
27 | 27 | */ |
28 | struct chrn_id_hd | |
28 | struct chrn_id_hd | |
29 | 29 | { |
30 | 30 | UINT16 C; |
31 | 31 | UINT8 H; |
r17959 | r17960 | |
---|---|---|
18 | 18 | #define GROMPORT_CONFIG(name) \ |
19 | 19 | const gromport_config(name) = |
20 | 20 | |
21 | struct gromport_config | |
21 | struct gromport_config | |
22 | 22 | { |
23 | 23 | devcb_write_line ready; |
24 | 24 | devcb_write_line reset; |
r17959 | r17960 | |
366 | 366 | }; |
367 | 367 | |
368 | 368 | |
369 | struct pcb_type | |
369 | struct pcb_type | |
370 | 370 | { |
371 | 371 | int id; |
372 | 372 | const char* name; |
r17959 | r17960 | |
---|---|---|
44 | 44 | |
45 | 45 | /*****************************************************************************/ |
46 | 46 | |
47 | struct geneve_keyboard_config | |
47 | struct geneve_keyboard_config | |
48 | 48 | { |
49 | 49 | devcb_write_line interrupt; |
50 | 50 | }; |
r17959 | r17960 | |
110 | 110 | |
111 | 111 | /*****************************************************************************/ |
112 | 112 | |
113 | struct geneve_mapper_config | |
113 | struct geneve_mapper_config | |
114 | 114 | { |
115 | 115 | devcb_write_line ready; |
116 | 116 | }; |
r17959 | r17960 | |
---|---|---|
334 | 334 | DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, nouspikel_ide_interface_device, clock_interrupt_callback) |
335 | 335 | }; |
336 | 336 | |
337 | static const ide_config ide_intf = | |
337 | static const ide_config ide_intf = | |
338 | 338 | { |
339 | ide_interrupt_callback, | |
340 | NULL, | |
339 | ide_interrupt_callback, | |
340 | NULL, | |
341 | 341 | 0 |
342 | 342 | }; |
343 | 343 |
r17959 | r17960 | |
---|---|---|
77 | 77 | extern const device_type TISOUND_94624; |
78 | 78 | extern const device_type TISOUND_76496; |
79 | 79 | |
80 | struct ti_sound_config | |
80 | struct ti_sound_config | |
81 | 81 | { |
82 | 82 | devcb_write_line ready; |
83 | 83 | }; |
r17959 | r17960 | |
---|---|---|
21 | 21 | #define SPEECH8_CONFIG(name) \ |
22 | 22 | const speech8_config(name) = |
23 | 23 | |
24 | struct speech8_config | |
24 | struct speech8_config | |
25 | 25 | { |
26 | 26 | devcb_write_line ready; |
27 | 27 | }; |
r17959 | r17960 | |
---|---|---|
23 | 23 | if the HGSPL expansion card is used, the GROMs in the console must be |
24 | 24 | removed. |
25 | 25 | */ |
26 | struct dmux_device_list_entry | |
26 | struct dmux_device_list_entry | |
27 | 27 | { |
28 | 28 | const char *name; // Name of the device (used for looking up the device) |
29 | 29 | UINT16 select; // State of the address line bits when addressing this device |
r17959 | r17960 | |
37 | 37 | #define DMUX_CONFIG(name) \ |
38 | 38 | const datamux_config(name) = |
39 | 39 | |
40 | struct datamux_config | |
40 | struct datamux_config | |
41 | 41 | { |
42 | 42 | devcb_write_line ready; |
43 | 43 | const dmux_device_list_entry *devlist; |
r17959 | r17960 | |
---|---|---|
23 | 23 | |
24 | 24 | #define DSRROM "dsrrom" |
25 | 25 | |
26 | struct peribox_config | |
26 | struct peribox_config | |
27 | 27 | { |
28 | 28 | devcb_write_line inta; |
29 | 29 | devcb_write_line intb; |
r17959 | r17960 | |
---|---|---|
36 | 36 | #define SRAM_SIZE 2048 |
37 | 37 | #define DRAM_SIZE 65536 |
38 | 38 | |
39 | struct mapper8_list_entry | |
39 | struct mapper8_list_entry | |
40 | 40 | { |
41 | 41 | const char* name; // Name of the device (used for looking up the device) |
42 | 42 | int mode; // Mode of the system which applies to this entry |
r17959 | r17960 | |
49 | 49 | #define MAPPER8_CONFIG(name) \ |
50 | 50 | const mapper8_config(name) = |
51 | 51 | |
52 | struct mapper8_config | |
52 | struct mapper8_config | |
53 | 53 | { |
54 | 54 | devcb_write_line ready; |
55 | 55 | const mapper8_list_entry *devlist; |
r17959 | r17960 | |
---|---|---|
31 | 31 | #define CFFA2_ROM_REGION "cffa2_rom" |
32 | 32 | #define CFFA2_IDE_TAG "cffa2_ide" |
33 | 33 | |
34 | static const ide_config ide_intf = | |
34 | static const ide_config ide_intf = | |
35 | 35 | { |
36 | NULL, | |
37 | NULL, | |
36 | NULL, | |
37 | NULL, | |
38 | 38 | 0 |
39 | 39 | }; |
40 | 40 |
r17959 | r17960 | |
---|---|---|
40 | 40 | /* We can use MAME's harddisk.c image format instead. */ |
41 | 41 | |
42 | 42 | /* machine-independent big-endian 32-bit integer */ |
43 | struct UINT32BE | |
43 | struct UINT32BE | |
44 | 44 | { |
45 | 45 | UINT8 bytes[4]; |
46 | 46 | }; |
r17959 | r17960 | |
61 | 61 | #endif |
62 | 62 | |
63 | 63 | /* disk image header */ |
64 | struct disk_image_header | |
64 | struct disk_image_header | |
65 | 65 | { |
66 | 66 | UINT32BE cylinders; /* number of cylinders on hard disk (big-endian) */ |
67 | 67 | UINT32BE heads; /* number of heads on hard disk (big-endian) */ |
r17959 | r17960 | |
81 | 81 | }; |
82 | 82 | |
83 | 83 | /* disk drive unit descriptor */ |
84 | struct hd_unit_t | |
84 | struct hd_unit_t | |
85 | 85 | { |
86 | 86 | device_image_interface *img; /* image descriptor */ |
87 | 87 | format_t format; |
r17959 | r17960 | |
94 | 94 | }; |
95 | 95 | |
96 | 96 | /* disk controller */ |
97 | struct hdc_t | |
97 | struct hdc_t | |
98 | 98 | { |
99 | 99 | UINT16 w[8]; |
100 | 100 |
r17959 | r17960 | |
---|---|---|
681 | 681 | |
682 | 682 | |
683 | 683 | |
684 | enum to7_io_dev | |
684 | enum to7_io_dev | |
685 | 685 | { |
686 | 686 | TO7_IO_NONE, |
687 | 687 | TO7_IO_CENTRONICS, |
r17959 | r17960 | |
---|---|---|
56 | 56 | } |
57 | 57 | |
58 | 58 | /* port 0x20 - in ROM (usually) stored in RAM 0x22 |
59 | * bit0 - | |
59 | * bit0 - | |
60 | 60 | * bit1 - |
61 | 61 | * bit2 - |
62 | 62 | * bit3 - |
r17959 | r17960 | |
---|---|---|
64 | 64 | * - "Keypad ," is not mapped |
65 | 65 | */ |
66 | 66 | |
67 | struct kay_kbd_t | |
67 | struct kay_kbd_t | |
68 | 68 | { |
69 | 69 | device_t *beeper; |
70 | 70 | UINT8 buff[16]; |
r17959 | r17960 | |
---|---|---|
13 | 13 | |
14 | 14 | // ======================> coco_rtc_type_t |
15 | 15 | |
16 | enum coco_rtc_type_t | |
16 | enum coco_rtc_type_t | |
17 | 17 | { |
18 | 18 | RTC_DISTO = 0x00, |
19 | 19 | RTC_CLOUD9 = 0x01, |
r17959 | r17960 | |
---|---|---|
139 | 139 | |
140 | 140 | value &= cbm_common_cia0_port_b_r(m_cia1, cia0porta); |
141 | 141 | /* |
142 | if (!intf->k0_r()) | |
143 | value &= m_keyline[0]; | |
144 | if (!intf->k1_r()) | |
145 | value &= m_keyline[1]; | |
146 | if (!intf->k2_r()) | |
147 | value &= m_keyline[2]; | |
142 | if (!intf->k0_r()) | |
143 | value &= m_keyline[0]; | |
144 | if (!intf->k1_r()) | |
145 | value &= m_keyline[1]; | |
146 | if (!intf->k2_r()) | |
147 | value &= m_keyline[2]; | |
148 | 148 | */ |
149 | 149 | return value; |
150 | 150 | } |
r17959 | r17960 | |
---|---|---|
24 | 24 | CR = 0, |
25 | 25 | PCRA, LCRA = PCRA, |
26 | 26 | PCRB, LCRB = PCRB, |
27 | PCRC, LCRC = PCRC, | |
27 | PCRC, LCRC = PCRC, | |
28 | 28 | PCRD, LCRD = PCRD, |
29 | 29 | MCR, |
30 | 30 | RCR, |
r17959 | r17960 | |
69 | 69 | |
70 | 70 | // RAM configuration register |
71 | 71 | static const offs_t RCR_BOTTOM_ADDRESS[4] = { 0x0400, 0x1000, 0x0400, 0x1000 }; |
72 | static const offs_t RCR_TOP_ADDRESS[4] = | |
72 | static const offs_t RCR_TOP_ADDRESS[4] = | |
73 | 73 | |
74 | 74 | enum |
75 | 75 | { |
r17959 | r17960 | |
337 | 337 | *cas1 = P1H_A16 ? 0 : 1; |
338 | 338 | } |
339 | 339 | } |
340 | ||
340 | ||
341 | 341 | if ((RCR_BOTTOM && offset < RCR_BOTTOM_ADDRESS[RCR_SHARE]) || |
342 | 342 | (RCR_TOP && offset >= RCR_TOP_ADDRESS[RCR_SHARE])) |
343 | 343 | { |
r17959 | r17960 | |
---|---|---|
810 | 810 | WRITE8_MEMBER( c1541_prologic_dos_classic_device::pia_pa_w ) |
811 | 811 | { |
812 | 812 | /* |
813 | ||
813 | ||
814 | 814 | bit description |
815 | ||
815 | ||
816 | 816 | 0 1/2 MHz |
817 | 1 | |
818 | 2 | |
817 | 1 | |
818 | 2 | |
819 | 819 | 3 35/40 tracks |
820 | 4 | |
821 | 5 | |
822 | 6 | |
820 | 4 | |
821 | 5 | |
822 | 6 | |
823 | 823 | 7 Hi |
824 | ||
824 | ||
825 | 825 | */ |
826 | 826 | } |
827 | 827 |
r17959 | r17960 | |
---|---|---|
24 | 24 | ACTION_REPLAY_MKIII |
25 | 25 | }; |
26 | 26 | |
27 | struct amigacrt_t | |
27 | struct amigacrt_t | |
28 | 28 | { |
29 | 29 | int cart_type; |
30 | 30 | int ar1_spurious; |
r17959 | r17960 | |
---|---|---|
122 | 122 | MCFG_LEGACY_FLOPPY_4_DRIVES_ADD(kc_d004_floppy_interface) |
123 | 123 | MACHINE_CONFIG_END |
124 | 124 | |
125 | static const ide_config ide_intf = | |
125 | static const ide_config ide_intf = | |
126 | 126 | { |
127 | NULL, | |
128 | NULL, | |
127 | NULL, | |
128 | NULL, | |
129 | 129 | 0 |
130 | 130 | }; |
131 | 131 |
r17959 | r17960 | |
---|---|---|
25 | 25 | // ======================> diag264_serial_loopback_device |
26 | 26 | |
27 | 27 | class diag264_serial_loopback_device : public device_t, |
28 | | |
28 | | |
29 | 29 | { |
30 | 30 | public: |
31 | 31 | // construction/destruction |
r17959 | r17960 | |
---|---|---|
65 | 65 | class device_pet_datassette_port_interface; |
66 | 66 | |
67 | 67 | class pet_datassette_port_device : public device_t, |
68 | public pet_datassette_port_interface, | |
69 | public device_slot_interface | |
68 | public pet_datassette_port_interface, | |
69 | public device_slot_interface | |
70 | 70 | { |
71 | 71 | public: |
72 | 72 | // construction/destruction |
r17959 | r17960 | |
---|---|---|
89 | 89 | emu_timer *command_complete_timer; |
90 | 90 | }; |
91 | 91 | |
92 | enum I8271_STATE_t | |
92 | enum I8271_STATE_t | |
93 | 93 | { |
94 | 94 | I8271_STATE_EXECUTION_READ = 0, |
95 | 95 | I8271_STATE_EXECUTION_WRITE |
r17959 | r17960 | |
---|---|---|
36 | 36 | TYPE DEFINITIONS |
37 | 37 | ***************************************************************************/ |
38 | 38 | |
39 | struct i8271_interface | |
39 | struct i8271_interface | |
40 | 40 | { |
41 | 41 | void (*interrupt)(device_t *device, int state); |
42 | 42 | void (*dma_request)(device_t *device, int state, int read_); |
r17959 | r17960 | |
---|---|---|
9 | 9 | |
10 | 10 | ****************************************************************************************/ |
11 | 11 | |
12 | struct unif | |
12 | struct unif | |
13 | 13 | { |
14 | 14 | const char *board; /* UNIF board */ |
15 | 15 |
r17959 | r17960 | |
---|---|---|
72 | 72 | #include "emu.h" |
73 | 73 | #include "ay31015.h" |
74 | 74 | |
75 | enum state_t | |
75 | enum state_t | |
76 | 76 | { |
77 | 77 | IDLE, |
78 | 78 | START_BIT, |
r17959 | r17960 | |
---|---|---|
12 | 12 | ***************************************************************************/ |
13 | 13 | |
14 | 14 | |
15 | enum ay31015_type_t | |
15 | enum ay31015_type_t | |
16 | 16 | { |
17 | 17 | /* For AY-3-1014A, AY-3-1015(D) and HD6402 variants */ |
18 | 18 | AY_3_1015, |
r17959 | r17960 | |
22 | 22 | }; |
23 | 23 | |
24 | 24 | |
25 | enum ay31015_input_pin_t | |
25 | enum ay31015_input_pin_t | |
26 | 26 | { |
27 | 27 | AY31015_SWE=16, /* -SWE - Pin 16 - Status word enable */ |
28 | 28 | AY31015_RDAV=18, /* -RDAV - Pin 18 - Reset data available */ |
r17959 | r17960 | |
37 | 37 | }; |
38 | 38 | |
39 | 39 | |
40 | enum ay31015_output_pin_t | |
40 | enum ay31015_output_pin_t | |
41 | 41 | { |
42 | 42 | AY31015_PE=13, /* PE - Pin 13 - Parity error */ |
43 | 43 | AY31015_FE=14, /* FE - Pin 14 - Framing error */ |
r17959 | r17960 | |
49 | 49 | }; |
50 | 50 | |
51 | 51 | |
52 | struct | |
52 | struct | |
53 | 53 | { |
54 | 54 | ay31015_type_t type; /* Type of chip */ |
55 | 55 | double transmitter_clock; /* TCP - pin 40 */ |
r17959 | r17960 | |
---|---|---|
42 | 42 | |
43 | 43 | /******************* internal chip data structure ******************/ |
44 | 44 | |
45 | struct mc6843_t | |
45 | struct mc6843_t | |
46 | 46 | { |
47 | 47 | |
48 | 48 | /* interface */ |
r17959 | r17960 | |
---|---|---|
27 | 27 | UINT16 proto; |
28 | 28 | }; |
29 | 29 | |
30 | struct ip_header | |
30 | struct ip_header | |
31 | 31 | { |
32 | 32 | UINT8 version; |
33 | 33 | UINT8 tos; |
r17959 | r17960 | |
---|---|---|
1970 | 1970 | { 0xE0000, 0xEFFFF } |
1971 | 1971 | }; |
1972 | 1972 | |
1973 | struct nimbus_block | |
1973 | struct nimbus_block | |
1974 | 1974 | { |
1975 | 1975 | int blockbase; |
1976 | 1976 | int blocksize; |
r17959 | r17960 | |
---|---|---|
36 | 36 | #define DS_READY 0x02 /* drive ready bit */ |
37 | 37 | #define DS_WRFAULT 0x01 /* write fault */ |
38 | 38 | |
39 | struct smc92x4_interface | |
39 | struct smc92x4_interface | |
40 | 40 | { |
41 | 41 | // Disk format support. This flag allows to choose between the full |
42 | 42 | // FM/MFM format and an abbreviated track layout. The difference results |
r17959 | r17960 | |
---|---|---|
30 | 30 | #define KEY_MODE_FM16B 1 // FM-16B (FM-77AV and later only) |
31 | 31 | #define KEY_MODE_SCAN 2 // Scancode Make/Break (PC-like) |
32 | 32 | |
33 | struct fm7_encoder_t | |
33 | struct fm7_encoder_t | |
34 | 34 | { |
35 | 35 | UINT8 buffer[12]; |
36 | 36 | UINT8 tx_count; |
r17959 | r17960 | |
42 | 42 | UINT8 position; |
43 | 43 | }; |
44 | 44 | |
45 | struct fm7_mmr_t | |
45 | struct fm7_mmr_t | |
46 | 46 | { |
47 | 47 | UINT8 bank_addr[8][16]; |
48 | 48 | UINT8 segment; |
r17959 | r17960 | |
51 | 51 | UINT8 mode; |
52 | 52 | }; |
53 | 53 | |
54 | struct fm7_video_t | |
54 | struct fm7_video_t | |
55 | 55 | { |
56 | 56 | UINT8 sub_busy; |
57 | 57 | UINT8 sub_halt; |
r17959 | r17960 | |
77 | 77 | UINT8 vsync_flag; |
78 | 78 | }; |
79 | 79 | |
80 | struct fm7_alu_t | |
80 | struct fm7_alu_t | |
81 | 81 | { |
82 | 82 | UINT8 command; |
83 | 83 | UINT8 lcolour; |
r17959 | r17960 | |
---|---|---|
73 | 73 | UINT16 ext[4]; |
74 | 74 | }; |
75 | 75 | |
76 | struct i186_state | |
76 | struct i186_state | |
77 | 77 | { |
78 | 78 | struct timer_state timer[3]; |
79 | 79 | struct dma_state dma[2]; |
r17959 | r17960 | |
83 | 83 | |
84 | 84 | |
85 | 85 | /* Keyboard */ |
86 | struct TYP_COMPIS_KEYBOARD | |
86 | struct TYP_COMPIS_KEYBOARD | |
87 | 87 | { |
88 | 88 | UINT8 nationality; /* Character set, keyboard layout (Swedish) */ |
89 | 89 | UINT8 release_time; /* Autorepeat release time (0.8) */ |
r17959 | r17960 | |
102 | 102 | }; |
103 | 103 | |
104 | 104 | /* USART 8251 */ |
105 | struct TYP_COMPIS_USART | |
105 | struct TYP_COMPIS_USART | |
106 | 106 | { |
107 | 107 | UINT8 status; |
108 | 108 | UINT8 bytes_sent; |
109 | 109 | }; |
110 | 110 | |
111 | 111 | /* Printer */ |
112 | struct TYP_COMPIS_PRINTER | |
112 | struct TYP_COMPIS_PRINTER | |
113 | 113 | { |
114 | 114 | UINT8 data; |
115 | 115 | UINT8 strobe; |
r17959 | r17960 | |
117 | 117 | |
118 | 118 | |
119 | 119 | /* Main emulation */ |
120 | struct TYP_COMPIS | |
120 | struct TYP_COMPIS | |
121 | 121 | { |
122 | 122 | TYP_COMPIS_PRINTER printer; /* Printer */ |
123 | 123 | TYP_COMPIS_USART usart; /* USART 8251 */ |
r17959 | r17960 | |
---|---|---|
40 | 40 | #include "machine/nvram.h" |
41 | 41 | |
42 | 42 | |
43 | struct EEPROM | |
43 | struct EEPROM | |
44 | 44 | { |
45 | 45 | UINT8 mode; /* eeprom mode */ |
46 | 46 | UINT16 address; /* Read/write address */ |
r17959 | r17960 | |
52 | 52 | UINT8 *page; /* pointer to current sram/eeprom page */ |
53 | 53 | }; |
54 | 54 | |
55 | struct RTC | |
55 | struct RTC | |
56 | 56 | { |
57 | 57 | UINT8 present; /* Is an RTC present */ |
58 | 58 | UINT8 setting; /* Timer setting byte */ |
r17959 | r17960 | |
66 | 66 | UINT8 index; /* index for reading/writing of current of alarm time */ |
67 | 67 | }; |
68 | 68 | |
69 | struct SoundDMA | |
69 | struct SoundDMA | |
70 | 70 | { |
71 | 71 | UINT32 source; /* Source address */ |
72 | 72 | UINT16 size; /* Size */ |
73 | 73 | UINT8 enable; /* Enabled */ |
74 | 74 | }; |
75 | 75 | |
76 | struct VDP | |
76 | struct VDP | |
77 | 77 | { |
78 | 78 | UINT8 layer_bg_enable; /* Background layer on/off */ |
79 | 79 | UINT8 layer_fg_enable; /* Foreground layer on/off */ |
r17959 | r17960 | |
---|---|---|
63 | 63 | |
64 | 64 | /***** Video Modes *****/ |
65 | 65 | |
66 | enum BETA_VID_MODES | |
66 | enum BETA_VID_MODES | |
67 | 67 | { |
68 | 68 | TEXT_40x25, /* Text mode 40x25 */ |
69 | 69 | TEXT_80x25, /* Text mode 80x25 */ |
r17959 | r17960 | |
74 | 74 | |
75 | 75 | #define iosize (0xfEFF-0xfc00) |
76 | 76 | |
77 | struct PageReg | |
77 | struct PageReg | |
78 | 78 | { |
79 | 79 | int value; /* Value of the page register */ |
80 | 80 | UINT8 *memory; /* The memory it actually points to */ |
r17959 | r17960 | |
---|---|---|
26 | 26 | #define LX385_TAPE_SAMPLE_FREQ 38400 |
27 | 27 | |
28 | 28 | /* wave duration threshold */ |
29 | enum z80netape_speed | |
29 | enum z80netape_speed | |
30 | 30 | { |
31 | 31 | TAPE_300BPS = 300, /* 300 bps */ |
32 | 32 | TAPE_600BPS = 600, /* 600 bps */ |
r17959 | r17960 | |
---|---|---|
164 | 164 | }; |
165 | 165 | |
166 | 166 | /* tape reader registers */ |
167 | struct tape_reader_t | |
167 | struct tape_reader_t | |
168 | 168 | { |
169 | 169 | device_image_interface *fd; /* file descriptor of tape image */ |
170 | 170 | |
r17959 | r17960 | |
182 | 182 | |
183 | 183 | |
184 | 184 | /* tape puncher registers */ |
185 | struct tape_puncher_t | |
185 | struct tape_puncher_t | |
186 | 186 | { |
187 | 187 | device_image_interface *fd; /* file descriptor of tape image */ |
188 | 188 | |
r17959 | r17960 | |
192 | 192 | |
193 | 193 | |
194 | 194 | /* typewriter registers */ |
195 | struct typewriter_t | |
195 | struct typewriter_t | |
196 | 196 | { |
197 | 197 | device_image_interface *fd; /* file descriptor of output image */ |
198 | 198 | |
r17959 | r17960 | |
202 | 202 | }; |
203 | 203 | |
204 | 204 | /* MIT parallel drum (mostly similar to type 23) */ |
205 | struct parallel_drum_t | |
205 | struct parallel_drum_t | |
206 | 206 | { |
207 | 207 | device_image_interface *fd; /* file descriptor of drum image */ |
208 | 208 | |
r17959 | r17960 | |
219 | 219 | }; |
220 | 220 | |
221 | 221 | |
222 | struct lightpen_t | |
222 | struct lightpen_t | |
223 | 223 | { |
224 | 224 | char active; |
225 | 225 | char down; |
r17959 | r17960 | |
---|---|---|
24 | 24 | #define BORDER_TOP (16) // (plus bottom) |
25 | 25 | |
26 | 26 | |
27 | enum apple2gs_clock_mode | |
27 | enum apple2gs_clock_mode | |
28 | 28 | { |
29 | 29 | CLOCKMODE_IDLE, |
30 | 30 | CLOCKMODE_TIME, |
r17959 | r17960 | |
34 | 34 | }; |
35 | 35 | |
36 | 36 | |
37 | enum adbstate_t | |
37 | enum adbstate_t | |
38 | 38 | { |
39 | 39 | ADBSTATE_IDLE, |
40 | 40 | ADBSTATE_INCOMMAND, |
r17959 | r17960 | |
---|---|---|
65 | 65 | DECLARE_READ8_MEMBER( ppi_pc_r ); |
66 | 66 | DECLARE_WRITE8_MEMBER( ppi_pc_w ); |
67 | 67 | DECLARE_PALETTE_INIT(pc8401a); |
68 | ||
68 | ||
69 | 69 | void scan_keyboard(); |
70 | 70 | void bankswitch(UINT8 data); |
71 | 71 |
r17959 | r17960 | |
---|---|---|
20 | 20 | }; |
21 | 21 | |
22 | 22 | /* memory module configuration */ |
23 | struct hp48_module | |
23 | struct hp48_module | |
24 | 24 | { |
25 | 25 | /* static part */ |
26 | 26 | UINT32 off_mask; /* offset bit-mask, indicates the real size */ |
r17959 | r17960 | |
---|---|---|
24 | 24 | #define MAC_539X_2_TAG "539x_2" |
25 | 25 | |
26 | 26 | /* tells which model is being emulated (set by macxxx_init) */ |
27 | enum model_t | |
27 | enum model_t | |
28 | 28 | { |
29 | 29 | PCIMODEL_MAC_PM5200, |
30 | 30 | PCIMODEL_MAC_PM6200, |
r17959 | r17960 | |
---|---|---|
10 | 10 | #include "includes/c64_legacy.h" |
11 | 11 | #include "machine/6526cia.h" |
12 | 12 | |
13 | struct dma_t | |
13 | struct dma_t | |
14 | 14 | { |
15 | 15 | int version; |
16 | 16 | UINT8 data[4]; |
17 | 17 | }; |
18 | 18 | |
19 | struct fdc_t | |
19 | struct fdc_t | |
20 | 20 | { |
21 | 21 | int state; |
22 | 22 | |
r17959 | r17960 | |
32 | 32 | int head,track,sector; |
33 | 33 | }; |
34 | 34 | |
35 | struct expansion_ram_t | |
35 | struct expansion_ram_t | |
36 | 36 | { |
37 | 37 | UINT8 reg; |
38 | 38 | }; |
r17959 | r17960 | |
---|---|---|
37 | 37 | #define ADB_IS_PM_CLASS ((m_model >= MODEL_MAC_PORTABLE && m_model <= MODEL_MAC_PB100) || (m_model >= MODEL_MAC_PB140 && m_model <= MODEL_MAC_PBDUO_270c)) |
38 | 38 | |
39 | 39 | /* for Egret and CUDA streaming MCU commands, command types */ |
40 | enum mac_streaming_t | |
40 | enum mac_streaming_t | |
41 | 41 | { |
42 | 42 | MCU_STREAMING_NONE = 0, |
43 | 43 | MCU_STREAMING_PRAMRD, |
r17959 | r17960 | |
55 | 55 | }; |
56 | 56 | |
57 | 57 | /* tells which model is being emulated (set by macxxx_init) */ |
58 | enum model_t | |
58 | enum model_t | |
59 | 59 | { |
60 | 60 | MODEL_MAC_128K512K, // 68000 machines |
61 | 61 | MODEL_MAC_512KE, |
r17959 | r17960 | |
---|---|---|
14 | 14 | #include "rendlay.h" |
15 | 15 | |
16 | 16 | |
17 | struct PRC | |
17 | struct PRC | |
18 | 18 | { |
19 | 19 | UINT8 colors_inverted; |
20 | 20 | UINT8 background_enabled; |
r17959 | r17960 | |
31 | 31 | }; |
32 | 32 | |
33 | 33 | |
34 | struct TIMERS | |
34 | struct TIMERS | |
35 | 35 | { |
36 | 36 | emu_timer *seconds_timer; |
37 | 37 | emu_timer *hz256_timer; |
r17959 | r17960 | |
---|---|---|
35 | 35 | #define CHRROM 0 |
36 | 36 | #define CHRRAM 1 |
37 | 37 | |
38 | struct chr_bank | |
38 | struct chr_bank | |
39 | 39 | { |
40 | 40 | int source; //defines source of base pointer |
41 | 41 | int origin; //defines offset of 0x400 byte segment at base pointer |
r17959 | r17960 | |
53 | 53 | #define NES_BATTERY 0 |
54 | 54 | #define NES_WRAM 1 |
55 | 55 | |
56 | struct name_table | |
56 | struct name_table | |
57 | 57 | { |
58 | 58 | int source; /* defines source of base pointer */ |
59 | 59 | int origin; /* defines offset of 0x400 byte segment at base pointer */ |
r17959 | r17960 | |
---|---|---|
241 | 241 | DECLARE_MACHINE_RESET(gbpocket); |
242 | 242 | DECLARE_PALETTE_INIT(gbp); |
243 | 243 | DECLARE_MACHINE_START(gbc); |
244 | DECLARE_MACHINE_RESET(gbc); | |
244 | DECLARE_MACHINE_RESET(gbc); | |
245 | 245 | DECLARE_PALETTE_INIT(gbc); |
246 | 246 | DECLARE_MACHINE_START(gb_video); |
247 | 247 | DECLARE_MACHINE_START(gbc_video); |
r17959 | r17960 | |
---|---|---|
44 | 44 | virtual void z80daisy_irq_reti(); |
45 | 45 | }; |
46 | 46 | |
47 | struct scrn_reg_t | |
47 | struct scrn_reg_t | |
48 | 48 | { |
49 | 49 | UINT8 gfx_bank; |
50 | 50 | UINT8 disp_bank; |
r17959 | r17960 | |
56 | 56 | UINT8 blackclip; // x1 turbo specific |
57 | 57 | }; |
58 | 58 | |
59 | struct turbo_reg_t | |
59 | struct turbo_reg_t | |
60 | 60 | { |
61 | 61 | UINT8 pal; |
62 | 62 | UINT8 gfx_pal; |
r17959 | r17960 | |
64 | 64 | UINT8 txt_disp; |
65 | 65 | }; |
66 | 66 | |
67 | struct x1_rtc_t | |
67 | struct x1_rtc_t | |
68 | 68 | { |
69 | 69 | UINT8 sec, min, hour, day, wday, month, year; |
70 | 70 | }; |
r17959 | r17960 | |
---|---|---|
21 | 21 | MaxKeyMessageLen = 1 |
22 | 22 | }; |
23 | 23 | |
24 | struct expansion_slot_t | |
24 | struct expansion_slot_t | |
25 | 25 | { |
26 | 26 | read8_space_func reg_read; |
27 | 27 | write8_space_func reg_write; |
r17959 | r17960 | |
---|---|---|
149 | 149 | SM8521_SG1W15 = 0x7F |
150 | 150 | }; |
151 | 151 | |
152 | struct GAMECOM_DMA | |
152 | struct GAMECOM_DMA | |
153 | 153 | { |
154 | 154 | int enabled; |
155 | 155 | int transfer_mode; |
r17959 | r17960 | |
182 | 182 | unsigned int dest_mask; |
183 | 183 | }; |
184 | 184 | |
185 | struct GAMECOM_TIMER | |
185 | struct GAMECOM_TIMER | |
186 | 186 | { |
187 | 187 | int enabled; |
188 | 188 | int state_count; |
r17959 | r17960 | |
190 | 190 | int check_value; |
191 | 191 | }; |
192 | 192 | |
193 | struct gamecom_sound_t | |
193 | struct gamecom_sound_t | |
194 | 194 | { |
195 | 195 | UINT8 sgc; |
196 | 196 | UINT8 sg0l; |
r17959 | r17960 | |
---|---|---|
9 | 9 | |
10 | 10 | #define MAX_CX_TIMERS 16 |
11 | 11 | |
12 | struct cx_timer_t | |
12 | struct cx_timer_t | |
13 | 13 | { |
14 | 14 | UINT32 value; |
15 | 15 | UINT32 limit; |
r17959 | r17960 | |
18 | 18 | emu_timer *timer; |
19 | 19 | }; |
20 | 20 | |
21 | struct cx_timer_regs_t | |
21 | struct cx_timer_regs_t | |
22 | 22 | { |
23 | 23 | cx_timer_t timer[MAX_CX_TIMERS]; |
24 | 24 | UINT32 timer_irq; |
r17959 | r17960 | |
---|---|---|
69 | 69 | DECLARE_READ8_MEMBER( vic_lightx_cb ); |
70 | 70 | DECLARE_READ8_MEMBER( vic_lighty_cb ); |
71 | 71 | DECLARE_READ8_MEMBER( vic_lightbut_cb ); |
72 | ||
72 | ||
73 | 73 | DECLARE_READ8_MEMBER( via0_pa_r ); |
74 | 74 | DECLARE_WRITE8_MEMBER( via0_pa_w ); |
75 | 75 |
r17959 | r17960 | |
---|---|---|
16 | 16 | #define KB_COP421_TAG "kbcop" |
17 | 17 | |
18 | 18 | /* lisa MMU segment regs */ |
19 | struct real_mmu_entry | |
19 | struct real_mmu_entry | |
20 | 20 | { |
21 | 21 | UINT16 sorg; |
22 | 22 | UINT16 slim; |
r17959 | r17960 | |
25 | 25 | /* MMU regs translated into a more efficient format */ |
26 | 26 | enum mmu_entry_t { RAM_stack_r, RAM_r, RAM_stack_rw, RAM_rw, IO, invalid, special_IO }; |
27 | 27 | |
28 | struct mmu_entry | |
28 | struct mmu_entry | |
29 | 29 | { |
30 | 30 | offs_t sorg; /* (real_sorg & 0x0fff) << 9 */ |
31 | 31 | mmu_entry_t type; /* <-> (real_slim & 0x0f00) */ |
r17959 | r17960 | |
48 | 48 | }; /* clock mode */ |
49 | 49 | |
50 | 50 | /* clock registers */ |
51 | struct clock_regs_t | |
51 | struct clock_regs_t | |
52 | 52 | { |
53 | 53 | long alarm; /* alarm (20-bit binary) */ |
54 | 54 | int years; /* years (4-bit binary ) */ |
r17959 | r17960 | |
68 | 68 | enum clock_mode_t clock_mode; |
69 | 69 | }; |
70 | 70 | |
71 | struct lisa_features_t | |
71 | struct lisa_features_t | |
72 | 72 | { |
73 | 73 | unsigned int has_fast_timers : 1; /* I/O board VIAs are clocked at 1.25 MHz (?) instead of .5 MHz (?) (Lisa 2/10, Mac XL) */ |
74 | 74 | /* Note that the beep routine in boot ROMs implies that |
r17959 | r17960 | |
---|---|---|
15 | 15 | |
16 | 16 | |
17 | 17 | class lynx_state; |
18 | struct BLITTER | |
18 | struct BLITTER | |
19 | 19 | { |
20 | 20 | UINT8 *mem; |
21 | 21 | // global |
r17959 | r17960 | |
54 | 54 | int busy; |
55 | 55 | }; |
56 | 56 | |
57 | struct UART | |
57 | struct UART | |
58 | 58 | { |
59 | 59 | UINT8 serctl; |
60 | 60 | UINT8 data_received, data_to_send, buffer; |
r17959 | r17960 | |
63 | 63 | int buffer_loaded; |
64 | 64 | }; |
65 | 65 | |
66 | struct SUZY | |
66 | struct SUZY | |
67 | 67 | { |
68 | 68 | UINT8 data[0x100]; |
69 | 69 | UINT8 high; |
r17959 | r17960 | |
73 | 73 | int accumulate_overflow; |
74 | 74 | }; |
75 | 75 | |
76 | struct MIKEY | |
76 | struct MIKEY | |
77 | 77 | { |
78 | 78 | UINT8 data[0x100]; |
79 | 79 | UINT16 disp_addr; |
80 | 80 | UINT8 vb_rest; |
81 | 81 | }; |
82 | 82 | |
83 | struct LYNX_TIMER | |
83 | struct LYNX_TIMER | |
84 | 84 | { |
85 | 85 | UINT8 bakup; |
86 | 86 | UINT8 cntrl1; |
r17959 | r17960 | |
---|---|---|
10 | 10 | #include "machine/wd17xx.h" |
11 | 11 | |
12 | 12 | // CRTC 6845 |
13 | struct CRTC6845 | |
13 | struct CRTC6845 | |
14 | 14 | { |
15 | 15 | UINT8 cursor_address_lo; |
16 | 16 | UINT8 cursor_address_hi; |
r17959 | r17960 | |
---|---|---|
51 | 51 | #define TS2068_RIGHT_BORDER 96 /* Number of right hand border pixels */ |
52 | 52 | #define TS2068_SCREEN_WIDTH (TS2068_LEFT_BORDER + TS2068_DISPLAY_XSIZE + TS2068_RIGHT_BORDER) |
53 | 53 | |
54 | struct EVENT_LIST_ITEM | |
54 | struct EVENT_LIST_ITEM | |
55 | 55 | { |
56 | 56 | /* driver defined ID for this write */ |
57 | 57 | int Event_ID; |
r17959 | r17960 | |
---|---|---|
55 | 55 | |
56 | 56 | |
57 | 57 | /* tape reader registers */ |
58 | struct tape_reader_t | |
58 | struct tape_reader_t | |
59 | 59 | { |
60 | 60 | device_image_interface *fd; /* file descriptor of tape image */ |
61 | 61 | |
r17959 | r17960 | |
70 | 70 | |
71 | 71 | |
72 | 72 | /* tape puncher registers */ |
73 | struct tape_puncher_t | |
73 | struct tape_puncher_t | |
74 | 74 | { |
75 | 75 | device_image_interface *fd; /* file descriptor of tape image */ |
76 | 76 | |
r17959 | r17960 | |
80 | 80 | |
81 | 81 | |
82 | 82 | /* typewriter registers */ |
83 | struct typewriter_t | |
83 | struct typewriter_t | |
84 | 84 | { |
85 | 85 | device_image_interface *fd; /* file descriptor of output image */ |
86 | 86 | |
r17959 | r17960 | |
89 | 89 | |
90 | 90 | |
91 | 91 | /* magnetic tape unit registers */ |
92 | struct magtape_t | |
92 | struct magtape_t | |
93 | 93 | { |
94 | 94 | device_image_interface *img; /* image descriptor */ |
95 | 95 |
r17959 | r17960 | |
---|---|---|
40 | 40 | UINT8 m_port_202f; |
41 | 41 | UINT8 m_port_303f; |
42 | 42 | UINT8 m_port_707f; |
43 | INT8 m_frame_count; | |
43 | INT8 m_frame_count; | |
44 | 44 | DECLARE_VIDEO_START(p2000m); |
45 | 45 | DECLARE_PALETTE_INIT(p2000m); |
46 | 46 | }; |
r17959 | r17960 | |
---|---|---|
13 | 13 | #include "machine/ieee488.h" |
14 | 14 | #include "imagedev/cartslot.h" |
15 | 15 | |
16 | struct spet_t | |
16 | struct spet_t | |
17 | 17 | { |
18 | 18 | int bank; /* rambank to be switched in 0x9000 */ |
19 | 19 | int rom; /* rom socket 6502? at 0x9000 */ |
r17959 | r17960 | |
---|---|---|
30 | 30 | TELESTRAT_MEM_BLOCK_ROM |
31 | 31 | }; |
32 | 32 | |
33 | struct telestrat_mem_block | |
33 | struct telestrat_mem_block | |
34 | 34 | { |
35 | 35 | int MemType; |
36 | 36 | unsigned char *ptr; |
r17959 | r17960 | |
40 | 40 | /* current state of the display */ |
41 | 41 | /* some attributes persist until they are turned off. |
42 | 42 | This structure holds this persistant information */ |
43 | struct oric_vh_state | |
43 | struct oric_vh_state | |
44 | 44 | { |
45 | 45 | /* foreground and background colour used for rendering */ |
46 | 46 | /* if flash attribute is set, these two will both be equal to background colour */ |
r17959 | r17960 | |
---|---|---|
75 | 75 | #define FDC_TAG "wd1793" |
76 | 76 | |
77 | 77 | |
78 | struct keyboard_t | |
78 | struct keyboard_t | |
79 | 79 | { |
80 | 80 | UINT8 keyrows[MBC55X_KEYROWS]; |
81 | 81 | emu_timer *keyscan_timer; |
r17959 | r17960 | |
161 | 161 | /* IO chips */ |
162 | 162 | |
163 | 163 | |
164 | struct msm_rx_t | |
164 | struct msm_rx_t | |
165 | 165 | { |
166 | 166 | }; |
167 | 167 |
r17959 | r17960 | |
---|---|---|
34 | 34 | #define INT_EINT1 1 |
35 | 35 | #define INT_EINT0 0 |
36 | 36 | |
37 | struct s3c240x_lcd_t | |
37 | struct s3c240x_lcd_t | |
38 | 38 | { |
39 | 39 | UINT32 vramaddr_cur; |
40 | 40 | UINT32 vramaddr_max; |
r17959 | r17960 | |
47 | 47 | int vpos, hpos; |
48 | 48 | }; |
49 | 49 | |
50 | struct smc_t | |
50 | struct smc_t | |
51 | 51 | { |
52 | 52 | int add_latch; |
53 | 53 | int chip; |
r17959 | r17960 | |
61 | 61 | UINT8 datatx; |
62 | 62 | }; |
63 | 63 | |
64 | struct i2s_t | |
64 | struct i2s_t | |
65 | 65 | { |
66 | 66 | int l3d; |
67 | 67 | int l3m; |
68 | 68 | int l3c; |
69 | 69 | }; |
70 | 70 | |
71 | struct s3c240x_iic_t | |
71 | struct s3c240x_iic_t | |
72 | 72 | { |
73 | 73 | UINT8 data[4]; |
74 | 74 | int data_index; |
75 | 75 | UINT16 address; |
76 | 76 | }; |
77 | 77 | |
78 | struct s3c240x_iis_t | |
78 | struct s3c240x_iis_t | |
79 | 79 | { |
80 | 80 | UINT16 fifo[16/2]; |
81 | 81 | int fifo_index; |
r17959 | r17960 | |
---|---|---|
23 | 23 | |
24 | 24 | /* ULA context */ |
25 | 25 | |
26 | struct ULA | |
26 | struct ULA | |
27 | 27 | { |
28 | 28 | UINT8 interrupt_status; |
29 | 29 | UINT8 interrupt_control; |
r17959 | r17960 | |
---|---|---|
13 | 13 | |
14 | 14 | |
15 | 15 | /* SKR - 2102 RAM chip on carts 10 and 18 I/O ports */ |
16 | struct r2102_t | |
16 | struct r2102_t | |
17 | 17 | { |
18 | 18 | UINT8 d; /* data bit:inverted logic, but reading/writing cancel out */ |
19 | 19 | UINT8 r_w; /* inverted logic: 0 means read, 1 means write */ |
r17959 | r17960 | |
---|---|---|
12 | 12 | |
13 | 13 | typedef short termchar_t; |
14 | 14 | |
15 | struct terminal_t | |
15 | struct terminal_t | |
16 | 16 | { |
17 | 17 | tilemap_t *tm; |
18 | 18 | int gfx; |
r17959 | r17960 | |
---|---|---|
13 | 13 | #include "machine/8237dma.h" |
14 | 14 | #include "machine/53c810.h" |
15 | 15 | |
16 | struct bebox_devices_t | |
16 | struct bebox_devices_t | |
17 | 17 | { |
18 | 18 | device_t *pic8259_master; |
19 | 19 | device_t *pic8259_slave; |
r17959 | r17960 | |
---|---|---|
10 | 10 | #include "imagedev/snapquik.h" |
11 | 11 | #include "machine/wd17xx.h" |
12 | 12 | |
13 | struct nascom1_portstat_t | |
13 | struct nascom1_portstat_t | |
14 | 14 | { |
15 | 15 | UINT8 stat_flags; |
16 | 16 | UINT8 stat_count; |
17 | 17 | }; |
18 | 18 | |
19 | struct nascom2_fdc_t | |
19 | struct nascom2_fdc_t | |
20 | 20 | { |
21 | 21 | UINT8 select; |
22 | 22 | UINT8 irq; |
r17959 | r17960 | |
---|---|---|
1 | 1 | #ifndef __GMASTER_H__ |
2 | 2 | #define __GMASTER_H__ |
3 | 3 | |
4 | struct GMASTER_VIDEO | |
4 | struct GMASTER_VIDEO | |
5 | 5 | { |
6 | 6 | UINT8 data[8]; |
7 | 7 | int index; |
r17959 | r17960 | |
11 | 11 | UINT8 pixels[8][64/*>=62 sure*/]; |
12 | 12 | }; |
13 | 13 | |
14 | struct GMASTER_MACHINE | |
14 | struct GMASTER_MACHINE | |
15 | 15 | { |
16 | 16 | UINT8 ports[5]; |
17 | 17 | }; |
r17959 | r17960 | |
---|---|---|
7 | 7 | #ifndef INTV_H_ |
8 | 8 | #define INTV_H_ |
9 | 9 | |
10 | struct intv_sprite_type | |
10 | struct intv_sprite_type | |
11 | 11 | { |
12 | 12 | int visible; |
13 | 13 | int xpos; |
r17959 | r17960 | |
---|---|---|
8 | 8 | #define SSYSTEM3_H_ |
9 | 9 | |
10 | 10 | |
11 | struct playfield_t | |
11 | struct playfield_t | |
12 | 12 | { |
13 | 13 | int signal; |
14 | 14 | // int on; |
r17959 | r17960 | |
26 | 26 | } u; |
27 | 27 | }; |
28 | 28 | |
29 | struct lcd_t | |
29 | struct lcd_t | |
30 | 30 | { |
31 | 31 | UINT8 data[5]; |
32 | 32 | int clock; |
r17959 | r17960 | |
---|---|---|
23 | 23 | /**************************** |
24 | 24 | * Gate Array data (CPC) - |
25 | 25 | ****************************/ |
26 | struct gate_array_t | |
26 | struct gate_array_t | |
27 | 27 | { |
28 | 28 | bitmap_ind16 *bitmap; /* The bitmap we work on */ |
29 | 29 | UINT8 pen_selected; /* Pen selection */ |
r17959 | r17960 | |
60 | 60 | /**************************** |
61 | 61 | * ASIC data (CPC plus) |
62 | 62 | ****************************/ |
63 | struct asic_t | |
63 | struct asic_t | |
64 | 64 | { |
65 | 65 | UINT8 *ram; /* pointer to RAM used for the CPC+ ASIC memory-mapped registers */ |
66 | 66 | UINT8 enabled; /* Are CPC plus features enabled/unlocked */ |
r17959 | r17960 | |
---|---|---|
26 | 26 | |
27 | 27 | /* Nimbus sub-bios structures for debugging */ |
28 | 28 | |
29 | struct t_area_params | |
29 | struct t_area_params | |
30 | 30 | { |
31 | 31 | UINT16 ofs_brush; |
32 | 32 | UINT16 seg_brush; |
r17959 | r17960 | |
35 | 35 | UINT16 count; |
36 | 36 | }; |
37 | 37 | |
38 | struct t_plot_string_params | |
38 | struct t_plot_string_params | |
39 | 39 | { |
40 | 40 | UINT16 ofs_font; |
41 | 41 | UINT16 seg_font; |
r17959 | r17960 | |
46 | 46 | UINT16 length; |
47 | 47 | }; |
48 | 48 | |
49 | struct t_nimbus_brush | |
49 | struct t_nimbus_brush | |
50 | 50 | { |
51 | 51 | UINT16 style; |
52 | 52 | UINT16 style_index; |
r17959 | r17960 | |
110 | 110 | UINT16 ext_vector[2]; // external vectors, when in cascade mode |
111 | 111 | }; |
112 | 112 | |
113 | struct i186_state | |
113 | struct i186_state | |
114 | 114 | { |
115 | 115 | struct timer_state timer[3]; |
116 | 116 | struct dma_state dma[2]; |
r17959 | r17960 | |
118 | 118 | struct mem_state mem; |
119 | 119 | }; |
120 | 120 | |
121 | struct keyboard_t | |
121 | struct keyboard_t | |
122 | 122 | { |
123 | 123 | UINT8 keyrows[NIMBUS_KEYROWS]; |
124 | 124 | emu_timer *keyscan_timer; |
r17959 | r17960 | |
128 | 128 | }; |
129 | 129 | |
130 | 130 | // Static data related to Floppy and SCSI hard disks |
131 | struct nimbus_drives_t | |
131 | struct nimbus_drives_t | |
132 | 132 | { |
133 | 133 | UINT8 reg400; |
134 | 134 | UINT8 reg410_in; |
r17959 | r17960 | |
140 | 140 | }; |
141 | 141 | |
142 | 142 | /* 8031 Peripheral controler */ |
143 | struct ipc_interface_t | |
143 | struct ipc_interface_t | |
144 | 144 | { |
145 | 145 | UINT8 ipc_in; |
146 | 146 | UINT8 ipc_out; |
r17959 | r17960 | |
152 | 152 | }; |
153 | 153 | |
154 | 154 | /* Mouse/Joystick */ |
155 | struct mouse_joy_state | |
155 | struct mouse_joy_state | |
156 | 156 | { |
157 | 157 | UINT8 m_mouse_px; |
158 | 158 | UINT8 m_mouse_py; |
r17959 | r17960 | |
---|---|---|
113 | 113 | /* sound state */ |
114 | 114 | int m_buzzer; /* buzzer select */ |
115 | 115 | int m_bell; /* bell output */ |
116 | ||
116 | ||
117 | 117 | DECLARE_PALETTE_INIT(kc85); |
118 | 118 | }; |
119 | 119 |
r17959 | r17960 | |
---|---|---|
28 | 28 | #include "machine/sst39vfx.h" |
29 | 29 | #include "machine/ram.h" |
30 | 30 | |
31 | struct CYBIKO_RS232_PINS | |
31 | struct CYBIKO_RS232_PINS | |
32 | 32 | { |
33 | 33 | int sck; // serial clock |
34 | 34 | int txd; // transmit data |
35 | 35 | int rxd; // receive data |
36 | 36 | }; |
37 | 37 | |
38 | struct CYBIKO_RS232 | |
38 | struct CYBIKO_RS232 | |
39 | 39 | { |
40 | 40 | CYBIKO_RS232_PINS pin; |
41 | 41 | UINT8 rx_bits, rx_byte, tx_byte, tx_bits; |
r17959 | r17960 | |
---|---|---|
54 | 54 | } s; |
55 | 55 | }; |
56 | 56 | |
57 | struct ef9341_t | |
57 | struct ef9341_t | |
58 | 58 | { |
59 | 59 | UINT8 X; |
60 | 60 | UINT8 Y; |
r17959 | r17960 | |
---|---|---|
72 | 72 | #define APPLE2_MEM_FLOATING 0xFFFFFFFF |
73 | 73 | #define APPLE2_MEM_MASK 0x00FFFFFF |
74 | 74 | |
75 | enum machine_type_t | |
75 | enum machine_type_t | |
76 | 76 | { |
77 | 77 | APPLE_II, // Apple II/II+ |
78 | 78 | APPLE_IIEPLUS, // Apple IIe/IIc/IIgs/IIc+ |
r17959 | r17960 | |
81 | 81 | SPACE84 // "Space 84" with flipped text mode |
82 | 82 | }; |
83 | 83 | |
84 | enum bank_disposition_t | |
84 | enum bank_disposition_t | |
85 | 85 | { |
86 | 86 | A2MEM_IO = 0, /* this is always handlers; never banked memory */ |
87 | 87 | A2MEM_MONO = 1, /* this is a bank where read and write are always in unison */ |
r17959 | r17960 | |
---|---|---|
7 | 7 | #ifndef SVISION_H_ |
8 | 8 | #define SVISION_H_ |
9 | 9 | |
10 | struct svision_t | |
10 | struct svision_t | |
11 | 11 | { |
12 | 12 | emu_timer *timer1; |
13 | 13 | int timer_shot; |
14 | 14 | }; |
15 | 15 | |
16 | struct svision_pet_t | |
16 | struct svision_pet_t | |
17 | 17 | { |
18 | 18 | int state; |
19 | 19 | int on, clock, data; |
r17959 | r17960 | |
21 | 21 | emu_timer *timer; |
22 | 22 | }; |
23 | 23 | |
24 | struct tvlink_t | |
24 | struct tvlink_t | |
25 | 25 | { |
26 | 26 | UINT32 palette[4/*0x40?*/]; /* rgb8 */ |
27 | 27 | int palette_on; |
r17959 | r17960 | |
---|---|---|
13 | 13 | #include "machine/ins8250.h" |
14 | 14 | #include "machine/wd17xx.h" |
15 | 15 | |
16 | struct SVI_318 | |
16 | struct SVI_318 | |
17 | 17 | { |
18 | 18 | /* general */ |
19 | 19 | UINT8 svi318; /* Are we dealing with an SVI-318 or a SVI-328 model. 0 = 328, 1 = 318 */ |
r17959 | r17960 | |
37 | 37 | UINT8 *svi806_gfx; |
38 | 38 | }; |
39 | 39 | |
40 | struct SVI318_FDC_STRUCT | |
40 | struct SVI318_FDC_STRUCT | |
41 | 41 | { |
42 | 42 | UINT8 driveselect; |
43 | 43 | int drq; |
r17959 | r17960 | |
---|---|---|
31 | 31 | /* the largest possible cartridge image (street fighter 2 - 2.5MB) */ |
32 | 32 | #define PCE_ROM_MAXSIZE 0x280000 |
33 | 33 | |
34 | struct pce_cd_t | |
34 | struct pce_cd_t | |
35 | 35 | { |
36 | 36 | UINT8 regs[16]; |
37 | 37 | UINT8 *bram; |
r17959 | r17960 | |
---|---|---|
19 | 19 | #define ANALOG_HACK |
20 | 20 | |
21 | 21 | |
22 | struct SPRITE_HELPER | |
22 | struct SPRITE_HELPER | |
23 | 23 | { |
24 | 24 | UINT8 bitmap[10],x1,x2,y1,y2, res1, res2; |
25 | 25 | }; |
26 | 26 | |
27 | struct SPRITE | |
27 | struct SPRITE | |
28 | 28 | { |
29 | 29 | const SPRITE_HELPER *data; |
30 | 30 | int mask; |
r17959 | r17960 | |
37 | 37 | int finished_now; |
38 | 38 | }; |
39 | 39 | |
40 | struct vc4000_video_t | |
40 | struct vc4000_video_t | |
41 | 41 | { |
42 | 42 | SPRITE sprites[4]; |
43 | 43 | int line; |
r17959 | r17960 | |
---|---|---|
86 | 86 | 0x01, 0x09, 0x01, 0x03, 0x03, 0x01, 0x01 |
87 | 87 | }; |
88 | 88 | |
89 | struct x07_kb | |
89 | struct x07_kb | |
90 | 90 | { |
91 | 91 | const char *tag; //input port tag |
92 | 92 | UINT8 mask; //bit mask |
r17959 | r17960 | |
---|---|---|
1 | 1 | /* |
2 | 2 | * isa_vga_ati.c |
3 | 3 | * |
4 | * Implementation of the ATi Graphics Ultra ISA Video card | |
5 | * - Uses ATi 28800-6 (VGA Wonder) and ATi 38800-1 (Mach8, 8514/A clone) | |
4 | * Implementation of the ATi Graphics Ultra ISA Video card | |
5 | * - Uses ATi 28800-6 (VGA Wonder) and ATi 38800-1 (Mach8, 8514/A clone) | |
6 | 6 | * |
7 | 7 | * Created on: 9/09/2012 |
8 | 8 | */ |
r17959 | r17960 | |
---|---|---|
1 | 1 | /* |
2 | 2 | * isa_vga_ati.h |
3 | 3 | * |
4 | * | |
4 | * Header for ATi Graphics Ultra ISA video card | |
5 | 5 | * |
6 | 6 | * Created on: 9/09/2012 |
7 | 7 | */ |
r17959 | r17960 | |
---|---|---|
79 | 79 | 2, 1 /* low intensity, reverse */ |
80 | 80 | }; |
81 | 81 | |
82 | struct vdt_t | |
82 | struct vdt_t | |
83 | 83 | { |
84 | 84 | vdt911_screen_size_t screen_size; /* char_960 for 960-char, 12-line model; char_1920 for 1920-char, 24-line model */ |
85 | 85 | vdt911_model_t model; /* country code */ |
r17959 | r17960 | |
---|---|---|
20 | 20 | GFXDECODE_EXTERN( vdt911 ); |
21 | 21 | |
22 | 22 | enum vdt911_screen_size_t { char_960, char_1920 }; |
23 | enum vdt911_model_t | |
23 | enum vdt911_model_t | |
24 | 24 | { |
25 | 25 | vdt911_model_US, |
26 | 26 | vdt911_model_UK, |
r17959 | r17960 | |
33 | 33 | vdt911_model_FrenchWP /* French word processing */ |
34 | 34 | }; |
35 | 35 | |
36 | struct vdt911_init_params_t | |
36 | struct vdt911_init_params_t | |
37 | 37 | { |
38 | 38 | vdt911_screen_size_t screen_size; |
39 | 39 | vdt911_model_t model; |
r17959 | r17960 | |
---|---|---|
52 | 52 | static READ32_HANDLER( newport_vc2_r ); |
53 | 53 | static WRITE32_HANDLER( newport_vc2_w ); |
54 | 54 | |
55 | struct VC2_t | |
55 | struct VC2_t | |
56 | 56 | { |
57 | 57 | UINT16 nRegister[0x21]; |
58 | 58 | UINT16 nRAM[0x8000]; |
r17959 | r17960 | |
79 | 79 | #define VC2_DISPLAYCTRL pNVID->VC2.nRegister[0x10] |
80 | 80 | #define VC2_CONFIG pNVID->VC2.nRegister[0x1f] |
81 | 81 | |
82 | struct XMAP_t | |
82 | struct XMAP_t | |
83 | 83 | { |
84 | 84 | UINT32 nRegister[0x08]; |
85 | 85 | UINT32 nModeTable[0x20]; |
r17959 | r17960 | |
100 | 100 | #define XMAP1_MODETBLIDX pNVID->XMAP1.nRegister[0x07] |
101 | 101 | |
102 | 102 | |
103 | struct REX3_t | |
103 | struct REX3_t | |
104 | 104 | { |
105 | 105 | UINT32 nDrawMode1; |
106 | 106 | UINT32 nDrawMode0; |
r17959 | r17960 | |
180 | 180 | }; |
181 | 181 | |
182 | 182 | |
183 | struct CMAP_t | |
183 | struct CMAP_t | |
184 | 184 | { |
185 | 185 | UINT16 nPaletteIndex; |
186 | 186 | UINT32 nPalette[0x10000]; |
r17959 | r17960 | |
---|---|---|
43 | 43 | |
44 | 44 | /* Nick executes a Display list, in the form of a list of Line Parameter |
45 | 45 | Tables, this is the form of the data */ |
46 | struct LPT_ENTRY | |
46 | struct LPT_ENTRY | |
47 | 47 | { |
48 | 48 | unsigned char SC; /* scanlines in this modeline (two's complement) */ |
49 | 49 | unsigned char MB; /* the MODEBYTE (defines video display mode) */ |
r17959 | r17960 | |
56 | 56 | unsigned char COL[8]; /* COL0..COL7 */ |
57 | 57 | }; |
58 | 58 | |
59 | struct NICK_STATE | |
59 | struct NICK_STATE | |
60 | 60 | { |
61 | 61 | /* horizontal position */ |
62 | 62 | unsigned char HorizontalClockCount; |
r17959 | r17960 | |
---|---|---|
843 | 843 | |
844 | 844 | apollo_mono19i_device::apollo_mono19i_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
845 | 845 | : apollo_mono_device(mconfig, APOLLO_MONO19I, "Apollo 19\" Monochrome Screen", tag, owner, clock) |
846 | { | |
846 | { | |
847 | 847 | } |
848 | 848 | |
849 | 849 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
75 | 75 | /* structure used to describe differences between national character sets and |
76 | 76 | US character set */ |
77 | 77 | /* much more compact than defining the complete 128-char vector */ |
78 | struct char_override_t | |
78 | struct char_override_t | |
79 | 79 | { |
80 | 80 | unsigned char char_index; /* char to replace */ |
81 | 81 | unsigned short symbol_index; /* replacement symbol */ |
r17959 | r17960 | |
---|---|---|
26 | 26 | |
27 | 27 | typedef UINT8 (*vic3_c64mem_callback)(running_machine &machine, int offset); |
28 | 28 | |
29 | enum vic3_type | |
29 | enum vic3_type | |
30 | 30 | { |
31 | 31 | VIC4567_NTSC, |
32 | 32 | VIC4567_PAL |
r17959 | r17960 | |
---|---|---|
186 | 186 | terminal_t *term; |
187 | 187 | int char_width, char_height; |
188 | 188 | apple1_state *state = machine.driver_data<apple1_state>(); |
189 | ||
189 | ||
190 | 190 | char_width = machine.gfx[gfx]->width(); |
191 | 191 | char_height = machine.gfx[gfx]->height(); |
192 | 192 |
r17959 | r17960 | |
---|---|---|
14 | 14 | TYPE DEFINITIONS |
15 | 15 | ***************************************************************************/ |
16 | 16 | |
17 | enum vic2_type | |
17 | enum vic2_type | |
18 | 18 | { |
19 | 19 | VIC6567, // VIC II NTSC |
20 | 20 | VIC6569, // VIC II PAL |
r17959 | r17960 | |
---|---|---|
281 | 281 | inline UINT8 mos6566_device::read_videoram(offs_t offset) |
282 | 282 | { |
283 | 283 | m_last_data = space(AS_0)->read_byte(offset & 0x3fff); |
284 | ||
284 | ||
285 | 285 | return m_last_data; |
286 | 286 | } |
287 | 287 | |
r17959 | r17960 | |
799 | 799 | m_spr_ptr[i] = 0; |
800 | 800 | m_mc_base[i] = 0; |
801 | 801 | m_mc[i] = 0; |
802 | ||
802 | ||
803 | 803 | for (int j = 0; j < 4; j++) |
804 | 804 | { |
805 | 805 | m_spr_draw_data[i][j] = 0; |
r17959 | r17960 | |
---|---|---|
32 | 32 | #include "video/crt.h" |
33 | 33 | |
34 | 34 | |
35 | struct point | |
35 | struct point | |
36 | 36 | { |
37 | 37 | int intensity; /* current intensity of the pixel */ |
38 | 38 | /* a node is not in the list when (intensity == -1) */ |
r17959 | r17960 | |
44 | 44 | intensity_pixel_not_in_list = -1 /* special value that tells that the node is not in list */ |
45 | 45 | }; |
46 | 46 | |
47 | struct crt_t | |
47 | struct crt_t | |
48 | 48 | { |
49 | 49 | point *list; /* array of (crt_window_width*crt_window_height) point */ |
50 | 50 | int *list_head; /* head of the list of lit pixels (index in the array) */ |
r17959 | r17960 | |
---|---|---|
266 | 266 | if (intf->update) |
267 | 267 | intf->update(device, i, pattern); |
268 | 268 | } |
269 | } | |
269 | } | |
270 | 270 | } |
271 | 271 | } |
272 | 272 | else /* cursor enable is not set, so standard write */ |
r17959 | r17960 | |
---|---|---|
34 | 34 | asr_scroll_step = 8 |
35 | 35 | }; |
36 | 36 | |
37 | struct asr_t | |
37 | struct asr_t | |
38 | 38 | { |
39 | 39 | #if 0 |
40 | 40 | UINT8 OutQueue[ASROutQueueSize]; |
r17959 | r17960 | |
---|---|---|
9 | 9 | asr733_chr_region_len = 128*asr733_single_char_len |
10 | 10 | }; |
11 | 11 | |
12 | struct asr733_init_params_t | |
12 | struct asr733_init_params_t | |
13 | 13 | { |
14 | 14 | void (*int_callback)(running_machine &machine, int state); |
15 | 15 | }; |
r17959 | r17960 | |
---|---|---|
18 | 18 | TIMEX_CART_HOME |
19 | 19 | }; |
20 | 20 | |
21 | struct timex_cart_t | |
21 | struct timex_cart_t | |
22 | 22 | { |
23 | 23 | int type; |
24 | 24 | UINT8 chunks; |
r17959 | r17960 | |
---|---|---|
141 | 141 | #define FRZ_HDR 42 |
142 | 142 | #define FRZ_SIZE (FRZ_HDR + 8*SPECTRUM_BANK) |
143 | 143 | |
144 | enum SPECTRUM_SNAPSHOT_TYPE | |
144 | enum SPECTRUM_SNAPSHOT_TYPE | |
145 | 145 | { |
146 | 146 | SPECTRUM_SNAPSHOT_NONE, |
147 | 147 | SPECTRUM_SNAPSHOT_SNA, |
r17959 | r17960 | |
---|---|---|
8 | 8 | - floppy interface doesn't seem to work at all with either floppy inserted or not, missing DMA irq? |
9 | 9 | - proper 8251 uart hook-up on keyboard |
10 | 10 | - boot is too slow right now, might be due of the floppy / HDD devices |
11 | ||
11 | - investigate on POR bit | |
12 | 12 | |
13 | 13 | TODO (PC-9801RS): |
14 | 14 | - floppy disk hook-up; |
r17959 | r17960 | |
17 | 17 | |
18 | 18 | TODO (PC-9821): |
19 | 19 | - fix CPU for some clones; |
20 | ||
20 | - PARITY ERROR, presumably it needs a far better emulation of the i8251 ports | |
21 | 21 | |
22 | 22 | TODO: (PC-486MU) |
23 | 23 | - Tries to read port C of i8255_sys (-> 0x35) at boot without setting up the control |
r17959 | r17960 | |
---|---|---|
10 | 10 | TODO: |
11 | 11 | - cassette interface, basically any program that's bigger than 8kb fails to load; |
12 | 12 | - implement remaining video capabilities |
13 | - add 80b compatibility support; | |
14 | - Vosque (color): keyboard doesn't work properly; | |
13 | - add 80b compatibility support; | |
14 | - Vosque (color): keyboard doesn't work properly; | |
15 | 15 | |
16 | 16 | ****************************************************************************/ |
17 | 17 | |
r17959 | r17960 | |
607 | 607 | static WRITE8_DEVICE_HANDLER( mz2000_porta_w ) |
608 | 608 | { |
609 | 609 | /* |
610 | ||
610 | These are enabled thru a 0->1 transition | |
611 | 611 | x--- ---- tape "APSS" |
612 | 612 | -x-- ---- tape "APLAY" |
613 | 613 | --x- ---- tape "AREW" |
r17959 | r17960 | |
---|---|---|
29 | 29 | #include "sound/2203intf.h" |
30 | 30 | #include "formats/basicdsk.h" |
31 | 31 | |
32 | struct tsp_t | |
32 | struct tsp_t | |
33 | 33 | { |
34 | 34 | UINT16 tvram_vreg_offset; |
35 | 35 | UINT16 attr_offset; |
r17959 | r17960 | |
---|---|---|
534 | 534 | * Sound interface |
535 | 535 | * |
536 | 536 | *************************************/ |
537 | ||
538 | ||
537 | ||
538 | ||
539 | 539 | //------------------------------------------------- |
540 | 540 | // sn76496_config psg_intf |
541 | 541 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
551 | 551 | * Sound interface |
552 | 552 | * |
553 | 553 | *************************************/ |
554 | ||
555 | ||
554 | ||
555 | ||
556 | 556 | //------------------------------------------------- |
557 | 557 | // sn76496_config psg_intf |
558 | 558 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
252 | 252 | DECLARE_WRITE8_MEMBER(tms9901_interrupt); |
253 | 253 | |
254 | 254 | DECLARE_WRITE_LINE_MEMBER( clock_out ); |
255 | virtual void machine_start(); | |
255 | virtual void machine_start(); | |
256 | 256 | virtual void machine_reset(); |
257 | 257 | |
258 | 258 | // Some values to keep |
r17959 | r17960 | |
---|---|---|
17 | 17 | #include "cpu/mips/r3000.h" |
18 | 18 | |
19 | 19 | |
20 | struct ip6_regs_t | |
20 | struct ip6_regs_t | |
21 | 21 | { |
22 | 22 | UINT16 unknown_half_0; |
23 | 23 | UINT8 unknown_byte_0; |
r17959 | r17960 | |
---|---|---|
226 | 226 | NULL |
227 | 227 | }; |
228 | 228 | |
229 | const dl1416_interface aim65_ds1_intf = | |
229 | const dl1416_interface aim65_ds1_intf = | |
230 | 230 | { |
231 | 231 | aim65_update_ds1 |
232 | 232 | }; |
233 | 233 | |
234 | const dl1416_interface aim65_ds2_intf = | |
234 | const dl1416_interface aim65_ds2_intf = | |
235 | 235 | { |
236 | 236 | aim65_update_ds2 |
237 | 237 | }; |
238 | 238 | |
239 | const dl1416_interface aim65_ds3_intf = | |
239 | const dl1416_interface aim65_ds3_intf = | |
240 | 240 | { |
241 | 241 | aim65_update_ds3 |
242 | 242 | }; |
243 | 243 | |
244 | const dl1416_interface aim65_ds4_intf = | |
244 | const dl1416_interface aim65_ds4_intf = | |
245 | 245 | { |
246 | 246 | aim65_update_ds4 |
247 | 247 | }; |
248 | 248 | |
249 | const dl1416_interface aim65_ds5_intf = | |
249 | const dl1416_interface aim65_ds5_intf = | |
250 | 250 | { |
251 | 251 | aim65_update_ds5 |
252 | 252 | }; |
r17959 | r17960 | |
---|---|---|
463 | 463 | PA2 |
464 | 464 | PA3 |
465 | 465 | PA4 |
466 | PA5 | |
466 | PA5 LITE PEN (FIRE) | |
467 | 467 | PA6 |
468 | 468 | PA7 SERIAL ATN OUT |
469 | 469 | |
r17959 | r17960 | |
550 | 550 | |
551 | 551 | // joystick |
552 | 552 | UINT8 joy = m_joy1->joy_r(); |
553 | ||
553 | ||
554 | 554 | data &= BIT(joy, 3) << 7; |
555 | 555 | |
556 | 556 | return data; |
r17959 | r17960 | |
881 | 881 | //************************************************************************** |
882 | 882 | |
883 | 883 | // YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS |
884 | COMP( 1980, vic1001, 0, 0, ntsc, vic1001, driver_device, 0, "Commodore Business Machines", "VIC-1001 (Japan)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
885 | COMP( 1981, vic20, vic1001, 0, ntsc, vic20, driver_device, 0, "Commodore Business Machines", "VIC-20 (NTSC)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
886 | COMP( 1981, vic20p, vic1001, 0, pal, vic20, driver_device, 0, "Commodore Business Machines", "VIC-20 / VC-20 (PAL)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
887 | COMP( 1981, vic20s, vic1001, 0, pal, vic20s, driver_device, 0, "Commodore Business Machines", "VIC-20 (Sweden/Finland)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
884 | COMP( 1980, vic1001, 0, 0, ntsc, vic1001, driver_device, 0, "Commodore Business Machines", "VIC-1001 (Japan)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
885 | COMP( 1981, vic20, vic1001, 0, ntsc, vic20, driver_device, 0, "Commodore Business Machines", "VIC-20 (NTSC)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
886 | COMP( 1981, vic20p, vic1001, 0, pal, vic20, driver_device, 0, "Commodore Business Machines", "VIC-20 / VC-20 (PAL)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) | |
887 | COMP( 1981, vic20s, vic1001, 0, pal, vic20s, driver_device, 0, "Commodore Business Machines", "VIC-20 (Sweden/Finland)", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE ) |
r17959 | r17960 | |
---|---|---|
35 | 35 | : driver_device(mconfig, type, tag), |
36 | 36 | m_sn(*this, "sn1") |
37 | 37 | { } |
38 | ||
38 | ||
39 | 39 | optional_device<sn76489a_new_device> m_sn; |
40 | 40 | UINT16 m_cursor_addr; |
41 | 41 | UINT16 m_cursor_raster; |
r17959 | r17960 | |
1060 | 1060 | * Sound interface |
1061 | 1061 | * |
1062 | 1062 | *************************************/ |
1063 | ||
1064 | ||
1063 | ||
1064 | ||
1065 | 1065 | //------------------------------------------------- |
1066 | 1066 | // sn76496_config psg_intf |
1067 | 1067 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
57 | 57 | #include "machine/scsihd.h" |
58 | 58 | #include "machine/wd33c93.h" |
59 | 59 | |
60 | struct RTC_t | |
60 | struct RTC_t | |
61 | 61 | { |
62 | 62 | UINT8 nRegs[0x80]; |
63 | 63 | UINT8 nUserRAM[0x200]; |
64 | 64 | UINT8 nRAM[0x800]; |
65 | 65 | }; |
66 | 66 | |
67 | struct HPC3_t | |
67 | struct HPC3_t | |
68 | 68 | { |
69 | 69 | UINT32 nenetr_nbdp; |
70 | 70 | UINT32 nenetr_cbp; |
r17959 | r17960 | |
75 | 75 | UINT32 nSCSI0DMACtrl; |
76 | 76 | }; |
77 | 77 | |
78 | struct HAL2_t | |
78 | struct HAL2_t | |
79 | 79 | { |
80 | 80 | UINT32 nIAR; |
81 | 81 | UINT32 nIDR[4]; |
82 | 82 | }; |
83 | 83 | |
84 | struct PBUS_DMA_t | |
84 | struct PBUS_DMA_t | |
85 | 85 | { |
86 | 86 | UINT8 nActive; |
87 | 87 | UINT32 nCurPtr; |
r17959 | r17960 | |
---|---|---|
171 | 171 | |
172 | 172 | /* |
173 | 173 | |
174 | ||
174 | TODO: | |
175 | 175 | |
176 | - connect to PLA | |
177 | - clean up ROMs | |
178 | - wire up function ROM softlist | |
179 | - remove banking code from machine/c128.h | |
180 | - inherit from c64_state and use common members from there | |
181 | - clean up inputs | |
182 | - fix fast serial | |
176 | - connect to PLA | |
177 | - clean up ROMs | |
178 | - wire up function ROM softlist | |
179 | - remove banking code from machine/c128.h | |
180 | - inherit from c64_state and use common members from there | |
181 | - clean up inputs | |
182 | - fix fast serial | |
183 | 183 | |
184 | 184 | */ |
185 | 185 | |
r17959 | r17960 | |
281 | 281 | UINT8 c128_state::read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io) |
282 | 282 | { |
283 | 283 | int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1; |
284 | int sden = 1, dir = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1, | |
284 | int sden = 1, dir = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1, | |
285 | 285 | from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1; |
286 | 286 | int io1 = 1, io2 = 1; |
287 | 287 | |
288 | 288 | offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3, &cas0, &cas1); |
289 | 289 | |
290 | 290 | bankswitch_pla(offset, ta, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0, |
291 | &sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, | |
291 | &sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, | |
292 | 292 | &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb); |
293 | 293 | |
294 | 294 | UINT8 data = 0xff; |
r17959 | r17960 | |
400 | 400 | void c128_state::write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io) |
401 | 401 | { |
402 | 402 | int rw = 0, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1; |
403 | int sden = 1, dir = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1, | |
403 | int sden = 1, dir = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1, | |
404 | 404 | from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1; |
405 | 405 | int io1 = 1, io2 = 1; |
406 | 406 | |
407 | 407 | offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3, &cas0, &cas1); |
408 | 408 | |
409 | 409 | bankswitch_pla(offset, ta, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0, |
410 | &sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, | |
410 | &sden, &dir, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, | |
411 | 411 | &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb); |
412 | 412 | |
413 | 413 | if (!casenb && !dwe) |
r17959 | r17960 | |
483 | 483 | { |
484 | 484 | int ba = 1, aec = 1, z80io = 1; |
485 | 485 | offs_t vma = 0; |
486 | ||
486 | ||
487 | 487 | write_memory(space, offset, vma, data, ba, aec, z80io); |
488 | 488 | } |
489 | 489 | |
r17959 | r17960 | |
491 | 491 | { |
492 | 492 | int ba = 1, aec = 1, z80io = 0; |
493 | 493 | offs_t vma = 0; |
494 | ||
494 | ||
495 | 495 | return read_memory(space, offset, vma, ba, aec, z80io); |
496 | 496 | } |
497 | 497 | |
r17959 | r17960 | |
499 | 499 | { |
500 | 500 | int ba = 1, aec = 1, z80io = 0; |
501 | 501 | offs_t vma = 0; |
502 | ||
502 | ||
503 | 503 | write_memory(space, offset, vma, data, ba, aec, z80io); |
504 | 504 | } |
505 | 505 | |
r17959 | r17960 | |
507 | 507 | { |
508 | 508 | int ba = 1, aec = 1, z80io = 1; |
509 | 509 | offs_t vma = 0; |
510 | ||
510 | ||
511 | 511 | return read_memory(space, vma, offset, ba, aec, z80io); |
512 | 512 | } |
513 | 513 | |
r17959 | r17960 | |
515 | 515 | { |
516 | 516 | int ba = 1, aec = 1, z80io = 1; |
517 | 517 | offs_t vma = 0; |
518 | ||
518 | ||
519 | 519 | write_memory(space, offset, vma, data, ba, aec, z80io); |
520 | 520 | } |
521 | 521 | |
r17959 | r17960 | |
523 | 523 | { |
524 | 524 | int ba = 0, aec = 0, z80io = 1; |
525 | 525 | offs_t vma = 0; |
526 | ||
526 | ||
527 | 527 | return read_memory(space, offset, vma, ba, aec, z80io); |
528 | 528 | } |
529 | 529 | |
r17959 | r17960 | |
969 | 969 | READ8_MEMBER( c128_state::sid_potx_r ) |
970 | 970 | { |
971 | 971 | UINT8 cia1_pa = mos6526_pa_r(m_cia1, 0); |
972 | ||
972 | ||
973 | 973 | int sela = BIT(cia1_pa, 6); |
974 | 974 | int selb = BIT(cia1_pa, 7); |
975 | 975 | |
r17959 | r17960 | |
984 | 984 | READ8_MEMBER( c128_state::sid_poty_r ) |
985 | 985 | { |
986 | 986 | UINT8 cia1_pa = mos6526_pa_r(m_cia1, 0); |
987 | ||
987 | ||
988 | 988 | int sela = BIT(cia1_pa, 6); |
989 | 989 | int selb = BIT(cia1_pa, 7); |
990 | 990 |
r17959 | r17960 | |
---|---|---|
25 | 25 | UINT8 osc_clk; /* Only used by data fetchers 5,6, and 7 */ |
26 | 26 | }; |
27 | 27 | |
28 | struct dpc_t | |
28 | struct dpc_t | |
29 | 29 | { |
30 | 30 | df_t df[8]; |
31 | 31 | UINT8 movamt; |
r17959 | r17960 | |
---|---|---|
8 | 8 | and http://www.vr32.de/modules/dokuwiki/doku.php? |
9 | 9 | |
10 | 10 | TODO: |
11 | ||
11 | - 3dtetris: missing gfxs on gameplay (writes to framebuffer) | |
12 | 12 | - boundh: game is way too fast |
13 | 13 | - galactic: ball goes out of bounds sometimes? |
14 | ||
14 | - golf: missing gfxs on gameplay (writes to framebuffer) | |
15 | 15 | - marioten: title screen logo is misplaced if Mario completes his animation |
16 | 16 | - nesterfb: once that you hit the pins, animation phase takes a while to start |
17 | 17 | - redalarm: gameplay doesn't work |
r17959 | r17960 | |
19 | 19 | - spaceinv: missing shots |
20 | 20 | - telerobo: crashes if you die |
21 | 21 | - telerobo: hangs after winning first match; |
22 | | |
22 | - vlab: doesn't boot (irq issue?) | |
23 | 23 | - wariolnd: brightness gets suddently darker during intro. |
24 | 24 | \ |
25 | 25 | ****************************************************************************/ |
r17959 | r17960 | |
699 | 699 | if(b > 0xff) { b = 0xff; } |
700 | 700 | if(c > 0xff) { c = 0xff; } |
701 | 701 | |
702 | // | |
702 | // popmessage("%02x %02x %02x %02x",m_vip_regs.BRTA,m_vip_regs.BRTB,m_vip_regs.BRTC,m_vip_regs.REST); | |
703 | 703 | palette_set_color_rgb(machine(), 1, a,0,0); |
704 | 704 | palette_set_color_rgb(machine(), 2, b,0,0); |
705 | 705 | palette_set_color_rgb(machine(), 3, c,0,0); |
r17959 | r17960 | |
716 | 716 | logerror("Error reading INTCLR\n"); |
717 | 717 | break; |
718 | 718 | /* |
719 | ---- -x-- ---- ---- LOCK (status column table address (CTA) lock) | |
720 | ---- --x- ---- ---- SYNCE (status of sync signal enable) | |
721 | ---- ---x ---- ---- RE (status of memory refresh cycle) | |
722 | ---- ---- x--- ---- FCLK | |
719 | ---- -x-- ---- ---- LOCK (status column table address (CTA) lock) | |
720 | ---- --x- ---- ---- SYNCE (status of sync signal enable) | |
721 | ---- ---x ---- ---- RE (status of memory refresh cycle) | |
722 | ---- ---- x--- ---- FCLK | |
723 | 723 | ---- ---- -x-- ---- SCANRDY (active low) |
724 | ---- ---- --xx xx-- DPBSY (current framebuffer displayed) | |
725 | ---- ---- --10 00-- RFB1 | |
726 | ---- ---- --01 00-- LFB1 | |
727 | ---- ---- --00 10-- RFB0 | |
728 | ---- ---- --00 01-- LFB0 | |
729 | ---- ---- ---- --x- DISP | |
724 | ---- ---- --xx xx-- DPBSY (current framebuffer displayed) | |
725 | ---- ---- --10 00-- RFB1 | |
726 | ---- ---- --01 00-- LFB1 | |
727 | ---- ---- --00 10-- RFB0 | |
728 | ---- ---- --00 01-- LFB0 | |
729 | ---- ---- ---- --x- DISP | |
730 | 730 | */ |
731 | 731 | case 0x20: //DPSTTS |
732 | 732 | { |
r17959 | r17960 | |
767 | 767 | case 0x40: //XPSTTS, piXel Processor STaTuS |
768 | 768 | { |
769 | 769 | /* |
770 | x--- ---- ---- ---- SBOUT | |
771 | ---x xxxx ---- ---- SBCOUNT | |
772 | ---- ---- ---x ---- OVERTIME (process overflow) | |
770 | x--- ---- ---- ---- SBOUT | |
771 | ---x xxxx ---- ---- SBCOUNT | |
772 | ---- ---- ---x ---- OVERTIME (process overflow) | |
773 | 773 | ---- ---- ---- x--- XPBSY1 (second framebuffer busy flag) |
774 | 774 | ---- ---- ---- -x-- XPBSY0 (first framebfuffer busy flag) |
775 | 775 | ---- ---- ---- --x- XPEN (starts drawing at beginning of game frame) |
r17959 | r17960 | |
862 | 862 | logerror("Error writing DPSTTS\n"); |
863 | 863 | break; |
864 | 864 | /* |
865 | ---- -x-- ---- ---- LOCK (status column table address (CTA) lock) | |
866 | ---- --x- ---- ---- SYNCE (status of sync signal enable) | |
867 | ---- ---x ---- ---- RE (status of memory refresh cycle) | |
868 | ---- ---- ---- --x- DISP | |
869 | ---- ---- ---- ---x DPRST (Resets the VIP internal counter) | |
865 | ---- -x-- ---- ---- LOCK (status column table address (CTA) lock) | |
866 | ---- --x- ---- ---- SYNCE (status of sync signal enable) | |
867 | ---- ---x ---- ---- RE (status of memory refresh cycle) | |
868 | ---- ---- ---- --x- DISP | |
869 | ---- ---- ---- ---x DPRST (Resets the VIP internal counter) | |
870 | 870 | */ |
871 | 871 | case 0x22: //DPCTRL |
872 | 872 | m_vip_regs.DPCTRL = data & 0x0702; |
r17959 | r17960 | |
1085 | 1085 | AM_RANGE( 0x02000000, 0x0200002b ) AM_MIRROR(0x0ffff00) AM_READWRITE(io_r, io_w) // Hardware control registers mask 0xff |
1086 | 1086 | //AM_RANGE( 0x04000000, 0x04ffffff ) // Expansion area |
1087 | 1087 | AM_RANGE( 0x05000000, 0x0500ffff ) AM_MIRROR(0x0ff0000) AM_RAM AM_SHARE("wram")// Main RAM - 64K mask 0xffff |
1088 | // | |
1088 | // AM_RANGE( 0x06000000, 0x06003fff ) AM_RAM AM_SHARE("nvram") // Cart RAM - 8K NVRAM | |
1089 | 1089 | AM_RANGE( 0x07000000, 0x071fffff ) AM_MIRROR(0x0e00000) AM_ROM AM_REGION("cartridge", 0) /* ROM */ |
1090 | 1090 | ADDRESS_MAP_END |
1091 | 1091 | |
r17959 | r17960 | |
1157 | 1157 | /* add a hook for battery save */ |
1158 | 1158 | machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(vboy_machine_stop),&machine())); |
1159 | 1159 | |
1160 | // | |
1160 | // m_vboy_sram = auto_alloc_array(machine(), UINT32, 0x10000/4); | |
1161 | 1161 | } |
1162 | 1162 | |
1163 | 1163 | void vboy_state::machine_reset() |
r17959 | r17960 | |
---|---|---|
44 | 44 | }; |
45 | 45 | |
46 | 46 | // CD-ROM / DMA control registers |
47 | struct neocd_ctrl_t | |
47 | struct neocd_ctrl_t | |
48 | 48 | { |
49 | 49 | UINT8 area_sel; |
50 | 50 | UINT8 pcm_bank_sel; |
r17959 | r17960 | |
91 | 91 | DECLARE_MACHINE_START(neocd); |
92 | 92 | DECLARE_MACHINE_START(neogeo); |
93 | 93 | DECLARE_MACHINE_RESET(neogeo); |
94 | ||
94 | ||
95 | 95 | }; |
96 | 96 | |
97 | 97 |
r17959 | r17960 | |
---|---|---|
19 | 19 | #include "machine/psxcd.h" |
20 | 20 | #include "machine/psxcard.h" |
21 | 21 | |
22 | struct pad_t | |
22 | struct pad_t | |
23 | 23 | { |
24 | 24 | UINT8 n_shiftin; |
25 | 25 | UINT8 n_shiftout; |
r17959 | r17960 | |
---|---|---|
36 | 36 | |
37 | 37 | #define MAX_PS_TIMERS 3 |
38 | 38 | |
39 | struct ps_ftlb_regs_t | |
39 | struct ps_ftlb_regs_t | |
40 | 40 | { |
41 | 41 | UINT32 control; |
42 | 42 | UINT32 stat; |
r17959 | r17960 | |
47 | 47 | UINT32 serial; |
48 | 48 | }; |
49 | 49 | |
50 | struct ps_intc_regs_t | |
50 | struct ps_intc_regs_t | |
51 | 51 | { |
52 | 52 | UINT32 hold; |
53 | 53 | UINT32 status; |
r17959 | r17960 | |
55 | 55 | UINT32 mask; |
56 | 56 | }; |
57 | 57 | |
58 | struct ps_timer_t | |
58 | struct ps_timer_t | |
59 | 59 | { |
60 | 60 | UINT32 period; |
61 | 61 | UINT32 count; |
r17959 | r17960 | |
63 | 63 | emu_timer *timer; |
64 | 64 | }; |
65 | 65 | |
66 | struct ps_timer_regs_t | |
66 | struct ps_timer_regs_t | |
67 | 67 | { |
68 | 68 | ps_timer_t timer[MAX_PS_TIMERS]; |
69 | 69 | }; |
70 | 70 | |
71 | struct ps_clock_regs_t | |
71 | struct ps_clock_regs_t | |
72 | 72 | { |
73 | 73 | UINT32 mode; |
74 | 74 | UINT32 control; |
r17959 | r17960 | |
76 | 76 | |
77 | 77 | #define PS_CLOCK_STEADY 0x10 |
78 | 78 | |
79 | struct ps_rtc_regs_t | |
79 | struct ps_rtc_regs_t | |
80 | 80 | { |
81 | 81 | UINT32 mode; |
82 | 82 | UINT32 control; |
r17959 | r17960 | |
---|---|---|
24 | 24 | } |
25 | 25 | } |
26 | 26 | |
27 | struct lcd_spi_t | |
27 | struct lcd_spi_t | |
28 | 28 | { |
29 | 29 | int l1; |
30 | 30 | int data; |
r17959 | r17960 | |
---|---|---|
15 | 15 | public: |
16 | 16 | pv1000_sound_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); |
17 | 17 | protected: |
18 | // device-level overrides | |
18 | // device-level overrides | |
19 | 19 | virtual void device_config_complete(); |
20 | 20 | virtual void device_start(); |
21 | 21 |
r17959 | r17960 | |
---|---|---|
91 | 91 | output_set_digit_value(4 + digit, data); |
92 | 92 | } |
93 | 93 | |
94 | const dl1416_interface sitcom_ds0_intf = | |
94 | const dl1416_interface sitcom_ds0_intf = | |
95 | 95 | { |
96 | 96 | sitcom_update_ds0 |
97 | 97 | }; |
98 | 98 | |
99 | const dl1416_interface sitcom_ds1_intf = | |
99 | const dl1416_interface sitcom_ds1_intf = | |
100 | 100 | { |
101 | 101 | sitcom_update_ds1 |
102 | 102 | }; |
r17959 | r17960 | |
---|---|---|
347 | 347 | { FUNC(pcw16_flash1_bank_handler3_w) } |
348 | 348 | }; |
349 | 349 | |
350 | enum PCW16_RAM_TYPE | |
350 | enum PCW16_RAM_TYPE | |
351 | 351 | { |
352 | 352 | /* rom which is really first block of flash0 */ |
353 | 353 | PCW16_MEM_ROM, |
r17959 | r17960 | |
---|---|---|
45 | 45 | , |
46 | 46 | m_p_ram(*this, "p_ram"){ } |
47 | 47 | |
48 | ||
48 | ||
49 | 49 | static const floppy_format_type floppy_formats[]; |
50 | ||
50 | ||
51 | 51 | required_device<cpu_device> m_maincpu; |
52 | 52 | required_device<generic_terminal_device> m_terminal; |
53 | 53 | required_device<device_t> m_duart; |
r17959 | r17960 | |
117 | 117 | if(con) |
118 | 118 | floppy = con->get_device(); |
119 | 119 | break; |
120 | } | |
120 | } | |
121 | 121 | } |
122 | 122 | if (floppy) floppy->ss_w(BIT(data,3) ? 0 : 1); |
123 | state->m_fdc->set_floppy(floppy); | |
123 | state->m_fdc->set_floppy(floppy); | |
124 | 124 | } |
125 | 125 | |
126 | 126 | WRITE8_MEMBER( ht68k_state::kbd_put ) |
r17959 | r17960 | |
162 | 162 | MCFG_FLOPPY_DRIVE_ADD("fd0", ht68k_floppies, "525dd", 0, ht68k_state::floppy_formats) |
163 | 163 | MCFG_FLOPPY_DRIVE_ADD("fd1", ht68k_floppies, "525dd", 0, ht68k_state::floppy_formats) |
164 | 164 | MCFG_FLOPPY_DRIVE_ADD("fd2", ht68k_floppies, "525dd", 0, ht68k_state::floppy_formats) |
165 | MCFG_FLOPPY_DRIVE_ADD("fd3", ht68k_floppies, "525dd", 0, ht68k_state::floppy_formats) | |
165 | MCFG_FLOPPY_DRIVE_ADD("fd3", ht68k_floppies, "525dd", 0, ht68k_state::floppy_formats) | |
166 | 166 | MACHINE_CONFIG_END |
167 | 167 | |
168 | 168 | /* ROM definition */ |
r17959 | r17960 | |
---|---|---|
321 | 321 | * Sound interface |
322 | 322 | * |
323 | 323 | *************************************/ |
324 | ||
325 | ||
324 | ||
325 | ||
326 | 326 | //------------------------------------------------- |
327 | 327 | // sn76496_config psg_intf |
328 | 328 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
1020 | 1020 | memcmp (db+0x22, "APOLLO", 6) == 0 && |
1021 | 1021 | omti8621_get_sector(machine().device(APOLLO_WDC_TAG), sector1, db, sizeof(db), 0) == sizeof(db)) |
1022 | 1022 | { |
1023 | // | |
1023 | // MLOG2(("machine_reset_dn3500: node ID is %06X (from ROM)", node_id)); | |
1024 | 1024 | |
1025 | 1025 | // set node_id from UID of logical volume 1 of logical unit 0 |
1026 | 1026 | node_id = (((db[0x49] << 8) | db[0x4a]) << 8) | db[0x4b]; |
1027 | 1027 | |
1028 | // | |
1028 | // MLOG2(("machine_reset_dn3500: node ID is %06X (from disk)", node_id)); | |
1029 | 1029 | } |
1030 | 1030 | } |
1031 | 1031 |
r17959 | r17960 | |
---|---|---|
18 | 18 | |
19 | 19 | /* Components */ |
20 | 20 | |
21 | struct hd63701y0_t | |
21 | struct hd63701y0_t | |
22 | 22 | { |
23 | 23 | UINT8 data[8]; |
24 | 24 | UINT8 P1DDR; |
r17959 | r17960 | |
57 | 57 | UINT8 P6CSR; |
58 | 58 | }; |
59 | 59 | |
60 | struct rvoicepc_t | |
60 | struct rvoicepc_t | |
61 | 61 | { |
62 | 62 | UINT8 data[8]; |
63 | 63 | UINT8 port1; |
r17959 | r17960 | |
---|---|---|
626 | 626 | // GATL GAT Length |
627 | 627 | // GATM GAT Mask |
628 | 628 | // DDGA Disk Directory Granule Allocation |
629 | struct PDRIVE | |
629 | struct PDRIVE | |
630 | 630 | { |
631 | 631 | UINT8 DDSL; // Disk Directory Start Lump (lump number of GAT) |
632 | 632 | UINT8 GATL; // # of bytes used in the Granule Allocation Table sector |
r17959 | r17960 | |
---|---|---|
258 | 258 | WRITE_LINE_MEMBER( mapper_ready ); |
259 | 259 | |
260 | 260 | DECLARE_DRIVER_INIT(geneve); |
261 | virtual void machine_start(); | |
261 | virtual void machine_start(); | |
262 | 262 | virtual void machine_reset(); |
263 | ||
263 | ||
264 | 264 | void set_tms9901_INT2_from_v9938(v99x8_device &vdp, int state); |
265 | 265 | |
266 | 266 | line_state m_inta; |
r17959 | r17960 | |
---|---|---|
271 | 271 | #define UPD1990A_TAG "upd1990a" |
272 | 272 | #define I8251_TAG "i8251" |
273 | 273 | |
274 | struct crtc_t | |
274 | struct crtc_t | |
275 | 275 | { |
276 | 276 | UINT8 cmd,param_count,cursor_on,status,irq_mask; |
277 | 277 | UINT8 param[8][5]; |
278 | 278 | UINT8 inverse; |
279 | 279 | }; |
280 | 280 | |
281 | struct mouse_t | |
281 | struct mouse_t | |
282 | 282 | { |
283 | 283 | UINT8 phase; |
284 | 284 | UINT8 x,y; |
r17959 | r17960 | |
450 | 450 | public: |
451 | 451 | DECLARE_MACHINE_RESET(pc8801_clock_speed); |
452 | 452 | DECLARE_MACHINE_RESET(pc8801_dic); |
453 | DECLARE_MACHINE_RESET(pc8801_cdrom); | |
453 | DECLARE_MACHINE_RESET(pc8801_cdrom); | |
454 | 454 | }; |
455 | 455 | |
456 | 456 |
r17959 | r17960 | |
---|---|---|
319 | 319 | |
320 | 320 | |
321 | 321 | /*************************************************************************** |
322 | | |
322 | SOUND INTERFACE | |
323 | 323 | **************************************************************************/ |
324 | ||
325 | ||
324 | ||
325 | ||
326 | 326 | //------------------------------------------------- |
327 | 327 | // sn76496_config psg_intf |
328 | 328 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
149 | 149 | SLOT_INTERFACE("cirrus", CIRRUS) |
150 | 150 | SLOT_INTERFACE_END |
151 | 151 | |
152 | static const ide_config ide_intf = | |
152 | static const ide_config ide_intf = | |
153 | 153 | { |
154 | bebox_ide_interrupt, | |
155 | NULL, | |
154 | bebox_ide_interrupt, | |
155 | NULL, | |
156 | 156 | 0 |
157 | 157 | }; |
158 | 158 |
r17959 | r17960 | |
---|---|---|
576 | 576 | * write command -> 0x05 (normal, normal, /RTS is 1, normal, normal, recieve ON, /DTR is 0, transmit off) |
577 | 577 | * read SYSTAT B (and xor with 0xe), expect d7 to be SET or jump to error |
578 | 578 | * after this it does something and waits for an rxrdy interrupt |
579 | ||
579 | ||
580 | 580 | shows the results of: |
581 | 581 | * ACTS (/CTS) ? ? ? ? ? ? ? |
582 | 582 | * d7 d6 d5 d4 d3 d2 d1 d0 |
r17959 | r17960 | |
---|---|---|
351 | 351 | * Sound interface |
352 | 352 | * |
353 | 353 | *************************************/ |
354 | ||
355 | ||
354 | ||
355 | ||
356 | 356 | //------------------------------------------------- |
357 | 357 | // sn76496_config psg_intf |
358 | 358 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
79 | 79 | |
80 | 80 | static ADDRESS_MAP_START( pcfx_mem, AS_PROGRAM, 32, pcfx_state ) |
81 | 81 | AM_RANGE( 0x00000000, 0x001FFFFF ) AM_RAM /* RAM */ |
82 | // | |
82 | // AM_RANGE( 0x80000000, 0x807FFFFF ) AM_READWRITE8(extio_r,extio_w,0xffffffff) /* EXTIO */ | |
83 | 83 | AM_RANGE( 0xE0000000, 0xE7FFFFFF ) AM_NOP /* BackUp RAM */ |
84 | 84 | AM_RANGE( 0xE8000000, 0xE9FFFFFF ) AM_NOP /* Extended BackUp RAM */ |
85 | 85 | AM_RANGE( 0xF8000000, 0xF8000007 ) AM_NOP /* PIO */ |
r17959 | r17960 | |
95 | 95 | { |
96 | 96 | // status |
97 | 97 | /* |
98 | ---- x--- | |
99 | ---- ---x incoming data state (0=available) | |
100 | */ | |
98 | ---- x--- | |
99 | ---- ---x incoming data state (0=available) | |
100 | */ | |
101 | 101 | res = m_pad.status[port_type]; |
102 | 102 | //printf("STATUS %d\n",port_type); |
103 | 103 | } |
r17959 | r17960 | |
126 | 126 | state->m_pad.status[param] |= 8; |
127 | 127 | state->m_pad.ctrl[param] &= ~1; // ack TX line |
128 | 128 | // TODO: pad IRQ |
129 | // | |
129 | // state->set_irq_line(11, 1); | |
130 | 130 | } |
131 | 131 | |
132 | 132 | WRITE16_MEMBER( pcfx_state::pad_w ) |
r17959 | r17960 | |
137 | 137 | { |
138 | 138 | // control |
139 | 139 | /* |
140 | ---- -x-- receiver enable | |
141 | ---- --x- enable multi-tap | |
142 | ---- ---x enable send (0->1 transition) | |
143 | */ | |
140 | ---- -x-- receiver enable | |
141 | ---- --x- enable multi-tap | |
142 | ---- ---x enable send (0->1 transition) | |
143 | */ | |
144 | 144 | if(data & 1 && (!(m_pad.ctrl[port_type] & 1))) |
145 | 145 | { |
146 | 146 | machine().scheduler().timer_set(attotime::from_msec(1), FUNC(pad_func), port_type); // TODO: time |
r17959 | r17960 | |
168 | 168 | AM_RANGE( 0x00000C80, 0x00000C83 ) AM_NOP |
169 | 169 | AM_RANGE( 0x00000E00, 0x00000EFF ) AM_READWRITE16( irq_read, irq_write, 0xffff ) /* Interrupt controller */ |
170 | 170 | AM_RANGE( 0x00000F00, 0x00000FFF ) AM_NOP |
171 | // | |
171 | // AM_RANGE( 0x00600000, 0x006FFFFF ) AM_READ(scsi_ctrl_r) | |
172 | 172 | AM_RANGE( 0x00780000, 0x007FFFFF ) AM_ROM AM_REGION("scsi_rom", 0 ) |
173 | 173 | AM_RANGE( 0x80500000, 0x805000FF ) AM_NOP /* HuC6273 */ |
174 | 174 | ADDRESS_MAP_END |
r17959 | r17960 | |
176 | 176 | |
177 | 177 | static INPUT_PORTS_START( pcfx ) |
178 | 178 | /* |
179 | xxxx ---- ---- ---- ID (0xf = 6 button pad, 0xe = tap, 0xd = ?) | |
180 | */ | |
179 | xxxx ---- ---- ---- ID (0xf = 6 button pad, 0xe = tap, 0xd = ?) | |
180 | */ | |
181 | 181 | PORT_START("P1") |
182 | 182 | PORT_BIT( 0xf0000000, IP_ACTIVE_LOW, IPT_UNKNOWN ) // ID |
183 | 183 | PORT_DIPNAME( 0x01000000, 0x01000000, "1" ) |
r17959 | r17960 | |
---|---|---|
31 | 31 | } |
32 | 32 | } |
33 | 33 | |
34 | struct smc_t | |
34 | struct smc_t | |
35 | 35 | { |
36 | 36 | int add_latch; |
37 | 37 | int cmd_latch; |
r17959 | r17960 | |
---|---|---|
342 | 342 | MCFG_RAM_EXTRA_OPTIONS("1M") |
343 | 343 | MACHINE_CONFIG_END |
344 | 344 | |
345 | const sst39vfx_config cybyko_sst39vfx_intf = | |
345 | const sst39vfx_config cybyko_sst39vfx_intf = | |
346 | 346 | { |
347 | 347 | 16, ENDIANNESS_BIG |
348 | 348 | }; |
r17959 | r17960 | |
---|---|---|
2 | 2 | |
3 | 3 | TODO: |
4 | 4 | |
5 | - floating bus writes to peripheral registers in m6502.c | |
6 | - sort out kernals between PAL/NTSC | |
5 | - floating bus writes to peripheral registers in m6502.c | |
6 | - sort out kernals between PAL/NTSC | |
7 | 7 | - tsuit215 test failures |
8 | 8 | - IRQ (WRONG $DC0D) |
9 | 9 | - NMI (WRONG $DD0D) |
r17959 | r17960 | |
428 | 428 | READ8_MEMBER( c64_state::sid_potx_r ) |
429 | 429 | { |
430 | 430 | UINT8 cia1_pa = mos6526_pa_r(m_cia1, 0); |
431 | ||
431 | ||
432 | 432 | int sela = BIT(cia1_pa, 6); |
433 | 433 | int selb = BIT(cia1_pa, 7); |
434 | 434 | |
r17959 | r17960 | |
443 | 443 | READ8_MEMBER( c64_state::sid_poty_r ) |
444 | 444 | { |
445 | 445 | UINT8 cia1_pa = mos6526_pa_r(m_cia1, 0); |
446 | ||
446 | ||
447 | 447 | int sela = BIT(cia1_pa, 6); |
448 | 448 | int selb = BIT(cia1_pa, 7); |
449 | 449 | |
r17959 | r17960 | |
646 | 646 | P0 1 |
647 | 647 | P1 1 |
648 | 648 | P2 1 |
649 | P3 | |
649 | P3 | |
650 | 650 | P4 CASS SENS |
651 | P5 | |
651 | P5 | |
652 | 652 | |
653 | 653 | */ |
654 | 654 | |
r17959 | r17960 | |
710 | 710 | P0 1 |
711 | 711 | P1 1 |
712 | 712 | P2 1 |
713 | P3 | |
714 | P4 | |
715 | P5 | |
713 | P3 | |
714 | P4 | |
715 | P5 | |
716 | 716 | |
717 | 717 | */ |
718 | 718 | |
r17959 | r17960 | |
764 | 764 | P0 1 |
765 | 765 | P1 1 |
766 | 766 | P2 1 |
767 | P3 | |
768 | P4 | |
769 | P5 | |
767 | P3 | |
768 | P4 | |
769 | P5 | |
770 | 770 | |
771 | 771 | */ |
772 | 772 | |
r17959 | r17960 | |
1489 | 1489 | //************************************************************************** |
1490 | 1490 | |
1491 | 1491 | // YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS |
1492 | COMP( 1982, c64n, 0, 0, ntsc, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64 (NTSC)", GAME_SUPPORTS_SAVE ) | |
1493 | COMP( 1982, c64j, c64n, 0, ntsc, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64 (Japan)", GAME_SUPPORTS_SAVE ) | |
1494 | COMP( 1982, c64p, c64n, 0, pal, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64 (PAL)", GAME_SUPPORTS_SAVE ) | |
1495 | COMP( 1982, c64sw, c64n, 0, pal, c64sw, driver_device, 0, "Commodore Business Machines", "Commodore 64 / VIC-64S (Sweden/Finland)", GAME_SUPPORTS_SAVE ) | |
1496 | COMP( 1983, pet64, c64n, 0, pet64, c64, driver_device, 0, "Commodore Business Machines", "PET 64 / CBM 4064 (NTSC)", GAME_SUPPORTS_SAVE | GAME_WRONG_COLORS ) | |
1497 | COMP( 1983, edu64, c64n, 0, pet64, c64, driver_device, 0, "Commodore Business Machines", "Educator 64 (NTSC)", GAME_SUPPORTS_SAVE | GAME_WRONG_COLORS ) | |
1498 | COMP( 1984, sx64n, c64n, 0, ntsc_sx, c64, driver_device, 0, "Commodore Business Machines", "SX-64 / Executive 64 (NTSC)", GAME_SUPPORTS_SAVE ) | |
1499 | COMP( 1984, sx64p, c64n, 0, pal_sx, c64, driver_device, 0, "Commodore Business Machines", "SX-64 / Executive 64 (PAL)", GAME_SUPPORTS_SAVE ) | |
1500 | COMP( 1984, vip64, c64n, 0, pal_sx, c64sw, driver_device, 0, "Commodore Business Machines", "VIP-64 (Sweden/Finland)", GAME_SUPPORTS_SAVE ) | |
1501 | COMP( 1984, dx64, c64n, 0, ntsc_dx, c64, driver_device, 0, "Commodore Business Machines", "DX-64 (NTSC)", GAME_SUPPORTS_SAVE ) | |
1492 | COMP( 1982, c64n, 0, 0, ntsc, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64 (NTSC)", GAME_SUPPORTS_SAVE ) | |
1493 | COMP( 1982, c64j, c64n, 0, ntsc, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64 (Japan)", GAME_SUPPORTS_SAVE ) | |
1494 | COMP( 1982, c64p, c64n, 0, pal, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64 (PAL)", GAME_SUPPORTS_SAVE ) | |
1495 | COMP( 1982, c64sw, c64n, 0, pal, c64sw, driver_device, 0, "Commodore Business Machines", "Commodore 64 / VIC-64S (Sweden/Finland)", GAME_SUPPORTS_SAVE ) | |
1496 | COMP( 1983, pet64, c64n, 0, pet64, c64, driver_device, 0, "Commodore Business Machines", "PET 64 / CBM 4064 (NTSC)", GAME_SUPPORTS_SAVE | GAME_WRONG_COLORS ) | |
1497 | COMP( 1983, edu64, c64n, 0, pet64, c64, driver_device, 0, "Commodore Business Machines", "Educator 64 (NTSC)", GAME_SUPPORTS_SAVE | GAME_WRONG_COLORS ) | |
1498 | COMP( 1984, sx64n, c64n, 0, ntsc_sx, c64, driver_device, 0, "Commodore Business Machines", "SX-64 / Executive 64 (NTSC)", GAME_SUPPORTS_SAVE ) | |
1499 | COMP( 1984, sx64p, c64n, 0, pal_sx, c64, driver_device, 0, "Commodore Business Machines", "SX-64 / Executive 64 (PAL)", GAME_SUPPORTS_SAVE ) | |
1500 | COMP( 1984, vip64, c64n, 0, pal_sx, c64sw, driver_device, 0, "Commodore Business Machines", "VIP-64 (Sweden/Finland)", GAME_SUPPORTS_SAVE ) | |
1501 | COMP( 1984, dx64, c64n, 0, ntsc_dx, c64, driver_device, 0, "Commodore Business Machines", "DX-64 (NTSC)", GAME_SUPPORTS_SAVE ) | |
1502 | 1502 | //COMP(1983, clipper, c64, 0, c64pal, clipper, XXX_CLASS, c64pal, "PDC", "Clipper", GAME_NOT_WORKING) // C64 in a briefcase with 3" floppy, electroluminescent flat screen, thermal printer |
1503 | 1503 | //COMP(1983, tesa6240, c64, 0, c64pal, c64, XXX_CLASS, c64pal, "Tesa", "6240", GAME_NOT_WORKING) // modified SX64 with label printer |
1504 | COMP( 1986, c64cn, c64n, 0, ntsc_c, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64C (NTSC)", GAME_SUPPORTS_SAVE ) | |
1505 | COMP( 1986, c64cp, c64n, 0, pal_c, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64C (PAL)", GAME_SUPPORTS_SAVE ) | |
1506 | COMP( 1986, c64csw, c64n, 0, pal_c, c64sw, driver_device, 0, "Commodore Business Machines", "Commodore 64C (Sweden/Finland)", GAME_SUPPORTS_SAVE ) | |
1507 | COMP( 1986, c64g, c64n, 0, pal_c, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64G (PAL)", GAME_SUPPORTS_SAVE ) | |
1508 | CONS( 1990, c64gs, c64n, 0, pal_gs, c64gs, driver_device, 0, "Commodore Business Machines", "Commodore 64 Games System (PAL)", GAME_SUPPORTS_SAVE ) | |
1504 | COMP( 1986, c64cn, c64n, 0, ntsc_c, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64C (NTSC)", GAME_SUPPORTS_SAVE ) | |
1505 | COMP( 1986, c64cp, c64n, 0, pal_c, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64C (PAL)", GAME_SUPPORTS_SAVE ) | |
1506 | COMP( 1986, c64csw, c64n, 0, pal_c, c64sw, driver_device, 0, "Commodore Business Machines", "Commodore 64C (Sweden/Finland)", GAME_SUPPORTS_SAVE ) | |
1507 | COMP( 1986, c64g, c64n, 0, pal_c, c64, driver_device, 0, "Commodore Business Machines", "Commodore 64G (PAL)", GAME_SUPPORTS_SAVE ) | |
1508 | CONS( 1990, c64gs, c64n, 0, pal_gs, c64gs, driver_device, 0, "Commodore Business Machines", "Commodore 64 Games System (PAL)", GAME_SUPPORTS_SAVE ) |
r17959 | r17960 | |
---|---|---|
933 | 933 | * Sound interface |
934 | 934 | * |
935 | 935 | *************************************/ |
936 | ||
937 | ||
936 | ||
937 | ||
938 | 938 | //------------------------------------------------- |
939 | 939 | // sn76496_config psg_intf |
940 | 940 | //------------------------------------------------- |
r17959 | r17960 | |
---|---|---|
967 | 967 | |
968 | 968 | m_cpu = static_cast<tms9900_device*>(machine().device("maincpu")); |
969 | 969 | m_tms9901 = static_cast<tms9901_device*>(machine().device(TMS9901_TAG)); |
970 | ||
970 | ||
971 | 971 | m_gromport = static_cast<gromport_device*>(machine().device(GROMPORT_TAG)); |
972 | 972 | m_peribox = static_cast<peribox_device*>(machine().device(PERIBOX_TAG)); |
973 | ||
973 | ||
974 | 974 | m_datamux = static_cast<ti99_datamux_device*>(machine().device(DATAMUX_TAG)); |
975 | 975 | m_joyport = static_cast<joyport_device*>(machine().device(JOYPORT_TAG)); |
976 | 976 | m_video = static_cast<ti_video_device*>(machine().device(VIDEO_SYSTEM_TAG)); |
977 | 977 | m_firstjoy = 6; |
978 | ||
978 | ||
979 | 979 | m_peribox->senila(CLEAR_LINE); |
980 | 980 | m_peribox->senilb(CLEAR_LINE); |
981 | 981 | m_ready_line = m_ready_line_dmux = ASSERT_LINE; |
r17959 | r17960 | |
---|---|---|
26 | 26 | #include "machine/scsicd.h" |
27 | 27 | #include "machine/wd33c93.h" |
28 | 28 | |
29 | struct HPC_t | |
29 | struct HPC_t | |
30 | 30 | { |
31 | 31 | UINT8 nMiscStatus; |
32 | 32 | UINT32 nParBufPtr; |
r17959 | r17960 | |
38 | 38 | UINT32 nSCSI0DMACtrl; |
39 | 39 | }; |
40 | 40 | |
41 | struct RTC_t | |
41 | struct RTC_t | |
42 | 42 | { |
43 | 43 | UINT8 nRAM[32]; |
44 | 44 | UINT8 nTemp; |
r17959 | r17960 | |
---|---|---|
480 | 480 | bit description |
481 | 481 | |
482 | 482 | P0 EXPANSION PORT |
483 | P1 | |
484 | P2 | |
483 | P1 | |
484 | P2 | |
485 | 485 | P3 |
486 | 486 | P4 CASS SENS |
487 | P5 | |
487 | P5 | |
488 | 488 | |
489 | 489 | */ |
490 | 490 |
r17959 | r17960 | |
---|---|---|
2474 | 2474 | return str.trimspace(); |
2475 | 2475 | } |
2476 | 2476 | |
2477 | struct gba_chip_fix_conflict_item | |
2477 | struct gba_chip_fix_conflict_item | |
2478 | 2478 | { |
2479 | 2479 | char game_code[5]; |
2480 | 2480 | UINT32 chip; |
r17959 | r17960 | |
2518 | 2518 | { "BYUJ", GBA_CHIP_EEPROM_64K }, // 2322 - Yggdra Union (JPN) |
2519 | 2519 | }; |
2520 | 2520 | |
2521 | struct gba_chip_fix_eeprom_item | |
2521 | struct gba_chip_fix_eeprom_item | |
2522 | 2522 | { |
2523 | 2523 | char game_code[5]; |
2524 | 2524 | }; |
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