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r17910 Saturday 15th September, 2012 at 22:30:30 UTC by Aaron Giles
Pass 2 of struct modernization.
[src/emu]drawgfxm.h
[src/emu/cpu/alph8201]8201dasm.c
[src/emu/cpu/arm]arm.c
[src/emu/cpu/arm7]arm7core.h
[src/emu/cpu/cubeqcpu]cubeqcpu.c
[src/emu/cpu/dsp56k]dsp56k.h dsp56pcu.c
[src/emu/cpu/esrip]esrip.c
[src/emu/cpu/g65816]g65816ds.c
[src/emu/cpu/h6280]h6280.h
[src/emu/cpu/h83002]h8priv.h h8speriph.c
[src/emu/cpu/hcd62121]hcd62121d.c
[src/emu/cpu/hd61700]hd61700d.c
[src/emu/cpu/hd6309]6309dasm.c
[src/emu/cpu/i386]cycles.h i386dasm.c i386ops.h i386priv.h
[src/emu/cpu/i860]i860dec.c i860dis.c
[src/emu/cpu/i960]i960dis.c
[src/emu/cpu/konami]knmidasm.c
[src/emu/cpu/lh5801]5801dasm.c
[src/emu/cpu/m37710]m7700ds.c
[src/emu/cpu/m68000]m68k_in.c m68kdasm.c m68kmake.c
[src/emu/cpu/m6805]m6805.c
[src/emu/cpu/m6809]6809dasm.c
[src/emu/cpu/mc68hc11]hc11dasm.c
[src/emu/cpu/minx]minx.c
[src/emu/cpu/mips]mips3.c
[src/emu/cpu/nec]necdasm.c
[src/emu/cpu/powerpc]ppc.c ppc_dasm.c
[src/emu/cpu/saturn]saturnds.c
[src/emu/cpu/scudsp]scudspdasm.c
[src/emu/cpu/sh2]sh2comn.h
[src/emu/cpu/sh4]sh4comn.h
[src/emu/cpu/sharc]sharc.c sharc.h sharcdsm.h sharcops.h
[src/emu/cpu/sm8500]sm8500.h
[src/emu/cpu/spc700]spc700.c spc700ds.c
[src/emu/cpu/superfx]superfx.c
[src/emu/cpu/tlcs900]900tbl.c dasm900.c
[src/emu/cpu/tms32051]tms32051.c
[src/emu/cpu/tms57002]tmsmake.c
[src/emu/cpu/tms7000]7000dasm.c
[src/emu/cpu/upd7810]upd7810.h
[src/emu/machine]68681.c matsucd.c msm6242.h pc16552d.c rtc9701.h s3520cf.h s3c2400.h s3c2410.h s3c2440.h scsibus.h v3021.h
[src/emu/sound]c140.c c352.h c6280.c digitalk.c discrete.c es5503.h fm.c fm2612.c fmopl.c i5000.h k005289.c k051649.c msm5232.c n63701x.c namco.c s14001a.c x1_010.c ym2151.c ym2413.c ymf262.c ymf271.c ymf278b.c ymz770.h
[src/emu/video]rgbgen.h vector.c
[src/lib/formats]ace_tap.h
[src/mame/audio]cage.c exidy440.c flower.c gomoku.c wiping.c
[src/mame/drivers]firebeat.c konamigx.c konamim2.c maygayv1.c meritm.c namcos23.c taitotz.c vegas.c viper.c
[src/mame/includes]3do.h atari.h gstriker.h model3.h namcos1.h playch10.h suprnova.h thief.h
[src/mame/machine]cdi070.h kaneko_calc3.c kaneko_calc3.h kaneko_hit.h pxa255.h snes7110.c snescx4.h snessdd1.c stvcd.c znsec.c
[src/mame/video]dc.c kaneko_spr.h mcd212.h model2.c model3.c namcos21.c namcos22.c vdc.c vrender0.c
[src/mess/audio]lynx.c mea8000.c socrates.c svision.c vboy.h
[src/mess/devices]sonydriv.c
[src/mess/drivers]a2600.c cgenie.c gba.c hp49gp.c ip20.c ip22.c juicebox.c ng_aes.c pc8801.c pc88va.c pockstat.c psx.c ptcsol.c rvoice.c sgi_ip6.c
[src/mess/formats]timex_dck.h
[src/mess/includes]amstrad.h apple1.h bebox.h c64_legacy.h c65.h cgenie.h channelf.h compis.h concept.h cxhumax.h cybiko.h dgn_beta.h electron.h fm7.h gamecom.h gamepock.h gb.h gmaster.h gp32.h hp48.h intv.h lynx.h mbc55x.h msx_slot.h nascom1.h nes.h odyssey2.h oric.h pce.h pet.h pokemini.h rmnimbus.h sorcerer.h spectrum.h ssystem3.h svi318.h svision.h vc4000.h wswan.h x07.h x1.h z80ne.h
[src/mess/machine]3c505.h amigacd.c amigacrt.c amigakbd.c apollo_net.c at45dbxx.c corvushd.c mboard.h mc68328.h mc6843.c mc6846.c mc6854.c rmnimbus.c s3c44b0.h sgi.c strata.c
[src/mess/tools/imgtool]library.h
[src/mess/tools/imgtool/modules]thomson.c
[src/mess/video]733_asr.c crt.c newport.c

trunk/src/mame/audio/cage.c
r17909r17910
3434 *************************************/
3535
3636
37typedef struct
37struct cage_t
3838{
3939   cpu_device *cpu;
4040   attotime cpu_h1_clock_period;
r17909r17910
5959
6060   UINT32 *speedup_ram;
6161   dmadac_sound_device *dmadac[DAC_BUFFER_CHANNELS];
62} cage_t;
62};
6363
6464static cage_t cage;
6565
trunk/src/mame/audio/wiping.c
r17909r17910
1919
2020
2121/* this structure defines the parameters for a channel */
22typedef struct
22struct sound_channel
2323{
2424   int frequency;
2525   int counter;
r17909r17910
2727   const UINT8 *wave;
2828   int oneshot;
2929   int oneshotplaying;
30} sound_channel;
30};
3131
3232
3333
trunk/src/mame/audio/gomoku.c
r17909r17910
1919
2020
2121/* this structure defines the parameters for a channel */
22typedef struct
22struct sound_channel
2323{
2424   int channel;
2525   int frequency;
2626   int counter;
2727   int volume;
2828   int oneshotplaying;
29} sound_channel;
29};
3030
3131
3232struct gomoku_sound_state
trunk/src/mame/audio/flower.c
r17909r17910
2020
2121
2222/* this structure defines the parameters for a channel */
23typedef struct
23struct sound_channel
2424{
2525   UINT32 start;
2626   UINT32 pos;
r17909r17910
3232   UINT8 effect;
3333   UINT32 ecount;
3434
35} sound_channel;
35};
3636
3737
3838struct flower_sound_state
trunk/src/mame/audio/exidy440.c
r17909r17910
7171
7272
7373
74typedef struct
74struct exidy440_audio_state
7575{
7676   UINT8 sound_command;
7777   UINT8 sound_command_ack;
r17909r17910
100100
101101   /* channel frequency is configurable */
102102   int channel_frequency[4];
103}  exidy440_audio_state;
103};
104104
105105/* constant channel parameters */
106106static const int channel_bits[4] =
trunk/src/mame/machine/snes7110.c
r17909r17910
788788
789789static const UINT32 spc7110_months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
790790
791typedef struct
791struct _snes_spc7110_t
792792{
793793   //==================
794794   //decompression unit
r17909r17910
871871   UINT8 rtc_ram[16];   // 0-12 secs, min, hrs, etc.; 13-14-15 control registers
872872
873873   UINT32 size;
874} _snes_spc7110_t;
874};
875875
876876static _snes_spc7110_t snes_spc7110;
877877
trunk/src/mame/machine/kaneko_hit.h
r17909r17910
11/* Kaneko Hit protection */
22
33
4typedef struct
4struct calc1_hit_t
55{
66   UINT16 x1p, y1p, x1s, y1s;
77   UINT16 x2p, y2p, x2s, y2s;
r17909r17910
99   INT16 x12, y12, x21, y21;
1010
1111   UINT16 mult_a, mult_b;
12} calc1_hit_t;
12};
1313
14typedef struct
14struct calc3_hit_t
1515{
1616   int x1p, y1p, z1p, x1s, y1s, z1s;
1717   int x2p, y2p, z2p, x2s, y2s, z2s;
r17909r17910
2929
3030   UINT16 flags;
3131   UINT16 mode;
32} calc3_hit_t;
32};
3333
3434
3535
trunk/src/mame/machine/stvcd.c
r17909r17910
4646#define MAX_BLOCKS   (200)
4747#define MAX_DIR_SIZE   (256*1024)
4848
49typedef struct
49struct direntryT
5050{
5151   UINT8 record_size;
5252   UINT8 xa_record_size;
r17909r17910
6464   UINT8 interleave_gap_size;
6565   UINT16 volume_sequencer_number;
6666   UINT8 name[128];
67} direntryT;
67};
6868
69typedef struct
69struct filterT
7070{
7171   UINT8 mode;
7272   UINT8 chan;
r17909r17910
7979   UINT8 condfalse;
8080   UINT32 fad;
8181   UINT32 range;
82} filterT;
82};
8383
84typedef struct
84struct blockT
8585{
8686   INT32 size;   // size of block
8787   INT32 FAD;   // FAD on disc
r17909r17910
9090   UINT8 fnum;   // file number
9191   UINT8 subm;   // subchannel mode
9292   UINT8 cinf;   // coding information
93} blockT;
93};
9494
95typedef struct
95struct partitionT
9696{
9797   INT32 size;
9898   blockT *blocks[MAX_BLOCKS];
9999   UINT8 bnum[MAX_BLOCKS];
100100   UINT8 numblks;
101} partitionT;
101};
102102
103103// 16-bit transfer types
104104typedef enum
trunk/src/mame/machine/znsec.c
r17909r17910
8585#include "emu.h"
8686#include "znsec.h"
8787
88typedef struct {
88struct znsec_state {
8989   const UINT8 *transform;
9090   UINT8 state;
9191   UINT8 bit;
92} znsec_state;
92};
9393
9494static znsec_state zns[2];
9595
trunk/src/mame/machine/pxa255.h
r17909r17910
163163      #define PXA255_DCMD_WIDTH_2   (0x00008000)
164164      #define PXA255_DCMD_WIDTH_4   (0x0000c000)
165165
166typedef struct
166struct PXA255_DMA_Regs
167167{
168168   UINT32 dcsr[16];
169169
r17909r17910
183183   UINT32 dcmd[16];
184184
185185   emu_timer* timer[16];
186} PXA255_DMA_Regs;
186};
187187
188188/*
189189
r17909r17910
230230#define PXA255_SADIV         (PXA255_I2S_BASE_ADDR + 0x00000060)
231231#define PXA255_SADR            (PXA255_I2S_BASE_ADDR + 0x00000080)
232232
233typedef struct
233struct PXA255_I2S_Regs
234234{
235235   UINT32 sacr0;
236236   UINT32 sacr1;
r17909r17910
251251   UINT32 pad3[6];
252252
253253   UINT32 sadr;
254} PXA255_I2S_Regs;
254};
255255
256256/*
257257
r17909r17910
279279   #define PXA255_OIER_E2      (0x00000004)
280280   #define PXA255_OIER_E3      (0x00000008)
281281
282typedef struct
282struct PXA255_OSTMR_Regs
283283{
284284   UINT32 osmr[4];
285285   UINT32 oscr;
r17909r17910
288288   UINT32 oier;
289289
290290   emu_timer* timer[4];
291} PXA255_OSTMR_Regs;
291};
292292
293293/*
294294
r17909r17910
331331#define PXA255_INT_RTC_HZ      (1 << 30)
332332#define PXA255_INT_RTC_ALARM   (1 << 31)
333333
334typedef struct
334struct PXA255_INTC_Regs
335335{
336336   UINT32 icip;
337337   UINT32 icmr;
r17909r17910
339339   UINT32 icfp;
340340   UINT32 icpr;
341341   UINT32 iccr;
342} PXA255_INTC_Regs;
342};
343343
344344/*
345345
r17909r17910
378378#define PXA255_GAFR2_L         (PXA255_GPIO_BASE_ADDR + 0x00000064)
379379#define PXA255_GAFR2_U         (PXA255_GPIO_BASE_ADDR + 0x00000068)
380380
381typedef struct
381struct PXA255_GPIO_Regs
382382{
383383   UINT32 gplr0; // GPIO Pin-Leve
384384   UINT32 gplr1;
r17909r17910
414414   UINT32 gafr1u;
415415   UINT32 gafr2l;
416416   UINT32 gafr2u;
417} PXA255_GPIO_Regs;
417};
418418
419419/*
420420
r17909r17910
476476#define PXA255_FIDR1         (PXA255_LCD_BASE_ADDR + 0x00000218)
477477#define PXA255_LDCMD1         (PXA255_LCD_BASE_ADDR + 0x0000021c)
478478
479typedef struct
479struct PXA255_LCD_DMA_Regs
480480{
481481   UINT32 fdadr;
482482   UINT32 fsadr;
483483   UINT32 fidr;
484484   UINT32 ldcmd;
485485   emu_timer *eof;
486} PXA255_LCD_DMA_Regs;
486};
487487
488typedef struct
488struct PXA255_LCD_Regs
489489{
490490   UINT32 lccr0;
491491   UINT32 lccr1;
r17909r17910
506506   UINT32 pad2[110];
507507
508508   PXA255_LCD_DMA_Regs dma[2];
509} PXA255_LCD_Regs;
509};
trunk/src/mame/machine/kaneko_calc3.c
r17909r17910
7070
7171
7272
73typedef struct
73struct calc3_t
7474{
7575
7676   int data_header[2];
7777
7878
79} calc3_t;
79};
8080
8181
8282
trunk/src/mame/machine/kaneko_calc3.h
r17909r17910
33#define CALC3_VERBOSE_OUTPUT 0
44
55
6typedef struct
6struct calc3_t
77{
88   int mcu_status;
99   int mcu_command_offset;
r17909r17910
2323   UINT16 eeprom_addr;
2424   UINT16 poll_addr;
2525   UINT16 checksumaddress;
26} calc3_t;
26};
2727
2828
2929
trunk/src/mame/machine/snessdd1.c
r17909r17910
178178}
179179
180180
181typedef struct
181struct SDD1_PEM_state
182182{
183183   UINT8 code_num;
184184   UINT8 nextIfMPS;
185185   UINT8 nextIfLPS;
186} SDD1_PEM_state;
186};
187187
188188static const SDD1_PEM_state SDD1_PEM_evolution_table[33] =
189189{
r17909r17910
222222   { 7,24,22}
223223};
224224
225typedef struct
225struct SDD1_PEM_ContextInfo
226226{
227227   UINT8 status;
228228   UINT8 MPS;
229} SDD1_PEM_ContextInfo;
229};
230230
231231class SDD1_PEM //Probability Estimation Module
232232{
trunk/src/mame/machine/snescx4.h
r17909r17910
88
99***************************************************************************/
1010
11typedef struct
11struct CX4
1212{
1313       UINT8 ram[0x0c00];
1414       UINT8 reg[0x0100];
r17909r17910
2121       double tanval;
2222       double c4x, c4y, c4z;
2323       double c4x2, c4y2, c4z2;
24} CX4;
24};
trunk/src/mame/machine/cdi070.h
r17909r17910
2424
2525#include "emu.h"
2626
27typedef struct
27struct scc68070_i2c_regs_t
2828{
2929   UINT8 reserved0;
3030   UINT8 data_register;
r17909r17910
3636   UINT8 control_register;
3737   UINT8 reserved;
3838   UINT8 clock_control_register;
39} scc68070_i2c_regs_t;
39};
4040
4141#define ISR_MST      0x80   // Master
4242#define ISR_TRX      0x40   // Transmitter
r17909r17910
4747#define ISR_AD0      0x02   // Address Zero
4848#define ISR_LRB      0x01   // Last Received Bit
4949
50typedef struct
50struct scc68070_uart_regs_t
5151{
5252   UINT8 reserved0;
5353   UINT8 mode_register;
r17909r17910
6969   INT16 transmit_pointer;
7070   UINT8 transmit_buffer[32768];
7171   emu_timer* tx_timer;
72} scc68070_uart_regs_t;
72};
7373
7474#define UMR_OM         0xc0
7575#define UMR_OM_NORMAL   0x00
r17909r17910
9090#define USR_TXRDY      0x04
9191#define USR_RXRDY      0x01
9292
93typedef struct
93struct scc68070_timer_regs_t
9494{
9595   UINT8 timer_status_register;
9696   UINT8 timer_control_register;
r17909r17910
9999   UINT16 timer1;
100100   UINT16 timer2;
101101   emu_timer* timer0_timer;
102} scc68070_timer_regs_t;
102};
103103
104104#define TSR_OV0         0x80
105105#define TSR_MA1         0x40
r17909r17910
130130#define TCR_M2_CAPTURE   0x02
131131#define TCR_M2_COUNT   0x03
132132
133typedef struct
133struct scc68070_dma_channel_t
134134{
135135   UINT8 channel_status;
136136   UINT8 channel_error;
r17909r17910
153153   UINT32 device_address_counter;
154154
155155   UINT8 reserved3[40];
156} scc68070_dma_channel_t;
156};
157157
158158#define CSR_COC         0x80
159159#define CSR_NDT         0x20
r17909r17910
193193#define CCR_INE         0x08
194194#define CCR_IPL         0x07
195195
196typedef struct
196struct scc68070_dma_regs_t
197197{
198198   scc68070_dma_channel_t channel[2];
199} scc68070_dma_regs_t;
199};
200200
201typedef struct
201struct scc68070_mmu_desc_t
202202{
203203   UINT16 attr;
204204   UINT16 length;
205205   UINT8  undefined;
206206   UINT8  segment;
207207   UINT16 base;
208} scc68070_mmu_desc_t;
208};
209209
210typedef struct
210struct scc68070_mmu_regs_t
211211{
212212   UINT8 status;
213213   UINT8 control;
r17909r17910
215215   UINT8 reserved[0x3e];
216216
217217   scc68070_mmu_desc_t desc[8];
218} scc68070_mmu_regs_t;
218};
219219
220typedef struct
220struct scc68070_regs_t
221221{
222222   UINT16 lir;
223223   UINT8 picr1;
r17909r17910
228228   scc68070_timer_regs_t timers;
229229   scc68070_dma_regs_t dma;
230230   scc68070_mmu_regs_t mmu;
231} scc68070_regs_t;
231};
232232
233233// Member functions
234234TIMER_CALLBACK( scc68070_timer0_callback );
trunk/src/mame/includes/thief.h
r17909r17910
1typedef struct {
1struct coprocessor_t {
22   UINT8 *context_ram;
33   UINT8 bank;
44   UINT8 *image_ram;
55   UINT8 param[0x9];
6} coprocessor_t;
6};
77
88class thief_state : public driver_device
99{
trunk/src/mame/includes/suprnova.h
r17909r17910
1typedef struct
1struct hit_t
22{
33   UINT16 x1p, y1p, z1p, x1s, y1s, z1s;
44   UINT16 x2p, y2p, z2p, x2s, y2s, z2s;
r17909r17910
1111   UINT16 flag;
1212
1313   UINT8 disconnect;
14} hit_t;
14};
1515
1616
1717class skns_state : public driver_device
trunk/src/mame/includes/gstriker.h
r17909r17910
55
66#define MAX_VS920A 2
77
8typedef struct
8struct sVS920A
99{
1010   tilemap_t* tmap;
1111   UINT16* vram;
1212   UINT16 pal_base;
1313   UINT8 gfx_region;
1414
15} sVS920A;
15};
1616
1717/*** MB60553 **********************************************/
1818
1919#define MAX_MB60553 2
2020
21typedef struct
21struct tMB60553
2222{
2323   tilemap_t* tmap;
2424   UINT16* vram;
r17909r17910
2727   UINT16 pal_base;
2828   UINT8 gfx_region;
2929
30} tMB60553;
30};
3131
3232/*** CG10103 **********************************************/
3333
3434#define MAX_CG10103 2
3535
36typedef struct
36struct tCG10103
3737{
3838   UINT16* vram;
3939   UINT16 pal_base;
4040   UINT8 gfx_region;
4141   UINT8 transpen;
4242
43} tCG10103;
43};
4444
4545class gstriker_state : public driver_device
4646{
trunk/src/mame/includes/model3.h
r17909r17910
66typedef float VECTOR[4];
77typedef float VECTOR3[3];
88
9typedef struct {
9struct PLANE {
1010   float x,y,z,d;
11} PLANE;
11};
1212
1313typedef struct _cached_texture cached_texture;
1414
trunk/src/mame/includes/3do.h
r17909r17910
77#ifndef _3DO_H_
88#define _3DO_H_
99
10typedef struct {
10struct SLOW2 {
1111   /* 03180000 - 0318003f - configuration group */
1212   /* 03180040 - 0318007f - diagnostic UART */
1313
r17909r17910
1515   UINT8   cg_w_count;
1616   UINT32   cg_input;
1717   UINT32   cg_output;
18} SLOW2;
18};
1919
2020
21typedef struct {
21struct MADAM {
2222   UINT32   revision;      /* 03300000 */
2323   UINT32   msysbits;      /* 03300004 */
2424   UINT32   mctl;         /* 03300008 */
r17909r17910
5151   UINT32   mult[40];      /* 03300600-0330069c */
5252   UINT32   mult_control;   /* 033007f0-033007f4 */
5353   UINT32   mult_status;   /* 033007f8 */
54} MADAM;
54};
5555
5656
57typedef struct {
57struct CLIO {
5858   screen_device *screen;
5959
6060   UINT32   revision;      /* 03400000 */
r17909r17910
150150   UINT32   uncle_soft_rev;   /* 0340c004 */
151151   UINT32   uncle_addr;      /* 0340c008 */
152152   UINT32   uncle_rom;      /* 0340c00c */
153} CLIO;
153};
154154
155155
156typedef struct {
156struct SVF {
157157   UINT32   sport[512];
158158   UINT32   color;
159} SVF;
159};
160160
161161
162162class _3do_state : public driver_device
trunk/src/mame/includes/namcos1.h
r17909r17910
11#define NAMCOS1_MAX_BANK 0x400
22
33/* Bank handler definitions */
4typedef struct
4struct bankhandler
55{
66   read8_space_func bank_handler_r;
77   write8_space_func bank_handler_w;
88   int           bank_offset;
99   UINT8 *bank_pointer;
10} bankhandler;
10};
1111
1212class namcos1_state : public driver_device
1313{
trunk/src/mame/includes/playch10.h
r17909r17910
1typedef struct
1struct chr_bank
22{
33   int writable;   // 1 for RAM, 0 for ROM
44   UINT8* chr;      // direct access to the memory
5} chr_bank;
5};
66
77class playch10_state : public driver_device
88{
trunk/src/mame/includes/atari.h
r17909r17910
208208}   ANTIC_W;  /* write registers */
209209
210210/* per scanline buffer for video data (and optimization variables) */
211typedef struct {
211struct VIDEO {
212212    UINT32  cmd;                /* antic command for this scanline */
213213    UINT16  data[HWIDTH];       /* graphics data buffer (text through chargen) */
214}   VIDEO;
214};
215215
216216typedef void (*atari_renderer_func)(address_space *space, VIDEO *video);
217217
218typedef struct {
218struct ANTIC {
219219   atari_renderer_func   renderer;   /* current renderer */
220220   UINT32   cmd;            /* currently executed display list command */
221221   UINT32   steal_cycles;      /* steal how many cpu cycles for this line ? */
r17909r17910
261261   UINT8   *uc_g2;            /* used colors for gfx GTIA 2 */
262262   UINT8   *uc_g3;            /* used colors for gfx GTIA 3 */
263263   bitmap_ind16 *bitmap;
264}   ANTIC;
264};
265265
266266#define RDANTIC(space)      space->read_byte(antic.dpage+antic.doffs)
267267#define RDVIDEO(space,o)   space->read_byte(antic.vpage+((antic.voffs+(o))&VOFFS))
trunk/src/mame/video/mcd212.h
r17909r17910
2424
2525#include "emu.h"
2626
27typedef struct
27struct mcd212_channel_t
2828{
2929    UINT8 csrr;
3030    UINT16 csrw;
r17909r17910
5858    UINT32 mosaic_hold_b;
5959    UINT8 weight_factor_a[768];
6060    UINT8 weight_factor_b[768];
61} mcd212_channel_t;
61};
6262
6363typedef struct
6464{
trunk/src/mame/video/vdc.c
r17909r17910
2020
2121/* the VDC context */
2222
23typedef struct
23struct VDC
2424{
2525   int dvssr_write;         /* Set when the DVSSR register has been written to */
2626   int physical_width;         /* Width of the display */
r17909r17910
3939   pair vdc_data[32];
4040   int status;
4141   int y_scroll;
42}VDC;
42};
4343
44typedef struct {
44struct VCE {
4545   UINT8   vce_control;         /* VCE control register */
4646   pair   vce_address;         /* Current address in the palette */
4747   pair   vce_data[512];         /* Palette data */
4848   int      current_bitmap_line;   /* The current line in the display we are on */
4949   bitmap_ind16   *bmp;
50}VCE;
50};
5151
52typedef struct {
52struct VPC_PRIO {
5353   UINT8 prio;
5454   UINT8 vdc0_enabled;
5555   UINT8 vdc1_enabled;
56} VPC_PRIO;
56};
5757
58typedef struct {
58struct VPC {
5959   VPC_PRIO vpc_prio[4];
6060   UINT8   prio_map[512];      /* Pre-calculated priority map */
6161   pair   priority;         /* Priority settings registers */
6262   pair   window1;         /* Window 1 setting */
6363   pair   window2;         /* Window 2 setting */
6464   UINT8   vdc_select;         /* Which VDC do the ST0, ST1, and ST2 instructions write to */
65}VPC;
65};
6666
6767static VDC vdc[2];
6868static VCE vce;
trunk/src/mame/video/model2.c
r17909r17910
104104 *
105105 *******************************************/
106106
107typedef struct
107struct plane
108108{
109109   poly_vertex   normal;
110110   float      distance;
111} plane;
111};
112112
113typedef struct
113struct texture_parameter
114114{
115115   float   diffuse;
116116   float   ambient;
117117   UINT32   specular_control;
118118   float   specular_scale;
119} texture_parameter;
119};
120120
121typedef struct
121struct triangle
122122{
123123   void *            next;
124124   poly_vertex         v[3];
r17909r17910
127127   UINT8            luma;
128128   INT16            viewport[4];
129129   INT16            center[2];
130} triangle;
130};
131131
132typedef struct
132struct _quad_m2
133133{
134134   poly_vertex         v[4];
135135   UINT16            z;
136136   UINT16            texheader[4];
137137   UINT8            luma;
138} _quad_m2;
138};
139139
140140struct poly_extra_data
141141{
trunk/src/mame/video/dc.c
r17909r17910
150150   float x, y, w, u, v;
151151} vert;
152152
153typedef struct
153struct strip
154154{
155155   int svert, evert;
156156   texinfo ti;
157} strip;
157};
158158
159typedef struct {
159struct receiveddata {
160160   vert verts[65536];
161161   strip strips[65536];
162162
r17909r17910
166166   UINT32 fbwsof2;
167167   int busy;
168168   int valid;
169} receiveddata;
169};
170170
171typedef struct {
171struct pvrta_state {
172172   int tafifo_pos, tafifo_mask, tafifo_vertexwords, tafifo_listtype;
173173   int start_render_received;
174174   int renderselect;
r17909r17910
184184   UINT32 blend_mode, srcselect,dstselect,fogcontrol,colorclamp, use_alpha;
185185   UINT32 ignoretexalpha,flipuv,clampuv,filtermode,sstexture,mmdadjust,tsinstruction;
186186   UINT32 depthcomparemode,cullingmode,zwritedisable,cachebypass,dcalcctrl,volumeinstruction,mipmapped,vqcompressed,strideselect,paletteselector;
187} pvrta_state;
187};
188188
189189enum
190190{
trunk/src/mame/video/namcos21.c
r17909r17910
233233
234234/*********************************************************************************************/
235235
236typedef struct
236struct vertex
237237{
238238   double x,y;
239239   double z;
240} vertex;
240};
241241
242typedef struct
242struct edge
243243{
244244   double x;
245245   double z;
246} edge;
246};
247247
248248#define SWAP(T,A,B) { const T *temp = A; A = B; B = temp; }
249249
trunk/src/mame/video/model3.c
r17909r17910
1212
1313
1414
15typedef struct
15struct TRIANGLE
1616{
1717   poly_vertex v[3];
1818   UINT8 texture_x, texture_y;
r17909r17910
2121   UINT8 texture_format, param;
2222   int intensity;
2323   UINT32 color;
24} TRIANGLE;
24};
2525
2626struct _cached_texture
2727{
trunk/src/mame/video/namcos22.c
r17909r17910
317317   mClip.scissor.set(0, 639, 0, 479);
318318}
319319
320typedef struct
320struct Poly3dVertex
321321{
322322   float x,y,z;
323323   int u,v; /* 0..0xfff */
324324   int bri; /* 0..0xff */
325} Poly3dVertex;
325};
326326
327327#define MIN_Z (10.0f)
328328
trunk/src/mame/video/vrender0.c
r17909r17910
2020
2121**************/
2222
23typedef struct
23struct _Quad
2424{
2525   UINT16 *Dest;
2626   UINT32 Pitch;   //in UINT16s
r17909r17910
4848   UINT32 SrcColor;
4949   UINT8 DstAlpha;
5050   UINT32 DstColor;
51} _Quad;
51};
5252
53typedef struct
53struct _RenderState
5454{
5555   UINT32 Tx;
5656   UINT32 Ty;
r17909r17910
7272   UINT32 PixelFormat;
7373   UINT32 Width;
7474   UINT32 Height;
75} _RenderState;
75};
7676
7777struct vr0video_state
7878{
trunk/src/mame/video/kaneko_spr.h
r17909r17910
1111
1212
1313
14typedef struct
14struct kaneko16_priority_t
1515{
1616   int sprite[4];
17} kaneko16_priority_t;
17};
1818
1919struct tempsprite
2020{
trunk/src/mame/drivers/viper.c
r17909r17910
447447#define I2C_STATE_DATA_TRANSFER      2
448448
449449
450typedef struct
450struct MPC8240_IRQ
451451{
452452   UINT32 vector;
453453   int priority;
r17909r17910
455455   int active;
456456   int pending;
457457   int mask;
458} MPC8240_IRQ;
458};
459459
460typedef struct
460struct MPC8240_GLOBAL_TIMER
461461{
462462   UINT32 base_count;
463463   int enable;
464464   emu_timer *timer;
465} MPC8240_GLOBAL_TIMER;
465};
466466
467467
468468
469typedef struct
469struct MPC8240_EPIC
470470{
471471   UINT32 iack;
472472   UINT32 eicr;
r17909r17910
484484
485485   MPC8240_GLOBAL_TIMER global_timer[4];
486486
487} MPC8240_EPIC;
487};
488488
489489// TODO: move to viper_state
490490static MPC8240_EPIC epic;
trunk/src/mame/drivers/maygayv1.c
r17909r17910
193193
194194#define DRAM_BANK_SEL      (banks[(VREG(DSBA) >> 7) & 3])
195195
196typedef struct
196struct i82716_t
197197{
198198   UINT16   r[16];
199199   UINT16   *dram;
200200
201201   UINT8   *line_buf;   // there's actually two
202} i82716_t;
202};
203203
204204
205typedef struct
205struct i8279_t
206206{
207207   UINT8   command;
208208   UINT8   mode;
r17909r17910
211211   UINT8   clear;
212212   UINT8   fifo[8];
213213   UINT8   ram[16];
214} i8279_t;
214};
215215
216216class maygayv1_state : public driver_device
217217{
trunk/src/mame/drivers/namcos23.c
r17909r17910
12691269enum { RENDER_MAX_ENTRIES = 1000, POLY_MAX_ENTRIES = 10000 };
12701270
12711271
1272typedef struct
1272struct c417_t
12731273{
12741274   UINT16 ram[0x10000];
12751275   UINT16 adr;
12761276   UINT32 pointrom_adr;
1277} c417_t;
1277};
12781278
1279typedef struct
1279struct c412_t
12801280{
12811281   UINT16 sdram_a[0x100000]; // Framebuffers, probably
12821282   UINT16 sdram_b[0x100000];
12831283   UINT16 sram[0x20000];     // Ram-based tiles for rendering
12841284   UINT16 pczram[0x200];     // Ram-based tilemap for rendering, or something else
12851285   UINT32 adr;
1286} c412_t;
1286};
12871287
1288typedef struct
1288struct c421_t
12891289{
12901290   UINT16 dram_a[0x40000];
12911291   UINT16 dram_b[0x40000];
12921292   UINT16 sram[0x8000];
12931293   UINT32 adr;
1294} c421_t;
1294};
12951295
1296typedef struct
1296struct c422_t
12971297{
12981298   INT16 regs[0x10];
1299} c422_t;
1299};
13001300
1301typedef struct
1301struct c361_t
13021302{
13031303   emu_timer *timer;
13041304   int scanline;
1305} c361_t;
1305};
13061306
1307typedef struct
1307struct render_t
13081308{
13091309   poly_manager *polymgr;
13101310   int cur;
r17909r17910
13131313   namcos23_render_entry entries[2][RENDER_MAX_ENTRIES];
13141314   namcos23_poly_entry polys[POLY_MAX_ENTRIES];
13151315   namcos23_poly_entry *poly_order[POLY_MAX_ENTRIES];
1316} render_t;
1316};
13171317
13181318class namcos23_state : public driver_device
13191319{
trunk/src/mame/drivers/meritm.c
r17909r17910
164164#include "machine/nvram.h"
165165
166166
167typedef struct
167struct ds1204_t
168168{
169169   int state;
170170   int read_ptr;
r17909r17910
174174   int out_bit;
175175   UINT8 command[3];
176176
177} ds1204_t;
177};
178178
179179class meritm_state : public driver_device
180180{
trunk/src/mame/drivers/taitotz.c
r17909r17910
373373   int specular_r, specular_g, specular_b;
374374};
375375
376typedef struct
376struct PLANE
377377{
378378   float x, y, z, d;
379} PLANE;
379};
380380
381381typedef float VECTOR3[3];
382382
trunk/src/mame/drivers/vegas.c
r17909r17910
442442
443443
444444
445typedef struct
445struct dynamic_address
446446{
447447   offs_t         start;
448448   offs_t         end;
r17909r17910
453453   device_t *device;
454454   const char *   rdname;
455455   const char *   wrname;
456} dynamic_address;
456};
457457
458458class vegas_state : public driver_device
459459{
trunk/src/mame/drivers/firebeat.c
r17909r17910
121121#include "firebeat.lh"
122122
123123
124typedef struct
124struct GCU_REGS
125125{
126126   UINT32 *vram;
127127   UINT32 vram_read_address;
128128   UINT32 vram_write_fifo_address;
129129   UINT32 visible_area;
130} GCU_REGS;
130};
131131
132typedef struct
132struct IBUTTON_SUBKEY
133133{
134134   UINT8 identifier[8];
135135   UINT8 password[8];
136136   UINT8 data[0x30];
137} IBUTTON_SUBKEY;
137};
138138
139typedef struct
139struct IBUTTON
140140{
141141   IBUTTON_SUBKEY subkey[3];
142} IBUTTON;
142};
143143
144144
145145
trunk/src/mame/drivers/konamigx.c
r17909r17910
36603660   }
36613661}
36623662
3663typedef struct
3663struct GXGameInfoT
36643664{
36653665   const char *romname;
36663666   UINT32 cfgport;
36673667   UINT32 sndhack;
36683668   UINT32 special;
36693669   UINT32 readback;
3670} GXGameInfoT;
3670};
36713671
36723672#define BPP4  0
36733673#define BPP5  1
trunk/src/mame/drivers/konamim2.c
r17909r17910
191191#include "cpu/powerpc/ppc.h"
192192
193193
194typedef struct
194struct CDE_DMA
195195{
196196   UINT32 dst_addr;
197197   int length;
198198   UINT32 next_dst_addr;
199199   int next_length;
200200   int dma_done;
201} CDE_DMA;
201};
202202
203203class konamim2_state : public driver_device
204204{
trunk/src/lib/formats/ace_tap.h
r17909r17910
1111
1212#include "cassimg.h"
1313
14typedef struct
14struct ace_tape_t
1515{
1616   UINT8 hdr_type;
1717   UINT8 hdr_name[10];
r17909r17910
2121   UINT8 hdr_3c4c;
2222   UINT8 hdr_3c4d;
2323   UINT16 dat_len;
24} ace_tape_t;
24};
2525
2626CASSETTE_FORMATLIST_EXTERN(ace_cassette_formats);
2727
trunk/src/emu/cpu/m6805/m6805.c
r17909r17910
4545};
4646
4747/* 6805 Registers */
48typedef struct
48struct m6805_Regs
4949{
5050   /* Pre-pointerafied public globals */
5151   int iCount;
r17909r17910
6767   direct_read_data *direct;
6868   int    irq_state[9];      /* KW Additional lines for HD63705 */
6969   int      nmi_state;
70} m6805_Regs;
70};
7171
7272INLINE m6805_Regs *get_safe_token(device_t *device)
7373{
trunk/src/emu/cpu/lh5801/5801dasm.c
r17909r17910
131131   "RPV", "SPV",
132132};
133133
134typedef struct { Ins ins; Adr adr; Regs reg; } Entry;
134struct Entry { Ins ins; Adr adr; Regs reg; };
135135
136136static const Entry table[0x100]={
137137   { SBC, Reg, XL }, // 0
trunk/src/emu/cpu/m6809/6809dasm.c
r17909r17910
2020#include "m6809.h"
2121
2222// Opcode structure
23typedef struct
23struct opcodeinfo
2424{
2525   UINT8   opcode;      // 8-bit opcode value
2626   UINT8   length;      // Opcode length in bytes
2727   char    name[6];   // Opcode name
2828   UINT8   mode;      // Addressing mode
2929   unsigned flags;      // Disassembly flags
30} opcodeinfo;
30};
3131
3232enum m6809_addressing_modes
3333{
trunk/src/emu/cpu/h83002/h8priv.h
r17909r17910
1111
1212#define H8_MAX_PORTS (16)  // number of I/O ports defined architecturally (1-9 and A-G = 16)
1313
14typedef struct
14struct H8S2XXX_TPU_ITEM
1515{
1616   UINT32 tgr, irq, out;
17} H8S2XXX_TPU_ITEM;
17};
1818
19typedef struct
19struct H8S2XXX_TPU
2020{
2121   emu_timer *timer;
2222   int cycles_per_tick;
2323   UINT64 timer_cycles;
24} H8S2XXX_TPU;
24};
2525
26typedef struct
26struct H8S2XXX_SCI
2727{
2828   emu_timer *timer;
2929   UINT32 bitrate;
30} H8S2XXX_SCI;
30};
3131
32typedef struct
32struct H8S2XXX_TMR
3333{
3434   emu_timer *timer;
3535   int cycles_per_tick;
3636   UINT64 timer_cycles;
37} H8S2XXX_TMR;
37};
3838
3939struct h83xx_state
4040{
trunk/src/emu/cpu/h83002/h8speriph.c
r17909r17910
11581158// SERIAL CONTROLLER INTERFACE //
11591159/////////////////////////////////
11601160
1161typedef struct
1161struct H8S_SCI_ENTRY
11621162{
11631163   UINT32 reg_smr, reg_brr, reg_scr, reg_tdr, reg_ssr, reg_rdr;
11641164   UINT32 reg_pdr, reg_port;
11651165   UINT8 port_mask_sck, port_mask_txd, port_mask_rxd;
11661166   UINT8 int_tx, int_rx;
1167} H8S_SCI_ENTRY;
1167};
11681168
11691169const H8S_SCI_ENTRY H8S_SCI_TABLE[] =
11701170{
trunk/src/emu/cpu/m68000/m68k_in.c
r17909r17910
128128unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
129129
130130/* This is used to generate the opcode handler jump table */
131typedef struct
131struct opcode_handler_struct
132132{
133133   void (*opcode_handler)(m68ki_cpu_core *m68k);        /* handler function */
134134   unsigned int  mask;                  /* mask on opcode */
135135   unsigned int  match;                 /* what to match after masking */
136136   unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
137} opcode_handler_struct;
137};
138138
139139
140140/* Opcode handler table */
trunk/src/emu/cpu/m68000/m68kmake.c
r17909r17910
175175
176176
177177/* Everything we need to know about an opcode */
178typedef struct
178struct opcode_struct
179179{
180180   char name[MAX_NAME_LENGTH];           /* opcode handler name */
181181   unsigned char size;                   /* Size of operation */
r17909r17910
188188   char cpu_mode[NUM_CPUS];              /* User or supervisor mode */
189189   char cpus[NUM_CPUS+1];                /* Allowed CPUs */
190190   unsigned char cycles[NUM_CPUS];       /* cycles for 000, 010, 020, 030, 040 */
191} opcode_struct;
191};
192192
193193
194194/* All modifications necessary for a specific EA mode of an instruction */
195typedef struct
195struct ea_info_struct
196196{
197197   const char* fname_add;
198198   const char* ea_add;
199199   unsigned int mask_add;
200200   unsigned int match_add;
201} ea_info_struct;
201};
202202
203203
204204/* Holds the body of a function */
205typedef struct
205struct body_struct
206206{
207207   char body[MAX_BODY_LENGTH][MAX_LINE_LENGTH+1];
208208   int length;
209} body_struct;
209};
210210
211211
212212/* Holds a sequence of search / replace strings */
213typedef struct
213struct replace_struct
214214{
215215   char replace[MAX_REPLACE_LENGTH][2][MAX_LINE_LENGTH+1];
216216   int length;
217} replace_struct;
217};
218218
219219
220220/* Function Prototypes */
trunk/src/emu/cpu/m68000/m68kdasm.c
r17909r17910
174174static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr);
175175
176176/* used to build opcode handler jump table */
177typedef struct
177struct opcode_struct
178178{
179179   void (*opcode_handler)(void); /* handler function */
180180   UINT32 mask;                    /* mask on opcode */
181181   UINT32 match;                   /* what to match after masking */
182182   UINT32 ea_mask;                 /* what ea modes are allowed */
183} opcode_struct;
183};
184184
185185
186186
trunk/src/emu/cpu/superfx/superfx.c
r17909r17910
22#include "debugger.h"
33#include "superfx.h"
44
5typedef struct
5struct pixelcache_t
66{
77   UINT16 offset;
88   UINT8 bitpend;
99   UINT8 data[8];
10} pixelcache_t;
10};
1111
12typedef struct
12struct cache_t
1313{
1414   UINT8 buffer[0x200];
1515   UINT8 valid[0x20];
16} cache_t;
16};
1717
1818struct superfx_state
1919{
trunk/src/emu/cpu/m37710/m7700ds.c
r17909r17910
1616
1717#define ADDRESS_24BIT(A) ((A)&0xffffff)
1818
19typedef struct
19struct opcode_struct
2020{
2121   unsigned char name;
2222   unsigned char flag;
2323   unsigned char ea;
24} opcode_struct;
24};
2525
2626enum
2727{
trunk/src/emu/cpu/sharc/sharc.c
r17909r17910
3939   SHARC_B12,      SHARC_B13,      SHARC_B14,      SHARC_B15,
4040};
4141
42typedef struct
42struct SHARC_DAG
4343{
4444   UINT32 i[8];
4545   UINT32 m[8];
4646   UINT32 b[8];
4747   UINT32 l[8];
48} SHARC_DAG;
48};
4949
5050typedef union
5151{
r17909r17910
5353   float f;
5454} SHARC_REG;
5555
56typedef struct
56struct DMA_REGS
5757{
5858   UINT32 control;
5959   UINT32 int_index;
r17909r17910
6464   UINT32 ext_index;
6565   UINT32 ext_modifier;
6666   UINT32 ext_count;
67} DMA_REGS;
67};
6868
69typedef struct
69struct LADDR
7070{
7171   UINT32 addr;
7272   UINT32 code;
7373   UINT32 loop_type;
74} LADDR;
74};
7575
76typedef struct
76struct DMA_OP
7777{
7878   UINT32 src;
7979   UINT32 dst;
r17909r17910
8686   INT32 chained_direction;
8787   emu_timer *timer;
8888   bool active;
89} DMA_OP;
89};
9090
9191typedef struct _SHARC_REGS SHARC_REGS;
9292struct _SHARC_REGS
trunk/src/emu/cpu/sharc/sharc.h
r17909r17910
1717   BOOT_MODE_NOBOOT
1818} SHARC_BOOT_MODE;
1919
20typedef struct {
20struct sharc_config {
2121   SHARC_BOOT_MODE boot_mode;
22} sharc_config;
22};
2323
2424extern void sharc_set_flag_input(device_t *device, int flag_num, int state);
2525
trunk/src/emu/cpu/sharc/sharcops.h
r17909r17910
1typedef struct
1struct SHARC_OP
22{
33   UINT32 op_mask;
44   UINT32 op_bits;
55   void (*handler)(SHARC_REGS *cpustate);
6} SHARC_OP;
6};
77
88static const SHARC_OP sharc_opcode_table[] =
99{
trunk/src/emu/cpu/sharc/sharcdsm.h
r17909r17910
6969   "???",   "???",   "???",   "???",   "???",   "???",   "???",   "???"
7070};
7171
72typedef struct
72struct SHARC_DASM_OP
7373{
7474   UINT32 op_mask;
7575   UINT32 op_bits;
7676   UINT32 (* handler)(UINT32, UINT64);
77} SHARC_DASM_OP;
77};
trunk/src/emu/cpu/tms57002/tmsmake.c
r17909r17910
3131
3232enum { PA, PC, PD, PD24, PI, PML, PMO, PMV, PB, PWA, PWC, PWD, SFAI };
3333
34typedef struct {
34struct instr {
3535  char *name;
3636  char *dasm;
3737  char *run;
3838  int line, cycles, type, baseval, variants;
3939  unsigned int flags;
40} instr;
40};
4141
42typedef struct {
42struct pdesc {
4343  const char *opt;
4444  int pcount, id;
45} pdesc;
45};
4646
47typedef struct {
47struct pinf {
4848  const char *start;
4949  int size;
5050  int id;
5151  int pcount;
5252  int ppos[4];
53} pinf;
53};
5454
5555static const pdesc pp_r[] = {
5656  { "a",    0, PA   },
r17909r17910
7474static pinf parse_res[4096];
7575static int parse_count;
7676
77typedef struct {
77struct vinfo {
7878  unsigned int mask;
7979  int variants;
8080  const char *name;
8181  const char *getter;
82} vinfo;
82};
8383
8484enum { IxCMODE, IxDMODE, IxSFAI, IxCRM, IxDBP, IxSFAO, IxSFMO, IxRND, IxMOVM, IxSFMA, IxCOUNT };
8585
trunk/src/emu/cpu/cubeqcpu/cubeqcpu.c
r17909r17910
7171    STRUCTURES & TYPEDEFS
7272***************************************************************************/
7373
74typedef struct
74struct cquestsnd_state
7575{
7676   /* AM2901 internals */
7777   UINT16   ram[16];
r17909r17910
101101   address_space *program;
102102   direct_read_data *direct;
103103   int icount;
104} cquestsnd_state;
104};
105105
106106
107typedef struct
107struct cquestrot_state
108108{
109109   /* AM2901 internals */
110110   UINT16   ram[16];
r17909r17910
143143   address_space *program;
144144   direct_read_data *direct;
145145   int icount;
146} cquestrot_state;
146};
147147
148148
149typedef struct
149struct cquestlin_state
150150{
151151   /* 12-bit AM2901 internals */
152152   UINT16   ram[16];
r17909r17910
190190   address_space *program;
191191   direct_read_data *direct;
192192   int icount;
193} cquestlin_state;
193};
194194
195195/***************************************************************************
196196    STATE ACCESSORS
trunk/src/emu/cpu/upd7810/upd7810.h
r17909r17910
3333typedef int (*upd7810_io_callback)(device_t *device, int ioline, int state);
3434
3535// use it as reset parameter in the Machine struct
36typedef struct {
36struct UPD7810_CONFIG {
3737    UPD7810_TYPE type;
3838    upd7810_io_callback io_callback;
39} UPD7810_CONFIG;
39};
4040
4141enum
4242{
trunk/src/emu/cpu/minx/minx.c
r17909r17910
6565#define EXEC_01 0x01
6666
6767
68typedef struct {
68struct minx_state {
6969//  MINX_CONFIG  config;
7070   UINT16   PC;
7171   UINT16   SP;
r17909r17910
8787   legacy_cpu_device *device;
8888   address_space *program;
8989   int icount;
90} minx_state;
90};
9191
9292#define RD(offset)      minx->program->read_byte( offset )
9393#define WR(offset,data)   minx->program->write_byte( offset, data )
trunk/src/emu/cpu/dsp56k/dsp56pcu.c
r17909r17910
236236/***************************************************************************
237237    INTERRUPT HANDLING
238238***************************************************************************/
239typedef struct
239struct dsp56k_irq_data
240240{
241241   UINT16 irq_vector;
242242   char   irq_source[128];
243} dsp56k_irq_data;
243};
244244
245245dsp56k_irq_data dsp56k_interrupt_sources[32];
246246
trunk/src/emu/cpu/dsp56k/dsp56k.h
r17909r17910
3030    STRUCTURES & TYPEDEFS
3131***************************************************************************/
3232// 5-4 Host Interface
33typedef struct
33struct dsp56k_host_interface
3434{
3535   // **** Dsp56k side **** //
3636   // Host Control Register
r17909r17910
6262   // HACK - Host interface bootstrap write offset
6363   UINT16 bootstrap_offset;
6464
65} dsp56k_host_interface;
65};
6666
6767// 1-9 ALU
68typedef struct
68struct dsp56k_data_alu
6969{
7070   // Four 16-bit input registers (can be accessed as 2 32-bit registers)
7171   PAIR x;
r17909r17910
7979   // One data bus shifter/limiter
8080   // A parallel, single cycle, non-pipelined Multiply-Accumulator (MAC) unit
8181   // Basics
82} dsp56k_data_alu;
82};
8383
8484// 1-10 Address Generation Unit (AGU)
85typedef struct
85struct dsp56k_agu
8686{
8787   // Four address registers
8888   UINT16 r0;
r17909r17910
109109   // UINT8 status;
110110
111111   // Basics
112} dsp56k_agu;
112};
113113
114114// 1-11 Program Control Unit (PCU)
115typedef struct
115struct dsp56k_pcu
116116{
117117   // Program Counter
118118   UINT16 pc;
r17909r17910
146146   // Other PCU internals
147147   UINT16 reset_vector;
148148
149} dsp56k_pcu;
149};
150150
151151// 1-8 The dsp56156 CORE
152typedef struct
152struct dsp56k_core
153153{
154154   // PROGRAM CONTROLLER
155155   dsp56k_pcu PCU;
r17909r17910
197197
198198   UINT16 peripheral_ram[0x40];
199199   UINT16 program_ram[0x800];
200} dsp56k_core;
200};
201201
202202
203203INLINE dsp56k_core *get_safe_token(device_t *device)
trunk/src/emu/cpu/spc700/spc700ds.c
r17909r17910
2020
2121
2222
23typedef struct
23struct opcode_struct
2424{
2525   unsigned char name;
2626   unsigned char args[2];
27} opcode_struct;
27};
2828
2929enum
3030{
trunk/src/emu/cpu/spc700/spc700.c
r17909r17910
6666#include "spc700.h"
6767
6868/* CPU Structure */
69typedef struct
69struct spc700i_cpu
7070{
7171   uint a;      /* Accumulator */
7272   uint x;      /* Index Register X */
r17909r17910
9696   uint temp1, temp2, temp3;
9797   short spc_int16;
9898   int spc_int32;
99} spc700i_cpu;
99};
100100
101101INLINE spc700i_cpu *get_safe_token(device_t *device)
102102{
trunk/src/emu/cpu/hd6309/6309dasm.c
r17909r17910
2525#include "hd6309.h"
2626
2727// Opcode structure
28typedef struct
28struct opcodeinfo
2929{
3030   UINT8   opcode;      // 8-bit opcode value
3131   UINT8   length;      // Opcode length in bytes
3232   char    name[6];   // Opcode name
3333   UINT8   mode;      // Addressing mode
3434   unsigned flags;      // Disassembly flags
35} opcodeinfo;
35};
3636
3737enum hd6309_addressing_modes
3838{
trunk/src/emu/cpu/i860/i860dec.c
r17909r17910
40734073};
40744074
40754075
4076typedef struct {
4076struct decode_tbl_t {
40774077   /* Execute function for this opcode.  */
40784078   void (*insn_exec)(i860s *, UINT32);
40794079
40804080   /* Flags for this opcode.  */
40814081   char flags;
4082} decode_tbl_t;
4082};
40834083
40844084
40854085/* First-level decode table (i.e., for the 6 primary opcode bits).  */
trunk/src/emu/cpu/i860/i860dis.c
r17909r17910
374374};
375375
376376
377typedef struct
377struct decode_tbl_t
378378{
379379   /* Disassembly function for this opcode.
380380       Call with buffer, mnemonic, pc, insn.  */
r17909r17910
386386    /* Mnemonic of this opcode (sometimes partial when more decode is
387387       done in disassembly routines-- e.g., loads and stores).  */
388388   const char *mnemonic;
389} decode_tbl_t;
389};
390390
391391
392392/* First-level decode table (i.e., for the 6 primary opcode bits).  */
trunk/src/emu/cpu/i386/i386dasm.c
r17909r17910
9090#define SPECIAL64         0x800
9191#define SPECIAL64_ENT(x)   (SPECIAL64 | ((x) << 24))
9292
93typedef struct {
93struct I386_OPCODE {
9494   const char *mnemonic;
9595   UINT32 flags;
9696   UINT32 param1;
9797   UINT32 param2;
9898   UINT32 param3;
9999   offs_t dasm_flags;
100} I386_OPCODE;
100};
101101
102typedef struct {
102struct GROUP_OP {
103103   char mnemonic[32];
104104   const I386_OPCODE *opcode;
105} GROUP_OP;
105};
106106
107107static const UINT8 *opcode_ptr;
108108static const UINT8 *opcode_ptr_base;
trunk/src/emu/cpu/i386/i386priv.h
r17909r17910
197197#define MXCSR_RC  (3<<13) // Rounding Control
198198#define MXCSR_FZ  (1<<15) // Flush to Zero
199199
200typedef struct {
200struct I386_SREG {
201201   UINT16 selector;
202202   UINT16 flags;
203203   UINT32 base;
204204   UINT32 limit;
205205   int d;      // Operand size
206206   bool valid;
207} I386_SREG;
207};
208208
209typedef struct
209struct I386_CALL_GATE
210210{
211211   UINT16 segment;
212212   UINT16 selector;
r17909r17910
215215   UINT8 dpl;
216216   UINT8 dword_count;
217217   UINT8 present;
218} I386_CALL_GATE;
218};
219219
220typedef struct {
220struct I386_SYS_TABLE {
221221   UINT32 base;
222222   UINT16 limit;
223} I386_SYS_TABLE;
223};
224224
225typedef struct {
225struct I386_SEG_DESC {
226226   UINT16 segment;
227227   UINT16 flags;
228228   UINT32 base;
229229   UINT32 limit;
230} I386_SEG_DESC;
230};
231231
232232typedef union {
233233   UINT32 d[8];
r17909r17910
420420
421421/***********************************************************************************/
422422
423typedef struct {
423struct MODRM_TABLE {
424424   struct {
425425      int b;
426426      int w;
r17909r17910
431431      int w;
432432      int d;
433433   } rm;
434} MODRM_TABLE;
434};
435435
436436extern MODRM_TABLE i386_MODRM_table[256];
437437
trunk/src/emu/cpu/i386/i386ops.h
r17909r17910
1typedef struct {
1struct X86_OPCODE {
22   UINT8 opcode;
33   UINT32 flags;
44   void (*handler16)(i386_state *cpustate);
55   void (*handler32)(i386_state *cpustate);
6} X86_OPCODE;
6};
77
88#define OP_I386         0x1
99#define OP_FPU         0x2
trunk/src/emu/cpu/i386/cycles.h
r17909r17910
337337#define CPU_CYCLES_MEDIAGX      3
338338
339339
340typedef struct
340struct X86_CYCLE_TABLE
341341{
342342   X86_CYCLES op;
343343   UINT8 cpu_cycles[X86_NUM_CPUS][2];
344} X86_CYCLE_TABLE;
344};
345345
346346static const X86_CYCLE_TABLE x86_cycle_table[] =
347347{
trunk/src/emu/cpu/mc68hc11/hc11dasm.c
r17909r17910
2626   PAGE4,
2727};
2828
29typedef struct {
29struct M68HC11_OPCODE {
3030   char mnemonic[32];
3131   int address_mode;
32} M68HC11_OPCODE;
32};
3333
3434static const M68HC11_OPCODE opcode_table[256] =
3535{
trunk/src/emu/cpu/hcd62121/hcd62121d.c
r17909r17910
3232   _4,         /* for nibble shifts */
3333};
3434
35typedef struct
35struct hcd62121_dasm
3636{
3737   const char *str;
3838   UINT8      arg1;
3939   UINT8      arg2;
40} hcd62121_dasm;
40};
4141
4242
4343static const hcd62121_dasm hcd62121_ops[256] =
trunk/src/emu/cpu/tlcs900/900tbl.c
r17909r17910
38523852}
38533853
38543854
3855typedef struct
3855struct tlcs900inst
38563856{
38573857   void (*opfunc)(tlcs900_state *cpustate);
38583858   int      operand1;
38593859   int      operand2;
38603860   int      cycles;
3861} tlcs900inst;
3861};
38623862
38633863
38643864static void prepare_operands(tlcs900_state *cpustate, const tlcs900inst *inst)
trunk/src/emu/cpu/tlcs900/dasm900.c
r17909r17910
8888};
8989
9090
91typedef struct
91struct tlcs900inst
9292{
9393   e_mnemonics   mnemonic;
9494   e_operand   operand1;
9595   e_operand   operand2;
96} tlcs900inst;
96};
9797
9898
9999static const tlcs900inst mnemonic_80[256] =
trunk/src/emu/cpu/scudsp/scudspdasm.c
r17909r17910
2626   EA_MVIDSTMEM,
2727};
2828
29typedef struct {
29struct SCUDSP_OPCODE {
3030   char mnemonic[32];
3131   int address_mode_1;
3232   int address_mode_2;
3333   int address_mode_3,
34} SCUDSP_OPCODE;
34};
3535
3636static const SCUDSP_OPCODE alu_table[16] =
3737{
trunk/src/emu/cpu/arm/arm.c
r17909r17910
227227/* Private Data */
228228
229229/* sArmRegister defines the CPU state */
230typedef struct
230struct ARM_REGS
231231{
232232   int icount;
233233   UINT32 sArmRegister[kNumRegisters];
r17909r17910
239239   address_space *program;
240240   direct_read_data *direct;
241241   endianness_t endian;
242} ARM_REGS;
242};
243243
244244/* Prototypes */
245245static void HandleALU( ARM_REGS* cpustate, UINT32 insn);
trunk/src/emu/cpu/powerpc/ppc.c
r17909r17910
195195#define BYTE_REVERSE16(x)   ((((x) >> 8) & 0xff) | (((x) << 8) & 0xff00))
196196#define BYTE_REVERSE32(x)   ((((x) >> 24) & 0xff) | (((x) >> 8) & 0xff00) | (((x) << 8) & 0xff0000) | (((x) << 24) & 0xff000000))
197197
198typedef struct {
198struct DMA_REGS {
199199   UINT32 cr;
200200   UINT32 da;
201201   UINT32 sa;
202202   UINT32 ct;
203203   UINT32 cc;
204} DMA_REGS;
204};
205205
206typedef struct {
206struct SPU_REGS {
207207   UINT8 spls;
208208   UINT8 sphs;
209209   UINT16 brd;
r17909r17910
214214   UINT8 sptb;
215215   emu_timer *rx_timer;
216216   emu_timer *tx_timer;
217} SPU_REGS;
217};
218218
219219typedef union {
220220   UINT64   id;
r17909r17910
226226   float f;
227227} FPR32;
228228
229typedef struct {
229struct BATENT {
230230   UINT32 u;
231231   UINT32 l;
232} BATENT;
232};
233233
234234
235typedef struct {
235struct PPC_REGS {
236236   UINT32 r[32];
237237   UINT32 pc;
238238   UINT32 npc;
r17909r17910
350350   void (* optable59[1024])(UINT32);
351351   void (* optable63[1024])(UINT32);
352352   void (* optable[64])(UINT32);
353} PPC_REGS;
353};
354354
355355
356356
357typedef struct {
357struct PPC_OPCODE {
358358   int code;
359359   int subcode;
360360   void (* handler)(UINT32);
361} PPC_OPCODE;
361};
362362
363363
364364
trunk/src/emu/cpu/powerpc/ppc_dasm.c
r17909r17910
102102 * Describes the layout of an instruction.
103103 */
104104
105typedef struct
105struct IDESCR
106106{
107107   char   mnem[32];   // mnemonic
108108   UINT32   match;      // bit pattern of instruction after it has been masked
r17909r17910
110110                  // bit pattern to determine a match)
111111   int   format;         // operand format
112112   int   flags;         // flags
113} IDESCR;
113};
114114
115115/*
116116 * Instruction Table
trunk/src/emu/cpu/sm8500/sm8500.h
r17909r17910
44#define __SM8500_H__
55
66
7typedef struct {
7struct SM8500_CONFIG {
88   void (*handle_dma)(device_t *device, int cycles);
99   void (*handle_timers)(device_t *device, int cycles);
10} SM8500_CONFIG;
10};
1111
1212/* interrupts */
1313#define ILL_INT         0
trunk/src/emu/cpu/sh2/sh2comn.h
r17909r17910
9090      sh2_exception(sh2,message,irq);         \
9191} while(0)
9292
93typedef struct
93struct sh2_state
9494{
9595   UINT32   ppc;
9696   UINT32   pc;
r17909r17910
182182   uml::code_handle *   nocode;               /* nocode */
183183   uml::code_handle *   out_of_cycles;            /* out of cycles exception handler */
184184#endif
185} sh2_state;
185};
186186
187187#ifdef USE_SH2DRC
188188class sh2_frontend : public drc_frontend
trunk/src/emu/cpu/tms32051/tms32051.c
r17909r17910
4646   TMS32051_AR7,
4747};
4848
49typedef struct
49struct PMST
5050{
5151   UINT16 iptr;
5252   UINT16 avis;
r17909r17910
5656   UINT16 ndx;
5757   UINT16 trm;
5858   UINT16 braf;
59} PMST;
59};
6060
61typedef struct
61struct ST0
6262{
6363   UINT16 dp;
6464   UINT16 intm;
6565   UINT16 ovm;
6666   UINT16 ov;
6767   UINT16 arp;
68} ST0;
68};
6969
70typedef struct
70struct ST1
7171{
7272   UINT16 arb;
7373   UINT16 cnf;
r17909r17910
7777   UINT16 hm;
7878   UINT16 xf;
7979   UINT16 pm;
80} ST1;
80};
8181
8282struct tms32051_state
8383{
trunk/src/emu/cpu/sh4/sh4comn.h
r17909r17910
4949#endif
5050
5151
52typedef struct
52struct sh4_state
5353{
5454   UINT32   ppc;
5555   UINT32   pc, spc;
r17909r17910
208208   UINT32 prefadr;
209209   UINT32 target;
210210#endif
211} sh4_state;
211};
212212
213213#ifdef USE_SH4DRC
214214class sh4_frontend : public drc_frontend
trunk/src/emu/cpu/alph8201/8201dasm.c
r17909r17910
259259
260260#define MAX_OPS (((sizeof(Formats) / sizeof(Formats[0])) - 1) / PTRS_PER_FORMAT)
261261
262typedef struct opcode {
262struct AD8201Opcode {
263263   byte mask;
264264   byte bits;
265265   byte type;
266266   byte pmask;
267267   byte pdown;
268268   const char *fmt;
269} AD8201Opcode;
269};
270270
271271static AD8201Opcode Op[MAX_OPS+1];
272272static int OpInizialized = 0;
trunk/src/emu/cpu/g65816/g65816ds.c
r17909r17910
2626#define ADDRESS_65816(A) ((A)&0xffffff)
2727
2828
29typedef struct
29struct opcode_struct
3030{
3131   unsigned char name;
3232   unsigned char flag;
3333   unsigned char ea;
34} opcode_struct;
34};
3535
3636enum
3737{
trunk/src/emu/cpu/nec/necdasm.c
r17909r17910
7474   SEG_SS
7575};
7676
77typedef struct {
77struct I386_OPCODE {
7878   char mnemonic[32];
7979   UINT32 flags;
8080   UINT32 param1;
8181   UINT32 param2;
8282   UINT32 param3;
8383   offs_t dasm_flags;
84} I386_OPCODE;
84};
8585
86typedef struct {
86struct GROUP_OP {
8787   char mnemonic[32];
8888   const I386_OPCODE *opcode;
89} GROUP_OP;
89};
9090
9191static const UINT8 *opcode_ptr;
9292static const UINT8 *opcode_ptr_base;
trunk/src/emu/cpu/mips/mips3.c
r17909r17910
8686***************************************************************************/
8787
8888/* MIPS3 Registers */
89typedef struct
89struct mips3_regs
9090{
9191   /* core state */
9292   mips3_state   core;
r17909r17910
112112   void      (*ldr)(UINT32 op);
113113   void      (*sdl)(UINT32 op);
114114   void      (*sdr)(UINT32 op);
115} mips3_regs;
115};
116116
117117
118118
trunk/src/emu/cpu/tms7000/7000dasm.c
r17909r17910
44
55typedef enum { DONE, NONE, UI8, I8, UI16, I16, PCREL, PCABS, TRAP } operandtype;
66
7typedef struct {
7struct oprandinfo {
88   char      opstr[4][12];
99   operandtype   decode[4];
10} oprandinfo;
10};
1111
12typedef struct {
12struct opcodeinfo {
1313   int      opcode;
1414   char      name[8];
1515   int      operand;
1616   UINT32      s_flag;
17} opcodeinfo;
17};
1818
1919static const oprandinfo of[] = {
2020/* 00 */ { {" B,A",      "",         "",         ""},      {NONE, DONE, DONE, DONE} },
trunk/src/emu/cpu/esrip/esrip.c
r17909r17910
6161    STRUCTURES & TYPEDEFS
6262***************************************************************************/
6363
64typedef struct
64struct esrip_state
6565{
6666   UINT16   ram[32];
6767   UINT16   acc;
r17909r17910
118118   write16_device_func   fdt_w;
119119   UINT8 (*status_in)(running_machine &machine);
120120   int (*draw)(running_machine &machine, int l, int r, int fig, int attr, int addr, int col, int x_scale, int bank);
121} esrip_state;
121};
122122
123123
124124INLINE esrip_state *get_safe_token(device_t *device)
trunk/src/emu/cpu/i960/i960dis.c
r17909r17910
88#include "i960.h"
99#include "i960dis.h"
1010
11typedef struct
11struct mnemonic_t
1212{
1313   const char      *mnem;
1414   unsigned short   type;
15} mnemonic_t;
15};
1616
1717
1818static const mnemonic_t mnemonic[256] = {
trunk/src/emu/cpu/hd61700/hd61700d.c
r17909r17910
3939   OP_RSIR,
4040};
4141
42typedef struct
42struct hd61700_dasm
4343{
4444   const char *str;
4545   UINT8      arg1;
4646   UINT8      arg2;
4747   bool      optjr;
48} hd61700_dasm;
48};
4949
5050static const hd61700_dasm hd61700_ops[256] =
5151{
trunk/src/emu/cpu/arm7/arm7core.h
r17909r17910
185185
186186
187187/* CPU state struct */
188typedef struct
188struct arm_state
189189{
190190   ARM7CORE_REGS         // these must be included in your cpu specific register implementation
191191   ARM7COPRO_REGS
r17909r17910
196196#if ARM7_MMU_ENABLE_HACK
197197   UINT32 mmu_enable_addr;   // workaround for "MMU is enabled when PA != VA" problem
198198#endif
199} arm_state;
199};
200200
201201/****************************************************************************************************
202202 *  VARIOUS INTERNAL STRUCS/DEFINES/ETC..
trunk/src/emu/cpu/h6280/h6280.h
r17909r17910
3737/****************************************************************************
3838 * The 6280 registers.
3939 ****************************************************************************/
40typedef struct
40struct h6280_Regs
4141{
4242   int ICount;
4343
r17909r17910
7070    INT32 NZ;         /* last value (lazy N and Z flag) */
7171#endif
7272   UINT8 io_buffer;   /* last value written to the PSG, timer, and interrupt pages */
73} h6280_Regs;
73};
7474
7575
7676DECLARE_LEGACY_CPU_DEVICE(H6280, h6280);
trunk/src/emu/cpu/saturn/saturnds.c
r17909r17910
586586};
587587typedef enum _opcode_adr opcode_adr;
588588
589typedef struct
589struct OPCODE
590590{
591591   opcode_sel sel;
592592   opcode_adr adr;
593593   MNEMONICS mnemonic;
594} OPCODE;
594};
595595
596596static const char *field_2_string(int adr_enum)
597597{
trunk/src/emu/cpu/konami/knmidasm.c
r17909r17910
15811581
15821582*********************************************************************************/
15831583
1584typedef struct {
1584struct konami_opcode_def {
15851585   void (*decode)( char *buf );
15861586   int confirmed;
1587} konami_opcode_def;
1587};
15881588
15891589static const konami_opcode_def op_table[256] = {
15901590   /* 00 */   { illegal, 0 },
trunk/src/emu/video/vector.c
r17909r17910
127127#define VCLIP   2
128128
129129/* The vertices are buffered here */
130typedef struct
130struct point
131131{
132132   int x; int y;
133133   rgb_t col;
134134   int intensity;
135135   int arg1; int arg2; /* start/end in pixel array or clipping info */
136136   int status;         /* for dirty and clipping handling */
137} point;
137};
138138
139139
140140
trunk/src/emu/video/rgbgen.h
r17909r17910
1818***************************************************************************/
1919
2020/* intermediate RGB values are stored in a struct */
21typedef struct { INT16 dummy, r, g, b; } rgbint;
21struct rgbint { INT16 dummy, r, g, b; };
2222
2323/* intermediate RGB values are stored in a struct */
24typedef struct { INT16 a, r, g, b; } rgbaint;
24struct rgbaint { INT16 a, r, g, b; };
2525
2626
2727
trunk/src/emu/sound/ym2413.c
r17909r17910
164164
165165
166166
167typedef struct
167struct OPLL_SLOT
168168{
169169   UINT32   ar;         /* attack rate: AR<<2           */
170170   UINT32   dr;         /* decay rate:  DR<<2           */
r17909r17910
207207
208208   /* waveform select */
209209   unsigned int wavetable;
210} OPLL_SLOT;
210};
211211
212typedef struct
212struct OPLL_CH
213213{
214214   OPLL_SLOT SLOT[2];
215215   /* phase generator state */
r17909r17910
218218   UINT32  ksl_base;   /* KeyScaleLevel Base step      */
219219   UINT8   kcode;      /* key code (for key scaling)   */
220220   UINT8   sus;      /* sus on/off (release speed in percussive mode)*/
221} OPLL_CH;
221};
222222
223223/* chip state */
224typedef struct
224struct YM2413
225225{
226226   OPLL_CH   P_CH[9];            /* OPLL chips have 9 channels*/
227227   UINT8   instvol_r[9];         /* instrument/volume (or volume/volume in percussive mode)*/
r17909r17910
272272   signed int output[2];
273273   signed int outchan;
274274
275} YM2413;
275};
276276
277277/* key scale level */
278278/* table is 3dB/octave, DV converts this into 6dB/octave */
trunk/src/emu/sound/fm2612.c
r17909r17910
531531
532532
533533/* struct describing a single operator (SLOT) */
534typedef struct
534struct FM_SLOT
535535{
536536   INT32   *DT;      /* detune          :dt_tab[DT] */
537537   UINT8   KSR;      /* key scale rate  :3-KSR */
r17909r17910
570570   /* LFO */
571571   UINT32   AMmask;      /* AM enable flag */
572572
573} FM_SLOT;
573};
574574
575typedef struct
575struct FM_CH
576576{
577577   FM_SLOT   SLOT[4];   /* four SLOTs (operators) */
578578
r17909r17910
594594   UINT32   fc;         /* fnum,blk:adjusted to sample rate */
595595   UINT8   kcode;      /* key code:                        */
596596   UINT32   block_fnum;   /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
597} FM_CH;
597};
598598
599599
600typedef struct
600struct FM_ST
601601{
602602   device_t *device;
603603   void *      param;            /* this chip parameter  */
r17909r17910
625625   FM_TIMERHANDLER   timer_handler;
626626   FM_IRQHANDLER   IRQ_Handler;
627627   const ssg_callbacks *SSG;
628} FM_ST;
628};
629629
630630
631631
r17909r17910
634634/***********************************************************/
635635
636636/* OPN 3slot struct */
637typedef struct
637struct FM_3SLOT
638638{
639639   UINT32  fc[3];         /* fnum3,blk3: calculated */
640640   UINT8   fn_h;         /* freq3 latch */
641641   UINT8   kcode[3];      /* key code */
642642   UINT32   block_fnum[3];   /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
643643   UINT8   key_csm;        /* CSM mode Key-ON flag */
644} FM_3SLOT;
644};
645645
646646/* OPN/A/B common state */
647typedef struct
647struct FM_OPN
648648{
649649   UINT8   type;         /* chip type */
650650   FM_ST   ST;            /* general state */
r17909r17910
675675   INT32   mem;         /* one sample delay memory */
676676   INT32   out_fm[8];      /* outputs of working channels */
677677
678} FM_OPN;
678};
679679
680680/* here's the virtual YM2612 */
681typedef struct
681struct YM2612
682682{
683683   UINT8      REGS[512];         /* registers            */
684684   FM_OPN      OPN;            /* OPN state            */
r17909r17910
688688   /* dac output (YM2612) */
689689   int         dacen;
690690   INT32      dacout;
691} YM2612;
691};
692692
693693/* log output level */
694694#define LOG_ERR  3      /* ERROR       */
trunk/src/emu/sound/c352.h
r17909r17910
6363       C352_FLG_REVERSE   = 0x0001,   // play sample backwards
6464    };
6565
66    typedef struct
66    struct c352_ch_t
6767    {
6868       UINT8   vol_l;
6969       UINT8   vol_r;
r17909r17910
8383       UINT16   repeat;
8484       UINT32   current_addr;
8585       UINT32   pos;
86    } c352_ch_t;
86    };
8787
8888   c352_ch_t m_c352_ch[32];
8989   int m_sample_rate_base;
trunk/src/emu/sound/k051649.c
r17909r17910
3030
3131
3232/* this structure defines the parameters for a channel */
33typedef struct
33struct k051649_sound_channel
3434{
3535   unsigned long counter;
3636   int frequency;
3737   int volume;
3838   int key;
3939   signed char waveram[32];
40} k051649_sound_channel;
40};
4141
4242struct k051649_state
4343{
trunk/src/emu/sound/c140.c
r17909r17910
6565   UINT8 reserved[4];
6666};
6767
68typedef struct
68struct VOICE
6969{
7070   long   ptoffset;
7171   long   pos;
r17909r17910
8484   long   sample_start;
8585   long   sample_end;
8686   long   sample_loop;
87} VOICE;
87};
8888
8989struct c140_state
9090{
trunk/src/emu/sound/digitalk.c
r17909r17910
237237*/
238238
239239
240typedef struct {
240struct digitalker {
241241   const UINT8 *rom;
242242   device_t *device;
243243   sound_stream *stream;
r17909r17910
258258   UINT8 dac_index; // 128 for done
259259   INT16 dac[128];
260260
261} digitalker;
261};
262262
263263// Quantized intensity values, first index is the volume, second the
264264// intensity (positive half only, real value goes -8..7)
trunk/src/emu/sound/ymz770.h
r17909r17910
3434
3535class ymz770_device : public device_t, public device_sound_interface
3636{
37    typedef struct
37    struct ymz_channel
3838    {
3939        UINT8 phrase;
4040        UINT8 pan;
r17909r17910
5555       UINT8 *seqdata;
5656       bool is_seq_playing;
5757
58    } ymz_channel;
58    };
5959
6060
6161public:
trunk/src/emu/sound/k005289.c
r17909r17910
3131#define FREQBASEBITS   16
3232
3333/* this structure defines the parameters for a channel */
34typedef struct
34struct k005289_sound_channel
3535{
3636   int frequency;
3737   int counter;
3838   int volume;
3939   const unsigned char *wave;
40} k005289_sound_channel;
40};
4141
4242struct k005289_state
4343{
trunk/src/emu/sound/ymf262.c
r17909r17910
141141#define OPL3_TYPE_YMF262 (0)   /* 36 operators, 8 waveforms */
142142
143143
144typedef struct
144struct OPL3_SLOT
145145{
146146   UINT32   ar;         /* attack rate: AR<<2           */
147147   UINT32   dr;         /* decay rate:  DR<<2           */
r17909r17910
190190//unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2
191191unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2
192192
193} OPL3_SLOT;
193};
194194
195typedef struct
195struct OPL3_CH
196196{
197197   OPL3_SLOT SLOT[2];
198198
r17909r17910
215215
216216unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2
217217
218} OPL3_CH;
218};
219219
220220/* OPL3 state */
221typedef struct
221struct OPL3
222222{
223223   OPL3_CH   P_CH[18];            /* OPL3 chips have 18 channels  */
224224
r17909r17910
278278   double freqbase;            /* frequency base               */
279279   attotime TimerBase;         /* Timer base time (==sampling time)*/
280280   device_t *device;
281} OPL3;
281};
282282
283283
284284
trunk/src/emu/sound/i5000.h
r17909r17910
4747   virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples);
4848
4949private:
50    typedef struct
50    struct channel_t
5151    {
5252        bool is_playing;
5353       oki_adpcm_state m_adpcm;
r17909r17910
6565        int output_r;
6666        int output_l;
6767
68    } channel_t;
68    };
6969
7070    channel_t m_channels[16];
7171
trunk/src/emu/sound/x1_010.c
r17909r17910
6767#define   VOL_BASE   (2*32*256/30)               // Volume base
6868
6969/* this structure defines the parameters for a channel */
70typedef struct {
70struct X1_010_CHANNEL {
7171   unsigned char   status;
7272   unsigned char   volume;                  //        volume / wave form no.
7373   unsigned char   frequency;               //     frequency / pitch lo
r17909r17910
7575   unsigned char   start;                  // start address / envelope time
7676   unsigned char   end;                  //   end address / envelope no.
7777   unsigned char   reserve[2];
78} X1_010_CHANNEL;
78};
7979
8080struct x1_010_state
8181{
trunk/src/emu/sound/ymf271.c
r17909r17910
3333
3434//#define log2(n) (log((float) n)/log((float) 2))
3535
36typedef struct
36struct YMF271Slot
3737{
3838   INT8  extout;
3939   UINT8 lfoFreq;
r17909r17910
8080   INT32 lfo_phase, lfo_step;
8181   INT32 lfo_amplitude;
8282   double lfo_phasemod;
83} YMF271Slot;
83};
8484
85typedef struct
85struct YMF271Group
8686{
8787   INT8 sync, pfm;
88} YMF271Group;
88};
8989
90typedef struct
90struct YMF271Chip
9191{
9292   YMF271Slot slots[48];
9393   YMF271Group groups[12];
r17909r17910
112112   UINT32 clock;
113113   sound_stream * stream;
114114   device_t *device;
115} YMF271Chip;
115};
116116
117117// slot mapping assists
118118static const int fm_tab[] = { 0, 1, 2, -1, 3, 4, 5, -1, 6, 7, 8, -1, 9, 10, 11, -1 };
trunk/src/emu/sound/n63701x.c
r17909r17910
1717#include "n63701x.h"
1818
1919
20typedef struct
20struct voice
2121{
2222   int select;
2323   int playing;
r17909r17910
2525   int position;
2626   int volume;
2727   int silence_counter;
28} voice;
28};
2929
3030
3131struct namco_63701x
trunk/src/emu/sound/ym2151.c
r17909r17910
2323
2424
2525/* struct describing a single operator */
26typedef struct
26struct YM2151Operator
2727{
2828   UINT32      phase;               /* accumulated operator phase */
2929   UINT32      freq;               /* operator frequency count */
r17909r17910
7373   UINT32      reserved0;            /**/
7474   UINT32      reserved1;            /**/
7575
76} YM2151Operator;
76};
7777
7878
79typedef struct
79struct YM2151
8080{
8181   signed int chanout[8];
8282   signed int m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
r17909r17910
168168   device_t *device;
169169   unsigned int clock;               /* chip clock in Hz (passed from 2151intf.c) */
170170   unsigned int sampfreq;            /* sampling frequency in Hz (passed from 2151intf.c) */
171} YM2151;
171};
172172
173173
174174#define FREQ_SH         16  /* 16.16 fixed point (frequency calculations) */
trunk/src/emu/sound/c6280.c
r17909r17910
5656#include "emu.h"
5757#include "c6280.h"
5858
59typedef struct {
59struct t_channel {
6060    UINT16 frequency;
6161    UINT8 control;
6262    UINT8 balance;
r17909r17910
6666    UINT8 noise_control;
6767    UINT32 noise_counter;
6868    UINT32 counter;
69} t_channel;
69};
7070
71typedef struct {
71struct c6280_t {
7272   sound_stream *stream;
7373   device_t *device;
7474   device_t *cpudevice;
r17909r17910
8080    INT16 volume_table[32];
8181    UINT32 noise_freq_tab[32];
8282    UINT32 wave_freq_tab[4096];
83} c6280_t;
83};
8484
8585INLINE c6280_t *get_safe_token(device_t *device)
8686{
trunk/src/emu/sound/discrete.c
r17909r17910
8383 *
8484 *************************************/
8585
86typedef struct
86struct output_buffer
8787{
8888   double                  *node_buf;
8989   const double            *source;
9090   volatile double            *ptr;
9191   int                     node_num;
92} output_buffer;
92};
9393
94typedef struct
94struct input_buffer
9595{
9696   volatile const double      *ptr;            /* pointer into linked_outbuf.nodebuf */
9797   output_buffer *            linked_outbuf;      /* what output are we connected to ? */
9898   double                  buffer;            /* input[] will point here */
99} input_buffer;
99};
100100
101101class discrete_task
102102{
trunk/src/emu/sound/msm5232.c
r17909r17910
99    8 channel tone generator
1010*/
1111
12typedef struct {
12struct VOICE {
1313   UINT8 mode;
1414
1515   int      TG_count_period;
r17909r17910
3535   int      pitch;         /* current pitch data */
3636
3737   int GF;
38} VOICE;
38};
3939
4040
41typedef struct {
41struct msm5232_state {
4242   sound_stream *stream;
4343
4444   VOICE   voi[8];
r17909r17910
7171   device_t *device;
7272   void (*gate_handler)(device_t *device, int state);   /* callback called when the GATE output pin changes state */
7373
74} msm5232_state;
74};
7575
7676
7777INLINE msm5232_state *get_safe_token(device_t *device)
trunk/src/emu/sound/fmopl.c
r17909r17910
198198
199199
200200
201typedef struct
201struct OPL_SLOT
202202{
203203   UINT32   ar;         /* attack rate: AR<<2           */
204204   UINT32   dr;         /* decay rate:  DR<<2           */
r17909r17910
237237
238238   /* waveform select */
239239   UINT16   wavetable;
240} OPL_SLOT;
240};
241241
242typedef struct
242struct OPL_CH
243243{
244244   OPL_SLOT SLOT[2];
245245   /* phase generator state */
r17909r17910
247247   UINT32  fc;         /* Freq. Increment base         */
248248   UINT32  ksl_base;   /* KeyScaleLevel Base step      */
249249   UINT8   kcode;      /* key code (for key scaling)   */
250} OPL_CH;
250};
251251
252252/* OPL state */
253typedef struct
253struct FM_OPL
254254{
255255   /* FM channel slots */
256256   OPL_CH   P_CH[9];            /* OPL/OPL2 chips have 9 channels*/
r17909r17910
325325#if BUILD_Y8950
326326   INT32 output_deltat[4];      /* for Y8950 DELTA-T, chip is mono, that 4 here is just for safety */
327327#endif
328} FM_OPL;
328};
329329
330330
331331
trunk/src/emu/sound/s14001a.c
r17909r17910
237237#include "emu.h"
238238#include "s14001a.h"
239239
240typedef struct
240struct S14001AChip
241241{
242242   sound_stream * stream;
243243
r17909r17910
262262   UINT8 *SpeechRom; // array to hold rom contents, mame will not need this, will use a pointer
263263   INT16 filtervals[8];
264264   UINT8 VSU1000_amp; // amplitude setting on VSU-1000 board
265} S14001AChip;
265};
266266
267267INLINE S14001AChip *get_safe_token(device_t *device)
268268{
trunk/src/emu/sound/fm.c
r17909r17910
519519
520520
521521/* struct describing a single operator (SLOT) */
522typedef struct
522struct FM_SLOT
523523{
524524   INT32   *DT;      /* detune          :dt_tab[DT] */
525525   UINT8   KSR;      /* key scale rate  :3-KSR */
r17909r17910
558558   /* LFO */
559559   UINT32   AMmask;      /* AM enable flag */
560560
561} FM_SLOT;
561};
562562
563typedef struct
563struct FM_CH
564564{
565565   FM_SLOT   SLOT[4];   /* four SLOTs (operators) */
566566
r17909r17910
582582   UINT32   fc;         /* fnum,blk:adjusted to sample rate */
583583   UINT8   kcode;      /* key code:                        */
584584   UINT32   block_fnum;   /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
585} FM_CH;
585};
586586
587587
588typedef struct
588struct FM_ST
589589{
590590   device_t *device;
591591   void *      param;            /* this chip parameter  */
r17909r17910
613613   FM_TIMERHANDLER   timer_handler;
614614   FM_IRQHANDLER   IRQ_Handler;
615615   const ssg_callbacks *SSG;
616} FM_ST;
616};
617617
618618
619619
r17909r17910
622622/***********************************************************/
623623
624624/* OPN 3slot struct */
625typedef struct
625struct FM_3SLOT
626626{
627627   UINT32  fc[3];         /* fnum3,blk3: calculated */
628628   UINT8   fn_h;         /* freq3 latch */
629629   UINT8   kcode[3];      /* key code */
630630   UINT32   block_fnum[3];   /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
631} FM_3SLOT;
631};
632632
633633/* OPN/A/B common state */
634typedef struct
634struct FM_OPN
635635{
636636   UINT8   type;         /* chip type */
637637   FM_ST   ST;            /* general state */
r17909r17910
669669   INT32   out_adpcm[4];   /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 ADPCM */
670670   INT32   out_delta[4];   /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 DELTAT*/
671671#endif
672} FM_OPN;
672};
673673
674674
675675
r17909r17910
20892089/*****************************************************************************/
20902090
20912091/* here's the virtual YM2203(OPN) */
2092typedef struct
2092struct YM2203
20932093{
20942094   UINT8 REGS[256];      /* registers         */
20952095   FM_OPN OPN;            /* OPN state         */
20962096   FM_CH CH[3];         /* channel state     */
2097} YM2203;
2097};
20982098
20992099/* Generate samples for one of the YM2203s */
21002100void ym2203_update_one(void *chip, FMSAMPLE *buffer, int length)
r17909r17910
23852385#if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
23862386
23872387/* ADPCM type A channel struct */
2388typedef struct
2388struct ADPCM_CH
23892389{
23902390   UINT8      flag;         /* port state               */
23912391   UINT8      flagMask;      /* arrived flag mask        */
r17909r17910
24022402   INT8      vol_mul;      /* volume in "0.75dB" steps */
24032403   UINT8      vol_shift;      /* volume in "-6dB" steps   */
24042404   INT32      *pan;         /* &out_adpcm[OPN_xxxx]     */
2405} ADPCM_CH;
2405};
24062406
24072407/* here's the virtual YM2610 */
2408typedef struct
2408struct YM2610
24092409{
24102410   UINT8      REGS[512];         /* registers            */
24112411   FM_OPN      OPN;            /* OPN state            */
r17909r17910
24232423
24242424   UINT8      flagmask;         /* YM2608 only */
24252425   UINT8      irqmask;         /* YM2608 only */
2426} YM2610;
2426};
24272427
24282428/* here is the virtual YM2608 */
24292429typedef YM2610 YM2608;
trunk/src/emu/sound/ymf278b.c
r17909r17910
7171#define VERBOSE 0
7272#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
7373
74typedef struct
74struct YMF278BSlot
7575{
7676   INT16 wave;      /* wavetable number */
7777   INT16 F_NUMBER;   /* frequency */
r17909r17910
111111
112112   int num;      /* slot number (for debug only) */
113113   struct _YMF278BChip *chip;   /* pointer back to parent chip */
114} YMF278BSlot;
114};
115115
116116typedef struct _YMF278BChip
117117{
trunk/src/emu/sound/namco.c
r17909r17910
3636
3737
3838/* this structure defines the parameters for a channel */
39typedef struct
39struct sound_channel
4040{
4141   UINT32 frequency;
4242   UINT32 counter;
r17909r17910
4747   UINT32 noise_counter;
4848   INT32 noise_hold;
4949   INT32 waveform_select;
50} sound_channel;
50};
5151
5252
5353struct namco_sound
trunk/src/emu/sound/es5503.h
r17909r17910
6767       MODE_SWAP = 3
6868    };
6969
70    typedef struct
70    struct ES5503Osc
7171    {
7272       UINT16 freq;
7373       UINT16 wtsize;
r17909r17910
8080
8181       UINT32 accumulator;
8282       UINT8  irqpend;
83    } ES5503Osc;
83    };
8484
8585   ES5503Osc oscillators[32];
8686
trunk/src/emu/machine/pc16552d.c
r17909r17910
3434#define INT_ENABLE_RX_LINE_STATUS   0x04
3535#define INT_ENABLE_MODEM_STATUS      0x08
3636
37typedef struct
37struct PC16552D_CHANNEL
3838{
3939   UINT16 divisor;
4040   UINT8 reg[8];
r17909r17910
4848   int tx_fifo_write_ptr;
4949   int tx_fifo_num;
5050   emu_timer *tx_fifo_timer;
51} PC16552D_CHANNEL;
51};
5252
53typedef struct
53struct PC16552D_REGS
5454{
5555   PC16552D_CHANNEL ch[2];
5656   int frequency;
5757   void (* irq_handler)(running_machine &machine, int channel, int value);
5858   void (* tx_callback)(running_machine &machine, int channel, int count, UINT8* data);
59} PC16552D_REGS;
59};
6060
6161#define MAX_PC16552D_CHIPS      4
6262
trunk/src/emu/machine/scsibus.h
r17909r17910
100100
101101#define SCSI_SENSE_SIZE            4
102102
103typedef struct
103struct adaptec_sense_t
104104{
105105   // parameter list
106106   UINT8      reserved1[3];
r17909r17910
121121   UINT8      step_pulse_code;
122122   UINT8      bit_flags;
123123   UINT8      sectors_per_track;
124} adaptec_sense_t;
124};
125125
126126class scsibus_device : public device_t
127127{
trunk/src/emu/machine/msm6242.h
r17909r17910
3030   devcb_write_line   m_out_int_cb;
3131};
3232
33typedef struct
33struct rtc_regs_t
3434{
3535   UINT8 sec, min, hour, day, wday, month;
3636   UINT16 year;
37} rtc_regs_t;
37};
3838
3939
4040// ======================> msm6242_device
trunk/src/emu/machine/matsucd.c
r17909r17910
2727#define MATSU_STATUS_MEDIA      ( 1 << 6 )   /* media present (in caddy or tray) */
2828#define MATSU_STATUS_DOORCLOSED   ( 1 << 7 )   /* tray status */
2929
30typedef struct
30struct matsucd
3131{
3232   UINT8   enabled;      /* /ENABLE - Unit enabled */
3333   UINT8   cmd_signal;      /* /CMD - Command mode   */
r17909r17910
5353   cdrom_file *cdrom;
5454   device_t *cdda;
5555   emu_timer *frame_timer;
56} matsucd;
56};
5757
5858static matsucd cd;
5959
trunk/src/emu/machine/s3c2440.h
r17909r17910
527527    TYPE DEFINITIONS
528528*******************************************************************************/
529529
530typedef struct
530struct s3c24xx_memcon_regs_t
531531{
532532   UINT32 data[0x34/4];
533} s3c24xx_memcon_regs_t;
533};
534534
535typedef struct
535struct s3c24xx_usbhost_regs_t
536536{
537537   UINT32 data[0x5C/4];
538} s3c24xx_usbhost_regs_t;
538};
539539
540typedef struct
540struct s3c24xx_irq_regs_t
541541{
542542   UINT32 srcpnd;
543543   UINT32 intmod;
r17909r17910
547547   UINT32 intoffset;
548548   UINT32 subsrcpnd;
549549   UINT32 intsubmsk;
550} s3c24xx_irq_regs_t;
550};
551551
552typedef struct
552struct s3c24xx_dma_regs_t
553553{
554554   UINT32 disrc;
555555   UINT32 disrcc;
r17909r17910
560560   UINT32 dcsrc;
561561   UINT32 dcdst;
562562   UINT32 dmasktrig;
563} s3c24xx_dma_regs_t;
563};
564564
565typedef struct
565struct s3c24xx_clkpow_regs_t
566566{
567567   UINT32 locktime;
568568   UINT32 mpllcon;
r17909r17910
571571   UINT32 clkslow;
572572   UINT32 clkdivn;
573573   UINT32 camdivn;
574} s3c24xx_clkpow_regs_t;
574};
575575
576typedef struct
576struct s3c24xx_lcd_regs_t
577577{
578578   UINT32 lcdcon1;
579579   UINT32 lcdcon2;
r17909r17910
593593   UINT32 lcdsrcpnd;
594594   UINT32 lcdintmsk;
595595   UINT32 tconsel;
596} s3c24xx_lcd_regs_t;
596};
597597
598typedef struct
598struct s3c24xx_lcdpal_regs_t
599599{
600600   UINT32 data[0x400/4];
601} s3c24xx_lcdpal_regs_t;
601};
602602
603typedef struct
603struct s3c24xx_nand_regs_t
604604{
605605   UINT32 nfconf;
606606   UINT32 nfcont;
r17909r17910
618618   UINT32 nfsecc;
619619   UINT32 nfsblk;
620620   UINT32 nfeblk;
621} s3c24xx_nand_regs_t;
621};
622622
623typedef struct
623struct s3c24xx_cam_regs_t
624624{
625625   UINT32 data[0xA4/4];
626} s3c24xx_cam_regs_t;
626};
627627
628typedef struct
628struct s3c24xx_uart_regs_t
629629{
630630   UINT32 ulcon;
631631   UINT32 ucon;
r17909r17910
638638   UINT32 utxh;
639639   UINT32 urxh;
640640   UINT32 ubrdiv;
641} s3c24xx_uart_regs_t;
641};
642642
643typedef struct
643struct s3c24xx_pwm_regs_t
644644{
645645   UINT32 tcfg0;
646646   UINT32 tcfg1;
r17909r17910
659659   UINT32 tcnto3;
660660   UINT32 tcntb4;
661661   UINT32 tcnto4;
662} s3c24xx_pwm_regs_t;
662};
663663
664typedef struct
664struct s3c24xx_usbdev_regs_t
665665{
666666   UINT32 data[0x130/4];
667} s3c24xx_usbdev_regs_t;
667};
668668
669typedef struct
669struct s3c24xx_wdt_regs_t
670670{
671671   UINT32 wtcon;
672672   UINT32 wtdat;
673673   UINT32 wtcnt;
674} s3c24xx_wdt_regs_t;
674};
675675
676typedef struct
676struct s3c24xx_iic_regs_t
677677{
678678   UINT32 iiccon;
679679   UINT32 iicstat;
680680   UINT32 iicadd;
681681   UINT32 iicds;
682682   UINT32 iiclc;
683} s3c24xx_iic_regs_t;
683};
684684
685typedef struct
685struct s3c24xx_iis_regs_t
686686{
687687   UINT32 iiscon;
688688   UINT32 iismod;
689689   UINT32 iispsr;
690690   UINT32 iisfcon;
691691   UINT32 iisfifo;
692} s3c24xx_iis_regs_t;
692};
693693
694typedef struct
694struct s3c24xx_gpio_regs_t
695695{
696696   UINT32 gpacon;
697697   UINT32 gpadat;
r17909r17910
748748   UINT32 gpjcon;
749749   UINT32 gpjdat;
750750   UINT32 gpjup;
751} s3c24xx_gpio_regs_t;
751};
752752
753typedef struct
753struct s3c24xx_rtc_regs_t
754754{
755755   UINT32 rtccon;
756756   UINT32 ticnt;
r17909r17910
770770   UINT32 bcddow;
771771   UINT32 bcdmon;
772772   UINT32 bcdyear;
773} s3c24xx_rtc_regs_t;
773};
774774
775typedef struct
775struct s3c24xx_adc_regs_t
776776{
777777   UINT32 adccon;
778778   UINT32 adctsc;
r17909r17910
780780   UINT32 adcdat0;
781781   UINT32 adcdat1;
782782   UINT32 adcupdn;
783} s3c24xx_adc_regs_t;
783};
784784
785typedef struct
785struct s3c24xx_spi_regs_t
786786{
787787   UINT32 spcon;
788788   UINT32 spsta;
r17909r17910
790790   UINT32 sppre;
791791   UINT32 sptdat;
792792   UINT32 sprdat;
793} s3c24xx_spi_regs_t;
793};
794794
795typedef struct
795struct s3c24xx_sdi_regs_t
796796{
797797   UINT32 data[0x44/4];
798} s3c24xx_sdi_regs_t;
798};
799799
800typedef struct
800struct s3c24xx_ac97_regs_t
801801{
802802   UINT32 data[0x20/4];
803} s3c24xx_ac97_regs_t;
803};
804804
805typedef struct
805struct s3c24xx_memcon_t
806806{
807807   s3c24xx_memcon_regs_t regs;
808} s3c24xx_memcon_t;
808};
809809
810typedef struct
810struct s3c24xx_usbhost_t
811811{
812812   s3c24xx_usbhost_regs_t regs;
813} s3c24xx_usbhost_t;
813};
814814
815typedef struct
815struct s3c24xx_irq_t
816816{
817817   s3c24xx_irq_regs_t regs;
818818   int line_irq, line_fiq;
819} s3c24xx_irq_t;
819};
820820
821typedef struct
821struct s3c24xx_dma_t
822822{
823823   s3c24xx_dma_regs_t regs;
824824   emu_timer *timer;
825} s3c24xx_dma_t;
825};
826826
827typedef struct
827struct s3c24xx_clkpow_t
828828{
829829   s3c24xx_clkpow_regs_t regs;
830} s3c24xx_clkpow_t;
830};
831831
832typedef struct
832struct s3c24xx_lcd_t
833833{
834834   s3c24xx_lcd_regs_t regs;
835835   emu_timer *timer;
r17909r17910
846846   UINT32 tpal;
847847   UINT32 hpos_min, hpos_max, vpos_min, vpos_max;
848848   UINT32 dma_data, dma_bits;
849} s3c24xx_lcd_t;
849};
850850
851typedef struct
851struct s3c24xx_lcdpal_t
852852{
853853   s3c24xx_lcdpal_regs_t regs;
854} s3c24xx_lcdpal_t;
854};
855855
856typedef struct
856struct s3c24xx_nand_t
857857{
858858   s3c24xx_nand_regs_t regs;
859859   UINT8 mecc[4];
860860   UINT8 secc[2];
861861   int ecc_pos, data_count;
862} s3c24xx_nand_t;
862};
863863
864typedef struct
864struct s3c24xx_cam_t
865865{
866866   s3c24xx_cam_regs_t regs;
867} s3c24xx_cam_t;
867};
868868
869typedef struct
869struct s3c24xx_uart_t
870870{
871871   s3c24xx_uart_regs_t regs;
872} s3c24xx_uart_t;
872};
873873
874typedef struct
874struct s3c24xx_pwm_t
875875{
876876   s3c24xx_pwm_regs_t regs;
877877   emu_timer *timer[5];
878878   UINT32 cnt[5];
879879   UINT32 cmp[5];
880880   UINT32 freq[5];
881} s3c24xx_pwm_t;
881};
882882
883typedef struct
883struct s3c24xx_usbdev_t
884884{
885885   s3c24xx_usbdev_regs_t regs;
886} s3c24xx_usbdev_t;
886};
887887
888typedef struct
888struct s3c24xx_wdt_t
889889{
890890   s3c24xx_wdt_regs_t regs;
891891   emu_timer *timer;
892} s3c24xx_wdt_t;
892};
893893
894typedef struct
894struct s3c24xx_iic_t
895895{
896896   s3c24xx_iic_regs_t regs;
897897   emu_timer *timer;
898898   int count;
899} s3c24xx_iic_t;
899};
900900
901typedef struct
901struct s3c24xx_iis_t
902902{
903903   s3c24xx_iis_regs_t regs;
904904   emu_timer *timer;
905905   UINT16 fifo[16/2];
906906   int fifo_index;
907} s3c24xx_iis_t;
907};
908908
909typedef struct
909struct s3c24xx_gpio_t
910910{
911911   s3c24xx_gpio_regs_t regs;
912} s3c24xx_gpio_t;
912};
913913
914typedef struct
914struct s3c24xx_rtc_t
915915{
916916   s3c24xx_rtc_regs_t regs;
917917   emu_timer *timer_tick_count;
918918   emu_timer *timer_update;
919} s3c24xx_rtc_t;
919};
920920
921typedef struct
921struct s3c24xx_adc_t
922922{
923923   s3c24xx_adc_regs_t regs;
924} s3c24xx_adc_t;
924};
925925
926typedef struct
926struct s3c24xx_spi_t
927927{
928928   s3c24xx_spi_regs_t regs;
929} s3c24xx_spi_t;
929};
930930
931typedef struct
931struct s3c24xx_sdi_t
932932{
933933   s3c24xx_sdi_regs_t regs;
934} s3c24xx_sdi_t;
934};
935935
936typedef struct
936struct s3c24xx_ac97_t
937937{
938938   s3c24xx_ac97_regs_t regs;
939} s3c24xx_ac97_t;
939};
940940
941typedef struct
941struct s3c24xx_t
942942{
943943   const s3c2440_interface *iface;
944944   UINT8 steppingstone[4*1024];
r17909r17910
963963   s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
964964   s3c24xx_sdi_t sdi;
965965   s3c24xx_ac97_t ac97;
966} s3c24xx_t;
966};
967967
968968#endif
trunk/src/emu/machine/v3021.h
r17909r17910
2727//  TYPE DEFINITIONS
2828//**************************************************************************
2929
30typedef struct
30struct rtc_regs_t
3131{
3232   UINT8 sec, min, hour, day, wday, month, year;
33} rtc_regs_t;
33};
3434
3535
3636// ======================> v3021_device
trunk/src/emu/machine/68681.c
r17909r17910
4444
4545#define RX_FIFO_SIZE            3
4646
47typedef struct
47struct DUART68681_CHANNEL
4848{
4949   /* Registers */
5050   UINT8 CR;  /* Command register */
r17909r17910
7070   UINT8 tx_ready;
7171   emu_timer *tx_timer;
7272
73} DUART68681_CHANNEL;
73};
7474
75typedef struct
75struct duart68681_state
7676{
7777   /* device */
7878   device_t *device;
r17909r17910
9999   /* UART channels */
100100   DUART68681_CHANNEL channel[2];
101101
102} duart68681_state;
102};
103103
104104INLINE duart68681_state *get_safe_token(device_t *device)
105105{
trunk/src/emu/machine/s3c2400.h
r17909r17910
407407    TYPE DEFINITIONS
408408*******************************************************************************/
409409
410typedef struct
410struct s3c24xx_memcon_regs_t
411411{
412412   UINT32 data[0x34/4];
413} s3c24xx_memcon_regs_t;
413};
414414
415typedef struct
415struct s3c24xx_usbhost_regs_t
416416{
417417   UINT32 data[0x5C/4];
418} s3c24xx_usbhost_regs_t;
418};
419419
420typedef struct
420struct s3c24xx_irq_regs_t
421421{
422422   UINT32 srcpnd;
423423   UINT32 intmod;
r17909r17910
425425   UINT32 priority;
426426   UINT32 intpnd;
427427   UINT32 intoffset;
428} s3c24xx_irq_regs_t;
428};
429429
430typedef struct
430struct s3c24xx_dma_regs_t
431431{
432432   UINT32 disrc;
433433   UINT32 didst;
r17909r17910
436436   UINT32 dcsrc;
437437   UINT32 dcdst;
438438   UINT32 dmasktrig;
439} s3c24xx_dma_regs_t;
439};
440440
441typedef struct
441struct s3c24xx_clkpow_regs_t
442442{
443443   UINT32 locktime;
444444   UINT32 mpllcon;
r17909r17910
446446   UINT32 clkcon;
447447   UINT32 clkslow;
448448   UINT32 clkdivn;
449} s3c24xx_clkpow_regs_t;
449};
450450
451typedef struct
451struct s3c24xx_lcd_regs_t
452452{
453453   UINT32 lcdcon1;
454454   UINT32 lcdcon2;
r17909r17910
464464   UINT32 reserved[8];
465465   UINT32 dithmode;
466466   UINT32 tpal;
467} s3c24xx_lcd_regs_t;
467};
468468
469typedef struct
469struct s3c24xx_lcdpal_regs_t
470470{
471471   UINT32 data[0x400/4];
472} s3c24xx_lcdpal_regs_t;
472};
473473
474typedef struct
474struct s3c24xx_uart_regs_t
475475{
476476   UINT32 ulcon;
477477   UINT32 ucon;
r17909r17910
484484   UINT32 utxh;
485485   UINT32 urxh;
486486   UINT32 ubrdiv;
487} s3c24xx_uart_regs_t;
487};
488488
489typedef struct
489struct s3c24xx_pwm_regs_t
490490{
491491   UINT32 tcfg0;
492492   UINT32 tcfg1;
r17909r17910
505505   UINT32 tcnto3;
506506   UINT32 tcntb4;
507507   UINT32 tcnto4;
508} s3c24xx_pwm_regs_t;
508};
509509
510typedef struct
510struct s3c24xx_usbdev_regs_t
511511{
512512   UINT32 data[0xBC/4];
513} s3c24xx_usbdev_regs_t;
513};
514514
515typedef struct
515struct s3c24xx_wdt_regs_t
516516{
517517   UINT32 wtcon;
518518   UINT32 wtdat;
519519   UINT32 wtcnt;
520} s3c24xx_wdt_regs_t;
520};
521521
522typedef struct
522struct s3c24xx_iic_regs_t
523523{
524524   UINT32 iiccon;
525525   UINT32 iicstat;
526526   UINT32 iicadd;
527527   UINT32 iicds;
528} s3c24xx_iic_regs_t;
528};
529529
530typedef struct
530struct s3c24xx_iis_regs_t
531531{
532532   UINT32 iiscon;
533533   UINT32 iismod;
534534   UINT32 iispsr;
535535   UINT32 iisfcon;
536536   UINT32 iisfifo;
537} s3c24xx_iis_regs_t;
537};
538538
539typedef struct
539struct s3c24xx_gpio_regs_t
540540{
541541   UINT32 gpacon;
542542   UINT32 gpadat;
r17909r17910
561561   UINT32 opencr;
562562   UINT32 misccr;
563563   UINT32 extint;
564} s3c24xx_gpio_regs_t;
564};
565565
566typedef struct
566struct s3c24xx_rtc_regs_t
567567{
568568   UINT32 rtccon;
569569   UINT32 ticnt;
r17909r17910
583583   UINT32 bcddow;
584584   UINT32 bcdmon;
585585   UINT32 bcdyear;
586} s3c24xx_rtc_regs_t;
586};
587587
588typedef struct
588struct s3c24xx_adc_regs_t
589589{
590590   UINT32 adccon;
591591   UINT32 adcdat;
592} s3c24xx_adc_regs_t;
592};
593593
594typedef struct
594struct s3c24xx_spi_regs_t
595595{
596596   UINT32 spcon;
597597   UINT32 spsta;
r17909r17910
599599   UINT32 sppre;
600600   UINT32 sptdat;
601601   UINT32 sprdat;
602} s3c24xx_spi_regs_t;
602};
603603
604typedef struct
604struct s3c24xx_mmc_regs_t
605605{
606606   UINT32 data[0x40/4];
607} s3c24xx_mmc_regs_t;
607};
608608
609typedef struct
609struct s3c24xx_memcon_t
610610{
611611   s3c24xx_memcon_regs_t regs;
612} s3c24xx_memcon_t;
612};
613613
614typedef struct
614struct s3c24xx_usbhost_t
615615{
616616   s3c24xx_usbhost_regs_t regs;
617} s3c24xx_usbhost_t;
617};
618618
619typedef struct
619struct s3c24xx_irq_t
620620{
621621   s3c24xx_irq_regs_t regs;
622622   int line_irq, line_fiq;
623} s3c24xx_irq_t;
623};
624624
625typedef struct
625struct s3c24xx_dma_t
626626{
627627   s3c24xx_dma_regs_t regs;
628628   emu_timer *timer;
629} s3c24xx_dma_t;
629};
630630
631typedef struct
631struct s3c24xx_clkpow_t
632632{
633633   s3c24xx_clkpow_regs_t regs;
634} s3c24xx_clkpow_t;
634};
635635
636typedef struct
636struct s3c24xx_lcd_t
637637{
638638   s3c24xx_lcd_regs_t regs;
639639   emu_timer *timer;
r17909r17910
650650   UINT32 tpal;
651651   UINT32 hpos_min, hpos_max, vpos_min, vpos_max;
652652   UINT32 dma_data, dma_bits;
653} s3c24xx_lcd_t;
653};
654654
655typedef struct
655struct s3c24xx_lcdpal_t
656656{
657657   s3c24xx_lcdpal_regs_t regs;
658} s3c24xx_lcdpal_t;
658};
659659
660typedef struct
660struct s3c24xx_uart_t
661661{
662662   s3c24xx_uart_regs_t regs;
663} s3c24xx_uart_t;
663};
664664
665typedef struct
665struct s3c24xx_pwm_t
666666{
667667   s3c24xx_pwm_regs_t regs;
668668   emu_timer *timer[5];
669669   UINT32 cnt[5];
670670   UINT32 cmp[5];
671671   UINT32 freq[5];
672} s3c24xx_pwm_t;
672};
673673
674typedef struct
674struct s3c24xx_usbdev_t
675675{
676676   s3c24xx_usbdev_regs_t regs;
677} s3c24xx_usbdev_t;
677};
678678
679typedef struct
679struct s3c24xx_wdt_t
680680{
681681   s3c24xx_wdt_regs_t regs;
682682   emu_timer *timer;
683} s3c24xx_wdt_t;
683};
684684
685typedef struct
685struct s3c24xx_iic_t
686686{
687687   s3c24xx_iic_regs_t regs;
688688   emu_timer *timer;
689689   int count;
690} s3c24xx_iic_t;
690};
691691
692typedef struct
692struct s3c24xx_iis_t
693693{
694694   s3c24xx_iis_regs_t regs;
695695   emu_timer *timer;
696696   UINT16 fifo[16/2];
697697   int fifo_index;
698} s3c24xx_iis_t;
698};
699699
700typedef struct
700struct s3c24xx_gpio_t
701701{
702702   s3c24xx_gpio_regs_t regs;
703} s3c24xx_gpio_t;
703};
704704
705typedef struct
705struct s3c24xx_rtc_t
706706{
707707   s3c24xx_rtc_regs_t regs;
708708   emu_timer *timer_tick_count;
709709   emu_timer *timer_update;
710} s3c24xx_rtc_t;
710};
711711
712typedef struct
712struct s3c24xx_adc_t
713713{
714714   s3c24xx_adc_regs_t regs;
715} s3c24xx_adc_t;
715};
716716
717typedef struct
717struct s3c24xx_spi_t
718718{
719719   s3c24xx_spi_regs_t regs;
720} s3c24xx_spi_t;
720};
721721
722typedef struct
722struct s3c24xx_mmc_t
723723{
724724   s3c24xx_mmc_regs_t regs;
725} s3c24xx_mmc_t;
725};
726726
727typedef struct
727struct s3c24xx_t
728728{
729729   const s3c2400_interface *iface;
730730   s3c24xx_memcon_t memcon;
r17909r17910
745745   s3c24xx_adc_t adc;
746746   s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
747747   s3c24xx_mmc_t mmc;
748} s3c24xx_t;
748};
749749
750750#endif
trunk/src/emu/machine/rtc9701.h
r17909r17910
3737
3838} rtc9701_state_t;
3939
40typedef struct
40struct rtc_regs_t
4141{
4242   UINT8 sec, min, hour, day, wday, month, year;
43} rtc_regs_t;
43};
4444
4545
4646// ======================> rtc9701_device
trunk/src/emu/machine/s3520cf.h
r17909r17910
2929   RTC_SET_DATA
3030} s3520cf_state_t;
3131
32typedef struct
32struct rtc_regs_t
3333{
3434   UINT8 sec, min, hour, day, wday, month, year;
35} rtc_regs_t;
35};
3636
3737
3838// ======================> s3520cf_device
trunk/src/emu/machine/s3c2410.h
r17909r17910
498498    TYPE DEFINITIONS
499499*******************************************************************************/
500500
501typedef struct
501struct s3c24xx_memcon_regs_t
502502{
503503   UINT32 data[0x34/4];
504} s3c24xx_memcon_regs_t;
504};
505505
506typedef struct
506struct s3c24xx_usbhost_regs_t
507507{
508508   UINT32 data[0x5C/4];
509} s3c24xx_usbhost_regs_t;
509};
510510
511typedef struct
511struct s3c24xx_irq_regs_t
512512{
513513   UINT32 srcpnd;
514514   UINT32 intmod;
r17909r17910
518518   UINT32 intoffset;
519519   UINT32 subsrcpnd;
520520   UINT32 intsubmsk;
521} s3c24xx_irq_regs_t;
521};
522522
523typedef struct
523struct s3c24xx_dma_regs_t
524524{
525525   UINT32 disrc;
526526   UINT32 disrcc;
r17909r17910
531531   UINT32 dcsrc;
532532   UINT32 dcdst;
533533   UINT32 dmasktrig;
534} s3c24xx_dma_regs_t;
534};
535535
536typedef struct
536struct s3c24xx_clkpow_regs_t
537537{
538538   UINT32 locktime;
539539   UINT32 mpllcon;
r17909r17910
541541   UINT32 clkcon;
542542   UINT32 clkslow;
543543   UINT32 clkdivn;
544} s3c24xx_clkpow_regs_t;
544};
545545
546typedef struct
546struct s3c24xx_lcd_regs_t
547547{
548548   UINT32 lcdcon1;
549549   UINT32 lcdcon2;
r17909r17910
563563   UINT32 lcdsrcpnd;
564564   UINT32 lcdintmsk;
565565   UINT32 lpcsel;
566} s3c24xx_lcd_regs_t;
566};
567567
568typedef struct
568struct s3c24xx_lcdpal_regs_t
569569{
570570   UINT32 data[0x400/4];
571} s3c24xx_lcdpal_regs_t;
571};
572572
573typedef struct
573struct s3c24xx_nand_regs_t
574574{
575575   UINT32 nfconf;
576576   UINT32 nfcmd;
r17909r17910
578578   UINT32 nfdata;
579579   UINT32 nfstat;
580580   UINT32 nfecc;
581} s3c24xx_nand_regs_t;
581};
582582
583typedef struct
583struct s3c24xx_uart_regs_t
584584{
585585   UINT32 ulcon;
586586   UINT32 ucon;
r17909r17910
593593   UINT32 utxh;
594594   UINT32 urxh;
595595   UINT32 ubrdiv;
596} s3c24xx_uart_regs_t;
596};
597597
598typedef struct
598struct s3c24xx_pwm_regs_t
599599{
600600   UINT32 tcfg0;
601601   UINT32 tcfg1;
r17909r17910
614614   UINT32 tcnto3;
615615   UINT32 tcntb4;
616616   UINT32 tcnto4;
617} s3c24xx_pwm_regs_t;
617};
618618
619typedef struct
619struct s3c24xx_usbdev_regs_t
620620{
621621   UINT32 data[0x130/4];
622} s3c24xx_usbdev_regs_t;
622};
623623
624typedef struct
624struct s3c24xx_wdt_regs_t
625625{
626626   UINT32 wtcon;
627627   UINT32 wtdat;
628628   UINT32 wtcnt;
629} s3c24xx_wdt_regs_t;
629};
630630
631typedef struct
631struct s3c24xx_iic_regs_t
632632{
633633   UINT32 iiccon;
634634   UINT32 iicstat;
635635   UINT32 iicadd;
636636   UINT32 iicds;
637} s3c24xx_iic_regs_t;
637};
638638
639typedef struct
639struct s3c24xx_iis_regs_t
640640{
641641   UINT32 iiscon;
642642   UINT32 iismod;
643643   UINT32 iispsr;
644644   UINT32 iisfcon;
645645   UINT32 iisfifo;
646} s3c24xx_iis_regs_t;
646};
647647
648typedef struct
648struct s3c24xx_gpio_regs_t
649649{
650650   UINT32 gpacon;
651651   UINT32 gpadat;
r17909r17910
695695   UINT32 gstatus2;
696696   UINT32 gstatus3;
697697   UINT32 gstatus4;
698} s3c24xx_gpio_regs_t;
698};
699699
700typedef struct
700struct s3c24xx_rtc_regs_t
701701{
702702   UINT32 rtccon;
703703   UINT32 ticnt;
r17909r17910
717717   UINT32 bcddow;
718718   UINT32 bcdmon;
719719   UINT32 bcdyear;
720} s3c24xx_rtc_regs_t;
720};
721721
722typedef struct
722struct s3c24xx_adc_regs_t
723723{
724724   UINT32 adccon;
725725   UINT32 adctsc;
726726   UINT32 adcdly;
727727   UINT32 adcdat0;
728728   UINT32 adcdat1;
729} s3c24xx_adc_regs_t;
729};
730730
731typedef struct
731struct s3c24xx_spi_regs_t
732732{
733733   UINT32 spcon;
734734   UINT32 spsta;
r17909r17910
736736   UINT32 sppre;
737737   UINT32 sptdat;
738738   UINT32 sprdat;
739} s3c24xx_spi_regs_t;
739};
740740
741typedef struct
741struct s3c24xx_sdi_regs_t
742742{
743743   UINT32 data[0x44/4];
744} s3c24xx_sdi_regs_t;
744};
745745
746typedef struct
746struct s3c24xx_memcon_t
747747{
748748   s3c24xx_memcon_regs_t regs;
749} s3c24xx_memcon_t;
749};
750750
751typedef struct
751struct s3c24xx_usbhost_t
752752{
753753   s3c24xx_usbhost_regs_t regs;
754} s3c24xx_usbhost_t;
754};
755755
756typedef struct
756struct s3c24xx_irq_t
757757{
758758   s3c24xx_irq_regs_t regs;
759759   int line_irq, line_fiq;
760} s3c24xx_irq_t;
760};
761761
762typedef struct
762struct s3c24xx_dma_t
763763{
764764   s3c24xx_dma_regs_t regs;
765765   emu_timer *timer;
766} s3c24xx_dma_t;
766};
767767
768typedef struct
768struct s3c24xx_clkpow_t
769769{
770770   s3c24xx_clkpow_regs_t regs;
771} s3c24xx_clkpow_t;
771};
772772
773typedef struct
773struct s3c24xx_lcd_t
774774{
775775   s3c24xx_lcd_regs_t regs;
776776   emu_timer *timer;
r17909r17910
787787   UINT32 tpal;
788788   UINT32 hpos_min, hpos_max, vpos_min, vpos_max;
789789   UINT32 dma_data, dma_bits;
790} s3c24xx_lcd_t;
790};
791791
792typedef struct
792struct s3c24xx_lcdpal_t
793793{
794794   s3c24xx_lcdpal_regs_t regs;
795} s3c24xx_lcdpal_t;
795};
796796
797typedef struct
797struct s3c24xx_nand_t
798798{
799799   s3c24xx_nand_regs_t regs;
800800   UINT8 mecc[3];
801801   int ecc_pos, data_count;
802} s3c24xx_nand_t;
802};
803803
804typedef struct
804struct s3c24xx_uart_t
805805{
806806   s3c24xx_uart_regs_t regs;
807} s3c24xx_uart_t;
807};
808808
809typedef struct
809struct s3c24xx_pwm_t
810810{
811811   s3c24xx_pwm_regs_t regs;
812812   emu_timer *timer[5];
813813   UINT32 cnt[5];
814814   UINT32 cmp[5];
815815   UINT32 freq[5];
816} s3c24xx_pwm_t;
816};
817817
818typedef struct
818struct s3c24xx_usbdev_t
819819{
820820   s3c24xx_usbdev_regs_t regs;
821} s3c24xx_usbdev_t;
821};
822822
823typedef struct
823struct s3c24xx_wdt_t
824824{
825825   s3c24xx_wdt_regs_t regs;
826826   emu_timer *timer;
827827   UINT32 freq, cnt;
828} s3c24xx_wdt_t;
828};
829829
830typedef struct
830struct s3c24xx_iic_t
831831{
832832   s3c24xx_iic_regs_t regs;
833833   emu_timer *timer;
834834   int count;
835} s3c24xx_iic_t;
835};
836836
837typedef struct
837struct s3c24xx_iis_t
838838{
839839   s3c24xx_iis_regs_t regs;
840840   emu_timer *timer;
841841   UINT16 fifo[16/2];
842842   int fifo_index;
843} s3c24xx_iis_t;
843};
844844
845typedef struct
845struct s3c24xx_gpio_t
846846{
847847   s3c24xx_gpio_regs_t regs;
848} s3c24xx_gpio_t;
848};
849849
850typedef struct
850struct s3c24xx_rtc_t
851851{
852852   s3c24xx_rtc_regs_t regs;
853853   emu_timer *timer_tick_count;
854854   emu_timer *timer_update;
855} s3c24xx_rtc_t;
855};
856856
857typedef struct
857struct s3c24xx_adc_t
858858{
859859   s3c24xx_adc_regs_t regs;
860} s3c24xx_adc_t;
860};
861861
862typedef struct
862struct s3c24xx_spi_t
863863{
864864   s3c24xx_spi_regs_t regs;
865} s3c24xx_spi_t;
865};
866866
867typedef struct
867struct s3c24xx_sdi_t
868868{
869869   s3c24xx_sdi_regs_t regs;
870} s3c24xx_sdi_t;
870};
871871
872typedef struct
872struct s3c24xx_t
873873{
874874   const s3c2410_interface *iface;
875875   UINT8 steppingstone[4*1024];
r17909r17910
892892   s3c24xx_adc_t adc;
893893   s3c24xx_spi_t spi[S3C24XX_SPI_COUNT];
894894   s3c24xx_sdi_t sdi;
895} s3c24xx_t;
895};
896896
897897#endif
trunk/src/emu/drawgfxm.h
r17909r17910
5656
5757
5858/* special priority type meaning "none" */
59typedef struct { char dummy[3]; } NO_PRIORITY;
59struct NO_PRIORITY { char dummy[3]; };
6060
6161extern bitmap_ind8 drawgfx_dummy_priority_bitmap;
6262#define DECLARE_NO_PRIORITY bitmap_t &priority = drawgfx_dummy_priority_bitmap;
trunk/src/mess/devices/sonydriv.c
r17909r17910
6060    Structure that describes the state of a floppy drive, and the associated
6161    disk image
6262*/
63typedef struct
63struct floppy_t
6464{
6565   device_t *img;
6666   emu_file *fd;
r17909r17910
7878
7979   int is_fdhd;            /* is drive an FDHD? */
8080    int is_400k;                /* drive is single-sided, which means 400K */
81} floppy_t;
81};
8282
83typedef struct
83struct sonydriv_t
8484{
8585   int lines;            /* four lines SONY_CA0 - SONY_LSTRB */
8686
r17909r17910
9191
9292   unsigned int rotation_speed;      /* drive rotation speed - ignored if ext_speed_control == 0 */
9393   floppy_t floppy[2];         /* data for two floppy disk units */
94} sonydriv_t;
94};
9595static sonydriv_t sony;
9696
9797/* bit of code used in several places - I am unsure why it is here */
trunk/src/mess/tools/imgtool/library.h
r17909r17910
5757   ITLS_DESCRIPTION
5858} imgtool_libsort_t;
5959
60typedef struct
60struct imgtool_dirent
6161{
6262   char filename[1024];
6363   char attr[64];
r17909r17910
7575   unsigned int corrupt : 1;
7676   unsigned int directory : 1;
7777   unsigned int hardlink : 1;
78} imgtool_dirent;
78};
7979
80typedef struct
80struct imgtool_chainent
8181{
8282   UINT8 level;
8383   UINT64 block;
84} imgtool_chainent;
84};
8585
8686typedef enum
8787{
r17909r17910
9191   FORK_ALTERNATE
9292} imgtool_forktype_t;
9393
94typedef struct
94struct imgtool_forkent
9595{
9696   imgtool_forktype_t type;
9797   UINT64 size;
9898   char forkname[64];
99} imgtool_forkent;
99};
100100
101typedef struct
101struct imgtool_transfer_suggestion
102102{
103103   imgtool_suggestion_viability_t viability;
104104   filter_getinfoproc filter;
105105   const char *fork;
106106   const char *description;
107} imgtool_transfer_suggestion;
107};
108108
109109enum
110110{
r17909r17910
140140   time_t   t;
141141} imgtool_attribute;
142142
143typedef struct
143struct imgtool_iconinfo
144144{
145145   unsigned icon16x16_specified : 1;
146146   unsigned icon32x32_specified : 1;
147147   UINT32 icon16x16[16][16];
148148   UINT32 icon32x32[32][32];
149} imgtool_iconinfo;
149};
150150
151151enum
152152{
trunk/src/mess/tools/imgtool/modules/thomson.c
r17909r17910
118118
119119#define MAXSIZE 80*16*256*2 /* room for two faces, double-density, 80 tracks */
120120
121typedef struct {
121struct thom_floppy {
122122
123123  imgtool_stream *stream;
124124
r17909r17910
130130
131131  int    modified;      /* data need to be copied back to image file */
132132
133} thom_floppy;
133};
134134
135135
136136typedef enum {
r17909r17910
143143} thom_dirent_type;
144144
145145
146typedef struct {
146struct thom_dirent {
147147
148148  thom_dirent_type type;
149149  int    index;
r17909r17910
159159  UINT8  month;
160160  UINT8  year;
161161
162} thom_dirent;
162};
163163
164164
165165static void thom_basic_get_info(const imgtool_class *clas, UINT32 param,
trunk/src/mess/audio/mea8000.c
r17909r17910
5555ALLOW_SAVE_TYPE( mea8000_state );
5656
5757
58typedef struct
58struct filter_t
5959{
6060#ifdef FLOAT_MODE
6161   double fm, last_fm;         /* frequency, in Hz */
r17909r17910
6666   UINT16 bw, last_bw;
6767   INT32  output, last_output;
6868#endif
69} filter_t;
69};
7070
7171
7272
73typedef struct
73struct mea8000_t
7474{
7575
7676   /* configuration parameters */
r17909r17910
102102
103103   emu_timer *timer;
104104
105} mea8000_t;
105};
106106
107107
108108
trunk/src/mess/audio/socrates.c
r17909r17910
1010#include "emu.h"
1111#include "socrates.h"
1212
13typedef struct
13struct SocratesASIC
1414{
1515   sound_stream *stream;
1616   UINT8 freq[2]; /* channel 1,2 frequencies */
r17909r17910
2020   UINT8 state[3]; /* output states for channels 1,2,3 */
2121   UINT8 accum[3]; /* accumulators for channels 1,2,3 */
2222   UINT16 DAC_output; /* output */
23} SocratesASIC;
23};
2424
2525
2626INLINE SocratesASIC *get_safe_token(device_t *device)
trunk/src/mess/audio/vboy.h
r17909r17910
3131//  TYPE DEFINITIONS
3232//**************************************************************************
3333
34typedef struct {
34struct s_snd_channel {
3535   INT8      playing;   // the sound is playing
3636
3737    // state when sound was enabled
r17909r17910
4848   int         time;            // the duration that this sample is to be played
4949   UINT8      envelope;         // Current envelope level (604)
5050   int         env_time;         // The duration between envelope decay/grow (608)
51} s_snd_channel;
51};
5252
53typedef struct {
53struct s_regchan {
5454   INT32 sINT;
5555   INT32 sLRV;
5656   INT32 sFQL;
r17909r17910
5858   INT32 sEV0;
5959   INT32 sEV1;
6060   INT32 sRAM;
61} s_regchan;
61};
6262
63typedef struct {
63struct s_sreg {
6464   // Sound registers structure
6565   s_regchan c[4];
66} s_sreg;
66};
6767
6868// ======================> vboysnd_device
6969
trunk/src/mess/audio/lynx.c
r17909r17910
8181
8282#define LYNX_AUDIO_CHANNELS 4
8383
84typedef struct {
84struct LYNX_AUDIO {
8585    struct {
8686      INT8 volume;
8787      UINT8 feedback;
r17909r17910
9797    UINT16 shifter; // 12-bit
9898    float ticks;
9999    int count;
100} LYNX_AUDIO;
100};
101101
102102struct lynx_sound_state
103103{
trunk/src/mess/audio/svision.c
r17909r17910
1313   SVISION_NOISE_Type14Bit
1414} SVISION_NOISE_Type;
1515
16typedef struct
16struct SVISION_NOISE
1717{
1818   UINT8 reg[3];
1919   int on, right, left, play;
r17909r17910
2323   int count;
2424   double step, pos;
2525   int value; // currently simple random function
26} SVISION_NOISE;
26};
2727
28typedef struct
28struct SVISION_DMA
2929{
3030   UINT8 reg[5];
3131   int on, right, left;
r17909r17910
3333   int start,size;
3434   double pos, step;
3535   int finished;
36} SVISION_DMA;
36};
3737
38typedef struct
38struct SVISION_CHANNEL
3939{
4040   UINT8 reg[4];
4141   int on;
r17909r17910
4343   int pos;
4444   int size;
4545   int count;
46} SVISION_CHANNEL;
46};
4747
4848struct svision_sound_state
4949{
trunk/src/mess/machine/strata.c
r17909r17910
4444   FM_CONFPART1,   // first half of configuration, awaiting second
4545   FM_WRPROTPART1   // first half of protection program, awaiting second
4646};
47typedef struct
47struct strata_t
4848{
4949   fm_mode_t mode;            // current operation mode
5050   int hard_unlock;   // 1 if RP* pin is at Vhh (not fully implemented)
r17909r17910
5757   UINT8 *data_ptr;   // main FEEPROM area
5858   UINT8 *blocklock;   // block lock flags
5959   UINT8 *prot_regs;   // protection registers
60} strata_t;
60};
6161
6262/* accessors for individual block lock flags */
6363#define READ_BLOCKLOCK(strata, block) (((strata)->blocklock[(block) >> 3] >> ((block) & 7)) & 1)
trunk/src/mess/machine/mc6854.c
r17909r17910
5757/******************* internal chip data structure ******************/
5858
5959
60typedef struct
60struct mc6854_t
6161{
6262   devcb_resolved_write_line   out_irq_func;
6363   devcb_resolved_read_line   in_rxd_func;
r17909r17910
9191   UINT8  frame[MAX_FRAME_LENGTH];
9292   UINT32 flen, fpos;
9393
94} mc6854_t;
94};
9595
9696/* meaning of tstate / rtate:
9797   0 = idle / waiting for frame flag
trunk/src/mess/machine/mc6846.c
r17909r17910
2828/******************* internal chip data structure ******************/
2929
3030
31typedef struct
31struct mc6846_t
3232{
3333
3434   const mc6846_interface* iface;
r17909r17910
6161
6262   int old_cif;
6363   int old_cto;
64} mc6846_t;
64};
6565
6666
6767
trunk/src/mess/machine/amigakbd.c
r17909r17910
1313
1414#define KEYBOARD_BUFFER_SIZE   256
1515
16typedef struct
16struct amigakbd_t
1717{
1818   UINT8 *buf;
1919   int buf_pos;
2020   int cur_pos;
2121   emu_timer *timer;
22} amigakbd_t;
22};
2323static amigakbd_t kbd;
2424
2525static void kbd_sendscancode( running_machine &machine, UINT8 scancode )
trunk/src/mess/machine/3c505.h
r17909r17910
126126 between the host and the adapter is done with these. (Except for the actual
127127 Ethernet data, which has different packaging.)
128128 */
129typedef struct
129struct pcb_struct
130130{
131131   UINT8 command;
132132   UINT8 length;
r17909r17910
147147      struct Memdump memdump;
148148      UINT8 raw[62];
149149   } data;
150} pcb_struct;
150};
151151
152152// ======================> threecom3c505_device
153153
trunk/src/mess/machine/s3c44b0.h
r17909r17910
373373    TYPE DEFINITIONS
374374*******************************************************************************/
375375
376typedef struct
376struct s3c44b0_memcon_regs_t
377377{
378378   UINT32 data[0x34/4];
379} s3c44b0_memcon_regs_t;
379};
380380
381typedef struct
381struct s3c44b0_irq_regs_t
382382{
383383   UINT32 intcon;
384384   UINT32 intpnd;
r17909r17910
393393   UINT32 reserved[4];
394394   UINT32 f_ispr;
395395   UINT32 f_ispc;
396} s3c44b0_irq_regs_t;
396};
397397
398typedef struct
398struct s3c44b0_dma_regs_t
399399{
400400   UINT32 dcon;
401401   UINT32 disrc;
r17909r17910
404404   UINT32 dcsrc;
405405   UINT32 dcdst;
406406   UINT32 dccnt;
407} s3c44b0_dma_regs_t;
407};
408408
409typedef struct
409struct s3c44b0_clkpow_regs_t
410410{
411411   UINT32 pllcon;
412412   UINT32 clkcon;
413413   UINT32 clkslow;
414414   UINT32 locktime;
415} s3c44b0_clkpow_regs_t;
415};
416416
417typedef struct
417struct s3c44b0_lcd_regs_t
418418{
419419   UINT32 lcdcon1;
420420   UINT32 lcdcon2;
r17909r17910
427427   UINT32 reserved[8];
428428   UINT32 lcdcon3;
429429   UINT32 dithmode;
430} s3c44b0_lcd_regs_t;
430};
431431
432typedef struct
432struct s3c44b0_uart_regs_t
433433{
434434   UINT32 ulcon;
435435   UINT32 ucon;
r17909r17910
442442   UINT32 utxh;
443443   UINT32 urxh;
444444   UINT32 ubrdiv;
445} s3c44b0_uart_regs_t;
445};
446446
447typedef struct
447struct s3c44b0_sio_regs_t
448448{
449449   UINT32 siocon;
450450   UINT32 siodat;
451451   UINT32 sbrdr;
452452   UINT32 itvcnt;
453453   UINT32 dcntz;
454} s3c44b0_sio_regs_t;
454};
455455
456typedef struct
456struct s3c44b0_pwm_regs_t
457457{
458458   UINT32 tcfg0;
459459   UINT32 tcfg1;
r17909r17910
475475   UINT32 tcnto4;
476476   UINT32 tcntb5;
477477   UINT32 tcnto5;
478} s3c44b0_pwm_regs_t;
478};
479479
480typedef struct
480struct s3c44b0_wdt_regs_t
481481{
482482   UINT32 wtcon;
483483   UINT32 wtdat;
484484   UINT32 wtcnt;
485} s3c44b0_wdt_regs_t;
485};
486486
487typedef struct
487struct s3c44b0_iic_regs_t
488488{
489489   UINT32 iiccon;
490490   UINT32 iicstat;
491491   UINT32 iicadd;
492492   UINT32 iicds;
493} s3c44b0_iic_regs_t;
493};
494494
495typedef struct
495struct s3c44b0_iis_regs_t
496496{
497497   UINT32 iiscon;
498498   UINT32 iismod;
499499   UINT32 iispsr;
500500   UINT32 iisfcon;
501501   UINT32 iisfifo;
502} s3c44b0_iis_regs_t;
502};
503503
504typedef struct
504struct s3c44b0_gpio_regs_t
505505{
506506   UINT32 gpacon;
507507   UINT32 gpadat;
r17909r17910
525525   UINT32 spucr;
526526   UINT32 extint;
527527   UINT32 extintpnd;
528} s3c44b0_gpio_regs_t;
528};
529529
530typedef struct
530struct s3c44b0_rtc_regs_t
531531{
532532   UINT32 rtccon;
533533   UINT32 reserved[3];
r17909r17910
547547   UINT32 bcdmon;
548548   UINT32 bcdyear;
549549   UINT32 ticnt;
550} s3c44b0_rtc_regs_t;
550};
551551
552typedef struct
552struct s3c44b0_adc_regs_t
553553{
554554   UINT32 adccon;
555555   UINT32 adcpsr;
556556   UINT32 adcdat;
557} s3c44b0_adc_regs_t;
557};
558558
559typedef struct
559struct s3c44b0_cpuwrap_regs_t
560560{
561561   UINT32 syscfg;
562562   UINT32 ncachbe0;
563563   UINT32 ncachbe1;
564} s3c44b0_cpuwrap_regs_t;
564};
565565
566typedef struct
566struct s3c44b0_memcon_t
567567{
568568   s3c44b0_memcon_regs_t regs;
569} s3c44b0_memcon_t;
569};
570570
571typedef struct
571struct s3c44b0_irq_t
572572{
573573   s3c44b0_irq_regs_t regs;
574574   int line_irq, line_fiq;
575} s3c44b0_irq_t;
575};
576576
577typedef struct
577struct s3c44b0_dma_t
578578{
579579   s3c44b0_dma_regs_t regs;
580580   emu_timer *timer;
581} s3c44b0_dma_t;
581};
582582
583typedef struct
583struct s3c44b0_clkpow_t
584584{
585585   s3c44b0_clkpow_regs_t regs;
586} s3c44b0_clkpow_t;
586};
587587
588typedef struct
588struct rectangle_t
589589{
590590   int x1, y1, x2, y2;
591} rectangle_t;
591};
592592
593typedef struct
593struct s3c44b0_lcd_t
594594{
595595   s3c44b0_lcd_regs_t regs;
596596   emu_timer *timer;
r17909r17910
607607   UINT32 hpos_min, hpos_max, hpos_end, vpos_min, vpos_max, vpos_end;
608608   attotime frame_time;
609609   attoseconds_t frame_period, pixeltime, scantime;
610} s3c44b0_lcd_t;
610};
611611
612typedef struct
612struct s3c44b0_uart_t
613613{
614614   s3c44b0_uart_regs_t regs;
615615   emu_timer *timer;
616} s3c44b0_uart_t;
616};
617617
618typedef struct
618struct s3c44b0_sio_t
619619{
620620   s3c44b0_sio_regs_t regs;
621621   emu_timer *timer;
622} s3c44b0_sio_t;
622};
623623
624typedef struct
624struct s3c44b0_pwm_t
625625{
626626   s3c44b0_pwm_regs_t regs;
627627   emu_timer *timer[6];
628628   UINT32 cnt[6];
629629   UINT32 cmp[6];
630630   UINT32 freq[6];
631} s3c44b0_pwm_t;
631};
632632
633typedef struct
633struct s3c44b0_wdt_t
634634{
635635   s3c44b0_wdt_regs_t regs;
636636   emu_timer *timer;
637} s3c44b0_wdt_t;
637};
638638
639typedef struct
639struct s3c44b0_iic_t
640640{
641641   s3c44b0_iic_regs_t regs;
642642   emu_timer *timer;
643643   int count;
644} s3c44b0_iic_t;
644};
645645
646typedef struct
646struct s3c44b0_iis_t
647647{
648648   s3c44b0_iis_regs_t regs;
649649   emu_timer *timer;
650650   UINT16 fifo[16/2];
651651   int fifo_index;
652} s3c44b0_iis_t;
652};
653653
654typedef struct
654struct s3c44b0_gpio_t
655655{
656656   s3c44b0_gpio_regs_t regs;
657} s3c44b0_gpio_t;
657};
658658
659typedef struct
659struct s3c44b0_rtc_t
660660{
661661   s3c44b0_rtc_regs_t regs;
662662   emu_timer *timer_tick_count;
663663   emu_timer *timer_update;
664} s3c44b0_rtc_t;
664};
665665
666typedef struct
666struct s3c44b0_adc_t
667667{
668668   s3c44b0_adc_regs_t regs;
669669   emu_timer *timer;
670} s3c44b0_adc_t;
670};
671671
672typedef struct
672struct s3c44b0_cpuwrap_t
673673{
674674   s3c44b0_cpuwrap_regs_t regs;
675} s3c44b0_cpuwrap_t;
675};
676676
677typedef struct
677struct s3c44b0_t
678678{
679679   const s3c44b0_interface *iface;
680680   address_space* space;
r17909r17910
695695   s3c44b0_rtc_t rtc;
696696   s3c44b0_adc_t adc;
697697   s3c44b0_cpuwrap_t cpuwrap;
698} s3c44b0_t;
698};
699699
700700#endif
trunk/src/mess/machine/mc68328.h
r17909r17910
1010#ifndef __MC68328_PRIVATE_H_
1111#define __MC68328_PRIVATE_H_
1212
13typedef struct
13struct mc68328_regs_t
1414{
1515    // $(FF)FFF000
1616    UINT8   scr;        // System Control Register
r17909r17910
201201    UINT16  rtcienr;    // RTC Interrupt Enable Register
202202    UINT16  stpwtch;    // Stopwatch Minutes
203203    UINT8   unused42[1260];
204} mc68328_regs_t;
204};
205205
206typedef struct
206struct mc68328_t
207207{
208208    const mc68328_interface* iface;
209209
r17909r17910
212212    emu_timer *gptimer[2];
213213    emu_timer *rtc;
214214    emu_timer *pwm;
215} mc68328_t;
215};
216216
217217#define SCR_BETO                0x80
218218#define SCR_WPV                 0x40
trunk/src/mess/machine/sgi.c
r17909r17910
2424   }
2525}
2626
27typedef struct
27struct MC_t
2828{
2929   emu_timer *tUpdateTimer;
3030   UINT32 nCPUControl0;
r17909r17910
6868   UINT32 nDMAMode;
6969   UINT32 nDMAZoomByteCnt;
7070   UINT32 nDMARunning;
71} MC_t;
71};
7272static MC_t *pMC;
7373
7474READ32_HANDLER( sgi_mc_r )
trunk/src/mess/machine/at45dbxx.c
r17909r17910
3636    TYPE DEFINITIONS
3737***************************************************************************/
3838
39typedef struct
39struct AT45DBXX_PINS
4040{
4141   int cs;    // chip select
4242   int sck;   // serial clock
r17909r17910
4545   int wp;    // write protect
4646   int reset; // reset
4747   int busy;  // busy
48} AT45DBXX_PINS;
48};
4949
50typedef struct
50struct AT45DBXX_CMD
5151{
5252   UINT8 data[8], size;
53} AT45DBXX_CMD;
53};
5454
55typedef struct
55struct AT45DBXX_IO
5656{
5757   UINT8 *data;
5858   UINT32 size, pos;
59} AT45DBXX_IO;
59};
6060
6161struct at45dbxx_t
6262{
trunk/src/mess/machine/amigacrt.c
r17909r17910
2424   ACTION_REPLAY_MKIII
2525};
2626
27typedef struct
27struct amigacrt_t
2828{
2929   int cart_type;
3030   int ar1_spurious;
3131   UINT16 ar23_mode;
32} amigacrt_t;
32};
3333static amigacrt_t amigacrt;
3434
3535/***************************************************************************
trunk/src/mess/machine/corvushd.c
r17909r17910
8989//
9090
9191// Sector addressing scheme for Rev B/H drives used in various commands (Called a DADR in the docs)
92typedef struct {
92struct dadr_t {
9393   UINT8 address_msn_and_drive;// Most significant nibble: Most signficant nibble of sector address, Least significant nibble: Drive #
9494   UINT8 address_lsb;         // Least significant byte of sector address
9595   UINT8 address_mid;         // Middle byte of sector address
96} dadr_t;
96};
9797
9898// Controller structure
99typedef struct {
99struct corvus_hdc_t {
100100   UINT8   status;            // Controller status byte (DIRECTION + BUSY/READY)
101101   char   prep_mode;         // Whether the controller is in Prep Mode or not
102102   // Physical drive info
r17909r17910
317317         UINT8   pattern[512]; // Pattern to be written
318318      } format_drive_revbh_command;
319319   } buffer;
320} corvus_hdc_t;
320};
321321
322322// Structure of Block #1, the Disk Parameter Block
323323typedef struct {
r17909r17910
340340} disk_parameter_block_t;
341341
342342// Structure of Block #3, the Constellation Parameter Block
343typedef struct {
343struct constellation_parameter_block_t {
344344   UINT8   mux_parameters[12];
345345   UINT8   pipe_name_table_ptr[2];
346346   UINT8   pipe_ptr_table_ptr[2];
r17909r17910
348348   UINT8   reserved[470];
349349   UINT8   software_protection[12];
350350   UINT8   serial_number[12];
351} constellation_parameter_block_t;
351};
352352
353353// Structure of Block #7, the Semaphore Table Block
354354typedef struct {
r17909r17910
362362} semaphore_table_block_t;
363363
364364// Command size structure (number of bytes to xmit and recv for each command)
365typedef struct {
365struct corvus_cmd_t {
366366   UINT16   recv_bytes;                     // Number of bytes from host for this command
367367   UINT16   xmit_bytes;                     // Number of bytes to return to host
368} corvus_cmd_t;
368};
369369
370370//
371371// Prototypes
trunk/src/mess/machine/amigacd.c
r17909r17910
5959#define ISTR_FF_FLG     (1<<1)  /* FIFO-Full Flag */
6060#define ISTR_FE_FLG     (1<<0)  /* FIFO-Empty Flag */
6161
62typedef struct
62struct _dmac_data
6363{
6464   UINT16      istr;      /* Interrupt Status Register (R) */
6565   UINT16      cntr;      /* Control Register (RW) */
r17909r17910
6767   UINT32      acr;      /* Address Count Register (RW) */
6868   UINT16      dawr;      /* DACK Width Register (W) */
6969   emu_timer *dma_timer;
70} _dmac_data;
70};
7171
7272static _dmac_data dmac_data;
7373
trunk/src/mess/machine/mboard.h
r17909r17910
4242    TYPE DEFINITIONS
4343***************************************************************************/
4444
45typedef struct {
45struct MOUSE_HOLD {
4646   int border_piece;
4747   UINT8 from;
4848   UINT8 piece;
49} MOUSE_HOLD;
49};
5050
5151/***************************************************************************
5252    FUNCTION PROTOTYPES
trunk/src/mess/machine/mc6843.c
r17909r17910
4242
4343/******************* internal chip data structure ******************/
4444
45typedef struct
45struct mc6843_t
4646{
4747
4848   /* interface */
r17909r17910
7272   /* trigger delayed actions (bottom halves) */
7373   emu_timer* timer_cont;
7474
75} mc6843_t;
75};
7676
7777
7878
trunk/src/mess/machine/apollo_net.c
r17909r17910
2121#include "includes/apollo.h"
2222#include "machine/3c505.h"
2323
24typedef struct {
24struct ethernet_header {
2525   UINT8 dest[6];
2626   UINT8 source[6];
2727   UINT16 proto;
28} ethernet_header;
28};
2929
30typedef struct
30struct ip_header
3131{
3232   UINT8 version;
3333   UINT8 tos;
r17909r17910
3939   UINT16 check;
4040   UINT32 saddr;
4141   UINT32 daddr;
42} ip_header;
42};
4343
4444#define ETHERNET_HEADER_SIZE sizeof(ethernet_header)
4545
trunk/src/mess/machine/rmnimbus.c
r17909r17910
19701970    { 0xE0000, 0xEFFFF }
19711971};
19721972
1973typedef struct
1973struct nimbus_block
19741974{
19751975    int     blockbase;
19761976    int     blocksize;
1977} nimbus_block;
1977};
19781978
19791979typedef nimbus_block nimbus_blocks[3];
19801980
trunk/src/mess/includes/fm7.h
r17909r17910
3030#define KEY_MODE_FM16B 1 // FM-16B (FM-77AV and later only)
3131#define KEY_MODE_SCAN  2 // Scancode Make/Break (PC-like)
3232
33typedef struct
33struct fm7_encoder_t
3434{
3535   UINT8 buffer[12];
3636   UINT8 tx_count;
r17909r17910
4040   UINT8 latch;  // 0=ready to receive
4141   UINT8 ack;
4242   UINT8 position;
43} fm7_encoder_t;
43};
4444
45typedef struct
45struct fm7_mmr_t
4646{
4747   UINT8 bank_addr[8][16];
4848   UINT8 segment;
4949   UINT8 window_offset;
5050   UINT8 enabled;
5151   UINT8 mode;
52} fm7_mmr_t;
52};
5353
54typedef struct
54struct fm7_video_t
5555{
5656   UINT8 sub_busy;
5757   UINT8 sub_halt;
r17909r17910
7575   UINT8 active_video_page;
7676   UINT8 display_video_page;
7777   UINT8 vsync_flag;
78} fm7_video_t;
78};
7979
80typedef struct
80struct fm7_alu_t
8181{
8282   UINT8 command;
8383   UINT8 lcolour;
r17909r17910
9595   UINT16 y0;
9696   UINT16 y1;
9797   UINT8 busy;
98} fm7_alu_t;
98};
9999
100100
101101class fm7_state : public driver_device
trunk/src/mess/includes/compis.h
r17909r17910
7373   UINT16   ext[4];
7474};
7575
76typedef struct
76struct i186_state
7777{
7878   struct timer_state   timer[3];
7979   struct dma_state   dma[2];
8080   struct intr_state   intr;
8181   struct mem_state   mem;
82} i186_state;
82};
8383
8484
8585/* Keyboard */
86typedef struct
86struct TYP_COMPIS_KEYBOARD
8787{
8888   UINT8 nationality;   /* Character set, keyboard layout (Swedish) */
8989   UINT8 release_time;  /* Autorepeat release time (0.8)   */
r17909r17910
9999   UINT8 boot_order[4]; /* Boot device order (FD HD NW PD) */
100100   UINT8 key_code;
101101   UINT8 key_status;
102} TYP_COMPIS_KEYBOARD;
102};
103103
104104/* USART 8251 */
105typedef struct
105struct TYP_COMPIS_USART
106106{
107107   UINT8 status;
108108   UINT8 bytes_sent;
109} TYP_COMPIS_USART;
109};
110110
111111/* Printer */
112typedef struct
112struct TYP_COMPIS_PRINTER
113113{
114114   UINT8 data;
115115   UINT8 strobe;
116} TYP_COMPIS_PRINTER;
116};
117117
118118
119119/* Main emulation */
120typedef struct
120struct TYP_COMPIS
121121{
122122   TYP_COMPIS_PRINTER   printer;   /* Printer */
123123   TYP_COMPIS_USART   usart;      /* USART 8251 */
124124   TYP_COMPIS_KEYBOARD   keyboard;   /* Keyboard  */
125} TYP_COMPIS;
125};
126126
127127
128128class compis_state : public driver_device
trunk/src/mess/includes/wswan.h
r17909r17910
4040#include "machine/nvram.h"
4141
4242
43typedef struct
43struct EEPROM
4444{
4545   UINT8   mode;      /* eeprom mode */
4646   UINT16   address;   /* Read/write address */
r17909r17910
5050   int   size;      /* size of eeprom/sram area */
5151   UINT8   *data;      /* pointer to start of sram/eeprom data */
5252   UINT8   *page;      /* pointer to current sram/eeprom page */
53} EEPROM;
53};
5454
55typedef struct
55struct RTC
5656{
5757   UINT8   present;   /* Is an RTC present */
5858   UINT8   setting;   /* Timer setting byte */
r17909r17910
6464   UINT8   minute;      /* Minute */
6565   UINT8   second;      /* Second */
6666   UINT8   index;      /* index for reading/writing of current of alarm time */
67} RTC;
67};
6868
69typedef struct
69struct SoundDMA
7070{
7171   UINT32   source;      /* Source address */
7272   UINT16   size;      /* Size */
7373   UINT8   enable;      /* Enabled */
74} SoundDMA;
74};
7575
76typedef struct
76struct VDP
7777{
7878   UINT8 layer_bg_enable;         /* Background layer on/off */
7979   UINT8 layer_fg_enable;         /* Foreground layer on/off */
r17909r17910
117117   UINT8 *palette_vram;         /* pointer to start of palette area in ram/vram (set by MACHINE_RESET), WSC only */
118118   int main_palette[8];
119119   emu_timer *timer;
120} VDP;
120};
121121
122122class wswan_state : public driver_device
123123{
trunk/src/mess/includes/dgn_beta.h
r17909r17910
7474
7575#define iosize   (0xfEFF-0xfc00)
7676
77typedef struct
77struct PageReg
7878{
7979   int       value;         /* Value of the page register */
8080   UINT8   *memory;      /* The memory it actually points to */
81} PageReg;
81};
8282
8383
8484class dgn_beta_state : public driver_device
trunk/src/mess/includes/z80ne.h
r17909r17910
3333   TAPE_1200BPS = 1200 /* 1200 bps */
3434} z80netape_speed;
3535
36typedef struct {
36struct cass_data_t {
3737   struct {
3838      int length;      /* time cassette level is at input.level */
3939      int level;      /* cassette level */
r17909r17910
4949   int wave_length;
5050   int wave_short;
5151   int wave_long;
52} cass_data_t;
52};
5353
54typedef struct {
54struct wd17xx_state_t {
5555   int drq;
5656   int intrq;
5757   UINT8 drive; /* current drive */
5858   UINT8 head;  /* current head */
59} wd17xx_state_t;
59};
6060
6161
6262class z80ne_state : public driver_device
trunk/src/mess/includes/hp48.h
r17909r17910
2020} hp48_models;
2121
2222/* memory module configuration */
23typedef struct
23struct hp48_module
2424{
2525   /* static part */
2626   UINT32 off_mask;             /* offset bit-mask, indicates the real size */
r17909r17910
3636   UINT32 base;                 /* base address */
3737   UINT32 mask;                 /* often improperly called size, it is an address select mask */
3838
39} hp48_module;
39};
4040
4141
4242/* screen image averaging */
trunk/src/mess/includes/c65.h
r17909r17910
1010#include "includes/c64_legacy.h"
1111#include "machine/6526cia.h"
1212
13typedef struct
13struct dma_t
1414{
1515   int version;
1616   UINT8 data[4];
17} dma_t;
17};
1818
19typedef struct
19struct fdc_t
2020{
2121   int state;
2222
r17909r17910
3030
3131   attotime time;
3232   int head,track,sector;
33} fdc_t;
33};
3434
35typedef struct
35struct expansion_ram_t
3636{
3737   UINT8 reg;
38} expansion_ram_t;
38};
3939
4040class c65_state : public legacy_c64_state
4141{
trunk/src/mess/includes/msx_slot.h
r17909r17910
1515   MSX_LAYOUT_LAST
1616};
1717
18typedef struct {
18struct msx_slot_layout {
1919   int entry;
2020   int type;
2121   int slot_primary, slot_secondary, slot_page, page_extent;
2222   int size, option;
23} msx_slot_layout;
23};
2424
2525#define MSX_LAYOUT_INIT(msx) \
2626static const msx_slot_layout msx_slot_layout_##msx[] = {
r17909r17910
112112   MSX_MEM_HANDLER
113113};
114114
115typedef struct {
115struct slot_state {
116116   int m_type;
117117   int m_start_page;
118118   int m_bank_mask;
r17909r17910
143143         int mode;
144144      } sccp;
145145   } m_cart;
146} slot_state;
146};
147147
148typedef struct {
148struct msx_slot {
149149   int slot_type;
150150   int mem_type;
151151   char name[32];
r17909r17910
155155   void (*write)(running_machine &machine, slot_state*, UINT16, UINT8);
156156   int (*loadsram)(running_machine &machine, slot_state*);
157157   int (*savesram)(running_machine &machine, slot_state*);
158} msx_slot;
158};
159159
160160extern const msx_slot msx_slot_list[];
161161
r17909r17910
239239#define MSX_SLOT_SAVESRAM(nm)      \
240240   static int slot_##nm##_savesram (running_machine &machine, slot_state *state)
241241
242typedef struct {
242struct msx_driver_struct {
243243   char name[9];
244244   const msx_slot_layout *layout;
245} msx_driver_struct;
245};
246246
247247extern const msx_driver_struct msx_driver_list[];
248248
trunk/src/mess/includes/pokemini.h
r17909r17910
1414#include "rendlay.h"
1515
1616
17typedef struct
17struct PRC
1818{
1919   UINT8      colors_inverted;
2020   UINT8      background_enabled;
r17909r17910
2828   UINT32      spr_tiles;
2929   UINT8      count;
3030   emu_timer   *count_timer;
31} PRC;
31};
3232
3333
34typedef struct
34struct TIMERS
3535{
3636   emu_timer   *seconds_timer;
3737   emu_timer   *hz256_timer;
r17909r17910
4141   emu_timer   *timer2_hi;            /* Timer 2 high */
4242   emu_timer   *timer3;            /* Timer 3 low or 16bit */
4343   emu_timer   *timer3_hi;            /* Timer 3 high */
44} TIMERS;
44};
4545
4646
4747class pokemini_state : public driver_device
trunk/src/mess/includes/nes.h
r17909r17910
3535#define CHRROM 0
3636#define CHRRAM 1
3737
38typedef struct
38struct chr_bank
3939{
4040   int source;   //defines source of base pointer
4141   int origin; //defines offset of 0x400 byte segment at base pointer
4242   UINT8* access;   //source translated + origin -> valid pointer!
43} chr_bank;
43};
4444
4545/*PPU nametable fast banking constants and structures */
4646
r17909r17910
5353#define NES_BATTERY 0
5454#define NES_WRAM 1
5555
56typedef struct
56struct name_table
5757{
5858   int source;      /* defines source of base pointer */
5959   int origin;      /* defines offset of 0x400 byte segment at base pointer */
6060   int writable;   /* ExRAM, at least, can be write-protected AND used as nametable */
6161   UINT8* access;   /* direct access when possible */
62} name_table;
62};
6363
6464typedef void (*nes_prg_callback)(running_machine &machine, int start, int bank);
6565typedef void (*nes_chr_callback)(running_machine &machine, int start, int bank, int source);
trunk/src/mess/includes/x1.h
r17909r17910
4444   virtual void z80daisy_irq_reti();
4545};
4646
47typedef struct
47struct scrn_reg_t
4848{
4949   UINT8 gfx_bank;
5050   UINT8 disp_bank;
r17909r17910
5454
5555   UINT8 pri;
5656   UINT8 blackclip; // x1 turbo specific
57} scrn_reg_t;
57};
5858
59typedef struct
59struct turbo_reg_t
6060{
6161   UINT8 pal;
6262   UINT8 gfx_pal;
6363   UINT8 txt_pal[8];
6464   UINT8 txt_disp;
65} turbo_reg_t;
65};
6666
67typedef struct
67struct x1_rtc_t
6868{
6969   UINT8 sec, min, hour, day, wday, month, year;
70} x1_rtc_t;
70};
7171
7272
7373class x1_state : public driver_device
trunk/src/mess/includes/gb.h
r17909r17910
5151   INT16  bgline;
5252};
5353
54typedef struct {
54struct gb_lcd_t {
5555   int   window_lines_drawn;
5656
5757   UINT8   gb_vid_regs[_NR_GB_VID_REGS];
r17909r17910
101101   UINT8   *gbc_chrgen;   /* CGB Character generator */
102102   UINT8   *gbc_bgdtab;   /* CGB Background character table */
103103   UINT8   *gbc_wndtab;   /* CGB Window character table */
104} gb_lcd_t;
104};
105105
106106
107107
trunk/src/mess/includes/concept.h
r17909r17910
2121   MaxKeyMessageLen = 1
2222};
2323
24typedef struct
24struct expansion_slot_t
2525{
2626   read8_space_func reg_read;
2727   write8_space_func reg_write;
2828   read8_space_func rom_read;
2929   write8_space_func rom_write;
30} expansion_slot_t;
30};
3131
3232
3333class concept_state : public driver_device
trunk/src/mess/includes/gamecom.h
r17909r17910
149149   SM8521_SG1W15   = 0x7F
150150};
151151
152typedef struct
152struct GAMECOM_DMA
153153{
154154   int enabled;
155155   int transfer_mode;
r17909r17910
180180   unsigned int dest_current;
181181   unsigned int dest_line;
182182   unsigned int dest_mask;
183} GAMECOM_DMA;
183};
184184
185typedef struct
185struct GAMECOM_TIMER
186186{
187187   int enabled;
188188   int state_count;
189189   int state_limit;
190190   int check_value;
191} GAMECOM_TIMER;
191};
192192
193typedef struct
193struct gamecom_sound_t
194194{
195195   UINT8 sgc;
196196   UINT8 sg0l;
r17909r17910
202202   UINT8 sgda;
203203   UINT8 sg0w[16];
204204   UINT8 sg1w[16];
205} gamecom_sound_t;
205};
206206
207207
208208class gamecom_state : public driver_device
trunk/src/mess/includes/cxhumax.h
r17909r17910
99
1010#define MAX_CX_TIMERS   16
1111
12typedef struct
12struct cx_timer_t
1313{
1414   UINT32 value;
1515   UINT32 limit;
1616   UINT32 mode;
1717   UINT32 timebase;
1818   emu_timer *timer;
19} cx_timer_t;
19};
2020
21typedef struct
21struct cx_timer_regs_t
2222{
2323   cx_timer_t timer[MAX_CX_TIMERS];
2424   UINT32 timer_irq;
25} cx_timer_regs_t;
25};
2626
2727class cxhumax_state : public driver_device
2828{
trunk/src/mess/includes/cgenie.h
r17909r17910
1010#include "machine/wd17xx.h"
1111
1212// CRTC 6845
13typedef struct
13struct CRTC6845
1414{
1515   UINT8    cursor_address_lo;
1616   UINT8    cursor_address_hi;
r17909r17910
3131   UINT8    idx;
3232   UINT8    cursor_visible;
3333   UINT8    cursor_phase;
34} CRTC6845;
34};
3535
3636
3737class cgenie_state : public driver_device
trunk/src/mess/includes/lynx.h
r17909r17910
1515
1616
1717class lynx_state;
18typedef struct
18struct BLITTER
1919{
2020   UINT8 *mem;
2121   // global
r17909r17910
5252   int vstretch;
5353   int lefthanded;
5454   int busy;
55} BLITTER;
55};
5656
57typedef struct
57struct UART
5858{
5959   UINT8 serctl;
6060   UINT8 data_received, data_to_send, buffer;
6161   int received;
6262   int sending;
6363   int buffer_loaded;
64} UART;
64};
6565
66typedef struct
66struct SUZY
6767{
6868   UINT8 data[0x100];
6969   UINT8 high;
r17909r17910
7171   int signed_math;
7272   int accumulate;
7373   int accumulate_overflow;
74} SUZY;
74};
7575
76typedef struct
76struct MIKEY
7777{
7878   UINT8 data[0x100];
7979   UINT16 disp_addr;
8080   UINT8 vb_rest;
81} MIKEY;
81};
8282
83typedef struct
83struct LYNX_TIMER
8484{
8585   UINT8   bakup;
8686   UINT8   cntrl1;
r17909r17910
8888   UINT8   counter;
8989   emu_timer   *timer;
9090   int      timer_active;
91} LYNX_TIMER;
91};
9292
9393#define NR_LYNX_TIMERS   8
9494
trunk/src/mess/includes/spectrum.h
r17909r17910
5151#define TS2068_RIGHT_BORDER  96   /* Number of right hand border pixels */
5252#define TS2068_SCREEN_WIDTH (TS2068_LEFT_BORDER + TS2068_DISPLAY_XSIZE + TS2068_RIGHT_BORDER)
5353
54typedef struct
54struct EVENT_LIST_ITEM
5555{
5656   /* driver defined ID for this write */
5757   int   Event_ID;
r17909r17910
5959   int   Event_Data;
6060   /* time at which this write occurred */
6161   int Event_Time;
62} EVENT_LIST_ITEM;
62};
6363
6464
6565class spectrum_state : public driver_device
trunk/src/mess/includes/pet.h
r17909r17910
1313#include "machine/ieee488.h"
1414#include "imagedev/cartslot.h"
1515
16typedef struct
16struct spet_t
1717{
1818   int bank; /* rambank to be switched in 0x9000 */
1919   int rom; /* rom socket 6502? at 0x9000 */
20} spet_t;
20};
2121
2222
2323class pet_state : public driver_device
trunk/src/mess/includes/oric.h
r17909r17910
3030   TELESTRAT_MEM_BLOCK_ROM
3131};
3232
33typedef struct
33struct telestrat_mem_block
3434{
3535   int      MemType;
3636   unsigned char *ptr;
37} telestrat_mem_block;
37};
3838
3939
4040/* current state of the display */
4141/* some attributes persist until they are turned off.
4242This structure holds this persistant information */
43typedef struct
43struct oric_vh_state
4444{
4545   /* foreground and background colour used for rendering */
4646   /* if flash attribute is set, these two will both be equal to background colour */
r17909r17910
6363   /* if (1<<3), display graphics, if 0, hide graphics */
6464   /* current count */
6565   UINT8 flash_count;
66} oric_vh_state;
66};
6767
6868
6969class oric_state : public driver_device
trunk/src/mess/includes/mbc55x.h
r17909r17910
7575#define FDC_TAG                 "wd1793"
7676
7777
78typedef struct
78struct keyboard_t
7979{
8080   UINT8       keyrows[MBC55X_KEYROWS];
8181   emu_timer   *keyscan_timer;
8282
8383   UINT8      key_special;
84}  keyboard_t;
84};
8585
8686
8787class mbc55x_state : public driver_device
r17909r17910
161161/* IO chips */
162162
163163
164typedef struct
164struct msm_rx_t
165165{
166} msm_rx_t;
166};
167167
168168/*----------- defined in drivers/mbc55x.c -----------*/
169169
trunk/src/mess/includes/gp32.h
r17909r17910
3434#define INT_EINT1      1
3535#define INT_EINT0      0
3636
37typedef struct
37struct s3c240x_lcd_t
3838{
3939   UINT32 vramaddr_cur;
4040   UINT32 vramaddr_max;
r17909r17910
4545   UINT32 bswp, hwswp;
4646   UINT32 hozval, lineval;
4747   int vpos, hpos;
48} s3c240x_lcd_t;
48};
4949
50typedef struct
50struct smc_t
5151{
5252   int add_latch;
5353   int chip;
r17909r17910
5959   int busy;
6060   UINT8 datarx;
6161   UINT8 datatx;
62} smc_t;
62};
6363
64typedef struct
64struct i2s_t
6565{
6666   int l3d;
6767   int l3m;
6868   int l3c;
69} i2s_t;
69};
7070
71typedef struct
71struct s3c240x_iic_t
7272{
7373   UINT8 data[4];
7474   int data_index;
7575   UINT16 address;
76} s3c240x_iic_t;
76};
7777
78typedef struct
78struct s3c240x_iis_t
7979{
8080   UINT16 fifo[16/2];
8181   int fifo_index;
82} s3c240x_iis_t;
82};
8383
8484
8585class gp32_state : public driver_device
trunk/src/mess/includes/electron.h
r17909r17910
2323
2424/* ULA context */
2525
26typedef struct
26struct ULA
2727{
2828   UINT8 interrupt_status;
2929   UINT8 interrupt_control;
r17909r17910
4848   int stop_bit;
4949   int tape_running;
5050   UINT8 tape_byte;
51} ULA;
51};
5252
5353
5454class electron_state : public driver_device
trunk/src/mess/includes/channelf.h
r17909r17910
1313
1414
1515/* SKR - 2102 RAM chip on carts 10 and 18 I/O ports */
16typedef struct
16struct r2102_t
1717{
1818   UINT8 d;         /* data bit:inverted logic, but reading/writing cancel out */
1919   UINT8 r_w;         /* inverted logic: 0 means read, 1 means write */
2020   UINT8 a[10];      /* addr bits: inverted logic, but reading/writing cancel out */
2121   UINT16 addr;      /* calculated addr from addr bits */
2222   UINT8 ram[1024];   /* RAM array */
23} r2102_t;
23};
2424
2525
2626class channelf_state : public driver_device
trunk/src/mess/includes/c64_legacy.h
r17909r17910
1919
2020#define C64_MAX_ROMBANK 64 // .crt files contain multiple 'CHIPs', i.e. rom banks (of variable size) with headers. Known carts have at most 64 'CHIPs'.
2121
22typedef struct {
22struct C64_ROM {
2323   int addr, size, index, start;
24} C64_ROM;
24};
2525
2626struct c64_cart_t {
2727   C64_ROM     bank[C64_MAX_ROMBANK];
trunk/src/mess/includes/apple1.h
r17909r17910
1212
1313typedef short termchar_t;
1414
15typedef struct
15struct terminal_t
1616{
1717   tilemap_t *tm;
1818   int gfx;
r17909r17910
2424   int cur_offset;
2525   int cur_hidden;
2626   termchar_t mem[1];
27} terminal_t;
27};
2828
2929
3030class apple1_state : public driver_device
trunk/src/mess/includes/sorcerer.h
r17909r17910
2323
2424#define SORCERER_USING_RS232 0
2525
26typedef struct {
26struct cass_data_t {
2727   struct {
2828      int length;      /* time cassette level is at input.level */
2929      int level;      /* cassette level */
r17909r17910
3434      int level;      /* cassette level */
3535      int bit;      /* bit to to output */
3636   } output;
37} cass_data_t;
37};
3838
3939
4040class sorcerer_state : public driver_device
trunk/src/mess/includes/bebox.h
r17909r17910
1313#include "machine/8237dma.h"
1414#include "machine/53c810.h"
1515
16typedef struct
16struct bebox_devices_t
1717{
1818   device_t *pic8259_master;
1919   device_t *pic8259_slave;
2020   device_t *dma8237_1;
2121   device_t *dma8237_2;
22} bebox_devices_t;
22};
2323
2424
2525class bebox_state : public driver_device
trunk/src/mess/includes/nascom1.h
r17909r17910
1010#include "imagedev/snapquik.h"
1111#include "machine/wd17xx.h"
1212
13typedef struct
13struct nascom1_portstat_t
1414{
1515   UINT8   stat_flags;
1616   UINT8   stat_count;
17} nascom1_portstat_t;
17};
1818
19typedef struct
19struct nascom2_fdc_t
2020{
2121   UINT8 select;
2222   UINT8 irq;
2323   UINT8 drq;
24} nascom2_fdc_t;
24};
2525
2626
2727class nascom1_state : public driver_device
trunk/src/mess/includes/gmaster.h
r17909r17910
11#ifndef __GMASTER_H__
22#define __GMASTER_H__
33
4typedef struct
4struct GMASTER_VIDEO
55{
66   UINT8 data[8];
77   int index;
r17909r17910
99   /*bool*/int mode; // true read does not increase address
1010   /*bool*/int delayed;
1111   UINT8 pixels[8][64/*>=62 sure*/];
12} GMASTER_VIDEO;
12};
1313
14typedef struct
14struct GMASTER_MACHINE
1515{
1616   UINT8 ports[5];
17} GMASTER_MACHINE;
17};
1818
1919
2020class gmaster_state : public driver_device
trunk/src/mess/includes/intv.h
r17909r17910
77#ifndef INTV_H_
88#define INTV_H_
99
10typedef struct
10struct intv_sprite_type
1111{
1212   int visible;
1313   int xpos;
r17909r17910
2525   int color;
2626   int doubleyres;
2727   int dirty;
28} intv_sprite_type;
28};
2929
3030class intv_state : public driver_device
3131{
trunk/src/mess/includes/ssystem3.h
r17909r17910
88#define SSYSTEM3_H_
99
1010
11typedef struct
11struct playfield_t
1212{
1313   int signal;
1414   //  int on;
r17909r17910
2424      } s;
2525      UINT8 data[7+8*8/2+5];
2626   } u;
27} playfield_t;
27};
2828
29typedef struct
29struct lcd_t
3030{
3131   UINT8 data[5];
3232   int clock;
3333   int count;
34} lcd_t;
34};
3535
3636
3737class ssystem3_state : public driver_device
trunk/src/mess/includes/amstrad.h
r17909r17910
2323/****************************
2424 * Gate Array data (CPC) -
2525 ****************************/
26typedef struct
26struct gate_array_t
2727{
2828   bitmap_ind16   *bitmap;      /* The bitmap we work on */
2929   UINT8   pen_selected;      /* Pen selection */
r17909r17910
5555   UINT16   line_ticks;
5656   UINT8   colour_ticks;
5757   UINT8   max_colour_ticks;
58} gate_array_t;
58};
5959
6060/****************************
6161 * ASIC data (CPC plus)
6262 ****************************/
63typedef struct
63struct asic_t
6464{
6565   UINT8   *ram;            /* pointer to RAM used for the CPC+ ASIC memory-mapped registers */
6666   UINT8   enabled;         /* Are CPC plus features enabled/unlocked */
r17909r17910
8585   UINT16   dma_addr[3];      /* DMA channel address */
8686   UINT16   dma_loopcount[3];   /* Count loops taken on this channel */
8787   UINT16   dma_pause[3];      /* DMA pause count */
88} asic_t;
88};
8989
9090
9191class amstrad_state : public driver_device
trunk/src/mess/includes/rmnimbus.h
r17909r17910
2626
2727/* Nimbus sub-bios structures for debugging */
2828
29typedef struct
29struct t_area_params
3030{
3131   UINT16  ofs_brush;
3232   UINT16  seg_brush;
3333   UINT16  ofs_data;
3434   UINT16  seg_data;
3535   UINT16  count;
36} t_area_params;
36};
3737
38typedef struct
38struct t_plot_string_params
3939{
4040   UINT16  ofs_font;
4141   UINT16  seg_font;
r17909r17910
4444   UINT16  x;
4545   UINT16  y;
4646   UINT16  length;
47} t_plot_string_params;
47};
4848
49typedef struct
49struct t_nimbus_brush
5050{
5151   UINT16  style;
5252   UINT16  style_index;
r17909r17910
5656   UINT16  boundary_spec;
5757   UINT16  boundary_colour;
5858   UINT16  save_colour;
59} t_nimbus_brush;
59};
6060
6161#define SCREEN_WIDTH_PIXELS     640
6262#define SCREEN_HEIGHT_LINES     250
r17909r17910
110110   UINT16  ext_vector[2]; // external vectors, when in cascade mode
111111};
112112
113typedef struct
113struct i186_state
114114{
115115   struct timer_state   timer[3];
116116   struct dma_state   dma[2];
117117   struct intr_state   intr;
118118   struct mem_state   mem;
119} i186_state;
119};
120120
121typedef struct
121struct keyboard_t
122122{
123123   UINT8       keyrows[NIMBUS_KEYROWS];
124124   emu_timer   *keyscan_timer;
125125   UINT8       queue[KEYBOARD_QUEUE_SIZE];
126126   UINT8       head;
127127   UINT8       tail;
128}  keyboard_t;
128};
129129
130130// Static data related to Floppy and SCSI hard disks
131typedef struct
131struct nimbus_drives_t
132132{
133133   UINT8   reg400;
134134   UINT8   reg410_in;
r17909r17910
137137
138138   UINT8   drq_ff;
139139   UINT8   int_ff;
140} nimbus_drives_t;
140};
141141
142142/* 8031 Peripheral controler */
143typedef struct
143struct ipc_interface_t
144144{
145145   UINT8   ipc_in;
146146   UINT8   ipc_out;
r17909r17910
149149   UINT8   int_8c_pending;
150150   UINT8   int_8e_pending;
151151   UINT8   int_8f_pending;
152} ipc_interface_t;
152};
153153
154154/* Mouse/Joystick */
155typedef struct
155struct _mouse_joy_state
156156{
157157   UINT8   m_mouse_px;
158158   UINT8   m_mouse_py;
r17909r17910
169169   UINT8   m_reg0a4;
170170
171171   emu_timer   *m_mouse_timer;
172} _mouse_joy_state;
172};
173173
174174
175175class rmnimbus_state : public driver_device
trunk/src/mess/includes/cybiko.h
r17909r17910
2828#include "machine/sst39vfx.h"
2929#include "machine/ram.h"
3030
31typedef struct
31struct CYBIKO_RS232_PINS
3232{
3333   int sck; // serial clock
3434   int txd; // transmit data
3535   int rxd; // receive data
36} CYBIKO_RS232_PINS;
36};
3737
38typedef struct
38struct CYBIKO_RS232
3939{
4040   CYBIKO_RS232_PINS pin;
4141   UINT8 rx_bits, rx_byte, tx_byte, tx_bits;
42} CYBIKO_RS232;
42};
4343
4444class cybiko_state : public driver_device
4545{
trunk/src/mess/includes/odyssey2.h
r17909r17910
5454    } s;
5555} o2_vdc_t;
5656
57typedef struct
57struct ef9341_t
5858{
5959   UINT8   X;
6060   UINT8   Y;
r17909r17910
6565   UINT8   TB;
6666   UINT8   busy;
6767   UINT8   ram[1024];
68} ef9341_t;
68};
6969
7070
7171class odyssey2_state : public driver_device
trunk/src/mess/includes/svision.h
r17909r17910
77#ifndef SVISION_H_
88#define SVISION_H_
99
10typedef struct
10struct svision_t
1111{
1212   emu_timer *timer1;
1313   int timer_shot;
14} svision_t;
14};
1515
16typedef struct
16struct svision_pet_t
1717{
1818   int state;
1919   int on, clock, data;
2020   UINT8 input;
2121   emu_timer *timer;
22} svision_pet_t;
22};
2323
24typedef struct
24struct tvlink_t
2525{
2626   UINT32 palette[4/*0x40?*/]; /* rgb8 */
2727   int palette_on;
28} tvlink_t;
28};
2929
3030
3131class svision_state : public driver_device
trunk/src/mess/includes/svi318.h
r17909r17910
1313#include "machine/ins8250.h"
1414#include "machine/wd17xx.h"
1515
16typedef struct
16struct SVI_318
1717{
1818   /* general */
1919   UINT8   svi318;      /* Are we dealing with an SVI-318 or a SVI-328 model. 0 = 328, 1 = 318 */
r17909r17910
3535   UINT8   svi806_ram_enabled;
3636   memory_region   *svi806_ram;
3737   UINT8   *svi806_gfx;
38} SVI_318;
38};
3939
40typedef struct
40struct SVI318_FDC_STRUCT
4141{
4242   UINT8 driveselect;
4343   int drq;
4444   int irq;
4545   UINT8 heads[2];
46} SVI318_FDC_STRUCT;
46};
4747
4848
4949class svi318_state : public driver_device
trunk/src/mess/includes/pce.h
r17909r17910
3131/* the largest possible cartridge image (street fighter 2 - 2.5MB) */
3232#define PCE_ROM_MAXSIZE      0x280000
3333
34typedef struct
34struct pce_cd_t
3535{
3636   UINT8   regs[16];
3737   UINT8   *bram;
r17909r17910
101101   emu_timer   *adpcm_fadeout_timer;
102102   emu_timer   *adpcm_fadein_timer;
103103   double   adpcm_volume;
104} pce_cd_t;
104};
105105
106106
107107class pce_state : public driver_device
trunk/src/mess/includes/vc4000.h
r17909r17910
1919#define ANALOG_HACK
2020
2121
22typedef struct
22struct SPRITE_HELPER
2323{
2424   UINT8 bitmap[10],x1,x2,y1,y2, res1, res2;
25} SPRITE_HELPER;
25};
2626
27typedef struct
27struct SPRITE
2828{
2929   const SPRITE_HELPER *data;
3030   int mask;
r17909r17910
3535   UINT8 scolor;
3636   int finished;
3737   int finished_now;
38} SPRITE;
38};
3939
40typedef struct
40struct vc4000_video_t
4141{
4242   SPRITE sprites[4];
4343   int line;
r17909r17910
6666         UINT8 sprite_collision;
6767      } d;
6868   } reg;
69} vc4000_video_t;
69} ;
7070
7171class vc4000_state : public driver_device
7272{
trunk/src/mess/includes/x07.h
r17909r17910
8686   0x01, 0x09, 0x01, 0x03, 0x03, 0x01, 0x01
8787};
8888
89typedef struct
89struct x07_kb
9090{
9191   const char *tag;      //input port tag
9292   UINT8      mask;      //bit mask
9393   UINT8      codes[7];   //port codes
94} x07_kb;
94};
9595
9696static const x07_kb x07_keycodes[56] =
9797{
trunk/src/mess/includes/gamepock.h
r17909r17910
11#ifndef _GAMEPOCK_H_
22#define _GAMEPOCK_H_
33
4typedef struct {
4struct HD44102CH {
55   UINT8   enabled;
66   UINT8   start_page;
77   UINT8   address;
88   UINT8   y_inc;
99   UINT8   ram[256];   /* There are actually 50 x 4 x 8 bits. This just makes addressing easier. */
10} HD44102CH;
10};
1111
1212class gamepock_state : public driver_device
1313{
trunk/src/mess/video/newport.c
r17909r17910
5252static READ32_HANDLER( newport_vc2_r );
5353static WRITE32_HANDLER( newport_vc2_w );
5454
55typedef struct
55struct VC2_t
5656{
5757   UINT16 nRegister[0x21];
5858   UINT16 nRAM[0x8000];
5959   UINT8 nRegIdx;
6060   UINT16 nRegData;
61} VC2_t;
61};
6262
6363#define VC2_VIDENTRY      pNVID->VC2.nRegister[0x00]
6464#define VC2_CURENTRY      pNVID->VC2.nRegister[0x01]
r17909r17910
7979#define VC2_DISPLAYCTRL      pNVID->VC2.nRegister[0x10]
8080#define VC2_CONFIG         pNVID->VC2.nRegister[0x1f]
8181
82typedef struct
82struct XMAP_t
8383{
8484   UINT32 nRegister[0x08];
8585   UINT32 nModeTable[0x20];
86} XMAP_t;
86};
8787
8888#define XMAP0_CONFIG      pNVID->XMAP0.nRegister[0x00]
8989#define XMAP0_REVISION      pNVID->XMAP0.nRegister[0x01]
r17909r17910
100100#define XMAP1_MODETBLIDX   pNVID->XMAP1.nRegister[0x07]
101101
102102
103typedef struct
103struct REX3_t
104104{
105105   UINT32 nDrawMode1;
106106   UINT32 nDrawMode0;
r17909r17910
177177   UINT32 nCurrentY;
178178#endif
179179   UINT32 nKludge_SkipLine;
180} REX3_t;
180};
181181
182182
183typedef struct
183struct CMAP_t
184184{
185185   UINT16 nPaletteIndex;
186186   UINT32 nPalette[0x10000];
187} CMAP_t;
187};
188188
189189struct newport_video_t
190190{
trunk/src/mess/video/crt.c
r17909r17910
3232#include "video/crt.h"
3333
3434
35typedef struct
35struct point
3636{
3737   int intensity;      /* current intensity of the pixel */
3838                     /* a node is not in the list when (intensity == -1) */
3939   int next;         /* index of next pixel in list */
40} point;
40};
4141
4242enum
4343{
4444   intensity_pixel_not_in_list = -1   /* special value that tells that the node is not in list */
4545};
4646
47typedef struct
47struct crt_t
4848{
4949   point *list;      /* array of (crt_window_width*crt_window_height) point */
5050   int *list_head;   /* head of the list of lit pixels (index in the array) */
r17909r17910
5656   int num_intensity_levels;
5757   int window_offset_x, window_offset_y;
5858   int window_width, window_height;
59} crt_t;
59};
6060
6161
6262INLINE crt_t *get_safe_token(device_t *device)
trunk/src/mess/video/733_asr.c
r17909r17910
3434   asr_scroll_step = 8
3535};
3636
37typedef struct
37struct asr_t
3838{
3939#if 0
4040   UINT8 OutQueue[ASROutQueueSize];
r17909r17910
5858   void (*int_callback)(running_machine &, int state);
5959
6060   bitmap_ind16 *bitmap;
61} asr_t;
61};
6262
6363enum
6464{
trunk/src/mess/formats/timex_dck.h
r17909r17910
1818   TIMEX_CART_HOME
1919};
2020
21typedef struct
21struct timex_cart_t
2222{
2323   int type;
2424   UINT8 chunks;
2525   UINT8 *data;
26} timex_cart_t;
26};
2727
2828const timex_cart_t *timex_cart_data(void);
2929
trunk/src/mess/drivers/pc88va.c
r17909r17910
2929#include "sound/2203intf.h"
3030#include "formats/basicdsk.h"
3131
32typedef struct
32struct tsp_t
3333{
3434   UINT16 tvram_vreg_offset;
3535   UINT16 attr_offset;
r17909r17910
4343   UINT16 cur_pos_x,cur_pos_y;
4444   UINT8 curn;
4545   UINT8 curn_blink;
46} tsp_t;
46};
4747
4848
4949class pc88va_state : public driver_device
trunk/src/mess/drivers/sgi_ip6.c
r17909r17910
1717#include "cpu/mips/r3000.h"
1818
1919
20typedef struct
20struct ip6_regs_t
2121{
2222   UINT16 unknown_half_0;
2323   UINT8 unknown_byte_0;
2424   UINT8 unknown_byte_1;
25} ip6_regs_t;
25};
2626
2727class sgi_ip6_state : public driver_device
2828{
trunk/src/mess/drivers/ip22.c
r17909r17910
5757#include "machine/scsihd.h"
5858#include "machine/wd33c93.h"
5959
60typedef struct
60struct RTC_t
6161{
6262   UINT8 nRegs[0x80];
6363   UINT8 nUserRAM[0x200];
6464   UINT8 nRAM[0x800];
65} RTC_t;
65};
6666
67typedef struct
67struct HPC3_t
6868{
6969   UINT32 nenetr_nbdp;
7070   UINT32 nenetr_cbp;
r17909r17910
7373   UINT32 nIC_Unk0;
7474   UINT32 nSCSI0Descriptor;
7575   UINT32 nSCSI0DMACtrl;
76} HPC3_t;
76};
7777
78typedef struct
78struct HAL2_t
7979{
8080   UINT32 nIAR;
8181   UINT32 nIDR[4];
82} HAL2_t;
82};
8383
84typedef struct
84struct PBUS_DMA_t
8585{
8686   UINT8 nActive;
8787   UINT32 nCurPtr;
8888   UINT32 nDescPtr;
8989   UINT32 nNextPtr;
9090   UINT32 nWordsLeft;
91} PBUS_DMA_t;
91};
9292
9393class ip22_state : public driver_device
9494{
trunk/src/mess/drivers/a2600.c
r17909r17910
1515#include "video/tia.h"
1616#include "hashfile.h"
1717
18typedef struct {
18struct df_t {
1919   UINT8   top;
2020   UINT8   bottom;
2121   UINT8   low;
r17909r17910
2323   UINT8   flag;
2424   UINT8   music_mode;      /* Only used by data fetchers 5,6, and 7 */
2525   UINT8   osc_clk;      /* Only used by data fetchers 5,6, and 7 */
26} df_t;
26};
2727
28typedef struct
28struct dpc_t
2929{
3030   df_t df[8];
3131   UINT8   movamt;
r17909r17910
3434   UINT8   dlc;
3535   UINT8   shift_reg;
3636   emu_timer   *oscillator;
37} dpc_t;
37};
3838
3939
4040class a2600_state : public driver_device
trunk/src/mess/drivers/ng_aes.c
r17909r17910
4444};
4545
4646// CD-ROM / DMA control registers
47typedef struct
47struct neocd_ctrl_t
4848{
4949   UINT8 area_sel;
5050   UINT8 pcm_bank_sel;
r17909r17910
5454   UINT16 fill_word;
5555   UINT32 word_count;
5656   UINT16 dma_mode[10];
57} neocd_ctrl_t;
57};
5858
5959class ng_aes_state : public neogeo_state
6060{
trunk/src/mess/drivers/psx.c
r17909r17910
1919#include "machine/psxcd.h"
2020#include "machine/psxcard.h"
2121
22typedef struct
22struct pad_t
2323{
2424   UINT8 n_shiftin;
2525   UINT8 n_shiftout;
r17909r17910
2828   int n_byte;
2929   int b_lastclock;
3030   int b_ack;
31} pad_t;
31};
3232
3333
3434class psx1_state : public psx_state
trunk/src/mess/drivers/pockstat.c
r17909r17910
3636
3737#define MAX_PS_TIMERS   3
3838
39typedef struct
39struct ps_ftlb_regs_t
4040{
4141   UINT32 control;
4242   UINT32 stat;
r17909r17910
4545   UINT32 wait2;
4646   UINT32 entry[16];
4747   UINT32 serial;
48} ps_ftlb_regs_t;
48};
4949
50typedef struct
50struct ps_intc_regs_t
5151{
5252   UINT32 hold;
5353   UINT32 status;
5454   UINT32 enable;
5555   UINT32 mask;
56} ps_intc_regs_t;
56};
5757
58typedef struct
58struct ps_timer_t
5959{
6060   UINT32 period;
6161   UINT32 count;
6262   UINT32 control;
6363   emu_timer *timer;
64} ps_timer_t;
64};
6565
66typedef struct
66struct ps_timer_regs_t
6767{
6868   ps_timer_t timer[MAX_PS_TIMERS];
69} ps_timer_regs_t;
69};
7070
71typedef struct
71struct ps_clock_regs_t
7272{
7373   UINT32 mode;
7474   UINT32 control;
75} ps_clock_regs_t;
75};
7676
7777#define PS_CLOCK_STEADY      0x10
7878
79typedef struct
79struct ps_rtc_regs_t
8080{
8181   UINT32 mode;
8282   UINT32 control;
8383   UINT32 time;
8484   UINT32 date;
8585   emu_timer *timer;
86} ps_rtc_regs_t;
86};
8787
8888
8989
trunk/src/mess/drivers/hp49gp.c
r17909r17910
2424   }
2525}
2626
27typedef struct
27struct lcd_spi_t
2828{
2929   int l1;
3030   int data;
3131   int l3;
3232   UINT32 shift, bits;
33} lcd_spi_t;
33};
3434
3535class hp49gp_state : public driver_device
3636{
trunk/src/mess/drivers/rvoice.c
r17909r17910
1818
1919/* Components */
2020
21typedef struct
21struct hd63701y0_t
2222{
2323   UINT8 data[8];
2424   UINT8 P1DDR;
r17909r17910
5555   UINT8 TSTREG;
5656   UINT8 P5DDR;
5757   UINT8 P6CSR;
58} hd63701y0_t;
58};
5959
60typedef struct
60struct rvoicepc_t
6161{
6262   UINT8 data[8];
6363   UINT8 port1;
r17909r17910
6767   UINT8 port5;
6868   UINT8 port6;
6969   UINT8 port7;
70} rvoicepc_t;
70};
7171
7272class rvoice_state : public driver_device
7373{
trunk/src/mess/drivers/cgenie.c
r17909r17910
626626//   GATL GAT Length
627627//   GATM GAT Mask
628628//   DDGA Disk Directory Granule Allocation
629typedef struct
629struct PDRIVE
630630{
631631    UINT8 DDSL;      // Disk Directory Start Lump (lump number of GAT)
632632    UINT8 GATL;      // # of bytes used in the Granule Allocation Table sector
r17909r17910
638638    UINT8 FLAGS;     // ???? some flags (SS/DS bit 6)
639639    UINT8 GPL;       // Sectors per granule (always 5 for the Colour Genie)
640640    UINT8 DDGA;      // Disk Directory Granule allocation (number of driectory granules)
641}   PDRIVE;
641};
642642
643643static const PDRIVE pd_list[12] = {
644644    {0x14, 0x28, 0x07, 0x28, 0x0A, 0x02, 0x00, 0x00, 0x05, 0x02}, // CMD"<0=A" 40 tracks, SS, SD
trunk/src/mess/drivers/pc8801.c
r17909r17910
271271#define UPD1990A_TAG   "upd1990a"
272272#define I8251_TAG      "i8251"
273273
274typedef struct
274struct crtc_t
275275{
276276   UINT8 cmd,param_count,cursor_on,status,irq_mask;
277277   UINT8 param[8][5];
278278   UINT8 inverse;
279} crtc_t;
279};
280280
281typedef struct
281struct mouse_t
282282{
283283   UINT8 phase;
284284   UINT8 x,y;
285285   attotime time;
286} mouse_t;
286};
287287
288288class pc8801_state : public driver_device
289289{
trunk/src/mess/drivers/juicebox.c
r17909r17910
3131   }
3232}
3333
34typedef struct
34struct smc_t
3535{
3636   int add_latch;
3737   int cmd_latch;
3838   int busy;
39} smc_t;
39};
4040
4141class juicebox_state : public driver_device
4242{
trunk/src/mess/drivers/ptcsol.c
r17909r17910
108108#include "machine/ay31015.h"
109109
110110
111typedef struct {
111struct cass_data_t {
112112   struct {
113113      int length;      /* time cassette level is at input.level */
114114      int level;      /* cassette level */
r17909r17910
119119      int level;      /* cassette level */
120120      int bit;      /* bit to to output */
121121   } output;
122} cass_data_t;
122};
123123
124124class sol20_state : public driver_device
125125{
trunk/src/mess/drivers/ip20.c
r17909r17910
2626#include "machine/scsicd.h"
2727#include "machine/wd33c93.h"
2828
29typedef struct
29struct HPC_t
3030{
3131   UINT8 nMiscStatus;
3232   UINT32 nParBufPtr;
r17909r17910
3636   UINT32 nVMEIntMask1;
3737   UINT32 nSCSI0Descriptor;
3838   UINT32 nSCSI0DMACtrl;
39} HPC_t;
39};
4040
41typedef struct
41struct RTC_t
4242{
4343   UINT8 nRAM[32];
4444   UINT8 nTemp;
45} RTC_t;
45};
4646
4747class ip20_state : public driver_device
4848{
trunk/src/mess/drivers/gba.c
r17909r17910
24742474   return str.trimspace();
24752475}
24762476
2477typedef struct
2477struct gba_chip_fix_conflict_item
24782478{
24792479   char game_code[5];
24802480   UINT32 chip;
2481} gba_chip_fix_conflict_item;
2481};
24822482
24832483static const gba_chip_fix_conflict_item gba_chip_fix_conflict_list[] =
24842484{
r17909r17910
25182518   { "BYUJ", GBA_CHIP_EEPROM_64K }, // 2322 - Yggdra Union (JPN)
25192519};
25202520
2521typedef struct
2521struct gba_chip_fix_eeprom_item
25222522{
25232523   char game_code[5];
2524} gba_chip_fix_eeprom_item;
2524};
25252525
25262526static const gba_chip_fix_eeprom_item gba_chip_fix_eeprom_list[] =
25272527{

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