Previous

199869 Revisions

Next

r17826 Wednesday 12th September, 2012 at 09:44:42 UTC by Aaron Giles
More AM_BASE_LEGACY removal.

[src/mame/drivers]	konamigx.c legionna.c midzeus.c mystwarr.c r2dx_v33.c
[src/mame/includes]	konamigx.h midzeus.h
[src/mame/machine]	seicop.c seicop.h
[src/mame/video]	konamigx.c konamiic.c konamiic.h midzeus.c midzeus2.c
[src/mess/drivers]	mmodular.c ng_aes.c

trunk/src/mame/machine/seicop.c

r17825	r17826
1411	1411	#define seibu_cop_log logerror
1412	1412	#define LOG_CMDS 1
1413	1413
1414		UINT16 *cop_mcu_ram;
	1414	static UINT16 *cop_mcu_ram;
1415	1415
1416	1416	static UINT16 copd2_table[0x100];
1417	1417	static UINT16 copd2_table_2[0x100/8];
r17825	r17826
1664	1664
1665	1665	*******************************************************************************************/
1666	1666
	1667	// temporary hack until this is a proper device
	1668	inline void get_ram(running_machine &machine)
	1669	{
	1670	if (cop_mcu_ram == NULL) cop_mcu_ram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("cop_mcu_ram")->ptr());
	1671	}
	1672
1667	1673	READ16_HANDLER( copdxbl_0_r )
1668	1674	{
	1675	get_ram(space->machine());
1669	1676	UINT16 retvalue = cop_mcu_ram[offset];
1670	1677
1671	1678	switch(offset)
r17825	r17826
1692	1699	WRITE16_HANDLER( copdxbl_0_w )
1693	1700	{
1694	1701	legionna_state *state = space->machine().driver_data<legionna_state>();
	1702	get_ram(space->machine());
1695	1703	COMBINE_DATA(&cop_mcu_ram[offset]);
1696	1704
1697	1705	switch(offset)
r17825	r17826
1814	1822	static READ16_HANDLER( generic_cop_r )
1815	1823	{
1816	1824	UINT16 retvalue;
	1825	get_ram(space->machine());
1817	1826	retvalue = cop_mcu_ram[offset];
1818	1827
1819	1828
r17825	r17826
1883	1892	static WRITE16_HANDLER( generic_cop_w )
1884	1893	{
1885	1894	UINT32 temp32;
	1895	get_ram(space->machine());
1886	1896
1887	1897	switch (offset)
1888	1898	{
r17825	r17826
2716	2726
2717	2727	WRITE16_HANDLER( heatbrl_mcu_w )
2718	2728	{
	2729	get_ram(space->machine());
2719	2730	COMBINE_DATA(&cop_mcu_ram[offset]);
2720	2731
2721	2732	/* external pin register, used for banking */
r17825	r17826
2771	2782
2772	2783	WRITE16_HANDLER( cupsoc_mcu_w )
2773	2784	{
	2785	get_ram(space->machine());
2774	2786	COMBINE_DATA(&cop_mcu_ram[offset]);
2775	2787
2776	2788	if(offset == 0x280/2) //irq ack / sprite buffering?
r17825	r17826
2813	2825
2814	2826	WRITE16_HANDLER( cupsocs_mcu_w )
2815	2827	{
	2828	get_ram(space->machine());
2816	2829	COMBINE_DATA(&cop_mcu_ram[offset]);
2817	2830
2818	2831	if(offset == 0x280/2) //irq ack / sprite buffering?
r17825	r17826
2860	2873
2861	2874	WRITE16_HANDLER( godzilla_mcu_w )
2862	2875	{
	2876	get_ram(space->machine());
2863	2877	COMBINE_DATA(&cop_mcu_ram[offset]);
2864	2878
2865	2879	if(offset == 0x070/2)
r17825	r17826
2912	2926
2913	2927	WRITE16_HANDLER( denjinmk_mcu_w )
2914	2928	{
	2929	get_ram(space->machine());
2915	2930	COMBINE_DATA(&cop_mcu_ram[offset]);
2916	2931
2917	2932	if(offset == 0x280/2) //irq ack / sprite buffering?
r17825	r17826
2965	2980
2966	2981	WRITE16_HANDLER( grainbow_mcu_w )
2967	2982	{
	2983	get_ram(space->machine());
2968	2984	COMBINE_DATA(&cop_mcu_ram[offset]);
2969	2985
2970	2986	if(offset == 0x280/2) //irq ack / sprite buffering?
r17825	r17826
3007	3023
3008	3024	WRITE16_HANDLER( legionna_mcu_w )
3009	3025	{
	3026	get_ram(space->machine());
3010	3027	COMBINE_DATA(&cop_mcu_ram[offset]);
3011	3028
3012	3029	if(offset == 0x070/2) //external pin: puts bit 13 high, delay, reads 0x748, writes bit 13 low

trunk/src/mame/machine/seicop.h

r17825	r17826
1		extern UINT16* cop_mcu_ram;
2
3	1	READ16_HANDLER( copdxbl_0_r );
4	2	WRITE16_HANDLER( copdxbl_0_w );
5	3

trunk/src/mame/video/midzeus.c

r17825	r17826
56	56	*
57	57	*************************************/
58	58
59		UINT32 *zeusbase;
60
61	59	static poly_manager *poly;
62	60	static UINT8 log_fifo;
63	61
r17825	r17826
341	339	/* normal update case */
342	340	if (!screen.machine().input().code_pressed(KEYCODE_W))
343	341	{
344		const void *base = waveram1_ptr_from_expanded_addr(zeusbase[0xcc]);
	342	midzeus_state *state = screen.machine().driver_data<midzeus_state>();
	343	const void *base = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0xcc]);
345	344	int xoffs = screen.visible_area().min_x;
346	345	for (y = cliprect.min_y; y <= cliprect.max_y; y++)
347	346	{
r17825	r17826
390	389	READ32_MEMBER(midzeus_state::zeus_r)
391	390	{
392	391	int logit = (offset < 0xb0 || offset > 0xb7);
393		UINT32 result = zeusbase[offset & ~1];
	392	UINT32 result = m_zeusbase[offset & ~1];
394	393
395	394	switch (offset & ~1)
396	395	{
r17825	r17826
414	413	case 0xf6:      // status -- they wait for this & 9 == 0
415	414	// value & $9600 must == $9600 to pass Zeus system test
416	415	result = 0x9600;
417		if (zeusbase[0xb6] == 0x80040000)
	416	if (m_zeusbase[0xb6] == 0x80040000)
418	417	result |= 1;
419	418	logit = 0;
420	419	break;
421	420	}
422	421
423	422	/* 32-bit mode */
424		if (zeusbase[0x80] & 0x00020000)
	423	if (m_zeusbase[0x80] & 0x00020000)
425	424	{
426	425	if (offset & 1)
427	426	result >>= 16;
r17825	r17826
465	464	logerror("%06X:zeus_w", space.device().safe_pc());
466	465
467	466	/* 32-bit mode */
468		if (zeusbase[0x80] & 0x00020000)
	467	if (m_zeusbase[0x80] & 0x00020000)
469	468	zeus_register32_w(machine(), offset, data, logit);
470	469
471	470	/* 16-bit mode */
r17825	r17826
546	545
547	546	static void zeus_register16_w(running_machine &machine, offs_t offset, UINT16 data, int logit)
548	547	{
	548	midzeus_state *state = machine.driver_data<midzeus_state>();
	549
549	550	/* writes to register $CC need to force a partial update */
550	551	if ((offset & ~1) == 0xcc)
551	552	machine.primary_screen->update_partial(machine.primary_screen->vpos());
552	553
553	554	/* write to high part on odd addresses */
554	555	if (offset & 1)
555		zeusbase[offset & ~1] = (zeusbase[offset & ~1] & 0x0000ffff) | (data << 16);
	556	state->m_zeusbase[offset & ~1] = (state->m_zeusbase[offset & ~1] & 0x0000ffff) | (data << 16);
556	557
557	558	/* write to low part on event addresses */
558	559	else
559		zeusbase[offset & ~1] = (zeusbase[offset & ~1] & 0xffff0000) | (data & 0xffff);
	560	state->m_zeusbase[offset & ~1] = (state->m_zeusbase[offset & ~1] & 0xffff0000) | (data & 0xffff);
560	561
561	562	/* log appropriately */
562	563	if (logit)
563		logerror("(%02X) = %04X [%08X]\n", offset, data & 0xffff, zeusbase[offset & ~1]);
	564	logerror("(%02X) = %04X [%08X]\n", offset, data & 0xffff, state->m_zeusbase[offset & ~1]);
564	565
565	566	/* handle the update */
566	567	if ((offset & 1) == 0)
r17825	r17826
570	571
571	572	static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 data, int logit)
572	573	{
	574	midzeus_state *state = machine.driver_data<midzeus_state>();
	575
573	576	/* writes to register $CC need to force a partial update */
574	577	if ((offset & ~1) == 0xcc)
575	578	machine.primary_screen->update_partial(machine.primary_screen->vpos());
576	579
577	580	/* always write to low word? */
578		zeusbase[offset & ~1] = data;
	581	state->m_zeusbase[offset & ~1] = data;
579	582
580	583	/* log appropriately */
581	584	if (logit)
r17825	r17826
603	606
604	607	static void zeus_register_update(running_machine &machine, offs_t offset)
605	608	{
	609	midzeus_state *state = machine.driver_data<midzeus_state>();
	610
606	611	/* handle the writes; only trigger on low accesses */
607	612	switch (offset)
608	613	{
609	614	case 0x52:
610		zeusbase[0xb2] = zeusbase[0x52];
	615	state->m_zeusbase[0xb2] = state->m_zeusbase[0x52];
611	616	break;
612	617
613	618	case 0x60:
614	619	/* invasn writes here to execute a command (?) */
615		if (zeusbase[0x60] & 1)
	620	if (state->m_zeusbase[0x60] & 1)
616	621	{
617		if ((zeusbase[0x80] & 0xffffff) == 0x22FCFF)
	622	if ((state->m_zeusbase[0x80] & 0xffffff) == 0x22FCFF)
618	623	{
619		// zeusbase[0x00] = color
620		// zeusbase[0x02] = ??? = 0x000C0000
621		// zeusbase[0x04] = ??? = 0x00000E01
622		// zeusbase[0x06] = ??? = 0xFFFF0030
623		// zeusbase[0x08] = vert[0] = (y0 << 16) | x0
624		// zeusbase[0x0a] = vert[1] = (y1 << 16) | x1
625		// zeusbase[0x0c] = vert[2] = (y2 << 16) | x2
626		// zeusbase[0x0e] = vert[3] = (y3 << 16) | x3
627		// zeusbase[0x18] = ??? = 0xFFFFFFFF
628		// zeusbase[0x1a] = ??? = 0xFFFFFFFF
629		// zeusbase[0x1c] = ??? = 0xFFFFFFFF
630		// zeusbase[0x1e] = ??? = 0xFFFFFFFF
631		// zeusbase[0x20] = ??? = 0x00000000
632		// zeusbase[0x22] = ??? = 0x00000000
633		// zeusbase[0x24] = ??? = 0x00000000
634		// zeusbase[0x26] = ??? = 0x00000000
635		// zeusbase[0x40] = ??? = 0x00000000
636		// zeusbase[0x42] = ??? = 0x00000000
637		// zeusbase[0x44] = ??? = 0x00000000
638		// zeusbase[0x46] = ??? = 0x00000000
639		// zeusbase[0x4c] = ??? = 0x00808080 (brightness?)
640		// zeusbase[0x4e] = ??? = 0x00808080 (brightness?)
	624	// state->m_zeusbase[0x00] = color
	625	// state->m_zeusbase[0x02] = ??? = 0x000C0000
	626	// state->m_zeusbase[0x04] = ??? = 0x00000E01
	627	// state->m_zeusbase[0x06] = ??? = 0xFFFF0030
	628	// state->m_zeusbase[0x08] = vert[0] = (y0 << 16) | x0
	629	// state->m_zeusbase[0x0a] = vert[1] = (y1 << 16) | x1
	630	// state->m_zeusbase[0x0c] = vert[2] = (y2 << 16) | x2
	631	// state->m_zeusbase[0x0e] = vert[3] = (y3 << 16) | x3
	632	// state->m_zeusbase[0x18] = ??? = 0xFFFFFFFF
	633	// state->m_zeusbase[0x1a] = ??? = 0xFFFFFFFF
	634	// state->m_zeusbase[0x1c] = ??? = 0xFFFFFFFF
	635	// state->m_zeusbase[0x1e] = ??? = 0xFFFFFFFF
	636	// state->m_zeusbase[0x20] = ??? = 0x00000000
	637	// state->m_zeusbase[0x22] = ??? = 0x00000000
	638	// state->m_zeusbase[0x24] = ??? = 0x00000000
	639	// state->m_zeusbase[0x26] = ??? = 0x00000000
	640	// state->m_zeusbase[0x40] = ??? = 0x00000000
	641	// state->m_zeusbase[0x42] = ??? = 0x00000000
	642	// state->m_zeusbase[0x44] = ??? = 0x00000000
	643	// state->m_zeusbase[0x46] = ??? = 0x00000000
	644	// state->m_zeusbase[0x4c] = ??? = 0x00808080 (brightness?)
	645	// state->m_zeusbase[0x4e] = ??? = 0x00808080 (brightness?)
641	646	poly_extra_data *extra = (poly_extra_data *)poly_get_extra_data(poly);
642	647	poly_vertex vert[4];
643	648
644		vert[0].x = (INT16)zeusbase[0x08];
645		vert[0].y = (INT16)(zeusbase[0x08] >> 16);
646		vert[1].x = (INT16)zeusbase[0x0a];
647		vert[1].y = (INT16)(zeusbase[0x0a] >> 16);
648		vert[2].x = (INT16)zeusbase[0x0c];
649		vert[2].y = (INT16)(zeusbase[0x0c] >> 16);
650		vert[3].x = (INT16)zeusbase[0x0e];
651		vert[3].y = (INT16)(zeusbase[0x0e] >> 16);
	649	vert[0].x = (INT16)state->m_zeusbase[0x08];
	650	vert[0].y = (INT16)(state->m_zeusbase[0x08] >> 16);
	651	vert[1].x = (INT16)state->m_zeusbase[0x0a];
	652	vert[1].y = (INT16)(state->m_zeusbase[0x0a] >> 16);
	653	vert[2].x = (INT16)state->m_zeusbase[0x0c];
	654	vert[2].y = (INT16)(state->m_zeusbase[0x0c] >> 16);
	655	vert[3].x = (INT16)state->m_zeusbase[0x0e];
	656	vert[3].y = (INT16)(state->m_zeusbase[0x0e] >> 16);
652	657
653		extra->solidcolor = zeusbase[0x00];
	658	extra->solidcolor = state->m_zeusbase[0x00];
654	659	extra->zoffset = 0x7fff;
655	660
656	661	poly_render_quad(poly, NULL, zeus_cliprect, render_poly_solid_fixedz, 0, &vert[0], &vert[1], &vert[2], &vert[3]);
r17825	r17826
662	667	break;
663	668
664	669	case 0x70:
665		zeus_point[0] = zeusbase[0x70] << 16;
	670	zeus_point[0] = state->m_zeusbase[0x70] << 16;
666	671	break;
667	672
668	673	case 0x72:
669		zeus_point[1] = zeusbase[0x72] << 16;
	674	zeus_point[1] = state->m_zeusbase[0x72] << 16;
670	675	break;
671	676
672	677	case 0x74:
673		zeus_point[2] = zeusbase[0x74] << 16;
	678	zeus_point[2] = state->m_zeusbase[0x74] << 16;
674	679	break;
675	680
676	681	case 0x80:
677	682	/* this bit enables the "FIFO empty" IRQ; since our virtual FIFO is always empty,
678	683	we simply assert immediately if this is enabled. invasn needs this for proper
679	684	operations */
680		if (zeusbase[0x80] & 0x02000000)
	685	if (state->m_zeusbase[0x80] & 0x02000000)
681	686	machine.device("maincpu")->execute().set_input_line(2, ASSERT_LINE);
682	687	else
683	688	machine.device("maincpu")->execute().set_input_line(2, CLEAR_LINE);
r17825	r17826
686	691	case 0x84:
687	692	/* MK4: Written in tandem with 0xcc */
688	693	/* MK4: Writes either 0x80 (and 0x000000 to 0xcc) or 0x00 (and 0x800000 to 0xcc) */
689		zeus_renderbase = waveram1_ptr_from_expanded_addr(zeusbase[0x84] << 16);
	694	zeus_renderbase = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x84] << 16);
690	695	break;
691	696
692	697	case 0xb0:
693	698	case 0xb2:
694		if ((zeusbase[0xb6] >> 16) != 0)
	699	if ((state->m_zeusbase[0xb6] >> 16) != 0)
695	700	{
696		if ((offset == 0xb0 && (zeusbase[0xb6] & 0x02000000) == 0) ||
697		(offset == 0xb2 && (zeusbase[0xb6] & 0x02000000) != 0))
	701	if ((offset == 0xb0 && (state->m_zeusbase[0xb6] & 0x02000000) == 0) ||
	702	(offset == 0xb2 && (state->m_zeusbase[0xb6] & 0x02000000) != 0))
698	703	{
699	704	void *dest;
700	705
701		if (zeusbase[0xb6] & 0x80000000)
702		dest = waveram1_ptr_from_expanded_addr(zeusbase[0xb4]);
	706	if (state->m_zeusbase[0xb6] & 0x80000000)
	707	dest = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
703	708	else
704		dest = waveram0_ptr_from_expanded_addr(zeusbase[0xb4]);
	709	dest = waveram0_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
705	710
706		if (zeusbase[0xb6] & 0x00100000)
707		WAVERAM_WRITE16(dest, 0, zeusbase[0xb0]);
708		if (zeusbase[0xb6] & 0x00200000)
709		WAVERAM_WRITE16(dest, 1, zeusbase[0xb0] >> 16);
710		if (zeusbase[0xb6] & 0x00400000)
711		WAVERAM_WRITE16(dest, 2, zeusbase[0xb2]);
712		if (zeusbase[0xb6] & 0x00800000)
713		WAVERAM_WRITE16(dest, 3, zeusbase[0xb2] >> 16);
714		if (zeusbase[0xb6] & 0x00020000)
715		zeusbase[0xb4]++;
	711	if (state->m_zeusbase[0xb6] & 0x00100000)
	712	WAVERAM_WRITE16(dest, 0, state->m_zeusbase[0xb0]);
	713	if (state->m_zeusbase[0xb6] & 0x00200000)
	714	WAVERAM_WRITE16(dest, 1, state->m_zeusbase[0xb0] >> 16);
	715	if (state->m_zeusbase[0xb6] & 0x00400000)
	716	WAVERAM_WRITE16(dest, 2, state->m_zeusbase[0xb2]);
	717	if (state->m_zeusbase[0xb6] & 0x00800000)
	718	WAVERAM_WRITE16(dest, 3, state->m_zeusbase[0xb2] >> 16);
	719	if (state->m_zeusbase[0xb6] & 0x00020000)
	720	state->m_zeusbase[0xb4]++;
716	721	}
717	722	}
718	723	break;
719	724
720	725	case 0xb4:
721		if (zeusbase[0xb6] & 0x00010000)
	726	if (state->m_zeusbase[0xb6] & 0x00010000)
722	727	{
723	728	const UINT32 *src;
724	729
725		if (zeusbase[0xb6] & 0x80000000)
726		src = (const UINT32 *)waveram1_ptr_from_expanded_addr(zeusbase[0xb4]);
	730	if (state->m_zeusbase[0xb6] & 0x80000000)
	731	src = (const UINT32 *)waveram1_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
727	732	else
728		src = (const UINT32 *)waveram0_ptr_from_expanded_addr(zeusbase[0xb4]);
	733	src = (const UINT32 *)waveram0_ptr_from_expanded_addr(state->m_zeusbase[0xb4]);
729	734
730	735	poly_wait(poly, "vram_read");
731		zeusbase[0xb0] = WAVERAM_READ32(src, 0);
732		zeusbase[0xb2] = WAVERAM_READ32(src, 1);
	736	state->m_zeusbase[0xb0] = WAVERAM_READ32(src, 0);
	737	state->m_zeusbase[0xb2] = WAVERAM_READ32(src, 1);
733	738	}
734	739	break;
735	740
r17825	r17826
741	746	case 0xca:
742	747	machine.primary_screen->update_partial(machine.primary_screen->vpos());
743	748	{
744		int vtotal = zeusbase[0xca] >> 16;
745		int htotal = zeusbase[0xc6] >> 16;
	749	int vtotal = state->m_zeusbase[0xca] >> 16;
	750	int htotal = state->m_zeusbase[0xc6] >> 16;
746	751
747		rectangle visarea(zeusbase[0xc6] & 0xffff, htotal - 3, 0, zeusbase[0xc8] & 0xffff);
	752	rectangle visarea(state->m_zeusbase[0xc6] & 0xffff, htotal - 3, 0, state->m_zeusbase[0xc8] & 0xffff);
748	753	if (htotal > 0 && vtotal > 0 && visarea.min_x < visarea.max_x && visarea.max_y < vtotal)
749	754	{
750	755	machine.primary_screen->configure(htotal, vtotal, visarea, HZ_TO_ATTOSECONDS((double)MIDZEUS_VIDEO_CLOCK / 8.0 / (htotal * vtotal)));
r17825	r17826
761	766	break;
762	767
763	768	case 0xe0:
764		zeus_fifo[zeus_fifo_words++] = zeusbase[0xe0];
	769	zeus_fifo[zeus_fifo_words++] = state->m_zeusbase[0xe0];
765	770	if (zeus_fifo_process(machine, zeus_fifo, zeus_fifo_words))
766	771	zeus_fifo_words = 0;
767	772	break;
r17825	r17826
778	783
779	784	static int zeus_fifo_process(running_machine &machine, const UINT32 *data, int numwords)
780	785	{
	786	midzeus_state *state = machine.driver_data<midzeus_state>();
	787
781	788	/* handle logging */
782	789	switch (data[0] >> 24)
783	790	{
r17825	r17826
796	803	case 0x13:   /* invasn */
797	804	if (log_fifo)
798	805	log_fifo_command(data, numwords, "");
799		zeus_draw_model(machine, (zeusbase[0x06] << 16), log_fifo);
	806	zeus_draw_model(machine, (state->m_zeusbase[0x06] << 16), log_fifo);
800	807	break;
801	808
802	809	/* 0x17: write 16-bit value to low registers */
r17825	r17826
957	964	}
958	965	else
959	966	{
960		UINT32 texdata = (zeusbase[0x06] << 16) | (zeusbase[0x00] >> 16);
	967	UINT32 texdata = (state->m_zeusbase[0x06] << 16) | (state->m_zeusbase[0x00] >> 16);
961	968	zeus_draw_quad(machine, FALSE, data, texdata, log_fifo);
962	969	}
963	970	break;
r17825	r17826
999	1006
1000	1007	static void zeus_draw_model(running_machine &machine, UINT32 texdata, int logit)
1001	1008	{
	1009	midzeus_state *state = machine.driver_data<midzeus_state>();
1002	1010	UINT32 databuffer[32];
1003	1011	int databufcount = 0;
1004	1012	int model_done = FALSE;
r17825	r17826
1058	1066	logerror("reg16");
1059	1067	zeus_register16_w(machine, (databuffer[0] >> 16) & 0x7f, databuffer[0], logit);
1060	1068	if (((databuffer[0] >> 16) & 0x7f) == 0x06)
1061		texdata = (texdata & 0xffff) | (zeusbase[0x06] << 16);
	1069	texdata = (texdata & 0xffff) | (state->m_zeusbase[0x06] << 16);
1062	1070	break;
1063	1071
1064	1072	case 0x19:   /* invasn */
r17825	r17826
1066	1074	logerror("reg32");
1067	1075	zeus_register32_w(machine, (databuffer[0] >> 16) & 0x7f, databuffer[1], logit);
1068	1076	if (((databuffer[0] >> 16) & 0x7f) == 0x06)
1069		texdata = (texdata & 0xffff) | (zeusbase[0x06] << 16);
	1077	texdata = (texdata & 0xffff) | (state->m_zeusbase[0x06] << 16);
1070	1078	break;
1071	1079
1072	1080	case 0x25:   /* mk4 */
r17825	r17826
1098	1106
1099	1107	static void zeus_draw_quad(running_machine &machine, int long_fmt, const UINT32 *databuffer, UINT32 texdata, int logit)
1100	1108	{
	1109	midzeus_state *state = machine.driver_data<midzeus_state>();
1101	1110	poly_draw_scanline_func callback;
1102	1111	poly_extra_data *extra;
1103	1112	poly_vertex clipvert[8];
r17825	r17826
1148	1157	val2 = (texdata >> 16) & 0x3ff;
1149	1158	texwshift = (val2 >> 6) & 7;
1150	1159
1151		uscale = (8 >> ((zeusbase[0x04] >> 4) & 3)) * 0.125f * 256.0f;
1152		vscale = (8 >> ((zeusbase[0x04] >> 6) & 3)) * 0.125f * 256.0f;
	1160	uscale = (8 >> ((state->m_zeusbase[0x04] >> 4) & 3)) * 0.125f * 256.0f;
	1161	vscale = (8 >> ((state->m_zeusbase[0x04] >> 6) & 3)) * 0.125f * 256.0f;
1153	1162
1154	1163	int xy_offset = long_fmt ? 2 : 1;
1155	1164
r17825	r17826
1265	1274	printf("Unknown draw mode: %.8x\n", ctrl_word);
1266	1275	return;
1267	1276	}
1268		extra->solidcolor = zeusbase[0x00] & 0x7fff;
1269		extra->zoffset = zeusbase[0x7e] >> 16;
1270		extra->alpha = zeusbase[0x4e];
	1277	extra->solidcolor = state->m_zeusbase[0x00] & 0x7fff;
	1278	extra->zoffset = state->m_zeusbase[0x7e] >> 16;
	1279	extra->alpha = state->m_zeusbase[0x4e];
1271	1280	extra->transcolor = ((ctrl_word >> 16) & 1) ? 0 : 0x100;
1272	1281	extra->palbase = waveram0_ptr_from_block_addr(zeus_palbase);
1273	1282

trunk/src/mame/video/midzeus2.c

r17825	r17826
370	370	/* normal update case */
371	371	if (!screen.machine().input().code_pressed(KEYCODE_W))
372	372	{
373		const void *base = waveram1_ptr_from_expanded_addr(zeusbase[0x38]);
	373	midzeus_state *state = screen.machine().driver_data<midzeus_state>();
	374	const void *base = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x38]);
374	375	int xoffs = screen.visible_area().min_x;
375	376	for (y = cliprect.min_y; y <= cliprect.max_y; y++)
376	377	{
r17825	r17826
419	420	READ32_HANDLER( zeus2_r )
420	421	{
421	422	int logit = (offset != 0x00 && offset != 0x01 && offset != 0x54 && offset != 0x48 && offset != 0x49 && offset != 0x58 && offset != 0x59 && offset != 0x5a);
422		UINT32 result = zeusbase[offset];
	423	midzeus_state *state = space->machine().driver_data<midzeus_state>();
	424	UINT32 result = state->m_zeusbase[offset];
423	425
424	426	#if TRACK_REG_USAGE
425	427	regread_count[offset]++;
r17825	r17826
486	488
487	489	static void zeus_register32_w(running_machine &machine, offs_t offset, UINT32 data, int logit)
488	490	{
489		UINT32 oldval = zeusbase[offset];
	491	midzeus_state *state = machine.driver_data<midzeus_state>();
	492	UINT32 oldval = state->m_zeusbase[offset];
490	493
491	494	#if TRACK_REG_USAGE
492	495	regwrite_count[offset]++;
r17825	r17826
512	515	//      machine.primary_screen->update_partial(machine.primary_screen->vpos());
513	516
514	517	/* always write to low word? */
515		zeusbase[offset] = data;
	518	state->m_zeusbase[offset] = data;
516	519
517	520	/* log appropriately */
518	521	if (logit)
r17825	r17826
533	536	static void zeus_register_update(running_machine &machine, offs_t offset, UINT32 oldval, int logit)
534	537	{
535	538	/* handle the writes; only trigger on low accesses */
	539	midzeus_state *state = machine.driver_data<midzeus_state>();
536	540	switch (offset)
537	541	{
538	542	case 0x08:
539		zeus_fifo[zeus_fifo_words++] = zeusbase[0x08];
	543	zeus_fifo[zeus_fifo_words++] = state->m_zeusbase[0x08];
540	544	if (zeus_fifo_process(machine, zeus_fifo, zeus_fifo_words))
541	545	zeus_fifo_words = 0;
542	546
r17825	r17826
547	551	case 0x20:
548	552	/* toggles between two values based on the page:
549	553
550		Page #      zeusbase[0x20]      zeusbase[0x38]
	554	Page #      state->m_zeusbase[0x20]      state->m_zeusbase[0x38]
551	555	------      --------------      --------------
552	556	0          $04000190           $00000000
553	557	1          $04000000           $01900000
554	558	*/
555		zeus_pointer_write(zeusbase[0x20] >> 24, zeusbase[0x20]);
	559	zeus_pointer_write(state->m_zeusbase[0x20] >> 24, state->m_zeusbase[0x20]);
556	560	break;
557	561
558	562	case 0x33:
r17825	r17826
562	566	case 0x37:
563	567	machine.primary_screen->update_partial(machine.primary_screen->vpos());
564	568	{
565		int vtotal = zeusbase[0x37] & 0xffff;
566		int htotal = zeusbase[0x34] >> 16;
	569	int vtotal = state->m_zeusbase[0x37] & 0xffff;
	570	int htotal = state->m_zeusbase[0x34] >> 16;
567	571
568		rectangle visarea(zeusbase[0x33] >> 16, (zeusbase[0x34] & 0xffff) - 1, 0, zeusbase[0x35] & 0xffff);
	572	rectangle visarea(state->m_zeusbase[0x33] >> 16, (state->m_zeusbase[0x34] & 0xffff) - 1, 0, state->m_zeusbase[0x35] & 0xffff);
569	573	if (htotal > 0 && vtotal > 0 && visarea.min_x < visarea.max_x && visarea.max_y < vtotal)
570	574	{
571	575	machine.primary_screen->configure(htotal, vtotal, visarea, HZ_TO_ATTOSECONDS((double)MIDZEUS_VIDEO_CLOCK / 4.0 / (htotal * vtotal)));
r17825	r17826
578	582
579	583	case 0x38:
580	584	{
581		UINT32 temp = zeusbase[0x38];
582		zeusbase[0x38] = oldval;
	585	UINT32 temp = state->m_zeusbase[0x38];
	586	state->m_zeusbase[0x38] = oldval;
583	587	machine.primary_screen->update_partial(machine.primary_screen->vpos());
584	588	log_fifo = machine.input().code_pressed(KEYCODE_L);
585		zeusbase[0x38] = temp;
	589	state->m_zeusbase[0x38] = temp;
586	590	}
587	591	break;
588	592
589	593	case 0x41:
590	594	/* this is the address, except in read mode, where it latches values */
591		if (zeusbase[0x4e] & 0x10)
	595	if (state->m_zeusbase[0x4e] & 0x10)
592	596	{
593	597	const void *src = waveram0_ptr_from_expanded_addr(oldval);
594		zeusbase[0x41] = oldval;
595		zeusbase[0x48] = WAVERAM_READ32(src, 0);
596		zeusbase[0x49] = WAVERAM_READ32(src, 1);
	598	state->m_zeusbase[0x41] = oldval;
	599	state->m_zeusbase[0x48] = WAVERAM_READ32(src, 0);
	600	state->m_zeusbase[0x49] = WAVERAM_READ32(src, 1);
597	601
598		if (zeusbase[0x4e] & 0x40)
	602	if (state->m_zeusbase[0x4e] & 0x40)
599	603	{
600		zeusbase[0x41]++;
601		zeusbase[0x41] += (zeusbase[0x41] & 0x400) << 6;
602		zeusbase[0x41] &= ~0xfc00;
	604	state->m_zeusbase[0x41]++;
	605	state->m_zeusbase[0x41] += (state->m_zeusbase[0x41] & 0x400) << 6;
	606	state->m_zeusbase[0x41] &= ~0xfc00;
603	607	}
604	608	}
605	609	break;
r17825	r17826
607	611	case 0x48:
608	612	case 0x49:
609	613	/* if we're in write mode, process it */
610		if (zeusbase[0x40] == 0x00890000)
	614	if (state->m_zeusbase[0x40] == 0x00890000)
611	615	{
612	616	/*
613		zeusbase[0x4e]:
	617	state->m_zeusbase[0x4e]:
614	618	bit 0-1: which register triggers write through
615	619	bit 3:   enable write through via these registers
616	620	bit 4:   seems to be set during reads, when 0x41 is used for latching
617	621	bit 6:   enable autoincrement on write through
618	622	*/
619		if ((zeusbase[0x4e] & 0x08) && (offset & 3) == (zeusbase[0x4e] & 3))
	623	if ((state->m_zeusbase[0x4e] & 0x08) && (offset & 3) == (state->m_zeusbase[0x4e] & 3))
620	624	{
621		void *dest = waveram0_ptr_from_expanded_addr(zeusbase[0x41]);
622		WAVERAM_WRITE32(dest, 0, zeusbase[0x48]);
623		WAVERAM_WRITE32(dest, 1, zeusbase[0x49]);
	625	void *dest = waveram0_ptr_from_expanded_addr(state->m_zeusbase[0x41]);
	626	WAVERAM_WRITE32(dest, 0, state->m_zeusbase[0x48]);
	627	WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x49]);
624	628
625		if (zeusbase[0x4e] & 0x40)
	629	if (state->m_zeusbase[0x4e] & 0x40)
626	630	{
627		zeusbase[0x41]++;
628		zeusbase[0x41] += (zeusbase[0x41] & 0x400) << 6;
629		zeusbase[0x41] &= ~0xfc00;
	631	state->m_zeusbase[0x41]++;
	632	state->m_zeusbase[0x41] += (state->m_zeusbase[0x41] & 0x400) << 6;
	633	state->m_zeusbase[0x41] &= ~0xfc00;
630	634	}
631	635	}
632	636	}
633	637
634	638	/* make sure we log anything else */
635	639	else if (logit)
636		logerror("\t[40]=%08X [4E]=%08X\n", zeusbase[0x40], zeusbase[0x4e]);
	640	logerror("\t[40]=%08X [4E]=%08X\n", state->m_zeusbase[0x40], state->m_zeusbase[0x4e]);
637	641	break;
638	642
639	643	case 0x51:
640	644
641	645	/* in this mode, crusnexo expects the reads to immediately latch */
642		if (zeusbase[0x50] == 0x00a20000)
643		oldval = zeusbase[0x51];
	646	if (state->m_zeusbase[0x50] == 0x00a20000)
	647	oldval = state->m_zeusbase[0x51];
644	648
645	649	/* this is the address, except in read mode, where it latches values */
646		if ((zeusbase[0x5e] & 0x10) || (zeusbase[0x50] == 0x00a20000))
	650	if ((state->m_zeusbase[0x5e] & 0x10) || (state->m_zeusbase[0x50] == 0x00a20000))
647	651	{
648	652	const void *src = waveram1_ptr_from_expanded_addr(oldval);
649		zeusbase[0x51] = oldval;
650		zeusbase[0x58] = WAVERAM_READ32(src, 0);
651		zeusbase[0x59] = WAVERAM_READ32(src, 1);
652		zeusbase[0x5a] = WAVERAM_READ32(src, 2);
	653	state->m_zeusbase[0x51] = oldval;
	654	state->m_zeusbase[0x58] = WAVERAM_READ32(src, 0);
	655	state->m_zeusbase[0x59] = WAVERAM_READ32(src, 1);
	656	state->m_zeusbase[0x5a] = WAVERAM_READ32(src, 2);
653	657
654		if (zeusbase[0x5e] & 0x40)
	658	if (state->m_zeusbase[0x5e] & 0x40)
655	659	{
656		zeusbase[0x51]++;
657		zeusbase[0x51] += (zeusbase[0x51] & 0x200) << 7;
658		zeusbase[0x51] &= ~0xfe00;
	660	state->m_zeusbase[0x51]++;
	661	state->m_zeusbase[0x51] += (state->m_zeusbase[0x51] & 0x200) << 7;
	662	state->m_zeusbase[0x51] &= ~0xfe00;
659	663	}
660	664	}
661	665	break;
662	666
663	667	case 0x57:
664	668	/* thegrid uses this to write either left or right halves of pixels */
665		if (zeusbase[0x50] == 0x00e90000)
	669	if (state->m_zeusbase[0x50] == 0x00e90000)
666	670	{
667		void *dest = waveram1_ptr_from_expanded_addr(zeusbase[0x51]);
668		if (zeusbase[0x57] & 1)
669		WAVERAM_WRITE32(dest, 0, zeusbase[0x58]);
670		if (zeusbase[0x57] & 4)
671		WAVERAM_WRITE32(dest, 1, zeusbase[0x59]);
	671	void *dest = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x51]);
	672	if (state->m_zeusbase[0x57] & 1)
	673	WAVERAM_WRITE32(dest, 0, state->m_zeusbase[0x58]);
	674	if (state->m_zeusbase[0x57] & 4)
	675	WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x59]);
672	676	}
673	677
674	678	/* make sure we log anything else */
675	679	else if (logit)
676		logerror("\t[50]=%08X [5E]=%08X\n", zeusbase[0x50], zeusbase[0x5e]);
	680	logerror("\t[50]=%08X [5E]=%08X\n", state->m_zeusbase[0x50], state->m_zeusbase[0x5e]);
677	681	break;
678	682
679	683	case 0x58:
680	684	case 0x59:
681	685	case 0x5a:
682	686	/* if we're in write mode, process it */
683		if (zeusbase[0x50] == 0x00890000)
	687	if (state->m_zeusbase[0x50] == 0x00890000)
684	688	{
685	689	/*
686		zeusbase[0x5e]:
	690	state->m_zeusbase[0x5e]:
687	691	bit 0-1: which register triggers write through
688	692	bit 3:   enable write through via these registers
689	693	bit 4:   seems to be set during reads, when 0x51 is used for latching
690	694	bit 5:   unknown, currently used to specify ordering, but this is suspect
691	695	bit 6:   enable autoincrement on write through
692	696	*/
693		if ((zeusbase[0x5e] & 0x08) && (offset & 3) == (zeusbase[0x5e] & 3))
	697	if ((state->m_zeusbase[0x5e] & 0x08) && (offset & 3) == (state->m_zeusbase[0x5e] & 3))
694	698	{
695		void *dest = waveram1_ptr_from_expanded_addr(zeusbase[0x51]);
696		WAVERAM_WRITE32(dest, 0, zeusbase[0x58]);
697		if (zeusbase[0x5e] & 0x20)
698		WAVERAM_WRITE32(dest, 1, zeusbase[0x5a]);
	699	void *dest = waveram1_ptr_from_expanded_addr(state->m_zeusbase[0x51]);
	700	WAVERAM_WRITE32(dest, 0, state->m_zeusbase[0x58]);
	701	if (state->m_zeusbase[0x5e] & 0x20)
	702	WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x5a]);
699	703	else
700	704	{
701		WAVERAM_WRITE32(dest, 1, zeusbase[0x59]);
702		WAVERAM_WRITE32(dest, 2, zeusbase[0x5a]);
	705	WAVERAM_WRITE32(dest, 1, state->m_zeusbase[0x59]);
	706	WAVERAM_WRITE32(dest, 2, state->m_zeusbase[0x5a]);
703	707	}
704	708
705		if (zeusbase[0x5e] & 0x40)
	709	if (state->m_zeusbase[0x5e] & 0x40)
706	710	{
707		zeusbase[0x51]++;
708		zeusbase[0x51] += (zeusbase[0x51] & 0x200) << 7;
709		zeusbase[0x51] &= ~0xfe00;
	711	state->m_zeusbase[0x51]++;
	712	state->m_zeusbase[0x51] += (state->m_zeusbase[0x51] & 0x200) << 7;
	713	state->m_zeusbase[0x51] &= ~0xfe00;
710	714	}
711	715	}
712	716	}
713	717
714	718	/* make sure we log anything else */
715	719	else if (logit)
716		logerror("\t[50]=%08X [5E]=%08X\n", zeusbase[0x50], zeusbase[0x5e]);
	720	logerror("\t[50]=%08X [5E]=%08X\n", state->m_zeusbase[0x50], state->m_zeusbase[0x5e]);
717	721	break;
718	722	}
719	723	}
r17825	r17826
1038	1042
1039	1043	static void zeus_draw_quad(running_machine &machine, const UINT32 *databuffer, UINT32 texoffs, int logit)
1040	1044	{
	1045	midzeus_state *state = machine.driver_data<midzeus_state>();
1041	1046	poly_draw_scanline_func callback;
1042	1047	poly_extra_data *extra;
1043	1048	poly_vertex clipvert[8];
r17825	r17826
1249	1254	}
1250	1255	}
1251	1256
1252		extra->solidcolor = 0;//zeusbase[0x00] & 0x7fff;
1253		extra->zoffset = 0;//zeusbase[0x7e] >> 16;
1254		extra->alpha = 0;//zeusbase[0x4e];
	1257	extra->solidcolor = 0;//state->m_zeusbase[0x00] & 0x7fff;
	1258	extra->zoffset = 0;//state->m_zeusbase[0x7e] >> 16;
	1259	extra->alpha = 0;//state->m_zeusbase[0x4e];
1255	1260	extra->transcolor = 0x100;//((databuffer[1] >> 16) & 1) ? 0 : 0x100;
1256	1261	extra->texbase = WAVERAM_BLOCK0(zeus_texbase);
1257		extra->palbase = waveram0_ptr_from_expanded_addr(zeusbase[0x41]);
	1262	extra->palbase = waveram0_ptr_from_expanded_addr(state->m_zeusbase[0x41]);
1258	1263
1259	1264	poly_render_quad_fan(poly, NULL, zeus_cliprect, callback, 4, numverts, &clipvert[0]);
1260	1265	}

trunk/src/mame/video/konamiic.c

r17825	r17826
1510	1510
1511	1511	#define K053936_MAX_CHIPS 2
1512	1512
1513		UINT16 *K053936_0_ctrl,*K053936_0_linectrl;
1514		UINT16 *K053936_1_ctrl,*K053936_1_linectrl;
1515	1513	static int K053936_offset[K053936_MAX_CHIPS][2];
1516	1514	static int K053936_wraparound[K053936_MAX_CHIPS];
1517	1515
r17825	r17826
1641	1639
1642	1640	void K053936_0_zoom_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack)
1643	1641	{
1644		K053936_zoom_draw(0,K053936_0_ctrl,K053936_0_linectrl,bitmap,cliprect,tmap,flags,priority, glfgreat_hack);
	1642	UINT16 *ctrl = reinterpret_cast<UINT16 *>(tmap->machine().root_device().memshare("k053936_0_ctrl")->ptr());
	1643	UINT16 *linectrl = reinterpret_cast<UINT16 *>(tmap->machine().root_device().memshare("k053936_0_line")->ptr());
	1644	K053936_zoom_draw(0,ctrl,linectrl,bitmap,cliprect,tmap,flags,priority, glfgreat_hack);
1645	1645	}
1646	1646
1647	1647	void K053936_wraparound_enable(int chip, int status)

trunk/src/mame/video/konamiic.h

r17825	r17826
36	36	int K053246_read_register(int regnum);
37	37
38	38	extern UINT16 *K053936_0_ctrl,*K053936_0_linectrl;
39		extern UINT16 *K053936_1_ctrl,*K053936_1_linectrl;
	39	//extern UINT16 *K053936_1_ctrl,*K053936_1_linectrl;
40	40	void K053936_0_zoom_draw(bitmap_ind16 &bitmap,const rectangle &cliprect,tilemap_t *tmap,int flags,UINT32 priority, int glfgreat_hack);
41	41	void K053936_wraparound_enable(int chip, int status);
42	42	void K053936_set_offset(int chip, int xoffs, int yoffs);

trunk/src/mame/video/konamigx.c

r17825	r17826
348	348	static void K053936GP_0_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect,
349	349	tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output)
350	350	{
351		K053936GP_zoom_draw(machine, 0,K053936_0_ctrl,K053936_0_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output);
	351	konamigx_state *state = machine.driver_data<konamigx_state>();
	352	K053936GP_zoom_draw(machine, 0,state->m_k053936_0_ctrl,state->m_k053936_0_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output);
352	353	}
353	354
354	355	static void K053936GP_1_zoom_draw(running_machine &machine, bitmap_rgb32 &bitmap, const rectangle &cliprect,
355	356	tilemap_t *tmap, int tilebpp, int blend, int alpha, int pixeldouble_output)
356	357	{
357		K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output);
	358	//   konamigx_state *state = machine.driver_data<konamigx_state>();
	359	//   K053936GP_zoom_draw(machine, 1,K053936_1_ctrl,K053936_1_linectrl,bitmap,cliprect,tmap,tilebpp,blend,alpha, pixeldouble_output);
358	360	}
359	361
360	362

trunk/src/mame/includes/midzeus.h

r17825	r17826
11	11	public:
12	12	midzeus_state(const machine_config &mconfig, device_type type, const char *tag)
13	13	: driver_device(mconfig, type, tag),
14		m_nvram(*this, "nvram") { }
	14	m_nvram(*this, "nvram"),
	15	m_ram_base(*this, "ram_base"),
	16	m_linkram(*this, "linkram"),
	17	m_tms32031_control(*this, "tms32031_ctl"),
	18	m_zeusbase(*this, "zeusbase") { }
15	19
16	20	required_shared_ptr<UINT32>   m_nvram;
	21	required_shared_ptr<UINT32>   m_ram_base;
	22	optional_shared_ptr<UINT32>   m_linkram;
	23	required_shared_ptr<UINT32>   m_tms32031_control;
	24	required_shared_ptr<UINT32>   m_zeusbase;
	25
17	26	DECLARE_WRITE32_MEMBER(cmos_w);
18	27	DECLARE_READ32_MEMBER(cmos_r);
19	28	DECLARE_WRITE32_MEMBER(cmos_protect_w);
r17825	r17826
48	57
49	58	/*----------- defined in video/midzeus.c -----------*/
50	59
51		extern UINT32 *zeusbase;
52
53	60	VIDEO_START( midzeus );
54	61	SCREEN_UPDATE_IND16( midzeus );
55	62

trunk/src/mame/includes/konamigx.h

r17825	r17826
6	6	m_maincpu(*this,"maincpu"),
7	7	m_workram(*this,"workram"),
8	8	m_psacram(*this,"psacram"),
9		m_subpaletteram32(*this,"subpaletteram")
	9	m_subpaletteram32(*this,"subpaletteram"),
	10	m_k053936_0_ctrl(*this,"k053936_0_ctrl",32),
	11	m_k053936_0_linectrl(*this,"k053936_0_line",32)
10	12	{ }
11	13
12	14	required_device<cpu_device> m_maincpu;
13		required_shared_ptr<UINT32> m_workram;
	15	optional_shared_ptr<UINT32> m_workram;
14	16	optional_shared_ptr<UINT32> m_psacram;
15	17	optional_shared_ptr<UINT32> m_subpaletteram32;
	18	optional_shared_ptr<UINT16> m_k053936_0_ctrl;
	19	optional_shared_ptr<UINT16> m_k053936_0_linectrl;
16	20	DECLARE_WRITE32_MEMBER(esc_w);
17	21	DECLARE_WRITE32_MEMBER(eeprom_w);
18	22	DECLARE_WRITE32_MEMBER(control_w);

trunk/src/mame/drivers/midzeus.c

r17825	r17826
56	56	static UINT8         keypad_select;
57	57	static UINT8         bitlatch[10];
58	58
59		static UINT32 *ram_base;
60	59	static UINT8 cmos_protected;
61	60
62		static UINT32 *linkram;
63	61
64	62	static emu_timer *timer[2];
65	63
66		static UINT32 *tms32031_control;
67
68
69	64	static TIMER_CALLBACK( invasn_gun_callback );
70	65
71	66
r17825	r17826
95	90
96	91	static MACHINE_RESET( midzeus )
97	92	{
98		memcpy(ram_base, machine.root_device().memregion("user1")->base(), 0x40000*4);
99		*ram_base <<= 1;
	93	midzeus_state *state = machine.driver_data<midzeus_state>();
	94
	95	memcpy(state->m_ram_base, machine.root_device().memregion("user1")->base(), 0x40000*4);
	96	*state->m_ram_base <<= 1;
100	97	machine.device("maincpu")->reset();
101	98
102	99	cmos_protected = TRUE;
r17825	r17826
362	359	return 0x30313042;
363	360	else if (offset == 0x3c)
364	361	return 0xffffffff;
365		return linkram[offset];
	362	return m_linkram[offset];
366	363	}
367	364
368	365	WRITE32_MEMBER(midzeus_state::linkram_w)
369	366	{
370	367	logerror("%06X:unknown_8a000_w(%02X) = %08X\n", space.device().safe_pc(),  offset, data);
371		COMBINE_DATA(&linkram[offset]);
	368	COMBINE_DATA(&m_linkram[offset]);
372	369	}
373	370
374	371
r17825	r17826
394	391	if (offset != 0x64)
395	392	logerror("%06X:tms32031_control_r(%02X)\n", space.device().safe_pc(), offset);
396	393
397		return tms32031_control[offset];
	394	return m_tms32031_control[offset];
398	395	}
399	396
400	397
401	398	WRITE32_MEMBER(midzeus_state::tms32031_control_w)
402	399	{
403		COMBINE_DATA(&tms32031_control[offset]);
	400	COMBINE_DATA(&m_tms32031_control[offset]);
404	401
405	402	/* ignore changes to the memory control register */
406	403	if (offset == 0x64)
r17825	r17826
567	564
568	565	static ADDRESS_MAP_START( zeus_map, AS_PROGRAM, 32, midzeus_state )
569	566	ADDRESS_MAP_UNMAP_HIGH
570		AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_BASE_LEGACY(&ram_base)
	567	AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_SHARE("ram_base")
571	568	AM_RANGE(0x400000, 0x41ffff) AM_RAM
572		AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_BASE_LEGACY(&tms32031_control)
573		AM_RANGE(0x880000, 0x8803ff) AM_READWRITE(zeus_r, zeus_w) AM_BASE_LEGACY(&zeusbase)
	569	AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl")
	570	AM_RANGE(0x880000, 0x8803ff) AM_READWRITE(zeus_r, zeus_w) AM_SHARE("zeusbase")
574	571	AM_RANGE(0x8d0000, 0x8d0004) AM_READWRITE(bitlatches_r, bitlatches_w)
575	572	AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
576	573	AM_RANGE(0x9e0000, 0x9e0000) AM_WRITENOP      // watchdog?
r17825	r17826
582	579
583	580	static ADDRESS_MAP_START( zeus2_map, AS_PROGRAM, 32, midzeus_state )
584	581	ADDRESS_MAP_UNMAP_HIGH
585		AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_BASE_LEGACY(&ram_base)
	582	AM_RANGE(0x000000, 0x03ffff) AM_RAM AM_SHARE("ram_base")
586	583	AM_RANGE(0x400000, 0x43ffff) AM_RAM
587		AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_BASE_LEGACY(&tms32031_control)
588		AM_RANGE(0x880000, 0x88007f) AM_READWRITE_LEGACY(zeus2_r, zeus2_w) AM_BASE_LEGACY(&zeusbase)
589		AM_RANGE(0x8a0000, 0x8a003f) AM_READWRITE(linkram_r, linkram_w) AM_BASE_LEGACY(&linkram)
	584	AM_RANGE(0x808000, 0x80807f) AM_READWRITE(tms32031_control_r, tms32031_control_w) AM_SHARE("tms32031_ctl")
	585	AM_RANGE(0x880000, 0x88007f) AM_READWRITE_LEGACY(zeus2_r, zeus2_w) AM_SHARE("zeusbase")
	586	AM_RANGE(0x8a0000, 0x8a003f) AM_READWRITE(linkram_r, linkram_w) AM_SHARE("linkram")
590	587	AM_RANGE(0x8d0000, 0x8d000a) AM_READWRITE(bitlatches_r, bitlatches_w)
591	588	AM_RANGE(0x900000, 0x91ffff) AM_READWRITE(zpram_r, zpram_w) AM_SHARE("nvram") AM_MIRROR(0x020000)
592	589	AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)

trunk/src/mame/drivers/legionna.c

r17825	r17826
82	82	static ADDRESS_MAP_START( legionna_map, AS_PROGRAM, 16, legionna_state )
83	83	AM_RANGE(0x000000, 0x07ffff) AM_ROM
84	84	AM_RANGE(0x100000, 0x1003ff) AM_RAM
85		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(legionna_mcu_r, legionna_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)   /* COP mcu */
	85	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(legionna_mcu_r, legionna_mcu_w) AM_SHARE("cop_mcu_ram")   /* COP mcu */
86	86	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
87	87	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
88	88	AM_RANGE(0x102000, 0x1027ff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
r17825	r17826
97	97	static ADDRESS_MAP_START( heatbrl_map, AS_PROGRAM, 16, legionna_state )
98	98	AM_RANGE(0x000000, 0x07ffff) AM_ROM
99	99	AM_RANGE(0x100000, 0x1003ff) AM_RAM
100		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(heatbrl_mcu_r, heatbrl_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)   /* COP mcu */
	100	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(heatbrl_mcu_r, heatbrl_mcu_w) AM_SHARE("cop_mcu_ram")   /* COP mcu */
101	101	AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
102	102	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
103	103	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
r17825	r17826
110	110	static ADDRESS_MAP_START( godzilla_map, AS_PROGRAM, 16, legionna_state )
111	111	AM_RANGE(0x000000, 0x07ffff) AM_ROM
112	112	AM_RANGE(0x100000, 0x1003ff) AM_RAM
113		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(godzilla_mcu_r, godzilla_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)   /* COP mcu */
	113	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(godzilla_mcu_r, godzilla_mcu_w) AM_SHARE("cop_mcu_ram")   /* COP mcu */
114	114	AM_RANGE(0x100800, 0x100fff) AM_RAM
115	115	AM_RANGE(0x101000, 0x101fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
116	116	AM_RANGE(0x102000, 0x1027ff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
r17825	r17826
135	135	static ADDRESS_MAP_START( denjinmk_map, AS_PROGRAM, 16, legionna_state )
136	136	AM_RANGE(0x000000, 0x0fffff) AM_ROM
137	137	AM_RANGE(0x100000, 0x1003ff) AM_RAM
138		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(denjinmk_mcu_r, denjinmk_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)   /* COP mcu */
	138	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(denjinmk_mcu_r, denjinmk_mcu_w) AM_SHARE("cop_mcu_ram")   /* COP mcu */
139	139	AM_RANGE(0x100800, 0x100fff) AM_RAM
140	140	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
141	141	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
r17825	r17826
152	152	static ADDRESS_MAP_START( grainbow_map, AS_PROGRAM, 16, legionna_state )
153	153	AM_RANGE(0x000000, 0x0fffff) AM_ROM
154	154	AM_RANGE(0x100000, 0x1003ff) AM_RAM
155		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(grainbow_mcu_r, grainbow_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)   /* COP mcu */
	155	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(grainbow_mcu_r, grainbow_mcu_w) AM_SHARE("cop_mcu_ram")   /* COP mcu */
156	156	AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
157	157	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
158	158	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
r17825	r17826
168	168	static ADDRESS_MAP_START( cupsoc_mem, AS_PROGRAM, 16, legionna_state )
169	169	AM_RANGE(0x000000, 0x0fffff) AM_ROM
170	170	AM_RANGE(0x100000, 0x1003ff) AM_RAM
171		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsoc_mcu_r,cupsoc_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)
	171	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsoc_mcu_r,cupsoc_mcu_w) AM_SHARE("cop_mcu_ram")
172	172	AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
173	173	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
174	174	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
r17825	r17826
187	187	static ADDRESS_MAP_START( cupsocs_mem, AS_PROGRAM, 16, legionna_state )
188	188	AM_RANGE(0x000000, 0x0fffff) AM_ROM
189	189	AM_RANGE(0x100000, 0x1003ff) AM_RAM
190		AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsocs_mcu_r,cupsocs_mcu_w) AM_BASE_LEGACY(&cop_mcu_ram)
	190	AM_RANGE(0x100400, 0x1007ff) AM_READWRITE_LEGACY(cupsocs_mcu_r,cupsocs_mcu_w) AM_SHARE("cop_mcu_ram")
191	191	AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
192	192	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
193	193	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")
r17825	r17826
206	206	static ADDRESS_MAP_START( cupsocbl_mem, AS_PROGRAM, 16, legionna_state )
207	207	AM_RANGE(0x000000, 0x0fffff) AM_ROM
208	208	//AM_RANGE(0x100000, 0x1003ff) AM_RAM
209		AM_RANGE(0x100000, 0x1007ff) AM_READWRITE_LEGACY(copdxbl_0_r,copdxbl_0_w) AM_BASE_LEGACY(&cop_mcu_ram)
	209	AM_RANGE(0x100000, 0x1007ff) AM_READWRITE_LEGACY(copdxbl_0_r,copdxbl_0_w) AM_SHARE("cop_mcu_ram")
210	210	AM_RANGE(0x100800, 0x100fff) AM_RAM_WRITE(legionna_background_w) AM_SHARE("back_data")
211	211	AM_RANGE(0x101000, 0x1017ff) AM_RAM_WRITE(legionna_foreground_w) AM_SHARE("fore_data")
212	212	AM_RANGE(0x101800, 0x101fff) AM_RAM_WRITE(legionna_midground_w) AM_SHARE("mid_data")

trunk/src/mame/drivers/r2dx_v33.c

r17825	r17826
30	30	public:
31	31	r2dx_v33_state(const machine_config &mconfig, device_type type, const char *tag)
32	32	: driver_device(mconfig, type, tag) ,
33		m_spriteram(*this, "spriteram"){ }
	33	m_spriteram(*this, "spriteram"),
	34	m_bg_vram(*this, "bg_vram"),
	35	m_md_vram(*this, "md_vram"),
	36	m_fg_vram(*this, "fg_vram"),
	37	m_tx_vram(*this, "tx_vram")
	38	{ }
34	39
35	40	required_shared_ptr<UINT16> m_spriteram;
36	41	DECLARE_WRITE16_MEMBER(rdx_bg_vram_w);
r17825	r17826
55	60	TILE_GET_INFO_MEMBER(get_md_tile_info);
56	61	TILE_GET_INFO_MEMBER(get_fg_tile_info);
57	62	TILE_GET_INFO_MEMBER(get_tx_tile_info);
	63
	64	required_shared_ptr<UINT16> m_bg_vram;
	65	required_shared_ptr<UINT16> m_md_vram;
	66	required_shared_ptr<UINT16> m_fg_vram;
	67	required_shared_ptr<UINT16> m_tx_vram;
	68	tilemap_t *m_bg_tilemap;
	69	tilemap_t *m_md_tilemap;
	70	tilemap_t *m_fg_tilemap;
	71	tilemap_t *m_tx_tilemap;
58	72	};
59	73
60	74
61		static UINT16 *seibu_crtc_regs;
62		static UINT16 *bg_vram,*md_vram,*fg_vram,*tx_vram;
63		static tilemap_t *bg_tilemap,*md_tilemap,*fg_tilemap,*tx_tilemap;
64
65	75	TILE_GET_INFO_MEMBER(r2dx_v33_state::get_bg_tile_info)
66	76	{
67		int tile = bg_vram[tile_index];
	77	int tile = m_bg_vram[tile_index];
68	78	int color = (tile>>12)&0xf;
69	79
70	80	tile &= 0xfff;
r17825	r17826
74	84
75	85	TILE_GET_INFO_MEMBER(r2dx_v33_state::get_md_tile_info)
76	86	{
77		int tile = md_vram[tile_index];
	87	int tile = m_md_vram[tile_index];
78	88	int color = (tile>>12)&0xf;
79	89
80	90	tile &= 0xfff;
r17825	r17826
84	94
85	95	TILE_GET_INFO_MEMBER(r2dx_v33_state::get_fg_tile_info)
86	96	{
87		int tile = fg_vram[tile_index];
	97	int tile = m_fg_vram[tile_index];
88	98	int color = (tile>>12)&0xf;
89	99
90	100	tile &= 0xfff;
r17825	r17826
94	104
95	105	TILE_GET_INFO_MEMBER(r2dx_v33_state::get_tx_tile_info)
96	106	{
97		int tile = tx_vram[tile_index];
	107	int tile = m_tx_vram[tile_index];
98	108	int color = (tile>>12)&0xf;
99	109
100	110	tile &= 0xfff;
r17825	r17826
192	202	static VIDEO_START( rdx_v33 )
193	203	{
194	204	r2dx_v33_state *state = machine.driver_data<r2dx_v33_state>();
195		bg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_bg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
196		md_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_md_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
197		fg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_fg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
198		tx_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_tx_tile_info),state), TILEMAP_SCAN_ROWS,8, 8, 64,32);
	205	state->m_bg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_bg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
	206	state->m_md_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_md_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
	207	state->m_fg_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_fg_tile_info),state), TILEMAP_SCAN_ROWS,16,16,32,32);
	208	state->m_tx_tilemap = &machine.tilemap().create(tilemap_get_info_delegate(FUNC(r2dx_v33_state::get_tx_tile_info),state), TILEMAP_SCAN_ROWS,8, 8, 64,32);
199	209
200		bg_tilemap->set_transparent_pen(15);
201		md_tilemap->set_transparent_pen(15);
202		fg_tilemap->set_transparent_pen(15);
203		tx_tilemap->set_transparent_pen(15);
	210	state->m_bg_tilemap->set_transparent_pen(15);
	211	state->m_md_tilemap->set_transparent_pen(15);
	212	state->m_fg_tilemap->set_transparent_pen(15);
	213	state->m_tx_tilemap->set_transparent_pen(15);
204	214	}
205	215
206	216	static SCREEN_UPDATE_IND16( rdx_v33 )
207	217	{
	218	r2dx_v33_state *state = screen.machine().driver_data<r2dx_v33_state>();
208	219	bitmap.fill(get_black_pen(screen.machine()), cliprect);
209	220
210		bg_tilemap->draw(bitmap, cliprect, 0, 0);
211		md_tilemap->draw(bitmap, cliprect, 0, 0);
212		fg_tilemap->draw(bitmap, cliprect, 0, 0);
	221	state->m_bg_tilemap->draw(bitmap, cliprect, 0, 0);
	222	state->m_md_tilemap->draw(bitmap, cliprect, 0, 0);
	223	state->m_fg_tilemap->draw(bitmap, cliprect, 0, 0);
213	224
214	225	draw_sprites(screen.machine(),bitmap,cliprect,0);
215	226
216		tx_tilemap->draw(bitmap, cliprect, 0, 0);
	227	state->m_tx_tilemap->draw(bitmap, cliprect, 0, 0);
217	228
218	229	/* debug DMA processing */
219	230	if(0)
r17825	r17826
247	258	}
248	259
249	260	popmessage("%08x 1",src_addr);
250		bg_tilemap->mark_all_dirty();
	261	state->m_bg_tilemap->mark_all_dirty();
251	262	frame = 0;
252	263	src_addr+=0x800;
253	264	}
r17825	r17826
312	323
313	324	WRITE16_MEMBER(r2dx_v33_state::rdx_bg_vram_w)
314	325	{
315		COMBINE_DATA(&bg_vram[offset]);
316		bg_tilemap->mark_tile_dirty(offset);
	326	COMBINE_DATA(&m_bg_vram[offset]);
	327	m_bg_tilemap->mark_tile_dirty(offset);
317	328	}
318	329
319	330	WRITE16_MEMBER(r2dx_v33_state::rdx_md_vram_w)
320	331	{
321		COMBINE_DATA(&md_vram[offset]);
322		md_tilemap->mark_tile_dirty(offset);
	332	COMBINE_DATA(&m_md_vram[offset]);
	333	m_md_tilemap->mark_tile_dirty(offset);
323	334	}
324	335
325	336	WRITE16_MEMBER(r2dx_v33_state::rdx_fg_vram_w)
326	337	{
327		COMBINE_DATA(&fg_vram[offset]);
328		fg_tilemap->mark_tile_dirty(offset);
	338	COMBINE_DATA(&m_fg_vram[offset]);
	339	m_fg_tilemap->mark_tile_dirty(offset);
329	340	}
330	341
331	342	WRITE16_MEMBER(r2dx_v33_state::rdx_tx_vram_w)
332	343	{
333		COMBINE_DATA(&tx_vram[offset]);
334		tx_tilemap->mark_tile_dirty(offset);
	344	COMBINE_DATA(&m_tx_vram[offset]);
	345	m_tx_tilemap->mark_tile_dirty(offset);
335	346	}
336	347
337	348	READ16_MEMBER(r2dx_v33_state::rdx_v33_unknown_r)
r17825	r17826
385	396	AM_RANGE(0x00434, 0x00435) AM_READ(rdx_v33_unknown_r)
386	397	AM_RANGE(0x00436, 0x00437) AM_READ(rdx_v33_unknown_r)
387	398
388		AM_RANGE(0x00600, 0x0064f) AM_RAM AM_BASE_LEGACY(&seibu_crtc_regs)
	399	AM_RANGE(0x00600, 0x0064f) AM_RAM AM_SHARE("crtc_regs")
389	400	AM_RANGE(0x00650, 0x0068f) AM_RAM //???
390	401
391	402	AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // synch for the MCU?
r17825	r17826
413	424
414	425	AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_SHARE("spriteram")
415	426	AM_RANGE(0x0c800, 0x0cfff) AM_RAM
416		AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram)
417		AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram)
418		AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram)
419		AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram)
	427	AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_SHARE("bg_vram")
	428	AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_SHARE("md_vram")
	429	AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_SHARE("fg_vram")
	430	AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_SHARE("tx_vram")
420	431	AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */
421	432	AM_RANGE(0x10000, 0x1efff) AM_RAM
422	433	AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
r17825	r17826
462	473	AM_RANGE(0x00400, 0x00407) AM_WRITE(mcu_table_w)
463	474	AM_RANGE(0x00420, 0x00427) AM_WRITE(mcu_table2_w)
464	475
465		AM_RANGE(0x00600, 0x0064f) AM_RAM AM_BASE_LEGACY(&seibu_crtc_regs)
	476	AM_RANGE(0x00600, 0x0064f) AM_RAM AM_SHARE("crtc_regs")
466	477
467	478	AM_RANGE(0x0068e, 0x0068f) AM_WRITENOP // synch for the MCU?
468	479	AM_RANGE(0x006b0, 0x006b1) AM_WRITE(mcu_prog_w)
r17825	r17826
486	497
487	498	AM_RANGE(0x0c000, 0x0c7ff) AM_RAM AM_SHARE("spriteram")
488	499	AM_RANGE(0x0c800, 0x0cfff) AM_RAM
489		AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_BASE_LEGACY(&bg_vram)
490		AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_BASE_LEGACY(&md_vram)
491		AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_BASE_LEGACY(&fg_vram)
492		AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_BASE_LEGACY(&tx_vram)
	500	AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE(rdx_bg_vram_w) AM_SHARE("bg_vram")
	501	AM_RANGE(0x0d800, 0x0dfff) AM_RAM_WRITE(rdx_md_vram_w) AM_SHARE("md_vram")
	502	AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE(rdx_fg_vram_w) AM_SHARE("fg_vram")
	503	AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(rdx_tx_vram_w) AM_SHARE("tx_vram")
493	504	AM_RANGE(0x0f800, 0x0ffff) AM_RAM /* Stack area */
494	505	AM_RANGE(0x10000, 0x1efff) AM_RAM
495	506	AM_RANGE(0x1f000, 0x1ffff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")

trunk/src/mame/drivers/mystwarr.c

r17825	r17826
471	471	AM_RANGE(0x440000, 0x443fff) AM_READ_LEGACY(K056832_mw_rom_word_r)
472	472	AM_RANGE(0x450000, 0x45000f) AM_READ_LEGACY(K055673_rom_word_r)
473	473	AM_RANGE(0x450010, 0x45001f) AM_WRITE_LEGACY(K053247_reg_word_w)
474		AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_BASE_LEGACY(&K053936_0_ctrl)
475		AM_RANGE(0x470000, 0x470fff) AM_RAM AM_BASE_LEGACY(&K053936_0_linectrl)
	474	AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_SHARE("k053936_0_ctrl")
	475	AM_RANGE(0x470000, 0x470fff) AM_RAM AM_SHARE("k053936_0_line")
476	476	AM_RANGE(0x480000, 0x48003f) AM_WRITE_LEGACY(K056832_word_w)      // VACSET
477	477	AM_RANGE(0x482000, 0x482007) AM_WRITE_LEGACY(K056832_b_word_w)   // VSCCS
478	478	AM_RANGE(0x484000, 0x484003) AM_WRITE(ddd_053936_clip_w)
r17825	r17826
518	518	AM_RANGE(0x440000, 0x441fff) AM_READ_LEGACY(K056832_mw_rom_word_r)
519	519	AM_RANGE(0x450000, 0x45000f) AM_READ_LEGACY(K055673_rom_word_r)
520	520	AM_RANGE(0x450010, 0x45001f) AM_WRITE_LEGACY(K053247_reg_word_w)
521		AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_BASE_LEGACY(&K053936_0_ctrl)
522		AM_RANGE(0x470000, 0x470fff) AM_RAM AM_BASE_LEGACY(&K053936_0_linectrl)
	521	AM_RANGE(0x460000, 0x46001f) AM_WRITEONLY AM_SHARE("k053936_0_ctrl")
	522	AM_RANGE(0x470000, 0x470fff) AM_RAM AM_SHARE("k053936_0_line")
523	523	AM_RANGE(0x480000, 0x48003f) AM_WRITE_LEGACY(K056832_word_w)         // VACSET
524	524	AM_RANGE(0x482000, 0x482007) AM_WRITE_LEGACY(K056832_b_word_w)         // VSCCS
525	525	AM_RANGE(0x484000, 0x484003) AM_WRITE(ddd_053936_clip_w)

trunk/src/mame/drivers/konamigx.c

r17825	r17826
1190	1190	AM_RANGE(0xdda000, 0xddafff) AM_WRITE_PORT("ADC-WRPORT")
1191	1191	AM_RANGE(0xddc000, 0xddcfff) AM_READ_PORT("ADC-RDPORT")
1192	1192	AM_RANGE(0xdde000, 0xdde003) AM_WRITE(type1_cablamps_w)
1193		AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_ctrl)
	1193	AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
1194	1194	AM_RANGE(0xe20000, 0xe2000f) AM_WRITENOP
1195	1195	AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
1196		AM_RANGE(0xe80000, 0xe81fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl)   // chips 21L+19L / S
	1196	AM_RANGE(0xe80000, 0xe81fff) AM_RAM AM_SHARE("k053936_0_line")   // chips 21L+19L / S
1197	1197	AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_SHARE("psacram")  // chips 20J+23J+18J / S
1198	1198	AM_RANGE(0xf00000, 0xf3ffff) AM_READ(type1_roz_r1)   // ROM readback
1199	1199	AM_RANGE(0xf40000, 0xf7ffff) AM_READ(type1_roz_r2)   // ROM readback
r17825	r17826
1211	1211	static ADDRESS_MAP_START( gx_type3_map, AS_PROGRAM, 32, konamigx_state )
1212	1212	AM_RANGE(0xd90000, 0xd97fff) AM_RAM
1213	1213	//AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w)
1214		AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_ctrl)
	1214	AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
1215	1215	//AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
1216	1216	AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE_LEGACY(&konamigx_type3_psac2_bank)
1217		AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl)
	1217	AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_SHARE("k053936_0_line")
1218	1218	AM_RANGE(0xe80000, 0xe83fff) AM_RAM AM_SHARE("paletteram")   // main monitor palette
1219	1219	AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_SHARE("subpaletteram")
1220	1220	AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r)
r17825	r17826
1225	1225	static ADDRESS_MAP_START( gx_type4_map, AS_PROGRAM, 32, konamigx_state )
1226	1226	AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w)
1227	1227	AM_RANGE(0xd90000, 0xd97fff) AM_RAM
1228		AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_ctrl)
	1228	AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
1229	1229	AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
1230	1230	AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
1231		AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl)  // 29C & 29G (PSAC2 line control)
	1231	AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_SHARE("k053936_0_line")  // 29C & 29G (PSAC2 line control)
1232	1232	AM_RANGE(0xe80000, 0xe87fff) AM_RAM AM_SHARE("paletteram") // 11G/13G/15G (main screen palette RAM)
1233	1233	AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_SHARE("subpaletteram") // 5G/7G/9G (sub screen palette RAM)
1234	1234	AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r)      // type 4 polls this too

trunk/src/mess/drivers/ng_aes.c

r17825	r17826
1303	1303	AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
1304	1304	AM_RANGE(0x800000, 0x800fff) AM_READWRITE(memcard_r, memcard_w)
1305	1305	AM_RANGE(0xc00000, 0xc1ffff) AM_MIRROR(0x0e0000) AM_ROMBANK(NEOGEO_BANK_BIOS)
1306		AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram)
	1306	AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_SHARE("save_ram")
1307	1307	AM_RANGE(0xe00000, 0xffffff) AM_READ(neogeo_unmapped_r)
1308	1308	ADDRESS_MAP_END
1309	1309
r17825	r17826
1329	1329	AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
1330	1330	AM_RANGE(0x800000, 0x803fff) AM_READWRITE(neocd_memcard_r, neocd_memcard_w)
1331	1331	AM_RANGE(0xc00000, 0xcfffff) AM_ROMBANK(NEOGEO_BANK_BIOS)
1332		AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram)
	1332	AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_READ(neogeo_unmapped_r) //AM_RAM_WRITE(save_ram_w) AM_SHARE("save_ram")
1333	1333	AM_RANGE(0xe00000, 0xefffff) AM_READWRITE(neocd_transfer_r,neocd_transfer_w)
1334	1334	AM_RANGE(0xf00000, 0xfeffff) AM_READ(neogeo_unmapped_r)
1335	1335	AM_RANGE(0xff0000, 0xff01ff) AM_READWRITE(neocd_control_r, neocd_control_w) // CDROM / DMA

trunk/src/mess/drivers/mmodular.c

r17825	r17826
99	99	#include "machine/nvram.h"
100	100
101	101	//static UINT16 unknown2_data = 0;
102		static UINT16 *save_ram;
103		static UINT32 *save_ram32;
104
105	102	// Berlin Pro 68020
106	103	static UINT32 BPL32latch_data = 0;
107	104
r17825	r17826
1005	1002	rom[0x870] = 0x38;
1006	1003	}
1007	1004	}
1008
1009		machine.device<nvram_device>("nvram")->set_base(save_ram32, 0x8000);
1010
1011	1005	}
1012	1006
1013	1007
r17825	r17826
1046	1040	{
1047	1041
1048	1042	mboard_savestate_register(machine);
1049		machine.device<nvram_device>("nvram")->set_base(save_ram, 0x4000);
1050	1043
1051	1044	}
1052	1045
r17825	r17826
1148	1141
1149	1142	AM_RANGE( 0x40000000, 0x4007ffff )  AM_RAM      /* 512KB */
1150	1143	AM_RANGE( 0x80000000, 0x8003ffff )  AM_RAM      /* 256KB */
1151		AM_RANGE( 0xe8000000, 0xe8007fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
	1144	AM_RANGE( 0xe8000000, 0xe8007fff )  AM_RAM AM_SHARE("nvram")
1152	1145
1153	1146	ADDRESS_MAP_END
1154	1147
r17825	r17826
1161	1154	AM_RANGE( 0xc00000 , 0xc00003 )  AM_WRITE(write_LCD_data_32 )
1162	1155	AM_RANGE( 0xb00000 , 0xb00003 )  AM_WRITE(write_IOenables_32 )
1163	1156	AM_RANGE( 0x400000 , 0x4fffff )  AM_RAM      /* 1024KB */
1164		AM_RANGE( 0xd00000 , 0xd07fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
	1157	AM_RANGE( 0xd00000 , 0xd07fff )  AM_RAM AM_SHARE("nvram")
1165	1158
1166	1159	ADDRESS_MAP_END
1167	1160
r17825	r17826
1180	1173	AM_RANGE( 0x9800000c , 0x9800000f )  AM_READ(read_unknown3_32 )
1181	1174
1182	1175	AM_RANGE( 0x40000000, 0x400fffff )  AM_RAM      /* 1024KB */
1183		AM_RANGE( 0xa8000000, 0xa8007fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
	1176	AM_RANGE( 0xa8000000, 0xa8007fff )  AM_RAM AM_SHARE("nvram")
1184	1177
1185	1178	ADDRESS_MAP_END
1186	1179
r17825	r17826
1200	1193	AM_RANGE( 0x9800000c , 0x9800000f )  AM_READ(read_unknown3_32 )
1201	1194
1202	1195	AM_RANGE( 0x40000000, 0x400fffff )  AM_RAM
1203		AM_RANGE( 0xa8000000, 0xa8007fff )  AM_RAM AM_BASE_LEGACY(&save_ram32) AM_SHARE("nvram")
	1196	AM_RANGE( 0xa8000000, 0xa8007fff )  AM_RAM AM_SHARE("nvram")
1204	1197
1205	1198	ADDRESS_MAP_END
1206	1199
r17825	r17826
1228	1221	AM_RANGE( 0xe80006 , 0xe80007 )  AM_READ(read_unknown3 )
1229	1222
1230	1223	AM_RANGE( 0x400000, 0x47ffff )  AM_RAM      /* 512KB */
1231		AM_RANGE( 0x800000, 0x803fff )  AM_RAM AM_BASE_LEGACY(&save_ram) AM_SHARE("nvram")
	1224	AM_RANGE( 0x800000, 0x803fff )  AM_RAM AM_SHARE("nvram")
1232	1225
1233	1226	ADDRESS_MAP_END
1234	1227
r17825	r17826
1248	1241
1249	1242
1250	1243	AM_RANGE( 0x400000, 0x47ffff )  AM_RAM      /* 512KB */
1251		AM_RANGE( 0x800000, 0x803fff )  AM_RAM  AM_BASE_LEGACY(&save_ram) AM_SHARE("nvram")
	1244	AM_RANGE( 0x800000, 0x803fff )  AM_RAM  AM_SHARE("nvram")
1252	1245	ADDRESS_MAP_END
1253	1246
1254	1247

Previous

199869 Revisions

Next

---

© 1997-2024 The MAME Team