trunk/src/mame/video/sei_crtc.c
| r17819 | r17820 | |
| 60 | 60 | #include "includes/sei_crtc.h" |
| 61 | 61 | |
| 62 | 62 | static tilemap_t *sc0_tilemap,*sc2_tilemap,*sc1_tilemap,*sc3_tilemap_0,*sc3_tilemap_1; |
| 63 | | UINT16 *seibucrtc_sc0vram,*seibucrtc_sc1vram,*seibucrtc_sc2vram,*seibucrtc_sc3vram; |
| 64 | | UINT16 *seibucrtc_vregs; |
| 63 | static UINT16 *seibucrtc_sc0vram,*seibucrtc_sc1vram,*seibucrtc_sc2vram,*seibucrtc_sc3vram; |
| 64 | static UINT16 *seibucrtc_vregs; |
| 65 | 65 | UINT16 seibucrtc_sc0bank; |
| 66 | 66 | |
| 67 | 67 | /******************************* |
| r17819 | r17820 | |
| 255 | 255 | |
| 256 | 256 | VIDEO_START( seibu_crtc ) |
| 257 | 257 | { |
| 258 | seibucrtc_sc0vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc0vram")->ptr()); |
| 259 | seibucrtc_sc1vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc1vram")->ptr()); |
| 260 | seibucrtc_sc2vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc2vram")->ptr()); |
| 261 | seibucrtc_sc3vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc3vram")->ptr()); |
| 262 | seibucrtc_vregs = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_vregs")->ptr()); |
| 263 | |
| 258 | 264 | sc0_tilemap = tilemap_create(machine, seibucrtc_sc0_tile_info,TILEMAP_SCAN_ROWS,16,16,32,32); |
| 259 | 265 | sc2_tilemap = tilemap_create(machine, seibucrtc_sc2_tile_info,TILEMAP_SCAN_ROWS,16,16,32,32); |
| 260 | 266 | sc1_tilemap = tilemap_create(machine, seibucrtc_sc1_tile_info,TILEMAP_SCAN_ROWS,16,16,32,32); |
trunk/src/mame/video/konamigx.c
| r17819 | r17820 | |
| 1817 | 1817 | int tileno, colour, col, flip = 0; |
| 1818 | 1818 | if (tile_index&1) |
| 1819 | 1819 | { |
| 1820 | | tileno = gx_psacram[tile_index/2] & 0x00001fff; |
| 1821 | | col =(gx_psacram[tile_index/2] & 0x00002000)>>13; |
| 1822 | | if (gx_psacram[tile_index/2] & 0x00004000) flip |= TILE_FLIPX; |
| 1823 | | if (gx_psacram[tile_index/2] & 0x00008000) flip |= TILE_FLIPY; |
| 1820 | tileno = m_psacram[tile_index/2] & 0x00001fff; |
| 1821 | col =(m_psacram[tile_index/2] & 0x00002000)>>13; |
| 1822 | if (m_psacram[tile_index/2] & 0x00004000) flip |= TILE_FLIPX; |
| 1823 | if (m_psacram[tile_index/2] & 0x00008000) flip |= TILE_FLIPY; |
| 1824 | 1824 | |
| 1825 | 1825 | } |
| 1826 | 1826 | else |
| 1827 | 1827 | { |
| 1828 | | tileno = (gx_psacram[tile_index/2] & 0x1fff0000)>>16; |
| 1829 | | col = (gx_psacram[tile_index/2] & 0x20000000)>>29; |
| 1830 | | if (gx_psacram[tile_index/2] & 0x40000000) flip |= TILE_FLIPX; |
| 1831 | | if (gx_psacram[tile_index/2] & 0x80000000) flip |= TILE_FLIPY; |
| 1828 | tileno = (m_psacram[tile_index/2] & 0x1fff0000)>>16; |
| 1829 | col = (m_psacram[tile_index/2] & 0x20000000)>>29; |
| 1830 | if (m_psacram[tile_index/2] & 0x40000000) flip |= TILE_FLIPX; |
| 1831 | if (m_psacram[tile_index/2] & 0x80000000) flip |= TILE_FLIPY; |
| 1832 | 1832 | |
| 1833 | 1833 | } |
| 1834 | 1834 | |
| r17819 | r17820 | |
| 1913 | 1913 | flip=0; |
| 1914 | 1914 | colour = 0; |
| 1915 | 1915 | |
| 1916 | | tileno = (gx_psacram[tile_index*2] & 0x00003fff)>>0; |
| 1916 | tileno = (m_psacram[tile_index*2] & 0x00003fff)>>0; |
| 1917 | 1917 | |
| 1918 | 1918 | // scanrows |
| 1919 | | //flipx = (gx_psacram[tile_index*2+1] & 0x00800000)>>23; |
| 1920 | | //flipy = (gx_psacram[tile_index*2+1] & 0x00400000)>>22; |
| 1919 | //flipx = (m_psacram[tile_index*2+1] & 0x00800000)>>23; |
| 1920 | //flipy = (m_psacram[tile_index*2+1] & 0x00400000)>>22; |
| 1921 | 1921 | // scancols |
| 1922 | | flipy = (gx_psacram[tile_index*2+1] & 0x00800000)>>23; |
| 1923 | | flipx = (gx_psacram[tile_index*2+1] & 0x00400000)>>22; |
| 1922 | flipy = (m_psacram[tile_index*2+1] & 0x00800000)>>23; |
| 1923 | flipx = (m_psacram[tile_index*2+1] & 0x00400000)>>22; |
| 1924 | 1924 | |
| 1925 | 1925 | if (flipx) flip |= TILE_FLIPX; |
| 1926 | 1926 | if (flipy) flip |= TILE_FLIPY; |
| r17819 | r17820 | |
| 1935 | 1935 | flip=0; |
| 1936 | 1936 | |
| 1937 | 1937 | colour = 0; |
| 1938 | | tileno = (gx_psacram[tile_index*2+1] & 0x00003fff)>>0; |
| 1938 | tileno = (m_psacram[tile_index*2+1] & 0x00003fff)>>0; |
| 1939 | 1939 | |
| 1940 | 1940 | // scanrows |
| 1941 | | //flipx = (gx_psacram[tile_index*2+1] & 0x00800000)>>23; |
| 1942 | | //flipy = (gx_psacram[tile_index*2+1] & 0x00400000)>>22; |
| 1941 | //flipx = (m_psacram[tile_index*2+1] & 0x00800000)>>23; |
| 1942 | //flipy = (m_psacram[tile_index*2+1] & 0x00400000)>>22; |
| 1943 | 1943 | // scancols |
| 1944 | | flipy = (gx_psacram[tile_index*2+1] & 0x00200000)>>21; |
| 1945 | | flipx = (gx_psacram[tile_index*2+1] & 0x00100000)>>20; |
| 1944 | flipy = (m_psacram[tile_index*2+1] & 0x00200000)>>21; |
| 1945 | flipx = (m_psacram[tile_index*2+1] & 0x00100000)>>20; |
| 1946 | 1946 | |
| 1947 | 1947 | if (flipx) flip |= TILE_FLIPX; |
| 1948 | 1948 | if (flipy) flip |= TILE_FLIPY; |
| r17819 | r17820 | |
| 2547 | 2547 | |
| 2548 | 2548 | SCREEN_UPDATE_RGB32(konamigx_right) |
| 2549 | 2549 | { |
| 2550 | konamigx_state *state = screen.machine().driver_data<konamigx_state>(); |
| 2551 | |
| 2550 | 2552 | if (konamigx_current_frame==1) |
| 2551 | 2553 | { |
| 2552 | 2554 | copybitmap(bitmap, *dualscreen_right_tempbitmap, 0, 0, 0, 0, cliprect); |
| r17819 | r17820 | |
| 2560 | 2562 | { |
| 2561 | 2563 | for (offset=0;offset<0x4000/4;offset++) |
| 2562 | 2564 | { |
| 2563 | | UINT32 coldat = gx_subpaletteram32[offset]; |
| 2565 | UINT32 coldat = state->m_subpaletteram32[offset]; |
| 2564 | 2566 | |
| 2565 | 2567 | set_color_555(screen.machine(), offset*2, 0, 5, 10,coldat >> 16); |
| 2566 | 2568 | set_color_555(screen.machine(), offset*2+1, 0, 5, 10,coldat & 0xffff); |
| r17819 | r17820 | |
| 2572 | 2574 | { |
| 2573 | 2575 | int r,g,b; |
| 2574 | 2576 | |
| 2575 | | r = (gx_subpaletteram32[offset] >>16) & 0xff; |
| 2576 | | g = (gx_subpaletteram32[offset] >> 8) & 0xff; |
| 2577 | | b = (gx_subpaletteram32[offset] >> 0) & 0xff; |
| 2577 | r = (state->m_subpaletteram32[offset] >>16) & 0xff; |
| 2578 | g = (state->m_subpaletteram32[offset] >> 8) & 0xff; |
| 2579 | b = (state->m_subpaletteram32[offset] >> 0) & 0xff; |
| 2578 | 2580 | |
| 2579 | 2581 | palette_set_color(screen.machine(),offset,MAKE_RGB(r,g,b)); |
| 2580 | 2582 | } |
| r17819 | r17820 | |
| 2606 | 2608 | { |
| 2607 | 2609 | int r,g,b; |
| 2608 | 2610 | |
| 2609 | | COMBINE_DATA(&gx_subpaletteram32[offset]); |
| 2611 | COMBINE_DATA(&state->m_subpaletteram32[offset]); |
| 2610 | 2612 | |
| 2611 | | r = (gx_subpaletteram32[offset] >>16) & 0xff; |
| 2612 | | g = (gx_subpaletteram32[offset] >> 8) & 0xff; |
| 2613 | | b = (gx_subpaletteram32[offset] >> 0) & 0xff; |
| 2613 | r = (state->m_subpaletteram32[offset] >>16) & 0xff; |
| 2614 | g = (state->m_subpaletteram32[offset] >> 8) & 0xff; |
| 2615 | b = (state->m_subpaletteram32[offset] >> 0) & 0xff; |
| 2614 | 2616 | |
| 2615 | 2617 | offset += (0x8000/4); |
| 2616 | 2618 | |
| r17819 | r17820 | |
| 2640 | 2642 | WRITE32_MEMBER(konamigx_state::konamigx_555_palette2_w) |
| 2641 | 2643 | { |
| 2642 | 2644 | UINT32 coldat; |
| 2643 | | COMBINE_DATA(&gx_subpaletteram32[offset]); |
| 2644 | | coldat = gx_subpaletteram32[offset]; |
| 2645 | COMBINE_DATA(&state->m_subpaletteram32[offset]); |
| 2646 | coldat = state->m_subpaletteram32[offset]; |
| 2645 | 2647 | |
| 2646 | 2648 | offset += (0x4000/4); |
| 2647 | 2649 | |
| r17819 | r17820 | |
| 2666 | 2668 | // type 1 RAM-based PSAC tilemap |
| 2667 | 2669 | WRITE32_MEMBER(konamigx_state::konamigx_t1_psacmap_w) |
| 2668 | 2670 | { |
| 2669 | | COMBINE_DATA(&gx_psacram[offset]); |
| 2671 | COMBINE_DATA(&m_psacram[offset]); |
| 2670 | 2672 | gx_psac_tilemap->mark_tile_dirty(offset/2); |
| 2671 | 2673 | gx_psac_tilemap2->mark_tile_dirty(offset/2); |
| 2672 | 2674 | } |
| r17819 | r17820 | |
| 2674 | 2676 | // type 4 RAM-based PSAC tilemap |
| 2675 | 2677 | WRITE32_MEMBER(konamigx_state::konamigx_t4_psacmap_w) |
| 2676 | 2678 | { |
| 2677 | | COMBINE_DATA(&gx_psacram[offset]); |
| 2679 | COMBINE_DATA(&m_psacram[offset]); |
| 2678 | 2680 | |
| 2679 | 2681 | gx_psac_tilemap->mark_tile_dirty(offset*2); |
| 2680 | 2682 | gx_psac_tilemap->mark_tile_dirty((offset*2)+1); |
trunk/src/mame/includes/konamigx.h
| r17819 | r17820 | |
| 3 | 3 | public: |
| 4 | 4 | konamigx_state(const machine_config &mconfig, device_type type, const char *tag) |
| 5 | 5 | : driver_device(mconfig, type, tag), |
| 6 | | m_maincpu(*this,"maincpu") |
| 6 | m_maincpu(*this,"maincpu"), |
| 7 | m_workram(*this,"workram"), |
| 8 | m_psacram(*this,"psacram"), |
| 9 | m_subpaletteram32(*this,"subpaletteram") |
| 7 | 10 | { } |
| 8 | 11 | |
| 9 | 12 | required_device<cpu_device> m_maincpu; |
| 13 | required_shared_ptr<UINT32> m_workram; |
| 14 | optional_shared_ptr<UINT32> m_psacram; |
| 15 | optional_shared_ptr<UINT32> m_subpaletteram32; |
| 10 | 16 | DECLARE_WRITE32_MEMBER(esc_w); |
| 11 | 17 | DECLARE_WRITE32_MEMBER(eeprom_w); |
| 12 | 18 | DECLARE_WRITE32_MEMBER(control_w); |
| r17819 | r17820 | |
| 52 | 58 | }; |
| 53 | 59 | |
| 54 | 60 | |
| 55 | | /*----------- defined in drivers/konamigx.c -----------*/ |
| 56 | | |
| 57 | | extern UINT32 *gx_psacram, *gx_subpaletteram32; |
| 58 | | |
| 59 | | |
| 60 | 61 | /*----------- defined in video/konamigx.c -----------*/ |
| 61 | 62 | |
| 62 | 63 | // 2nd-Tier GX/MW Hardware Functions |
trunk/src/mame/drivers/deco32.c
| r17819 | r17820 | |
| 786 | 786 | AM_RANGE(0x16c000, 0x16c01f) AM_READNOP |
| 787 | 787 | AM_RANGE(0x17c000, 0x17c03f) AM_READNOP |
| 788 | 788 | |
| 789 | | AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_BASE_LEGACY(&deco32_prot_ram) |
| 789 | AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_SHARE("prot32ram") |
| 790 | 790 | AM_RANGE(0x208800, 0x208803) AM_WRITENOP /* ? */ |
| 791 | 791 | ADDRESS_MAP_END |
| 792 | 792 | |
| r17819 | r17820 | |
| 816 | 816 | AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_rowscroll_w) AM_SHARE("pf4_rowscroll32") |
| 817 | 817 | AM_RANGE(0x1e0000, 0x1e001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w) |
| 818 | 818 | |
| 819 | | AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_BASE_LEGACY(&deco32_prot_ram) |
| 819 | AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_SHARE("prot32ram") |
| 820 | 820 | ADDRESS_MAP_END |
| 821 | 821 | |
| 822 | 822 | // the video drawing (especially sprite) code on this is too slow to cope with proper partial updates |
| r17819 | r17820 | |
| 956 | 956 | AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_rowscroll_w) AM_SHARE("pf4_rowscroll32") |
| 957 | 957 | AM_RANGE(0x1e0000, 0x1e001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w) |
| 958 | 958 | |
| 959 | | AM_RANGE(0x200000, 0x200fff) AM_READWRITE(tattass_prot_r, tattass_prot_w) AM_BASE_LEGACY(&deco32_prot_ram) |
| 959 | AM_RANGE(0x200000, 0x200fff) AM_READWRITE(tattass_prot_r, tattass_prot_w) AM_SHARE("prot32ram") |
| 960 | 960 | ADDRESS_MAP_END |
| 961 | 961 | |
| 962 | 962 | static ADDRESS_MAP_START( nslasher_map, AS_PROGRAM, 32, deco32_state ) |
| r17819 | r17820 | |
| 997 | 997 | AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_rowscroll_w) AM_SHARE("pf4_rowscroll32") |
| 998 | 998 | AM_RANGE(0x1e0000, 0x1e001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w) |
| 999 | 999 | |
| 1000 | | AM_RANGE(0x200000, 0x200fff) AM_READWRITE(nslasher_prot_r, nslasher_prot_w) AM_BASE_LEGACY(&deco32_prot_ram) |
| 1000 | AM_RANGE(0x200000, 0x200fff) AM_READWRITE(nslasher_prot_r, nslasher_prot_w) AM_SHARE("prot32ram") |
| 1001 | 1001 | ADDRESS_MAP_END |
| 1002 | 1002 | |
| 1003 | 1003 | /******************************************************************************/ |
| r17819 | r17820 | |
| 1669 | 1669 | { |
| 1670 | 1670 | deco32_state *state = machine.driver_data<deco32_state>(); |
| 1671 | 1671 | state->m_raster_irq_timer = machine.device<timer_device>("int_timer"); |
| 1672 | decoprot_reset(machine); |
| 1672 | 1673 | } |
| 1673 | 1674 | |
| 1674 | 1675 | static INTERRUPT_GEN( deco32_vbl_interrupt ) |
trunk/src/mame/drivers/cninja.c
| r17819 | r17820 | |
| 181 | 181 | |
| 182 | 182 | AM_RANGE(0x1a4000, 0x1a47ff) AM_RAM AM_SHARE("spriteram") /* Sprites */ |
| 183 | 183 | AM_RANGE(0x1b4000, 0x1b4001) AM_DEVWRITE("spriteram", buffered_spriteram16_device, write) /* DMA flag */ |
| 184 | | AM_RANGE(0x1bc000, 0x1bc0ff) AM_WRITE_LEGACY(deco16_104_cninja_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection writes */ |
| 185 | | AM_RANGE(0x1bc000, 0x1bcfff) AM_READ_LEGACY(deco16_104_cninja_prot_r) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 184 | AM_RANGE(0x1bc000, 0x1bc0ff) AM_WRITE_LEGACY(deco16_104_cninja_prot_w) AM_SHARE("prot16ram") /* Protection writes */ |
| 185 | AM_RANGE(0x1bc000, 0x1bcfff) AM_READ_LEGACY(deco16_104_cninja_prot_r) AM_SHARE("prot16ram") /* Protection device */ |
| 186 | 186 | |
| 187 | 187 | AM_RANGE(0x308000, 0x308fff) AM_WRITENOP /* Bootleg only */ |
| 188 | 188 | ADDRESS_MAP_END |
| r17819 | r17820 | |
| 234 | 234 | |
| 235 | 235 | AM_RANGE(0x188000, 0x189fff) AM_RAM_DEVWRITE_LEGACY("deco_common", decocomn_nonbuffered_palette_w) AM_SHARE("paletteram") |
| 236 | 236 | AM_RANGE(0x194000, 0x197fff) AM_RAM AM_SHARE("ram") /* Main ram */ |
| 237 | | AM_RANGE(0x198000, 0x1987ff) AM_READWRITE_LEGACY(deco16_60_prot_r, deco16_60_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 237 | AM_RANGE(0x198000, 0x1987ff) AM_READWRITE_LEGACY(deco16_60_prot_r, deco16_60_prot_w) AM_SHARE("prot16ram") /* Protection device */ |
| 238 | 238 | AM_RANGE(0x199550, 0x199551) AM_WRITENOP /* Looks like a bug in game code, a protection write is referenced off a5 instead of a6 and ends up here */ |
| 239 | 239 | AM_RANGE(0x199750, 0x199751) AM_WRITENOP /* Looks like a bug in game code, a protection write is referenced off a5 instead of a6 and ends up here */ |
| 240 | 240 | |
| r17819 | r17820 | |
| 280 | 280 | AM_RANGE(0x160000, 0x161fff) AM_RAM_DEVWRITE_LEGACY("deco_common", decocomn_nonbuffered_palette_w) AM_SHARE("paletteram") |
| 281 | 281 | AM_RANGE(0x180000, 0x180001) AM_DEVWRITE_LEGACY("deco_common", decocomn_priority_w) |
| 282 | 282 | AM_RANGE(0x180002, 0x180003) AM_WRITENOP /* VBL irq ack */ |
| 283 | | AM_RANGE(0x1a0000, 0x1a07ff) AM_READWRITE_LEGACY(deco16_66_prot_r, deco16_66_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 283 | AM_RANGE(0x1a0000, 0x1a07ff) AM_READWRITE_LEGACY(deco16_66_prot_r, deco16_66_prot_w) AM_SHARE("prot16ram") /* Protection device */ |
| 284 | 284 | AM_RANGE(0x1c0000, 0x1c0001) AM_DEVWRITE("spriteram", buffered_spriteram16_device, write) AM_DEVREAD_LEGACY("deco_common", decocomn_71_r) |
| 285 | 285 | AM_RANGE(0x1e0000, 0x1e0001) AM_DEVWRITE("spriteram2", buffered_spriteram16_device, write) |
| 286 | 286 | |
| r17819 | r17820 | |
| 875 | 875 | |
| 876 | 876 | state->save_item(NAME(state->m_scanline)); |
| 877 | 877 | state->save_item(NAME(state->m_irq_mask)); |
| 878 | |
| 879 | decoprot_reset(machine); |
| 878 | 880 | } |
| 879 | 881 | |
| 880 | 882 | static MACHINE_RESET( cninja ) |
trunk/src/mame/drivers/boogwing.c
| r17819 | r17820 | |
| 105 | 105 | AM_RANGE(0x24e6c0, 0x24e6c1) AM_READ_PORT("DSW") |
| 106 | 106 | AM_RANGE(0x24e138, 0x24e139) AM_READ_PORT("SYSTEM") |
| 107 | 107 | AM_RANGE(0x24e344, 0x24e345) AM_READ_PORT("INPUTS") |
| 108 | | AM_RANGE(0x24e000, 0x24e7ff) AM_WRITE_LEGACY(deco16_104_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) |
| 108 | AM_RANGE(0x24e000, 0x24e7ff) AM_WRITE_LEGACY(deco16_104_prot_w) AM_SHARE("prot16ram") |
| 109 | 109 | |
| 110 | 110 | AM_RANGE(0x260000, 0x26000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w) |
| 111 | 111 | AM_RANGE(0x264000, 0x265fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf1_data_r, deco16ic_pf1_data_w) |
| r17819 | r17820 | |
| 581 | 581 | deco56_remap_gfx(machine(), "gfx6"); |
| 582 | 582 | deco102_decrypt_cpu(machine(), "maincpu", 0x42ba, 0x00, 0x18); |
| 583 | 583 | memcpy(dst, src, 0x100000); |
| 584 | |
| 585 | decoprot_reset(machine()); |
| 584 | 586 | } |
| 585 | 587 | |
| 586 | 588 | GAME( 1992, boogwing, 0, boogwing, boogwing, boogwing_state, boogwing, ROT0, "Data East Corporation", "Boogie Wings (Euro v1.5, 92.12.07)", GAME_SUPPORTS_SAVE ) |
trunk/src/mame/drivers/sengokmj.c
| r17819 | r17820 | |
| 117 | 117 | static ADDRESS_MAP_START( sengokmj_map, AS_PROGRAM, 16, sengokmj_state ) |
| 118 | 118 | AM_RANGE(0x00000, 0x07fff) AM_RAM |
| 119 | 119 | AM_RANGE(0x08000, 0x09fff) AM_RAM AM_SHARE("nvram") |
| 120 | | AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_BASE_LEGACY(&seibucrtc_sc0vram) |
| 121 | | AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_BASE_LEGACY(&seibucrtc_sc1vram) |
| 122 | | AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_BASE_LEGACY(&seibucrtc_sc2vram) |
| 123 | | AM_RANGE(0x0d800, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_BASE_LEGACY(&seibucrtc_sc3vram) |
| 120 | AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_SHARE("crtc_sc0vram") |
| 121 | AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_SHARE("crtc_sc1vram") |
| 122 | AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_SHARE("crtc_sc2vram") |
| 123 | AM_RANGE(0x0d800, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_SHARE("crtc_sc3vram") |
| 124 | 124 | AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram") |
| 125 | 125 | AM_RANGE(0x0f800, 0x0ffff) AM_RAM AM_SHARE("spriteram") |
| 126 | 126 | AM_RANGE(0xc0000, 0xfffff) AM_ROM |
| r17819 | r17820 | |
| 129 | 129 | static ADDRESS_MAP_START( sengokmj_io_map, AS_IO, 16, sengokmj_state ) |
| 130 | 130 | AM_RANGE(0x4000, 0x400f) AM_READWRITE_LEGACY(seibu_main_word_r, seibu_main_word_w) |
| 131 | 131 | /*Areas from 8000-804f are for the custom Seibu CRTC.*/ |
| 132 | | AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_BASE_LEGACY(&seibucrtc_vregs) |
| 132 | AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_SHARE("crtc_vregs") |
| 133 | 133 | |
| 134 | 134 | // AM_RANGE(0x8080, 0x8081) CRTC extra register? |
| 135 | 135 | // AM_RANGE(0x80c0, 0x80c1) CRTC extra register? |
trunk/src/mame/drivers/goodejan.c
| r17819 | r17820 | |
| 105 | 105 | |
| 106 | 106 | static ADDRESS_MAP_START( goodejan_map, AS_PROGRAM, 16, goodejan_state ) |
| 107 | 107 | AM_RANGE(0x00000, 0x0afff) AM_RAM |
| 108 | | AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_BASE_LEGACY(&seibucrtc_sc0vram) |
| 109 | | AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_BASE_LEGACY(&seibucrtc_sc3vram) |
| 108 | AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_SHARE("crtc_sc0vram") |
| 109 | AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_SHARE("crtc_sc3vram") |
| 110 | 110 | AM_RANGE(0x0d000, 0x0dfff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_word_w) AM_SHARE("paletteram") |
| 111 | 111 | /*Guess: these two aren't used/initialized at all.*/ |
| 112 | | AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_BASE_LEGACY(&seibucrtc_sc1vram) |
| 113 | | AM_RANGE(0x0e800, 0x0efff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_BASE_LEGACY(&seibucrtc_sc2vram) |
| 112 | AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_SHARE("crtc_sc1vram") |
| 113 | AM_RANGE(0x0e800, 0x0efff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_SHARE("crtc_sc2vram") |
| 114 | 114 | AM_RANGE(0x0f800, 0x0ffff) AM_RAM AM_SHARE("spriteram") |
| 115 | 115 | AM_RANGE(0xc0000, 0xfffff) AM_ROM |
| 116 | 116 | ADDRESS_MAP_END |
| r17819 | r17820 | |
| 128 | 128 | ADDRESS_MAP_END |
| 129 | 129 | |
| 130 | 130 | static ADDRESS_MAP_START( totmejan_io_map, AS_IO, 16, goodejan_state ) |
| 131 | | AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_BASE_LEGACY(&seibucrtc_vregs) |
| 131 | AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_SHARE("crtc_vregs") |
| 132 | 132 | AM_IMPORT_FROM(common_io_map) |
| 133 | 133 | ADDRESS_MAP_END |
| 134 | 134 | |
| 135 | 135 | static ADDRESS_MAP_START( goodejan_io_map, AS_IO, 16, goodejan_state ) |
| 136 | | AM_RANGE(0x8040, 0x807f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_BASE_LEGACY(&seibucrtc_vregs) |
| 136 | AM_RANGE(0x8040, 0x807f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_SHARE("crtc_vregs") |
| 137 | 137 | AM_IMPORT_FROM(common_io_map) |
| 138 | 138 | ADDRESS_MAP_END |
| 139 | 139 | |
trunk/src/mame/drivers/rohga.c
| r17819 | r17820 | |
| 138 | 138 | AM_RANGE(0x200000, 0x20000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w) |
| 139 | 139 | AM_RANGE(0x240000, 0x24000f) AM_DEVWRITE_LEGACY("tilegen2", deco16ic_pf_control_w) |
| 140 | 140 | |
| 141 | | AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 141 | AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_SHARE("prot16ram") /* Protection device */ |
| 142 | 142 | |
| 143 | 143 | AM_RANGE(0x2c0000, 0x2c0001) AM_READ_PORT("DSW3") |
| 144 | 144 | |
| r17819 | r17820 | |
| 191 | 191 | AM_RANGE(0x380000, 0x381fff) AM_RAM_DEVWRITE_LEGACY("deco_common", decocomn_buffered_palette_w) AM_SHARE("paletteram") |
| 192 | 192 | AM_RANGE(0x390008, 0x390009) AM_DEVWRITE_LEGACY("deco_common", decocomn_palette_dma_w) |
| 193 | 193 | |
| 194 | | AM_RANGE(0xfe4000, 0xfe47ff) AM_READWRITE_LEGACY(deco16_104_prot_r,deco16_104_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 194 | AM_RANGE(0xfe4000, 0xfe47ff) AM_READWRITE_LEGACY(deco16_104_prot_r,deco16_104_prot_w) AM_SHARE("prot16ram") /* Protection device */ |
| 195 | 195 | AM_RANGE(0xfdc000, 0xffffff) AM_RAM |
| 196 | 196 | ADDRESS_MAP_END |
| 197 | 197 | |
| r17819 | r17820 | |
| 224 | 224 | AM_RANGE(0x390008, 0x390009) AM_DEVWRITE_LEGACY("deco_common", decocomn_palette_dma_w) |
| 225 | 225 | |
| 226 | 226 | AM_RANGE(0xfec000, 0xff3fff) AM_RAM |
| 227 | | AM_RANGE(0xff4000, 0xff47ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_146_nitroball_prot_r,deco16_146_nitroball_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 227 | AM_RANGE(0xff4000, 0xff47ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_146_nitroball_prot_r,deco16_146_nitroball_prot_w) AM_SHARE("prot16ram") /* Protection device */ |
| 228 | 228 | AM_RANGE(0xff8000, 0xffffff) AM_RAM |
| 229 | 229 | ADDRESS_MAP_END |
| 230 | 230 | |
| r17819 | r17820 | |
| 232 | 232 | AM_RANGE(0x000000, 0x0fffff) AM_ROM |
| 233 | 233 | AM_RANGE(0x200000, 0x20000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w) |
| 234 | 234 | AM_RANGE(0x240000, 0x24000f) AM_DEVWRITE_LEGACY("tilegen2", deco16ic_pf_control_w) |
| 235 | | AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */ |
| 235 | AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_SHARE("prot16ram") /* Protection device */ |
| 236 | 236 | |
| 237 | 237 | AM_RANGE(0x2c0000, 0x2c0001) AM_READ_PORT("DSW3") |
| 238 | 238 | AM_RANGE(0x300000, 0x300001) AM_READ_PORT("DSW3") AM_WRITE(rohga_buffer_spriteram16_w) /* write 1 for sprite dma */ |
| r17819 | r17820 | |
| 1544 | 1544 | deco74_decrypt_gfx(machine(), "gfx1"); |
| 1545 | 1545 | deco74_decrypt_gfx(machine(), "gfx2"); |
| 1546 | 1546 | deco74_decrypt_gfx(machine(), "gfx3"); |
| 1547 | |
| 1548 | decoprot_reset(machine()); |
| 1547 | 1549 | } |
| 1548 | 1550 | |
| 1549 | 1551 | DRIVER_INIT_MEMBER(rohga_state,nitrobal) |
trunk/src/mame/drivers/aristmk5.c
| r17819 | r17820 | |
| 297 | 297 | /* U.S games have no dram emulator enabled */ |
| 298 | 298 | static ADDRESS_MAP_START( aristmk5_map, AS_PROGRAM, 32, aristmk5_state ) |
| 299 | 299 | AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w) |
| 300 | | AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */ |
| 300 | AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */ |
| 301 | 301 | |
| 302 | 302 | /* MK-5 overrides */ |
| 303 | 303 | AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write |
| r17819 | r17820 | |
| 323 | 323 | /* with dram emulator enabled */ |
| 324 | 324 | static ADDRESS_MAP_START( aristmk5_drame_map, AS_PROGRAM, 32, aristmk5_state ) |
| 325 | 325 | AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(aristmk5_drame_memc_logical_r, archimedes_memc_logical_w) |
| 326 | | AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */ |
| 326 | AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */ |
| 327 | 327 | |
| 328 | 328 | /* MK-5 overrides */ |
| 329 | 329 | AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write |
trunk/src/mame/drivers/konamigx.c
| r17819 | r17820 | |
| 110 | 110 | static MACHINE_START(konamigx); |
| 111 | 111 | static MACHINE_RESET(konamigx); |
| 112 | 112 | |
| 113 | | UINT32 *gx_psacram, *gx_subpaletteram32; |
| 114 | | |
| 115 | 113 | static int konamigx_cfgport; |
| 116 | 114 | |
| 117 | | static UINT32 *gx_workram; /* workram pointer for ESC protection fun */ |
| 118 | | static UINT16 *gx_sndram; |
| 119 | 115 | static int gx_rdport1_3, gx_syncen; |
| 120 | 116 | |
| 121 | 117 | static emu_timer *dmadelay_timer; |
| r17819 | r17820 | |
| 323 | 319 | |
| 324 | 320 | static void tkmmpzdm_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4) |
| 325 | 321 | { |
| 326 | | konamigx_esc_alert(gx_workram, 0x0142, 0x100, 0); |
| 322 | konamigx_esc_alert(space->machine().driver_data<konamigx_state>()->m_workram, 0x0142, 0x100, 0); |
| 327 | 323 | } |
| 328 | 324 | |
| 329 | 325 | static void dragoonj_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4) |
| 330 | 326 | { |
| 331 | | konamigx_esc_alert(gx_workram, 0x5c00, 0x100, 0); |
| 327 | konamigx_esc_alert(space->machine().driver_data<konamigx_state>()->m_workram, 0x5c00, 0x100, 0); |
| 332 | 328 | } |
| 333 | 329 | |
| 334 | 330 | static void sal2_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4) |
| 335 | 331 | { |
| 336 | | konamigx_esc_alert(gx_workram, 0x1c8c, 0x172, 1); |
| 332 | konamigx_esc_alert(space->machine().driver_data<konamigx_state>()->m_workram, 0x1c8c, 0x172, 1); |
| 337 | 333 | } |
| 338 | 334 | |
| 339 | 335 | static void sexyparo_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4) |
| r17819 | r17820 | |
| 544 | 540 | |
| 545 | 541 | READ32_MEMBER(konamigx_state::waitskip_r) |
| 546 | 542 | { |
| 547 | | UINT32 data = gx_workram[waitskip.offs+offset]; |
| 543 | UINT32 data = m_workram[waitskip.offs+offset]; |
| 548 | 544 | |
| 549 | 545 | if (space.device().safe_pc() == waitskip.pc && (data & mem_mask) == (waitskip.data & mem_mask)) |
| 550 | 546 | { |
| r17819 | r17820 | |
| 1158 | 1154 | AM_RANGE(0x000000, 0x01ffff) AM_ROM // BIOS ROM |
| 1159 | 1155 | AM_RANGE(0x200000, 0x3fffff) AM_ROM // main program ROM |
| 1160 | 1156 | AM_RANGE(0x400000, 0x7fffff) AM_ROM // data ROM |
| 1161 | | AM_RANGE(0xc00000, 0xc1ffff) AM_RAM AM_BASE_LEGACY(&gx_workram) // work RAM |
| 1157 | AM_RANGE(0xc00000, 0xc1ffff) AM_RAM AM_SHARE("workram") // work RAM |
| 1162 | 1158 | AM_RANGE(0xd00000, 0xd01fff) AM_READ_LEGACY(K056832_5bpp_rom_long_r) |
| 1163 | 1159 | AM_RANGE(0xd20000, 0xd20fff) AM_READWRITE_LEGACY(K053247_long_r, K053247_long_w) |
| 1164 | 1160 | AM_RANGE(0xd21000, 0xd23fff) AM_RAM |
| r17819 | r17820 | |
| 1198 | 1194 | AM_RANGE(0xe20000, 0xe2000f) AM_WRITENOP |
| 1199 | 1195 | AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP |
| 1200 | 1196 | AM_RANGE(0xe80000, 0xe81fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) // chips 21L+19L / S |
| 1201 | | AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_BASE_LEGACY(&gx_psacram) // chips 20J+23J+18J / S |
| 1197 | AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_SHARE("psacram") // chips 20J+23J+18J / S |
| 1202 | 1198 | AM_RANGE(0xf00000, 0xf3ffff) AM_READ(type1_roz_r1) // ROM readback |
| 1203 | 1199 | AM_RANGE(0xf40000, 0xf7ffff) AM_READ(type1_roz_r2) // ROM readback |
| 1204 | 1200 | AM_RANGE(0xf80000, 0xf80fff) AM_RAM // chip 21Q / S |
| r17819 | r17820 | |
| 1220 | 1216 | AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE_LEGACY(&konamigx_type3_psac2_bank) |
| 1221 | 1217 | AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) |
| 1222 | 1218 | AM_RANGE(0xe80000, 0xe83fff) AM_RAM AM_SHARE("paletteram") // main monitor palette |
| 1223 | | AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_BASE_LEGACY(&gx_subpaletteram32) |
| 1219 | AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_SHARE("subpaletteram") |
| 1224 | 1220 | AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) |
| 1225 | 1221 | //AM_RANGE(0xf00000, 0xf07fff) AM_RAM |
| 1226 | 1222 | AM_IMPORT_FROM(gx_base_memmap) |
| r17819 | r17820 | |
| 1234 | 1230 | AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP |
| 1235 | 1231 | AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) // 29C & 29G (PSAC2 line control) |
| 1236 | 1232 | AM_RANGE(0xe80000, 0xe87fff) AM_RAM AM_SHARE("paletteram") // 11G/13G/15G (main screen palette RAM) |
| 1237 | | AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_BASE_LEGACY(&gx_subpaletteram32) // 5G/7G/9G (sub screen palette RAM) |
| 1233 | AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_SHARE("subpaletteram") // 5G/7G/9G (sub screen palette RAM) |
| 1238 | 1234 | AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) // type 4 polls this too |
| 1239 | | AM_RANGE(0xf00000, 0xf07fff) AM_RAM_WRITE(konamigx_t4_psacmap_w) AM_BASE_LEGACY(&gx_psacram) // PSAC2 tilemap |
| 1235 | AM_RANGE(0xf00000, 0xf07fff) AM_RAM_WRITE(konamigx_t4_psacmap_w) AM_SHARE("psacram") // PSAC2 tilemap |
| 1240 | 1236 | // AM_RANGE(0xf00000, 0xf07fff) AM_RAM |
| 1241 | 1237 | AM_IMPORT_FROM(gx_base_memmap) |
| 1242 | 1238 | ADDRESS_MAP_END |
| r17819 | r17820 | |
| 1290 | 1286 | /* 68000 memory handling */ |
| 1291 | 1287 | static ADDRESS_MAP_START( gxsndmap, AS_PROGRAM, 16, konamigx_state ) |
| 1292 | 1288 | AM_RANGE(0x000000, 0x03ffff) AM_ROM |
| 1293 | | AM_RANGE(0x100000, 0x10ffff) AM_RAM AM_BASE_LEGACY(&gx_sndram) |
| 1289 | AM_RANGE(0x100000, 0x10ffff) AM_RAM |
| 1294 | 1290 | AM_RANGE(0x200000, 0x2004ff) AM_DEVREADWRITE8("konami1", k054539_device, read, write, 0xff00) |
| 1295 | 1291 | AM_RANGE(0x200000, 0x2004ff) AM_DEVREADWRITE8("konami2", k054539_device, read, write, 0x00ff) |
| 1296 | 1292 | AM_RANGE(0x300000, 0x300001) AM_READWRITE(tms57002_data_word_r, tms57002_data_word_w) |
trunk/src/mess/drivers/a310.c
| r17819 | r17820 | |
| 69 | 69 | { |
| 70 | 70 | public: |
| 71 | 71 | a310_state(const machine_config &mconfig, device_type type, const char *tag) |
| 72 | | : driver_device(mconfig, type, tag) { } |
| 72 | : driver_device(mconfig, type, tag), |
| 73 | m_physram(*this, "physicalram") { } |
| 73 | 74 | |
| 75 | required_shared_ptr<UINT32> m_physram; |
| 76 | |
| 74 | 77 | DECLARE_READ32_MEMBER(a310_psy_wram_r); |
| 75 | 78 | DECLARE_WRITE32_MEMBER(a310_psy_wram_w); |
| 76 | 79 | DECLARE_DRIVER_INIT(a310); |
| r17819 | r17820 | |
| 95 | 98 | |
| 96 | 99 | READ32_MEMBER(a310_state::a310_psy_wram_r) |
| 97 | 100 | { |
| 98 | | return archimedes_memc_physmem[offset]; |
| 101 | return m_physram[offset]; |
| 99 | 102 | } |
| 100 | 103 | |
| 101 | 104 | WRITE32_MEMBER(a310_state::a310_psy_wram_w) |
| 102 | 105 | { |
| 103 | | COMBINE_DATA(&archimedes_memc_physmem[offset]); |
| 106 | COMBINE_DATA(&m_physram[offset]); |
| 104 | 107 | } |
| 105 | 108 | |
| 106 | 109 | |
| 107 | 110 | DRIVER_INIT_MEMBER(a310_state,a310) |
| 108 | 111 | { |
| 109 | 112 | UINT32 ram_size = machine().device<ram_device>(RAM_TAG)->size(); |
| 110 | | archimedes_memc_physmem = auto_alloc_array(machine(), UINT32, 0x01000000); |
| 111 | 113 | |
| 112 | 114 | machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), read32_delegate(FUNC(a310_state::a310_psy_wram_r), this), write32_delegate(FUNC(a310_state::a310_psy_wram_w), this)); |
| 113 | 115 | |
| r17819 | r17820 | |
| 129 | 131 | |
| 130 | 132 | static ADDRESS_MAP_START( a310_mem, AS_PROGRAM, 32, a310_state ) |
| 131 | 133 | AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w) |
| 132 | | // AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */ |
| 134 | AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */ |
| 133 | 135 | AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE_LEGACY(archimedes_ioc_r, archimedes_ioc_w) |
| 134 | 136 | AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE_LEGACY(archimedes_vidc_r, archimedes_vidc_w) |
| 135 | 137 | AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w) |