trunk/src/emu/cpu/sharc/sharc.c
| r17807 | r17808 | |
|---|
| 161 | 161 | |
| 162 | 162 | INT32 interrupt_active; |
| 163 | 163 | |
| 164 | | INT32 iop_latency_cycles; |
| 165 | | INT32 iop_latency_reg; |
| 166 | | UINT32 iop_latency_data; |
| 164 | UINT32 iop_delayed_reg; |
| 165 | UINT32 iop_delayed_data; |
| 166 | emu_timer *delayed_iop_timer; |
| 167 | 167 | |
| 168 | 168 | UINT32 delay_slot1, delay_slot2; |
| 169 | 169 | |
| r17807 | r17808 | |
|---|
| 212 | 212 | cpustate->delay_slot2 = cpustate->daddr; |
| 213 | 213 | } |
| 214 | 214 | |
| 215 | | |
| 216 | | |
| 217 | | static void add_iop_write_latency_effect(SHARC_REGS *cpustate, int iop_reg, UINT32 data, int latency) |
| 215 | static TIMER_CALLBACK(sharc_iop_delayed_write_callback) |
| 218 | 216 | { |
| 219 | | cpustate->iop_latency_cycles = latency+1; |
| 220 | | cpustate->iop_latency_reg = iop_reg; |
| 221 | | cpustate->iop_latency_data = data; |
| 222 | | } |
| 217 | SHARC_REGS *cpustate = (SHARC_REGS *)ptr; |
| 223 | 218 | |
| 224 | | static void iop_write_latency_effect(SHARC_REGS *cpustate) |
| 225 | | { |
| 226 | | UINT32 data = cpustate->iop_latency_data; |
| 227 | | |
| 228 | | switch (cpustate->iop_latency_reg) |
| 219 | switch (cpustate->iop_delayed_reg) |
| 229 | 220 | { |
| 230 | 221 | case 0x1c: |
| 231 | 222 | { |
| 232 | | if (data & 0x1) |
| 223 | if (cpustate->iop_delayed_data & 0x1) |
| 233 | 224 | { |
| 234 | 225 | sharc_dma_exec(cpustate, 6); |
| 235 | 226 | } |
| r17807 | r17808 | |
|---|
| 238 | 229 | |
| 239 | 230 | case 0x1d: |
| 240 | 231 | { |
| 241 | | if (data & 0x1) |
| 232 | if (cpustate->iop_delayed_data & 0x1) |
| 242 | 233 | { |
| 243 | 234 | sharc_dma_exec(cpustate, 7); |
| 244 | 235 | } |
| 245 | 236 | break; |
| 246 | 237 | } |
| 247 | 238 | |
| 248 | | default: fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X\n", cpustate->iop_latency_reg); |
| 239 | default: fatalerror("SHARC: sharc_iop_d |
| 249 | 240 | } |
| 241 | |
| 242 | cpustate->delayed_iop_timer->adjust(attotime::never, 0); |
| 250 | 243 | } |
| 251 | 244 | |
| 245 | static void sharc_iop_delayed_w(SHARC_REGS *cpustate, UINT32 reg, UINT32 data, int cycles) |
| 246 | { |
| 247 | cpustate->iop_delayed_reg = reg; |
| 248 | cpustate->iop_delayed_data = data; |
| 252 | 249 | |
| 250 | cpustate->delayed_iop_timer->adjust(cpustate->device->cycles_to_attotime(cycles), 0); |
| 251 | } |
| 253 | 252 | |
| 253 | |
| 254 | 254 | /* IOP registers */ |
| 255 | 255 | static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address) |
| 256 | 256 | { |
| r17807 | r17808 | |
|---|
| 292 | 292 | case 0x1c: |
| 293 | 293 | { |
| 294 | 294 | cpustate->dma[6].control = data; |
| 295 | | add_iop_write_latency_effect(cpustate, 0x1c, data, 1); |
| 295 | //add_iop_write_latency_effect(cpustate, 0x1c, data, 1); |
| 296 | sharc_iop_delayed_w(cpustate, 0x1c, data, 1); |
| 296 | 297 | break; |
| 297 | 298 | } |
| 298 | 299 | |
| r17807 | r17808 | |
|---|
| 311 | 312 | case 0x1d: |
| 312 | 313 | { |
| 313 | 314 | cpustate->dma[7].control = data; |
| 314 | | add_iop_write_latency_effect(cpustate, 0x1d, data, 30); |
| 315 | //add_iop_write_latency_effect(cpustate, 0x1d, data, 30); |
| 316 | sharc_iop_delayed_w(cpustate, 0x1d, data, 30); |
| 315 | 317 | break; |
| 316 | 318 | } |
| 317 | 319 | |
| r17807 | r17808 | |
|---|
| 434 | 436 | cpustate->internal_ram_block0 = &cpustate->internal_ram[0]; |
| 435 | 437 | cpustate->internal_ram_block1 = &cpustate->internal_ram[0x20000/2]; |
| 436 | 438 | |
| 439 | cpustate->delayed_iop_timer = device->machine().scheduler().timer_alloc(FUNC(sharc_iop_delayed_write_callback), cpustate); |
| 440 | |
| 437 | 441 | device->save_item(NAME(cpustate->pc)); |
| 438 | 442 | device->save_pointer(NAME(&cpustate->r[0].r), ARRAY_LENGTH(cpustate->r)); |
| 439 | 443 | device->save_pointer(NAME(&cpustate->reg_alt[0].r), ARRAY_LENGTH(cpustate->reg_alt)); |
| r17807 | r17808 | |
|---|
| 533 | 537 | |
| 534 | 538 | device->save_item(NAME(cpustate->interrupt_active)); |
| 535 | 539 | |
| 536 | | device->save_item(NAME(cpustate->iop_latency_cycles)); |
| 537 | | device->save_item(NAME(cpustate->iop_latency_reg)); |
| 538 | | device->save_item(NAME(cpustate->iop_latency_data)); |
| 540 | device->save_item(NAME(cpustate->iop_delayed_reg)); |
| 541 | device->save_item(NAME(cpustate->iop_delayed_data)); |
| 539 | 542 | |
| 540 | 543 | device->save_item(NAME(cpustate->delay_slot1)); |
| 541 | 544 | device->save_item(NAME(cpustate->delay_slot2)); |
| r17807 | r17808 | |
|---|
| 787 | 790 | } |
| 788 | 791 | } |
| 789 | 792 | |
| 790 | | // IOP register latency effect |
| 791 | | if (cpustate->iop_latency_cycles > 0) |
| 792 | | { |
| 793 | | --cpustate->iop_latency_cycles; |
| 794 | | if (cpustate->iop_latency_cycles <= 0) |
| 795 | | { |
| 796 | | iop_write_latency_effect(cpustate); |
| 797 | | } |
| 798 | | } |
| 799 | | |
| 800 | 793 | // DMA transfer |
| 801 | 794 | if (cpustate->dmaop_cycles > 0) |
| 802 | 795 | { |