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r17779 Monday 10th September, 2012 at 14:18:45 UTC by Curt Coder
(MESS) c128: MMU WIP. (nw) (MESS) mos6581: Improved interface. (nw) mos6526: Improved interface. (nw)

[src/emu/machine]	6526cia.c 6526cia.h
[src/emu/sound]	sid6581.c sid6581.h
[src/emu/video]	mc6845.c mc6845.h
[src/mame/drivers]	alg.c arcadia.c cd32.c mquake.c upscope.c
[src/mess/drivers]	ami1200.c amiga.c c128.c c64.c c65.c cbmb.c sbc6510.c vic10.c
[src/mess/includes]	c128.h c65.h vic10.h
[src/mess/machine]	c128.c c1571.c c1581.c c64.c c65.c cbmb.c cbmipt.c mos8722.c mos8722.h plus4_sid.c plus4_sid.h

trunk/src/mame/drivers/arcadia.c

r17778	r17779
286	286
287	287	static const mos6526_interface cia_0_intf =
288	288	{
289		0,                                          /* tod_clock */
290	289	DEVCB_LINE(amiga_cia_0_irq),                              /* irq_func */
291	290	DEVCB_NULL,   /* pc_func */
292	291	DEVCB_NULL,
r17778	r17779
299	298
300	299	static const mos6526_interface cia_1_intf =
301	300	{
302		0,                                          /* tod_clock */
303	301	DEVCB_LINE(amiga_cia_1_irq),                              /* irq_func */
304	302	DEVCB_NULL,   /* pc_func */
305	303	DEVCB_NULL,
r17778	r17779
344	342	MCFG_SOUND_ROUTE(3, "lspeaker", 0.50)
345	343
346	344	/* cia */
347		MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, cia_0_intf)
348		MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, cia_1_intf)
	345	MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_0_intf)
	346	MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_1_intf)
349	347
350	348	/* fdc */
351	349	MCFG_AMIGA_FDC_ADD("fdc", AMIGA_68000_NTSC_CLOCK)

trunk/src/mame/drivers/cd32.c

r17778	r17779
727	727
728	728	static const mos6526_interface cia_0_intf =
729	729	{
730		0,                                       /* tod_clock */
731	730	DEVCB_LINE(amiga_cia_0_irq),                           /* irq_func */
732	731	DEVCB_NULL,   /* pc_func */
733	732	DEVCB_NULL,
r17778	r17779
740	739
741	740	static const mos6526_interface cia_1_intf =
742	741	{
743		0,                                       /* tod_clock */
744	742	DEVCB_LINE(amiga_cia_1_irq),                           /* irq_func */
745	743	DEVCB_NULL,   /* pc_func */
746	744	DEVCB_NULL,
r17778	r17779
802	800	MCFG_SOUND_ROUTE( 1, "rspeaker", 0.50 )
803	801
804	802	/* cia */
805		MCFG_MOS8520_ADD("cia_0", AMIGA_68EC020_PAL_CLOCK / 10, cia_0_intf)
806		MCFG_MOS8520_ADD("cia_1", AMIGA_68EC020_PAL_CLOCK / 10, cia_1_intf)
	803	MCFG_MOS8520_ADD("cia_0", AMIGA_68EC020_PAL_CLOCK / 10, 0, cia_0_intf)
	804	MCFG_MOS8520_ADD("cia_1", AMIGA_68EC020_PAL_CLOCK / 10, 0, cia_1_intf)
807	805
808	806	MCFG_MICROTOUCH_ADD( "microtouch", cd32_microtouch_config )
809	807

trunk/src/mame/drivers/alg.c

r17778	r17779
412	412
413	413	static const mos6526_interface cia_0_intf =
414	414	{
415		0,                                    /* tod_clock */
416	415	DEVCB_LINE(amiga_cia_0_irq),                        /* irq_func */
417	416	DEVCB_NULL,   /* pc_func */
418	417	DEVCB_NULL,
r17778	r17779
425	424
426	425	static const mos6526_interface cia_1_intf =
427	426	{
428		0,                                    /* tod_clock */
429	427	DEVCB_LINE(amiga_cia_1_irq),                        /* irq_func */
430	428	DEVCB_NULL,   /* pc_func */
431	429	DEVCB_NULL,
r17778	r17779
475	473	MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
476	474
477	475	/* cia */
478		MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, cia_0_intf)
479		MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, cia_1_intf)
	476	MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_0_intf)
	477	MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_1_intf)
480	478
481	479	/* fdc */
482	480	MCFG_AMIGA_FDC_ADD("fdc", AMIGA_68000_NTSC_CLOCK)

trunk/src/mame/drivers/upscope.c

r17778	r17779
285	285
286	286	static const mos6526_interface cia_0_intf =
287	287	{
288		0,                                          /* tod_clock */
289	288	DEVCB_LINE(amiga_cia_0_irq),                              /* irq_func */
290	289	DEVCB_NULL,   /* pc_func */
291	290	DEVCB_NULL,
r17778	r17779
298	297
299	298	static const mos6526_interface cia_1_intf =
300	299	{
301		0,                                          /* tod_clock */
302	300	DEVCB_LINE(amiga_cia_1_irq),                              /* irq_func */
303	301	DEVCB_NULL,   /* pc_func */
304	302	DEVCB_NULL,
r17778	r17779
343	341	MCFG_SOUND_ROUTE(3, "rspeaker", 0.50)
344	342
345	343	/* cia */
346		MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, cia_0_intf)
347		MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, cia_1_intf)
	344	MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_0_intf)
	345	MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_1_intf)
348	346
349	347	/* fdc */
350	348	MCFG_AMIGA_FDC_ADD("fdc", AMIGA_68000_NTSC_CLOCK)

trunk/src/mame/drivers/mquake.c

r17778	r17779
315	315
316	316	static const mos6526_interface cia_0_intf =
317	317	{
318		0,                                       /* tod_clock */
319	318	DEVCB_LINE(amiga_cia_0_irq),                           /* irq_func */
320	319	DEVCB_NULL,   /* pc_func */
321	320	DEVCB_NULL,
r17778	r17779
328	327
329	328	static const mos6526_interface cia_1_intf =
330	329	{
331		0,                                       /* tod_clock */
332	330	DEVCB_LINE(amiga_cia_1_irq),                           /* irq_func */
333	331	DEVCB_NULL,   /* pc_func */
334	332	DEVCB_NULL,
r17778	r17779
380	378	MCFG_SOUND_ROUTE(1, "rspeaker", 0.50)
381	379
382	380	/* cia */
383		MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, cia_0_intf)
384		MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, cia_1_intf)
	381	MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_0_intf)
	382	MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK / 10, 0, cia_1_intf)
385	383
386	384	/* fdc */
387	385	MCFG_AMIGA_FDC_ADD("fdc", AMIGA_68000_NTSC_CLOCK)

trunk/src/emu/video/mc6845.c

r17778	r17779
1169	1169	m_supports_status_reg_d7 = true;
1170	1170	m_update_ready_bit = 1;
1171	1171
	1172	m_update_row = vdc_update_row;
	1173
1172	1174	save_item(NAME(m_char_buffer));
1173	1175	save_item(NAME(m_attr_buffer));
1174	1176	save_item(NAME(m_attribute_addr));
r17778	r17779
1424	1426	}
1425	1427	}
1426	1428	}
	1429
	1430	MC6845_UPDATE_ROW( mos8563_device::vdc_update_row )
	1431	{
	1432	mos8563_device *mos8563 = static_cast<mos8563_device *>(device);
	1433
	1434	mos8563->update_row(bitmap, cliprect, ma, ra, y, x_count, cursor_x, param);
	1435	}

trunk/src/emu/video/mc6845.h

r17778	r17779
395	395	inline void write_videoram(offs_t offset, UINT8 data);
396	396
397	397	void update_row(bitmap_rgb32 &bitmap, const rectangle &cliprect, UINT16 ma, UINT8 ra, UINT16 y, UINT8 x_count, INT8 cursor_x, void *param);
	398	static MC6845_UPDATE_ROW( vdc_update_row );
398	399
399	400	protected:
400	401	// device-level overrides

trunk/src/emu/sound/sid6581.c

r17778	r17779
73	73
74	74
75	75
76		READ8_DEVICE_HANDLER  ( sid6581_r )
	76	READ8_MEMBER( sid6581_device::read )
77	77	{
78		return sid6581_port_r(device->machine(), get_sid(device), offset);
	78	return sid6581_port_r(machine(), get_sid(this), offset);
79	79	}
80	80
81	81
82		WRITE8_DEVICE_HANDLER ( sid6581_w )
	82	WRITE8_MEMBER( sid6581_device::write )
83	83	{
84		sid6581_port_w(get_sid(device), offset, data);
	84	sid6581_port_w(get_sid(this), offset, data);
85	85	}
86	86
87	87	const device_type SID6581 = &device_creator<sid6581_device>;

trunk/src/emu/sound/sid6581.h

r17778	r17779
30	30	devcb_read8 in_poty_cb;
31	31	};
32	32
33
34		READ8_DEVICE_HANDLER  ( sid6581_r );
35		WRITE8_DEVICE_HANDLER ( sid6581_w );
36
37	33	class sid6581_device : public device_t,
38	34	public device_sound_interface
39	35	{
r17778	r17779
44	40
45	41	// access to legacy token
46	42	void *token() const { assert(m_token != NULL); return m_token; }
	43
	44	DECLARE_READ8_MEMBER( read );
	45	DECLARE_WRITE8_MEMBER( write );
	46
47	47	protected:
48	48	// device-level overrides
49	49	virtual void device_config_complete();

trunk/src/emu/machine/6526cia.c

r17778	r17779
53	53	const device_type MOS6526R1 = &device_creator<mos6526r1_device>;
54	54	const device_type MOS6526R2 = &device_creator<mos6526r2_device>;
55	55	const device_type MOS8520 = &device_creator<mos8520_device>;
	56	const device_type MOS5710 = &device_creator<mos5710_device>;
56	57
57	58
58	59
r17778	r17779
89	90	mos8520_device::mos8520_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
90	91	: mos6526_device(mconfig, MOS8520, "MOS8520", tag, owner, clock) { }
91	92
	93	mos5710_device::mos5710_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	94	: mos6526_device(mconfig, MOS5710, "MOS5710", tag, owner, clock) { }
92	95
	96
	97	void mos6526_device::static_set_tod_clock(device_t &device, int tod_clock)
	98	{
	99	mos6526_device &cia = dynamic_cast<mos6526_device &>(device);
	100
	101	cia.m_tod_clock = tod_clock;
	102	}
	103
	104
93	105	//-------------------------------------------------
94	106	//  device_reset - device-specific reset
95	107	//-------------------------------------------------
r17778	r17779
152	164	// or initialize to defaults if none provided
153	165	else
154	166	{
155		m_tod_clock = 0;
156	167	memset(&m_out_irq_cb, 0, sizeof(m_out_irq_cb));
157	168	memset(&m_out_pc_cb, 0, sizeof(m_out_pc_cb));
158	169	memset(&m_out_cnt_cb, 0, sizeof(m_out_cnt_cb));
r17778	r17779
200	211	timer->m_irq = 0x01 << t;
201	212	}
202	213
203		/* setup TOD timer, if appropriate */
204		if (m_tod_clock != 0)
	214	if (m_tod_clock > 0)
205	215	{
206		machine().scheduler().timer_pulse(attotime::from_hz(m_tod_clock), FUNC(clock_tod_callback), 0, (void *)this);
	216	m_tod_timer = timer_alloc(TIMER_TOD);
	217	m_tod_timer->adjust(attotime::from_hz(m_tod_clock), 0, attotime::from_hz(m_tod_clock));
207	218	}
208	219
209	220	/* state save support */
r17778	r17779
254	265	case TIMER_PC:
255	266	m_out_pc_func(1);
256	267	break;
	268
	269	case TIMER_TOD:
	270	clock_tod();
	271	break;
257	272	}
258	273	}
259	274
r17778	r17779
506	521
507	522
508	523	/*-------------------------------------------------
509		clock_tod_callback
510		-------------------------------------------------*/
511
512		TIMER_CALLBACK( mos6526_device::clock_tod_callback )
513		{
514		mos6526_device *cia = reinterpret_cast<mos6526_device *>(ptr);
515		cia->clock_tod();
516		}
517
518
519		/*-------------------------------------------------
520	524	cnt_w
521	525	-------------------------------------------------*/
522	526
r17778	r17779
577	581	m_flag = state;
578	582	}
579	583
	584	READ8_MEMBER( mos6526_device::read )
	585	{
	586	return reg_r(offset);
	587	}
	588
	589	WRITE8_MEMBER( mos6526_device::write )
	590	{
	591	reg_w(offset, data);
	592	}
	593
580	594	/*-------------------------------------------------
581	595	reg_r
582	596	-------------------------------------------------*/

trunk/src/emu/machine/6526cia.h

r17778	r17779
43	43	//  INTERFACE CONFIGURATION MACROS
44	44	//**************************************************************************
45	45
46		#define MCFG_MOS6526R1_ADD(_tag, _clock, _config) \
	46	#define MCFG_MOS6526R1_ADD(_tag, _clock, _tod_clock, _config) \
47	47	MCFG_DEVICE_ADD(_tag, MOS6526R1, _clock) \
48		MCFG_DEVICE_CONFIG(_config)
	48	MCFG_DEVICE_CONFIG(_config) \
	49	mos6526_device::static_set_tod_clock(*device, _tod_clock);
49	50
50		#define MCFG_MOS6526R2_ADD(_tag, _clock, _config) \
	51	#define MCFG_MOS6526R2_ADD(_tag, _clock, _tod_clock, _config) \
51	52	MCFG_DEVICE_ADD(_tag, MOS6526R2, _clock) \
52		MCFG_DEVICE_CONFIG(_config)
	53	MCFG_DEVICE_CONFIG(_config) \
	54	mos6526_device::static_set_tod_clock(*device, _tod_clock);
53	55
54		#define MCFG_MOS8520_ADD(_tag, _clock, _config) \
	56	#define MCFG_MOS8520_ADD(_tag, _clock, _tod_clock, _config) \
55	57	MCFG_DEVICE_ADD(_tag, MOS8520, _clock) \
56		MCFG_DEVICE_CONFIG(_config)
	58	MCFG_DEVICE_CONFIG(_config) \
	59	mos6526_device::static_set_tod_clock(*device, _tod_clock);
57	60
	61	#define MCFG_MOS5710_ADD(_tag, _clock, _tod_clock, _config) \
	62	MCFG_DEVICE_ADD(_tag, MOS5710, _clock) \
	63	MCFG_DEVICE_CONFIG(_config) \
	64	mos6526_device::static_set_tod_clock(*device, _tod_clock);
	65
	66
58	67	#define MOS6526_INTERFACE(name) \
59	68	const mos6526_interface (name)=
60	69
61	70	#define MOS8520_INTERFACE(name) \
62	71	const mos6526_interface (name)=
63	72
	73	#define MOS5710_INTERFACE(name) \
	74	const mos6526_interface (name)=
	75
	76
	77
64	78	/***************************************************************************
65	79	TYPE DEFINITIONS
66	80	***************************************************************************/
r17778	r17779
70	84
71	85	struct mos6526_interface
72	86	{
73		int m_tod_clock;
74
75	87	devcb_write_line   m_out_irq_cb;
76	88	devcb_write_line   m_out_pc_cb;
77	89	devcb_write_line   m_out_cnt_cb;
r17778	r17779
91	103	class mos6526_device :  public device_t,
92	104	public mos6526_interface
93	105	{
94		friend class dart_channel;
95
96	106	protected:
97	107	// construction/destruction
98	108	mos6526_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
99	109
100	110	public:
	111	// inline configuration
	112	static void static_set_tod_clock(device_t &device, int tod_clock);
	113
	114	DECLARE_READ8_MEMBER( read );
	115	DECLARE_WRITE8_MEMBER( write );
	116
101	117	UINT8 reg_r(UINT8 offset);
102	118	void reg_w(UINT8 offset, UINT8 data);
103	119
r17778	r17779
138	154	static TIMER_CALLBACK( clock_tod_callback );
139	155
140	156	private:
141		static const device_timer_id TIMER_PC = 0;
	157	enum
	158	{
	159	TIMER_PC,
	160	TIMER_TOD
	161	};
142	162
143	163	inline attotime cycles_to_time(int c);
144	164	void update_pc();
r17778	r17779
185	205	cia_timer      m_timer[2];
186	206
187	207	/* Time Of the Day clock (TOD) */
	208	int            m_tod_clock;
188	209	UINT32         m_tod;
189	210	UINT32         m_tod_latch;
190	211	UINT8         m_tod_latched;
r17778	r17779
206	227	UINT8         m_serial;
207	228
208	229	emu_timer *m_pc_timer;
	230	emu_timer *m_tod_timer;
209	231	};
210	232
211	233	class mos6526r1_device : public mos6526_device
r17778	r17779
226	248	mos8520_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
227	249	};
228	250
	251	class mos5710_device : public mos6526_device
	252	{
	253	public:
	254	mos5710_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	255	};
229	256
	257
230	258	// device type definition
231	259	extern const device_type MOS6526R1;
232	260	extern const device_type MOS6526R2;
233	261	extern const device_type MOS8520;
	262	extern const device_type MOS5710;
234	263
235	264
236	265

trunk/src/mess/machine/c1581.c

r17778	r17779
276	276
277	277	static MOS8520_INTERFACE( cia_intf )
278	278	{
279		XTAL_16MHz/8,
280	279	DEVCB_CPU_INPUT_LINE(M6502_TAG, INPUT_LINE_IRQ0),
281	280	DEVCB_NULL,
282	281	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, base_c1581_device, cnt_w),
r17778	r17779
336	335	MCFG_CPU_ADD(M6502_TAG, M6502, XTAL_16MHz/8)
337	336	MCFG_CPU_PROGRAM_MAP(c1581_mem)
338	337
339		MCFG_MOS8520_ADD(M8520_TAG, XTAL_16MHz/8, cia_intf)
	338	MCFG_MOS8520_ADD(M8520_TAG, XTAL_16MHz/8, 0, cia_intf)
340	339	MCFG_WD1770_ADD(WD1770_TAG, /*XTAL_16MHz/2,*/ fdc_intf)
341	340
342	341	MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, c1581_floppy_interface)

trunk/src/mess/machine/cbmb.c

r17778	r17779
259	259
260	260	const mos6526_interface cbmb_cia =
261	261	{
262		60,
263	262	DEVCB_DEVICE_LINE("tpi6525_0", tpi6525_i2_w),
264	263	DEVCB_NULL,   /* pc_func */
265	264	DEVCB_NULL,

trunk/src/mess/machine/cbmipt.c

r17778	r17779
408	408	PORT_CONFNAME( 0x10, 0x10, "40 80 Display (switch) (active after a rebooting)")
409	409	PORT_CONFSETTING(   0x00, "40 Columns (DIN/TV)")
410	410	PORT_CONFSETTING(   0x10, "80 Columns (RGBI)")
411		PORT_CONFNAME( 0x06, 0x00, "Main Memory / MMU Version")
412		PORT_CONFSETTING(   0x00, "128 KByte" )
413		PORT_CONFSETTING(   0x02, "256 KByte" )
414		PORT_CONFSETTING(   0x04, "1024 KByte" )
415	411	INPUT_PORTS_END
416	412
417	413

trunk/src/mess/machine/plus4_sid.c

r17778	r17779
141	141	{
142	142	if ((offset >= 0xfe80 && offset < 0xfea0) || (offset >= 0xfd40 && offset < 0xfd60))
143	143	{
144		data = sid6581_r(m_sid, offset & 0x1f);
	144	data = m_sid->read(space, offset & 0x1f);
145	145	}
146	146	else if (offset >= 0xfd80 && offset < 0xfd90)
147	147	{
r17778	r17779
160	160	{
161	161	if ((offset >= 0xfe80 && offset < 0xfea0) || (offset >= 0xfd40 && offset < 0xfd60))
162	162	{
163		sid6581_w(m_sid, offset & 0x1f, data);
	163	m_sid->write(space, offset & 0x1f, data);
164	164	}
165	165	}
166	166

trunk/src/mess/machine/plus4_sid.h

r17778	r17779
51	51	virtual void plus4_breset_w(int state);
52	52
53	53	private:
54		required_device<device_t> m_sid;
	54	required_device<sid6581_device> m_sid;
55	55	required_device<vcs_control_port_device> m_joy;
56	56	};
57	57

trunk/src/mess/machine/c64.c

r17778	r17779
129	129
130	130	const mos6526_interface c64_ntsc_cia0 =
131	131	{
132		10, /* 1/10 second */
133	132	DEVCB_LINE(c64_cia0_interrupt),
134	133	DEVCB_NULL,   /* pc_func */
135	134	DEVCB_NULL,
r17778	r17779
142	141
143	142	const mos6526_interface c64_pal_cia0 =
144	143	{
145		10, /* 1/10 second */
146	144	DEVCB_LINE(c64_cia0_interrupt),
147	145	DEVCB_NULL,   /* pc_func */
148	146	DEVCB_NULL,
r17778	r17779
210	208
211	209	const mos6526_interface c64_ntsc_cia1 =
212	210	{
213		10, /* 1/10 second */
214	211	DEVCB_LINE(c64_cia1_interrupt),
215	212	DEVCB_NULL,   /* pc_func */
216	213	DEVCB_NULL,
r17778	r17779
223	220
224	221	const mos6526_interface c64_pal_cia1 =
225	222	{
226		10, /* 1/10 second */
227	223	DEVCB_LINE(c64_cia1_interrupt),
228	224	DEVCB_NULL,   /* pc_func */
229	225	DEVCB_NULL,
r17778	r17779
255	251	legacy_c64_state *state = space->machine().driver_data<legacy_c64_state>();
256	252	device_t *cia_0 = space->machine().device("cia_0");
257	253	device_t *cia_1 = space->machine().device("cia_1");
258		device_t *sid = space->machine().device("sid6581");
	254	sid6581_device *sid = space->machine().device<sid6581_device>("sid6581");
259	255	device_t *vic2 = space->machine().device("vic2");
260	256
261	257	state->m_io_mirror[offset] = data;
262	258	if (offset < 0x400)
263	259	vic2_port_w(vic2, offset & 0x3ff, data);
264	260	else if (offset < 0x800)
265		sid6581_w(sid, offset & 0x3ff, data);
	261	sid->write(*space, offset & 0x3ff, data);
266	262	else if (offset < 0xc00)
267	263	state->m_colorram[offset & 0x3ff] = data | 0xf0;
268	264	else if (offset < 0xd00)
r17778	r17779
294	290	legacy_c64_state *state = space->machine().driver_data<legacy_c64_state>();
295	291	device_t *cia_0 = space->machine().device("cia_0");
296	292	device_t *cia_1 = space->machine().device("cia_1");
297		device_t *sid = space->machine().device("sid6581");
	293	sid6581_device *sid = space->machine().device<sid6581_device>("sid6581");
298	294	device_t *vic2 = space->machine().device("vic2");
299	295
300	296	if (offset < 0x400)
301	297	return vic2_port_r(vic2, offset & 0x3ff);
302	298
303	299	else if (offset < 0x800)
304		return sid6581_r(sid, offset & 0x3ff);
	300	return sid->read(*space, offset & 0x3ff);
305	301
306	302	else if (offset < 0xc00)
307	303	return state->m_colorram[offset & 0x3ff];

trunk/src/mess/machine/c65.c

r17778	r17779
130	130	#endif
131	131	}
132	132
133		const mos6526_interface c65_ntsc_cia0 =
	133	const mos6526_interface c65_cia0 =
134	134	{
135		60,
136	135	DEVCB_LINE(c65_cia0_interrupt),
137	136	DEVCB_NULL,   /* pc_func */
138	137	DEVCB_NULL,
r17778	r17779
143	142	DEVCB_HANDLER(c65_cia0_port_b_w)
144	143	};
145	144
146		const mos6526_interface c65_pal_cia0 =
147		{
148		50,
149		DEVCB_LINE(c65_cia0_interrupt),
150		DEVCB_NULL,   /* pc_func */
151		DEVCB_NULL,
152		DEVCB_NULL,
153		DEVCB_HANDLER(c65_cia0_port_a_r),
154		DEVCB_NULL,
155		DEVCB_HANDLER(c65_cia0_port_b_r),
156		DEVCB_HANDLER(c65_cia0_port_b_w)
157		};
158
159	145	/*
160	146	* CIA 1 - Port A
161	147	* bit 7 serial bus data input
r17778	r17779
210	196	c65_nmi(device->machine());
211	197	}
212	198
213		const mos6526_interface c65_ntsc_cia1 =
	199	const mos6526_interface c65_cia1 =
214	200	{
215		60,
216	201	DEVCB_LINE(c65_cia1_interrupt),
217	202	DEVCB_NULL,   /* pc_func */
218	203	DEVCB_NULL,
r17778	r17779
223	208	DEVCB_NULL
224	209	};
225	210
226		const mos6526_interface c65_pal_cia1 =
227		{
228		50,
229		DEVCB_LINE(c65_cia1_interrupt),
230		DEVCB_NULL,   /* pc_func */
231		DEVCB_NULL,
232		DEVCB_NULL,
233		DEVCB_HANDLER(c65_cia1_port_a_r),
234		DEVCB_HANDLER(c65_cia1_port_a_w),
235		DEVCB_NULL,
236		DEVCB_NULL
237		};
238
239	211	/***********************************************
240	212
241	213	Memory Handlers
r17778	r17779
674	646
675	647	static WRITE8_HANDLER( c65_write_io )
676	648	{
677		device_t *sid_0 = space->machine().device("sid_r");
678		device_t *sid_1 = space->machine().device("sid_l");
	649	sid6581_device *sid_0 = space->machine().device<sid6581_device>("sid_r");
	650	sid6581_device *sid_1 = space->machine().device<sid6581_device>("sid_l");
679	651	device_t *vic3 = space->machine().device("vic3");
680	652
681	653	switch (offset & 0xf00)
r17778	r17779
698	670	break;
699	671	case 0x400:
700	672	if (offset<0x420) /* maybe 0x20 */
701		sid6581_w(sid_0, offset & 0x3f, data);
	673	sid_0->write(*space, offset & 0x3f, data);
702	674	else if (offset<0x440)
703		sid6581_w(sid_1, offset & 0x3f, data);
	675	sid_1->write(*space, offset & 0x3f, data);
704	676	else
705	677	DBG_LOG(space->machine(), 1, "io write", ("%.3x %.2x\n", offset, data));
706	678	break;
r17778	r17779
738	710
739	711	static READ8_HANDLER( c65_read_io )
740	712	{
741		device_t *sid_0 = space->machine().device("sid_r");
742		device_t *sid_1 = space->machine().device("sid_l");
	713	sid6581_device *sid_0 = space->machine().device<sid6581_device>("sid_r");
	714	sid6581_device *sid_1 = space->machine().device<sid6581_device>("sid_l");
743	715	device_t *vic3 = space->machine().device("vic3");
744	716
745	717	switch (offset & 0xf00)
r17778	r17779
763	735	break;
764	736	case 0x400:
765	737	if (offset < 0x420)
766		return sid6581_r(sid_0, offset & 0x3f);
	738	return sid_0->read(*space, offset & 0x3f);
767	739	if (offset < 0x440)
768		return sid6581_r(sid_1, offset & 0x3f);
	740	return sid_1->read(*space, offset & 0x3f);
769	741	DBG_LOG(space->machine(), 1, "io read", ("%.3x\n", offset));
770	742	break;
771	743	case 0x500:

trunk/src/mess/machine/c128.c

r17778	r17779
223	223	iec_data_out_w();
224	224	}
225	225
226		const mos6526_interface c128_ntsc_cia0 =
	226	const mos6526_interface c128_cia1_intf =
227	227	{
228		60,
229	228	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_irq_w),
230	229	DEVCB_NULL,   /* pc_func */
231	230	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_cnt_w),
r17778	r17779
236	235	DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_w)
237	236	};
238	237
239		const mos6526_interface c128_pal_cia0 =
240		{
241		50,
242		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_irq_w),
243		DEVCB_NULL,   /* pc_func */
244		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_cnt_w),
245		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia1_sp_w),
246		DEVCB_DRIVER_MEMBER(c128_state, cia1_pa_r),
247		DEVCB_NULL,
248		DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_r),
249		DEVCB_DRIVER_MEMBER(c128_state, cia1_pb_w)
250		};
251
252	238	WRITE_LINE_MEMBER( c128_state::iec_srq_w )
253	239	{
254	240	mos6526_cnt_w(m_cia1, MMU_FSDIR || state);
r17778	r17779
315	301	nmi();
316	302	}
317	303
318		const mos6526_interface c128_ntsc_cia1 =
	304	const mos6526_interface c128_cia2_intf =
319	305	{
320		60,
321	306	DEVCB_DRIVER_LINE_MEMBER(c128_state, cia2_irq_w),
322	307	DEVCB_NULL,   /* pc_func */
323	308	DEVCB_NULL,
r17778	r17779
328	313	DEVCB_NULL
329	314	};
330	315
331		const mos6526_interface c128_pal_cia1 =
332		{
333		50,
334		DEVCB_DRIVER_LINE_MEMBER(c128_state, cia2_irq_w),
335		DEVCB_NULL,   /* pc_func */
336		DEVCB_NULL,
337		DEVCB_NULL,
338		DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_r),
339		DEVCB_DRIVER_MEMBER(c128_state, cia2_pa_w),
340		DEVCB_NULL,
341		DEVCB_NULL
342		};
343
344	316	/***********************************************
345	317
346	318	Memory Handlers
r17778	r17779
366	338	if (offset + 0xd000 >= m_ram_top)
367	339	m_memory[0xd000 + offset] = data;
368	340	else
369		m_ram[0xd000 + offset] = data;
	341	m_ram_ptr[0xd000 + offset] = data;
370	342	}
371	343	else
372	344	{
r17778	r17779
376	348	m_vic->write(space, offset & 0x3f, data);
377	349	break;
378	350	case 4:
379		sid6581_w(m_sid, offset & 0x3f, data);
	351	m_sid->write(space, offset & 0x3f, data);
380	352	break;
381	353	case 5:
382	354	mmu8722_port_w(space, offset & 0xff, data);
r17778	r17779
416	388	if (offset < 0x400)
417	389	return m_vic->read(space, offset & 0x3f);
418	390	else if (offset < 0x500)
419		return sid6581_r(m_sid, offset & 0xff);
	391	return m_sid->read(space, offset & 0xff);
420	392	else if (offset < 0x600)
421	393	return mmu8722_port_r(space, offset & 0xff);
422	394	else if (offset < 0x800)
r17778	r17779
519	491	0x3f 0x3f 0x7f 0x3e 0x7e 0xb0 0x0b 0x00 0x00 0x01 0x00 */
520	492	void c128_state::bankswitch_z80()
521	493	{
522		m_ram = m_memory + MMU_RAM_ADDR;
	494	m_ram_ptr = m_memory + MMU_RAM_ADDR;
523	495	m_va1617 = MMU_VIC_ADDR;
524	496	#if 1
525	497	membank("bank10")->set_base(m_z80);
526		membank("bank11")->set_base(m_ram + 0x1000);
	498	membank("bank11")->set_base(m_ram_ptr + 0x1000);
527	499	if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
528	500	|| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
529		m_ram = NULL;
	501	m_ram_ptr = NULL;
530	502	#else
531	503	if (MMU_BOTTOM)
532	504	m_ram_bottom = MMU_SIZE;
r17778	r17779
587	559	if (m_c64mode)
588	560	{
589	561	/* mmu works also in c64 mode, but this can wait */
590		m_ram = m_memory;
	562	m_ram_ptr = m_memory;
591	563	m_va1617 = 0;
592	564	m_ram_bottom = 0;
593	565	m_ram_top = 0x10000;
r17778	r17779
608	580	}
609	581	else
610	582	{
611		m_ram = m_memory + MMU_RAM_ADDR;
	583	m_ram_ptr = m_memory + MMU_RAM_ADDR;
612	584	m_va1617 = MMU_VIC_ADDR;
613	585	membank("bank1")->set_base(m_memory + m_mmu_page0);
614	586	membank("bank2")->set_base(m_memory + m_mmu_page1);
r17778	r17779
618	590	}
619	591	else
620	592	m_ram_bottom = 0;
621		membank("bank3")->set_base((m_ram_bottom > 0x200 ? m_memory : m_ram) + 0x200);
622		membank("bank4")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram) + 0x400);
623		membank("bank5")->set_base((m_ram_bottom > 0x1000 ? m_memory : m_ram) + 0x1000);
624		membank("bank6")->set_base((m_ram_bottom > 0x2000 ? m_memory : m_ram) + 0x2000);
	593	membank("bank3")->set_base((m_ram_bottom > 0x200 ? m_memory : m_ram_ptr) + 0x200);
	594	membank("bank4")->set_base((m_ram_bottom > 0x400 ? m_memory : m_ram_ptr) + 0x400);
	595	membank("bank5")->set_base((m_ram_bottom > 0x1000 ? m_memory : m_ram_ptr) + 0x1000);
	596	membank("bank6")->set_base((m_ram_bottom > 0x2000 ? m_memory : m_ram_ptr) + 0x2000);
625	597
626	598	if (MMU_RAM_LO)
627	599	{
628		membank("bank7")->set_base(m_ram + 0x4000);
	600	membank("bank7")->set_base(m_ram_ptr + 0x4000);
629	601	}
630	602	else
631	603	{
r17778	r17779
634	606
635	607	if (MMU_RAM_MID)
636	608	{
637		membank("bank8")->set_base(m_ram + 0x8000);
638		membank("bank9")->set_base(m_ram + 0xa000);
	609	membank("bank8")->set_base(m_ram_ptr + 0x8000);
	610	membank("bank9")->set_base(m_ram_ptr + 0xa000);
639	611	}
640	612	else if (MMU_ROM_MID)
641	613	{
r17778	r17779
678	650	{
679	651	if (m_ram_top > 0xc000)
680	652	{
681		membank("bank12")->set_base(m_ram + 0xc000);
	653	membank("bank12")->set_base(m_ram_ptr + 0xc000);
682	654	}
683	655	else
684	656	{
r17778	r17779
688	660	{
689	661	if (m_ram_top > 0xd000)
690	662	{
691		membank("bank13")->set_base(m_ram + 0xd000);
	663	membank("bank13")->set_base(m_ram_ptr + 0xd000);
692	664	}
693	665	else
694	666	{
r17778	r17779
697	669	}
698	670	if (m_ram_top > 0xe000)
699	671	{
700		membank("bank14")->set_base(m_ram + 0xe000);
	672	membank("bank14")->set_base(m_ram_ptr + 0xe000);
701	673	}
702	674	else
703	675	{
r17778	r17779
705	677	}
706	678	if (m_ram_top > 0xff05)
707	679	{
708		membank("bank16")->set_base(m_ram + 0xff05);
	680	membank("bank16")->set_base(m_ram_ptr + 0xff05);
709	681	}
710	682	else
711	683	{
r17778	r17779
742	714
743	715	if ( (( (ioport("SPECIAL")->read() & 0x06) == 0x02 ) && (MMU_RAM_ADDR >= 0x40000))
744	716	|| (( (ioport("SPECIAL")->read() & 0x06) == 0x00) && (MMU_RAM_ADDR >= 0x20000)) )
745		m_ram = NULL;
	717	m_ram_ptr = NULL;
746	718	}
747	719	}
748	720
r17778	r17779
918	890
919	891	WRITE8_MEMBER( c128_state::write_0000 )
920	892	{
921		if (m_ram != NULL)
922		m_ram[0x0000 + offset] = data;
	893	if (m_ram_ptr != NULL)
	894	m_ram_ptr[0x0000 + offset] = data;
923	895	}
924	896
925	897	WRITE8_MEMBER( c128_state::write_1000 )
926	898	{
927		if (m_ram != NULL)
928		m_ram[0x1000 + offset] = data;
	899	if (m_ram_ptr != NULL)
	900	m_ram_ptr[0x1000 + offset] = data;
929	901	}
930	902
931	903	WRITE8_MEMBER( c128_state::write_4000 )
932	904	{
933		if (m_ram != NULL)
934		m_ram[0x4000 + offset] = data;
	905	if (m_ram_ptr != NULL)
	906	m_ram_ptr[0x4000 + offset] = data;
935	907	}
936	908
937	909	WRITE8_MEMBER( c128_state::write_8000 )
938	910	{
939		if (m_ram != NULL)
940		m_ram[0x8000 + offset] = data;
	911	if (m_ram_ptr != NULL)
	912	m_ram_ptr[0x8000 + offset] = data;
941	913	}
942	914
943	915	WRITE8_MEMBER( c128_state::write_a000 )
944	916	{
945		if (m_ram != NULL)
946		m_ram[0xa000 + offset] = data;
	917	if (m_ram_ptr != NULL)
	918	m_ram_ptr[0xa000 + offset] = data;
947	919	}
948	920
949	921	WRITE8_MEMBER( c128_state::write_c000 )
950	922	{
951		if (m_ram != NULL)
952		m_ram[0xc000 + offset] = data;
	923	if (m_ram_ptr != NULL)
	924	m_ram_ptr[0xc000 + offset] = data;
953	925	}
954	926
955	927	WRITE8_MEMBER( c128_state::write_e000 )
956	928	{
957	929	if (offset + 0xe000 >= m_ram_top)
958	930	m_memory[0xe000 + offset] = data;
959		else if (m_ram != NULL)
960		m_ram[0xe000 + offset] = data;
	931	else if (m_ram_ptr != NULL)
	932	m_ram_ptr[0xe000 + offset] = data;
961	933	}
962	934
963	935	WRITE8_MEMBER( c128_state::write_ff00 )
964	936	{
965	937	if (!m_c64mode)
966	938	mmu8722_ff00_w(space, offset, data);
967		else if (m_ram!=NULL)
	939	else if (m_ram_ptr!=NULL)
968	940	m_memory[0xff00 + offset] = data;
969	941	}
970	942
r17778	r17779
972	944	{
973	945	if (offset + 0xff05 >= m_ram_top)
974	946	m_memory[0xff05 + offset] = data;
975		else if (m_ram!=NULL)
976		m_ram[0xff05 + offset] = data;
	947	else if (m_ram_ptr!=NULL)
	948	m_ram_ptr[0xff05 + offset] = data;
977	949	}
978	950
979	951	/*

trunk/src/mess/machine/mos8722.c

r17778	r17779
55	55	#define CR_ROM_LO      BIT(m_reg[CR], 1)
56	56	#define CR_ROM_MID      ((m_reg[CR] >> 2) & 0x03)
57	57	#define CR_ROM_HI      ((m_reg[CR] >> 4) & 0x03)
58		#define CR_A16         BIT(m_reg[CR], 6)
	58	#define CR_RAM         ((m_reg[CR] >> 6) & 0x03)
59	59
60	60
61	61	// mode configuration register
r17778	r17779
68	68
69	69
70	70	// RAM configuration register
	71	static const offs_t RCR_BOTTOM_ADDRESS[4] = { 0x0400, 0x1000, 0x0400, 0x1000 };
	72	static const offs_t RCR_TOP_ADDRESS[4] =    { 0xf000, 0xf000, 0xe000, 0xc000 };
	73
71	74	enum
72	75	{
73		RCR_STATUS_NO = 0,
74		RCR_STATUS_BOTTOM,
75		RCR_STATUS_TOP,
76		RCR_STATUS_BOTH
	76	RCR_SHARE_1K = 0,
	77	RCR_SHARE_4K,
	78	RCR_SHARE_8K,
	79	RCR_SHARE_16K
77	80	};
78	81
79	82	#define RCR_SHARE      (m_reg[RCR] & 0x03)
80		#define RCR_STATUS      ((m_reg[RCR] >> 2) & 0x03)
81		#define RCR_A16         BIT(m_reg[RCR], 6)
	83	#define RCR_BOTTOM      BIT(m_reg[RCR], 2)
	84	#define RCR_TOP         BIT(m_reg[RCR], 3)
	85	#define RCR_VA16      BIT(m_reg[RCR], 6)
82	86
83	87
	88	// page 0 pointer register
	89	#define P0H_A16         BIT(m_reg[P0H], 0)
84	90
	91
	92	// page 1 pointer register
	93	#define P1H_A16         BIT(m_reg[P1H], 0)
	94
	95
	96
85	97	//**************************************************************************
86	98	//  DEVICE DEFINITIONS
87	99	//**************************************************************************
r17778	r17779
149	161
150	162	void mos8722_device::device_reset()
151	163	{
	164	for (int i = 0; i < 12; i++)
	165	{
	166	m_reg[i] = 0;
	167	}
	168
	169	m_p0l_written = false;
	170	m_p1l_written = false;
152	171	}
153	172
154	173
r17778	r17779
156	175	//  read - register read
157	176	//-------------------------------------------------
158	177
159		READ8_MEMBER( mos8722_device::read )
	178	UINT8 mos8722_device::read(offs_t offset, UINT8 data)
160	179	{
161		UINT8 data = 0;
162
163	180	if (!MCR_C64)
164	181	{
	182	if (!CR_IO && offset >= 0xd500 && offset < 0xd50c)
	183	{
	184	switch (offset & 0x0f)
	185	{
	186	case MCR:
	187	data = m_reg[MCR] & 0x49;
165	188
	189	data |= m_in_game_func() << 4;
	190	data |= m_in_exrom_func() << 5;
	191	data |= m_in_sense40_func() << 7;
	192	break;
	193
	194	case VR:
	195	data = 0x20;
	196	break;
	197
	198	default:
	199	data = m_reg[offset & 0x0f];
	200	break;
	201	}
	202	}
	203	else if (offset == 0xff00)
	204	{
	205	return m_reg[CR];
	206	}
166	207	}
167	208
168	209	return data;
r17778	r17779
177	218	{
178	219	if (!MCR_C64)
179	220	{
	221	if (!CR_IO && offset >= 0xd500 && offset < 0xd50c)
	222	{
	223	m_reg[offset & 0x0f] = data;
180	224
	225	switch (offset & 0x0f)
	226	{
	227	case MCR:
	228	m_out_z80en_func(MCR_8500);
	229	m_out_fsdir_func(MCR_FSDIR);
	230	break;
	231
	232	case P0L:
	233	m_p0l_written = true;
	234	break;
	235
	236	case P0H:
	237	m_p0l_written = false;
	238	break;
	239
	240	case P1L:
	241	m_p1l_written = true;
	242	break;
	243
	244	case P1H:
	245	m_p1l_written = false;
	246	break;
	247	}
	248	}
	249	else if (offset >= 0xff00 && offset < 0xff05)
	250	{
	251	switch (offset & 0x0f)
	252	{
	253	case CR:
	254	m_reg[CR] = data;
	255	break;
	256
	257	default:
	258	m_reg[CR] = m_reg[offset & 0x0f];
	259	break;
	260	}
	261	}
181	262	}
182	263	}
183	264
r17778	r17779
196	277	//  ta_r - translated address read
197	278	//-------------------------------------------------
198	279
199		offs_t mos8722_device::ta_r(offs_t offset, int aec, int *ms0, int *ms1, int *ms2, int *ms3)
	280	offs_t mos8722_device::ta_r(offs_t offset, int aec, int *ms0, int *ms1, int *ms2, int *ms3, int *cas0, int *cas1)
200	281	{
201	282	offs_t ta = offset;
202	283
203		if (aec)
	284	if (!MCR_C64)
204	285	{
205		if (MCR_C64)
	286	*ms0 = 1;
	287	*ms1 = 1;
	288	*ms2 = CR_IO;
	289
	290	if (offset < 0x1000 && !MCR_8500)
206	291	{
207		*ms0 = 1;
208		*ms1 = 1;
	292	ta = 0xd000 | (offset & 0xfff);
	293
	294	*ms0 = 0;
	295	*ms1 = 0;
209	296	}
	297	else if (offset >= 0x4000 && offset < 0x8000)
	298	{
	299	*ms0 = CR_ROM_LO;
	300	*ms1 = CR_ROM_LO;
	301	}
	302	else if (offset >= 0x8000 && offset < 0xc000)
	303	{
	304	*ms0 = BIT(CR_ROM_MID, 0);
	305	*ms1 = BIT(CR_ROM_MID, 1);
	306	}
	307	else if (offset >= 0xc000)
	308	{
	309	*ms0 = BIT(CR_ROM_HI, 0);
	310	*ms1 = BIT(CR_ROM_HI, 1);
	311	}
210	312
211		*ms3 = !MCR_C64;
	313	if (*ms0 == 1 && *ms1 == 1)
	314	{
	315	if (aec)
	316	{
	317	*cas0 = BIT(CR_RAM, 0);
	318	*cas1 = BIT(CR_RAM, 1);
	319
	320	if (offset < 0x0100)
	321	{
	322	if (m_p0l_written && m_reg[P0L])
	323	{
	324	ta = (m_reg[P0L] << 8) | (offset & 0xff);
	325
	326	*cas0 = P0H_A16 ? 1 : 0;
	327	*cas1 = P0H_A16 ? 0 : 1;
	328	}
	329	}
	330	else if (offset < 0x0200)
	331	{
	332	if (m_p1l_written && m_reg[P1L])
	333	{
	334	ta = (m_reg[P1L] << 8) | (offset & 0xff);
	335
	336	*cas0 = P1H_A16 ? 1 : 0;
	337	*cas1 = P1H_A16 ? 0 : 1;
	338	}
	339	}
	340
	341	if ((RCR_BOTTOM && offset < RCR_BOTTOM_ADDRESS[RCR_SHARE]) ||
	342	(RCR_TOP && offset >= RCR_TOP_ADDRESS[RCR_SHARE]))
	343	{
	344	*cas0 = 0;
	345	*cas1 = 1;
	346	}
	347	}
	348	else
	349	{
	350	*cas0 = RCR_VA16 ? 1 : 0;
	351	*cas1 = RCR_VA16 ? 0 : 1;
	352	}
	353	}
	354	else
	355	{
	356	*cas0 = 1;
	357	*cas1 = 1;
	358	}
212	359	}
	360	else
	361	{
	362	*ms0 = 1;
	363	*ms1 = 1;
	364	*ms2 = 1;
213	365
	366	*cas0 = 0;
	367	*cas1 = 1;
	368	}
	369
	370	*ms3 = !MCR_C64;
	371
214	372	return ta;
215	373	}

trunk/src/mess/machine/mos8722.h

r17778	r17779
82	82	// construction/destruction
83	83	mos8722_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
84	84
85		DECLARE_READ8_MEMBER( read );
	85	UINT8 read(offs_t offset, UINT8 data);
86	86	DECLARE_WRITE8_MEMBER( write );
87	87
88	88	DECLARE_READ_LINE_MEMBER( fsdir_r );
89	89
90		offs_t ta_r(offs_t offset, int aec, int *ms0, int *ms1, int *ms2, int *ms3);
	90	offs_t ta_r(offs_t offset, int aec, int *ms0, int *ms1, int *ms2, int *ms3, int *cas0, int *cas1);
91	91
92	92	protected:
93	93	// device-level overrides
r17778	r17779
103	103	devcb_resolved_read_line   m_in_sense40_func;
104	104
105	105	UINT8 m_reg[10];
	106
	107	bool m_p0l_written;
	108	bool m_p1l_written;
106	109	};
107	110
108	111

trunk/src/mess/machine/c1571.c

r17778	r17779
491	491
492	492	static MOS6526_INTERFACE( cia_intf )
493	493	{
494		0,
495	494	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, base_c1571_device, cia_irq_w),
496	495	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, base_c1571_device, cia_pc_w),
497	496	DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF_OWNER, base_c1571_device, cia_cnt_w),
r17778	r17779
603	602
604	603	MCFG_VIA6522_ADD(M6522_0_TAG, XTAL_16MHz/16, via0_intf)
605	604	MCFG_VIA6522_ADD(M6522_1_TAG, XTAL_16MHz/16, via1_intf)
606		MCFG_MOS6526R1_ADD(M6526_TAG, XTAL_16MHz/16, cia_intf)
	605	MCFG_MOS6526R1_ADD(M6526_TAG, XTAL_16MHz/16, 0, cia_intf)
607	606	MCFG_WD1770_ADD(WD1770_TAG, /* XTAL_16MHz/2, */ fdc_intf)
608	607
609	608	MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, c1571_floppy_interface)
r17778	r17779
622	621
623	622	MCFG_VIA6522_ADD(M6522_0_TAG, XTAL_16MHz/16, via0_intf)
624	623	MCFG_VIA6522_ADD(M6522_1_TAG, XTAL_16MHz/16, via1_intf)
625		MCFG_MOS6526R1_ADD(M6526_TAG, XTAL_16MHz/16, cia_intf)
	624	MCFG_MOS6526R1_ADD(M6526_TAG, XTAL_16MHz/16, 0, cia_intf)
626	625	MCFG_WD1770_ADD(WD1770_TAG, /* XTAL_16MHz/2, */ fdc_intf)
627	626
628	627	MCFG_LEGACY_FLOPPY_DRIVE_ADD(FLOPPY_0, c1570_floppy_interface)

trunk/src/mess/includes/c65.h

r17778	r17779
85	85	MACHINE_START( c65 );
86	86	INTERRUPT_GEN( c65_frame_interrupt );
87	87
88		extern const mos6526_interface c65_ntsc_cia0, c65_pal_cia0;
89		extern const mos6526_interface c65_ntsc_cia1, c65_pal_cia1;
	88	extern const mos6526_interface c65_cia0;
	89	extern const mos6526_interface c65_cia1;
90	90
91	91	#endif /* C65_H_ */

trunk/src/mess/includes/c128.h

r17778	r17779
63	63	m_cia1(*this, MOS6526_1_TAG),
64	64	m_cia2(*this, MOS6526_2_TAG),
65	65	//m_iec(*this, CBM_IEC_TAG),
66		//m_joy1(*this, CONTROL1_TAG),
67		//m_joy2(*this, CONTROL2_TAG),
68		//m_exp(*this, C128_EXPANSION_SLOT_TAG),
69		//m_user(*this, C128_USER_PORT_TAG),
70		//m_ram(*this, RAM_TAG),
71		m_cassette(*this, PET_DATASSETTE_PORT_TAG)
	66	m_joy1(*this, CONTROL1_TAG),
	67	m_joy2(*this, CONTROL2_TAG),
	68	m_exp(*this, C64_EXPANSION_SLOT_TAG),
	69	m_user(*this, C64_USER_PORT_TAG),
	70	m_ram(*this, RAM_TAG),
	71	m_cassette(*this, PET_DATASSETTE_PORT_TAG),
	72	m_rom1(NULL),
	73	m_rom2(NULL),
	74	m_rom3(NULL),
	75	m_rom4(NULL),
	76	m_from(NULL),
	77	m_charom(NULL)
72	78	{ }
73	79
74	80	required_device<legacy_cpu_device> m_maincpu;
r17778	r17779
80	86	required_device<mos6526_device> m_cia1;
81	87	required_device<mos6526_device> m_cia2;
82	88	//required_device<cbm_iec_device> m_iec;
83		//required_device<vcs_control_port_device> m_joy1;
84		//required_device<vcs_control_port_device> m_joy2;
85		//required_device<c64_expansion_slot_device> m_exp;
86		//required_device<c64_user_port_device> m_user;
87		//required_device<ram_device> m_ram;
	89	required_device<vcs_control_port_device> m_joy1;
	90	required_device<vcs_control_port_device> m_joy2;
	91	required_device<c64_expansion_slot_device> m_exp;
	92	required_device<c64_user_port_device> m_user;
	93	required_device<ram_device> m_ram;
88	94	required_device<pet_datassette_port_device> m_cassette;
89	95
90	96	virtual void machine_start();
91	97	virtual void machine_reset();
92	98
93		void bankswitch_pla(offs_t offset, int ba, int rw, int aec, int z80io, int ma5, int ma4, int ms3, int ms2, int ms1, int ms0,
	99	void bankswitch_pla(offs_t offset, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
94	100	int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic, int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb);
95		UINT8 read_memory(offs_t offset, int ba, int aec, int z80io);
96		void write_memory(offs_t offset, UINT8 data, int ba, int aec, int z80io);
	101	UINT8 read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io);
	102	void write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io);
97	103
98	104	DECLARE_READ8_MEMBER( z80_r );
99	105	DECLARE_WRITE8_MEMBER( z80_w );
r17778	r17779
165	171	void bankswitch(int reset);
166	172	void mmu8722_reset();
167	173
	174	const UINT8 *m_rom1;
	175	const UINT8 *m_rom2;
	176	const UINT8 *m_rom3;
	177	const UINT8 *m_rom4;
	178	const UINT8 *m_from;
	179	const UINT8 *m_charom;
	180	UINT8 *m_color_ram;
	181
168	182	UINT8 *m_c128_basic;
169	183	UINT8 *m_c128_kernal;
170	184	UINT8 *m_c128_chargen;
r17778	r17779
181	195	int m_write_io;
182	196	int m_ram_bottom;
183	197	int m_ram_top;
184		UINT8 *m_ram;
	198	UINT8 *m_ram_ptr;
185	199	UINT8 m_c64_port_data;
186	200	UINT8 m_keyline[3];
187	201	int m_cnt1;
r17778	r17779
204	218
205	219	extern INTERRUPT_GEN( c128_frame_interrupt );
206	220
207		extern const mos6526_interface c128_ntsc_cia0, c128_pal_cia0;
208		extern const mos6526_interface c128_ntsc_cia1, c128_pal_cia1;
	221	extern const mos6526_interface c128_cia1_intf, c128_cia2_intf;
209	222
210	223	#endif /* __C128_H__ */

trunk/src/mess/includes/vic10.h

r17778	r17779
40	40
41	41	required_device<cpu_device> m_maincpu;
42	42	required_device<mos6566_device> m_vic;
43		required_device<device_t> m_sid;
	43	required_device<sid6581_device> m_sid;
44	44	required_device<mos6526_device> m_cia;
45	45	required_device<vic10_expansion_slot_device> m_exp;
46	46	required_device<ram_device> m_ram;

trunk/src/mess/drivers/c65.c

r17778	r17779
337	337	MCFG_QUICKLOAD_ADD("quickload", cbm_c65, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
338	338
339	339	/* cia */
340		MCFG_MOS6526R1_ADD("cia_0", 3500000, c65_ntsc_cia0)
341		MCFG_MOS6526R1_ADD("cia_1", 3500000, c65_ntsc_cia1)
	340	MCFG_MOS6526R1_ADD("cia_0", 3500000, 60, c65_cia0)
	341	MCFG_MOS6526R1_ADD("cia_1", 3500000, 60, c65_cia1)
342	342
343	343	/* floppy from serial bus */
344	344	MCFG_CBM_IEC_ADD(cbm_iec_intf, NULL)
r17778	r17779
371	371	/* cia */
372	372	MCFG_DEVICE_REMOVE("cia_0")
373	373	MCFG_DEVICE_REMOVE("cia_1")
374		MCFG_MOS6526R1_ADD("cia_0", 3500000, c65_pal_cia0)
375		MCFG_MOS6526R1_ADD("cia_1", 3500000, c65_pal_cia1)
	374	MCFG_MOS6526R1_ADD("cia_0", 3500000, 50, c65_cia0)
	375	MCFG_MOS6526R1_ADD("cia_1", 3500000, 50, c65_cia1)
376	376	MACHINE_CONFIG_END
377	377
378	378

trunk/src/mess/drivers/cbmb.c

r17778	r17779
137	137	AM_RANGE(0xfd800, 0xfd800) AM_MIRROR(0xfe) AM_DEVWRITE("crtc", mc6845_device, address_w)
138	138	AM_RANGE(0xfd801, 0xfd801) AM_MIRROR(0xfe) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
139	139	/* disk units */
140		AM_RANGE(0xfda00, 0xfdaff) AM_DEVREADWRITE_LEGACY("sid6581", sid6581_r, sid6581_w)
	140	AM_RANGE(0xfda00, 0xfdaff) AM_DEVREADWRITE("sid6581", sid6581_device, read, write)
141	141	/* db00 coprocessor */
142	142	AM_RANGE(0xfdc00, 0xfdcff) AM_DEVREADWRITE_LEGACY("cia", mos6526_r, mos6526_w)
143	143	/* dd00 acia */
r17778	r17779
164	164	AM_RANGE(0xfd400, 0xfd7ff) AM_RAM_WRITE(cbmb_colorram_w) AM_SHARE("colorram")      /* colorram */
165	165	AM_RANGE(0xfd800, 0xfd8ff) AM_DEVREADWRITE("vic6567", mos6566_device, read, write)
166	166	/* disk units */
167		AM_RANGE(0xfda00, 0xfdaff) AM_DEVREADWRITE_LEGACY("sid6581", sid6581_r, sid6581_w)
	167	AM_RANGE(0xfda00, 0xfdaff) AM_DEVREADWRITE("sid6581", sid6581_device, read, write)
168	168	/* db00 coprocessor */
169	169	AM_RANGE(0xfdc00, 0xfdcff) AM_DEVREADWRITE_LEGACY("cia", mos6526_r, mos6526_w)
170	170	/* dd00 acia */
r17778	r17779
450	450	MCFG_QUICKLOAD_ADD("quickload", cbmb, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
451	451
452	452	/* cia */
453		MCFG_MOS6526R1_ADD("cia", 7833600, cbmb_cia)
	453	MCFG_MOS6526R1_ADD("cia", 7833600, 60, cbmb_cia)
454	454
455	455	/* tpi */
456	456	MCFG_TPI6525_ADD("tpi6525_0", cbmb_tpi_0_intf)
r17778	r17779
515	515	MCFG_QUICKLOAD_ADD("quickload", p500, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
516	516
517	517	/* cia */
518		MCFG_MOS6526R1_ADD("cia", VIC6567_CLOCK, cbmb_cia)
	518	MCFG_MOS6526R1_ADD("cia", VIC6567_CLOCK, 60, cbmb_cia)
519	519
520	520	/* tpi */
521	521	MCFG_TPI6525_ADD("tpi6525_0", cbmb_tpi_0_intf)

trunk/src/mess/drivers/c128.c

r17778	r17779
169	169	to use an EEPROM reader, in order to obtain a dump of the whole content.
170	170	*/
171	171
	172	/*
172	173
	174	TODO:
	175
	176	- connect to PLA
	177	- clean up ROMs
	178	- wire up function ROM softlist
	179	- remove banking code from machine/c128.h
	180	- inherit from c64_state and use common members from there
	181	- clean up inputs
	182	- fix fast serial
	183
	184	*/
	185
173	186	#include "emu.h"
174	187	#include "cpu/z80/z80.h"
175	188	#include "cpu/m6502/m6502.h"
r17778	r17779
212	225	* 0xe000-0xffff ram as bank 0
213	226	*/
214	227
215		void c128_state::bankswitch_pla(offs_t offset, int ba, int rw, int aec, int z80io, int ma5, int ma4, int ms3, int ms2, int ms1, int ms0,
216		int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic, int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb)
	228	void c128_state::bankswitch_pla(offs_t offset, offs_t vma, int ba, int rw, int aec, int z80io, int ms3, int ms2, int ms1, int ms0,
	229	int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic,
	230	int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb)
217	231	{
218	232	//int game = m_exp->game_r(offset, ba, rw, m_hiram);
219	233	//int exrom = m_exp->exrom_r(offset, ba, rw, m_hiram);
r17778	r17779
221	235	//int _128_256 = 1;
222	236	}
223	237
224		UINT8 c128_state::read_memory(offs_t offset, int ba, int aec, int z80io)
	238	UINT8 c128_state::read_memory(address_space &space, offs_t offset, offs_t vma, int ba, int aec, int z80io)
225	239	{
226		int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1;
227		//offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3);
228		int cas, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic, from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb;
229		//int io1 = 1, io2 = 1;
	240	int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1;
	241	int cas = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1,
	242	from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1;
	243	int io1 = 1, io2 = 1;
230	244
231		bankswitch_pla(offset, ba, rw, aec, z80io, 0, 0, ms3, ms2, ms1, ms0,
232		&cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
	245	offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3, &cas0, &cas1);
233	246
	247	bankswitch_pla(offset, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
	248	&cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
	249	&from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
	250
234	251	UINT8 data = 0xff;
235	252
236	253	if (ba)
r17778	r17779
238	255	data = m_vic->bus_r();
239	256	}
240	257
241		if (!cas)
	258	if (!casenb)
242	259	{
243
	260	if (!cas0)
	261	{
	262	data = m_ram->pointer()[(ta & 0xff00) | (offset & 0xff)];
	263	}
	264	else if (!cas1)
	265	{
	266	data = m_ram->pointer()[0x10000 | (ta & 0xff00) | (offset & 0xff)];
	267	}
244	268	}
245	269	else if (!rom1)
246	270	{
247
	271	if (m_rom3)
	272	{
	273	data = m_rom1[((BIT(ta, 14) && BIT(offset, 13)) << 13) | (ta & 0x1000) | (offset & 0xfff)];
	274	}
	275	else
	276	{
	277	data = m_rom1[(ms3 << 14) | ((BIT(ta, 14) && BIT(offset, 13)) << 13) | (ta & 0x1000) | (offset & 0xfff)];
	278	}
248	279	}
249		else if (!rom2)
	280	else if (!rom2 && m_rom3)
250	281	{
251
	282	data = m_rom2[offset & 0x3fff];
252	283	}
253	284	else if (!rom3)
254	285	{
255
	286	if (m_rom3)
	287	{
	288	data = m_rom3[offset & 0x3fff];
	289	}
	290	else
	291	{
	292	data = m_rom2[(BIT(offset, 15) << 14) | (offset & 0x3fff)];
	293	}
256	294	}
257		else if (!rom4)
	295	else if (!rom4 && m_rom3)
258	296	{
259
	297	data = m_rom4[(ta & 0x1000) | (offset & 0x2fff)];
260	298	}
261	299	else if (!charom)
262	300	{
263
	301	data = m_charom[(ms3 << 12) | (ta & 0xf00) | (offset & 0xff)];
264	302	}
265	303	else if (!colorram)
266	304	{
267
	305	data = m_color_ram[(clrbank << 10) | (ta & 0x300) | (offset & 0xff)] & 0x0f;
268	306	}
269	307	else if (!vic)
270	308	{
271
	309	data = m_vic->read(space, offset & 0x3f);
272	310	}
273	311	else if (!from1)
274	312	{
275
	313	data = m_from[offset & 0x7fff];
276	314	}
277		else if (!iocs)
	315	else if (!iocs && BIT(offset, 10))
278	316	{
279		switch (offset)
	317	switch ((BIT(offset, 11) << 2) | ((offset >> 8) & 0x03))
280	318	{
281	319	case 0: // SID
	320	data = m_sid->read(space, offset & 0x1f);
282	321	break;
283	322
284	323	case 2: // CS8563
	324	if BIT(offset, 0)
	325	{
	326	data = m_vdc->register_r(space, 0);
	327	}
	328	else
	329	{
	330	data = m_vdc->status_r(space, 0);
	331	}
285	332	break;
286	333
287	334	case 4: // CIA1
	335	data = m_cia1->read(space, offset & 0x0f);
288	336	break;
289	337
290	338	case 5: // CIA2
	339	data = m_cia2->read(space, offset & 0x0f);
291	340	break;
292	341
293	342	case 6: // I/O1
	343	io1 = 0;
294	344	break;
295	345
296	346	case 7: // I/O2
	347	io2 = 0;
297	348	break;
298	349	}
299	350	}
300	351
301		return data;//m_exp->cd_r(space, offset, data, ba, roml, romh, io1, io2);
	352	data = m_exp->cd_r(space, ta, data, ba, roml, romh, io1, io2);
	353
	354	return m_mmu->read(offset, data);
302	355	}
303	356
304		void c128_state::write_memory(offs_t offset, UINT8 data, int ba, int aec, int z80io)
	357	void c128_state::write_memory(address_space &space, offs_t offset, offs_t vma, UINT8 data, int ba, int aec, int z80io)
305	358	{
306		int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1;
307		//offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3);
308		int cas, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic, from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb;
309		//int io1 = 1, io2 = 1;
	359	int rw = 0, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1, cas0 = 1, cas1 = 1;
	360	int cas = 1, gwe = 1, rom1 = 1, rom2 = 1, rom3 = 1, rom4 = 1, charom = 1, colorram = 1, vic = 1,
	361	from1 = 1, romh = 1, roml = 1, dwe = 1, ioacc = 1, clrbank = 1, iocs = 1, casenb = 1;
	362	int io1 = 1, io2 = 1;
310	363
311		bankswitch_pla(offset, ba, rw, aec, z80io, 0, 0, ms3, ms2, ms1, ms0,
312		&cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
	364	offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3, &cas0, &cas1);
313	365
314		if (!cas)
315		{
	366	bankswitch_pla(offset, vma, ba, rw, aec, z80io, ms3, ms2, ms1, ms0,
	367	&cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic,
	368	&from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
316	369
317		}
318		else if (!gwe)
	370	if (!casenb && !dwe)
319	371	{
320
	372	if (!cas0)
	373	{
	374	m_ram->pointer()[(ta & 0xff00) | (offset & 0xff)] = data;
	375	}
	376	else if (!cas1)
	377	{
	378	m_ram->pointer()[0x10000 | (ta & 0xff00) | (offset & 0xff)] = data;
	379	}
321	380	}
322		else if (!rom1)
	381	else if (!colorram && !gwe)
323	382	{
324
	383	m_color_ram[(clrbank << 10) | (ta & 0x300) | (offset & 0xff)] = data | 0xf0;
325	384	}
326		else if (!rom2)
	385	else if (!vic)
327	386	{
328
	387	m_vic->write(space, offset & 0x3f, data);
329	388	}
330		else if (!rom3)
	389	else if (!iocs && BIT(offset, 10))
331	390	{
	391	switch ((BIT(offset, 11) << 2) | ((offset >> 8) & 0x03))
	392	{
	393	case 0: // SID
	394	m_sid->write(space, offset & 0x1f, data);
	395	break;
332	396
333		}
334		else if (!rom4)
335		{
	397	case 2: // CS8563
	398	if BIT(offset, 0)
	399	{
	400	m_vdc->register_w(space, 0, data);
	401	}
	402	else
	403	{
	404	m_vdc->address_w(space, 0, data);
	405	}
	406	break;
336	407
337		}
338		else if (!charom)
339		{
	408	case 4: // CIA1
	409	m_cia1->write(space, offset & 0x0f, data);
	410	break;
340	411
341		}
342		else if (!colorram)
343		{
	412	case 5: // CIA2
	413	m_cia2->write(space, offset & 0x0f, data);
	414	break;
344	415
345		}
346		else if (!vic)
347		{
	416	case 6: // I/O1
	417	io1 = 0;
	418	break;
348	419
	420	case 7: // I/O2
	421	io2 = 0;
	422	break;
	423	}
349	424	}
350		else if (!from1)
351		{
352	425
353		}
354		else if (!dwe)
355		{
	426	m_exp->cd_w(space, ta, data, ba, roml, romh, io1, io2);
356	427
357		}
358		else if (!iocs)
359		{
360
361		}
362
363		//m_exp->cd_w(space, offset, data, ba, roml, romh, io1, io2);
	428	m_mmu->write(space, offset, data);
364	429	}
365	430
366	431	READ8_MEMBER( c128_state::z80_r )
367	432	{
368	433	int ba = 1, aec = 1, z80io = 1;
	434	offs_t vma = 0;
369	435
370		return read_memory(offset, ba, aec, z80io);
	436	return read_memory(space, offset, vma, ba, aec, z80io);
371	437	}
372	438
373	439	WRITE8_MEMBER( c128_state::z80_w )
374	440	{
375	441	int ba = 1, aec = 1, z80io = 1;
	442	offs_t vma = 0;
376	443
377		write_memory(offset, data, ba, aec, z80io);
	444	write_memory(space, offset, vma, data, ba, aec, z80io);
378	445	}
379	446
380	447	READ8_MEMBER( c128_state::z80_io_r )
381	448	{
382	449	int ba = 1, aec = 1, z80io = 0;
	450	offs_t vma = 0;
383	451
384		return read_memory(offset, ba, aec, z80io);
	452	return read_memory(space, offset, vma, ba, aec, z80io);
385	453	}
386	454
387	455	WRITE8_MEMBER( c128_state::z80_io_w )
388	456	{
389	457	int ba = 1, aec = 1, z80io = 0;
	458	offs_t vma = 0;
390	459
391		write_memory(offset, data, ba, aec, z80io);
	460	write_memory(space, offset, vma, data, ba, aec, z80io);
392	461	}
393	462
394	463	READ8_MEMBER( c128_state::read )
395	464	{
396	465	int ba = 1, aec = 1, z80io = 1;
	466	offs_t vma = 0;
397	467
398		return read_memory(offset, ba, aec, z80io);
	468	return read_memory(space, vma, offset, ba, aec, z80io);
399	469	}
400	470
401	471	WRITE8_MEMBER( c128_state::write )
402	472	{
403	473	int ba = 1, aec = 1, z80io = 1;
	474	offs_t vma = 0;
404	475
405		write_memory(offset, data, ba, aec, z80io);
	476	write_memory(space, offset, vma, data, ba, aec, z80io);
406	477	}
407	478
408	479	READ8_MEMBER( c128_state::vic_videoram_r )
409	480	{
410	481	int ba = 0, aec = 0, z80io = 1;
	482	offs_t vma = 0;
411	483
412		return read_memory(offset, ba, aec, z80io);
	484	return read_memory(space, offset, vma, ba, aec, z80io);
413	485	}
414	486
415	487
r17778	r17779
436	508	static ADDRESS_MAP_START( z80_io, AS_IO, 8, c128_state )
437	509	AM_RANGE(0x1000, 0x13ff) AM_READWRITE_LEGACY(c64_colorram_read, c64_colorram_write)
438	510	AM_RANGE(0xd000, 0xd3ff) AM_DEVREADWRITE(MOS8564_TAG, mos6566_device, read, write)
439		AM_RANGE(0xd400, 0xd4ff) AM_DEVREADWRITE_LEGACY(MOS6581_TAG, sid6581_r, sid6581_w)
	511	AM_RANGE(0xd400, 0xd4ff) AM_DEVREADWRITE(MOS6581_TAG, sid6581_device, read, write)
440	512	AM_RANGE(0xd500, 0xd5ff) AM_READWRITE(mmu8722_port_r, mmu8722_port_w)
441		//AM_RANGE(0xd600, 0xd7ff) AM_DEVREADWRITE_LEGACY(MOS8563_TAG, vdc8563_port_r, vdc8563_port_w)
442	513	AM_RANGE(0xd600, 0xd600) AM_MIRROR(0x1fe) AM_DEVREADWRITE(MOS8563_TAG, mos8563_device, status_r, address_w)
443	514	AM_RANGE(0xd601, 0xd601) AM_MIRROR(0x1fe) AM_DEVREADWRITE(MOS8563_TAG, mos8563_device, register_r, register_w)
444	515	AM_RANGE(0xdc00, 0xdcff) AM_DEVREADWRITE_LEGACY(MOS6526_1_TAG, mos6526_r, mos6526_w)
r17778	r17779
749	820
750	821	WRITE_LINE_MEMBER( c128_state::mmu_z80en_w )
751	822	{
752
	823	if (state)
	824	{
	825	m_maincpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	826	m_subcpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	827	}
	828	else
	829	{
	830	m_maincpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
	831	m_subcpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
	832	}
753	833	}
754	834
755	835	WRITE_LINE_MEMBER( c128_state::mmu_fsdir_w )
756	836	{
757
758	837	}
759	838
760	839	READ_LINE_MEMBER( c128_state::mmu_game_r )
r17778	r17779
823	902	//  mc6845_interface vdc_intf
824	903	//-------------------------------------------------
825	904
826		static MC6845_UPDATE_ROW( vdc_update_row )
827		{
828		mos8563_device *mos8563 = static_cast<mos8563_device *>(device);
829
830		mos8563->update_row(bitmap, cliprect, ma, ra, y, x_count, cursor_x, param);
831		}
832
833	905	static const mc6845_interface vdc_intf =
834	906	{
835	907	SCREEN_VDC_TAG,
836	908	8,
837	909	NULL,
838		vdc_update_row,
839	910	NULL,
	911	NULL,
840	912	DEVCB_NULL,
841	913	DEVCB_NULL,
842	914	DEVCB_NULL,
r17778	r17779
846	918
847	919
848	920	//-------------------------------------------------
849		//  sid6581_interface sid_intf
	921	//  MOS6581_INTERFACE( sid_intf )
850	922	//-------------------------------------------------
851	923
852	924	READ8_MEMBER( c128_state::sid_potx_r )
853	925	{
854		return c64_paddle_read(m_sid, 0);
	926	UINT8 cia1_pa = mos6526_pa_r(m_cia1, 0);
	927
	928	int sela = BIT(cia1_pa, 6);
	929	int selb = BIT(cia1_pa, 7);
	930
	931	UINT8 data = 0;
	932
	933	if (sela) data = m_joy1->pot_x_r();
	934	if (selb) data = m_joy2->pot_x_r();
	935
	936	return data;
855	937	}
856	938
857	939	READ8_MEMBER( c128_state::sid_poty_r )
858	940	{
859		return c64_paddle_read(m_sid, 1);
	941	UINT8 cia1_pa = mos6526_pa_r(m_cia1, 0);
	942
	943	int sela = BIT(cia1_pa, 6);
	944	int selb = BIT(cia1_pa, 7);
	945
	946	UINT8 data = 0;
	947
	948	if (sela) data = m_joy1->pot_y_r();
	949	if (selb) data = m_joy2->pot_y_r();
	950
	951	return data;
860	952	}
861	953
862		static const sid6581_interface sid_intf =
	954	static MOS6581_INTERFACE( sid_intf )
863	955	{
864	956	DEVCB_DRIVER_MEMBER(c128_state, sid_potx_r),
865	957	DEVCB_DRIVER_MEMBER(c128_state, sid_poty_r)
r17778	r17779
880	972	0x20
881	973	};
882	974
	975
883	976	//-------------------------------------------------
884	977	//  CBM_IEC_INTERFACE( cbm_iec_intf )
885	978	//-------------------------------------------------
r17778	r17779
904	997	};
905	998
906	999
	1000	//-------------------------------------------------
	1001	//  C64_EXPANSION_INTERFACE( expansion_intf )
	1002	//-------------------------------------------------
907	1003
	1004	static C64_EXPANSION_INTERFACE( expansion_intf )
	1005	{
	1006	DEVCB_NULL,
	1007	DEVCB_NULL,
	1008	DEVCB_NULL,
	1009	DEVCB_NULL,
	1010	DEVCB_NULL,
	1011	DEVCB_NULL
	1012	};
	1013
	1014
	1015	//-------------------------------------------------
	1016	//  C64_USER_PORT_INTERFACE( user_intf )
	1017	//-------------------------------------------------
	1018
	1019	static C64_USER_PORT_INTERFACE( user_intf )
	1020	{
	1021	DEVCB_NULL,
	1022	DEVCB_NULL,
	1023	DEVCB_NULL,
	1024	DEVCB_NULL,
	1025	DEVCB_NULL,
	1026	DEVCB_NULL
	1027	};
	1028
	1029
908	1030	//**************************************************************************
909	1031	//  MACHINE DRIVERS
910	1032	//**************************************************************************
r17778	r17779
914	1036	//-------------------------------------------------
915	1037
916	1038	static MACHINE_CONFIG_START( ntsc, c128_state )
917		/* basic machine hardware */
	1039	// basic hardware
918	1040	MCFG_CPU_ADD(Z80A_TAG, Z80, VIC6567_CLOCK)
919	1041	MCFG_CPU_PROGRAM_MAP( z80_mem)
920	1042	MCFG_CPU_IO_MAP( z80_io)
921	1043	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
922		//MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6567_HRETRACERATE)
	1044	MCFG_QUANTUM_PERFECT_CPU(Z80A_TAG)
923	1045
924	1046	MCFG_CPU_ADD(M8502_TAG, M8502, VIC6567_CLOCK)
925	1047	MCFG_CPU_PROGRAM_MAP( m8502_mem)
926	1048	MCFG_CPU_CONFIG( cpu_intf )
927	1049	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
928		// MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6567_HRETRACERATE)
	1050	MCFG_QUANTUM_PERFECT_CPU(M8502_TAG)
929	1051
930		/* video hardware */
931		MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
	1052	// video hardware
	1053	MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, VIC6567_CLOCK*2, vdc_intf, vdc_videoram_map)
932	1054	MCFG_MOS8564_ADD(MOS8564_TAG, SCREEN_VIC_TAG, VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
933		MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map)
934	1055
935		/* sound hardware */
	1056	// sound hardware
936	1057	MCFG_SPEAKER_STANDARD_MONO("mono")
937	1058	MCFG_SOUND_ADD(MOS6581_TAG, SID6581, VIC6567_CLOCK)
938	1059	MCFG_SOUND_CONFIG(sid_intf)
r17778	r17779
940	1061	MCFG_SOUND_ADD("dac", DAC, 0)
941	1062	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
942	1063
943		/* quickload */
	1064	// devices
	1065	MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
	1066	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6567_CLOCK, 60, c128_cia1_intf)
	1067	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6567_CLOCK, 60, c128_cia2_intf)
944	1068	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
945
946		/* cassette */
947	1069	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
	1070	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
	1071	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
	1072	MCFG_C64_EXPANSION_SLOT_ADD(C64_EXPANSION_SLOT_TAG, VIC6567_CLOCK, expansion_intf, c64_expansion_cards, NULL, NULL)
	1073	MCFG_C64_USER_PORT_ADD(C64_USER_PORT_TAG, user_intf, c64_user_port_cards, NULL, NULL)
948	1074
949		/* cia */
950		MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6567_CLOCK, c128_ntsc_cia0)
951		MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6567_CLOCK, c128_ntsc_cia1)
	1075	// software list
	1076	MCFG_SOFTWARE_LIST_ADD("cart_list_vic10", "vic10")
	1077	MCFG_SOFTWARE_LIST_FILTER("cart_list_vic10", "NTSC")
	1078	MCFG_SOFTWARE_LIST_ADD("cart_list_c64", "c64_cart")
	1079	MCFG_SOFTWARE_LIST_FILTER("cart_list_c64", "NTSC")
	1080	MCFG_SOFTWARE_LIST_ADD("cart_list_c128", "c128_cart")
	1081	MCFG_SOFTWARE_LIST_FILTER("cart_list_c128", "NTSC")
	1082	MCFG_SOFTWARE_LIST_ADD("disk_list_c64", "c64_flop")
	1083	MCFG_SOFTWARE_LIST_FILTER("disk_list_c64", "NTSC")
	1084	MCFG_SOFTWARE_LIST_ADD("disk_list_c128", "c128_flop")
	1085	MCFG_SOFTWARE_LIST_FILTER("disk_list_c128", "NTSC")
	1086	MCFG_SOFTWARE_LIST_ADD("from_list", "c128_rom")
	1087	MCFG_SOFTWARE_LIST_FILTER("from_list", "NTSC")
952	1088
953		MCFG_FRAGMENT_ADD(c64_cartslot)
954		MCFG_SOFTWARE_LIST_ADD("c64_disk_list", "c64_flop")
955		MCFG_SOFTWARE_LIST_ADD("c128_disk_list", "c128_flop")
	1089	// internal ram
	1090	MCFG_RAM_ADD(RAM_TAG)
	1091	MCFG_RAM_DEFAULT_SIZE("128K")
956	1092	MACHINE_CONFIG_END
957	1093
958	1094
r17778	r17779
1006	1142	//-------------------------------------------------
1007	1143
1008	1144	static MACHINE_CONFIG_START( pal, c128_state )
1009		/* basic machine hardware */
	1145	// basic hardware
1010	1146	MCFG_CPU_ADD(Z80A_TAG, Z80, VIC6569_CLOCK)
1011	1147	MCFG_CPU_PROGRAM_MAP( z80_mem)
1012		MCFG_CPU_IO_MAP( z80_io)
	1148	MCFG_CPU_IO_MAP(z80_io)
1013	1149	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
1014		//MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6569_HRETRACERATE)
	1150	MCFG_QUANTUM_PERFECT_CPU(Z80A_TAG)
1015	1151
1016	1152	MCFG_CPU_ADD(M8502_TAG, M8502, VIC6569_CLOCK)
1017	1153	MCFG_CPU_PROGRAM_MAP( m8502_mem)
1018	1154	MCFG_CPU_CONFIG( cpu_intf )
1019	1155	MCFG_CPU_VBLANK_INT(SCREEN_VIC_TAG, c128_frame_interrupt)
1020		// MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6569_HRETRACERATE)
	1156	MCFG_QUANTUM_PERFECT_CPU(M8502_TAG)
1021	1157
1022		/* video hardware */
1023		MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
1024		MCFG_MOS8566_ADD(MOS8566_TAG, SCREEN_VIC_TAG, VIC6569_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
1025		MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map)
	1158	// video hardware
	1159	MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, VIC6569_CLOCK*2, vdc_intf, vdc_videoram_map)
	1160	MCFG_MOS8564_ADD(MOS8564_TAG, SCREEN_VIC_TAG, VIC6569_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
1026	1161
1027		/* sound hardware */
	1162	// sound hardware
1028	1163	MCFG_SPEAKER_STANDARD_MONO("mono")
1029	1164	MCFG_SOUND_ADD(MOS6581_TAG, SID6581, VIC6569_CLOCK)
1030	1165	MCFG_SOUND_CONFIG(sid_intf)
r17778	r17779
1032	1167	MCFG_SOUND_ADD("dac", DAC, 0)
1033	1168	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
1034	1169
1035		/* quickload */
	1170	// devices
	1171	MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
	1172	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, 50, c128_cia1_intf)
	1173	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, 50, c128_cia2_intf)
1036	1174	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg", CBM_QUICKLOAD_DELAY_SECONDS)
1037
1038		/* cassette */
1039	1175	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
	1176	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
	1177	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)
	1178	MCFG_C64_EXPANSION_SLOT_ADD(C64_EXPANSION_SLOT_TAG, VIC6569_CLOCK, expansion_intf, c64_expansion_cards, NULL, NULL)
	1179	MCFG_C64_USER_PORT_ADD(C64_USER_PORT_TAG, user_intf, c64_user_port_cards, NULL, NULL)
1040	1180
1041		/* cia */
1042		MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, c128_ntsc_cia0)
1043		MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, c128_ntsc_cia1)
	1181	// software list
	1182	MCFG_SOFTWARE_LIST_ADD("cart_list_vic10", "vic10")
	1183	MCFG_SOFTWARE_LIST_FILTER("cart_list_vic10", "PAL")
	1184	MCFG_SOFTWARE_LIST_ADD("cart_list_c64", "c64_cart")
	1185	MCFG_SOFTWARE_LIST_FILTER("cart_list_c64", "PAL")
	1186	MCFG_SOFTWARE_LIST_ADD("cart_list_c128", "c128_cart")
	1187	MCFG_SOFTWARE_LIST_FILTER("cart_list_c128", "PAL")
	1188	MCFG_SOFTWARE_LIST_ADD("disk_list_c64", "c64_flop")
	1189	MCFG_SOFTWARE_LIST_FILTER("disk_list_c64", "PAL")
	1190	MCFG_SOFTWARE_LIST_ADD("disk_list_c128", "c128_flop")
	1191	MCFG_SOFTWARE_LIST_FILTER("disk_list_c128", "PAL")
	1192	MCFG_SOFTWARE_LIST_ADD("from_list", "c128_rom")
	1193	MCFG_SOFTWARE_LIST_FILTER("from_list", "PAL")
1044	1194
1045		MCFG_FRAGMENT_ADD(c64_cartslot)
1046		MCFG_SOFTWARE_LIST_ADD("c64_disk_list", "c64_flop")
1047		MCFG_SOFTWARE_LIST_ADD("c128_disk_list", "c128_flop")
	1195	// internal ram
	1196	MCFG_RAM_ADD(RAM_TAG)
	1197	MCFG_RAM_DEFAULT_SIZE("128K")
1048	1198	MACHINE_CONFIG_END
1049	1199
1050	1200

trunk/src/mess/drivers/amiga.c

r17778	r17779
283	283
284	284	static const mos6526_interface cia_0_ntsc_intf =
285	285	{
286		60,                                          /* tod_clock */
287	286	DEVCB_DEVICE_LINE("cia_0", amiga_cia_0_irq),                     /* irq_func */
288	287	DEVCB_DEVICE_LINE_MEMBER("centronics", centronics_device, strobe_w),   /* pc_func */
289	288	DEVCB_NULL,
r17778	r17779
296	295
297	296	static const mos6526_interface cia_0_pal_intf =
298	297	{
299		50,                                          /* tod_clock */
300	298	DEVCB_DEVICE_LINE("cia_0", amiga_cia_0_irq),                     /* irq_func */
301	299	DEVCB_DEVICE_LINE_MEMBER("centronics", centronics_device, strobe_w),   /* pc_func */
302	300	DEVCB_NULL,
r17778	r17779
309	307
310	308	static const mos6526_interface cia_1_intf =
311	309	{
312		0,                                          /* tod_clock */
313	310	DEVCB_DEVICE_LINE("cia_1", amiga_cia_1_irq),                     /* irq_func */
314	311	DEVCB_NULL,                                    /* pc_func */
315	312	DEVCB_NULL,
r17778	r17779
322	319
323	320	static const mos6526_interface cia_0_cdtv_intf =
324	321	{
325		0,                                          /* tod_clock */
326	322	DEVCB_DEVICE_LINE("cia_0", amiga_cia_0_irq),                     /* irq_func */
327	323	DEVCB_DEVICE_LINE_MEMBER("centronics", centronics_device, strobe_w),   /* pc_func */
328	324	DEVCB_NULL,
r17778	r17779
335	331
336	332	static const mos6526_interface cia_1_cdtv_intf =
337	333	{
338		0,                                          /* tod_clock */
339	334	DEVCB_DEVICE_LINE("cia_1", amiga_cia_1_irq),                     /* irq_func */
340	335	DEVCB_NULL,   /* pc_func */
341	336	DEVCB_NULL,
r17778	r17779
414	409	MCFG_SOUND_ROUTE(3, "lspeaker", 0.50)
415	410
416	411	/* cia */
417		MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, cia_0_ntsc_intf)
418		MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK, cia_1_intf)
	412	MCFG_MOS8520_ADD("cia_0", AMIGA_68000_NTSC_CLOCK / 10, 60, cia_0_ntsc_intf)
	413	MCFG_MOS8520_ADD("cia_1", AMIGA_68000_NTSC_CLOCK, 0, cia_1_intf)
419	414
420	415	/* fdc */
421	416	MCFG_AMIGA_FDC_ADD("fdc", AMIGA_68000_NTSC_CLOCK)
r17778	r17779
471	466	/* cia */
472	467	MCFG_DEVICE_REMOVE("cia_0")
473	468	MCFG_DEVICE_REMOVE("cia_1")
474		MCFG_MOS8520_ADD("cia_0", CDTV_CLOCK_X1 / 40, cia_0_cdtv_intf)
475		MCFG_MOS8520_ADD("cia_1", CDTV_CLOCK_X1 / 4, cia_1_cdtv_intf)
	469	MCFG_MOS8520_ADD("cia_0", CDTV_CLOCK_X1 / 40, 0, cia_0_cdtv_intf)
	470	MCFG_MOS8520_ADD("cia_1", CDTV_CLOCK_X1 / 4, 0, cia_1_cdtv_intf)
476	471
477	472	/* fdc */
478	473	MCFG_DEVICE_MODIFY("fdc")
r17778	r17779
495	490
496	491	/* cia */
497	492	MCFG_DEVICE_REMOVE("cia_0")
498		MCFG_MOS8520_ADD("cia_0", AMIGA_68000_PAL_CLOCK / 10, cia_0_pal_intf)
	493	MCFG_MOS8520_ADD("cia_0", AMIGA_68000_PAL_CLOCK / 10, 50, cia_0_pal_intf)
499	494
500	495	/* fdc */
501	496	MCFG_DEVICE_MODIFY("fdc")

trunk/src/mess/drivers/ami1200.c

r17778	r17779
256	256
257	257	static const mos6526_interface a1200_cia_0_intf =
258	258	{
259		0,                                       /* tod_clock */
260	259	DEVCB_DEVICE_LINE("cia_0", amiga_cia_0_irq),                           /* irq_func */
261	260	DEVCB_NULL,   /* pc_func */
262	261	DEVCB_NULL,
r17778	r17779
269	268
270	269	static const mos6526_interface a1200_cia_1_intf =
271	270	{
272		0,                                       /* tod_clock */
273	271	DEVCB_DEVICE_LINE("cia_1", amiga_cia_1_irq),                           /* irq_func */
274	272	DEVCB_NULL,   /* pc_func */
275	273	DEVCB_NULL,
r17778	r17779
317	315	MCFG_SOUND_ROUTE(3, "lspeaker", 0.25)
318	316
319	317	/* cia */
320		MCFG_MOS8520_ADD("cia_0", AMIGA_68EC020_NTSC_CLOCK / 10, a1200_cia_0_intf)
321		MCFG_MOS8520_ADD("cia_1", AMIGA_68EC020_NTSC_CLOCK / 10, a1200_cia_1_intf)
	318	MCFG_MOS8520_ADD("cia_0", AMIGA_68EC020_NTSC_CLOCK / 10, 0, a1200_cia_0_intf)
	319	MCFG_MOS8520_ADD("cia_1", AMIGA_68EC020_NTSC_CLOCK / 10, 0, a1200_cia_1_intf)
322	320
323	321	/* fdc */
324	322	MCFG_AMIGA_FDC_ADD("fdc", AMIGA_68EC020_NTSC_CLOCK/2)

trunk/src/mess/drivers/c64.c

r17778	r17779
124	124	break;
125	125
126	126	case 1: // SID
127		data = sid6581_r(m_sid, offset & 0x1f);
	127	data = m_sid->read(space, offset & 0x1f);
128	128	break;
129	129
130	130	case 2: // COLOR
r17778	r17779
140	140	else
141	141	cia_set_port_mask_value(m_cia1, 0, ioport("CTRLSEL")->read() & 0x80 ? c64_keyline[8] : c64_keyline[9] );
142	142
143		data = mos6526_r(m_cia1, offset & 0x0f);
	143	data = m_cia1->read(space, offset & 0x0f);
144	144	break;
145	145
146	146	case 1: // CIA2
147		data = mos6526_r(m_cia2, offset & 0x0f);
	147	data = m_cia2->read(space, offset & 0x0f);
148	148	break;
149	149
150	150	case 2: // I/O1
r17778	r17779
211	211	break;
212	212
213	213	case 1: // SID
214		sid6581_w(m_sid, offset & 0x1f, data);
	214	m_sid->write(space, offset & 0x1f, data);
215	215	break;
216	216
217	217	case 2: // COLOR
r17778	r17779
222	222	switch ((offset >> 8) & 0x03)
223	223	{
224	224	case 0: // CIA1
225		mos6526_w(m_cia1, offset & 0x0f, data);
	225	m_cia1->write(space, offset & 0x0f, data);
226	226	break;
227	227
228	228	case 1: // CIA2
229		mos6526_w(m_cia2, offset & 0x0f, data);
	229	m_cia2->write(space, offset & 0x0f, data);
230	230	break;
231	231
232	232	case 2: // I/O1
r17778	r17779
422	422
423	423
424	424	//-------------------------------------------------
425		//  sid6581_interface sid_intf
	425	//  MOS6581_INTERFACE( sid_intf )
426	426	//-------------------------------------------------
427	427
428	428	READ8_MEMBER( c64_state::sid_potx_r )
r17778	r17779
539	539
540	540	static const mos6526_interface cia1_intf =
541	541	{
542		10,
543	542	DEVCB_DRIVER_LINE_MEMBER(c64_state, cia1_irq_w),
544	543	DEVCB_NULL,
545	544	DEVCB_DEVICE_LINE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, sp1_w),
r17778	r17779
623	622
624	623	static const mos6526_interface cia2_intf =
625	624	{
626		10,
627	625	DEVCB_DRIVER_LINE_MEMBER(c64_state, cia2_irq_w),
628	626	DEVCB_DEVICE_LINE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, pc2_w),
629	627	DEVCB_DEVICE_LINE_MEMBER(C64_USER_PORT_TAG, c64_user_port_device, sp2_w),
r17778	r17779
1009	1007
1010	1008	// devices
1011	1009	MCFG_PLS100_ADD(PLA_TAG)
1012		MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6567_CLOCK, cia1_intf)
1013		MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6567_CLOCK, cia2_intf)
	1010	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6567_CLOCK, 60, cia1_intf)
	1011	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6567_CLOCK, 60, cia2_intf)
1014	1012	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg,t64", CBM_QUICKLOAD_DELAY_SECONDS)
1015	1013	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
1016	1014	MCFG_CBM_IEC_ADD(iec_intf, "c1541")
r17778	r17779
1108	1106
1109	1107	// devices
1110	1108	MCFG_PLS100_ADD(PLA_TAG)
1111		MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, cia1_intf)
1112		MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, cia2_intf)
	1109	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, 50, cia1_intf)
	1110	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, 50, cia2_intf)
1113	1111	MCFG_QUICKLOAD_ADD("quickload", cbm_c64, "p00,prg,t64", CBM_QUICKLOAD_DELAY_SECONDS)
1114	1112	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, "c1530", NULL)
1115	1113	MCFG_CBM_IEC_ADD(iec_intf, "c1541")
r17778	r17779
1185	1183
1186	1184	// devices
1187	1185	MCFG_PLS100_ADD(PLA_TAG)
1188		MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, cia1_intf)
1189		MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, cia2_intf)
	1186	MCFG_MOS6526R1_ADD(MOS6526_1_TAG, VIC6569_CLOCK, 50, cia1_intf)
	1187	MCFG_MOS6526R1_ADD(MOS6526_2_TAG, VIC6569_CLOCK, 50, cia2_intf)
1190	1188	MCFG_CBM_IEC_BUS_ADD(iec_intf)
1191	1189	MCFG_VCS_CONTROL_PORT_ADD(CONTROL1_TAG, vcs_control_port_devices, NULL, NULL)
1192	1190	MCFG_VCS_CONTROL_PORT_ADD(CONTROL2_TAG, vcs_control_port_devices, NULL, NULL)

trunk/src/mess/drivers/vic10.c

r17778	r17779
60	60	}
61	61	else if (offset >= 0xd400 && offset < 0xd800)
62	62	{
63		data = sid6581_r(m_sid, offset & 0x1f);
	63	data = m_sid->read(space, offset & 0x1f);
64	64	}
65	65	else if (offset >= 0xd800 && offset < 0xdc00)
66	66	{
r17778	r17779
103	103	}
104	104	else if (offset >= 0xd400 && offset < 0xd800)
105	105	{
106		sid6581_w(m_sid, offset & 0x1f, data);
	106	m_sid->write(space, offset & 0x1f, data);
107	107	}
108	108	else if (offset >= 0xd800 && offset < 0xdc00)
109	109	{
r17778	r17779
458	458
459	459	static const mos6526_interface cia_intf =
460	460	{
461		10,
462	461	DEVCB_DRIVER_LINE_MEMBER(vic10_state, cia_irq_w),
463	462	DEVCB_NULL,
464	463	DEVCB_DEVICE_LINE_MEMBER(VIC10_EXPANSION_SLOT_TAG, vic10_expansion_slot_device, sp_w),
r17778	r17779
630	629	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
631	630
632	631	// devices
633		MCFG_MOS6526R1_ADD(MOS6526_TAG, VIC6566_CLOCK, cia_intf)
	632	MCFG_MOS6526R1_ADD(MOS6526_TAG, VIC6566_CLOCK, 60, cia_intf)
634	633	MCFG_PET_DATASSETTE_PORT_ADD(PET_DATASSETTE_PORT_TAG, datassette_intf, cbm_datassette_devices, NULL, NULL)
635	634	MCFG_VIC10_EXPANSION_SLOT_ADD(VIC10_EXPANSION_SLOT_TAG, VIC6566_CLOCK, expansion_intf, vic10_expansion_cards, NULL, NULL)
636	635

trunk/src/mess/drivers/sbc6510.c

r17778	r17779
249	249
250	250	const mos6526_interface cia_intf =
251	251	{
252		10,      // time-of-day clock 1/10 second - no idea about this
253	252	DEVCB_CPU_INPUT_LINE("maincpu", M6502_IRQ_LINE), // irq
254	253	DEVCB_NULL,   // pc (timer related) not connected
255	254	DEVCB_NULL,   // cnt (serial related) not connected
r17778	r17779
277	276	MCFG_SOUND_CONFIG(sbc6510_ay_interface)
278	277	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
279	278
280		MCFG_MOS6526R1_ADD("cia6526", XTAL_1MHz, cia_intf)
	279	MCFG_MOS6526R1_ADD("cia6526", XTAL_1MHz, 50, cia_intf)
281	280	MACHINE_CONFIG_END
282	281
283	282	/* ROM definition */

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