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r17763 Sunday 9th September, 2012 at 20:04:57 UTC by Curt Coder
(MESS) c128: MMU WIP. (nw)
[src/mess/drivers]c128.c
[src/mess/includes]c128.h
[src/mess/machine]c128.c

trunk/src/mess/machine/c128.c
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2121#include "video/mos6566.h"
2222#include "video/mc6845.h"
2323
24#define MMU_PAGE1 ((((m_mmu[10]&0xf)<<8)|m_mmu[9])<<8)
25#define MMU_PAGE0 ((((m_mmu[8]&0xf)<<8)|m_mmu[7])<<8)
26#define MMU_VIC_ADDR ((m_mmu[6]&0xc0)<<10)
27#define MMU_RAM_RCR_ADDR ((m_mmu[6]&0x30)<<14)
28#define MMU_SIZE (c128_mmu_helper[m_mmu[6]&3])
29#define MMU_BOTTOM (m_mmu[6]&4)
30#define MMU_TOP (m_mmu[6]&8)
31#define MMU_CPU8502 (m_mmu[5]&1)      /* else z80 */
24#define MMU_PAGE1 ((((m_mmu_reg[10]&0xf)<<8)|m_mmu_reg[9])<<8)
25#define MMU_PAGE0 ((((m_mmu_reg[8]&0xf)<<8)|m_mmu_reg[7])<<8)
26#define MMU_VIC_ADDR ((m_mmu_reg[6]&0xc0)<<10)
27#define MMU_RAM_RCR_ADDR ((m_mmu_reg[6]&0x30)<<14)
28#define MMU_SIZE (c128_mmu_helper[m_mmu_reg[6]&3])
29#define MMU_BOTTOM (m_mmu_reg[6]&4)
30#define MMU_TOP (m_mmu_reg[6]&8)
31#define MMU_CPU8502 (m_mmu_reg[5]&1)      /* else z80 */
3232/* fastio output (c128_mmu[5]&8) else input */
33#define MMU_FSDIR (m_mmu[5]&0x08)
34#define MMU_GAME_IN (m_mmu[5]&0x10)
35#define MMU_EXROM_IN (m_mmu[5]&0x20)
36#define MMU_64MODE (m_mmu[5]&0x40)
37#define MMU_40_IN (m_mmu[5]&0x80)
33#define MMU_FSDIR (m_mmu_reg[5]&0x08)
34#define MMU_GAME_IN (m_mmu_reg[5]&0x10)
35#define MMU_EXROM_IN (m_mmu_reg[5]&0x20)
36#define MMU_64MODE (m_mmu_reg[5]&0x40)
37#define MMU_40_IN (m_mmu_reg[5]&0x80)
3838
39#define MMU_RAM_CR_ADDR ((m_mmu[0]&0xc0)<<10)
40#define MMU_RAM_LO (m_mmu[0]&2)      /* else rom at 0x4000 */
41#define MMU_RAM_MID ((m_mmu[0]&0xc)==0xc)   /* 0x8000 - 0xbfff */
42#define MMU_ROM_MID ((m_mmu[0]&0xc)==0)
43#define MMU_EXTERNAL_ROM_MID ((m_mmu[0]&0xc)==8)
44#define MMU_INTERNAL_ROM_MID ((m_mmu[0]&0xc)==4)
39#define MMU_RAM_CR_ADDR ((m_mmu_reg[0]&0xc0)<<10)
40#define MMU_RAM_LO (m_mmu_reg[0]&2)      /* else rom at 0x4000 */
41#define MMU_RAM_MID ((m_mmu_reg[0]&0xc)==0xc)   /* 0x8000 - 0xbfff */
42#define MMU_ROM_MID ((m_mmu_reg[0]&0xc)==0)
43#define MMU_EXTERNAL_ROM_MID ((m_mmu_reg[0]&0xc)==8)
44#define MMU_INTERNAL_ROM_MID ((m_mmu_reg[0]&0xc)==4)
4545
46#define MMU_IO_ON (!(m_mmu[0]&1))   /* io window at 0xd000 */
47#define MMU_ROM_HI ((m_mmu[0]&0x30)==0)   /* rom at 0xc000 */
48#define MMU_EXTERNAL_ROM_HI ((m_mmu[0]&0x30)==0x20)
49#define MMU_INTERNAL_ROM_HI ((m_mmu[0]&0x30)==0x10)
50#define MMU_RAM_HI ((m_mmu[0]&0x30)==0x30)
46#define MMU_IO_ON (!(m_mmu_reg[0]&1))   /* io window at 0xd000 */
47#define MMU_ROM_HI ((m_mmu_reg[0]&0x30)==0)   /* rom at 0xc000 */
48#define MMU_EXTERNAL_ROM_HI ((m_mmu_reg[0]&0x30)==0x20)
49#define MMU_INTERNAL_ROM_HI ((m_mmu_reg[0]&0x30)==0x10)
50#define MMU_RAM_HI ((m_mmu_reg[0]&0x30)==0x30)
5151
5252#define MMU_RAM_ADDR (MMU_RAM_RCR_ADDR|MMU_RAM_CR_ADDR)
5353
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796796
797797void c128_state::mmu8722_reset()
798798{
799   memset(m_mmu, 0, sizeof (m_mmu));
800   m_mmu[5] |= 0x38;
801   m_mmu[10] = 1;
799   memset(m_mmu_reg, 0, sizeof (m_mmu_reg));
800   m_mmu_reg[5] |= 0x38;
801   m_mmu_reg[10] = 1;
802802   m_mmu_cpu = 0;
803803   m_mmu_page0 = 0;
804804   m_mmu_page1 = 0x0100;
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816816   case 4:
817817   case 8:
818818   case 10:
819      m_mmu[offset] = data;
819      m_mmu_reg[offset] = data;
820820      break;
821821   case 5:
822      m_mmu[offset] = data;
822      m_mmu_reg[offset] = data;
823823      bankswitch(0);
824824      iec_srq_out_w();
825825      iec_data_out_w();
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828828      break;
829829   case 0:
830830   case 6:
831      m_mmu[offset] = data;
831      m_mmu_reg[offset] = data;
832832      bankswitch(0);
833833      break;
834834   case 7:
835      m_mmu[offset] = data;
835      m_mmu_reg[offset] = data;
836836      m_mmu_page0=MMU_PAGE0;
837837      break;
838838   case 9:
839      m_mmu[offset] = data;
839      m_mmu_reg[offset] = data;
840840      m_mmu_page1=MMU_PAGE1;
841841      bankswitch(0);
842842      break;
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858858   switch (offset)
859859   {
860860   case 5:
861      data = m_mmu[offset] | 6;
861      data = m_mmu_reg[offset] | 6;
862862      if ( /*disk enable signal */ 0)
863863         data &= ~8;
864864      if (!m_game)
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884884      data=0xff;
885885      break;
886886   default:
887      data=m_mmu[offset];
887      data=m_mmu_reg[offset];
888888   }
889889   return data;
890890}
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894894   switch (offset)
895895   {
896896   case 0:
897      m_mmu[offset] = data;
897      m_mmu_reg[offset] = data;
898898      bankswitch(0);
899899      break;
900900   case 1:
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902902   case 3:
903903   case 4:
904904#if 1
905      m_mmu[0]= m_mmu[offset];
905      m_mmu_reg[0]= m_mmu_reg[offset];
906906#else
907      m_mmu[0]|= m_mmu[offset];
907      m_mmu_reg[0]|= m_mmu_reg[offset];
908908#endif
909909      bankswitch(0);
910910      break;
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913913
914914READ8_MEMBER( c128_state::mmu8722_ff00_r )
915915{
916   return m_mmu[offset];
916   return m_mmu_reg[offset];
917917}
918918
919919WRITE8_MEMBER( c128_state::write_0000 )
trunk/src/mess/includes/c128.h
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2222#include "machine/c64user.h"
2323#include "machine/cbmiec.h"
2424#include "machine/cbmipt.h"
25#include "machine/mos8722.h"
2526#include "machine/petcass.h"
2627#include "machine/ram.h"
2728#include "machine/vcsctrl.h"
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5556      : legacy_c64_state(mconfig, type, tag),
5657        m_maincpu(*this, Z80A_TAG),
5758        m_subcpu(*this, M8502_TAG),
59        m_mmu(*this, MOS8722_TAG),
5860        m_vdc(*this, MOS8563_TAG),
5961        m_vic(*this, MOS8564_TAG),
6062        m_sid(*this, MOS6581_TAG),
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7173
7274   required_device<legacy_cpu_device> m_maincpu;
7375   required_device<legacy_cpu_device> m_subcpu;
76   required_device<mos8722_device> m_mmu;
7477   required_device<mos8563_device> m_vdc;
7578   required_device<mos6566_device> m_vic;
7679   required_device<sid6581_device> m_sid;
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8790   virtual void machine_start();
8891   virtual void machine_reset();
8992
93   void bankswitch_pla(offs_t offset, int ba, int rw, int aec, int z80io, int ma5, int ma4, int ms3, int ms2, int ms1, int ms0,
94      int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic, int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb);
95   UINT8 read_memory(offs_t offset, int ba, int aec, int z80io);
96   void write_memory(offs_t offset, UINT8 data, int ba, int aec, int z80io);
97
98   DECLARE_READ8_MEMBER( z80_r );
99   DECLARE_WRITE8_MEMBER( z80_w );
100   DECLARE_READ8_MEMBER( z80_io_r );
101   DECLARE_WRITE8_MEMBER( z80_io_w );
102   DECLARE_READ8_MEMBER( read );
103   DECLARE_WRITE8_MEMBER( write );
104   DECLARE_READ8_MEMBER( vic_videoram_r );
105
90106   DECLARE_READ8_MEMBER( read_io );
91107   DECLARE_READ8_MEMBER( mmu8722_port_r );
92108   DECLARE_WRITE8_MEMBER( mmu8722_port_w );
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105121   DECLARE_WRITE8_MEMBER( write_ff00 );
106122   DECLARE_WRITE8_MEMBER( write_ff05 );
107123
124   DECLARE_WRITE_LINE_MEMBER( mmu_z80en_w );
125   DECLARE_WRITE_LINE_MEMBER( mmu_fsdir_w );
126   DECLARE_READ_LINE_MEMBER( mmu_game_r );
127   DECLARE_READ_LINE_MEMBER( mmu_exrom_r );
128   DECLARE_READ_LINE_MEMBER( mmu_sense40_r );
129
108130   DECLARE_READ8_MEMBER( vic_lightpen_x_cb );
109131   DECLARE_READ8_MEMBER( vic_lightpen_y_cb );
110132   DECLARE_READ8_MEMBER( vic_lightpen_button_cb );
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151173   UINT8 *m_internal_function;
152174   UINT8 *m_external_function;
153175   UINT8 *m_vdcram;
154   UINT8 m_mmu[0x0b];
176   UINT8 m_mmu_reg[0x0b];
155177   int m_mmu_cpu;
156178   int m_mmu_page0;
157179   int m_mmu_page1;
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167189   int m_data_out;
168190   int m_va1617;
169191   int m_nmilevel;
192   int m_z80en;
170193   DECLARE_DRIVER_INIT(c128pal);
171194   DECLARE_DRIVER_INIT(c128dcrp);
172195   DECLARE_DRIVER_INIT(c128dcr);
trunk/src/mess/drivers/c128.c
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211211 * 0x0000-0xedff ram (dram bank 1?)
212212 * 0xe000-0xffff ram as bank 0
213213 */
214
215void c128_state::bankswitch_pla(offs_t offset, int ba, int rw, int aec, int z80io, int ma5, int ma4, int ms3, int ms2, int ms1, int ms0,
216      int *cas, int *gwe, int *rom1, int *rom2, int *rom3, int *rom4, int *charom, int *colorram, int *vic, int *from1, int *romh, int *roml, int *dwe, int *ioacc, int *clrbank, int *iocs, int *casenb)
217{
218   //int game = m_exp->game_r(offset, ba, rw, m_hiram);
219   //int exrom = m_exp->exrom_r(offset, ba, rw, m_hiram);
220   //int vicfix = 0;
221   //int _128_256 = 1;
222}
223
224UINT8 c128_state::read_memory(offs_t offset, int ba, int aec, int z80io)
225{
226   int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1;
227   //offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3);
228   int cas, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic, from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb;
229   //int io1 = 1, io2 = 1;
230
231   bankswitch_pla(offset, ba, rw, aec, z80io, 0, 0, ms3, ms2, ms1, ms0,
232      &cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
233
234   UINT8 data = 0xff;
235
236   if (ba)
237   {
238      data = m_vic->bus_r();
239   }
240
241   if (!cas)
242   {
243
244   }
245   else if (!rom1)
246   {
247
248   }
249   else if (!rom2)
250   {
251
252   }
253   else if (!rom3)
254   {
255
256   }
257   else if (!rom4)
258   {
259
260   }
261   else if (!charom)
262   {
263
264   }
265   else if (!colorram)
266   {
267
268   }
269   else if (!vic)
270   {
271
272   }
273   else if (!from1)
274   {
275
276   }
277   else if (!iocs)
278   {
279      switch (offset)
280      {
281      case 0: // SID
282         break;
283
284      case 2: // CS8563
285         break;
286
287      case 4: // CIA1
288         break;
289
290      case 5: // CIA2
291         break;
292
293      case 6: // I/O1
294         break;
295
296      case 7: // I/O2
297         break;
298      }
299   }
300
301   return data;//m_exp->cd_r(space, offset, data, ba, roml, romh, io1, io2);
302}
303
304void c128_state::write_memory(offs_t offset, UINT8 data, int ba, int aec, int z80io)
305{
306   int rw = 1, ms0 = 1, ms1 = 1, ms2 = 1, ms3 = 1;
307   //offs_t ta = m_mmu->ta_r(offset, aec, &ms0, &ms1, &ms2, &ms3);
308   int cas, gwe, rom1, rom2, rom3, rom4, charom, colorram, vic, from1, romh, roml, dwe, ioacc, clrbank, iocs, casenb;
309   //int io1 = 1, io2 = 1;
310
311   bankswitch_pla(offset, ba, rw, aec, z80io, 0, 0, ms3, ms2, ms1, ms0,
312      &cas, &gwe, &rom1, &rom2, &rom3, &rom4, &charom, &colorram, &vic, &from1, &romh, &roml, &dwe, &ioacc, &clrbank, &iocs, &casenb);
313
314   if (!cas)
315   {
316
317   }
318   else if (!gwe)
319   {
320
321   }
322   else if (!rom1)
323   {
324
325   }
326   else if (!rom2)
327   {
328
329   }
330   else if (!rom3)
331   {
332
333   }
334   else if (!rom4)
335   {
336
337   }
338   else if (!charom)
339   {
340
341   }
342   else if (!colorram)
343   {
344
345   }
346   else if (!vic)
347   {
348
349   }
350   else if (!from1)
351   {
352
353   }
354   else if (!dwe)
355   {
356
357   }
358   else if (!iocs)
359   {
360
361   }
362
363   //m_exp->cd_w(space, offset, data, ba, roml, romh, io1, io2);
364}
365
366READ8_MEMBER( c128_state::z80_r )
367{
368   int ba = 1, aec = 1, z80io = 1;
369
370   return read_memory(offset, ba, aec, z80io);
371}
372
373WRITE8_MEMBER( c128_state::z80_w )
374{
375   int ba = 1, aec = 1, z80io = 1;
376   
377   write_memory(offset, data, ba, aec, z80io);
378}
379
380READ8_MEMBER( c128_state::z80_io_r )
381{
382   int ba = 1, aec = 1, z80io = 0;
383   
384   return read_memory(offset, ba, aec, z80io);
385}
386
387WRITE8_MEMBER( c128_state::z80_io_w )
388{
389   int ba = 1, aec = 1, z80io = 0;
390   
391   write_memory(offset, data, ba, aec, z80io);
392}
393
394READ8_MEMBER( c128_state::read )
395{
396   int ba = 1, aec = 1, z80io = 1;
397   
398   return read_memory(offset, ba, aec, z80io);
399}
400
401WRITE8_MEMBER( c128_state::write )
402{
403   int ba = 1, aec = 1, z80io = 1;
404   
405   write_memory(offset, data, ba, aec, z80io);
406}
407
408READ8_MEMBER( c128_state::vic_videoram_r )
409{
410   int ba = 0, aec = 0, z80io = 1;
411   
412   return read_memory(offset, ba, aec, z80io);
413}
414
415
416
214417//**************************************************************************
215418//  ADDRESS MAPS
216419//**************************************************************************
r17762r17763
541744//**************************************************************************
542745
543746//-------------------------------------------------
747//  MOS8722_INTERFACE( mmu_intf )
748//-------------------------------------------------
749
750WRITE_LINE_MEMBER( c128_state::mmu_z80en_w )
751{
752
753}
754
755WRITE_LINE_MEMBER( c128_state::mmu_fsdir_w )
756{
757   
758}
759
760READ_LINE_MEMBER( c128_state::mmu_game_r )
761{
762   return 1;
763}
764
765READ_LINE_MEMBER( c128_state::mmu_exrom_r )
766{
767   return 1;
768}
769
770READ_LINE_MEMBER( c128_state::mmu_sense40_r )
771{
772   return 1;
773}
774
775static MOS8722_INTERFACE( mmu_intf )
776{
777   DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_z80en_w),
778   DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_fsdir_w),
779   DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_game_r),
780   DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_exrom_r),
781   DEVCB_DRIVER_LINE_MEMBER(c128_state, mmu_sense40_r)
782};
783
784
785//-------------------------------------------------
544786//  MOS8564_INTERFACE( vic_intf )
545787//-------------------------------------------------
546788
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686928   // MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6567_HRETRACERATE)
687929
688930   /* video hardware */
931   MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
689932   MCFG_MOS8564_ADD(MOS8564_TAG, SCREEN_VIC_TAG, VIC6567_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
690933   MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map)
691934
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7771020   // MCFG_CPU_PERIODIC_INT(vic2_raster_irq, VIC6569_HRETRACERATE)
7781021
7791022   /* video hardware */
1023   MCFG_MOS8722_ADD(MOS8722_TAG, mmu_intf)
7801024   MCFG_MOS8566_ADD(MOS8566_TAG, SCREEN_VIC_TAG, VIC6569_CLOCK, vic_intf, vic_videoram_map, vic_colorram_map)
7811025   MCFG_MOS8563_ADD(MOS8563_TAG, SCREEN_VDC_TAG, 2000000, vdc_intf, vdc_videoram_map)
7821026

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