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r17703 Friday 7th September, 2012 at 19:46:27 UTC by Oliver Stöneberg
added missing \n to some fatalerror() calls (no whatsnew)
[src/emu/cpu]drcbec.c drcbeut.c drcbex64.c drcbex86.c drcuml.c uml.c
[src/emu/cpu/am29000]am29000.c
[src/emu/cpu/arm7]arm7.c arm7core.c
[src/emu/cpu/cosmac]cosmac.c
[src/emu/cpu/dsp32]dsp32ops.c
[src/emu/cpu/dsp56k]dsp56ops.c
[src/emu/cpu/e132xs]e132xs.c
[src/emu/cpu/h83002]h8_16.c h8_8.c h8ops.h
[src/emu/cpu/i386]i386.c i386op16.c i386op32.c i386ops.c i486ops.c pentops.c x87ops.c
[src/emu/cpu/i960]i960.c
[src/emu/cpu/jaguar]jaguar.c
[src/emu/cpu/mc68hc11]hc11ops.c
[src/emu/cpu/mcs48]mcs48.c
[src/emu/cpu/mips]mips3.c mips3com.c mips3drc.c
[src/emu/cpu/pic16c5x]16c5xdsm.c
[src/emu/cpu/pic16c62x]16c62xdsm.c
[src/emu/cpu/powerpc]drc_ops.c ppc.c ppc403.c ppc602.c ppc603.c ppc_mem.c ppc_ops.c ppccom.c ppcdrc.c
[src/emu/cpu/rsp]rspdrc.c
[src/emu/cpu/sh2]sh2comn.c sh2drc.c
[src/emu/cpu/sharc]compute.c sharc.c sharcdma.c sharcmem.c sharcops.c
[src/emu/cpu/tms32010]32010dsm.c
[src/emu/cpu/tms32025]32025dsm.c
[src/emu/cpu/tms32031]32031ops.c
[src/emu/cpu/tms32051]32051ops.c
[src/emu/cpu/tms34010]tms34010.c
[src/emu/cpu/tms57002]tms57002.c
[src/emu/cpu/upd7810]upd7810.c
[src/emu/cpu/v60]am1.c am2.c am3.c op12.c op2.c op5.c op7a.c v60.c
[src/emu/cpu/v810]v810.c
[src/emu/cpu/z80]z80daisy.c
[src/osd/sdl]draw13.c

trunk/src/osd/sdl/draw13.c
r17702r17703
622622
623623   if (!sdl->sdl_renderer)
624624   {
625      fatalerror("Error on creating renderer: %s \n", SDL_GetError());
625      fatalerror("Error on creating renderer: %s\n", SDL_GetError());
626626   }
627627
628628    //SDL_SelectRenderer(window->sdl_window);
trunk/src/emu/cpu/h83002/h8_16.c
r17702r17703
492492   case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX:   h8_3002_InterruptRequest(h8, 57, info->i);      break;
493493
494494   default:
495      fatalerror("h8_set_info unknown request %x", state);
495      fatalerror("h8_set_info unknown request %x\n", state);
496496      break;
497497   }
498498}
r17702r17703
529529   case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX:   h8_3002_InterruptRequest(h8, 85, info->i);      break;
530530
531531   default:
532      fatalerror("h8_set_info unknown request %x", state);
532      fatalerror("h8_set_info unknown request %x\n", state);
533533      break;
534534   }
535535}
trunk/src/emu/cpu/h83002/h8ops.h
r17702r17703
247247
248248   if (h8->h8err)
249249   {
250      fatalerror("H8/3xx: Unknown opcode (PC=%x) %x", h8->ppc, opcode);
250      fatalerror("H8/3xx: Unknown opcode (PC=%x) %x\n", h8->ppc, opcode);
251251   }
252252}
253253
trunk/src/emu/cpu/h83002/h8_8.c
r17702r17703
504504   case CPUINFO_INT_INPUT_STATE + H8_SCI_1_RX:   h8_300_InterruptRequest(h8, 32, info->i);      break;
505505
506506   default:
507      fatalerror("h8_set_info unknown request %x", state);
507      fatalerror("h8_set_info unknown request %x\n", state);
508508      break;
509509   }
510510}
trunk/src/emu/cpu/pic16c62x/16c62xdsm.c
r17702r17703
135135            case 'x':
136136               bit --;
137137               break;
138            default: fatalerror("Invalid instruction encoding '%s %s'",
138            default: fatalerror("Invalid instruction encoding '%s %s'\n",
139139               ops[0],ops[1]);
140140         }
141141      }
142142      if (bit != -1 )
143143      {
144         fatalerror("not enough bits in encoding '%s %s' %d",
144         fatalerror("not enough bits in encoding '%s %s' %d\n",
145145            ops[0],ops[1],bit);
146146      }
147147      while (isspace((UINT8)*p)) p++;
r17702r17703
224224         case 'k': k <<=1; k |= ((code & (1<<bit)) ? 1 : 0); bit--; break;
225225         case ' ': break;
226226         case '1': case '0': case 'x':  bit--; break;
227         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d",code,bit);
227         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d\n",code,bit);
228228      }
229229      cp++;
230230   }
r17702r17703
250250            case 'F': if (f < 0x20) sprintf(num,"%s",regfile[f]); else sprintf(num,"Reg$%02X",f); break;
251251            case 'K': sprintf(num,"%02Xh",k); break;
252252            default:
253               fatalerror("illegal escape character in format '%s'",Op[op].fmt);
253               fatalerror("illegal escape character in format '%s'\n",Op[op].fmt);
254254         }
255255         q = num; while (*q) *buffer++ = *q++;
256256         *buffer = '\0';
trunk/src/emu/cpu/am29000/am29000.c
r17702r17703
274274      return state->direct->read_decrypted_dword(address);
275275   else
276276   {
277      fatalerror("Am29000 instruction MMU translation enabled!");
277      fatalerror("Am29000 instruction MMU translation enabled!\n");
278278   }
279279   return 0;
280280}
r17702r17703
425425         }
426426         else
427427         {
428            fatalerror("Am29000: Non vectored interrupt fetch!");
428            fatalerror("Am29000: Non vectored interrupt fetch!\n");
429429         }
430430
431431         am29000->exceptions = 0;
trunk/src/emu/cpu/tms34010/tms34010.c
r17702r17703
997997
998998            /* interlaced timing not supported */
999999            if ((SMART_IOREG(tms, DPYCTL) & 0x4000) == 0)
1000               fatalerror("Interlaced video configured on the TMS34010 (unsupported)");
1000               fatalerror("Interlaced video configured on the TMS34010 (unsupported)\n");
10011001         }
10021002      }
10031003   }
trunk/src/emu/cpu/tms32031/32031ops.c
r17702r17703
110110
111111void tms3203x_device::unimplemented(UINT32 op)
112112{
113   fatalerror("Unimplemented op @ %06X: %08X (tbl=%03X)", m_pc - 1, op, op >> 21);
113   fatalerror("Unimplemented op @ %06X: %08X (tbl=%03X)\n", m_pc - 1, op, op >> 21);
114114}
115115
116116
r17702r17703
855855#if USE_FP
856856void tms3203x_device::norm(tmsreg &dst, tmsreg &src)
857857{
858   fatalerror("norm not implemented");
858   fatalerror("norm not implemented\n");
859859}
860860#else
861861void tms3203x_device::norm(tmsreg &dst, tmsreg &src)
trunk/src/emu/cpu/mcs48/mcs48.c
r17702r17703
14341434         else if (ramsize == 256)
14351435            info->i = 8;
14361436         else
1437            fatalerror("mcs48_generic_get_info: Invalid RAM size");
1437            fatalerror("mcs48_generic_get_info: Invalid RAM size\n");
14381438         break;
14391439
14401440      /* --- the following bits of info are returned as pointers to functions --- */
r17702r17703
14481448         else if (romsize == 4096)
14491449            info->init = CPU_INIT_NAME(mcs48_4k_rom);
14501450         else
1451            fatalerror("mcs48_generic_get_info: Invalid ROM size");
1451            fatalerror("mcs48_generic_get_info: Invalid ROM size\n");
14521452         break;
14531453
14541454      case CPUINFO_FCT_DISASSEMBLE:
r17702r17703
14691469         else if (romsize == 4096)
14701470            info->internal_map8 = ADDRESS_MAP_NAME(program_12bit);
14711471         else
1472            fatalerror("mcs48_generic_get_info: Invalid RAM size");
1472            fatalerror("mcs48_generic_get_info: Invalid RAM size\n");
14731473         break;
14741474
14751475      case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA:
r17702r17703
14801480         else if (ramsize == 256)
14811481            info->internal_map8 = ADDRESS_MAP_NAME(data_8bit);
14821482         else
1483            fatalerror("mcs48_generic_get_info: Invalid RAM size");
1483            fatalerror("mcs48_generic_get_info: Invalid RAM size\n");
14841484         break;
14851485
14861486      /* --- the following bits of info are returned as NULL-terminated strings --- */
trunk/src/emu/cpu/sharc/sharcmem.c
r17702r17703
1818                  (cpustate->internal_ram_block1[addr + 1]);
1919   }
2020   else {
21      fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc);
21      fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, cpustate->pc);
2222   }
2323}
2424
r17702r17703
4242      return;
4343   }
4444   else {
45      fatalerror("SHARC: PM Bus Write %08X, %08X at %08X", address, data, cpustate->pc);
45      fatalerror("SHARC: PM Bus Write %08X, %08X at %08X\n", address, data, cpustate->pc);
4646   }
4747}
4848
r17702r17703
6666            ((UINT64)(cpustate->internal_ram_block1[addr + 2]) << 0);
6767   }
6868   else {
69      fatalerror("SHARC: PM Bus Read %08X at %08X", address, cpustate->pc);
69      fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, cpustate->pc);
7070   }
7171
7272   return 0;
r17702r17703
9494      return;
9595   }
9696   else {
97      fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc);
97      fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X\n", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc);
9898   }
9999}
100100
trunk/src/emu/cpu/sharc/sharc.c
r17702r17703
245245         break;
246246      }
247247
248      default:   fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X", cpustate->iop_latency_reg);
248      default:   fatalerror("SHARC: iop_write_latency_effect: unknown IOP register %02X\n", cpustate->iop_latency_reg);
249249   }
250250}
251251
r17702r17703
267267         }
268268         return r;
269269      }
270      default:      fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X", address, cpustate->pc);
270      default:      fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, cpustate->pc);
271271   }
272272   return 0;
273273}
r17702r17703
324324      case 0x4e: cpustate->dma[7].ext_modifier = data; return;
325325      case 0x4f: cpustate->dma[7].ext_count = data; return;
326326
327      default:      fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X", address, data, cpustate->pc);
327      default:      fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X\n", address, data, cpustate->pc);
328328   }
329329}
330330
r17702r17703
579579         break;
580580
581581      default:
582         fatalerror("SHARC: Unimplemented boot mode %d", cpustate->boot_mode);
582         fatalerror("SHARC: Unimplemented boot mode %d\n", cpustate->boot_mode);
583583   }
584584
585585   cpustate->pc = 0x20004;
r17702r17703
618618      }
619619      else
620620      {
621         fatalerror("sharc_set_flag_input: flag %d is set output!", flag_num);
621         fatalerror("sharc_set_flag_input: flag %d is set output!\n", flag_num);
622622      }
623623   }
624624}
r17702r17703
755755            }
756756            case 1:      // counter-based, length 1
757757            {
758               //fatalerror("SHARC: counter-based loop, length 1 at %08X", cpustate->pc);
758               //fatalerror("SHARC: counter-based loop, length 1 at %08X\n", cpustate->pc);
759759               //break;
760760            }
761761            case 2:      // counter-based, length 2
762762            {
763               //fatalerror("SHARC: counter-based loop, length 2 at %08X", cpustate->pc);
763               //fatalerror("SHARC: counter-based loop, length 2 at %08X\n", cpustate->pc);
764764               //break;
765765            }
766766            case 3:      // counter-based, length >2
trunk/src/emu/cpu/sharc/sharcops.c
r17702r17703
161161
162162         if ((data & 0x1) != (oldreg & 0x1))
163163         {
164            fatalerror("SHARC: systemreg_latency_op: enable I8 bit-reversing");
164            fatalerror("SHARC: systemreg_latency_op: enable I8 bit-reversing\n");
165165         }
166166         if ((data & 0x2) != (oldreg & 0x2))
167167         {
168            fatalerror("SHARC: systemreg_latency_op: enable I0 bit-reversing");
168            fatalerror("SHARC: systemreg_latency_op: enable I0 bit-reversing\n");
169169         }
170170         if ((data & 0x4) != (oldreg & 0x4))
171171         {
172            fatalerror("SHARC: systemreg_latency_op: enable MR alternate");
172            fatalerror("SHARC: systemreg_latency_op: enable MR alternate\n");
173173         }
174174
175175         if ((data & 0x8) != (oldreg & 0x8))         /* Switch DAG1 7-4 */
r17702r17703
260260         }
261261         break;
262262      }
263      default:   fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X", cpustate->systemreg_latency_reg, cpustate->pc);
263      default:   fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X\n", cpustate->systemreg_latency_reg, cpustate->pc);
264264   }
265265
266266   cpustate->systemreg_latency_reg = -1;
r17702r17703
332332         switch(reg)
333333         {
334334            case 0x4:   return cpustate->pcstack[cpustate->pcstkp];      /* PCSTK */
335            default:   fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
335            default:   fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
336336         }
337337         break;
338338      }
r17702r17703
358358            }
359359            case 0xd:   return cpustate->imask;         /* IMASK */
360360            case 0xe:   return cpustate->stky;         /* STKY */
361            default:   fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
361            default:   fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
362362         }
363363         break;
364364      }
r17702r17703
371371            case 0xb:   return (UINT32)(cpustate->px);         /* PX */
372372            case 0xc:   return (UINT16)(cpustate->px);         /* PX1 */
373373            case 0xd:   return (UINT32)(cpustate->px >> 16);   /* PX2 */
374            default:   fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
374            default:   fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
375375         }
376376         break;
377377      }
378378
379      default:         fatalerror("SHARC: GET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
379      default:         fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
380380   }
381381}
382382
r17702r17703
441441         {
442442            case 0x5:   cpustate->pcstkp = data; break;      /* PCSTKP */
443443            case 0x8:   cpustate->lcntr = data; break;      /* LCNTR */
444            default:   fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
444            default:   fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
445445         }
446446         break;
447447
r17702r17703
471471            }
472472
473473            case 0xe:   cpustate->stky = data; break;      /* STKY */
474            default:   fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
474            default:   fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
475475         }
476476         break;
477477
r17702r17703
480480         {
481481            case 0xc:   cpustate->px &= U64(0xffffffffffff0000); cpustate->px |= (data & 0xffff); break;      /* PX1 */
482482            case 0xd:   cpustate->px &= U64(0x000000000000ffff); cpustate->px |= (UINT64)data << 16; break;      /* PX2 */
483            default:   fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
483            default:   fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
484484         }
485485         break;
486486
487      default:         fatalerror("SHARC: SET_UREG: unknown register %08X at %08X", ureg, cpustate->pc);
487      default:         fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc);
488488   }
489489}
490490
r17702r17703
694694         break;
695695      }
696696
697      default:   fatalerror("SHARC: unimplemented shift operation %02X at %08X", shiftop, cpustate->pc);
697      default:   fatalerror("SHARC: unimplemented shift operation %02X at %08X\n", shiftop, cpustate->pc);
698698   }
699699}
700700
r17702r17703
786786         }
787787
788788         default:
789            fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)", multiop, cpustate->pc, opcode);
789            fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)\n", multiop, cpustate->pc, opcode);
790790            break;
791791      }
792792   }
r17702r17703
853853                  break;
854854               }
855855
856               default:      fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)", op, cpustate->pc, opcode);
856               default:      fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)\n", op, cpustate->pc, opcode);
857857            }
858858            break;
859859         }
r17702r17703
875875               case 0xb2:      REG(rn) = compute_mrb_plus_mul_ssin(cpustate, rx, ry); break;
876876
877877               default:
878                  fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)", op, cpustate->pc, opcode);
878                  fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)\n", op, cpustate->pc, opcode);
879879                  break;
880880            }
881881            break;
r17702r17703
10461046               }
10471047
10481048               default:
1049                  fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)", op, cpustate->pc, opcode);
1049                  fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)\n", op, cpustate->pc, opcode);
10501050            }
10511051            break;
10521052         }
10531053
10541054         default:
1055            fatalerror("SHARC: compute: invalid single-function operation %02X", cu);
1055            fatalerror("SHARC: compute: invalid single-function operation %02X\n", cu);
10561056      }
10571057   }
10581058}
r17702r17703
10621062   cpustate->pcstkp++;
10631063   if(cpustate->pcstkp >= 32)
10641064   {
1065      fatalerror("SHARC: PC Stack overflow !");
1065      fatalerror("SHARC: PC Stack overflow!\n");
10661066   }
10671067
10681068   if (cpustate->pcstkp == 0)
r17702r17703
10841084
10851085   if(cpustate->pcstkp == 0)
10861086   {
1087      fatalerror("SHARC: PC Stack underflow !");
1087      fatalerror("SHARC: PC Stack underflow!\n");
10881088   }
10891089
10901090   cpustate->pcstkp--;
r17702r17703
11111111   cpustate->lstkp++;
11121112   if(cpustate->lstkp >= 6)
11131113   {
1114      fatalerror("SHARC: Loop Stack overflow !");
1114      fatalerror("SHARC: Loop Stack overflow!\n");
11151115   }
11161116
11171117   if (cpustate->lstkp == 0)
r17702r17703
11331133{
11341134   if(cpustate->lstkp == 0)
11351135   {
1136      fatalerror("SHARC: Loop Stack underflow !");
1136      fatalerror("SHARC: Loop Stack underflow!\n");
11371137   }
11381138
11391139   cpustate->lstkp--;
r17702r17703
11561156   cpustate->status_stkp++;
11571157   if (cpustate->status_stkp >= 5)
11581158   {
1159      fatalerror("SHARC: Status stack overflow !");
1159      fatalerror("SHARC: Status stack overflow!\n");
11601160   }
11611161
11621162   if (cpustate->status_stkp == 0)
r17702r17703
11801180   cpustate->status_stkp--;
11811181   if (cpustate->status_stkp < 0)
11821182   {
1183      fatalerror("SHARC: Status stack underflow !");
1183      fatalerror("SHARC: Status stack underflow!\n");
11841184   }
11851185
11861186   if (cpustate->status_stkp == 0)
r17702r17703
22542254   int compute = cpustate->opcode & 0x7fffff;
22552255
22562256   //if(lr)
2257   //  fatalerror("SHARC: rts: loop reentry not implemented !");
2257   //  fatalerror("SHARC: rts: loop reentry not implemented!\n");
22582258
22592259   if (e)      /* IF...ELSE */
22602260   {
r17702r17703
26462646         break;
26472647      }
26482648      default:
2649         fatalerror("SHARC: sysreg_bitop: invalid bitop %d", bop);
2649         fatalerror("SHARC: sysreg_bitop: invalid bitop %d\n", bop);
26502650         break;
26512651   }
26522652
r17702r17703
26812681/* I register bit-reverse */
26822682static void sharcop_bit_reverse(SHARC_REGS *cpustate)
26832683{
2684   fatalerror("SHARC: sharcop_bit_reverse unimplemented");
2684   fatalerror("SHARC: sharcop_bit_reverse unimplemented\n");
26852685}
26862686
26872687/*****************************************************************************/
r17702r17703
26922692{
26932693   if (cpustate->opcode & U64(0x008000000000))
26942694   {
2695      fatalerror("sharcop_push_pop_stacks: push loop not implemented");
2695      fatalerror("sharcop_push_pop_stacks: push loop not implemented\n");
26962696   }
26972697   if (cpustate->opcode & U64(0x004000000000))
26982698   {
2699      fatalerror("sharcop_push_pop_stacks: pop loop not implemented");
2699      fatalerror("sharcop_push_pop_stacks: pop loop not implemented\n");
27002700   }
27012701   if (cpustate->opcode & U64(0x002000000000))
27022702   {
2703      //fatalerror("sharcop_push_pop_stacks: push sts not implemented");
2703      //fatalerror("sharcop_push_pop_stacks: push sts not implemented\n");
27042704      PUSH_STATUS_STACK(cpustate);
27052705   }
27062706   if (cpustate->opcode & U64(0x001000000000))
27072707   {
2708      //fatalerror("sharcop_push_pop_stacks: pop sts not implemented");
2708      //fatalerror("sharcop_push_pop_stacks: pop sts not implemented\n");
27092709      POP_STATUS_STACK(cpustate);
27102710   }
27112711   if (cpustate->opcode & U64(0x000800000000))
r17702r17703
27502750   char dasm[1000];
27512751   CPU_DISASSEMBLE_NAME(sharc)(NULL, dasm, cpustate->pc, NULL, NULL, 0);
27522752   mame_printf_debug("SHARC: %08X: %s\n", cpustate->pc, dasm);
2753   fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X", (UINT16)(cpustate->opcode >> 32), (UINT32)(cpustate->opcode), cpustate->pc);
2753   fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X\n", (UINT16)(cpustate->opcode >> 32), (UINT32)(cpustate->opcode), cpustate->pc);
27542754}
trunk/src/emu/cpu/sharc/sharcdma.c
r17702r17703
2121
2222   if (cpustate->dmaop_cycles > 0)
2323   {
24      fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!", cpustate->pc);
24      fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc);
2525   }
2626
2727   if (chained_direction)      // Transmit to external
r17702r17703
5454{
5555   if (cpustate->dmaop_cycles > 0)
5656   {
57      fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!", cpustate->pc);
57      fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc);
5858   }
5959
6060   cpustate->dmaop_channel = channel;
r17702r17703
155155   //flsh = (cpustate->dma[channel].control >> 13) & 0x1;
156156
157157   if (ishake)
158      fatalerror("SHARC: dma_exec: handshake not supported");
158      fatalerror("SHARC: dma_exec: handshake not supported\n");
159159   if (intio)
160      fatalerror("SHARC: dma_exec: single-word interrupt enable not supported");
160      fatalerror("SHARC: dma_exec: single-word interrupt enable not supported\n");
161161
162162
163163
trunk/src/emu/cpu/sharc/compute.c
r17702r17703
114114   UINT32 r = REG(rx) + REG(ry);
115115
116116   if (cpustate->mode1 & MODE1_ALUSAT)
117      fatalerror("SHARC: compute_add: ALU saturation not implemented !");
117      fatalerror("SHARC: compute_add: ALU saturation not implemented!\n");
118118
119119   CLEAR_ALU_FLAGS();
120120   SET_FLAG_AN(r);
r17702r17703
132132   UINT32 r = REG(rx) - REG(ry);
133133
134134   if (cpustate->mode1 & MODE1_ALUSAT)
135      fatalerror("SHARC: compute_sub: ALU saturation not implemented !");
135      fatalerror("SHARC: compute_sub: ALU saturation not implemented!\n");
136136
137137   CLEAR_ALU_FLAGS();
138138   SET_FLAG_AN(r);
r17702r17703
151151   UINT32 r = REG(rx) + REG(ry) + c;
152152
153153   if (cpustate->mode1 & MODE1_ALUSAT)
154      fatalerror("SHARC: compute_add_ci: ALU saturation not implemented !");
154      fatalerror("SHARC: compute_add_ci: ALU saturation not implemented!\n");
155155
156156   CLEAR_ALU_FLAGS();
157157   SET_FLAG_AN(r);
r17702r17703
170170   UINT32 r = REG(rx) - REG(ry) + c - 1;
171171
172172   if (cpustate->mode1 & MODE1_ALUSAT)
173      fatalerror("SHARC: compute_sub_ci: ALU saturation not implemented !");
173      fatalerror("SHARC: compute_sub_ci: ALU saturation not implemented!\n");
174174
175175   CLEAR_ALU_FLAGS();
176176   SET_FLAG_AN(r);
r17702r17703
971971   {
972972      case 0:      SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf)); break;
973973      case 1:      SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf >> 32)); break;
974      case 2:      fatalerror("SHARC: tried to load MR2F"); break;
974      case 2:      fatalerror("SHARC: tried to load MR2F\n"); break;
975975      case 4:      SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb)); break;
976976      case 5:      SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb >> 32)); break;
977      case 6:      fatalerror("SHARC: tried to load MR2B"); break;
978      default:   fatalerror("SHARC: unknown ai %d in mr_to_reg", ai);
977      case 6:      fatalerror("SHARC: tried to load MR2B\n"); break;
978      default:   fatalerror("SHARC: unknown ai %d in mr_to_reg\n", ai);
979979   }
980980
981981   CLEAR_MULTIPLIER_FLAGS();
r17702r17703
987987   {
988988      case 0:      cpustate->mrf &= ~0xffffffff; cpustate->mrf |= GET_UREG(cpustate, rk); break;
989989      case 1:      cpustate->mrf &= 0xffffffff; cpustate->mrf |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break;
990      case 2:      fatalerror("SHARC: tried to write MR2F"); break;
990      case 2:      fatalerror("SHARC: tried to write MR2F\n"); break;
991991      case 4:      cpustate->mrb &= ~0xffffffff; cpustate->mrb |= GET_UREG(cpustate, rk); break;
992992      case 5:      cpustate->mrb &= 0xffffffff; cpustate->mrb |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break;
993      case 6:      fatalerror("SHARC: tried to write MR2B"); break;
994      default:   fatalerror("SHARC: unknown ai %d in reg_to_mr", ai);
993      case 6:      fatalerror("SHARC: tried to write MR2B\n"); break;
994      default:   fatalerror("SHARC: unknown ai %d in reg_to_mr\n", ai);
995995   }
996996
997997   CLEAR_MULTIPLIER_FLAGS();
trunk/src/emu/cpu/tms57002/tms57002.c
r17702r17703
759759#undef CINTRP
760760
761761         default:
762            fatalerror("Unhandled opcode in tms57002_execute");
762            fatalerror("Unhandled opcode in tms57002_execute\n");
763763         }
764764      }
765765   inst:
trunk/src/emu/cpu/drcuml.c
r17702r17703
211211   }
212212   catch (drcuml_block::abort_compilation &)
213213   {
214      fatalerror("Out of cache space in drcuml_state::reset");
214      fatalerror("Out of cache space in drcuml_state::reset\n");
215215   }
216216}
217217
r17702r17703
401401   // get a pointer to the next instruction
402402   instruction &curinst = m_inst[m_nextinst++];
403403   if (m_nextinst > m_maxinst)
404      fatalerror("Overran maxinst in drcuml_block_append");
404      fatalerror("Overran maxinst in drcuml_block_append\n");
405405
406406   return curinst;
407407}
r17702r17703
771771      bevalidate_iterate_over_params(drcuml, handles, test, param, 0);
772772      printf("\n");
773773   }
774   fatalerror("All tests passed!");
774   fatalerror("All tests passed!\n");
775775}
776776
777777
r17702r17703
11611161      printf("\n");
11621162      printf("Errors:\n");
11631163      printf("%s\n", errorbuf);
1164      fatalerror("Error during validation");
1164      fatalerror("Error during validation\n");
11651165   }
11661166   return errend != errorbuf;
11671167}
trunk/src/emu/cpu/upd7810/upd7810.c
r17702r17703
19461946               PC += cpustate->op74[OP2].oplen - 2;
19471947               break;
19481948            default:
1949               fatalerror("uPD7810 internal error: check cycle counts for main");
1949               fatalerror("uPD7810 internal error: check cycle counts for main\n");
19501950            }
19511951         }
19521952         PSW &= ~SK;
trunk/src/emu/cpu/v60/am1.c
r17702r17703
105105      cpustate->reg[cpustate->modval & 0x1F] +=4;
106106      break;
107107   default:
108      fatalerror("CPU - BAM1 - 7");
108      fatalerror("CPU - BAM1 - 7\n");
109109      break;
110110   }
111111   return 1;
r17702r17703
144144      cpustate->reg[cpustate->modval & 0x1F]-=4;
145145      break;
146146   default:
147      fatalerror("CPU - BAM1 - 7");
147      fatalerror("CPU - BAM1 - 7\n");
148148      break;
149149   }
150150   cpustate->amout = cpustate->program->read_dword_unaligned(cpustate->reg[cpustate->modval & 0x1F]);
r17702r17703
10871087
10881088static UINT32 am1Error1(v60_state *cpustate)
10891089{
1090   fatalerror("CPU - AM1 - 1 (cpustate->PC=%06x)", cpustate->PC);
1090   fatalerror("CPU - AM1 - 1 (cpustate->PC=%06x)\n", cpustate->PC);
10911091   return 0; /* never reached, fatalerror won't return */
10921092}
10931093
10941094static UINT32 bam1Error1(v60_state *cpustate)
10951095{
1096   fatalerror("CPU - BAM1 - 1 (cpustate->PC=%06x)", cpustate->PC);
1096   fatalerror("CPU - BAM1 - 1 (cpustate->PC=%06x)\n", cpustate->PC);
10971097   return 0; /* never reached, fatalerror won't return */
10981098}
10991099
11001100static UINT32 am1Error2(v60_state *cpustate)
11011101{
1102   fatalerror("CPU - AM1 - 2 (cpustate->PC=%06x)", cpustate->PC);
1102   fatalerror("CPU - AM1 - 2 (cpustate->PC=%06x)\n", cpustate->PC);
11031103   return 0; /* never reached, fatalerror won't return */
11041104}
11051105
11061106static UINT32 bam1Error2(v60_state *cpustate)
11071107{
1108   fatalerror("CPU - BAM1 - 2 (cpustate->PC=%06x)", cpustate->PC);
1108   fatalerror("CPU - BAM1 - 2 (cpustate->PC=%06x)\n", cpustate->PC);
11091109   return 0; /* never reached, fatalerror won't return */
11101110}
11111111
11121112#ifdef UNUSED_FUNCTION
11131113static UINT32 am1Error3(v60_state *cpustate)
11141114{
1115   fatalerror("CPU - AM1 - 3 (cpustate->PC=%06x)", cpustate->PC);
1115   fatalerror("CPU - AM1 - 3 (cpustate->PC=%06x)\n", cpustate->PC);
11161116   return 0; /* never reached, fatalerror won't return */
11171117}
11181118
11191119static UINT32 bam1Error3(v60_state *cpustate)
11201120{
1121   fatalerror("CPU - BAM1 - 3 (cpustate->PC=%06x)", cpustate->PC);
1121   fatalerror("CPU - BAM1 - 3 (cpustate->PC=%06x)\n", cpustate->PC);
11221122   return 0; /* never reached, fatalerror won't return */
11231123}
11241124#endif
11251125
11261126static UINT32 am1Error4(v60_state *cpustate)
11271127{
1128   fatalerror("CPU - AM1 - 4 (cpustate->PC=%06x)", cpustate->PC);
1128   fatalerror("CPU - AM1 - 4 (cpustate->PC=%06x)\n", cpustate->PC);
11291129   return 0; /* never reached, fatalerror won't return */
11301130}
11311131
11321132static UINT32 bam1Error4(v60_state *cpustate)
11331133{
1134   fatalerror("CPU - BAM1 - 4 (cpustate->PC=%06x)", cpustate->PC);
1134   fatalerror("CPU - BAM1 - 4 (cpustate->PC=%06x)\n", cpustate->PC);
11351135   return 0; /* never reached, fatalerror won't return */
11361136}
11371137
11381138static UINT32 am1Error5(v60_state *cpustate)
11391139{
1140   fatalerror("CPU - AM1 - 5 (cpustate->PC=%06x)", cpustate->PC);
1140   fatalerror("CPU - AM1 - 5 (cpustate->PC=%06x)\n", cpustate->PC);
11411141   return 0; /* never reached, fatalerror won't return */
11421142}
11431143
11441144static UINT32 bam1Error5(v60_state *cpustate)
11451145{
1146   fatalerror("CPU - BAM1 - 5 (cpustate->PC=%06x)", cpustate->PC);
1146   fatalerror("CPU - BAM1 - 5 (cpustate->PC=%06x)\n", cpustate->PC);
11471147   return 0; /* never reached, fatalerror won't return */
11481148}
11491149
11501150static UINT32 bam1Error6(v60_state *cpustate)
11511151{
1152   fatalerror("CPU - BAM1 - 6 (cpustate->PC=%06x)", cpustate->PC);
1152   fatalerror("CPU - BAM1 - 6 (cpustate->PC=%06x)\n", cpustate->PC);
11531153   return 0; /* never reached, fatalerror won't return */
11541154}
11551155
trunk/src/emu/cpu/v60/am2.c
r17702r17703
9494      cpustate->reg[cpustate->modval & 0x1F] +=4;
9595      break;
9696   default:
97      fatalerror("CPU - AM2 - 7 (t0 cpustate->PC=%x)", cpustate->PC);
97      fatalerror("CPU - AM2 - 7 (t0 cpustate->PC=%x)\n", cpustate->PC);
9898      break;
9999   }
100100
r17702r17703
139139      cpustate->reg[cpustate->modval & 0x1F]-=4;
140140      break;
141141   default:
142      fatalerror("CPU - BAM2 - 7 (cpustate->PC=%06x)", cpustate->PC);
142      fatalerror("CPU - BAM2 - 7 (cpustate->PC=%06x)\n", cpustate->PC);
143143      break;
144144   }
145145
r17702r17703
963963
964964static UINT32 am2Error2(v60_state *cpustate)
965965{
966   fatalerror("CPU - AM2 - 2 (cpustate->PC=%06x)", cpustate->PC);
966   fatalerror("CPU - AM2 - 2 (cpustate->PC=%06x)\n", cpustate->PC);
967967   return 0; /* never reached, fatalerror won't return */
968968}
969969
970970#ifdef UNUSED_FUNCTION
971971static UINT32 am2Error3(v60_state *cpustate)
972972{
973   fatalerror("CPU - AM2 - 3 (cpustate->PC=%06x)", cpustate->PC);
973   fatalerror("CPU - AM2 - 3 (cpustate->PC=%06x)\n", cpustate->PC);
974974   return 0; /* never reached, fatalerror won't return */
975975}
976976#endif
977977
978978static UINT32 am2Error4(v60_state *cpustate)
979979{
980   fatalerror("CPU - AM2 - 4 (cpustate->PC=%06x)", cpustate->PC);
980   fatalerror("CPU - AM2 - 4 (cpustate->PC=%06x)\n", cpustate->PC);
981981   return 0; /* never reached, fatalerror won't return */
982982}
983983
984984static UINT32 am2Error5(v60_state *cpustate)
985985{
986   fatalerror("CPU - AM2 - 5 (cpustate->PC=%06x)", cpustate->PC);
986   fatalerror("CPU - AM2 - 5 (cpustate->PC=%06x)\n", cpustate->PC);
987987   return 0; /* never reached, fatalerror won't return */
988988}
989989
990990static UINT32 bam2Error1(v60_state *cpustate)
991991{
992   fatalerror("CPU - BAM2 - 1 (cpustate->PC=%06x)", cpustate->PC);
992   fatalerror("CPU - BAM2 - 1 (cpustate->PC=%06x)\n", cpustate->PC);
993993   return 0; /* never reached, fatalerror won't return */
994994}
995995
996996static UINT32 bam2Error2(v60_state *cpustate)
997997{
998   fatalerror("CPU - BAM2 - 2 (cpustate->PC=%06x)", cpustate->PC);
998   fatalerror("CPU - BAM2 - 2 (cpustate->PC=%06x)\n", cpustate->PC);
999999   return 0; /* never reached, fatalerror won't return */
10001000}
10011001
10021002#ifdef UNUSED_FUNCTION
10031003static UINT32 bam2Error3(v60_state *cpustate)
10041004{
1005   fatalerror("CPU - BAM2 - 3 (cpustate->PC=%06x)", cpustate->PC);
1005   fatalerror("CPU - BAM2 - 3 (cpustate->PC=%06x)\n", cpustate->PC);
10061006   return 0; /* never reached, fatalerror won't return */
10071007}
10081008#endif
10091009
10101010static UINT32 bam2Error4(v60_state *cpustate)
10111011{
1012   fatalerror("CPU - BAM2 - 4 (cpustate->PC=%06x)", cpustate->PC);
1012   fatalerror("CPU - BAM2 - 4 (cpustate->PC=%06x)\n", cpustate->PC);
10131013   return 0; /* never reached, fatalerror won't return */
10141014}
10151015
10161016static UINT32 bam2Error5(v60_state *cpustate)
10171017{
1018   fatalerror("CPU - BAM2 - 5 (cpustate->PC=%06x)", cpustate->PC);
1018   fatalerror("CPU - BAM2 - 5 (cpustate->PC=%06x)\n", cpustate->PC);
10191019   return 0; /* never reached, fatalerror won't return */
10201020}
10211021
10221022static UINT32 bam2Error6(v60_state *cpustate)
10231023{
1024   fatalerror("CPU - BAM2 - 6 (cpustate->PC=%06x)", cpustate->PC);
1024   fatalerror("CPU - BAM2 - 6 (cpustate->PC=%06x)\n", cpustate->PC);
10251025   return 0; /* never reached, fatalerror won't return */
10261026}
10271027
trunk/src/emu/cpu/v60/am3.c
r17702r17703
718718
719719static UINT32 am3Immediate(v60_state *cpustate)
720720{
721   fatalerror("CPU - AM3 - IMM (cpustate->PC=%06x)", cpustate->PC);
721   fatalerror("CPU - AM3 - IMM (cpustate->PC=%06x)\n", cpustate->PC);
722722   return 0; /* never reached, fatalerror won't return */
723723}
724724
725725static UINT32 am3ImmediateQuick(v60_state *cpustate)
726726{
727   fatalerror("CPU - AM3 - IMMQ (cpustate->PC=%06x)", cpustate->PC);
727   fatalerror("CPU - AM3 - IMMQ (cpustate->PC=%06x)\n", cpustate->PC);
728728   return 0; /* never reached, fatalerror won't return */
729729}
730730
r17702r17703
735735
736736static UINT32 am3Error1(v60_state *cpustate)
737737{
738   fatalerror("CPU - AM3 - 1 (cpustate->PC=%06x)", cpustate->PC);
738   fatalerror("CPU - AM3 - 1 (cpustate->PC=%06x)\n", cpustate->PC);
739739   return 0; /* never reached, fatalerror won't return */
740740}
741741
742742static UINT32 am3Error2(v60_state *cpustate)
743743{
744   fatalerror("CPU - AM3 - 2 (cpustate->PC=%06x)", cpustate->PC);
744   fatalerror("CPU - AM3 - 2 (cpustate->PC=%06x)\n", cpustate->PC);
745745   return 0; /* never reached, fatalerror won't return */
746746}
747747
748748#ifdef UNUSED_FUNCTION
749749static UINT32 am3Error3(v60_state *cpustate)
750750{
751   fatalerror("CPU - AM3 - 3 (cpustate->PC=%06x)", cpustate->PC);
751   fatalerror("CPU - AM3 - 3 (cpustate->PC=%06x)\n", cpustate->PC);
752752   return 0; /* never reached, fatalerror won't return */
753753}
754754#endif
755755
756756static UINT32 am3Error4(v60_state *cpustate)
757757{
758   fatalerror("CPU - AM3 - 4 (cpustate->PC=%06x)", cpustate->PC);
758   fatalerror("CPU - AM3 - 4 (cpustate->PC=%06x)\n", cpustate->PC);
759759   return 0; /* never reached, fatalerror won't return */
760760}
761761
762762static UINT32 am3Error5(v60_state *cpustate)
763763{
764   fatalerror("CPU - AM3 - 5 (cpustate->PC=%06x)", cpustate->PC);
764   fatalerror("CPU - AM3 - 5 (cpustate->PC=%06x)\n", cpustate->PC);
765765   return 0; /* never reached, fatalerror won't return */
766766}
767767
trunk/src/emu/cpu/v60/op2.c
r17702r17703
255255
256256static UINT32 op5FUNHANDLED(v60_state *cpustate)
257257{
258   fatalerror("Unhandled 5F opcode at %08x", cpustate->PC);
258   fatalerror("Unhandled 5F opcode at %08x\n", cpustate->PC);
259259   return 0; /* never reached, fatalerror won't return */
260260}
261261
262262static UINT32 op5CUNHANDLED(v60_state *cpustate)
263263{
264   fatalerror("Unhandled 5C opcode at %08x", cpustate->PC);
264   fatalerror("Unhandled 5C opcode at %08x\n", cpustate->PC);
265265   return 0; /* never reached, fatalerror won't return */
266266}
267267
trunk/src/emu/cpu/v60/op12.c
r17702r17703
456456
457457   if (cpustate->op1 > 3)
458458   {
459      fatalerror("Illegal data field on opCHLVL, cpustate->PC=%x", cpustate->PC);
459      fatalerror("Illegal data field on opCHLVL, cpustate->PC=%x\n", cpustate->PC);
460460   }
461461
462462   oldPSW = v60_update_psw_for_exception(cpustate, 0, cpustate->op1);
r17702r17703
762762   }
763763   else
764764   {
765      fatalerror("Invalid operand on LDPR cpustate->PC=%x", cpustate->PC);
765      fatalerror("Invalid operand on LDPR cpustate->PC=%x\n", cpustate->PC);
766766   }
767767   F12END(cpustate);
768768}
r17702r17703
21002100      cpustate->modwritevalw = cpustate->reg[cpustate->op1 + 36];
21012101   else
21022102   {
2103      fatalerror("Invalid operand on STPR cpustate->PC=%x", cpustate->PC);
2103      fatalerror("Invalid operand on STPR cpustate->PC=%x\n", cpustate->PC);
21042104   }
21052105   F12WriteSecondOperand(cpustate, 2);
21062106   F12END(cpustate);
trunk/src/emu/cpu/v60/op5.c
r17702r17703
7979   if ((cpustate->TKCW & 0x1F0) & ((v60ReadPSW(cpustate) & 0x1F00) >> 4))
8080   {
8181      // @@@ FPU exception
82      fatalerror("Hit TRAPFL! cpustate->PC=%x", cpustate->PC);
82      fatalerror("Hit TRAPFL! cpustate->PC=%x\n", cpustate->PC);
8383   }
8484
8585   return 1;
trunk/src/emu/cpu/v60/op7a.c
r17702r17703
965965
966966static UINT32 op58UNHANDLED(v60_state *cpustate)
967967{
968   fatalerror("Unhandled 58 opcode at cpustate->PC: /%06x", cpustate->PC);
968   fatalerror("Unhandled 58 opcode at cpustate->PC: /%06x\n", cpustate->PC);
969969   return 0; /* never reached, fatalerror won't return */
970970}
971971
972972static UINT32 op5AUNHANDLED(v60_state *cpustate)
973973{
974   fatalerror("Unhandled 5A opcode at cpustate->PC: /%06x", cpustate->PC);
974   fatalerror("Unhandled 5A opcode at cpustate->PC: /%06x\n", cpustate->PC);
975975   return 0; /* never reached, fatalerror won't return */
976976}
977977
978978static UINT32 op5BUNHANDLED(v60_state *cpustate)
979979{
980   fatalerror("Unhandled 5B opcode at cpustate->PC: /%06x", cpustate->PC);
980   fatalerror("Unhandled 5B opcode at cpustate->PC: /%06x\n", cpustate->PC);
981981   return 0; /* never reached, fatalerror won't return */
982982}
983983
984984static UINT32 op5DUNHANDLED(v60_state *cpustate)
985985{
986   fatalerror("Unhandled 5D opcode at cpustate->PC: /%06x", cpustate->PC);
986   fatalerror("Unhandled 5D opcode at cpustate->PC: /%06x\n", cpustate->PC);
987987   return 0; /* never reached, fatalerror won't return */
988988}
989989
990990static UINT32 op59UNHANDLED(v60_state *cpustate)
991991{
992   fatalerror("Unhandled 59 opcode at cpustate->PC: /%06x", cpustate->PC);
992   fatalerror("Unhandled 59 opcode at cpustate->PC: /%06x\n", cpustate->PC);
993993   return 0; /* never reached, fatalerror won't return */
994994}
995995
trunk/src/emu/cpu/v60/v60.c
r17702r17703
317317
318318static UINT32 opUNHANDLED(v60_state *cpustate)
319319{
320   fatalerror("Unhandled OpCode found : %02x at %08x", OpRead16(cpustate, cpustate->PC), cpustate->PC);
320   fatalerror("Unhandled OpCode found : %02x at %08x\n", OpRead16(cpustate, cpustate->PC), cpustate->PC);
321321   return 0; /* never reached, fatalerror won't return */
322322}
323323
trunk/src/emu/cpu/dsp56k/dsp56ops.c
r17702r17703
21922192         break;
21932193
21942194      default:
2195         fatalerror("DSP56k - BAD EE value in andi operation") ;
2195         fatalerror("DSP56k - BAD EE value in andi operation\n") ;
21962196   }
21972197
21982198   /* S L E U N Z V C */
r17702r17703
44674467      case 0x0: rX = &R0;  nX = &N0;  break;
44684468      case 0x1: rX = &R1;  nX = &N1;  break;
44694469      case 0x2: rX = &R2;  nX = &N2;  break;
4470      case 0x3: fatalerror("Dsp56k: Error. execute_mm_table specified R3 as its first source!");  break;
4470      case 0x3: fatalerror("Dsp56k: Error. execute_mm_table specified R3 as its first source!\n");  break;
44714471   }
44724472
44734473   switch(mm)
r17702r17703
45224522   }
45234523
45244524   /* Should not get here */
4525   fatalerror("dsp56k: execute_q_table did something impossible!");
4525   fatalerror("dsp56k: execute_q_table did something impossible!\n");
45264526   return 0;
45274527}
45284528
r17702r17703
47854785
47864786   /* Can't do an R3 for S1 */
47874787   if (R.addr == &R3)
4788      fatalerror("Dsp56k: Error. Dual x memory data read specified R3 as its first source!");
4788      fatalerror("Dsp56k: Error. Dual x memory data read specified R3 as its first source!\n");
47894789
47904790   /* The note on A-142 is very interesting.
47914791       You can effectively access external memory in the last 64 bytes of X data memory! */
47924792   if (*((UINT16*)D2.addr) >= 0xffc0)
4793      fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.");
4793      fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.\n");
47944794
47954795   /* First memmove */
47964796   srcVal1 = cpustate->data->read_word(ADDRESS(*((UINT16*)R.addr)));
trunk/src/emu/cpu/e132xs/e132xs.c
r17702r17703
41944194
41954195INLINE void hyperstone_do(hyperstone_state *cpustate, struct regs_decode *decode)
41964196{
4197   fatalerror("Executed hyperstone_do instruction. PC = %08X", PPC);
4197   fatalerror("Executed hyperstone_do instruction. PC = %08X\n", PPC);
41984198}
41994199
42004200INLINE void hyperstone_ldwr(hyperstone_state *cpustate, struct regs_decode *decode)
trunk/src/emu/cpu/i386/i386op16.c
r17702r17703
29652965            UINT16 address, selector;
29662966            if( modrm >= 0xc0 )
29672967            {
2968               fatalerror("i386: groupFF_16 /%d NYI", (modrm >> 3) & 0x7);
2968               fatalerror("i386: groupFF_16 /%d NYI\n", (modrm >> 3) & 0x7);
29692969            }
29702970            else
29712971            {
r17702r17703
30123012
30133013            if( modrm >= 0xc0 )
30143014            {
3015               fatalerror("i386: groupFF_16 /%d NYI", (modrm >> 3) & 0x7);
3015               fatalerror("i386: groupFF_16 /%d NYI\n", (modrm >> 3) & 0x7);
30163016            }
30173017            else
30183018            {
r17702r17703
30523052         I386OP(invalid)(cpustate);
30533053         break;
30543054      default:
3055         fatalerror("i386: groupFF_16 /%d unimplemented", (modrm >> 3) & 0x7);
3055         fatalerror("i386: groupFF_16 /%d unimplemented\n", (modrm >> 3) & 0x7);
30563056         break;
30573057   }
30583058}
r17702r17703
32463246         break;
32473247
32483248      default:
3249         fatalerror("i386: group0F00_16 /%d unimplemented", (modrm >> 3) & 0x7);
3249         fatalerror("i386: group0F00_16 /%d unimplemented\n", (modrm >> 3) & 0x7);
32503250         break;
32513251   }
32523252}
r17702r17703
33503350            break;
33513351         }
33523352      default:
3353         fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2);
3353         fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2);
33543354         break;
33553355   }
33563356}
r17702r17703
34703470         }
34713471         break;
34723472      default:
3473         fatalerror("i386: group0FBA_16 /%d unknown", (modrm >> 3) & 0x7);
3473         fatalerror("i386: group0FBA_16 /%d unknown\n", (modrm >> 3) & 0x7);
34743474         break;
34753475   }
34763476}
r17702r17703
36763676   UINT16 selector;
36773677
36783678   if( modrm >= 0xc0 ) {
3679      fatalerror("i386: load_far_pointer16 NYI");
3679      fatalerror("i386: load_far_pointer16 NYI\n");
36803680   } else {
36813681      UINT32 ea = GetEA(cpustate,modrm,0);
36823682      STORE_REG16(modrm, READ16(cpustate,ea + 0));
trunk/src/emu/cpu/i386/x87ops.c
r17702r17703
42494249void x87_invalid(i386_state *cpustate, UINT8 modrm)
42504250{
42514251   // TODO
4252   fatalerror("x87 invalid instruction (PC:%.4x)", cpustate->pc);
4252   fatalerror("x87 invalid instruction (PC:%.4x)\n", cpustate->pc);
42534253}
42544254
42554255
trunk/src/emu/cpu/i386/pentops.c
r17702r17703
7575{
7676   UINT8 modm = FETCH(cpustate);
7777   if( modm >= 0xc0 ) {
78      fatalerror("pentium: cmpxchg8b_m64 - invalid modm");
78      fatalerror("pentium: cmpxchg8b_m64 - invalid modm\n");
7979   } else {
8080      UINT32 ea = GetEA(cpustate, modm, 0);
8181      UINT64 value = READ64(cpustate,ea);
r17702r17703
132132            GetNonTranslatedEA(cpustate, modm, NULL);
133133            break;
134134         default:
135            fatalerror("pentium: bad/unsupported 0f ae opcode");
135            fatalerror("pentium: bad/unsupported 0f ae opcode\n");
136136      }
137137   } else {
138      fatalerror("pentium: bad/unsupported 0f ae opcode");
138      fatalerror("pentium: bad/unsupported 0f ae opcode\n");
139139   }
140140}
141141
trunk/src/emu/cpu/i386/i386.c
r17702r17703
289289   UINT8 segment;
290290
291291   if( mod_rm >= 0xc0 )
292      fatalerror("i386: Called modrm_to_EA with modrm value %02X !",mod_rm);
292      fatalerror("i386: Called modrm_to_EA with modrm value %02X!\n",mod_rm);
293293
294294   if( cpustate->address_size ) {
295295      switch( rm )
r17702r17703
27192719static void report_unimplemented_opcode(i386_state *cpustate)
27202720{
27212721#ifndef DEBUG_MISSING_OPCODE
2722   fatalerror("i386: Unimplemented opcode %02X at %08X", cpustate->opcode, cpustate->pc - 1 );
2722   fatalerror("i386: Unimplemented opcode %02X at %08X\n", cpustate->opcode, cpustate->pc - 1 );
27232723#else
27242724   astring errmsg;
27252725   errmsg.cat("i386: Unimplemented opcode ");
trunk/src/emu/cpu/i386/i386ops.c
r17702r17703
694694      case 3: CYCLES(cpustate,CYCLES_MOV_REG_CR3); break;
695695      case 4: CYCLES(cpustate,1); break; // TODO
696696      default:
697         fatalerror("i386: mov_cr_r32 CR%d !", cr);
697         fatalerror("i386: mov_cr_r32 CR%d!\n", cr);
698698         break;
699699   }
700700}
r17702r17703
718718         CYCLES(cpustate,CYCLES_MOV_DR6_7_REG);
719719         break;
720720      default:
721         fatalerror("i386: mov_dr_r32 DR%d !", dr);
721         fatalerror("i386: mov_dr_r32 DR%d!\n", dr);
722722         break;
723723   }
724724}
r17702r17703
12011201         break;
12021202
12031203      default:
1204         fatalerror("i386: Invalid REP/opcode %02X combination",opcode);
1204         fatalerror("i386: Invalid REP/opcode %02X combination\n",opcode);
12051205         break;
12061206   }
12071207
r17702r17703
22042204         }
22052205         break;
22062206      default:
2207         fatalerror("i386: groupFE_8 /%d unimplemented", (modrm >> 3) & 0x7);
2207         fatalerror("i386: groupFE_8 /%d unimplemented\n", (modrm >> 3) & 0x7);
22082208         break;
22092209   }
22102210}
trunk/src/emu/cpu/i386/i486ops.c
r17702r17703
305305            break;
306306         }
307307      default:
308         fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2);
308         fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2);
309309         break;
310310   }
311311}
r17702r17703
414414            break;
415415         }
416416      default:
417         fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2);
417         fatalerror("i486: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2);
418418         break;
419419   }
420420}
trunk/src/emu/cpu/i386/i386op32.c
r17702r17703
27682768
27692769            if( modrm >= 0xc0 )
27702770            {
2771               fatalerror("i386: groupFF_32 /%d: NYI", (modrm >> 3) & 0x7);
2771               fatalerror("i386: groupFF_32 /%d: NYI\n", (modrm >> 3) & 0x7);
27722772            }
27732773            else
27742774            {
r17702r17703
28152815
28162816            if( modrm >= 0xc0 )
28172817            {
2818               fatalerror("i386: groupFF_32 /%d: NYI", (modrm >> 3) & 0x7);
2818               fatalerror("i386: groupFF_32 /%d: NYI\n", (modrm >> 3) & 0x7);
28192819            }
28202820            else
28212821            {
r17702r17703
28522852         }
28532853         break;
28542854      default:
2855         fatalerror("i386: groupFF_32 /%d unimplemented at %08X", (modrm >> 3) & 0x7, cpustate->pc-2);
2855         fatalerror("i386: groupFF_32 /%d unimplemented at %08X\n", (modrm >> 3) & 0x7, cpustate->pc-2);
28562856         break;
28572857   }
28582858}
r17702r17703
30443044         break;
30453045
30463046      default:
3047         fatalerror("i386: group0F00_32 /%d unimplemented", (modrm >> 3) & 0x7);
3047         fatalerror("i386: group0F00_32 /%d unimplemented\n", (modrm >> 3) & 0x7);
30483048         break;
30493049   }
30503050}
r17702r17703
31483148            break;
31493149         }
31503150      default:
3151         fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X", (modrm >> 3) & 0x7, cpustate->eip - 2);
3151         fatalerror("i386: unimplemented opcode 0x0f 01 /%d at %08X\n", (modrm >> 3) & 0x7, cpustate->eip - 2);
31523152         break;
31533153   }
31543154}
r17702r17703
32683268         }
32693269         break;
32703270      default:
3271         fatalerror("i386: group0FBA_32 /%d unknown", (modrm >> 3) & 0x7);
3271         fatalerror("i386: group0FBA_32 /%d unknown\n", (modrm >> 3) & 0x7);
32723272         break;
32733273   }
32743274}
r17702r17703
34743474   UINT16 selector;
34753475
34763476   if( modrm >= 0xc0 ) {
3477      fatalerror("i386: load_far_pointer32 NYI");
3477      fatalerror("i386: load_far_pointer32 NYI\n");
34783478   } else {
34793479      UINT32 ea = GetEA(cpustate,modrm,0);
34803480      STORE_REG32(modrm, READ32(cpustate,ea + 0));
trunk/src/emu/cpu/mc68hc11/hc11ops.c
r17702r17703
35383538
35393539static void HC11OP(invalid)(hc11_state *cpustate)
35403540{
3541   fatalerror("HC11: Invalid opcode 0x%02X at %04X", READ8(cpustate, cpustate->pc-1), cpustate->pc-1);
3541   fatalerror("HC11: Invalid opcode 0x%02X at %04X\n", READ8(cpustate, cpustate->pc-1), cpustate->pc-1);
35423542}
trunk/src/emu/cpu/dsp32/dsp32ops.c
r17702r17703
145145
146146void dsp32c_device::unimplemented(UINT32 op)
147147{
148    fatalerror("Unimplemented op @ %06X: %08X (dis=%02X, tbl=%03X)", PC - 4, op, op >> 25, op >> 21);
148    fatalerror("Unimplemented op @ %06X: %08X (dis=%02X, tbl=%03X)\n", PC - 4, op, op >> 25, op >> 21);
149149}
150150
151151
r17702r17703
449449
450450double dsp32c_device::dau_read_pi_special(int i)
451451{
452    fatalerror("Unimplemented dau_read_pi_special(%d)", i);
452    fatalerror("Unimplemented dau_read_pi_special(%d)\n", i);
453453   return 0;
454454}
455455
456456
457457void dsp32c_device::dau_write_pi_special(int i, double val)
458458{
459    fatalerror("Unimplemented dau_write_pi_special(%d)", i);
459    fatalerror("Unimplemented dau_write_pi_special(%d)\n", i);
460460}
461461
462462
r17702r17703
696696      case 46:   // !ireq2
697697      case 47:   // ireq2
698698      default:
699          fatalerror("Unimplemented condition: %X", cond);
699          fatalerror("Unimplemented condition: %X\n", cond);
700700   }
701701}
702702#endif
trunk/src/emu/cpu/drcbex64.c
r17702r17703
470470
471471      // everything else is unexpected
472472      default:
473         fatalerror("Unexpected parameter type");
473         fatalerror("Unexpected parameter type\n");
474474         break;
475475   }
476476}
r17702r17703
709709   // generate a little bit of glue code to set up the environment
710710   drccodeptr *cachetop = m_cache.begin_codegen(500);
711711   if (cachetop == NULL)
712      fatalerror("Out of cache space after a reset!");
712      fatalerror("Out of cache space after a reset!\n");
713713
714714   x86code *dst = (x86code *)*cachetop;
715715
r17702r17703
25952595      ((UINT32 *)src)[-1] = labelcodeptr - src;
25962596   }
25972597   else
2598      fatalerror("fixup_label called with invalid jmp source!");
2598      fatalerror("fixup_label called with invalid jmp source!\n");
25992599}
26002600
26012601
trunk/src/emu/cpu/drcbec.c
r17702r17703
548548         case MAKE_OPCODE_SHORT(OP_MAPVAR, 4, 0):   // MAPVAR  mapvar,value
549549
550550            // these opcodes should be processed at compile-time only
551            fatalerror("Unexpected opcode");
551            fatalerror("Unexpected opcode\n");
552552            break;
553553
554554         case MAKE_OPCODE_SHORT(OP_DEBUG, 4, 0):      // DEBUG   pc
r17702r17703
21022102            break;
21032103
21042104         default:
2105            fatalerror("Unexpected opcode!");
2105            fatalerror("Unexpected opcode!\n");
21062106            break;
21072107      }
21082108
r17702r17703
21932193         break;
21942194
21952195      default:
2196         fatalerror("Unexpected param->type");
2196         fatalerror("Unexpected param->type\n");
21972197         break;
21982198   }
21992199
trunk/src/emu/cpu/rsp/rspdrc.c
r17702r17703
486486   }
487487   else
488488   {
489      fatalerror("RSP: cfunc_get_cop0_reg: %d", reg);
489      fatalerror("RSP: cfunc_get_cop0_reg: %d\n", reg);
490490   }
491491}
492492
r17702r17703
34573457   }
34583458   catch (drcuml_block::abort_compilation &)
34593459   {
3460      fatalerror("Unable to generate static RSP code");
3460      fatalerror("Unable to generate static RSP code\n");
34613461   }
34623462}
34633463
r17702r17703
35793579{
35803580   rsp_state *rsp = (rsp_state *)param;
35813581   UINT32 opcode = rsp->impstate->arg0;
3582   fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)", rsp->pc, opcode, opcode >> 26, opcode & 0x3f);
3582   fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", rsp->pc, opcode, opcode >> 26, opcode & 0x3f);
35833583}
35843584
35853585
r17702r17703
35903590#ifdef UNUSED_CODE
35913591static void cfunc_fatalerror(void *param)
35923592{
3593   fatalerror("fatalerror");
3593   fatalerror("fatalerror\n");
35943594}
35953595#endif
35963596
trunk/src/emu/cpu/jaguar/jaguar.c
r17702r17703
496496      UINT32 op;
497497
498498      /* debugging */
499      //if (jaguar->PC < 0xf03000 || jaguar->PC > 0xf04000) { fatalerror("GPU: jaguar->PC = %06X (ppc = %06X)", jaguar->PC, jaguar->ppc); }
499      //if (jaguar->PC < 0xf03000 || jaguar->PC > 0xf04000) { fatalerror("GPU: jaguar->PC = %06X (ppc = %06X)\n", jaguar->PC, jaguar->ppc); }
500500      jaguar->ppc = jaguar->PC;
501501      debugger_instruction_hook(device, jaguar->PC);
502502
r17702r17703
535535      UINT32 op;
536536
537537      /* debugging */
538      //if (jaguar->PC < 0xf1b000 || jaguar->PC > 0xf1d000) { fatalerror(stderr, "DSP: jaguar->PC = %06X", jaguar->PC); }
538      //if (jaguar->PC < 0xf1b000 || jaguar->PC > 0xf1d000) { fatalerror(stderr, "DSP: jaguar->PC = %06X\n", jaguar->PC); }
539539      jaguar->ppc = jaguar->PC;
540540      debugger_instruction_hook(device, jaguar->PC);
541541
trunk/src/emu/cpu/powerpc/ppc_ops.c
r17702r17703
66#ifndef PPC_DRC
77static void ppc_unimplemented(UINT32 op)
88{
9   fatalerror("ppc: Unimplemented opcode %08X at %08X", op, ppc.pc);
9   fatalerror("ppc: Unimplemented opcode %08X at %08X\n", op, ppc.pc);
1010}
1111
1212static void ppc_addx(UINT32 op)
r17702r17703
16101610
16111611static void ppc_invalid(UINT32 op)
16121612{
1613   fatalerror("ppc: Invalid opcode %08X PC : %X", op, ppc.pc);
1613   fatalerror("ppc: Invalid opcode %08X PC : %X\n", op, ppc.pc);
16141614}
16151615#endif
16161616
r17702r17703
19511951   {
19521952      case 268:   REG(RT) = (UINT32)(ppc_read_timebase()); break;
19531953      case 269:   REG(RT) = (UINT32)(ppc_read_timebase() >> 32); break;
1954      default:   fatalerror("ppc: Invalid timebase register %d at %08X", x, ppc.pc); break;
1954      default:   fatalerror("ppc: Invalid timebase register %d at %08X\n", x, ppc.pc); break;
19551955   }
19561956}
19571957
trunk/src/emu/cpu/powerpc/ppc403.c
r17702r17703
6969      case DCR_DMACR3:   ppc.dma[3].cr = value; ppc403_dma_exec(3); break;
7070
7171      default:
72         fatalerror("ppc: set_dcr: Unimplemented DCR %X", dcr);
72         fatalerror("ppc: set_dcr: Unimplemented DCR %X\n", dcr);
7373         break;
7474   }
7575}
r17702r17703
110110      case DCR_DMACR3:   return ppc.dma[3].cr;
111111
112112      default:
113         fatalerror("ppc: get_dcr: Unimplemented DCR %X", dcr);
113         fatalerror("ppc: get_dcr: Unimplemented DCR %X\n", dcr);
114114         break;
115115   }
116116}
r17702r17703
232232               }
233233               break;
234234            case 3:
235               fatalerror("PPC: Watchdog Timer caused reset");
235               fatalerror("PPC: Watchdog Timer caused reset\n");
236236               break;
237237         }
238238      }
r17702r17703
395395      }
396396
397397      default:
398         fatalerror("ppc: Unhandled exception %d", exception);
398         fatalerror("ppc: Unhandled exception %d\n", exception);
399399         break;
400400   }
401401}
r17702r17703
452452   }
453453   else
454454   {
455      fatalerror("PPC: Unknown IRQ line %d", irqline);
455      fatalerror("PPC: Unknown IRQ line %d\n", irqline);
456456   }
457457}
458458
r17702r17703
565565      case 0x7:      return ppc.spu.sprc;
566566      case 0x8:      return ppc.spu.sptc;
567567      case 0x9:      return ppc.spu.sprb;
568      default:      fatalerror("ppc: spu_r: %02X", a & 0xf);
568      default:      fatalerror("ppc: spu_r: %02X\n", a & 0xf);
569569   }
570570}
571571
r17702r17703
671671         break;
672672
673673      default:
674         fatalerror("ppc: spu_w: %02X, %02X", a & 0xf, d);
674         fatalerror("ppc: spu_w: %02X, %02X\n", a & 0xf, d);
675675         break;
676676   }
677677   //mame_printf_debug("spu_w: %02X, %02X at %08X\n", a & 0xf, d, ppc.pc);
r17702r17703
821821#endif
822822               }
823823               else {
824                  fatalerror("ppc: dma_exec: buffered DMA to unknown peripheral ! (channel %d)", ch);
824                  fatalerror("ppc: dma_exec: buffered DMA to unknown peripheral ! (channel %d)\n", ch);
825825               }
826826
827827            }
828828            break;
829829
830830         case 1:      /* fly-by DMA */
831            fatalerror("ppc: dma_exec: fly-by DMA not implemented");
831            fatalerror("ppc: dma_exec: fly-by DMA not implemented\n");
832832            break;
833833
834834         case 2:      /* software initiated mem-to-mem DMA */
r17702r17703
879879                  }
880880                  break;
881881               default:
882                  fatalerror("dma: dma_exec: SW mem-to-mem DMA, width = %d", width);
882                  fatalerror("dma: dma_exec: SW mem-to-mem DMA, width = %d\n", width);
883883            }
884884            break;
885885
886886         case 3:      /* hardware initiated mem-to-mem DMA */
887            fatalerror("ppc: dma_exec: HW mem-to-mem DMA not implemented");
887            fatalerror("ppc: dma_exec: HW mem-to-mem DMA not implemented\n");
888888            break;
889889      }
890890
r17702r17703
892892
893893      /* DEBUG: check for not yet supported features */
894894      if( (ppc.dma[ch].cr & DMA_TCE) == 0 )
895         fatalerror("ppc: dma_exec: DMA_TCE == 0");
895         fatalerror("ppc: dma_exec: DMA_TCE == 0\n");
896896
897897      if( ppc.dma[ch].cr & DMA_CH )
898         fatalerror("ppc: dma_exec: DMA chaining not implemented");
898         fatalerror("ppc: dma_exec: DMA chaining not implemented\n");
899899
900900      /* generate interrupts */
901901      if( ppc.dma[ch].cr & DMA_CIE )
r17702r17703
931931
932932static UINT16 ppc403_read16_unaligned(address_space *space, UINT32 a)
933933{
934   fatalerror("ppc: Unaligned read16 %08X at %08X", a, ppc.pc);
934   fatalerror("ppc: Unaligned read16 %08X at %08X\n", a, ppc.pc);
935935   return 0;
936936}
937937
938938static UINT32 ppc403_read32_unaligned(address_space *space, UINT32 a)
939939{
940   fatalerror("ppc: Unaligned read32 %08X at %08X", a, ppc.pc);
940   fatalerror("ppc: Unaligned read32 %08X at %08X\n", a, ppc.pc);
941941   return 0;
942942}
943943
944944static void ppc403_write16_unaligned(address_space *space, UINT32 a, UINT16 d)
945945{
946   fatalerror("ppc: Unaligned write16 %08X, %04X at %08X", a, d, ppc.pc);
946   fatalerror("ppc: Unaligned write16 %08X, %04X at %08X\n", a, d, ppc.pc);
947947}
948948
949949static void ppc403_write32_unaligned(address_space *space, UINT32 a, UINT32 d)
950950{
951   fatalerror("ppc: Unaligned write32 %08X, %08X at %08X", a, d, ppc.pc);
951   fatalerror("ppc: Unaligned write32 %08X, %08X at %08X\n", a, d, ppc.pc);
952952}
953953
trunk/src/emu/cpu/powerpc/ppc602.c
r17702r17703
157157
158158
159159      default:
160         fatalerror("ppc: Unhandled exception %d", exception);
160         fatalerror("ppc: Unhandled exception %d\n", exception);
161161         break;
162162   }
163163}
trunk/src/emu/cpu/powerpc/ppcdrc.c
r17702r17703
912912   }
913913   catch (drcuml_block::abort_compilation &)
914914   {
915      fatalerror("Error generating PPC static handlers");
915      fatalerror("Error generating PPC static handlers\n");
916916   }
917917}
918918
r17702r17703
10961096{
10971097   powerpc_state *ppc = (powerpc_state *)param;
10981098   UINT32 opcode = ppc->impstate->arg0;
1099   fatalerror("PC=%08X: Unimplemented op %08X", ppc->pc, opcode);
1099   fatalerror("PC=%08X: Unimplemented op %08X\n", ppc->pc, opcode);
11001100}
11011101
11021102
trunk/src/emu/cpu/powerpc/ppc603.c
r17702r17703
160160         break;
161161
162162      default:
163         fatalerror("ppc: Unhandled exception %d", exception);
163         fatalerror("ppc: Unhandled exception %d\n", exception);
164164         break;
165165   }
166166}
trunk/src/emu/cpu/powerpc/ppc_mem.c
r17702r17703
176176   {
177177      /* direct store translation */
178178      if ((flags & PPC_TRANSLATE_NOEXCEPTION) == 0)
179         fatalerror("ppc: direct store translation not yet implemented");
179         fatalerror("ppc: direct store translation not yet implemented\n");
180180      return 0;
181181   }
182182   else
trunk/src/emu/cpu/powerpc/ppccom.c
r17702r17703
507507   {
508508      /* we don't support the MMU of the 403GCX */
509509      if (ppc->flavor == PPC_MODEL_403GCX && (ppc->msr & MSROEA_DR))
510         fatalerror("MMU enabled but not supported!");
510         fatalerror("MMU enabled but not supported!\n");
511511
512512      /* only check if PE is enabled */
513513      if (transtype == TRANSLATE_WRITE && (ppc->msr & MSR4XX_PE))
r17702r17703
20232023
20242024   /* check for unsupported features */
20252025   if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_TCE))
2026      fatalerror("ppc4xx_dma_exec: DMA_TCE == 0");
2026      fatalerror("ppc4xx_dma_exec: DMA_TCE == 0\n");
20272027
20282028   /* transfer mode */
20292029   switch ((dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_TM_MASK) >> 21)
r17702r17703
20582058
20592059      /* fly-by mode DMA */
20602060      case 1:
2061         fatalerror("ppc4xx_dma_exec: fly-by DMA not implemented");
2061         fatalerror("ppc4xx_dma_exec: fly-by DMA not implemented\n");
20622062         break;
20632063
20642064      /* software initiated memory-to-memory mode DMA */
r17702r17703
21142114
21152115      /* hardware initiated memory-to-memory mode DMA */
21162116      case 3:
2117         fatalerror("ppc4xx_dma_exec: HW mem-to-mem DMA not implemented");
2117         fatalerror("ppc4xx_dma_exec: HW mem-to-mem DMA not implemented\n");
21182118         break;
21192119   }
21202120}
r17702r17703
22252225   /* fail if we are going to overflow */
22262226   new_rxin = (ppc->spu.rxin + 1) % ARRAY_LENGTH(ppc->spu.rxbuffer);
22272227   if (new_rxin == ppc->spu.rxout)
2228      fatalerror("ppc4xx_spu_rx_data: buffer overrun!");
2228      fatalerror("ppc4xx_spu_rx_data: buffer overrun!\n");
22292229
22302230   /* store the data and accept the new in index */
22312231   ppc->spu.rxbuffer[ppc->spu.rxin] = data;
trunk/src/emu/cpu/powerpc/ppc.c
r17702r17703
671671      }
672672   }
673673
674   fatalerror("ppc: set_spr: unknown spr %d (%03X) !", spr, spr);
674   fatalerror("ppc: set_spr: unknown spr %d (%03X)!\n", spr, spr);
675675}
676676
677677INLINE UINT32 ppc_get_spr(int spr)
r17702r17703
739739      switch (spr)
740740      {
741741         case SPR603E_TBL_R:
742            fatalerror("ppc: get_spr: TBL_R ");
742            fatalerror("ppc: get_spr: TBL_R\n");
743743            break;
744744
745745         case SPR603E_TBU_R:
746            fatalerror("ppc: get_spr: TBU_R ");
746            fatalerror("ppc: get_spr: TBU_R\n");
747747            break;
748748
749749         case SPR603E_TBL_W:      return (UINT32)(ppc_read_timebase());
r17702r17703
782782      }
783783   }
784784
785   fatalerror("ppc: get_spr: unknown spr %d (%03X) !", spr, spr);
785   fatalerror("ppc: get_spr: unknown spr %d (%03X)!\n", spr, spr);
786786   return 0;
787787}
788788
r17702r17703
798798INLINE void ppc_set_msr(UINT32 value)
799799{
800800   if( value & (MSR_ILE | MSR_LE) )
801      fatalerror("ppc: set_msr: little_endian mode not supported !");
801      fatalerror("ppc: set_msr: little_endian mode not supported!\n");
802802
803803   MSR = value;
804804
r17702r17703
11521152
11531153   if (pll_config == -1)
11541154   {
1155      fatalerror("PPC: Invalid bus/multiplier combination (bus frequency = %d, multiplier = %1.1f)", config->bus_frequency, multiplier);
1155      fatalerror("PPC: Invalid bus/multiplier combination (bus frequency = %d, multiplier = %1.1f)\n", config->bus_frequency, multiplier);
11561156   }
11571157
11581158   ppc.hid1 = pll_config << 28;
trunk/src/emu/cpu/powerpc/drc_ops.c
r17702r17703
272272
273273   /* handle the results */
274274   if (!(result & RECOMPILE_SUCCESSFUL))
275      fatalerror("Unimplemented op %08X", *opptr);
275      fatalerror("Unimplemented op %08X\n", *opptr);
276276
277277   pcdelta = (INT8)(result >> 24);
278278   cycles = (INT8)(result >> 16);
trunk/src/emu/cpu/tms32010/32010dsm.c
r17702r17703
199199            case 'w':
200200               bit --;
201201               break;
202            default: fatalerror("Invalid instruction encoding '%s %s'",
202            default: fatalerror("Invalid instruction encoding '%s %s'\n",
203203               ops[0],ops[1]);
204204         }
205205      }
206206      if (bit != -1 )
207207      {
208         fatalerror("not enough bits in encoding '%s %s' %d",
208         fatalerror("not enough bits in encoding '%s %s' %d\n",
209209            ops[0],ops[1],bit);
210210      }
211211      while (isspace((UINT8)*p)) p++;
r17702r17703
289289         case 'w': w <<=1; w |= ((code & (1<<bit)) ? 1 : 0); bit--; break;
290290         case ' ': break;
291291         case '1': case '0':  bit--; break;
292         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d",code,bit);
292         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d\n",code,bit);
293293      }
294294      cp++;
295295   }
r17702r17703
321321            case 'S': sprintf(num,",%d",s); break;
322322            case 'W': sprintf(num,"%04Xh",w); break;
323323            default:
324               fatalerror("illegal escape character in format '%s'",Op[op].fmt);
324               fatalerror("illegal escape character in format '%s'\n",Op[op].fmt);
325325         }
326326         q = num; while (*q) *buffer++ = *q++;
327327         *buffer = '\0';
trunk/src/emu/cpu/sh2/sh2drc.c
r17702r17703
276276{
277277   sh2_state *sh2 = (sh2_state *)param;
278278   UINT16 opcode = sh2->arg0;
279   fatalerror("PC=%08X: Unimplemented op %04X", sh2->pc, opcode);
279   fatalerror("PC=%08X: Unimplemented op %04X\n", sh2->pc, opcode);
280280}
281281
282282/*-------------------------------------------------
r17702r17703
863863   }
864864   catch (drcuml_block::abort_compilation &)
865865   {
866      fatalerror("Unable to generate SH2 static code");
866      fatalerror("Unable to generate SH2 static code\n");
867867   }
868868
869869   sh2->cache_dirty = FALSE;
trunk/src/emu/cpu/sh2/sh2comn.c
r17702r17703
360360               {
361361                  //printf("dma stalled\n");
362362                  sh2->dma_timer_active[dma]=2;// mark as stalled
363                  fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode");
363                  fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode\n");
364364               }
365365            }
366366
trunk/src/emu/cpu/tms32051/32051ops.c
r17702r17703
269269
270270static void op_invalid(tms32051_state *cpustate)
271271{
272   fatalerror("32051: invalid op at %08X", cpustate->pc-1);
272   fatalerror("32051: invalid op at %08X\n", cpustate->pc-1);
273273}
274274
275275static void op_group_be(tms32051_state *cpustate);
r17702r17703
279279
280280static void op_abs(tms32051_state *cpustate)
281281{
282   fatalerror("32051: unimplemented op abs at %08X", cpustate->pc-1);
282   fatalerror("32051: unimplemented op abs at %08X\n", cpustate->pc-1);
283283}
284284
285285static void op_adcb(tms32051_state *cpustate)
286286{
287   fatalerror("32051: unimplemented op adcb at %08X", cpustate->pc-1);
287   fatalerror("32051: unimplemented op adcb at %08X\n", cpustate->pc-1);
288288}
289289
290290static void op_add_mem(tms32051_state *cpustate)
r17702r17703
339339
340340static void op_add_s16_mem(tms32051_state *cpustate)
341341{
342   fatalerror("32051: unimplemented op add s16 mem at %08X", cpustate->pc-1);
342   fatalerror("32051: unimplemented op add s16 mem at %08X\n", cpustate->pc-1);
343343}
344344
345345static void op_addb(tms32051_state *cpustate)
r17702r17703
351351
352352static void op_addc(tms32051_state *cpustate)
353353{
354   fatalerror("32051: unimplemented op addc at %08X", cpustate->pc-1);
354   fatalerror("32051: unimplemented op addc at %08X\n", cpustate->pc-1);
355355}
356356
357357static void op_adds(tms32051_state *cpustate)
358358{
359   fatalerror("32051: unimplemented op adds at %08X", cpustate->pc-1);
359   fatalerror("32051: unimplemented op adds at %08X\n", cpustate->pc-1);
360360}
361361
362362static void op_addt(tms32051_state *cpustate)
363363{
364   fatalerror("32051: unimplemented op addt at %08X", cpustate->pc-1);
364   fatalerror("32051: unimplemented op addt at %08X\n", cpustate->pc-1);
365365}
366366
367367static void op_and_mem(tms32051_state *cpustate)
368368{
369   fatalerror("32051: unimplemented op and mem at %08X", cpustate->pc-1);
369   fatalerror("32051: unimplemented op and mem at %08X\n", cpustate->pc-1);
370370}
371371
372372static void op_and_limm(tms32051_state *cpustate)
r17702r17703
381381
382382static void op_and_s16_limm(tms32051_state *cpustate)
383383{
384   fatalerror("32051: unimplemented op and s16 limm at %08X", cpustate->pc-1);
384   fatalerror("32051: unimplemented op and s16 limm at %08X\n", cpustate->pc-1);
385385}
386386
387387static void op_andb(tms32051_state *cpustate)
388388{
389   fatalerror("32051: unimplemented op andb at %08X", cpustate->pc-1);
389   fatalerror("32051: unimplemented op andb at %08X\n", cpustate->pc-1);
390390}
391391
392392static void op_bsar(tms32051_state *cpustate)
r17702r17703
520520
521521static void op_lact(tms32051_state *cpustate)
522522{
523   fatalerror("32051: unimplemented op lact at %08X", cpustate->pc-1);
523   fatalerror("32051: unimplemented op lact at %08X\n", cpustate->pc-1);
524524}
525525
526526static void op_lamm(tms32051_state *cpustate)
r17702r17703
550550
551551static void op_norm(tms32051_state *cpustate)
552552{
553   fatalerror("32051: unimplemented op norm at %08X", cpustate->pc-1);
553   fatalerror("32051: unimplemented op norm at %08X\n", cpustate->pc-1);
554554}
555555
556556static void op_or_mem(tms32051_state *cpustate)
r17702r17703
575575
576576static void op_or_s16_limm(tms32051_state *cpustate)
577577{
578   fatalerror("32051: unimplemented op or s16 limm at %08X", cpustate->pc-1);
578   fatalerror("32051: unimplemented op or s16 limm at %08X\n", cpustate->pc-1);
579579}
580580
581581static void op_orb(tms32051_state *cpustate)
r17702r17703
587587
588588static void op_rol(tms32051_state *cpustate)
589589{
590   fatalerror("32051: unimplemented op rol at %08X", cpustate->pc-1);
590   fatalerror("32051: unimplemented op rol at %08X\n", cpustate->pc-1);
591591}
592592
593593static void op_rolb(tms32051_state *cpustate)
r17702r17703
605605
606606static void op_ror(tms32051_state *cpustate)
607607{
608   fatalerror("32051: unimplemented op ror at %08X", cpustate->pc-1);
608   fatalerror("32051: unimplemented op ror at %08X\n", cpustate->pc-1);
609609}
610610
611611static void op_rorb(tms32051_state *cpustate)
612612{
613   fatalerror("32051: unimplemented op rorb at %08X", cpustate->pc-1);
613   fatalerror("32051: unimplemented op rorb at %08X\n", cpustate->pc-1);
614614}
615615
616616static void op_sacb(tms32051_state *cpustate)
r17702r17703
649649
650650static void op_sath(tms32051_state *cpustate)
651651{
652   fatalerror("32051: unimplemented op sath at %08X", cpustate->pc-1);
652   fatalerror("32051: unimplemented op sath at %08X\n", cpustate->pc-1);
653653}
654654
655655static void op_satl(tms32051_state *cpustate)
656656{
657   fatalerror("32051: unimplemented op satl at %08X", cpustate->pc-1);
657   fatalerror("32051: unimplemented op satl at %08X\n", cpustate->pc-1);
658658}
659659
660660static void op_sbb(tms32051_state *cpustate)
r17702r17703
666666
667667static void op_sbbb(tms32051_state *cpustate)
668668{
669   fatalerror("32051: unimplemented op sbbb at %08X", cpustate->pc-1);
669   fatalerror("32051: unimplemented op sbbb at %08X\n", cpustate->pc-1);
670670}
671671
672672static void op_sfl(tms32051_state *cpustate)
r17702r17703
707707
708708static void op_sfrb(tms32051_state *cpustate)
709709{
710   fatalerror("32051: unimplemented op sfrb at %08X", cpustate->pc-1);
710   fatalerror("32051: unimplemented op sfrb at %08X\n", cpustate->pc-1);
711711}
712712
713713static void op_sub_mem(tms32051_state *cpustate)
r17702r17703
733733
734734static void op_sub_s16_mem(tms32051_state *cpustate)
735735{
736   fatalerror("32051: unimplemented op sub s16 mem at %08X", cpustate->pc-1);
736   fatalerror("32051: unimplemented op sub s16 mem at %08X\n", cpustate->pc-1);
737737}
738738
739739static void op_sub_simm(tms32051_state *cpustate)
r17702r17703
767767
768768static void op_subb(tms32051_state *cpustate)
769769{
770   fatalerror("32051: unimplemented op subb at %08X", cpustate->pc-1);
770   fatalerror("32051: unimplemented op subb at %08X\n", cpustate->pc-1);
771771}
772772
773773static void op_subc(tms32051_state *cpustate)
774774{
775   fatalerror("32051: unimplemented op subc at %08X", cpustate->pc-1);
775   fatalerror("32051: unimplemented op subc at %08X\n", cpustate->pc-1);
776776}
777777
778778static void op_subs(tms32051_state *cpustate)
779779{
780   fatalerror("32051: unimplemented op subs at %08X", cpustate->pc-1);
780   fatalerror("32051: unimplemented op subs at %08X\n", cpustate->pc-1);
781781}
782782
783783static void op_subt(tms32051_state *cpustate)
784784{
785   fatalerror("32051: unimplemented op subt at %08X", cpustate->pc-1);
785   fatalerror("32051: unimplemented op subt at %08X\n", cpustate->pc-1);
786786}
787787
788788static void op_xor_mem(tms32051_state *cpustate)
r17702r17703
807807
808808static void op_xor_s16_limm(tms32051_state *cpustate)
809809{
810   fatalerror("32051: unimplemented op xor s16 limm at %08X", cpustate->pc-1);
810   fatalerror("32051: unimplemented op xor s16 limm at %08X\n", cpustate->pc-1);
811811}
812812
813813static void op_xorb(tms32051_state *cpustate)
814814{
815   fatalerror("32051: unimplemented op xorb at %08X", cpustate->pc-1);
815   fatalerror("32051: unimplemented op xorb at %08X\n", cpustate->pc-1);
816816}
817817
818818static void op_zalr(tms32051_state *cpustate)
819819{
820   fatalerror("32051: unimplemented op zalr at %08X", cpustate->pc-1);
820   fatalerror("32051: unimplemented op zalr at %08X\n", cpustate->pc-1);
821821}
822822
823823static void op_zap(tms32051_state *cpustate)
r17702r17703
911911
912912static void op_ldp_mem(tms32051_state *cpustate)
913913{
914   fatalerror("32051: unimplemented op ldp mem at %08X", cpustate->pc-1);
914   fatalerror("32051: unimplemented op ldp mem at %08X\n", cpustate->pc-1);
915915}
916916
917917static void op_ldp_imm(tms32051_state *cpustate)
r17702r17703
995995
996996static void op_banzd(tms32051_state *cpustate)
997997{
998   fatalerror("32051: unimplemented op banzd at %08X", cpustate->pc-1);
998   fatalerror("32051: unimplemented op banzd at %08X\n", cpustate->pc-1);
999999}
10001000
10011001static void op_bcnd(tms32051_state *cpustate)
r17702r17703
10841084
10851085static void op_cc(tms32051_state *cpustate)
10861086{
1087   fatalerror("32051: unimplemented op cc at %08X", cpustate->pc-1);
1087   fatalerror("32051: unimplemented op cc at %08X\n", cpustate->pc-1);
10881088}
10891089
10901090static void op_ccd(tms32051_state *cpustate)
r17702r17703
11041104
11051105static void op_intr(tms32051_state *cpustate)
11061106{
1107   fatalerror("32051: unimplemented op intr at %08X", cpustate->pc-1);
1107   fatalerror("32051: unimplemented op intr at %08X\n", cpustate->pc-1);
11081108}
11091109
11101110static void op_nmi(tms32051_state *cpustate)
11111111{
1112   fatalerror("32051: unimplemented op nmi at %08X", cpustate->pc-1);
1112   fatalerror("32051: unimplemented op nmi at %08X\n", cpustate->pc-1);
11131113}
11141114
11151115static void op_retc(tms32051_state *cpustate)
r17702r17703
11551155
11561156static void op_reti(tms32051_state *cpustate)
11571157{
1158   fatalerror("32051: unimplemented op reti at %08X", cpustate->pc-1);
1158   fatalerror("32051: unimplemented op reti at %08X\n", cpustate->pc-1);
11591159}
11601160
11611161static void op_trap(tms32051_state *cpustate)
11621162{
1163   fatalerror("32051: unimplemented op trap at %08X", cpustate->pc-1);
1163   fatalerror("32051: unimplemented op trap at %08X\n", cpustate->pc-1);
11641164}
11651165
11661166static void op_xc(tms32051_state *cpustate)
r17702r17703
12131213
12141214static void op_bldd_sbmar(tms32051_state *cpustate)
12151215{
1216   fatalerror("32051: unimplemented op bldd sbmar at %08X", cpustate->pc-1);
1216   fatalerror("32051: unimplemented op bldd sbmar at %08X\n", cpustate->pc-1);
12171217}
12181218
12191219static void op_bldd_dbmar(tms32051_state *cpustate)
r17702r17703
12501250
12511251static void op_blpd_bmar(tms32051_state *cpustate)
12521252{
1253   fatalerror("32051: unimplemented op bpld bmar at %08X", cpustate->pc-1);
1253   fatalerror("32051: unimplemented op bpld bmar at %08X\n", cpustate->pc-1);
12541254}
12551255
12561256static void op_blpd_imm(tms32051_state *cpustate)
r17702r17703
12731273
12741274static void op_dmov(tms32051_state *cpustate)
12751275{
1276   fatalerror("32051: unimplemented op dmov at %08X", cpustate->pc-1);
1276   fatalerror("32051: unimplemented op dmov at %08X\n", cpustate->pc-1);
12771277}
12781278
12791279static void op_in(tms32051_state *cpustate)
12801280{
1281   fatalerror("32051: unimplemented op in at %08X", cpustate->pc-1);
1281   fatalerror("32051: unimplemented op in at %08X\n", cpustate->pc-1);
12821282}
12831283
12841284static void op_lmmr(tms32051_state *cpustate)
r17702r17703
12991299
13001300static void op_out(tms32051_state *cpustate)
13011301{
1302   fatalerror("32051: unimplemented op out at %08X", cpustate->pc-1);
1302   fatalerror("32051: unimplemented op out at %08X\n", cpustate->pc-1);
13031303}
13041304
13051305static void op_smmr(tms32051_state *cpustate)
r17702r17703
13731373
13741374static void op_cpl_dbmr(tms32051_state *cpustate)
13751375{
1376   fatalerror("32051: unimplemented op cpl dbmr at %08X", cpustate->pc-1);
1376   fatalerror("32051: unimplemented op cpl dbmr at %08X\n", cpustate->pc-1);
13771377}
13781378
13791379static void op_cpl_imm(tms32051_state *cpustate)
r17702r17703
14181418
14191419static void op_xpl_dbmr(tms32051_state *cpustate)
14201420{
1421   fatalerror("32051: unimplemented op xpl dbmr at %08X", cpustate->pc-1);
1421   fatalerror("32051: unimplemented op xpl dbmr at %08X\n", cpustate->pc-1);
14221422}
14231423
14241424static void op_xpl_imm(tms32051_state *cpustate)
14251425{
1426   fatalerror("32051: unimplemented op xpl imm at %08X", cpustate->pc-1);
1426   fatalerror("32051: unimplemented op xpl imm at %08X\n", cpustate->pc-1);
14271427}
14281428
14291429static void op_apac(tms32051_state *cpustate)
r17702r17703
14361436
14371437static void op_lph(tms32051_state *cpustate)
14381438{
1439   fatalerror("32051: unimplemented op lph at %08X", cpustate->pc-1);
1439   fatalerror("32051: unimplemented op lph at %08X\n", cpustate->pc-1);
14401440}
14411441
14421442static void op_lt(tms32051_state *cpustate)
r17702r17703
14741474
14751475static void op_ltd(tms32051_state *cpustate)
14761476{
1477   fatalerror("32051: unimplemented op ltd at %08X", cpustate->pc-1);
1477   fatalerror("32051: unimplemented op ltd at %08X\n", cpustate->pc-1);
14781478}
14791479
14801480static void op_ltp(tms32051_state *cpustate)
14811481{
1482   fatalerror("32051: unimplemented op ltp at %08X", cpustate->pc-1);
1482   fatalerror("32051: unimplemented op ltp at %08X\n", cpustate->pc-1);
14831483}
14841484
14851485static void op_lts(tms32051_state *cpustate)
14861486{
1487   fatalerror("32051: unimplemented op lts at %08X", cpustate->pc-1);
1487   fatalerror("32051: unimplemented op lts at %08X\n", cpustate->pc-1);
14881488}
14891489
14901490static void op_mac(tms32051_state *cpustate)
14911491{
1492   fatalerror("32051: unimplemented op mac at %08X", cpustate->pc-1);
1492   fatalerror("32051: unimplemented op mac at %08X\n", cpustate->pc-1);
14931493}
14941494
14951495static void op_macd(tms32051_state *cpustate)
14961496{
1497   fatalerror("32051: unimplemented op macd at %08X", cpustate->pc-1);
1497   fatalerror("32051: unimplemented op macd at %08X\n", cpustate->pc-1);
14981498}
14991499
15001500static void op_madd(tms32051_state *cpustate)
15011501{
1502   fatalerror("32051: unimplemented op madd at %08X", cpustate->pc-1);
1502   fatalerror("32051: unimplemented op madd at %08X\n", cpustate->pc-1);
15031503}
15041504
15051505static void op_mads(tms32051_state *cpustate)
15061506{
1507   fatalerror("32051: unimplemented op mads at %08X", cpustate->pc-1);
1507   fatalerror("32051: unimplemented op mads at %08X\n", cpustate->pc-1);
15081508}
15091509
15101510static void op_mpy_mem(tms32051_state *cpustate)
r17702r17703
15191519
15201520static void op_mpy_simm(tms32051_state *cpustate)
15211521{
1522   fatalerror("32051: unimplemented op mpy simm at %08X", cpustate->pc-1);
1522   fatalerror("32051: unimplemented op mpy simm at %08X\n", cpustate->pc-1);
15231523}
15241524
15251525static void op_mpy_limm(tms32051_state *cpustate)
15261526{
1527   fatalerror("32051: unimplemented op mpy limm at %08X", cpustate->pc-1);
1527   fatalerror("32051: unimplemented op mpy limm at %08X\n", cpustate->pc-1);
15281528}
15291529
15301530static void op_mpya(tms32051_state *cpustate)
15311531{
1532   fatalerror("32051: unimplemented op mpya at %08X", cpustate->pc-1);
1532   fatalerror("32051: unimplemented op mpya at %08X\n", cpustate->pc-1);
15331533}
15341534
15351535static void op_mpys(tms32051_state *cpustate)
15361536{
1537   fatalerror("32051: unimplemented op mpys at %08X", cpustate->pc-1);
1537   fatalerror("32051: unimplemented op mpys at %08X\n", cpustate->pc-1);
15381538}
15391539
15401540static void op_mpyu(tms32051_state *cpustate)
15411541{
1542   fatalerror("32051: unimplemented op mpyu at %08X", cpustate->pc-1);
1542   fatalerror("32051: unimplemented op mpyu at %08X\n", cpustate->pc-1);
15431543}
15441544
15451545static void op_pac(tms32051_state *cpustate)
15461546{
1547   fatalerror("32051: unimplemented op pac at %08X", cpustate->pc-1);
1547   fatalerror("32051: unimplemented op pac at %08X\n", cpustate->pc-1);
15481548}
15491549
15501550static void op_spac(tms32051_state *cpustate)
15511551{
1552   fatalerror("32051: unimplemented op spac at %08X", cpustate->pc-1);
1552   fatalerror("32051: unimplemented op spac at %08X\n", cpustate->pc-1);
15531553}
15541554
15551555static void op_sph(tms32051_state *cpustate)
r17702r17703
15631563
15641564static void op_spl(tms32051_state *cpustate)
15651565{
1566   fatalerror("32051: unimplemented op spl at %08X", cpustate->pc-1);
1566   fatalerror("32051: unimplemented op spl at %08X\n", cpustate->pc-1);
15671567}
15681568
15691569static void op_spm(tms32051_state *cpustate)
r17702r17703
15751575
15761576static void op_sqra(tms32051_state *cpustate)
15771577{
1578   fatalerror("32051: unimplemented op sqra at %08X", cpustate->pc-1);
1578   fatalerror("32051: unimplemented op sqra at %08X\n", cpustate->pc-1);
15791579}
15801580
15811581static void op_sqrs(tms32051_state *cpustate)
15821582{
1583   fatalerror("32051: unimplemented op sqrs at %08X", cpustate->pc-1);
1583   fatalerror("32051: unimplemented op sqrs at %08X\n", cpustate->pc-1);
15841584}
15851585
15861586static void op_zpr(tms32051_state *cpustate)
15871587{
1588   fatalerror("32051: unimplemented op zpr at %08X", cpustate->pc-1);
1588   fatalerror("32051: unimplemented op zpr at %08X\n", cpustate->pc-1);
15891589}
15901590
15911591static void op_bit(tms32051_state *cpustate)
r17702r17703
16241624
16251625static void op_clrc_hold(tms32051_state *cpustate)
16261626{
1627   fatalerror("32051: unimplemented op clrc hold at %08X", cpustate->pc-1);
1627   fatalerror("32051: unimplemented op clrc hold at %08X\n", cpustate->pc-1);
16281628}
16291629
16301630static void op_clrc_tc(tms32051_state *cpustate)
16311631{
1632   fatalerror("32051: unimplemented op clrc tc at %08X", cpustate->pc-1);
1632   fatalerror("32051: unimplemented op clrc tc at %08X\n", cpustate->pc-1);
16331633}
16341634
16351635static void op_clrc_carry(tms32051_state *cpustate)
16361636{
1637   fatalerror("32051: unimplemented op clrc carry at %08X", cpustate->pc-1);
1637   fatalerror("32051: unimplemented op clrc carry at %08X\n", cpustate->pc-1);
16381638}
16391639
16401640static void op_clrc_cnf(tms32051_state *cpustate)
r17702r17703
16551655
16561656static void op_clrc_xf(tms32051_state *cpustate)
16571657{
1658   fatalerror("32051: unimplemented op clrc xf at %08X", cpustate->pc-1);
1658   fatalerror("32051: unimplemented op clrc xf at %08X\n", cpustate->pc-1);
16591659}
16601660
16611661static void op_idle(tms32051_state *cpustate)
16621662{
1663   fatalerror("32051: unimplemented op idle at %08X", cpustate->pc-1);
1663   fatalerror("32051: unimplemented op idle at %08X\n", cpustate->pc-1);
16641664}
16651665
16661666static void op_idle2(tms32051_state *cpustate)
16671667{
1668   fatalerror("32051: unimplemented op idle2 at %08X", cpustate->pc-1);
1668   fatalerror("32051: unimplemented op idle2 at %08X\n", cpustate->pc-1);
16691669}
16701670
16711671static void op_lst_st0(tms32051_state *cpustate)
16721672{
1673   fatalerror("32051: unimplemented op lst st0 at %08X", cpustate->pc-1);
1673   fatalerror("32051: unimplemented op lst st0 at %08X\n", cpustate->pc-1);
16741674}
16751675
16761676static void op_lst_st1(tms32051_state *cpustate)
16771677{
1678   fatalerror("32051: unimplemented op lst st1 at %08X", cpustate->pc-1);
1678   fatalerror("32051: unimplemented op lst st1 at %08X\n", cpustate->pc-1);
16791679}
16801680
16811681static void op_pop(tms32051_state *cpustate)
r17702r17703
16871687
16881688static void op_popd(tms32051_state *cpustate)
16891689{
1690   fatalerror("32051: unimplemented op popd at %08X", cpustate->pc-1);
1690   fatalerror("32051: unimplemented op popd at %08X\n", cpustate->pc-1);
16911691}
16921692
16931693static void op_pshd(tms32051_state *cpustate)
16941694{
1695   fatalerror("32051: unimplemented op pshd at %08X", cpustate->pc-1);
1695   fatalerror("32051: unimplemented op pshd at %08X\n", cpustate->pc-1);
16961696}
16971697
16981698static void op_push(tms32051_state *cpustate)
16991699{
1700   fatalerror("32051: unimplemented op push at %08X", cpustate->pc-1);
1700   fatalerror("32051: unimplemented op push at %08X\n", cpustate->pc-1);
17011701}
17021702
17031703static void op_rpt_mem(tms32051_state *cpustate)
r17702r17703
17411741
17421742static void op_rptz(tms32051_state *cpustate)
17431743{
1744   fatalerror("32051: unimplemented op rptz at %08X", cpustate->pc-1);
1744   fatalerror("32051: unimplemented op rptz at %08X\n", cpustate->pc-1);
17451745}
17461746
17471747static void op_setc_ov(tms32051_state *cpustate)
r17702r17703
17601760
17611761static void op_setc_hold(tms32051_state *cpustate)
17621762{
1763   fatalerror("32051: unimplemented op setc hold at %08X", cpustate->pc-1);
1763   fatalerror("32051: unimplemented op setc hold at %08X\n", cpustate->pc-1);
17641764}
17651765
17661766static void op_setc_tc(tms32051_state *cpustate)
17671767{
1768   fatalerror("32051: unimplemented op setc tc at %08X", cpustate->pc-1);
1768   fatalerror("32051: unimplemented op setc tc at %08X\n", cpustate->pc-1);
17691769}
17701770
17711771static void op_setc_carry(tms32051_state *cpustate)
17721772{
1773   fatalerror("32051: unimplemented op setc carry at %08X", cpustate->pc-1);
1773   fatalerror("32051: unimplemented op setc carry at %08X\n", cpustate->pc-1);
17741774}
17751775
17761776static void op_setc_xf(tms32051_state *cpustate)
17771777{
1778   fatalerror("32051: unimplemented op setc xf at %08X", cpustate->pc-1);
1778   fatalerror("32051: unimplemented op setc xf at %08X\n", cpustate->pc-1);
17791779}
17801780
17811781static void op_setc_cnf(tms32051_state *cpustate)
r17702r17703
17961796
17971797static void op_sst_st0(tms32051_state *cpustate)
17981798{
1799   fatalerror("32051: unimplemented op sst st0 at %08X", cpustate->pc-1);
1799   fatalerror("32051: unimplemented op sst st0 at %08X\n", cpustate->pc-1);
18001800}
18011801
18021802static void op_sst_st1(tms32051_state *cpustate)
18031803{
1804   fatalerror("32051: unimplemented op sst st1 at %08X", cpustate->pc-1);
1804   fatalerror("32051: unimplemented op sst st1 at %08X\n", cpustate->pc-1);
18051805}
trunk/src/emu/cpu/cosmac/cosmac.c
r17702r17703
219219   // or error out if none provided
220220   else
221221   {
222      fatalerror("COSMAC_INTERFACE for cpu '%s' not defined!", tag());
222      fatalerror("COSMAC_INTERFACE for cpu '%s' not defined!\n", tag());
223223   }
224224}
225225
trunk/src/emu/cpu/mips/mips3drc.c
r17702r17703
397397   /* allocate enough space for the cache and the core */
398398   cache = auto_alloc(device->machine(), drc_cache(CACHE_SIZE + sizeof(*mips3)));
399399   if (cache == NULL)
400      fatalerror("Unable to allocate cache of size %d", (UINT32)(CACHE_SIZE + sizeof(*mips3)));
400      fatalerror("Unable to allocate cache of size %d\n", (UINT32)(CACHE_SIZE + sizeof(*mips3)));
401401
402402   /* allocate the core memory */
403403   *(mips3_state **)device->token() = mips3 = (mips3_state *)cache->alloc_near(sizeof(*mips3));
r17702r17703
744744   }
745745   catch (drcuml_block::abort_compilation &)
746746   {
747      fatalerror("Unrecoverable error generating static code");
747      fatalerror("Unrecoverable error generating static code\n");
748748   }
749749}
750750
r17702r17703
967967{
968968   mips3_state *mips3 = (mips3_state *)param;
969969   UINT32 opcode = mips3->impstate->arg0;
970   fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)", mips3->pc, opcode, opcode >> 26, opcode & 0x3f);
970   fatalerror("PC=%08X: Unimplemented op %08X (%02X,%02X)\n", mips3->pc, opcode, opcode >> 26, opcode & 0x3f);
971971}
972972
973973
trunk/src/emu/cpu/mips/mips3com.c
r17702r17703
857857         return 0x2700;
858858
859859      default:
860         fatalerror("Unknown MIPS flavor specified");
860         fatalerror("Unknown MIPS flavor specified\n");
861861   }
862862   return 0x2000;
863863}
trunk/src/emu/cpu/mips/mips3.c
r17702r17703
688688         /* update interrupts and cycle counting */
689689         UINT32 diff = mips3.core.cpr[0][idx] ^ val;
690690//          if (val & 0xe0)
691//              fatalerror("System set 64-bit addressing mode, SR=%08X", val);
691//              fatalerror("System set 64-bit addressing mode, SR=%08X\n", val);
692692         mips3.core.cpr[0][idx] = val;
693693         if (diff & 0x8000)
694694            mips3com_update_cycle_counting(&mips3.core);
trunk/src/emu/cpu/drcbeut.c
r17702r17703
561561   {
562562      // fatal if we were a leftover
563563      if (fatal_on_leftovers && curlabel->m_codeptr == NULL)
564         fatalerror("Label %08X never defined!", curlabel->m_label.label());
564         fatalerror("Label %08X never defined!\n", curlabel->m_label.label());
565565
566566      // free the label
567567      m_cache.dealloc(curlabel, sizeof(*curlabel));
trunk/src/emu/cpu/z80/z80daisy.c
r17702r17703
6262      // find the device
6363      device_t *target = cpudevice->siblingdevice(daisy->devname);
6464      if (target == NULL)
65         fatalerror("Unable to locate device '%s'", daisy->devname);
65         fatalerror("Unable to locate device '%s'\n", daisy->devname);
6666
6767      // make sure it has an interface
6868      device_z80daisy_interface *intf;
6969      if (!target->interface(intf))
70         fatalerror("Device '%s' does not implement the z80daisy interface!", daisy->devname);
70         fatalerror("Device '%s' does not implement the z80daisy interface!\n", daisy->devname);
7171
7272      // append to the end
7373      *tailptr = auto_alloc(cpudevice->machine(), daisy_entry(target));
trunk/src/emu/cpu/i960/i960.c
r17702r17703
109109      i960->IP   = iac[3];
110110      break;
111111   default:
112      fatalerror("I960: %x: IAC %08x %08x %08x %08x", i960->PIP, iac[0], iac[1], iac[2], iac[3]);
112      fatalerror("I960: %x: IAC %08x %08x %08x %08x\n", i960->PIP, iac[0], iac[1], iac[2], iac[3]);
113113      break;
114114   }
115115}
r17702r17703
157157         return ret;
158158
159159      default:
160         fatalerror("I960: %x: unhandled MEMB mode %x", i960->PIP, mode);
160         fatalerror("I960: %x: unhandled MEMB mode %x\n", i960->PIP, mode);
161161         return 0;
162162      }
163163   }
r17702r17703
192192   if(!(opcode & 0x00002000))
193193      i960->r[(opcode>>19) & 0x1f] = val;
194194   else {
195      fatalerror("I960: %x: set_ri on literal?", i960->PIP);
195      fatalerror("I960: %x: set_ri on literal?\n", i960->PIP);
196196   }
197197}
198198
r17702r17703
204204      i960->r[((opcode>>19) & 0x1f)+1] = val2;
205205   }
206206   else {
207      fatalerror("I960: %x: set_ri2 on literal?", i960->PIP);
207      fatalerror("I960: %x: set_ri2 on literal?\n", i960->PIP);
208208   }
209209}
210210
r17702r17703
214214      i960->r[(opcode>>19) & 0x1f] = val;
215215      i960->r[((opcode>>19) & 0x1f)+1] = val >> 32;
216216   } else
217      fatalerror("I960: %x: set_ri64 on literal?", i960->PIP);
217      fatalerror("I960: %x: set_ri64 on literal?\n", i960->PIP);
218218}
219219
220220INLINE double get_1_rif(i960_state_t *i960, UINT32 opcode)
r17702r17703
252252   else if(!(opcode & 0x00e00000))
253253      i960->fp[(opcode>>19) & 3] = val;
254254   else
255      fatalerror("I960: %x: set_rif on literal?", i960->PIP);
255      fatalerror("I960: %x: set_rif on literal?\n", i960->PIP);
256256}
257257
258258INLINE double get_1_rifl(i960_state_t *i960, UINT32 opcode)
r17702r17703
296296   } else if(!(opcode & 0x00e00000))
297297      i960->fp[(opcode>>19) & 3] = val;
298298   else
299      fatalerror("I960: %x: set_rifl on literal?", i960->PIP);
299      fatalerror("I960: %x: set_rifl on literal?\n", i960->PIP);
300300}
301301
302302INLINE UINT32 get_1_ci(i960_state_t *i960, UINT32 opcode)
r17702r17703
608608      break;
609609
610610   default:
611      fatalerror("I960: %x: Unsupported return mode %d", i960->PIP, i960->r[I960_PFP] & 7);
611      fatalerror("I960: %x: Unsupported return mode %d\n", i960->PIP, i960->r[I960_PFP] & 7);
612612   }
613613}
614614
r17702r17703
950950            break;
951951
952952         default:
953            fatalerror("I960: %x: Unhandled 58.%x", i960->PIP, (opcode >> 7) & 0xf);
953            fatalerror("I960: %x: Unhandled 58.%x\n", i960->PIP, (opcode >> 7) & 0xf);
954954         }
955955         break;
956956
r17702r17703
10361036            break;
10371037
10381038         default:
1039            fatalerror("I960: %x: Unhandled 59.%x", i960->PIP, (opcode >> 7) & 0xf);
1039            fatalerror("I960: %x: Unhandled 59.%x\n", i960->PIP, (opcode >> 7) & 0xf);
10401040         }
10411041         break;
10421042
r17702r17703
11171117            break;
11181118
11191119         default:
1120            fatalerror("I960: %x: Unhandled 5a.%x", i960->PIP, (opcode >> 7) & 0xf);
1120            fatalerror("I960: %x: Unhandled 5a.%x\n", i960->PIP, (opcode >> 7) & 0xf);
11211121         }
11221122         break;
11231123
r17702r17703
11601160            break;
11611161
11621162         default:
1163            fatalerror("I960: %x: Unhandled 5b.%x", i960->PIP, (opcode >> 7) & 0xf);
1163            fatalerror("I960: %x: Unhandled 5b.%x\n", i960->PIP, (opcode >> 7) & 0xf);
11641164         }
11651165         break;
11661166
r17702r17703
11731173            break;
11741174
11751175         default:
1176            fatalerror("I960: %x: Unhandled 5c.%x", i960->PIP, (opcode >> 7) & 0xf);
1176            fatalerror("I960: %x: Unhandled 5c.%x\n", i960->PIP, (opcode >> 7) & 0xf);
11771177         }
11781178         break;
11791179
r17702r17703
11901190            break;
11911191
11921192         default:
1193            fatalerror("I960: %x: Unhandled 5d.%x", i960->PIP, (opcode >> 7) & 0xf);
1193            fatalerror("I960: %x: Unhandled 5d.%x\n", i960->PIP, (opcode >> 7) & 0xf);
11941194         }
11951195         break;
11961196
r17702r17703
12071207            break;
12081208
12091209         default:
1210            fatalerror("I960: %x: Unhandled 5e.%x", i960->PIP, (opcode >> 7) & 0xf);
1210            fatalerror("I960: %x: Unhandled 5e.%x\n", i960->PIP, (opcode >> 7) & 0xf);
12111211         }
12121212         break;
12131213
r17702r17703
12241224            break;
12251225
12261226         default:
1227            fatalerror("I960: %x: Unhandled 5f.%x", i960->PIP, (opcode >> 7) & 0xf);
1227            fatalerror("I960: %x: Unhandled 5f.%x\n", i960->PIP, (opcode >> 7) & 0xf);
12281228         }
12291229         break;
12301230
r17702r17703
12581258            break;
12591259
12601260         default:
1261            fatalerror("I960: %x: Unhandled 60.%x", i960->PIP, (opcode >> 7) & 0xf);
1261            fatalerror("I960: %x: Unhandled 60.%x\n", i960->PIP, (opcode >> 7) & 0xf);
12621262         }
12631263         break;
12641264
r17702r17703
13211321            break;
13221322
13231323         default:
1324            fatalerror("I960: %x: Unhandled 64.%x", i960->PIP, (opcode >> 7) & 0xf);
1324            fatalerror("I960: %x: Unhandled 64.%x\n", i960->PIP, (opcode >> 7) & 0xf);
13251325         }
13261326         break;
13271327
r17702r17703
13361336            break;
13371337
13381338         default:
1339            fatalerror("I960: %x: Unhandled 65.%x", i960->PIP, (opcode >> 7) & 0xf);
1339            fatalerror("I960: %x: Unhandled 65.%x\n", i960->PIP, (opcode >> 7) & 0xf);
13401340         }
13411341         break;
13421342
r17702r17703
13601360            break;
13611361
13621362         default:
1363            fatalerror("I960: %x: Unhandled 66.%x", i960->PIP, (opcode >> 7) & 0xf);
1363            fatalerror("I960: %x: Unhandled 66.%x\n", i960->PIP, (opcode >> 7) & 0xf);
13641364         }
13651365         break;
13661366
r17702r17703
14071407            break;
14081408
14091409         default:
1410            fatalerror("I960: %x: Unhandled 67.%x", i960->PIP, (opcode >> 7) & 0xf);
1410            fatalerror("I960: %x: Unhandled 67.%x\n", i960->PIP, (opcode >> 7) & 0xf);
14111411         }
14121412         break;
14131413
r17702r17703
14801480            break;
14811481
14821482         default:
1483            fatalerror("I960: %x: Unhandled 68.%x", i960->PIP, (opcode >> 7) & 0xf);
1483            fatalerror("I960: %x: Unhandled 68.%x\n", i960->PIP, (opcode >> 7) & 0xf);
14841484         }
14851485         break;
14861486
r17702r17703
15511551            break;
15521552
15531553         default:
1554            fatalerror("I960: %x: Unhandled 69.%x", i960->PIP, (opcode >> 7) & 0xf);
1554            fatalerror("I960: %x: Unhandled 69.%x\n", i960->PIP, (opcode >> 7) & 0xf);
15551555         }
15561556         break;
15571557
r17702r17703
15921592            break;
15931593
15941594         default:
1595            fatalerror("I960: %x: Unhandled 6c.%x", i960->PIP, (opcode >> 7) & 0xf);
1595            fatalerror("I960: %x: Unhandled 6c.%x\n", i960->PIP, (opcode >> 7) & 0xf);
15961596         }
15971597         break;
15981598
r17702r17703
16051605            break;
16061606
16071607         default:
1608            fatalerror("I960: %x: Unhandled 6d.%x", i960->PIP, (opcode >> 7) & 0xf);
1608            fatalerror("I960: %x: Unhandled 6d.%x\n", i960->PIP, (opcode >> 7) & 0xf);
16091609         }
16101610         break;
16111611
r17702r17703
16461646               set_rifl(i960, opcode, -fabs(t1f));
16471647            break;
16481648         default:
1649            fatalerror("I960: %x: Unhandled 6e.%x", i960->PIP, (opcode >> 7) & 0xf);
1649            fatalerror("I960: %x: Unhandled 6e.%x\n", i960->PIP, (opcode >> 7) & 0xf);
16501650         }
16511651         break;
16521652
r17702r17703
16771677            break;
16781678
16791679         default:
1680            fatalerror("I960: %x: Unhandled 70.%x", i960->PIP, (opcode >> 7) & 0xf);
1680            fatalerror("I960: %x: Unhandled 70.%x\n", i960->PIP, (opcode >> 7) & 0xf);
16811681         }
16821682         break;
16831683
r17702r17703
17171717            break;
17181718
17191719         default:
1720            fatalerror("I960: %x: Unhandled 74.%x", i960->PIP, (opcode >> 7) & 0xf);
1720            fatalerror("I960: %x: Unhandled 74.%x\n", i960->PIP, (opcode >> 7) & 0xf);
17211721         }
17221722         break;
17231723
r17702r17703
17521752            break;
17531753
17541754         default:
1755            fatalerror("I960: %x: Unhandled 78.%x", i960->PIP, (opcode >> 7) & 0xf);
1755            fatalerror("I960: %x: Unhandled 78.%x\n", i960->PIP, (opcode >> 7) & 0xf);
17561756         }
17571757         break;
17581758
r17702r17703
17871787            break;
17881788
17891789         default:
1790            fatalerror("I960: %x: Unhandled 79.%x", i960->PIP, (opcode >> 7) & 0xf);
1790            fatalerror("I960: %x: Unhandled 79.%x\n", i960->PIP, (opcode >> 7) & 0xf);
17911791         }
17921792         break;
17931793
r17702r17703
19481948         break;
19491949
19501950      default:
1951         fatalerror("I960: %x: Unhandled %02x", i960->PIP, opcode >> 24);
1951         fatalerror("I960: %x: Unhandled %02x\n", i960->PIP, opcode >> 24);
19521952   }
19531953
19541954}
r17702r17703
20582058   case CPUINFO_INT_INPUT_STATE + I960_IRQ3:   set_irq_line(i960, I960_IRQ3, info->i);      break;
20592059
20602060   default:
2061      fatalerror("i960_set_info %x", state);
2061      fatalerror("i960_set_info %x\n", state);
20622062   }
20632063}
20642064
r17702r17703
22112211   case CPUINFO_STR_REGISTER + I960_G15:   sprintf(info->s, "fp   :%08x", i960->r[31]);      break;
22122212
22132213//  default:
2214//      fatalerror("i960_get_info %x          ", state);
2214//      fatalerror("i960_get_info %x          \n", state);
22152215   }
22162216}
22172217
trunk/src/emu/cpu/v810/v810.c
r17702r17703
10671067static UINT32 opBSU(v810_state *cpustate,UINT32 op)
10681068{
10691069   if(!(op & 8))
1070      fatalerror("V810: unknown BSU opcode %04x",op);
1070      fatalerror("V810: unknown BSU opcode %04x\n",op);
10711071
10721072   {
10731073      UINT32 srcbit,dstbit,src,dst,size;
trunk/src/emu/cpu/tms32025/32025dsm.c
r17702r17703
362362            case 'x':
363363               bit --;
364364               break;
365            default: fatalerror("Invalid instruction encoding '%s %s'",
365            default: fatalerror("Invalid instruction encoding '%s %s'\n",
366366               ops[0],ops[1]);
367367         }
368368      }
369369      if (bit != -1 )
370370      {
371         fatalerror("not enough bits in encoding '%s %s' %d",
371         fatalerror("not enough bits in encoding '%s %s' %d\n",
372372            ops[0],ops[1],bit);
373373      }
374374      while (isspace((UINT8)*p)) p++;
r17702r17703
455455         case 'x': bit--; break;
456456         case ' ': break;
457457         case '1': case '0': bit--; break;
458         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d",code,bit);
458         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d\n",code,bit);
459459      }
460460      cp++;
461461   }
r17702r17703
490490            case 'W': sprintf(num,"%04Xh",w); break;
491491            case 'X': break;
492492            default:
493               fatalerror("illegal escape character in format '%s'",Op[op].fmt);
493               fatalerror("illegal escape character in format '%s'\n",Op[op].fmt);
494494         }
495495         q = num; while (*q) *buffer++ = *q++;
496496         *buffer = '\0';
trunk/src/emu/cpu/pic16c5x/16c5xdsm.c
r17702r17703
124124            case 'k':
125125               bit --;
126126               break;
127            default: fatalerror("Invalid instruction encoding '%s %s'",
127            default: fatalerror("Invalid instruction encoding '%s %s'\n",
128128               ops[0],ops[1]);
129129         }
130130      }
131131      if (bit != -1 )
132132      {
133         fatalerror("not enough bits in encoding '%s %s' %d",
133         fatalerror("not enough bits in encoding '%s %s' %d\n",
134134            ops[0],ops[1],bit);
135135      }
136136      while (isspace((UINT8)*p)) p++;
r17702r17703
213213         case 'k': k <<=1; k |= ((code & (1<<bit)) ? 1 : 0); bit--; break;
214214         case ' ': break;
215215         case '1': case '0':  bit--; break;
216         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d",code,bit);
216         case '\0': fatalerror("premature end of parse string, opcode %x, bit = %d\n",code,bit);
217217      }
218218      cp++;
219219   }
r17702r17703
239239            case 'F': sprintf(num,"%s",regfile[f]); break;
240240            case 'K': sprintf(num,"%02Xh",k); break;
241241            default:
242               fatalerror("illegal escape character in format '%s'",Op[op].fmt);
242               fatalerror("illegal escape character in format '%s'\n",Op[op].fmt);
243243         }
244244         q = num; while (*q) *buffer++ = *q++;
245245         *buffer = '\0';
trunk/src/emu/cpu/arm7/arm7core.c
r17702r17703
170170
171171    // Data Abort
172172    if (cpustate->pendingAbtD) {
173       if (MODE26) fatalerror( "pendingAbtD (todo)");
173       if (MODE26) fatalerror( "pendingAbtD (todo)\n");
174174        SwitchMode(cpustate, eARM7_MODE_ABT);             /* Set ABT mode so PC is saved to correct R14 bank */
175175        SET_REGISTER(cpustate, 14, pc - 8 + 8);                   /* save PC to R14 */
176176        SET_REGISTER(cpustate, SPSR, cpsr);               /* Save current CPSR */
r17702r17703
184184
185185    // FIQ
186186    if (cpustate->pendingFiq && (cpsr & F_MASK) == 0) {
187       if (MODE26) fatalerror( "pendingFiq (todo)");
187       if (MODE26) fatalerror( "pendingFiq (todo)\n");
188188        SwitchMode(cpustate, eARM7_MODE_FIQ);             /* Set FIQ mode so PC is saved to correct R14 bank */
189189        SET_REGISTER(cpustate, 14, pc - 4 + 4);                   /* save PC to R14 */
190190        SET_REGISTER(cpustate, SPSR, cpsr);               /* Save current CPSR */
r17702r17703
219219
220220    // Prefetch Abort
221221    if (cpustate->pendingAbtP) {
222       if (MODE26) fatalerror( "pendingAbtP (todo)");
222       if (MODE26) fatalerror( "pendingAbtP (todo)\n");
223223        SwitchMode(cpustate, eARM7_MODE_ABT);             /* Set ABT mode so PC is saved to correct R14 bank */
224224        SET_REGISTER(cpustate, 14, pc - 4 + 4);                   /* save PC to R14 */
225225        SET_REGISTER(cpustate, SPSR, cpsr);               /* Save current CPSR */
r17702r17703
233233
234234    // Undefined instruction
235235    if (cpustate->pendingUnd) {
236       if (MODE26) fatalerror( "pendingUnd (todo)");
236       if (MODE26) fatalerror( "pendingUnd (todo)\n");
237237        SwitchMode(cpustate, eARM7_MODE_UND);             /* Set UND mode so PC is saved to correct R14 bank */
238238        // compensate for prefetch (should this also be done for normal IRQ?)
239239        if (T_IS_SET(GET_CPSR))
trunk/src/emu/cpu/arm7/arm7.c
r17702r17703
288288            }
289289            else
290290            {
291                fatalerror("ARM7: Not Yet Implemented: Coarse Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x", vaddr, domain, R15);
291                fatalerror("ARM7: Not Yet Implemented: Coarse Table, Section Domain fault on virtual address, vaddr = %08x, domain = %08x, PC = %08x\n", vaddr, domain, R15);
292292            }
293293            break;
294294        case COPRO_TLB_SECTION_TABLE:
r17702r17703
323323            break;
324324        case COPRO_TLB_FINE_TABLE:
325325            // Entry is the physical address of a fine second-level table
326            fatalerror("ARM7: Not Yet Implemented: fine second-level TLB lookup, PC = %08x, vaddr = %08x", R15, vaddr);
326            fatalerror("ARM7: Not Yet Implemented: fine second-level TLB lookup, PC = %08x, vaddr = %08x\n", R15, vaddr);
327327            break;
328328        default:
329329            // Entry is the physical address of a three-legged termite-eaten table
r17702r17703
577577            UINT32 temp1, temp2;
578578            temp1 = GET_CPSR & 0xF00000C3;
579579            temp2 = (R15 & 0xF0000000) | ((R15 & 0x0C000000) >> (26 - 6)) | (R15 & 0x00000003);
580            if (temp1 != temp2) fatalerror( "%08X: 32-bit and 26-bit modes are out of sync (%08X %08X)", pc, temp1, temp2);
580            if (temp1 != temp2) fatalerror( "%08X: 32-bit and 26-bit modes are out of sync (%08X %08X)\n", pc, temp1, temp2);
581581         }
582582#endif
583583
r17702r17703
12501250            {
12511251               if (!arm7_tlb_translate( cpustate, &R15, 0))
12521252               {
1253                  fatalerror("ARM7_MMU_ENABLE_HACK translate failed");
1253                  fatalerror("ARM7_MMU_ENABLE_HACK translate failed\n");
12541254               }
12551255            }
12561256#endif
trunk/src/emu/cpu/drcbex86.c
r17702r17703
350350
351351      // everything else is unexpected
352352      default:
353         fatalerror("Unexpected parameter type");
353         fatalerror("Unexpected parameter type\n");
354354         break;
355355   }
356356}
r17702r17703
625625   // generate a little bit of glue code to set up the environment
626626   drccodeptr *cachetop = m_cache.begin_codegen(500);
627627   if (cachetop == NULL)
628      fatalerror("Out of cache space after a reset!");
628      fatalerror("Out of cache space after a reset!\n");
629629
630630   x86code *dst = (x86code *)*cachetop;
631631
r17702r17703
28342834      ((UINT32 *)src)[-1] = labelcodeptr - src;
28352835   }
28362836   else
2837      fatalerror("fixup_label called with invalid jmp source!");
2837      fatalerror("fixup_label called with invalid jmp source!\n");
28382838}
28392839
28402840
trunk/src/emu/cpu/uml.c
r17702r17703
495495                  case SIZE_WORD:      convert_to_mov_immediate((INT16)m_param[1].immediate());   break;
496496                  case SIZE_DWORD:   convert_to_mov_immediate((INT32)m_param[1].immediate());   break;
497497                  case SIZE_QWORD:   convert_to_mov_immediate((INT64)m_param[1].immediate());   break;
498                  case SIZE_DQWORD:   fatalerror("Invalid SEXT target size");                  break;
498                  case SIZE_DQWORD:   fatalerror("Invalid SEXT target size\n");               break;
499499               }
500500            break;
501501

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