MAME SVN History

199869 Revisions

r176942 Sunday 21st March, 2021 at 19:29:21 UTC by Olivier Galibert
mac128: Fix the keyboard [O. Galibert, AJR] via6522: Don't retrigger the shift register timer on a second sr access This is a slightly hacky change. The 68k starts the shift register in internal clock mode just long enough that cb2 is set to zero, then stops it and restarts it in external clocking mode. The retrigger-corrected via code wants to change cb2 40 cycles in the future (8 edges of the 10 clocks/cycle E clock). The instruction that stops the shift register starts ~38 cycles in the future but does the actual write 50 cycles in. But the instructions not being interruptible, the write happens before the timer timeout is called. There are two problems there: the lack of interruptibility for the 68k, which is a hard problem that is worked on but is still going to take some time, and the fact that the via is supposed to change cb2 (data) at +35 (well, +34, but lets not get in the intricacies of the E clock) and cb1 (clock) at +40. But changing the serial output behaviour of the via is a very ugly "here be dragons" case. Which will have ot be done, but still. The quick hack is the make the via change data and clock at +35. Fast enough that the 68000 didn't start the instruction yet, not different enough that other systems would break. 100% proper fix will be later.

r176942 Sunday 21st March, 2021 at 19:29:21 UTC by Olivier Galibert

mac128: Fix the keyboard [O. Galibert, AJR]
via6522: Don't retrigger the shift register timer on a second sr access

This is a slightly hacky change. The 68k starts the shift register in
internal clock mode just long enough that cb2 is set to zero, then
stops it and restarts it in external clocking mode.

The retrigger-corrected via code wants to change cb2 40 cycles in the
future (8 edges of the 10 clocks/cycle E clock). The instruction that
stops the shift register starts ~38 cycles in the future but does the
actual write 50 cycles in. But the instructions not being
interruptible, the write happens before the timer timeout is called.

There are two problems there: the lack of interruptibility for the
68k, which is a hard problem that is worked on but is still going to
take some time, and the fact that the via is supposed to change cb2
(data) at +35 (well, +34, but lets not get in the intricacies of the E
clock) and cb1 (clock) at +40. But changing the serial output
behaviour of the via is a very ugly "here be dragons" case. Which
will have ot be done, but still.

The quick hack is the make the via change data and clock at +35. Fast
enough that the 68000 didn't start the instruction yet, not different
enough that other systems would break. 100% proper fix will be later.

[/branches/time-experiments/src/devices/machine]	6522via.cpp
[/branches/time-experiments/src/mame/drivers]	mac128.cpp

https://github.com/mamedev/mame/commit/025183d82c38c9af7ff88bc1db1556ff951822b0

199869 Revisions