trunk/src/mame/drivers/ttchamp.c
| r17671 | r17672 | |
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| 49 | 49 | { |
| 50 | 50 | public: |
| 51 | 51 | ttchamp_state(const machine_config &mconfig, device_type type, const char *tag) |
| 52 | | : driver_device(mconfig, type, tag) , |
| 53 | | m_peno_vram(*this, "peno_vram"){ } |
| 52 | : driver_device(mconfig, type, tag) |
| 53 | { } |
| 54 | 54 | |
| 55 | | required_shared_ptr<UINT16> m_peno_vram; |
| 55 | UINT16* m_peno_vram; |
| 56 | UINT16* m_peno_mainram; |
| 57 | |
| 56 | 58 | UINT16 m_paloff; |
| 57 | 59 | DECLARE_WRITE16_MEMBER(paloff_w); |
| 58 | 60 | DECLARE_WRITE16_MEMBER(pcup_prgbank_w); |
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| 60 | 62 | DECLARE_READ16_MEMBER(peno_rand); |
| 61 | 63 | DECLARE_READ16_MEMBER(peno_rand2); |
| 62 | 64 | DECLARE_DRIVER_INIT(ttchamp); |
| 65 | |
| 66 | DECLARE_WRITE16_MEMBER( penocup_vid_w ) |
| 67 | { |
| 68 | offset &=0x7fff; |
| 69 | COMBINE_DATA(&m_peno_vram[offset]); |
| 70 | } |
| 71 | |
| 72 | DECLARE_READ16_MEMBER( penocup_mainram_r ) |
| 73 | { |
| 74 | return m_peno_mainram[offset]; |
| 75 | } |
| 76 | |
| 77 | DECLARE_WRITE16_MEMBER( penocup_mainram_w ) |
| 78 | { |
| 79 | offset &=0x7fff; |
| 80 | COMBINE_DATA(&m_peno_mainram[offset]); |
| 81 | // COMBINE_DATA(&m_peno_vram[offset]); |
| 82 | } |
| 83 | |
| 84 | |
| 85 | |
| 63 | 86 | }; |
| 64 | 87 | |
| 65 | 88 | |
| 89 | |
| 66 | 90 | static VIDEO_START(ttchamp) |
| 67 | 91 | { |
| 92 | ttchamp_state *state = machine.driver_data<ttchamp_state>(); |
| 93 | state->m_peno_vram = (UINT16*)auto_alloc_array_clear(machine, UINT16, 0x10000/2); |
| 94 | state->m_peno_mainram = (UINT16*)auto_alloc_array_clear(machine, UINT16, 0x10000/2); |
| 95 | |
| 96 | |
| 97 | |
| 68 | 98 | } |
| 69 | 99 | |
| 70 | 100 | static SCREEN_UPDATE_IND16(ttchamp) |
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| 88 | 118 | // } |
| 89 | 119 | |
| 90 | 120 | count=0; |
| 91 | | UINT8 *videoram = reinterpret_cast<UINT8 *>(state->m_peno_vram.target()); |
| 121 | UINT8 *videoram = ( |
| 92 | 122 | for (y=0;y<yyy;y++) |
| 93 | 123 | { |
| 94 | 124 | for(x=0;x<xxx;x++) |
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| 138 | 168 | #endif |
| 139 | 169 | |
| 140 | 170 | static ADDRESS_MAP_START( ttchamp_map, AS_PROGRAM, 16, ttchamp_state ) |
| 141 | | AM_RANGE(0x00000, 0x0ffff) AM_RAM |
| 142 | | AM_RANGE(0x10000, 0x1ffff) AM_RAM AM_SHARE("peno_vram") |
| 143 | | AM_RANGE(0x20000, 0x7ffff) AM_ROMBANK("bank1") // ? |
| 171 | AM_RANGE(0x00000, 0x0ffff) AM_RAM AM_READWRITE(penocup_mainram_r, penocup_mainram_w) |
| 172 | |
| 173 | /* 0x10000 - 0x1ffff is where it writes most image stuff, but other address get written to 0 where the left edge of 'sprites' would be? why? bad code execution, or some kind of write address based blitter? |
| 174 | see for example the lines written down the side of where the (not displayed) CREDIT text would go, as well as beside the actual credit number.. also ingame if you can get it to start |
| 175 | */ |
| 176 | |
| 177 | AM_RANGE(0x10000, 0xfffff) AM_WRITE(penocup_vid_w) |
| 178 | |
| 179 | // how are these banked? what are the bank sizes? data needed for startup is at 0x20000-0x2ffff (strings) and 0x30000-0x3ffff (code) the rest seems to be graphics.. |
| 180 | AM_RANGE(0x00000, 0x7ffff) AM_ROMBANK("bank1") // ? |
| 144 | 181 | AM_RANGE(0x80000, 0xfffff) AM_ROMBANK("bank2") // ? |
| 145 | 182 | ADDRESS_MAP_END |
| 146 | 183 | |
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| 170 | 207 | PORT_START("SYSTEM") |
| 171 | 208 | PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 ) |
| 172 | 209 | PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 ) |
| 173 | | PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Unknown ) ) |
| 174 | | PORT_DIPSETTING( 0x0004, DEF_STR( Off ) ) |
| 175 | | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| 210 | PORT_SERVICE( 0x0004, IP_ACTIVE_LOW ) |
| 176 | 211 | PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) ) |
| 177 | 212 | PORT_DIPSETTING( 0x0008, DEF_STR( Off ) ) |
| 178 | 213 | PORT_DIPSETTING( 0x0000, DEF_STR( On ) ) |
| r17671 | r17672 | |
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| 229 | 264 | PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) |
| 230 | 265 | PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) |
| 231 | 266 | PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2) |
| 232 | | PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START1 ) |
| 267 | PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START2 ) |
| 233 | 268 | |
| 234 | 269 | INPUT_PORTS_END |
| 235 | 270 | |
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| 339 | 374 | DRIVER_INIT_MEMBER(ttchamp_state,ttchamp) |
| 340 | 375 | { |
| 341 | 376 | UINT8 *ROM1 = machine().root_device().memregion("user1")->base(); |
| 342 | | machine().root_device().membank("bank1")->set_base(&ROM1[0x120000]); |
| 377 | machine().root_device().membank("bank1")->set_base(&ROM1[0x100000]); |
| 343 | 378 | machine().root_device().membank("bank2")->set_base(&ROM1[0x180000]); |
| 344 | 379 | } |
| 345 | 380 | |