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r17558 Wednesday 29th August, 2012 at 17:06:18 UTC by Jonathan Gevaryahu
(MESS) VK100 IO mirroring, also a lot of prom tracing and comment updates [Lord Nightmare]
[src/mess/drivers]vk100.c

trunk/src/mess/drivers/vk100.c
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1414
1515 Tony DiCenzo, now the director of standards and architecture at Oracle, was on the team that developed the VK100
1616 see http://startup.nmnaturalhistory.org/visitorstories/view.php?ii=79
17 Robert "Bob" C. Quinn was definitely lead engineer on the VT125 and may have been lead engineer on the VK100 as well
1718
1819 The prototype name for the VK100 was 'SMAKY' (Smart Keyboard)
1920
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166167   UINT8 m_vgDVM;
167168   UINT8 m_vgDIR;
168169   UINT8 m_vgWOPS;
169   UINT8 m_VG_MODE; // latched on EXEC
170   UINT8 m_VG_MODE; // 2 bits, latched on EXEC
170171   UINT8 m_vgGO; // activated on next SYNC pulse after EXEC
171172   UINT8 m_ACTS;
172173   UINT16 m_RXDivisor;
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278279         state->m_vgGO = 0; // done
279280         break;
280281   }
281   /* this is the "DIRECTION ROM"  == mb6309 (256x8, 82s135)
282    /* this is the "DIRECTION ROM"  == mb6309 (256x8, 82s135)
282283     * see figure 5-24 on page 5-39
283284     * It tells the direction and enable for counting on the X and Y counters
284285     * and also handles the non-math related parts of the bresenham line algorithm
285286     * control bits:
286     *            /CE1 ----- ? ENA ERROR L?
287     *            /CE2 ----- ? D COUNT 0?
287     *            /CE1 ----- DCOUNT 0 H [verified via tracing]
288     *            /CE2 ----- ENA ERROR L [verified via tracing]
288289     * addr bits: 76543210
289290     *            ||||\\\\-- DIR (vgDIR register low 4 bits)
290     *            |||\------ ERROR CARRY (strobed in by STROBE L from the error counter's adder)
291     *            ||\------- Y0 (the otherwise unused lsb of the Y register, used for bresenham)
292     *            |\-------- feedback bit from d5 gated by V CLK
291     *            |||\------ C OUT aka ERROR CARRY (strobed in by STROBE L from the error counter's adder) [verified via tracing]
292     *            ||\------- Y0 (the otherwise unused lsb of the Y register, used for bresenham) [verified via tracing]
293     *            |\-------- feedback bit from d5 strobed by V CLK [verified via tracing]
293294     *            \--------- GND; the second half of the prom is blank (0x00)
294295     * data bits: 76543210
295296     *            |||||||\-- ENA X (enables change on X counter)
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297298     *            |||||\---- Y DIRECTION (high is count down, low is count up)
298299     *            ||||\----- X DIRECTION (high is count down, low is count up)
299300     *            |||\------ PIXEL WRT
300     *            ||\------- feedback bit to a6
301     *            ||\------- feedback bit to a6, this bit is held in PRESET/1 condition by GO being inactive, and if the vector prom is disabled it is pulled to 1 [verified via tracing and schematics]
301302     *            |\-------- UNUSED, always 0
302303     *            \--------- UNUSED, always 0
304     * The VT125 prom @ E41 is literally identical to this, the same exact part: 23-059B1
303305     */
304306   //UINT8 direction_rom = state->m_dir[];
305307   // HACK: we need the proper direction rom dump for this!
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571573 * write command -> 0x05 (normal, normal, /RTS is 1, normal, normal, recieve ON, /DTR is 0, transmit off)
572574 * read SYSTAT B (and xor with 0xe), expect d7 to be SET or jump to error
573575 * after this it does something and waits for an rxrdy interrupt
574
576
575577 shows the results of:
576578 * ACTS (/CTS)  ?      ?      ?      ?      ?      ?      ?
577579 * d7           d6     d5     d4     d3     d2     d1     d0
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606608   AM_RANGE( 0x8000, 0xbfff ) AM_RAM
607609ADDRESS_MAP_END
608610
611/*
612 * 8085 IO address map (x = ignored; * = selects address within this range; ? = not sure; ** = subparts check this bit)
613 * (a15 to a8 are latched the same value as a7-a0 on the 8080 and 8085)
614 * [this map is derived from extensive tracing as well as some guesswork, noted for the crtc, systat_b and the uart]
615   a7  a6  a5  a4  a3  a2  a1  a0
616   ?x  0   ?x  ?x  ?x  ?x  ?x  0     W     CRTC address
617   ?x  0   ?x  ?x  ?x  ?x  ?x  1     RW    CRTC register r/w
618   x   1   *   *   *   **  **  **        read area (rightmost 74ls138):
619   x   1   0   0   0   *   *   *     R     SYSTAT_A (a0-a3 chooses the bit of the dipswitches read via d3)
620   x   1   0   0   1   ?x  ?x  ?x    R     SYSTAT_B
621   x   1   0   1   0   ?x  ?x  0     R     i8251 UART data
622   x   1   0   1   0   ?x  ?x  1     R     i8251 UART status
623   x   1   0   1   1   x   x   x     R     unused
624   x   1   1   0   0   x   x   x     R     unused
625   x   1   1   0   1   x   x   x     R     unused
626   x   1   1   1   0   x   x   x     R     unused
627   x   1   1   1   1   x   x   x     R     unused
628   x   1   0   x   x   *   *   *         write area (right 74ls138):
629   x   1   0   x   x   0   0   0     W     X (low 8 bits)
630   x   1   0   x   x   0   0   1     W     X (high 4 bits)
631   x   1   0   x   x   0   1   0     W     Y (low 8 bits)
632   x   1   0   x   x   0   1   1     W     Y (high 4 bits)
633   x   1   0   x   x   1   0   0     W     ERR
634   x   1   0   x   x   1   0   1     W     SOPS
635   x   1   0   x   x   1   1   0     W     PAT
636   x   1   0   x   x   1   1   1     W     PMUL
637   x   1   1   *   *   *   **  **        write area (middle 74ls138):
638   x   1   1   0   0   0   **  **          write to register file 2x 74ls670:
639   x   1   1   0   0   0   0   0     W       DU
640   x   1   1   0   0   0   0   1     W       DVM
641   x   1   1   0   0   0   1   0     W       DIR
642   x   1   1   0   0   0   1   1     W       WOPS
643   x   1   1   0   0   1   *   *     W     set VG_MODE to * * XOR 3 and Execute (if GO is not active)
644   x   1   1   0   1   0   x   x     W     KYBDW
645   x   1   1   0   1   1   x   x     W     BAUD
646   x   1   1   1   0   0   ?x  0     W     i8251 UART data
647   x   1   1   1   0   0   ?x  1     W     i8251 UART control
648   x   1   1   1   0   1   x   x     W     unused
649   x   1   1   1   1   0   x   x     W     unused? (may be wired-or to KYBDW)
650   x   1   1   1   1   1   x   x     W     unused
651*/
609652static ADDRESS_MAP_START(vk100_io, AS_IO, 8, vk100_state)
610653   ADDRESS_MAP_UNMAP_HIGH
611   //ADDRESS_MAP_GLOBAL_MASK(0x7f) // guess
612   AM_RANGE(0x00, 0x00) AM_DEVWRITE("crtc", mc6845_device, address_w)
613   AM_RANGE(0x01, 0x01) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
654   //ADDRESS_MAP_GLOBAL_MASK(0x7f) // guess, probably correct
655   AM_RANGE(0x00, 0x00) AM_MIRROR(0xBE) AM_DEVWRITE("crtc", mc6845_device, address_w)
656   AM_RANGE(0x01, 0x01) AM_MIRROR(0xBE) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
614657   // Comments are from page 118 (5-14) of http://web.archive.org/web/20091015205827/http://www.computer.museum.uq.edu.au/pdf/EK-VK100-TM-001%20VK100%20Technical%20Manual.pdf
615   AM_RANGE (0x40, 0x41) AM_WRITE(vgLD_X)  //LD X LO + HI 12 bits
616   AM_RANGE (0x42, 0x43) AM_WRITE(vgLD_Y)  //LD Y LO + HI 12 bits
617   AM_RANGE (0x44, 0x44) AM_WRITE(vgERR)    //LD ERR ('error' in bresenham algorithm)
618   AM_RANGE (0x45, 0x45) AM_WRITE(vgSOPS)   //LD SOPS (screen options (plus uart dest))
619   AM_RANGE (0x46, 0x46) AM_WRITE(vgPAT)    //LD PAT (pattern register)
620   AM_RANGE (0x47, 0x47) AM_WRITE(vgPMUL)   //LD PMUL (pattern multiplier)
621   AM_RANGE (0x60, 0x60) AM_WRITE(vgDU)     //LD DU (major)
622   AM_RANGE (0x61, 0x61) AM_WRITE(vgDVM)    //LD DVM (minor)
623   AM_RANGE (0x62, 0x62) AM_WRITE(vgDIR)    //LD DIR (direction)
624   AM_RANGE (0x63, 0x63) AM_WRITE(vgWOPS)   //LD WOPS (write options)
625   AM_RANGE (0x64, 0x67) AM_WRITE(vgEX)    //EX MOV, DOT, VEC, ER
626   AM_RANGE (0x68, 0x68) AM_WRITE(KBDW)   //KBDW (probably AM_MIRROR(0x03))
627   AM_RANGE (0x6C, 0x6C) AM_WRITE(BAUD)   //LD BAUD (baud rate clock divider setting for i8251 tx and rx clocks) (probably AM_MIRROR(0x03))
628   AM_RANGE (0x70, 0x70) AM_DEVWRITE("i8251", i8251_device, data_w) //LD COMD (i8251 data reg)
629   AM_RANGE (0x71, 0x71) AM_DEVWRITE("i8251", i8251_device, control_w) //LD COM (i8251 control reg)
630   //AM_RANGE (0x74, 0x74) AM_WRITE(unknown_74)
631   //AM_RANGE (0x78, 0x78) AM_WRITE(kbdw)   //KBDW ?(mirror?)
632   //AM_RANGE (0x7C, 0x7C) AM_WRITE(unknown_7C)
633   AM_RANGE (0x40, 0x47) AM_READ(SYSTAT_A) // SYSTAT A (state machine done and last 4 bits of vram, as well as dipswitches)
634   AM_RANGE (0x48, 0x48) AM_READ(SYSTAT_B) // SYSTAT B (uart stuff)
635   AM_RANGE (0x50, 0x50) AM_DEVREAD("i8251", i8251_device, data_r) // UART O
636   AM_RANGE (0x51, 0x51) AM_DEVREAD("i8251", i8251_device, status_r) // UAR
637   //AM_RANGE (0x58, 0x58) AM_READ(unknown_58)
638   //AM_RANGE (0x60, 0x60) AM_READ(unknown_60)
639   //AM_RANGE (0x68, 0x68) AM_READ(unknown_68) // NOT USED
640   //AM_RANGE (0x70, 0x70) AM_READ(unknown_70)
641   //AM_RANGE (0x78, 0x7f) AM_READ(unknown_78)
658   AM_RANGE (0x40, 0x41) AM_MIRROR(0x98) AM_WRITE(vgLD_X)  //LD X LO + HI 12 bits
659   AM_RANGE (0x42, 0x43) AM_MIRROR(0x98) AM_WRITE(vgLD_Y)  //LD Y LO + HI 12 bits
660   AM_RANGE (0x44, 0x44) AM_MIRROR(0x98) AM_WRITE(vgERR)    //LD ERR ('error' in bresenham algorithm)
661   AM_RANGE (0x45, 0x45) AM_MIRROR(0x98) AM_WRITE(vgSOPS)   //LD SOPS (screen options (plus uart dest))
662   AM_RANGE (0x46, 0x46) AM_MIRROR(0x98) AM_WRITE(vgPAT)    //LD PAT (pattern register)
663   AM_RANGE (0x47, 0x47) AM_MIRROR(0x98) AM_WRITE(vgPMUL)   //LD PMUL (pattern multiplier)
664   AM_RANGE (0x60, 0x60) AM_MIRROR(0x80) AM_WRITE(vgDU)     //LD DU (major)
665   AM_RANGE (0x61, 0x61) AM_MIRROR(0x80) AM_WRITE(vgDVM)    //LD DVM (minor)
666   AM_RANGE (0x62, 0x62) AM_MIRROR(0x80) AM_WRITE(vgDIR)    //LD DIR (direction)
667   AM_RANGE (0x63, 0x63) AM_MIRROR(0x80) AM_WRITE(vgWOPS)   //LD WOPS (write options)
668   AM_RANGE (0x64, 0x67) AM_MIRROR(0x80) AM_WRITE(vgEX)    //EX MOV, DOT, VEC, ER
669   AM_RANGE (0x68, 0x68) AM_MIRROR(0x83) AM_WRITE(KBDW)   //KBDW (probably AM_MIRROR(0x03))
670   AM_RANGE (0x6C, 0x6C) AM_MIRROR(0x83) AM_WRITE(BAUD)   //LD BAUD (baud rate clock divider setting for i8251 tx and rx clocks) (probably AM_MIRROR(0x03))
671   AM_RANGE (0x70, 0x70) AM_MIRROR(0x82) AM_DEVWRITE("i8251", i8251_device, data_w) //LD COMD (i8251 data reg)
672   AM_RANGE (0x71, 0x71) AM_MIRROR(0x82) AM_DEVWRITE("i8251", i8251_device, control_w) //LD COM (i8251 control reg)
673   //AM_RANGE (0x74, 0x74) AM_MIRROR(0x83) AM_WRITE(unknown_74)
674   //AM_RANGE (0x78, 0x78) AM_MIRROR(0x83) AM_WRITE(kbdw)   //KBDW ?(mirror?)
675   //AM_RANGE (0x7C, 0x7C) AM_MIRROR(0x83) AM_WRITE(unknown_7C)
676   AM_RANGE (0x40, 0x47) AM_MIRROR(0x80) AM_READ(SYSTAT_A) // SYSTAT A (state machine done and last 4 bits of vram, as well as dipswitches)
677   AM_RANGE (0x48, 0x48) AM_MIRROR(0x87/*0x80*/) AM_READ(SYSTAT_B) // SYSTAT B (uart stuff)
678   AM_RANGE (0x50, 0x50) AM_MIRROR(0x86) AM_DEVREAD("i8251", i8251_device, data_r) // UART O
679   AM_RANGE (0x51, 0x51) AM_MIRROR(0x86) AM_DEVREAD("i8251", i8251_device, status_r) // UAR
680   //AM_RANGE (0x58, 0x58) AM_MIRROR(0x87) AM_READ(unknown_58)
681   //AM_RANGE (0x60, 0x60) AM_MIRROR(0x87) AM_READ(unknown_60)
682   //AM_RANGE (0x68, 0x68) AM_MIRROR(0x87) AM_READ(unknown_68) // NOT USED
683   //AM_RANGE (0x70, 0x70) AM_MIRROR(0x87) AM_READ(unknown_70)
684   //AM_RANGE (0x78, 0x7f) AM_MIRROR(0x87) AM_READ(unknown_78)
642685ADDRESS_MAP_END
643686
644687/* Input ports */
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9831026     * 2 select bits to choose one of the 4 bits, sourced from the X reg LSBs (a4, a5)
9841027     * 3 pattern function bits from WOPS (F0 "N" is a6, F1 and F2 are a7 and a8
9851028     * and one bit from the lsb of the pattern register shifter (a9)
986i.e. addr bits 9876543210
987     *         ||||||\\\\- input from ram A
988     *         ||||\\----- bit select (from x reg lsb)
989     *         |||\------- negate N \___ low 3 bits of WOPS
990     *         |\\-------- function /
991     *         \---------- pattern bit P
1029     * control bits:
1030     *            /CE1 ----- GND [verified via tracing]
1031     *            /CE2 ----- GND [verified via tracing]
1032     * addr bits 9876543210
1033     *           ||||||\\\\- input from ram (A)
1034     *           ||||\\----- bit select (from x reg lsb)
1035     *           |||\------- negate (N) \___ low 3 bits of WOPS
1036     *           |\\-------- function   /
1037     *           \---------- pattern bit (P)
1038     * data bits: 3210
1039     *            \\\\-- output to ram (M), but gated by an io line from vector rom
9921040     *    functions are:
9931041     *    Overlay: M=A|(P^N)
9941042     *    Replace: M=P^N
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9981046   ROM_LOAD( "wb8201_656f1.m1-7643-5.pr4.ic17", 0x0000, 0x0400, CRC(e8ecf59f) SHA1(49e9d109dad3d203d45471a3f4ca4985d556161f)) // label verified from nigwil's board
9991047
10001048   ROM_REGION(0x100, "trans", ROMREGION_ERASEFF )
1001   // this is the "TRANSLATOR ROM" described in figure 5-17 on page 5-27 (256*8, 82s135)
1002   // it contains a table of 256 values which skips every fourth value so 00 01 02 04 05 06 08.. etc, wraps at the end
1003   // The VT125 prom @ E60 is literally identical to this, the same exact part: 23-060B1
1049    /* this is the "TRANSLATOR ROM" described in figure 5-17 on page 5-27 (256*8, 82s135)
1050     * it contains a table of 256 values which skips every fourth value so 00 01 02 04 05 06 08.. etc, wraps at the end
1051     * control bits:
1052     *            /CE1 ----- GND [verified via tracing]
1053     *            /CE2 ----- GND [verified via tracing]
1054     * addr bits: 76543210
1055     *            \\\\\\\\- X9 thru X2
1056     * data bits: 76543210
1057     *            \\\\\\\\- X'9 thru X'2
1058     * The VT125 prom @ E60 is literally identical to this, the same exact part: 23-060B1
1059     */
10041060   ROM_LOAD( "wb---0_060b1.mmi6309.pr2.ic77", 0x0000, 0x0100, CRC(198317fc) SHA1(00e97104952b3fbe03a4f18d800d608b837d10ae)) // label verified from nigwil's board
10051061
10061062   ROM_REGION(0x100, "dir", ROMREGION_ERASEFF )
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10091065     * It tells the direction and enable for counting on the X and Y counters
10101066     * and also handles the non-math related parts of the bresenham line algorithm
10111067     * control bits:
1012     *            /CE1 ----- ? ENA ERROR L?
1013     *            /CE2 ----- ? D COUNT 0?
1068     *            /CE1 ----- DCOUNT 0 H [verified via tracing]
1069     *            /CE2 ----- ENA ERROR L [verified via tracing]
10141070     * addr bits: 76543210
10151071     *            ||||\\\\-- DIR (vgDIR register low 4 bits)
1016     *            |||\------ ERROR CARRY (strobed in by STROBE L from the error counter's adder)
1017     *            ||\------- Y0 (the otherwise unused lsb of the Y register, used for bresenham)
1018     *            |\-------- feedback bit from d5 gated by V CLK
1072     *            |||\------ C OUT aka ERROR CARRY (strobed in by STROBE L from the error counter's adder) [verified via tracing]
1073     *            ||\------- Y0 (the otherwise unused lsb of the Y register, used for bresenham) [verified via tracing]
1074     *            |\-------- feedback bit from d5 strobed by V CLK [verified via tracing]
10191075     *            \--------- GND; the second half of the prom is blank (0x00)
10201076     * data bits: 76543210
10211077     *            |||||||\-- ENA X (enables change on X counter)
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10231079     *            |||||\---- Y DIRECTION (high is count down, low is count up)
10241080     *            ||||\----- X DIRECTION (high is count down, low is count up)
10251081     *            |||\------ PIXEL WRT
1026     *            ||\------- feedback bit to a6
1082     *            ||\------- feedback bit to a6, this bit is held in PRESET/1 condition by GO being inactive, and if the vector prom is disabled it is pulled to 1 [verified via tracing and schematics]
10271083     *            |\-------- UNUSED, always 0
10281084     *            \--------- UNUSED, always 0
10291085     * The VT125 prom @ E41 is literally identical to this, the same exact part: 23-059B1
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10331089   ROM_REGION( 0x400, "proms", ROMREGION_ERASEFF )
10341090   /* this is the "RAS/ERASE ROM" involved with driving the RAS lines and erasing VRAM dram (256*4, 82s129)
10351091     * control bits:
1036     *            /CE1 ----- /WRITE aka WRITE L (pin 6 of vector rom after being latched by its ls273) [verified from tracing and vt125 schematic]
1037     *            /CE2 ----- /ENA WRITE aka ENA WRITE L [verified from tracing and vt125 schematic]
1092     *            /CE1 ----- /WRITE aka WRITE L (pin 6 of vector rom after being latched by its ls273) [verified via tracing and vt125 schematic]
1093     *            /CE2 ----- /ENA WRITE aka ENA WRITE L [verified via tracing and vt125 schematic]
10381094     *                       (INHIBIT WRITE L (pin 5 of ls74 to extreme left edge of translate prom) XOR STROBE D COUNT (pin 5 of ls74 near the 20ma port) (pin 3 of the ls86 above the crtc)
10391095     * addr bits: 76543210
1040     *            |||||||\-- X'2 [verified from tracing]
1041     *            ||||||\--- X'3 [verified from tracing]
1042     *            |||||\---- register file bit 3/upper file MSB (DIR prom pin 4, ls191 2nd from left edge left of the hd46505 pin 9, upper ls670n pin 6, ls283 at the left edge left of the hd46505 pin 15) [verified from tracing]
1043     *            ||||\----- (Y8 NOR !(X10 NAND X9)) (pins 4,5,6 of ls32 left of 8085, and pins 1,2 of the ls04 in the lower left corner, pins 10,9,8 of the ls00 at the left edge drawn from the ls74 between the 8251 and 8202) [verified from tracing]
1044     *            |||\------ (X10 NOR Y10) (pins 10,9,8 of ;s32 left of 8085) [verified from tracing]
1045     *            ||\------- X11 (D out of ls191 left of ls191 left of hd46505) [verified from tracing]
1046     *            |\-------- Y11 (D out of ls191 left of hd46505) [verified from tracing]
1047     *            \--------- ERASE L/d5 on the vector rom [verified from tracing]
1096     *            |||||||\-- X'2 [verified via tracing]
1097     *            ||||||\--- X'3 [verified via tracing]
1098     *            |||||\---- register file bit 3/upper file MSB (DIR prom pin 4, ls191 2nd from left edge left of the hd46505 pin 9, upper ls670n pin 6, ls283 at the left edge left of the hd46505 pin 15) [verified via tracing]
1099     *            ||||\----- (Y8 NOR !(X10 NAND X9)) (pins 4,5,6 of ls32 left of 8085, and pins 1,2 of the ls04 in the lower left corner, pins 10,9,8 of the ls00 at the left edge drawn from the ls74 between the 8251 and 8202) [verified via tracing]
1100     *            |||\------ (X10 NOR Y10) (pins 10,9,8 of ls32 left of 8085) [verified via tracing]
1101     *            ||\------- X11 (D out of ls191 left of ls191 left of hd46505) [verified via tracing]
1102     *            |\-------- Y11 (D out of ls191 left of hd46505) [verified via tracing]
1103     *            \--------- ERASE L/d5 on the vector rom [verified via tracing]
10481104     * data bits: 3210
10491105     *            |||\-- ? wr_1?
10501106     *            ||\--- ? wr_2?
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10751131     * the vector rom bits are complex and are unfortunately poorly documented
10761132     * in the tech manual. see figure 5-23.
10771133     * control bits:
1078     *            /CE1 ----- /GO aka GO L
1079     *            /CE2 ----- GND
1134     *            /CE1 ----- /GO aka GO L [verified via tracing]
1135     *            /CE2 ----- GND [verified via tracing]
10801136     * addr bits: 76543210
10811137     *            ||||\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order
1082     *            |||\------ A0\__Address lsb bits of the execute write, i.e. VG_MODE; these are INVERTED FIRST.
1083     *            ||\------- A1/
1084     *            |\-------- CARRY_IN (when set, only one /LD ERROR pulse occurs instead of two)
1085     *            \--------- ??? (/LD ERROR only goes active (low) when this is unset)
1138     *            |||\------ (MODE 0 NAND GO) \_This effectively means when GO is low, these bits are both 1, when GO is high, these bits are the inverse of the MODE bits; this is DIFFERENT from the vt125, and was probably removed as unnecessary given that /GO is an enable for the vector rom anyway [verified via tracing]
1139     *            ||\------- (MODE 1 NAND GO) /
1140     *            |\-------- ? C OUT (when set, only one /LD ERROR pulse occurs instead of two)
1141     *            \--------- ? FINISH (/LD ERROR only goes active (low) when this is unset)
10861142     *
10871143     * data bits: 76543210
10881144     *            |||||||\-- /WRITE aka WRITE L (fig 5-20, page 5-32, writes the post-pattern-converted value back to vram at X,Y)
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10901146     *            |||||\---- VECTOR CLK aka V CLK [verified via tracing]
10911147     *            ||||\----- /LD ERROR aka STROBE ERROR L (strobes the adder result value into the vgERR register)
10921148     *            |||\------ D LOAD [by process of elimination and limited tracing]
1093     *            ||\------- ERASE L (latched, forces a4 on the sync rom low and also forces a7 on the ras/erase rom; the counter rom may be involved in blanking all of vram) [verified from tracing]
1149     *            ||\------- ERASE L (latched, forces a4 on the sync rom low and also forces a7 on the ras/erase rom; the counter rom may be involved in blanking all of vram) [verified via tracing]
10941150     *            |\-------- C0 aka C IN (high during DVM read, low otherwise, a carry in to the adder so DVM is converted from 1s to 2s complement)
10951151     *            \--------- SHIFT ENA [verified via tracing]
10961152     * The data bits all have pull-ups to +5v if the /CE1 pin is not low
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11141170     *            /CE1 -- GND(Unused)
11151171     * addr bits: 43210
11161172     *            |\\\\-- To sync counter, which counts 0xC 0x3 0x2 0x1 0x0 0x5 0x4 0xB 0xA 0x9 0x8 0xD in that order
1117     *            \------ comes from the gated ERASE L/d5 from the vector rom, only low during VG_MODE == ER (ERase Screen) [verified from tracing]
1173     *            \------ comes from the gated ERASE L/d5 from the vector rom, only low during VG_MODE == ER (ERase Screen) [verified via tracing]
11181174     *                      when high: the sync rom matches figure 5-20 (page 5-32) and 5-23 (page 5-38)
11191175     *                      when low: RA/RB is fixed on WOPS in the register file
11201176     *                                LD SHFR does NOT output pulses (effectively blanking the screen)

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