trunk/src/emu/machine/m6m80011ap.c
r17494 | r17495 | |
26 | 26 | //------------------------------------------------- |
27 | 27 | |
28 | 28 | m6m80011ap_device::m6m80011ap_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) |
29 | | : device_t(mconfig, M6M80011AP, "m6m80011ap", tag, owner, clock) |
| 29 | : device_t(mconfig, M6M80011AP, "m6m80011ap", tag, owner, clock), |
| 30 | device_nvram_interface(mconfig, *this) |
30 | 31 | { |
31 | 32 | |
32 | 33 | } |
r17494 | r17495 | |
60 | 61 | { |
61 | 62 | } |
62 | 63 | |
| 64 | //------------------------------------------------- |
| 65 | // nvram_default - called to initialize NVRAM to |
| 66 | // its default state |
| 67 | //------------------------------------------------- |
63 | 68 | |
| 69 | void m6m80011ap_device::nvram_default() |
| 70 | { |
| 71 | for (offs_t offs = 0; offs < 0x80; offs++) |
| 72 | m_eeprom_data[offs] = 0xffff; |
| 73 | } |
| 74 | |
| 75 | |
| 76 | |
| 77 | |
| 78 | //------------------------------------------------- |
| 79 | // nvram_read - called to read NVRAM from the |
| 80 | // .nv file |
| 81 | //------------------------------------------------- |
| 82 | |
| 83 | void m6m80011ap_device::nvram_read(emu_file &file) |
| 84 | { |
| 85 | file.read(m_eeprom_data, 0x100); |
| 86 | } |
| 87 | |
| 88 | |
| 89 | //------------------------------------------------- |
| 90 | // nvram_write - called to write NVRAM to the |
| 91 | // .nv file |
| 92 | //------------------------------------------------- |
| 93 | |
| 94 | void m6m80011ap_device::nvram_write(emu_file &file) |
| 95 | { |
| 96 | file.write(m_eeprom_data, 0x100); |
| 97 | } |
| 98 | |
64 | 99 | //************************************************************************** |
65 | 100 | // READ/WRITE HANDLERS |
66 | 101 | //************************************************************************** |
r17494 | r17495 | |
68 | 103 | |
69 | 104 | READ_LINE_MEMBER( m6m80011ap_device::read_bit ) |
70 | 105 | { |
71 | | return 0; |
| 106 | return m_read_latch; |
72 | 107 | } |
73 | 108 | |
74 | 109 | READ_LINE_MEMBER( m6m80011ap_device::ready_line ) |
r17494 | r17495 | |
78 | 113 | |
79 | 114 | WRITE_LINE_MEMBER( m6m80011ap_device::set_cs_line ) |
80 | 115 | { |
| 116 | m_reset_line = state; |
81 | 117 | |
| 118 | if (m_reset_line != CLEAR_LINE) |
| 119 | { |
| 120 | m_eeprom_state = EEPROM_GET_CMD; |
| 121 | m_cmd_stream_pos = 0; |
| 122 | m_current_cmd = 0; |
| 123 | } |
82 | 124 | } |
83 | 125 | |
84 | | WRITE_LINE_MEMBER( m6m80011ap_device::set_clock_line ) |
| 126 | |
| 127 | WRITE_LINE_MEMBER( m6m80011ap_device::write_bit ) |
85 | 128 | { |
86 | | |
| 129 | m_latch = state; |
87 | 130 | } |
88 | 131 | |
89 | | WRITE_LINE_MEMBER( m6m80011ap_device::write_bit ) |
| 132 | WRITE_LINE_MEMBER( m6m80011ap_device::set_clock_line ) |
90 | 133 | { |
| 134 | if (m_reset_line == CLEAR_LINE) |
| 135 | { |
| 136 | if(state == 1) |
| 137 | { |
| 138 | switch(m_eeprom_state) |
| 139 | { |
| 140 | case EEPROM_GET_CMD: |
| 141 | m_current_cmd = (m_current_cmd >> 1) | ((m_latch & 1)<< 7); |
| 142 | m_cmd_stream_pos++; |
91 | 143 | |
| 144 | if (m_cmd_stream_pos==8) |
| 145 | { |
| 146 | m_cmd_stream_pos = 0; |
| 147 | switch(m_current_cmd) |
| 148 | { |
| 149 | case 0xc5: m_eeprom_state = EEPROM_WRITE_ENABLE; break; |
| 150 | case 0x05: m_eeprom_state = EEPROM_WRITE_DISABLE; break; |
| 151 | case 0x25: m_eeprom_state = EEPROM_WRITE; break; |
| 152 | case 0x15: m_eeprom_state = EEPROM_READ; break; |
| 153 | case 0x95: m_eeprom_state = EEPROM_STATUS_OUTPUT; break; |
| 154 | default: |
| 155 | printf("Write M6M80011 unknown %02x cmd\n",m_current_cmd ); |
| 156 | break; |
| 157 | } |
| 158 | } |
| 159 | break; |
| 160 | |
| 161 | case EEPROM_READ: |
| 162 | m_current_cmd = (m_current_cmd >> 1) | ((m_latch & 1)<< 23); |
| 163 | m_cmd_stream_pos++; |
| 164 | |
| 165 | if (m_cmd_stream_pos==8) |
| 166 | { |
| 167 | m_current_addr = m_current_cmd >> 16; |
| 168 | } |
| 169 | |
| 170 | if(m_cmd_stream_pos>=8) |
| 171 | { |
| 172 | m_read_latch = (m_eeprom_data[m_current_addr] >> (23-m_cmd_stream_pos)) & 1; |
| 173 | //printf("%d %04x <- %04x %d\n",m_read_latch,m_eeprom_data[m_current_addr],m_current_addr,m_cmd_stream_pos-8); |
| 174 | } |
| 175 | |
| 176 | if(m_cmd_stream_pos==24) |
| 177 | { |
| 178 | m_eeprom_state = EEPROM_GET_CMD; |
| 179 | m_cmd_stream_pos = 0; |
| 180 | } |
| 181 | break; |
| 182 | |
| 183 | case EEPROM_WRITE: |
| 184 | m_current_cmd = (m_current_cmd >> 1) | ((m_latch & 1)<< 23); |
| 185 | m_cmd_stream_pos++; |
| 186 | |
| 187 | if (m_cmd_stream_pos==8) |
| 188 | { |
| 189 | m_current_addr = m_current_cmd >> 16; |
| 190 | } |
| 191 | |
| 192 | if(m_cmd_stream_pos==24) |
| 193 | { |
| 194 | if(m_eeprom_we) |
| 195 | m_eeprom_data[m_current_addr] = (m_current_cmd >> 8) & 0xffff; |
| 196 | |
| 197 | //printf("%04x %04x -> %04x\n",m_eeprom_data[m_current_addr],m_current_addr,m_current_cmd >> 8); |
| 198 | |
| 199 | m_eeprom_state = EEPROM_GET_CMD; |
| 200 | m_cmd_stream_pos = 0; |
| 201 | } |
| 202 | break; |
| 203 | |
| 204 | case EEPROM_WRITE_ENABLE: |
| 205 | case EEPROM_WRITE_DISABLE: |
| 206 | m_current_cmd = (m_current_cmd >> 1) | ((m_latch & 1)<< 7); |
| 207 | m_cmd_stream_pos++; |
| 208 | |
| 209 | if (m_cmd_stream_pos==8) |
| 210 | { |
| 211 | m_eeprom_we = (m_eeprom_state == EEPROM_WRITE_ENABLE) ? 1 : 0; |
| 212 | m_eeprom_state = EEPROM_GET_CMD; |
| 213 | m_cmd_stream_pos = 0; |
| 214 | } |
| 215 | |
| 216 | break; |
| 217 | |
| 218 | case EEPROM_STATUS_OUTPUT: |
| 219 | m_current_cmd = (m_current_cmd >> 1) | ((m_latch & 1)<< 7); |
| 220 | m_cmd_stream_pos++; |
| 221 | |
| 222 | if (m_cmd_stream_pos==8) |
| 223 | { |
| 224 | printf("Status output\n"); |
| 225 | m_eeprom_state = EEPROM_GET_CMD; |
| 226 | m_cmd_stream_pos = 0; |
| 227 | } |
| 228 | break; |
| 229 | } |
| 230 | } |
| 231 | } |
92 | 232 | } |
| 233 | |