trunk/src/emu/video/pc_vga.c
| r17476 | r17477 | |
|---|
| 193 | 193 | UINT8 crt_reg_lock; |
| 194 | 194 | UINT8 reg_lock1; |
| 195 | 195 | UINT8 reg_lock2; |
| 196 | UINT8 enable_8514; |
| 196 | 197 | }s3; |
| 197 | 198 | |
| 198 | 199 | #define CRTC_PORT_ADDR ((vga.miscellaneous_output&1)?0x3d0:0x3b0) |
| r17476 | r17477 | |
|---|
| 2563 | 2564 | /* TODO: reg lock mechanism */ |
| 2564 | 2565 | s3.reg_lock2 = data; |
| 2565 | 2566 | break; |
| 2567 | case 0x40: |
| 2568 | s3.enable_8514 = data & 0x01; // enable 8514/A registers (x2e8, x6e8, xae8, xee8) |
| 2569 | break; |
| 2566 | 2570 | case 0x51: |
| 2567 | 2571 | vga.crtc.start_addr &= ~0xc0000; |
| 2568 | 2572 | vga.crtc.start_addr |= ((data & 0x3) << 18); |
| r17476 | r17477 | |
|---|
| 2686 | 2690 | } |
| 2687 | 2691 | |
| 2688 | 2692 | /* accelerated ports, TBD ... */ |
| 2689 | | READ8_HANDLER(s3_port_9ae8_r) |
| 2693 | /* |
| 2694 | 9AE8h W(R): Graphics Processor Status Register (GP_STAT) |
| 2695 | bit 0-7 Queue State. |
| 2696 | 00h = 8 words available - queue is empty |
| 2697 | 01h = 7 words available |
| 2698 | 03h = 6 words available |
| 2699 | 07h = 5 words available |
| 2700 | 0Fh = 4 words available |
| 2701 | 1Fh = 3 words available |
| 2702 | 3Fh = 2 words available |
| 2703 | 7Fh = 1 word available |
| 2704 | FFh = 0 words available - queue is full |
| 2705 | 8 (911-928) DTA AVA. Read Data Available. If set data is ready to be |
| 2706 | read from the PIX_TRANS register (E2E8h). |
| 2707 | 9 HDW BSY. Hardware Graphics Processor Busy |
| 2708 | If set the Graphics Processor is busy. |
| 2709 | 10 (928 +) AE. All FIFO Slots Empty. If set all FIFO slots are empty. |
| 2710 | 11-15 (864/964) (R) Queue State bits 8-12. 1Fh if 8 words or less |
| 2711 | available, Fh for 9 words, 7 for 10 words, 3 for 11 words, 1 for |
| 2712 | 12 words and 0 for 13 words available. |
| 2713 | */ |
| 2714 | READ16_HANDLER(s3_port_9ae8_r) |
| 2690 | 2715 | { |
| 2691 | | return 0; |
| 2716 | logerror("S3: 9AE8 read\n"); |
| 2717 | if(s3.enable_8514 != 0) |
| 2718 | return 0; |
| 2719 | else |
| 2720 | return 0xffff; |
| 2692 | 2721 | } |
| 2693 | 2722 | |
| 2694 | | WRITE8_HANDLER(s3_port_9ae8_w) |
| 2723 | /* |
| 2724 | 9AE8h W(W): Drawing Command Register (CMD) |
| 2725 | bit 0 (911-928) ~RD/WT. Read/Write Data. If set VRAM write operations are |
| 2726 | enabled. If clear operations execute normally but writes are |
| 2727 | disabled. |
| 2728 | 1 PX MD. Pixel Mode. Defines the orientation of the display bitmap. |
| 2729 | 0 = Through plane mode (Single pixel transferred at a time) |
| 2730 | 1 = Across plane mode (Multiple pixels transferred at a time). |
| 2731 | 2 LAST PXOF. Last Pixel Off. If set the last pixel of a line command |
| 2732 | (CMD_LINE, SSV or LINEAF) is not drawn. This is used for mixes such |
| 2733 | as XOR where drawing the same pixel twice would give the wrong |
| 2734 | color. |
| 2735 | 3 DIR TYP. Direction Type. |
| 2736 | 0: Bresenham line drawing (X-Y Axial) |
| 2737 | CMD_LINE draws a line using the Bresenham algorithm as |
| 2738 | specified in the DESTY_AXSTP (8AE8h), DESTX_DIASTP (8EE8h), |
| 2739 | ERR_TERM (92E8h) and MAJ_AXIS_PCNT (96E8h) registers |
| 2740 | INC_X, INC_Y and YMAJAXIS determines the direction. |
| 2741 | 1: Vector line draws (Radial). |
| 2742 | CMD_NOP allows drawing of Short Stroke Vectors (SSVs) by |
| 2743 | writing to the Short Stroke register (9EE8h). |
| 2744 | CMD_LINE draws a vector of length MAJ_AXIS_PCNT (96E8h) |
| 2745 | in the direction specified by LINEDIR (bits 5-7). |
| 2746 | DRWG-DIR determines the direction of the line. |
| 2747 | 4 DRAW YES. If clear the current position is moved, but no pixels |
| 2748 | are modified. This bit should be set when attempting read or |
| 2749 | write of bitmap data. |
| 2750 | 5-7 DRWG-DIR. Drawing Direction. When a line draw command (CMD_LINE) |
| 2751 | with DIR TYP=1 (Radial) is issued, these bits define the direction |
| 2752 | of the line counter clockwise relative to the positive X-axis. |
| 2753 | 0 = 000 degrees |
| 2754 | 1 = 045 degrees |
| 2755 | 2 = 090 degrees |
| 2756 | 3 = 135 degrees |
| 2757 | 4 = 180 degrees |
| 2758 | 5 = 225 degrees |
| 2759 | 6 = 270 degrees |
| 2760 | 7 = 315 degrees |
| 2761 | 5 INC_X. This bit together with INC_Y determines which quadrant |
| 2762 | the slope of a line lies within. They also determine the |
| 2763 | orientation of rectangle draw commands. |
| 2764 | If set lines are drawn in the positive X direction (left to right). |
| 2765 | 6 YMAJAXIS. For Bresenham line drawing commands this bit determines |
| 2766 | which axis is the independent or major axis. INC_X and INC_Y |
| 2767 | determines which quadrant the slope falls within. This bit further |
| 2768 | defines the slope to within an octant. |
| 2769 | If set Y is the major (independent) axis. |
| 2770 | 7 INC_Y. This bit together with INC_X determines which quadrant |
| 2771 | the slope of a line lies within. They also determine the |
| 2772 | orientation of rectangle draw commands. |
| 2773 | If set lines are drawn in the positive Y direction (down). |
| 2774 | 8 WAIT YES. If set the drawing engine waits for read/write of the |
| 2775 | PIX_TRANS register (E2E8h) for each pixel during a draw operation. |
| 2776 | 9 (911-928) BUS SIZE. If set the PIX_TRANS register (E2E8h) is |
| 2777 | processed internally as two bytes in the order specified by BYTE |
| 2778 | SWAP. If clear all accesses to E2E8h are 8bit. |
| 2779 | 9-10 (864,964) BUS SIZE. Select System Bus Size. Controls the width of |
| 2780 | the Pixel Data Transfer registers (E2E8h,E2EAh) and the memory |
| 2781 | mapped I/O. 0: 8bit, 1: 16bit, 2: 32bit |
| 2782 | 12 BYTE SWAP. Affects both reads and writes of SHORT_STROKE (9EE8h) |
| 2783 | and PIX_TRANS (E2E8h) when 16bit=1. |
| 2784 | If set take low byte first, if clear take high byte first. |
| 2785 | 13-15 Draw Command: |
| 2786 | 0 = NOP. Used for Short Stroke Vectors. |
| 2787 | 1 = Draw Line. If bit 3 is set the line is drawn to the angle in |
| 2788 | bits 5-7 and the length in the Major Axis Pixel Count register |
| 2789 | (96E8h), if clear the line is drawn from the Bresenham |
| 2790 | constants in the Axial Step Constant register(8AE8h), Diagonal |
| 2791 | Step Constant register (8EE8h), Line Error Term register |
| 2792 | (92E8h) and bits 5-7 of this register. |
| 2793 | 2 = Rectangle Fill. The Destination X (8EE8h) and Y (8AE8h) |
| 2794 | registers holds the coordinates of the rectangle to fill and |
| 2795 | the Major Axis Pixel Count register (96E8h) holds the |
| 2796 | horizontal width (in pixels) fill and the Minor Axis Pixel |
| 2797 | Count register (BEE8h index 0) holds the height of the |
| 2798 | rectangle. |
| 2799 | 6 = BitBLT. Copies the source rectangle specified by the Current X |
| 2800 | (86E8h) and Y (8AE8h) registers to the destination rectangle, |
| 2801 | specified as for the Rectangle Fills. |
| 2802 | 7 = (80x +) Pattern Fill. The source rectangle is an 8x8 pattern |
| 2803 | rectangle, which is copied repeatably to the destination |
| 2804 | rectangle. |
| 2805 | */ |
| 2806 | WRITE16_HANDLER(s3_port_9ae8_w) |
| 2695 | 2807 | { |
| 2696 | | // ... |
| 2808 | /* really needs to be 16-bit... */ |
| 2809 | if(s3.enable_8514 != 0) |
| 2810 | { |
| 2811 | logerror("S3: 9AE8+%i write %04x\n",offset,data); |
| 2812 | } |
| 2813 | else |
| 2814 | logerror("S3: Write to 8514/A port 9ae8 while disabled.\n"); |
| 2697 | 2815 | } |
| 2698 | 2816 | |
| 2699 | 2817 | READ8_HANDLER( s3_mem_r ) |
trunk/src/mess/machine/isa.c
| r17476 | r17477 | |
|---|
| 599 | 599 | } |
| 600 | 600 | } |
| 601 | 601 | |
| 602 | void isa16_device::install16_device(offs_t start, offs_t end, offs_t mask, offs_t mirror, read16_space_func rhandler, const char* rhandler_name, write16_space_func whandler, const char *whandler_name) |
| 603 | { |
| 604 | int buswidth = m_maincpu->memory().space_config(AS_PROGRAM)->m_databus_width; |
| 605 | switch(buswidth) |
| 606 | { |
| 607 | case 16: |
| 608 | m_maincpu->memory().space(AS_IO)->install_legacy_readwrite_handler(start, end, mask, mirror, rhandler, rhandler_name, whandler, whandler_name, 0); |
| 609 | break; |
| 610 | case 32: |
| 611 | m_maincpu->memory().space(AS_IO)->install_legacy_readwrite_handler(start, end, mask, mirror, rhandler, rhandler_name, whandler, whandler_name, 0xffffffff); |
| 612 | if ((start % 4) == 0) { |
| 613 | if ((end-start)==1) { |
| 614 | m_maincpu->memory().space(AS_IO)->install_legacy_readwrite_handler(start, end+2, mask, mirror, rhandler, rhandler_name, whandler, whandler_name, 0x0000ffff); |
| 615 | } else { |
| 616 | m_maincpu->memory().space(AS_IO)->install_legacy_readwrite_handler(start, end, mask, mirror, rhandler, rhandler_name, whandler, whandler_name, 0xffffffff); |
| 617 | } |
| 618 | } else { |
| 619 | // we handle just misalligned by 2 |
| 620 | m_maincpu->memory().space(AS_IO)->install_legacy_readwrite_handler(start-2, end, mask, mirror, rhandler, rhandler_name, whandler, whandler_name, 0xffff0000); |
| 621 | } |
| 622 | |
| 623 | break; |
| 624 | default: |
| 625 | fatalerror("ISA16: Bus width %d not supported", buswidth); |
| 626 | break; |
| 627 | } |
| 628 | } |
| 629 | |
| 602 | 630 | // interrupt request from isa card |
| 603 | 631 | WRITE_LINE_MEMBER( isa16_device::irq10_w ) { m_out_irq10_func(state); } |
| 604 | 632 | WRITE_LINE_MEMBER( isa16_device::irq11_w ) { m_out_irq11_func(state); } |
trunk/src/mess/video/isa_svga_s3.c
| r17476 | r17477 | |
|---|
| 18 | 18 | // GLOBAL VARIABLES |
| 19 | 19 | //************************************************************************** |
| 20 | 20 | |
| 21 | | const device_type ISA8_SVGA_S3 = &device_creator<isa8_svga_s3_device>; |
| 21 | const device_type ISA16_SVGA_S3 = &device_creator<isa16_svga_s3_device>; |
| 22 | 22 | |
| 23 | 23 | |
| 24 | 24 | //------------------------------------------------- |
| r17476 | r17477 | |
|---|
| 26 | 26 | // machine configurations |
| 27 | 27 | //------------------------------------------------- |
| 28 | 28 | |
| 29 | | machine_config_constructor isa8_svga_s3_device::device_mconfig_additions() const |
| 29 | machine_config_constructor isa16_svga_s3_device::device_mconfig_additions() const |
| 30 | 30 | { |
| 31 | 31 | return MACHINE_CONFIG_NAME( pcvideo_vga_isa ); |
| 32 | 32 | } |
| r17476 | r17477 | |
|---|
| 35 | 35 | // rom_region - device-specific ROM region |
| 36 | 36 | //------------------------------------------------- |
| 37 | 37 | |
| 38 | | const rom_entry *isa8_svga_s3_device::device_rom_region() const |
| 38 | const rom_entry *isa16_svga_s3_device::device_rom_region() const |
| 39 | 39 | { |
| 40 | 40 | return ROM_NAME( s3_764 ); |
| 41 | 41 | } |
| r17476 | r17477 | |
|---|
| 48 | 48 | // isa8_vga_device - constructor |
| 49 | 49 | //------------------------------------------------- |
| 50 | 50 | |
| 51 | | isa8_svga_s3_device::isa8_svga_s3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : |
| 52 | | device_t(mconfig, ISA8_SVGA_S3, "SVGA S3 Graphics Card", tag, owner, clock), |
| 53 | | device_isa8_card_interface(mconfig, *this) |
| 51 | isa16_svga_s3_device::isa16_svga_s3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : |
| 52 | device_t(mconfig, ISA16_SVGA_S3, "SVGA S3 Graphics Card", tag, owner, clock), |
| 53 | device_isa16_card_interface(mconfig, *this) |
| 54 | 54 | { |
| 55 | 55 | m_shortname = "s3_764"; |
| 56 | 56 | } |
| r17476 | r17477 | |
|---|
| 60 | 60 | //------------------------------------------------- |
| 61 | 61 | static READ8_HANDLER( input_port_0_r ) { return 0xff; } //return space->machine().root_device().ioport("IN0")->read(); } |
| 62 | 62 | |
| 63 | | void isa8_svga_s3_device::device_start() |
| 63 | void isa16_svga_s3_device::device_start() |
| 64 | 64 | { |
| 65 | 65 | set_isa_device(); |
| 66 | 66 | |
| r17476 | r17477 | |
|---|
| 78 | 78 | m_isa->install_device(0x03b0, 0x03bf, 0, 0, FUNC(s3_port_03b0_r), FUNC(s3_port_03b0_w)); |
| 79 | 79 | m_isa->install_device(0x03c0, 0x03cf, 0, 0, FUNC(s3_port_03c0_r), FUNC(s3_port_03c0_w)); |
| 80 | 80 | m_isa->install_device(0x03d0, 0x03df, 0, 0, FUNC(s3_port_03d0_r), FUNC(s3_port_03d0_w)); |
| 81 | | m_isa->install_device(0x9ae8, 0x9aeb, 0, 0, FUNC(s3_port_9ae8_r), FUNC(s3_port_9ae8_w)); |
| 81 | m_isa->install16_device(0x9ae8, 0x9aeb, 0, 0, FUNC(s3_port_9ae8_r), FUNC(s3_port_9ae8_w)); |
| 82 | 82 | |
| 83 | 83 | m_isa->install_memory(0xa0000, 0xbffff, 0, 0, FUNC(s3_mem_r), FUNC(s3_mem_w)); |
| 84 | 84 | } |
| r17476 | r17477 | |
|---|
| 87 | 87 | // device_reset - device-specific reset |
| 88 | 88 | //------------------------------------------------- |
| 89 | 89 | |
| 90 | | void isa8_svga_s3_device::device_reset() |
| 90 | void isa16_svga_s3_device::device_reset() |
| 91 | 91 | { |
| 92 | 92 | pc_vga_reset(machine()); |
| 93 | 93 | } |