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r17466 Saturday 25th August, 2012 at 12:55:22 UTC by Tafoid
Moved a bunch of other stuff into the device state involving 32x.  There should be no real functional changes at this point.  From Haze (nw)

[src/mame/includes]	megadriv.h
[src/mame/machine]	mega32x.c mega32x.h megadriv.c megavdp.c megavdp.h

trunk/src/mame/machine/mega32x.c

r17465	r17466
201	201
202	202
203	203	/* the main Megadrive emulation needs to know this */
204		int _32x_is_connected;
205	204	cpu_device *_32x_master_cpu;
206	205	cpu_device *_32x_slave_cpu;
207	206
208		/* our current main rendering code needs to know this for mixing in */
209		int _32x_displaymode;
210		int _32x_videopriority;
	207	/* need to make fifo callback part of device */
	208	static UINT16 fifo_block_a[4];
	209	static UINT16 fifo_block_b[4];
	210	static UINT16* current_fifo_block;
	211	static UINT16* current_fifo_readblock;
	212	int current_fifo_write_pos;
	213	int current_fifo_read_pos;
	214	int fifo_block_a_full;
	215	int fifo_block_b_full;
211	216
212		/* our main vblank handler resets this */
213		int _32x_hcount_compare_val;
214	217
215	218
216		static int sh2_are_running;
217		static int _32x_adapter_enabled;
218		static int _32x_access_auth;
219		static int _32x_screenshift;
220
221		static int _32x_240mode;
222
223		static UINT16 _32x_68k_a15104_reg;
224
225
226		static int sh2_master_vint_enable, sh2_slave_vint_enable;
227		static int sh2_master_hint_enable, sh2_slave_hint_enable;
228		static int sh2_master_cmdint_enable, sh2_slave_cmdint_enable;
229		static int sh2_master_pwmint_enable, sh2_slave_pwmint_enable;
230		static int sh2_hint_in_vbl;
231
232		static int sh2_master_vint_pending;
233		static int sh2_slave_vint_pending;
234		static int _32x_fb_swap;
235		static int _32x_hcount_reg;
236
237		void _32x_check_irqs(running_machine& machine);
238
239		#define SH2_VRES_IRQ_LEVEL 14
240		#define SH2_VINT_IRQ_LEVEL 12
241		#define SH2_HINT_IRQ_LEVEL 10
242		#define SH2_CINT_IRQ_LEVEL 8
243		#define SH2_PINT_IRQ_LEVEL 6
244
245
246		static UINT16* _32x_dram0;
247		static UINT16* _32x_dram1;
248		static UINT16 *_32x_display_dram, *_32x_access_dram;
249		static UINT16* _32x_palette;
250		static UINT16* _32x_palette_lookup;
251
252
253
254
255	219	const device_type SEGA_32X_NTSC = &device_creator<sega_32x_ntsc_device>;
256	220	const device_type SEGA_32X_PAL = &device_creator<sega_32x_pal_device>;
257	221
r17465	r17466
277	241
278	242	TIMER_CALLBACK( _32x_pwm_callback );
279	243
280		/****************************************** 32X related ******************************************/
281	244
282		/**********************************************************************************************/
283		// Function Prototypes
284		/**********************************************************************************************/
285	245
286
287
288		static UINT16 _32x_autofill_length;
289		static UINT16 _32x_autofill_address;
290		static UINT16 _32x_autofill_data;
291
292
293
294
295
296
297	246	READ16_MEMBER( sega_32x_device::_32x_68k_palette_r )
298	247	{
299		return _32x_palette[offset];
	248	return m_32x_palette[offset];
300	249	}
301	250
302	251	WRITE16_MEMBER( sega_32x_device::_32x_68k_palette_w )
303	252	{
304	253	int r,g,b, p;
305	254
306		COMBINE_DATA(&_32x_palette[offset]);
307		data = _32x_palette[offset];
	255	COMBINE_DATA(&m_32x_palette[offset]);
	256	data = m_32x_palette[offset];
308	257
309	258	r = ((data >> 0)  & 0x1f);
310	259	g = ((data >> 5)  & 0x1f);
311	260	b = ((data >> 10) & 0x1f);
312	261	p = ((data >> 15) & 0x01); // priority 'through' bit
313	262
314		_32x_palette_lookup[offset] = (r << 10) | (g << 5) | (b << 0) | (p << 15);
	263	m_32x_palette_lookup[offset] = (r << 10) | (g << 5) | (b << 0) | (p << 15);
315	264
316	265	palette_set_color_rgb(space.machine(),offset+0x40,pal5bit(r),pal5bit(g),pal5bit(b));
317	266
r17465	r17466
319	268
320	269	READ16_MEMBER( sega_32x_device::_32x_68k_dram_r )
321	270	{
322		return _32x_access_dram[offset];
	271	return m_32x_access_dram[offset];
323	272	}
324	273
325	274	WRITE16_MEMBER( sega_32x_device::_32x_68k_dram_w )
r17465	r17466
327	276	if ((mem_mask&0xffff) == 0xffff)
328	277	{
329	278	// 16-bit accesses are normal
330		COMBINE_DATA(&_32x_access_dram[offset]);
	279	COMBINE_DATA(&m_32x_access_dram[offset]);
331	280	}
332	281	else
333	282	{
r17465	r17466
339	288	{
340	289	if ((data & 0xff00) != 0x0000)
341	290	{
342		_32x_access_dram[offset] = (data & 0xff00) |  (_32x_access_dram[offset] & 0x00ff);
	291	m_32x_access_dram[offset] = (data & 0xff00) |  (m_32x_access_dram[offset] & 0x00ff);
343	292	}
344	293	}
345	294	else if ((mem_mask & 0xffff) == 0x00ff)
346	295	{
347	296	if ((data & 0x00ff) != 0x0000)
348	297	{
349		_32x_access_dram[offset] = (data & 0x00ff) |  (_32x_access_dram[offset] & 0xff00);
	298	m_32x_access_dram[offset] = (data & 0x00ff) |  (m_32x_access_dram[offset] & 0xff00);
350	299	}
351	300	}
352	301	}
r17465	r17466
354	303
355	304	READ16_MEMBER( sega_32x_device::_32x_68k_dram_overwrite_r )
356	305	{
357		return _32x_access_dram[offset];
	306	return m_32x_access_dram[offset];
358	307	}
359	308
360	309	WRITE16_MEMBER( sega_32x_device::_32x_68k_dram_overwrite_w )
361	310	{
362		//COMBINE_DATA(&_32x_access_dram[offset+0x10000]);
	311	//COMBINE_DATA(&m_32x_access_dram[offset+0x10000]);
363	312
364	313	if (ACCESSING_BITS_8_15)
365	314	{
366	315	if (data & 0xff00)
367	316	{
368		_32x_access_dram[offset] = (_32x_access_dram[offset]&0x00ff) | (data & 0xff00);
	317	m_32x_access_dram[offset] = (m_32x_access_dram[offset]&0x00ff) | (data & 0xff00);
369	318	}
370	319	}
371	320
r17465	r17466
373	322	{
374	323	if (data & 0x00ff)
375	324	{
376		_32x_access_dram[offset] = (_32x_access_dram[offset]&0xff00) | (data & 0x00ff);
	325	m_32x_access_dram[offset] = (m_32x_access_dram[offset]&0xff00) | (data & 0x00ff);
377	326	}
378	327	}
379	328	}
r17465	r17466
383	332	// FIFO
384	333	/**********************************************************************************************/
385	334
386		static UINT16 fifo_block_a[4];
387		static UINT16 fifo_block_b[4];
388		static UINT16* current_fifo_block;
389		static UINT16* current_fifo_readblock;
390		int current_fifo_write_pos;
391		int current_fifo_read_pos;
392		int fifo_block_a_full;
393		int fifo_block_b_full;
394	335
395	336
396	337
397
398	338	/*
399	339
400	340	15106 DREQ
r17465	r17466
408	348
409	349	*/
410	350
411		static UINT16 a15106_reg;
412	351
413	352
	353
414	354	READ16_MEMBER( sega_32x_device::_32x_68k_a15106_r )
415	355	{
416	356	UINT16 retval;
417	357
418		retval = a15106_reg;
	358	retval = m_a15106_reg;
419	359
420	360	if (fifo_block_a_full && fifo_block_b_full) retval |= 0x8080;
421	361
r17465	r17466
426	366	{
427	367	if (ACCESSING_BITS_0_7)
428	368	{
429		a15106_reg = data & 0x7;
	369	m_a15106_reg = data & 0x7;
430	370
431		if (a15106_reg & 0x1) /* NBA Jam TE relies on this */
	371	if (m_a15106_reg & 0x1) /* NBA Jam TE relies on this */
432	372	{
433	373
434	374	// install the game rom in the normal 0x000000-0x03fffff space used by the genesis - this allows VDP DMA operations to work as they have to be from this area or RAM
r17465	r17466
444	384	space.install_rom(0x0000100, 0x03fffff, space.machine().root_device().memregion("maincpu")->base()+0x100);
445	385	}
446	386
447		if((a15106_reg & 4) == 0) // clears the FIFO state
	387	if((m_a15106_reg & 4) == 0) // clears the FIFO state
448	388	{
449	389	current_fifo_block = fifo_block_a;
450	390	current_fifo_readblock = fifo_block_b;
r17465	r17466
456	396
457	397	//printf("_32x_68k_a15106_w %04x\n", data);
458	398	/*
459		if (a15106_reg & 0x4)
	399	if (m_a15106_reg & 0x4)
460	400	printf(" --- 68k Write Mode enabled\n");
461	401	else
462	402	printf(" --- 68k Write Mode disabled\n");
463	403
464		if (a15106_reg & 0x1)
	404	if (m_a15106_reg & 0x1)
465	405	printf(" --- DMA Start Allowed \n");
466	406	else
467	407	printf(" --- DMA Start No Operation\n");
r17465	r17466
470	410	}
471	411	}
472	412
473		static UINT16 dreq_src_addr[2],dreq_dst_addr[2],dreq_size;
474	413
	414
475	415	READ16_MEMBER( sega_32x_device::_32x_dreq_common_r )
476	416	{
477	417	address_space* _68kspace = space.machine().device("maincpu")->memory().space(AS_PROGRAM);
r17465	r17466
480	420	{
481	421	case 0x00/2: // a15108 / 4008
482	422	case 0x02/2: // a1510a / 400a
483		return dreq_src_addr[offset&1];
	423	return m_dreq_src_addr[offset&1];
484	424
485	425	case 0x04/2: // a1510c / 400c
486	426	case 0x06/2: // a1510e / 400e
487		return dreq_dst_addr[offset&1];
	427	return m_dreq_dst_addr[offset&1];
488	428
489	429	case 0x08/2: // a15110 / 4010
490		return dreq_size;
	430	return m_dreq_size;
491	431
492	432	case 0x0a/2: // a15112 / 4012
493	433	if (&space == _68kspace)
r17465	r17466
557	497	return;
558	498	}
559	499
560		dreq_src_addr[offset&1] = ((offset&1) == 0) ? (data & 0xff) : (data & 0xfffe);
	500	m_dreq_src_addr[offset&1] = ((offset&1) == 0) ? (data & 0xff) : (data & 0xfffe);
561	501
562		//if((dreq_src_addr[0]<<16)|dreq_src_addr[1])
563		//  printf("DREQ set SRC = %08x\n",(dreq_src_addr[0]<<16)|dreq_src_addr[1]);
	502	//if((m_dreq_src_addr[0]<<16)|m_dreq_src_addr[1])
	503	//  printf("DREQ set SRC = %08x\n",(m_dreq_src_addr[0]<<16)|m_dreq_src_addr[1]);
564	504
565	505	break;
566	506
r17465	r17466
572	512	return;
573	513	}
574	514
575		dreq_dst_addr[offset&1] = ((offset&1) == 0) ? (data & 0xff) : (data & 0xffff);
	515	m_dreq_dst_addr[offset&1] = ((offset&1) == 0) ? (data & 0xff) : (data & 0xffff);
576	516
577		//if((dreq_dst_addr[0]<<16)|dreq_dst_addr[1])
578		//  printf("DREQ set DST = %08x\n",(dreq_dst_addr[0]<<16)|dreq_dst_addr[1]);
	517	//if((m_dreq_dst_addr[0]<<16)|m_dreq_dst_addr[1])
	518	//  printf("DREQ set DST = %08x\n",(m_dreq_dst_addr[0]<<16)|m_dreq_dst_addr[1]);
579	519
580	520	break;
581	521
r17465	r17466
586	526	return;
587	527	}
588	528
589		dreq_size = data & 0xfffc;
	529	m_dreq_size = data & 0xfffc;
590	530
591		//  if(dreq_size)
592		//      printf("DREQ set SIZE = %04x\n",dreq_size);
	531	//  if(m_dreq_size)
	532	//      printf("DREQ set SIZE = %04x\n",m_dreq_size);
593	533
594	534	break;
595	535
r17465	r17466
612	552	return;
613	553	}
614	554
615		if((a15106_reg & 4) == 0)
	555	if((m_a15106_reg & 4) == 0)
616	556	{
617	557	printf("attempting to WRITE FIFO with 68S cleared!\n"); // corpse32
618	558	return;
r17465	r17466
660	600	}
661	601
662	602
663		static UINT8 sega_tv;
664	603
	604
665	605	READ16_MEMBER( sega_32x_device::_32x_68k_a1511a_r )
666	606	{
667		return sega_tv;
	607	return m_sega_tv;
668	608	}
669	609
670	610	WRITE16_MEMBER( sega_32x_device::_32x_68k_a1511a_w )
671	611	{
672		sega_tv = data & 1;
	612	m_sega_tv = data & 1;
673	613
674	614	printf("SEGA TV register set = %04x\n",data);
675	615	}
r17465	r17466
678	618	000070 H interrupt vector can be overwritten apparently
679	619	*/
680	620
681		static UINT16 hint_vector[2];
682	621
683		READ16_MEMBER( sega_32x_device::_32x_68k_hint_vector_r )
	622
	623	READ16_MEMBER( sega_32x_device::_32x_68k_m_hint_vector_r )
684	624	{
685		return hint_vector[offset];
	625	return m_hint_vector[offset];
686	626	}
687	627
688		WRITE16_MEMBER( sega_32x_device::_32x_68k_hint_vector_w )
	628	WRITE16_MEMBER( sega_32x_device::_32x_68k_m_hint_vector_w )
689	629	{
690		hint_vector[offset] = data;
	630	m_hint_vector[offset] = data;
691	631	}
692	632
693	633	// returns MARS, the system ID of the 32x
r17465	r17466
711	651	// control register - used to enable 32x etc.
712	652	/**********************************************************************************************/
713	653
714		static UINT16 a15100_reg;
715	654
	655
716	656	READ16_MEMBER( sega_32x_device::_32x_68k_a15100_r )
717	657	{
718		return (_32x_access_auth<<15) | 0x0080;
	658	return (m_32x_access_auth<<15) | 0x0080;
719	659	}
720	660
721	661	WRITE16_MEMBER( sega_32x_device::_32x_68k_a15100_w )
722	662	{
723	663	if (ACCESSING_BITS_0_7)
724	664	{
725		a15100_reg = (a15100_reg & 0xff00) | (data & 0x00ff);
	665	m_a15100_reg = (m_a15100_reg & 0xff00) | (data & 0x00ff);
726	666
727	667	if (data & 0x02)
728	668	{
r17465	r17466
732	672
733	673	if (data & 0x01)
734	674	{
735		_32x_adapter_enabled = 1;
	675	m_32x_adapter_enabled = 1;
736	676	space.install_rom(0x0880000, 0x08fffff, space.machine().root_device().memregion("gamecart")->base()); // 'fixed' 512kb rom bank
737	677
738	678	space.install_read_bank(0x0900000, 0x09fffff, "bank12"); // 'bankable' 1024kb rom bank
739		space.machine().root_device().membank("bank12")->set_base(space.machine().root_device().memregion("gamecart")->base()+((_32x_68k_a15104_reg&0x3)*0x100000) );
	679	space.machine().root_device().membank("bank12")->set_base(space.machine().root_device().memregion("gamecart")->base()+((m_32x_68k_a15104_reg&0x3)*0x100000) );
740	680
741	681	space.install_rom(0x0000000, 0x03fffff, space.machine().root_device().memregion("32x_68k_bios")->base());
742	682
r17465	r17466
748	688
749	689
750	690
751		space.machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_hint_vector_w),this)); // h interrupt vector
	691	space.machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_w),this)); // h interrupt vector
752	692	}
753	693	else
754	694	{
755		_32x_adapter_enabled = 0;
	695	m_32x_adapter_enabled = 0;
756	696
757	697	space.install_rom(0x0000000, 0x03fffff, space.machine().root_device().memregion("gamecart")->base());
758		space.machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_hint_vector_w),this)); // h interrupt vector
	698	space.machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_w),this)); // h interrupt vector
759	699	}
760	700	}
761	701
762	702	if (ACCESSING_BITS_8_15)
763	703	{
764		a15100_reg = (a15100_reg & 0x00ff) | (data & 0xff00);
765		_32x_access_auth = (data & 0x8000)>>15;
	704	m_a15100_reg = (m_a15100_reg & 0x00ff) | (data & 0xff00);
	705	m_32x_access_auth = (data & 0x8000)>>15;
766	706	}
767	707	}
768	708
r17465	r17466
771	711	// command interrupt to SH2
772	712	/**********************************************************************************************/
773	713
774		static int _32x_68k_a15102_reg;
775	714
	715
776	716	READ16_MEMBER( sega_32x_device::_32x_68k_a15102_r )
777	717	{
778	718	//printf("_32x_68k_a15102_r\n");
779		return _32x_68k_a15102_reg;
	719	return m_32x_68k_a15102_reg;
780	720	}
781	721
782	722	WRITE16_MEMBER( sega_32x_device::_32x_68k_a15102_w )
783	723	{
784	724	if (ACCESSING_BITS_0_7)
785	725	{
786		_32x_68k_a15102_reg = data & 3;
	726	m_32x_68k_a15102_reg = data & 3;
787	727
788	728	if (data&0x1)
789	729	{
790		if (sh2_master_cmdint_enable) device_set_input_line(_32x_master_cpu,SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
	730	if (m_sh2_master_cmdint_enable) device_set_input_line(_32x_master_cpu,SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
791	731	else printf("master cmdint when masked!\n");
792	732	}
793	733
794	734	if (data&0x2)
795	735	{
796		if (sh2_slave_cmdint_enable) device_set_input_line(_32x_slave_cpu,SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
	736	if (m_sh2_slave_cmdint_enable) device_set_input_line(_32x_slave_cpu,SH2_CINT_IRQ_LEVEL,ASSERT_LINE);
797	737	else printf("slave cmdint when masked!\n");
798	738	}
799	739	}
r17465	r17466
807	747
808	748	READ16_MEMBER( sega_32x_device::_32x_68k_a15104_r )
809	749	{
810		return _32x_68k_a15104_reg;
	750	return m_32x_68k_a15104_reg;
811	751	}
812	752
813	753	WRITE16_MEMBER( sega_32x_device::_32x_68k_a15104_w )
814	754	{
815	755	if (ACCESSING_BITS_0_7)
816	756	{
817		_32x_68k_a15104_reg = (_32x_68k_a15104_reg & 0xff00) | (data & 0x00ff);
	757	m_32x_68k_a15104_reg = (m_32x_68k_a15104_reg & 0xff00) | (data & 0x00ff);
818	758	}
819	759
820	760	if (ACCESSING_BITS_8_15)
821	761	{
822		_32x_68k_a15104_reg = (_32x_68k_a15104_reg & 0x00ff) | (data & 0xff00);
	762	m_32x_68k_a15104_reg = (m_32x_68k_a15104_reg & 0x00ff) | (data & 0xff00);
823	763	}
824	764
825		space.machine().root_device().membank("bank12")->set_base(space.machine().root_device().memregion("gamecart")->base()+((_32x_68k_a15104_reg&0x3)*0x100000) );
	765	space.machine().root_device().membank("bank12")->set_base(space.machine().root_device().memregion("gamecart")->base()+((m_32x_68k_a15104_reg&0x3)*0x100000) );
826	766	}
827	767
828	768	/**********************************************************************************************/
r17465	r17466
830	770	// Communication Port 0
831	771	// access from the SH2 via 4020 - 402f
832	772	/**********************************************************************************************/
833		#define _32X_COMMS_PORT_SYNC 0
834		static UINT16 commsram[8];
835	773
	774
836	775	/**********************************************************************************************/
837	776
838	777	// reads
839		READ16_MEMBER( sega_32x_device::_32x_68k_commsram_r )
	778	READ16_MEMBER( sega_32x_device::_32x_68k_m_commsram_r )
840	779	{
841	780	if (_32X_COMMS_PORT_SYNC) space.machine().scheduler().synchronize();
842		return commsram[offset];
	781	return m_commsram[offset];
843	782	}
844	783
845	784	// writes
846		WRITE16_MEMBER( sega_32x_device::_32x_68k_commsram_w )
	785	WRITE16_MEMBER( sega_32x_device::_32x_68k_m_commsram_w )
847	786	{
848		COMBINE_DATA(&commsram[offset]);
	787	COMBINE_DATA(&m_commsram[offset]);
849	788	if (_32X_COMMS_PORT_SYNC) space.machine().scheduler().synchronize();
850	789	}
851	790
r17465	r17466
861	800	- Understand if Speaker OFF makes the FIFO to advance or not
862	801	*/
863	802
864		#define PWM_FIFO_SIZE pwm_tm_reg // guess, Marsch calls this register as FIFO width
865		#define PWM_CLOCK megadrive_region_pal ? ((MASTER_CLOCK_PAL*3) / 7) : ((MASTER_CLOCK_NTSC*3) / 7)
866	803
867		static UINT16 pwm_ctrl,pwm_cycle,pwm_tm_reg;
868		static UINT16 cur_lch[0x10],cur_rch[0x10];
869		static UINT16 pwm_cycle_reg; //used for latching
870		static UINT8 pwm_timer_tick;
871		static UINT8 lch_index_r,rch_index_r,lch_index_w,rch_index_w;
872		static UINT16 lch_fifo_state,rch_fifo_state;
873	804
874	805
875
876		static void calculate_pwm_timer(running_machine &machine)
	806	void sega_32x_device::calculate_pwm_timer(running_machine &machine)
877	807	{
878		sega_32x_device* _32xdev = (sega_32x_device*)machine.device(":sega32x");
	808	if(m_pwm_tm_reg == 0) { m_pwm_tm_reg = 16; } // zero gives max range
	809	if(m_pwm_cycle == 0) { m_pwm_cycle = 4095; } // zero gives max range
879	810
880
881		if(pwm_tm_reg == 0) { pwm_tm_reg = 16; } // zero gives max range
882		if(pwm_cycle == 0) { pwm_cycle = 4095; } // zero gives max range
883
884	811	/* if both RMD and LMD are set to OFF or pwm cycle register is one, then PWM timer ticks doesn't occur */
885		if(pwm_cycle == 1 || ((pwm_ctrl & 0xf) == 0))
886		_32xdev->m_32x_pwm_timer->adjust(attotime::never);
	812	if(m_pwm_cycle == 1 || ((m_pwm_ctrl & 0xf) == 0))
	813	m_32x_pwm_timer->adjust(attotime::never);
887	814	else
888	815	{
889		pwm_timer_tick = 0;
890		lch_fifo_state = rch_fifo_state = 0x4000;
891		lch_index_r = rch_index_r = 0;
892		lch_index_w = rch_index_w = 0;
893		_32xdev->m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
	816	m_pwm_timer_tick = 0;
	817	m_lch_fifo_state = m_rch_fifo_state = 0x4000;
	818	m_lch_index_r = m_rch_index_r = 0;
	819	m_lch_index_w = m_rch_index_w = 0;
	820	m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (m_pwm_cycle - 1)));
894	821	}
895	822	}
896	823
897		TIMER_CALLBACK( _32x_pwm_callback )
898		{
899		sega_32x_device* _32xdev = (sega_32x_device*)ptr;
900	824
901
902		if(lch_index_r < PWM_FIFO_SIZE)
	825	void sega_32x_device::handle_pwm_callback(void)
	826	{
	827	if(m_lch_index_r < PWM_FIFO_SIZE)
903	828	{
904		switch(pwm_ctrl & 3)
	829	switch(m_pwm_ctrl & 3)
905	830	{
906		case 0: lch_index_r++; /*Speaker OFF*/ break;
907		case 1: _32xdev->m_lch_pwm->write_signed16(cur_lch[lch_index_r++]); break;
908		case 2: _32xdev->m_rch_pwm->write_signed16(cur_lch[lch_index_r++]); break;
	831	case 0: m_lch_index_r++; /*Speaker OFF*/ break;
	832	case 1: m_lch_pwm->write_signed16(m_cur_lch[m_lch_index_r++]); break;
	833	case 2: m_rch_pwm->write_signed16(m_cur_lch[m_lch_index_r++]); break;
909	834	case 3: popmessage("Undefined PWM Lch value 3, contact MESSdev"); break;
910	835	}
911	836
912		lch_index_w = 0;
	837	m_lch_index_w = 0;
913	838	}
914	839
915		lch_fifo_state = (lch_index_r == PWM_FIFO_SIZE) ? 0x4000 : 0x0000;
	840	m_lch_fifo_state = (m_lch_index_r == PWM_FIFO_SIZE) ? 0x4000 : 0x0000;
916	841
917		if(rch_index_r < PWM_FIFO_SIZE)
	842	if(m_rch_index_r < PWM_FIFO_SIZE)
918	843	{
919		switch((pwm_ctrl & 0xc) >> 2)
	844	switch((m_pwm_ctrl & 0xc) >> 2)
920	845	{
921		case 0: rch_index_r++; /*Speaker OFF*/ break;
922		case 1: _32xdev->m_rch_pwm->write_signed16(cur_rch[rch_index_r++]); break;
923		case 2: _32xdev->m_lch_pwm->write_signed16(cur_rch[rch_index_r++]); break;
	846	case 0: m_rch_index_r++; /*Speaker OFF*/ break;
	847	case 1: m_rch_pwm->write_signed16(m_cur_rch[m_rch_index_r++]); break;
	848	case 2: m_lch_pwm->write_signed16(m_cur_rch[m_rch_index_r++]); break;
924	849	case 3: popmessage("Undefined PWM Rch value 3, contact MESSdev"); break;
925	850	}
926	851
927		rch_index_w = 0;
	852	m_rch_index_w = 0;
928	853	}
929	854
930		rch_fifo_state = (rch_index_r == PWM_FIFO_SIZE) ? 0x4000 : 0x0000;
	855	m_rch_fifo_state = (m_rch_index_r == PWM_FIFO_SIZE) ? 0x4000 : 0x0000;
931	856
932		pwm_timer_tick++;
	857	m_pwm_timer_tick++;
933	858
934		if(pwm_timer_tick == pwm_tm_reg)
	859	if(m_pwm_timer_tick == m_pwm_tm_reg)
935	860	{
936		pwm_timer_tick = 0;
	861	m_pwm_timer_tick = 0;
937	862	if(sh2_master_pwmint_enable) { device_set_input_line(_32x_master_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
938	863	if(sh2_slave_pwmint_enable) { device_set_input_line(_32x_slave_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
939	864	}
940	865
941		_32xdev->m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
	866	m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (m_pwm_cycle - 1)));
942	867	}
943	868
	869	TIMER_CALLBACK( _32x_pwm_callback )
	870	{
	871	sega_32x_device* _32xdev = (sega_32x_device*)ptr;
	872	_32xdev->handle_pwm_callback();
	873	}
	874
944	875	READ16_MEMBER( sega_32x_device::_32x_pwm_r )
945	876	{
946	877	switch(offset)
947	878	{
948		case 0x00/2: return pwm_ctrl; //control register
949		case 0x02/2: return pwm_cycle_reg; // cycle register
950		case 0x04/2: return lch_fifo_state; // l ch
951		case 0x06/2: return rch_fifo_state; // r ch
952		case 0x08/2: return lch_fifo_state & rch_fifo_state; // mono ch
	879	case 0x00/2: return m_pwm_ctrl; //control register
	880	case 0x02/2: return m_pwm_cycle_reg; // cycle register
	881	case 0x04/2: return m_lch_fifo_state; // l ch
	882	case 0x06/2: return m_rch_fifo_state; // r ch
	883	case 0x08/2: return m_lch_fifo_state & m_rch_fifo_state; // mono ch
953	884	}
954	885
955	886	printf("Read at undefined PWM register %02x\n",offset);
r17465	r17466
962	893	switch(offset)
963	894	{
964	895	case 0x00/2:
965		pwm_ctrl = data & 0xffff;
966		pwm_tm_reg = (pwm_ctrl & 0xf00) >> 8;
	896	m_pwm_ctrl = data & 0xffff;
	897	m_pwm_tm_reg = (m_pwm_ctrl & 0xf00) >> 8;
967	898	calculate_pwm_timer(space.machine());
968	899	break;
969	900	case 0x02/2:
970		pwm_cycle = pwm_cycle_reg = data & 0xfff;
	901	m_pwm_cycle = m_pwm_cycle_reg = data & 0xfff;
971	902	calculate_pwm_timer(space.machine());
972	903	break;
973	904	case 0x04/2:
974		if(lch_index_w < PWM_FIFO_SIZE)
	905	if(m_lch_index_w < PWM_FIFO_SIZE)
975	906	{
976		cur_lch[lch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
977		lch_index_r = 0;
	907	m_cur_lch[m_lch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
	908	m_lch_index_r = 0;
978	909	}
979	910
980		lch_fifo_state = (lch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
	911	m_lch_fifo_state = (m_lch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
981	912	break;
982	913	case 0x06/2:
983		if(rch_index_w < PWM_FIFO_SIZE)
	914	if(m_rch_index_w < PWM_FIFO_SIZE)
984	915	{
985		cur_rch[rch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
986		rch_index_r = 0;
	916	m_cur_rch[m_rch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
	917	m_rch_index_r = 0;
987	918	}
988	919
989		rch_fifo_state = (rch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
	920	m_rch_fifo_state = (m_rch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
990	921
991	922	break;
992	923	case 0x08/2:
993		if(lch_index_w < PWM_FIFO_SIZE)
	924	if(m_lch_index_w < PWM_FIFO_SIZE)
994	925	{
995		cur_lch[lch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
996		lch_index_r = 0;
	926	m_cur_lch[m_lch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
	927	m_lch_index_r = 0;
997	928	}
998	929
999		if(rch_index_w < PWM_FIFO_SIZE)
	930	if(m_rch_index_w < PWM_FIFO_SIZE)
1000	931	{
1001		cur_rch[rch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
1002		rch_index_r = 0;
	932	m_cur_rch[m_rch_index_w++] = ((data & 0xfff) << 4) | (data & 0xf);
	933	m_rch_index_r = 0;
1003	934	}
1004	935
1005		lch_fifo_state = (lch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
1006		rch_fifo_state = (rch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
	936	m_lch_fifo_state = (m_lch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
	937	m_rch_fifo_state = (m_rch_index_w == PWM_FIFO_SIZE) ? 0x8000 : 0x0000;
1007	938
1008	939	break;
1009	940	default:
r17465	r17466
1015	946	WRITE16_MEMBER( sega_32x_device::_32x_68k_pwm_w )
1016	947	{
1017	948	if(offset == 0/2)
1018		_32x_pwm_w(space,offset,(data & 0x7f) | (pwm_ctrl & 0xff80),mem_mask);
	949	_32x_pwm_w(space,offset,(data & 0x7f) | (m_pwm_ctrl & 0xff80),mem_mask);
1019	950	else
1020	951	_32x_pwm_w(space,offset,data,mem_mask);
1021	952	}
r17465	r17466
1026	957	// also accessed from the SH2 @ 4100
1027	958	/**********************************************************************************************/
1028	959
1029		static UINT16 _32x_a1518a_reg;
1030		#define MAX_HPOSITION 480
1031
1032		static UINT16 get_hposition(void)
	960	UINT16 sega_32x_device::get_hposition(void)
1033	961	{
1034	962	attotime time_elapsed_since_megadriv_scanline_timer;
1035	963	UINT16 value4;
r17465	r17466
1067	995	else ntsc = 1;
1068	996
1069	997	return (ntsc << 15) |
1070		(_32x_videopriority << 7 ) |
1071		( _32x_240mode << 6 ) |
1072		( _32x_displaymode << 0 );
	998	(m_32x_videopriority << 7 ) |
	999	( m_32x_240mode << 6 ) |
	1000	( m_32x_displaymode << 0 );
1073	1001
1074	1002
1075	1003
1076	1004	case 0x02/2:
1077		return _32x_screenshift;
	1005	return m_32x_screenshift;
1078	1006
1079	1007	case 0x04/2:
1080		return _32x_autofill_length;
	1008	return m_32x_autofill_length;
1081	1009
1082	1010	case 0x06/2:
1083		return _32x_autofill_address;
	1011	return m_32x_autofill_address;
1084	1012
1085	1013	case 0x08/2:
1086		return _32x_autofill_data;
	1014	return m_32x_autofill_data;
1087	1015
1088	1016	case 0x0a/2:
1089		UINT16 retdata = _32x_a1518a_reg;
	1017	UINT16 retdata = m_32x_a1518a_reg;
1090	1018	UINT16 hpos = get_hposition();
1091	1019	int megadrive_hblank_flag = 0;
1092	1020
r17465	r17466
1108	1036	}
1109	1037
1110	1038
1111		void _32x_check_framebuffer_swap(void)
	1039	void sega_32x_device::_32x_check_framebuffer_swap(void)
1112	1040	{
1113
1114		if(_32x_is_connected)
	1041	// this logic should be correct, but makes things worse?
	1042	//if (genesis_scanline_counter >= megadrive_irq6_scanline)
1115	1043	{
	1044	m_32x_a1518a_reg = m_32x_fb_swap & 1;
1116	1045
1117		// this logic should be correct, but makes things worse?
1118		//if (genesis_scanline_counter >= megadrive_irq6_scanline)
1119		{
1120		_32x_a1518a_reg = _32x_fb_swap & 1;
1121	1046
1122	1047
1123
1124		if (_32x_fb_swap & 1)
1125		{
1126		_32x_access_dram = _32x_dram0;
1127		_32x_display_dram = _32x_dram1;
1128		}
1129		else
1130		{
1131		_32x_display_dram = _32x_dram0;
1132		_32x_access_dram = _32x_dram1;
1133		}
	1048	if (m_32x_fb_swap & 1)
	1049	{
	1050	m_32x_access_dram = m_32x_dram0;
	1051	m_32x_display_dram = m_32x_dram1;
1134	1052	}
	1053	else
	1054	{
	1055	m_32x_display_dram = m_32x_dram0;
	1056	m_32x_access_dram = m_32x_dram1;
	1057	}
1135	1058	}
1136	1059	}
1137	1060
r17465	r17466
1144	1067
1145	1068	if (&space!= _68kspace)
1146	1069	{
1147		if (_32x_access_auth!=1)
	1070	if (m_32x_access_auth!=1)
1148	1071	return;
1149	1072	}
1150	1073
1151	1074	if (&space== _68kspace)
1152	1075	{
1153		if (_32x_access_auth!=0)
	1076	if (m_32x_access_auth!=0)
1154	1077	return;
1155	1078	}
1156	1079
r17465	r17466
1159	1082	{
1160	1083
1161	1084	case 0x00:
1162		//printf("_32x_68k_a15180_w (a15180) %04x %04x   source _32x_access_auth %04x\n",data,mem_mask, _32x_access_auth);
	1085	//printf("_32x_68k_a15180_w (a15180) %04x %04x   source m_32x_access_auth %04x\n",data,mem_mask, m_32x_access_auth);
1163	1086
1164	1087	if (ACCESSING_BITS_0_7)
1165	1088	{
1166		_32x_videopriority = (data & 0x80) >> 7;
1167		_32x_240mode   = (data & 0x40) >> 6;
1168		_32x_displaymode   = (data & 0x03) >> 0;
	1089	m_32x_videopriority = (data & 0x80) >> 7;
	1090	m_32x_240mode   = (data & 0x40) >> 6;
	1091	m_32x_displaymode   = (data & 0x03) >> 0;
1169	1092	}
1170	1093	break;
1171	1094
1172	1095	case 0x02/2:
1173	1096	if (ACCESSING_BITS_0_7)
1174	1097	{
1175		_32x_screenshift = data & 1; // allows 1 pixel shifting
	1098	m_32x_screenshift = data & 1; // allows 1 pixel shifting
1176	1099	}
1177	1100	if (ACCESSING_BITS_8_15)
1178	1101	{
r17465	r17466
1183	1106	case 0x04/2:
1184	1107	if (ACCESSING_BITS_0_7)
1185	1108	{
1186		_32x_autofill_length = data & 0xff;
	1109	m_32x_autofill_length = data & 0xff;
1187	1110	}
1188	1111
1189	1112	if (ACCESSING_BITS_8_15)
r17465	r17466
1195	1118	case 0x06/2:
1196	1119	if (ACCESSING_BITS_0_7)
1197	1120	{
1198		_32x_autofill_address = (_32x_autofill_address & 0xff00) | (data & 0x00ff);
	1121	m_32x_autofill_address = (m_32x_autofill_address & 0xff00) | (data & 0x00ff);
1199	1122	}
1200	1123
1201	1124	if (ACCESSING_BITS_8_15)
1202	1125	{
1203		_32x_autofill_address = (_32x_autofill_address & 0x00ff) | (data & 0xff00);
	1126	m_32x_autofill_address = (m_32x_autofill_address & 0x00ff) | (data & 0xff00);
1204	1127	}
1205	1128	break;
1206	1129
1207	1130	case 0x08/2:
1208	1131	if (ACCESSING_BITS_0_7)
1209	1132	{
1210		_32x_autofill_data = (_32x_autofill_data & 0xff00) | (data & 0x00ff);
	1133	m_32x_autofill_data = (m_32x_autofill_data & 0xff00) | (data & 0x00ff);
1211	1134	}
1212	1135
1213	1136	if (ACCESSING_BITS_8_15)
1214	1137	{
1215		_32x_autofill_data = (_32x_autofill_data & 0x00ff) | (data & 0xff00);
	1138	m_32x_autofill_data = (m_32x_autofill_data & 0x00ff) | (data & 0xff00);
1216	1139	}
1217	1140
1218	1141	// do the fill - shouldn't be instant..
1219	1142	{
1220	1143	int i;
1221		for (i=0; i<_32x_autofill_length+1;i++)
	1144	for (i=0; i<m_32x_autofill_length+1;i++)
1222	1145	{
1223		_32x_access_dram[_32x_autofill_address] = _32x_autofill_data;
1224		_32x_autofill_address = (_32x_autofill_address & 0xff00) | ((_32x_autofill_address+1) & 0x00ff);
	1146	m_32x_access_dram[m_32x_autofill_address] = m_32x_autofill_data;
	1147	m_32x_autofill_address = (m_32x_autofill_address & 0xff00) | ((m_32x_autofill_address+1) & 0x00ff);
1225	1148	}
1226	1149	}
1227	1150	break;
1228	1151
1229	1152	case 0x0a/2:
1230	1153	// bit 0 is the framebuffer select, change is delayed until vblank;
1231		//  _32x_a1518a_reg = (_32x_a1518a_reg & 0xfffe);
	1154	//  m_32x_a1518a_reg = (m_32x_a1518a_reg & 0xfffe);
1232	1155	if (ACCESSING_BITS_0_7)
1233	1156	{
1234		_32x_fb_swap = data & 1;
	1157	m_32x_fb_swap = data & 1;
1235	1158
1236	1159	_32x_check_framebuffer_swap();
1237	1160	}
r17465	r17466
1271	1194	READ16_MEMBER( sega_32x_device::_32x_sh2_master_4000_r )
1272	1195	{
1273	1196	UINT16 retvalue = 0x0200;
1274		retvalue |= _32x_access_auth << 15;
	1197	retvalue |= m_32x_access_auth << 15;
1275	1198
1276		retvalue |=   sh2_hint_in_vbl;
1277		retvalue |= sh2_master_vint_enable;
1278		retvalue |= sh2_master_hint_enable;
1279		retvalue |= sh2_master_cmdint_enable;
	1199	retvalue |=   m_sh2_hint_in_vbl;
	1200	retvalue |= m_sh2_master_vint_enable;
	1201	retvalue |= m_sh2_master_hint_enable;
	1202	retvalue |= m_sh2_master_cmdint_enable;
1280	1203	retvalue |= sh2_master_pwmint_enable;
1281	1204
1282	1205	return retvalue;
r17465	r17466
1286	1209	{
1287	1210	if (ACCESSING_BITS_8_15)
1288	1211	{
1289		_32x_access_auth = (data &0x8000) >> 15;
	1212	m_32x_access_auth = (data &0x8000) >> 15;
1290	1213	}
1291	1214
1292	1215	if (ACCESSING_BITS_0_7)
1293	1216	{
1294		sh2_hint_in_vbl = data & 0x80;
1295		sh2_master_vint_enable = data & 0x8;
1296		sh2_master_hint_enable = data & 0x4;
1297		sh2_master_cmdint_enable = data & 0x2;
	1217	m_sh2_hint_in_vbl = data & 0x80;
	1218	m_sh2_master_vint_enable = data & 0x8;
	1219	m_sh2_master_hint_enable = data & 0x4;
	1220	m_sh2_master_cmdint_enable = data & 0x2;
1298	1221	sh2_master_pwmint_enable = data & 0x1;
1299	1222
1300		//if (sh2_master_hint_enable) printf("sh2_master_hint_enable enable!\n");
	1223	//if (m_sh2_master_hint_enable) printf("m_sh2_master_hint_enable enable!\n");
1301	1224	//if (sh2_master_pwmint_enable) printf("sh2_master_pwn_enable enable!\n");
1302	1225
1303	1226	_32x_check_irqs(space.machine());
r17465	r17466
1309	1232	READ16_MEMBER( sega_32x_device::_32x_sh2_slave_4000_r )
1310	1233	{
1311	1234	UINT16 retvalue = 0x0200;
1312		retvalue |= _32x_access_auth << 15;
1313		retvalue |=   sh2_hint_in_vbl;
1314		retvalue |= sh2_slave_vint_enable;
1315		retvalue |= sh2_slave_hint_enable;
1316		retvalue |= sh2_slave_cmdint_enable;
	1235	retvalue |= m_32x_access_auth << 15;
	1236	retvalue |=   m_sh2_hint_in_vbl;
	1237	retvalue |= m_sh2_slave_vint_enable;
	1238	retvalue |= m_sh2_slave_hint_enable;
	1239	retvalue |= m_sh2_slave_cmdint_enable;
1317	1240	retvalue |= sh2_slave_pwmint_enable;
1318	1241
1319	1242	return retvalue;
r17465	r17466
1324	1247	{
1325	1248	if (ACCESSING_BITS_8_15)
1326	1249	{
1327		_32x_access_auth = (data &0x8000) >> 15;
	1250	m_32x_access_auth = (data &0x8000) >> 15;
1328	1251	}
1329	1252
1330	1253	if (ACCESSING_BITS_0_7)
1331	1254	{
1332		sh2_hint_in_vbl = data & 0x80;
1333		sh2_slave_vint_enable = data & 0x8;
1334		sh2_slave_hint_enable = data & 0x4;
1335		sh2_slave_cmdint_enable = data & 0x2;
	1255	m_sh2_hint_in_vbl = data & 0x80;
	1256	m_sh2_slave_vint_enable = data & 0x8;
	1257	m_sh2_slave_hint_enable = data & 0x4;
	1258	m_sh2_slave_cmdint_enable = data & 0x2;
1336	1259	sh2_slave_pwmint_enable = data & 0x1;
1337	1260
1338		//if (sh2_slave_hint_enable) printf("sh2_slave_hint_enable enable!\n");
	1261	//if (m_sh2_slave_hint_enable) printf("m_sh2_slave_hint_enable enable!\n");
1339	1262	//if (sh2_slave_pwmint_enable) printf("sh2_slave_pwm_enable enable!\n");
1340	1263
1341	1264	_32x_check_irqs(space.machine());
r17465	r17466
1368	1291	/**********************************************************************************************/
1369	1292	READ16_MEMBER( sega_32x_device::_32x_sh2_common_4004_r )
1370	1293	{
1371		return _32x_hcount_reg;
	1294	return m_32x_hcount_reg;
1372	1295	}
1373	1296
1374	1297	WRITE16_MEMBER( sega_32x_device::_32x_sh2_common_4004_w )
1375	1298	{
1376		_32x_hcount_reg = data & 0xff;
	1299	m_32x_hcount_reg = data & 0xff;
1377	1300	}
1378	1301
1379	1302
r17465	r17466
1407	1330	// VINT (vertical interrupt) clear
1408	1331	/**********************************************************************************************/
1409	1332
1410		WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4016_w ){ sh2_master_vint_pending = 0; _32x_check_irqs(space.machine()); }
1411		WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4016_w ) { sh2_slave_vint_pending = 0; _32x_check_irqs(space.machine()); }
	1333	WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_4016_w ){ m_sh2_master_vint_pending = 0; _32x_check_irqs(space.machine()); }
	1334	WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_4016_w ) { m_sh2_slave_vint_pending = 0; _32x_check_irqs(space.machine()); }
1412	1335
1413	1336	/**********************************************************************************************/
1414	1337	// SH2 side 4018
r17465	r17466
1424	1347	// Note: flag cleared here is a guess, according to After Burner behaviour
1425	1348	/**********************************************************************************************/
1426	1349
1427		WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401a_w ){ _32x_68k_a15102_reg &= ~1; device_set_input_line(_32x_master_cpu,SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
1428		WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401a_w ) { _32x_68k_a15102_reg &= ~2; device_set_input_line(_32x_slave_cpu, SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
	1350	WRITE16_MEMBER( sega_32x_device::_32x_sh2_master_401a_w ){ m_32x_68k_a15102_reg &= ~1; device_set_input_line(_32x_master_cpu,SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
	1351	WRITE16_MEMBER( sega_32x_device::_32x_sh2_slave_401a_w ) { m_32x_68k_a15102_reg &= ~2; device_set_input_line(_32x_slave_cpu, SH2_CINT_IRQ_LEVEL,CLEAR_LINE);}
1429	1352
1430	1353	/**********************************************************************************************/
1431	1354	// SH2 side 401C
r17465	r17466
1592	1515	AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE(_32x_sh2_master_4018_master_401a_w ) // IRQ clear
1593	1516	AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE(_32x_sh2_master_401c_master_401e_w ) // IRQ clear
1594	1517
1595		AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16(_32x_68k_commsram_r, _32x_68k_commsram_w, 0xffffffff )
	1518	AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16(_32x_68k_m_commsram_r, _32x_68k_m_commsram_w, 0xffffffff )
1596	1519	AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16(_32x_pwm_r, _32x_pwm_w, 0xffffffff )
1597	1520
1598	1521	AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
r17465	r17466
1621	1544	AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE(_32x_sh2_slave_4018_slave_401a_w ) // IRQ clear
1622	1545	AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE(_32x_sh2_slave_401c_slave_401e_w ) // IRQ clear
1623	1546
1624		AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16(_32x_68k_commsram_r, _32x_68k_commsram_w, 0xffffffff )
	1547	AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16(_32x_68k_m_commsram_r, _32x_68k_m_commsram_w, 0xffffffff )
1625	1548	AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16(_32x_pwm_r, _32x_pwm_w, 0xffffffff )
1626	1549
1627	1550	AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
r17465	r17466
1643	1566
1644	1567
1645	1568
1646		void _32x_check_irqs(running_machine& machine)
	1569	void sega_32x_device::_32x_check_irqs(running_machine& machine)
1647	1570	{
1648	1571
1649		if (sh2_master_vint_enable && sh2_master_vint_pending) device_set_input_line(_32x_master_cpu,SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
	1572	if (m_sh2_master_vint_enable && m_sh2_master_vint_pending) device_set_input_line(_32x_master_cpu,SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
1650	1573	else device_set_input_line(_32x_master_cpu,SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
1651	1574
1652		if (sh2_slave_vint_enable && sh2_slave_vint_pending) device_set_input_line(_32x_slave_cpu,SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
	1575	if (m_sh2_slave_vint_enable && m_sh2_slave_vint_pending) device_set_input_line(_32x_slave_cpu,SH2_VINT_IRQ_LEVEL,ASSERT_LINE);
1653	1576	else device_set_input_line(_32x_slave_cpu,SH2_VINT_IRQ_LEVEL,CLEAR_LINE);
1654	1577	}
1655	1578
1656		void _32x_scanline_cb0(running_machine& machine)
	1579	void sega_32x_device::_32x_scanline_cb0(running_machine& machine)
1657	1580	{
1658		sh2_master_vint_pending = 1;
1659		sh2_slave_vint_pending = 1;
	1581	m_sh2_master_vint_pending = 1;
	1582	m_sh2_slave_vint_pending = 1;
1660	1583	_32x_check_irqs(machine);
1661	1584	}
1662	1585
1663	1586
1664		void _32x_scanline_cb1()
	1587	void sega_32x_device::_32x_scanline_cb1()
1665	1588	{
1666		_32x_hcount_compare_val++;
	1589	m_32x_hcount_compare_val++;
1667	1590
1668		if(_32x_hcount_compare_val >= _32x_hcount_reg)
	1591	if(m_32x_hcount_compare_val >= m_32x_hcount_reg)
1669	1592	{
1670		_32x_hcount_compare_val = -1;
	1593	m_32x_hcount_compare_val = -1;
1671	1594
1672		if(genesis_scanline_counter < 224 || sh2_hint_in_vbl)
	1595	if(genesis_scanline_counter < 224 || m_sh2_hint_in_vbl)
1673	1596	{
1674		if(sh2_master_hint_enable) { device_set_input_line(_32x_master_cpu,SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
1675		if(sh2_slave_hint_enable) { device_set_input_line(_32x_slave_cpu,SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
	1597	if(m_sh2_master_hint_enable) { device_set_input_line(_32x_master_cpu,SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
	1598	if(m_sh2_slave_hint_enable) { device_set_input_line(_32x_slave_cpu,SH2_HINT_IRQ_LEVEL,ASSERT_LINE); }
1676	1599	}
1677	1600	}
1678	1601	}
r17465	r17466
1696	1619	}
1697	1620
1698	1621
1699		static UINT32 _32x_linerender[320+258]; // tmp buffer (bigger than it needs to be to simplify RLE decode)
1700	1622
1701		UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline)
	1623	UINT32* sega_32x_device::_32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline)
1702	1624	{
1703	1625	int x;
1704	1626
1705	1627	/* render 32x output to a buffer */
1706		if (_32x_is_connected && (_32x_displaymode != 0))
	1628	if (m_32x_displaymode != 0)
1707	1629	{
1708		if (_32x_displaymode==1)
	1630	if (m_32x_displaymode==1)
1709	1631	{
1710	1632
1711	1633	UINT32 lineoffs;
1712	1634	int start;
1713	1635
1714		lineoffs = _32x_display_dram[scanline];
	1636	lineoffs = m_32x_display_dram[scanline];
1715	1637
1716		if (_32x_screenshift == 0) start=0;
	1638	if (m_32x_screenshift == 0) start=0;
1717	1639	else start = -1;
1718	1640
1719	1641	for (x=start;x<320;x++)
1720	1642	{
1721	1643	UINT16 coldata;
1722		coldata = _32x_display_dram[lineoffs];
	1644	coldata = m_32x_display_dram[lineoffs];
1723	1645
1724	1646	{
1725	1647	if (x>=0)
1726	1648	{
1727		_32x_linerender[x] = _32x_palette_lookup[(coldata & 0xff00)>>8];
	1649	m_32x_linerender[x] = m_32x_palette_lookup[(coldata & 0xff00)>>8];
1728	1650	}
1729	1651
1730	1652	x++;
1731	1653
1732	1654	if (x>=0)
1733	1655	{
1734		_32x_linerender[x] = _32x_palette_lookup[(coldata & 0x00ff)];
	1656	m_32x_linerender[x] = m_32x_palette_lookup[(coldata & 0x00ff)];
1735	1657	}
1736	1658	}
1737	1659
r17465	r17466
1739	1661
1740	1662	}
1741	1663	}
1742		else if (_32x_displaymode==3) // mode 3 = RLE  (used by BRUTAL intro)
	1664	else if (m_32x_displaymode==3) // mode 3 = RLE  (used by BRUTAL intro)
1743	1665	{
1744	1666	UINT32 lineoffs;
1745	1667	int start;
1746	1668
1747		lineoffs = _32x_display_dram[scanline];
	1669	lineoffs = m_32x_display_dram[scanline];
1748	1670
1749		if (_32x_screenshift == 0) start=0;
	1671	if (m_32x_screenshift == 0) start=0;
1750	1672	else start = -1;
1751	1673
1752	1674	x = start;
1753	1675	while (x<320)
1754	1676	{
1755	1677	UINT16 coldata, length, l;
1756		coldata = _32x_display_dram[lineoffs];
	1678	coldata = m_32x_display_dram[lineoffs];
1757	1679	length = ((coldata & 0xff00)>>8)+1;
1758	1680	coldata = (coldata & 0x00ff)>>0;
1759	1681	for (l=0;l<length;l++)
1760	1682	{
1761	1683	if (x>=0)
1762	1684	{
1763		_32x_linerender[x] = _32x_palette_lookup[(coldata)];
	1685	m_32x_linerender[x] = m_32x_palette_lookup[(coldata)];
1764	1686	}
1765	1687	x++;
1766	1688	}
r17465	r17466
1774	1696	UINT32 lineoffs;
1775	1697	int start;
1776	1698
1777		lineoffs = _32x_display_dram[scanline];
	1699	lineoffs = m_32x_display_dram[scanline];
1778	1700
1779		if (_32x_screenshift == 0) start=0;
	1701	if (m_32x_screenshift == 0) start=0;
1780	1702	else start = -1;
1781	1703
1782	1704	x = start;
1783	1705	while (x<320)
1784	1706	{
1785	1707	UINT16 coldata;
1786		coldata = _32x_display_dram[lineoffs&0xffff];
	1708	coldata = m_32x_display_dram[lineoffs&0xffff];
1787	1709
1788	1710	// need to swap red and blue around for MAME
1789	1711	{
r17465	r17466
1797	1719	}
1798	1720
1799	1721	if (x>=0)
1800		_32x_linerender[x] = coldata;
	1722	m_32x_linerender[x] = coldata;
1801	1723
1802	1724	x++;
1803	1725	lineoffs++;
r17465	r17466
1805	1727	}
1806	1728	}
1807	1729
1808		return _32x_linerender;
	1730	return m_32x_linerender;
1809	1731	}
1810	1732
1811	1733	static const sh2_cpu_core sh2_conf_master = { 0, NULL, _32x_fifo_available_callback };
r17465	r17466
1911	1833	m_32x_pwm_timer = machine().scheduler().timer_alloc(FUNC(_32x_pwm_callback), (void*)this);
1912	1834	m_32x_pwm_timer->adjust(attotime::never);
1913	1835
1914		_32x_dram0 = auto_alloc_array(machine(), UINT16, 0x40000/2);
1915		_32x_dram1 = auto_alloc_array(machine(), UINT16, 0x40000/2);
	1836	m_32x_dram0 = auto_alloc_array(machine(), UINT16, 0x40000/2);
	1837	m_32x_dram1 = auto_alloc_array(machine(), UINT16, 0x40000/2);
1916	1838
1917		memset(_32x_dram0, 0x00, 0x40000);
1918		memset(_32x_dram1, 0x00, 0x40000);
	1839	memset(m_32x_dram0, 0x00, 0x40000);
	1840	memset(m_32x_dram1, 0x00, 0x40000);
1919	1841
1920		_32x_palette_lookup = auto_alloc_array(machine(), UINT16, 0x200/2);
1921		_32x_palette = auto_alloc_array(machine(), UINT16, 0x200/2);
	1842	m_32x_palette_lookup = auto_alloc_array(machine(), UINT16, 0x200/2);
	1843	m_32x_palette = auto_alloc_array(machine(), UINT16, 0x200/2);
1922	1844
1923		memset(_32x_palette_lookup, 0x00, 0x200);
1924		memset(_32x_palette, 0x00, 0x200);
	1845	memset(m_32x_palette_lookup, 0x00, 0x200);
	1846	memset(m_32x_palette, 0x00, 0x200);
1925	1847
1926		_32x_display_dram = _32x_dram0;
1927		_32x_access_dram = _32x_dram1;
	1848	m_32x_display_dram = m_32x_dram0;
	1849	m_32x_access_dram = m_32x_dram1;
1928	1850	}
1929	1851
1930	1852	void sega_32x_device::device_reset()
1931	1853	{
1932	1854	/* Interrupts are masked / disabled at first */
1933		sh2_master_vint_enable = sh2_slave_vint_enable = 0;
1934		sh2_master_hint_enable = sh2_slave_hint_enable = 0;
1935		sh2_master_cmdint_enable = sh2_slave_cmdint_enable = 0;
	1855	m_sh2_master_vint_enable = m_sh2_slave_vint_enable = 0;
	1856	m_sh2_master_hint_enable = m_sh2_slave_hint_enable = 0;
	1857	m_sh2_master_cmdint_enable = m_sh2_slave_cmdint_enable = 0;
1936	1858	sh2_master_pwmint_enable = sh2_slave_pwmint_enable = 0;
1937		sh2_master_vint_pending = sh2_slave_vint_pending = 0;
	1859	m_sh2_master_vint_pending = m_sh2_slave_vint_pending = 0;
1938	1860
1939	1861	// start in a reset state
1940		sh2_are_running = 0;
	1862	m_sh2_are_running = 0;
1941	1863
1942		_32x_a1518a_reg = 0x00; // inital value
1943		_32x_68k_a15104_reg = 0x00;
	1864	m_32x_a1518a_reg = 0x00; // inital value
	1865	m_32x_68k_a15104_reg = 0x00;
1944	1866
1945		_32x_autofill_length = 0;
1946		_32x_autofill_address = 0;
1947		_32x_autofill_data = 0;
1948		_32x_screenshift = 0;
1949		_32x_videopriority = 0; // MD priority
1950		_32x_displaymode = 0;
1951		_32x_240mode = 0;
	1867	m_32x_autofill_length = 0;
	1868	m_32x_autofill_address = 0;
	1869	m_32x_autofill_data = 0;
	1870	m_32x_screenshift = 0;
	1871	m_32x_videopriority = 0; // MD priority
	1872	m_32x_displaymode = 0;
	1873	m_32x_240mode = 0;
1952	1874
1953	1875
1954	1876	current_fifo_block = fifo_block_a;
r17465	r17466
1958	1880	fifo_block_a_full = 0;
1959	1881	fifo_block_b_full = 0;
1960	1882
1961		_32x_hcount_compare_val = -1;
	1883	m_32x_hcount_compare_val = -1;
1962	1884
1963	1885
1964	1886	// moved from init
1965	1887
1966		_32x_adapter_enabled = 0;
	1888	m_32x_adapter_enabled = 0;
1967	1889
1968		if (_32x_adapter_enabled == 0)
	1890	if (m_32x_adapter_enabled == 0)
1969	1891	{
1970	1892	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_rom(0x0000000, 0x03fffff, machine().root_device().memregion(":gamecart")->base());
1971		machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_hint_vector_w),this)); // h interrupt vector
	1893	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0x000070, 0x000073, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_hint_vector_w),this)); // h interrupt vector
1972	1894	};
1973	1895
1974	1896
1975		a15100_reg = 0x0000;
	1897	m_a15100_reg = 0x0000;
1976	1898	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15100, 0xa15101, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15100_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15100_w),this)); // framebuffer control regs
1977	1899	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15102, 0xa15103, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15102_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15102_w),this)); // send irq to sh2
1978	1900	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15104, 0xa15105, read16_delegate(FUNC(sega_32x_device::_32x_68k_a15104_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a15104_w),this)); // 68k BANK rom set
r17465	r17466
1981	1903
1982	1904	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa1511a, 0xa1511b, read16_delegate(FUNC(sega_32x_device::_32x_68k_a1511a_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_a1511a_w),this)); // SEGA TV
1983	1905
1984		machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15120, 0xa1512f, read16_delegate(FUNC(sega_32x_device::_32x_68k_commsram_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_commsram_w),this)); // comms reg 0-7
	1906	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15120, 0xa1512f, read16_delegate(FUNC(sega_32x_device::_32x_68k_m_commsram_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_m_commsram_w),this)); // comms reg 0-7
1985	1907	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler(0xa15130, 0xa1513f, read16_delegate(FUNC(sega_32x_device::_32x_pwm_r),this), write16_delegate(FUNC(sega_32x_device::_32x_68k_pwm_w),this));
1986	1908
1987	1909	machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_read_handler(0x0a130ec, 0x0a130ef, read16_delegate(FUNC(sega_32x_device::_32x_68k_MARS_r),this)); // system ID

trunk/src/mame/machine/mega32x.h

r17465	r17466
5	5	// when using the DRC core.  Needs further investigation, the non-DRC core works either
6	6	// way
7	7	#define _32X_SWAP_MASTER_SLAVE_HACK
	8	#define _32X_COMMS_PORT_SYNC 0
	9	#define MAX_HPOSITION 480
	10	/* need to make some pwm stuff part of device */
	11	#define PWM_FIFO_SIZE m_pwm_tm_reg // guess, Marsch calls this register as FIFO width
	12	#define PWM_CLOCK megadrive_region_pal ? ((MASTER_CLOCK_PAL*3) / 7) : ((MASTER_CLOCK_NTSC*3) / 7)
8	13
9	14
	15
	16	#define SH2_VRES_IRQ_LEVEL 14
	17	#define SH2_VINT_IRQ_LEVEL 12
	18	#define SH2_HINT_IRQ_LEVEL 10
	19	#define SH2_CINT_IRQ_LEVEL 8
	20	#define SH2_PINT_IRQ_LEVEL 6
	21
	22
10	23	#include "sound/dac.h"
11	24
12	25	#define _32X_MASTER_TAG (":sega32x:32x_master_sh2")
r17465	r17466
47	60	DECLARE_WRITE16_MEMBER( _32x_dreq_common_w );
48	61	DECLARE_READ16_MEMBER( _32x_68k_a1511a_r );
49	62	DECLARE_WRITE16_MEMBER( _32x_68k_a1511a_w );
50		DECLARE_READ16_MEMBER( _32x_68k_hint_vector_r );
51		DECLARE_WRITE16_MEMBER( _32x_68k_hint_vector_w );
	63	DECLARE_READ16_MEMBER( _32x_68k_m_hint_vector_r );
	64	DECLARE_WRITE16_MEMBER( _32x_68k_m_hint_vector_w );
52	65	DECLARE_READ16_MEMBER( _32x_68k_MARS_r );
53	66	DECLARE_READ16_MEMBER( _32x_68k_a15100_r );
54	67	DECLARE_WRITE16_MEMBER( _32x_68k_a15100_w );
r17465	r17466
56	69	DECLARE_WRITE16_MEMBER( _32x_68k_a15102_w );
57	70	DECLARE_READ16_MEMBER( _32x_68k_a15104_r );
58	71	DECLARE_WRITE16_MEMBER( _32x_68k_a15104_w );
59		DECLARE_READ16_MEMBER( _32x_68k_commsram_r );
60		DECLARE_WRITE16_MEMBER( _32x_68k_commsram_w );
	72	DECLARE_READ16_MEMBER( _32x_68k_m_commsram_r );
	73	DECLARE_WRITE16_MEMBER( _32x_68k_m_commsram_w );
61	74	DECLARE_READ16_MEMBER( _32x_pwm_r );
62	75	DECLARE_WRITE16_MEMBER( _32x_pwm_w );
63	76	DECLARE_WRITE16_MEMBER( _32x_68k_pwm_w );
r17465	r17466
86	99	DECLARE_WRITE16_MEMBER( _32x_sh2_master_401e_w );
87	100	DECLARE_WRITE16_MEMBER( _32x_sh2_slave_401e_w );
88	101
	102	UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline);
	103	int sh2_master_pwmint_enable, sh2_slave_pwmint_enable;
	104
	105	void _32x_check_framebuffer_swap(void);
	106	void _32x_check_irqs(running_machine& machine);
	107	void _32x_scanline_cb0(running_machine& machine);
	108	void _32x_scanline_cb1();
	109
	110	/* our current main rendering code needs to know this for mixing in */
	111	int m_32x_displaymode;
	112	int m_32x_videopriority;
	113	/* our main vblank handler resets this */
	114	int m_32x_hcount_compare_val;
	115	int m_sh2_are_running;
	116	int m_32x_240mode;
	117	UINT16 m_32x_a1518a_reg;
	118
	119
	120	UINT32 m_32x_linerender[320+258]; // tmp buffer (bigger than it needs to be to simplify RLE decode)
	121
	122
	123	void handle_pwm_callback(void);
	124	void calculate_pwm_timer(running_machine &machine);
	125	UINT16 m_pwm_ctrl,m_pwm_cycle,m_pwm_tm_reg;
	126	UINT16 m_cur_lch[0x10],m_cur_rch[0x10];
	127	UINT16 m_pwm_cycle_reg; //used for latching
	128	UINT8 m_pwm_timer_tick;
	129	UINT8 m_lch_index_r,m_rch_index_r,m_lch_index_w,m_rch_index_w;
	130	UINT16 m_lch_fifo_state,m_rch_fifo_state;
	131
	132
	133	UINT16 get_hposition(void);
	134
89	135	emu_timer *m_32x_pwm_timer;
90	136	protected:
91	137	virtual void device_start();
r17465	r17466
96	142	virtual machine_config_constructor device_mconfig_additions() const;
97	143	private:
98	144	//   virtual void device_config_complete();
	145	int m_32x_adapter_enabled;
	146	int m_32x_access_auth;
	147	int m_32x_screenshift;
	148
	149	UINT16 m_32x_68k_a15104_reg;
	150	int m_sh2_master_vint_enable, m_sh2_slave_vint_enable;
	151	int m_sh2_master_hint_enable, m_sh2_slave_hint_enable;
	152	int m_sh2_master_cmdint_enable, m_sh2_slave_cmdint_enable;
	153	int m_sh2_hint_in_vbl;
	154	int m_sh2_master_vint_pending;
	155	int m_sh2_slave_vint_pending;
	156	int m_32x_fb_swap;
	157	int m_32x_hcount_reg;
	158
	159	UINT16 m_32x_autofill_length;
	160	UINT16 m_32x_autofill_address;
	161	UINT16 m_32x_autofill_data;
	162	UINT16 m_a15106_reg;
	163	UINT16 m_dreq_src_addr[2],m_dreq_dst_addr[2],m_dreq_size;
	164	UINT8 m_sega_tv;
	165	UINT16 m_hint_vector[2];
	166	UINT16 m_a15100_reg;
	167	int m_32x_68k_a15102_reg;
	168
	169	UINT16 m_commsram[8];
	170
	171	UINT16* m_32x_dram0;
	172	UINT16* m_32x_dram1;
	173	UINT16 *m_32x_display_dram, *m_32x_access_dram;
	174	UINT16* m_32x_palette;
	175	UINT16* m_32x_palette_lookup;
99	176	};
100	177
101	178

trunk/src/mame/machine/megadriv.c

r17465	r17466
1386	1386	printf("32x SLAVE SH2 cpu found '%s'\n", _32x_slave_cpu->tag() );
1387	1387	}
1388	1388
1389		if ((_32x_master_cpu != NULL) && (_32x_slave_cpu != NULL))
1390		{
1391		_32x_is_connected = 1;
1392		}
1393		else
1394		{
1395		_32x_is_connected = 0;
1396		}
1397	1389
1398	1390
1399
1400	1391	sega_cd_connected = 0;
1401	1392	segacd_wordram_mapped = 0;
1402	1393	_segacd_68k_cpu = machine.device<cpu_device>("segacd_68k");

trunk/src/mame/machine/megavdp.c

r17465	r17466
2	2
3	3	#include "emu.h"
4	4	#include "megavdp.h"
	5	#include "mega32x.h"
5	6
6	7	/* still have dependencies on the following external gunk */
7	8
r17465	r17466
11	12	extern int segacd_wordram_mapped;
12	13	extern timer_device* megadriv_scanline_timer;
13	14
14		extern UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine, int scanline);
15		extern void _32x_scanline_cb0(running_machine& machine);
16		extern void _32x_scanline_cb1(void);
17		extern void _32x_check_framebuffer_swap(void);
18		extern int _32x_hcount_compare_val;
19		extern int _32x_displaymode;
20		extern int _32x_videopriority;
21		extern int _32x_is_connected;
22	15
23	16
	17
24	18	#define MAX_HPOSITION 480
25	19
26	20
r17465	r17466
2552	2546	/* This converts our render buffer to real screen colours */
2553	2547	void sega_genesis_vdp_device::genesis_render_videobuffer_to_screenbuffer(running_machine &machine, int scanline)
2554	2548	{
	2549	sega_32x_device *_32xdev = machine.device<sega_32x_device>("sega32x"); // take this out of the VDP eventually
	2550
	2551
2555	2552	UINT16*lineptr;
2556	2553	int x;
2557	2554
r17465	r17466
2564	2561	lineptr = m_render_line;
2565	2562	}
2566	2563
2567		UINT32* _32x_linerender = _32x_render_videobuffer_to_screenbuffer_helper(machine, scanline);
2568	2564
	2565	if (_32xdev) _32xdev->_32x_render_videobuffer_to_screenbuffer_helper(machine, scanline);
2569	2566
2570	2567
	2568
2571	2569	if (!MEGADRIVE_REG0C_SHADOW_HIGLIGHT)
2572	2570	{
2573	2571
r17465	r17466
2578	2576	int drawn = 0;
2579	2577
2580	2578	// low priority 32x - if it's the bg pen, we have a 32x, and it's display is enabled...
2581		if ((dat&0x20000) && (_32x_is_connected) && (_32x_displaymode != 0))
	2579	if (_32xdev)
2582	2580	{
2583		if (!_32x_videopriority)
	2581	if ((dat&0x20000) && (_32xdev->m_32x_displaymode != 0))
2584	2582	{
2585		if (!(_32x_linerender[x]&0x8000))
	2583	if (!_32xdev->m_32x_videopriority)
2586	2584	{
2587		lineptr[x] = _32x_linerender[x]&0x7fff;
2588		drawn = 1;
	2585	if (!(_32xdev->m_32x_linerender[x]&0x8000))
	2586	{
	2587	lineptr[x] = _32xdev->m_32x_linerender[x]&0x7fff;
	2588	drawn = 1;
	2589	}
2589	2590	}
2590		}
2591		else
2592		{
2593		if ((_32x_linerender[x]&0x8000))
	2591	else
2594	2592	{
2595		lineptr[x] = _32x_linerender[x]&0x7fff;
2596		drawn = 1;
	2593	if ((_32xdev->m_32x_linerender[x]&0x8000))
	2594	{
	2595	lineptr[x] = _32xdev->m_32x_linerender[x]&0x7fff;
	2596	drawn = 1;
	2597	}
2597	2598	}
2598	2599	}
2599	2600	}
r17465	r17466
2633	2634	int drawn = 0;
2634	2635
2635	2636	// low priority 32x - if it's the bg pen, we have a 32x, and it's display is enabled...
2636		if ((dat&0x20000) && (_32x_is_connected) && (_32x_displaymode != 0))
	2637	if (_32xdev)
2637	2638	{
2638		if (!_32x_videopriority)
	2639	if ((dat&0x20000) && (_32xdev->m_32x_displaymode != 0))
2639	2640	{
2640		if (!(_32x_linerender[x]&0x8000))
	2641	if (!_32xdev->m_32x_videopriority)
2641	2642	{
2642		lineptr[x] = _32x_linerender[x]&0x7fff;
2643		drawn = 1;
	2643	if (!(_32xdev->m_32x_linerender[x]&0x8000))
	2644	{
	2645	lineptr[x] = _32xdev->m_32x_linerender[x]&0x7fff;
	2646	drawn = 1;
	2647	}
2644	2648	}
2645		}
2646		else
2647		{
2648		if ((_32x_linerender[x]&0x8000))
	2649	else
2649	2650	{
2650		lineptr[x] = _32x_linerender[x]&0x7fff;
2651		drawn = 1;
	2651	if ((_32xdev->m_32x_linerender[x]&0x8000))
	2652	{
	2653	lineptr[x] = _32xdev->m_32x_linerender[x]&0x7fff;
	2654	drawn = 1;
	2655	}
2652	2656	}
2653	2657	}
2654	2658	}
2655
	2659
2656	2660	if (!(dat&0x20000))
2657	2661	m_render_line_raw[x] = 0x100;
2658	2662	else
r17465	r17466
2712	2716
2713	2717
2714	2718	// high priority 32x
2715		if ((_32x_is_connected) && (_32x_displaymode != 0))
	2719	if (_32xdev)
2716	2720	{
2717		for (x=0;x<320;x++)
	2721	if (_32xdev->m_32x_displaymode != 0)
2718	2722	{
2719		if (!_32x_videopriority)
	2723	for (x=0;x<320;x++)
2720	2724	{
2721		if ((_32x_linerender[x]&0x8000))
2722		lineptr[x] = _32x_linerender[x]&0x7fff;
	2725	if (!_32xdev->m_32x_videopriority)
	2726	{
	2727	if ((_32xdev->m_32x_linerender[x]&0x8000))
	2728	lineptr[x] = _32xdev->m_32x_linerender[x]&0x7fff;
	2729	}
	2730	else
	2731	{
	2732	if (!(_32xdev->m_32x_linerender[x]&0x8000))
	2733	lineptr[x] = _32xdev->m_32x_linerender[x]&0x7fff;
	2734	}
2723	2735	}
2724		else
2725		{
2726		if (!(_32x_linerender[x]&0x8000))
2727		lineptr[x] = _32x_linerender[x]&0x7fff;
2728		}
2729	2736	}
2730	2737	}
2731	2738	}
r17465	r17466
2756	2763	to rounding errors in the timer calculation we're not quite there.  Let's assume we are
2757	2764	still in the previous scanline for now.
2758	2765	*/
	2766	sega_32x_device *_32xdev = machine.device<sega_32x_device>("sega32x"); // take this out of the VDP eventually
2759	2767
	2768
2760	2769	if (genesis_get_scanline_counter(machine)!=(megadrive_total_scanlines-1))
2761	2770	{
2762	2771	if (!m_use_alt_timing) genesis_scanline_counter++;
r17465	r17466
2771	2780	megadrive_vblank_flag = 1;
2772	2781
2773	2782	// 32x interrupt!
2774		if (_32x_is_connected)
2775		{
2776		_32x_scanline_cb0(machine);
2777		}
	2783	if (_32xdev) _32xdev->_32x_scanline_cb0(machine);
2778	2784
2779	2785	}
2780	2786
2781	2787
2782	2788
2783		_32x_check_framebuffer_swap();
	2789	if (_32xdev) _32xdev->_32x_check_framebuffer_swap();
2784	2790
2785	2791
2786	2792	//  if (genesis_get_scanline_counter(machine)==0) m_irq4counter = MEGADRIVE_REG0A_HINT_VALUE;
r17465	r17466
2812	2818
2813	2819	//if (genesis_get_scanline_counter(machine)==0) irq4_on_timer->adjust(attotime::from_usec(2));
2814	2820
2815		if(_32x_is_connected)
2816		{
2817		_32x_scanline_cb1();
2818		}
	2821
	2822	if (_32xdev) _32xdev->_32x_scanline_cb1();
2819	2823
	2824
2820	2825	if (genesis_get_scanline_counter(machine) == megadrive_z80irq_scanline)
2821	2826	{
2822	2827	m_genesis_vdp_sndirqline_callback(machine, true);
r17465	r17466
2838	2843
2839	2844	void sega_genesis_vdp_device::vdp_handle_eof(running_machine &machine)
2840	2845	{
	2846	sega_32x_device *_32xdev = machine.device<sega_32x_device>("sega32x"); // take this out of the VDP eventually
	2847
2841	2848	rectangle visarea;
2842	2849	int scr_width = 320;
2843	2850
r17465	r17466
2913	2920	machine.primary_screen->configure(480, megadrive_total_scanlines, visarea, machine.primary_screen->frame_period().attoseconds);
2914	2921
2915	2922
2916		if(_32x_is_connected)
2917		_32x_hcount_compare_val = -1;
	2923	if(_32xdev) _32xdev->m_32x_hcount_compare_val = -1;
2918	2924	}
2919	2925
2920	2926

trunk/src/mame/machine/megavdp.h

r17465	r17466
2	2
3	3	#pragma once
4	4
	5
	6
5	7	/*  The VDP occupies addresses C00000h to C0001Fh.
6	8
7	9	C00000h    -   Data port (8=r/w, 16=r/w)

trunk/src/mame/includes/megadriv.h

r17465	r17466
420	420
421	421
422	422
423		extern int _32x_is_connected;
424	423	extern cpu_device *_32x_master_cpu;
425	424	extern cpu_device *_32x_slave_cpu;
426	425
r17465	r17466
428	427
429	428
430	429
431		extern int megadrive_vblank_flag;
432		extern int genesis_scanline_counter;
433	430
	431
434	432	class segacd_state : public _32x_state   // use _32x_state as base to make easier the combo 32X + SCD
435	433	{
436	434	public:
r17465	r17466
468	466	extern int megadrive_vblank_flag;
469	467	extern int genesis_scanline_counter;
470	468	extern UINT16* megadrive_vdp_palette_lookup;
471		extern UINT16* megadrive_vdp_palette_lookup_sprite; // for C2
472		extern UINT16* megadrive_vdp_palette_lookup_shadow;
473		extern UINT16* megadrive_vdp_palette_lookup_highlight;
474		extern int segac2_bg_pal_lookup[4];
475		extern int segac2_sp_pal_lookup[4];
476		extern int genvdp_use_cram;
	469
477	470	extern int megadrive_region_export;
478	471	extern int megadrive_region_pal;
479		TIMER_DEVICE_CALLBACK( megadriv_scanline_timer_callback );
480	472
481	473	/* machine/megadriv.c */
482	474	extern TIMER_DEVICE_CALLBACK( megadriv_scanline_timer_callback );

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