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r17440 Friday 24th August, 2012 at 10:45:35 UTC by smf
am53cf96 is now a device (nw)

[src/emu/machine]	am53cf96.c am53cf96.h
[src/mame/drivers]	konamigq.c konamigv.c twinkle.c

trunk/src/mame/drivers/konamigq.c

r17439	r17440
177	177
178	178	static ADDRESS_MAP_START( konamigq_map, AS_PROGRAM, 32, konamigq_state )
179	179	AM_RANGE(0x00000000, 0x003fffff) AM_RAM   AM_SHARE("share1") /* ram */
180		AM_RANGE(0x1f000000, 0x1f00001f) AM_READWRITE_LEGACY(am53cf96_r, am53cf96_w)
	180	AM_RANGE(0x1f000000, 0x1f00001f) AM_DEVREADWRITE8("am53cf96", am53cf96_device, read, write, 0x00ff00ff)
181	181	AM_RANGE(0x1f100000, 0x1f10000f) AM_WRITE(soundr3k_w)
182	182	AM_RANGE(0x1f100010, 0x1f10001f) AM_READ(soundr3k_r)
183	183	AM_RANGE(0x1f180000, 0x1f180003) AM_WRITE(eeprom_w)
r17439	r17440
260	260
261	261	static void scsi_dma_read( konamigq_state *state, UINT32 n_address, INT32 n_size )
262	262	{
	263	am53cf96_device *am53cf96 = state->machine().device<am53cf96_device>("am53cf96");
	264
263	265	UINT32 *p_n_psxram = state->m_p_n_psxram;
264	266	UINT8 *sector_buffer = state->m_sector_buffer;
265	267	int i;
r17439	r17440
275	277	{
276	278	n_this = n_size;
277	279	}
278		am53cf96_read_data( n_this * 4, sector_buffer );
	280	am53cf96->dma_read_data( n_this * 4, sector_buffer );
279	281	n_size -= n_this;
280	282
281	283	i = 0;
r17439	r17440
328	330	{
329	331	konamigq_state *state = machine.driver_data<konamigq_state>();
330	332
331		/* init the scsi controller and hook up it's DMA */
332		am53cf96_init(machine, &scsi_intf);
333
334	333	state->save_pointer(NAME(state->m_p_n_pcmram), 0x380000);
335	334	state->save_item(NAME(state->m_sndto000));
336	335	state->save_item(NAME(state->m_sndtor3k));
r17439	r17440
358	357	MCFG_EEPROM_93C46_ADD("eeprom")
359	358	MCFG_EEPROM_DATA(konamigq_def_eeprom, 128)
360	359
	360	MCFG_AM53CF96_ADD("am53cf96", scsi_intf);
	361
361	362	MCFG_SCSIDEV_ADD("disk", SCSIHD, SCSI_ID_0)
362	363
363	364	/* video hardware */

trunk/src/mame/drivers/twinkle.c

r17439	r17440
627	627	static ADDRESS_MAP_START( main_map, AS_PROGRAM, 32, twinkle_state )
628	628	AM_RANGE(0x00000000, 0x003fffff) AM_RAM   AM_SHARE("share1") /* ram */
629	629	AM_RANGE(0x1f000000, 0x1f0007ff) AM_READWRITE(shared_psx_r, shared_psx_w)
630		AM_RANGE(0x1f200000, 0x1f20001f) AM_READWRITE_LEGACY(am53cf96_r, am53cf96_w)
	630	AM_RANGE(0x1f200000, 0x1f20001f) AM_DEVREADWRITE8("am53cf96", am53cf96_device, read, write, 0x00ff00ff)
631	631	AM_RANGE(0x1f20a01c, 0x1f20a01f) AM_WRITENOP /* scsi? */
632	632	AM_RANGE(0x1f210400, 0x1f2107ff) AM_READNOP
633	633	AM_RANGE(0x1f218000, 0x1f218003) AM_WRITE(watchdog_reset32_w) /* LTC1232 */
r17439	r17440
768	768	static void scsi_dma_read( twinkle_state *state, UINT32 n_address, INT32 n_size )
769	769	{
770	770	UINT32 *p_n_psxram = state->m_p_n_psxram;
	771	am53cf96_device *am53cf96 = state->machine().device<am53cf96_device>("am53cf96");
	772
771	773	int i;
772	774	int n_this;
773	775
r17439	r17440
784	786	if( n_this < 2048 / 4 )
785	787	{
786	788	/* non-READ commands */
787		am53cf96_read_data( n_this * 4, state->m_sector_buffer );
	789	am53cf96->dma_read_data( n_this * 4, state->m_sector_buffer );
788	790	}
789	791	else
790	792	{
791	793	/* assume normal 2048 byte data for now */
792		am53cf96_read_data( 2048, state->m_sector_buffer );
	794	am53cf96->dma_read_data( 2048, state->m_sector_buffer );
793	795	n_this = 2048 / 4;
794	796	}
795	797	n_size -= n_this;
r17439	r17440
812	814	static void scsi_dma_write( twinkle_state *state, UINT32 n_address, INT32 n_size )
813	815	{
814	816	UINT32 *p_n_psxram = state->m_p_n_psxram;
	817	am53cf96_device *am53cf96 = state->machine().device<am53cf96_device>("am53cf96");
	818
815	819	int i;
816	820	int n_this;
817	821
r17439	r17440
839	843	n_this--;
840	844	}
841	845
842		am53cf96_write_data( n_this * 4, state->m_sector_buffer );
	846	am53cf96->dma_write_data( n_this * 4, state->m_sector_buffer );
843	847	}
844	848	}
845	849
r17439	r17440
865	869	DRIVER_INIT_MEMBER(twinkle_state,twinkle)
866	870	{
867	871	psx_driver_init(machine());
868		am53cf96_init(machine(), &scsi_intf);
869	872
870	873	device_t *i2cmem = machine().device("security");
871	874	i2cmem_e0_write( i2cmem, 0 );
r17439	r17440
917	920	MCFG_MACHINE_RESET( twinkle )
918	921	MCFG_I2CMEM_ADD("security",i2cmem_interface)
919	922
	923	MCFG_AM53CF96_ADD("am53cf96", scsi_intf);
	924
920	925	MCFG_SCSIDEV_ADD("cdrom0", SCSICD, SCSI_ID_4)
921	926
922	927	MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt, ide_devices, "hdd", NULL, true)

trunk/src/mame/drivers/konamigv.c

r17439	r17440
190	190
191	191	static ADDRESS_MAP_START( konamigv_map, AS_PROGRAM, 32, konamigv_state )
192	192	AM_RANGE(0x00000000, 0x001fffff) AM_RAM   AM_SHARE("share1") /* ram */
193		AM_RANGE(0x1f000000, 0x1f00001f) AM_READWRITE_LEGACY(am53cf96_r, am53cf96_w)
	193	AM_RANGE(0x1f000000, 0x1f00001f) AM_DEVREADWRITE8("am53cf96", am53cf96_device, read, write, 0x00ff00ff)
194	194	AM_RANGE(0x1f100000, 0x1f100003) AM_READ_PORT("P1")
195	195	AM_RANGE(0x1f100004, 0x1f100007) AM_READ_PORT("P2")
196	196	AM_RANGE(0x1f100008, 0x1f10000b) AM_READ_PORT("P3_P4")
r17439	r17440
209	209
210	210	static void scsi_dma_read( konamigv_state *state, UINT32 n_address, INT32 n_size )
211	211	{
	212	am53cf96_device *am53cf96 = state->machine().device<am53cf96_device>("am53cf96");
	213
212	214	UINT32 *p_n_psxram = state->m_p_n_psxram;
213	215	UINT8 *sector_buffer = state->m_sector_buffer;
214	216	int i;
r17439	r17440
227	229	if( n_this < 2048 / 4 )
228	230	{
229	231	/* non-READ commands */
230		am53cf96_read_data( n_this * 4, sector_buffer );
	232	am53cf96->dma_read_data( n_this * 4, sector_buffer );
231	233	}
232	234	else
233	235	{
234	236	/* assume normal 2048 byte data for now */
235		am53cf96_read_data( 2048, sector_buffer );
	237	am53cf96->dma_read_data( 2048, sector_buffer );
236	238	n_this = 2048 / 4;
237	239	}
238	240	n_size -= n_this;
r17439	r17440
254	256
255	257	static void scsi_dma_write( konamigv_state *state, UINT32 n_address, INT32 n_size )
256	258	{
	259	am53cf96_device *am53cf96 = state->machine().device<am53cf96_device>("am53cf96");
	260
257	261	UINT32 *p_n_psxram = state->m_p_n_psxram;
258	262	UINT8 *sector_buffer = state->m_sector_buffer;
259	263	int i;
r17439	r17440
283	287	n_this--;
284	288	}
285	289
286		am53cf96_write_data( n_this * 4, sector_buffer );
	290	am53cf96->dma_write_data( n_this * 4, sector_buffer );
287	291	}
288	292	}
289	293
r17439	r17440
309	313	DRIVER_INIT_MEMBER(konamigv_state,konamigv)
310	314	{
311	315	psx_driver_init(machine());
312
313		/* init the scsi controller and hook up it's DMA */
314		am53cf96_init(machine(), &scsi_intf);
315	316	}
316	317
317	318	static MACHINE_START( konamigv )
r17439	r17440
356	357
357	358	MCFG_EEPROM_93C46_ADD("eeprom")
358	359
	360	MCFG_AM53CF96_ADD("am53cf96", scsi_intf);
	361
359	362	MCFG_SCSIDEV_ADD("cdrom", SCSICD, SCSI_ID_4)
360	363
361	364	/* video hardware */

trunk/src/emu/machine/am53cf96.c

r17439	r17440
13	13	#include "am53cf96.h"
14	14	#include "machine/scsidev.h"
15	15
16		static UINT8 scsi_regs[32], fifo[16], fptr = 0, xfer_state, last_id;
17		static const struct AM53CF96interface *intf;
18
19		static scsidev_device *devices[8];   // SCSI IDs 0-7
20
21		// 53CF96 register set
22		enum
	16	READ8_MEMBER( am53cf96_device::read )
23	17	{
24		REG_XFERCNTLOW = 0,   // read = current xfer count lo byte, write = set xfer count lo byte
25		REG_XFERCNTMID,      // read = current xfer count mid byte, write = set xfer count mid byte
26		REG_FIFO,      // read/write = FIFO
27		REG_COMMAND,      // read/write = command
28
29		REG_STATUS,      // read = status, write = destination SCSI ID (4)
30		REG_IRQSTATE,      // read = IRQ status, write = timeout         (5)
31		REG_INTSTATE,      // read = internal state, write = sync xfer period (6)
32		REG_FIFOSTATE,      // read = FIFO status, write = sync offset
33		REG_CTRL1,      // read/write = control 1
34		REG_CLOCKFCTR,      // clock factor (write only)
35		REG_TESTMODE,      // test mode (write only)
36		REG_CTRL2,      // read/write = control 2
37		REG_CTRL3,      // read/write = control 3
38		REG_CTRL4,      // read/write = control 4
39		REG_XFERCNTHI,      // read = current xfer count hi byte, write = set xfer count hi byte
40		REG_DATAALIGN      // data alignment (write only)
41		};
42
43		READ32_HANDLER( am53cf96_r )
44		{
45		int reg, shift, rv;
	18	int rv;
46	19	static const int states[] = { 0, 0, 1, 1, 2, 3, 4, 5, 6, 7, 0 };
47	20
48		reg = offset * 2;
49		if (mem_mask == 0x000000ff)
	21	if (offset == REG_STATUS)
50	22	{
51		shift = 0;
52		}
53		else
54		{
55		reg++;
56		shift = 16;
57		}
58
59		if (reg == REG_STATUS)
60		{
61	23	scsi_regs[REG_STATUS] &= ~0x7;
62	24	scsi_regs[REG_STATUS] |= states[xfer_state];
63	25	if (xfer_state < 10)
r17439	r17440
66	28	}
67	29	}
68	30
69		rv = scsi_regs[reg]<<shift;
	31	rv = scsi_regs[offset];
70	32
71		if (reg == REG_FIFO)
	33	if (offset == REG_FIFO)
72	34	{
73		//      mame_printf_debug("53cf96: read FIFO PC=%x\n", cpu_get_pc(&space->device()));
	35	//      mame_printf_debug("53cf96: read FIFO PC=%x\n", cpu_get_pc(&space.device()));
74	36	return 0;
75	37	}
76	38
77		//  logerror("53cf96: read reg %d = %x (PC=%x)\n", reg, rv>>shift, cpu_get_pc(&space->device()));
	39	//  logerror("53cf96: read reg %d = %x (PC=%x)\n", reg, rv>>shift, cpu_get_pc(&space.device()));
78	40
79		if (reg == REG_IRQSTATE)
	41	if (offset == REG_IRQSTATE)
80	42	{
81	43	scsi_regs[REG_STATUS] &= ~0x80;   // clear IRQ flag
82	44	}
r17439	r17440
84	46	return rv;
85	47	}
86	48
87		static TIMER_CALLBACK( am53cf96_irq )
	49	void am53cf96_device::device_timer(emu_timer &timer, device_timer_id tid, int param, void *ptr)
88	50	{
89	51	scsi_regs[REG_IRQSTATE] = 8;   // indicate success
90	52	scsi_regs[REG_STATUS] |= 0x80;   // indicate IRQ
91		intf->irq_callback(machine);
	53	irq_callback(machine());
92	54	}
93	55
94		WRITE32_HANDLER( am53cf96_w )
	56	WRITE8_MEMBER( am53cf96_device::write )
95	57	{
96		int reg, val/*, dma*/;
	58	//  logerror("53cf96: w %x to reg %d (PC=%x)\n", data, offset, cpu_get_pc(&space.device()));
97	59
98		reg = offset * 2;
99		val = data;
100		if (mem_mask == 0x000000ff)
101		{
102		}
103		else
104		{
105		reg++;
106		val >>= 16;
107		}
108		val &= 0xff;
109
110		//  logerror("53cf96: w %x to reg %d (ofs %02x data %08x mask %08x PC=%x)\n", val, reg, offset, data, mem_mask, cpu_get_pc(&space->device()));
111
112	60	// if writing to the target ID, cache it off for later
113		if (reg == REG_STATUS)
	61	if (offset == REG_STATUS)
114	62	{
115		last_id = val;
	63	last_id = data;
116	64	}
117	65
118		if (reg == REG_XFERCNTLOW || reg == REG_XFERCNTMID || reg == REG_XFERCNTHI)
	66	if (offset == REG_XFERCNTLOW || offset == REG_XFERCNTMID || offset == REG_XFERCNTHI)
119	67	{
120	68	scsi_regs[REG_STATUS] &= ~0x10;   // clear CTZ bit
121	69	}
122	70
123	71	// FIFO
124		if (reg == REG_FIFO)
	72	if (offset == REG_FIFO)
125	73	{
126		//      mame_printf_debug("%02x to FIFO @ %02d\n", val, fptr);
127		fifo[fptr++] = val;
	74	//      mame_printf_debug("%02x to FIFO @ %02d\n", data, fptr);
	75	fifo[fptr++] = data;
128	76	if (fptr > 15)
129	77	{
130	78	fptr = 15;
r17439	r17440
132	80	}
133	81
134	82	// command
135		if (reg == REG_COMMAND)
	83	if (offset == REG_COMMAND)
136	84	{
137		//dma = (val & 0x80) ? 1 : 0;
	85	//dma = (data & 0x80) ? 1 : 0;
138	86	fptr = 0;
139		switch (val & 0x7f)
	87	switch (data & 0x7f)
140	88	{
141	89	case 0:   // NOP
142	90	scsi_regs[REG_IRQSTATE] = 8;   // indicate success
r17439	r17440
145	93	case 2: // reset device
146	94	scsi_regs[REG_IRQSTATE] = 8;   // indicate success
147	95
148		logerror("53cf96: reset  target ID = %d (PC = %x)\n", last_id, cpu_get_pc(&space->device()));
	96	logerror("53cf96: reset  target ID = %d (PC = %x)\n", last_id, cpu_get_pc(&space.device()));
149	97	if (devices[last_id])
150	98	{
151	99	devices[last_id]->reset();
r17439	r17440
160	108	case 3:   // reset SCSI bus
161	109	scsi_regs[REG_INTSTATE] = 4;   // command sent OK
162	110	xfer_state = 0;
163		space->machine().scheduler().timer_set( attotime::from_hz( 16384 ), FUNC(am53cf96_irq ));
	111	m_transfer_timer->adjust( attotime::from_hz( 16384 ) );
164	112	break;
165	113	case 0x42:     // select with ATN steps
166		space->machine().scheduler().timer_set( attotime::from_hz( 16384 ), FUNC(am53cf96_irq ));
	114	m_transfer_timer->adjust( attotime::from_hz( 16384 ) );
167	115	if ((fifo[1] == 0) || (fifo[1] == 0x48) || (fifo[1] == 0x4b))
168	116	{
169	117	scsi_regs[REG_INTSTATE] = 6;
r17439	r17440
173	121	scsi_regs[REG_INTSTATE] = 4;
174	122	}
175	123
176		logerror("53cf96: command %x exec.  target ID = %d (PC = %x)\n", fifo[1], last_id, cpu_get_pc(&space->device()));
	124	logerror("53cf96: command %x exec.  target ID = %d (PC = %x)\n", fifo[1], last_id, cpu_get_pc(&space.device()));
177	125	if (devices[last_id])
178	126	{
179	127	int length;
r17439	r17440
193	141	case 0x10:   // information transfer (must not change xfer_state)
194	142	case 0x11:   // second phase of information transfer
195	143	case 0x12:   // message accepted
196		space->machine().scheduler().timer_set( attotime::from_hz( 16384 ), FUNC(am53cf96_irq ));
	144	m_transfer_timer->adjust( attotime::from_hz( 16384 ) );
197	145	scsi_regs[REG_INTSTATE] = 6;   // command sent OK
198	146	break;
199	147	default:
200		printf( "unsupported command %02x\n", val );
	148	printf( "unsupported command %02x\n", data );
201	149	break;
202	150	}
203	151	}
204	152
205	153	// only update the register mirror if it's not a write-only reg
206		if (reg != REG_STATUS && reg != REG_INTSTATE && reg != REG_IRQSTATE && reg != REG_FIFOSTATE)
	154	if (offset != REG_STATUS && offset != REG_INTSTATE && offset != REG_IRQSTATE && offset != REG_FIFOSTATE)
207	155	{
208		scsi_regs[reg] = val;
	156	scsi_regs[offset] = data;
209	157	}
210	158	}
211	159
212		void am53cf96_init( running_machine &machine, const struct AM53CF96interface *interface )
	160	am53cf96_device::am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
	161	: device_t(mconfig, AM53CF96, "53CF96 SCSI", tag, owner, clock)
213	162	{
214		int i;
	163	}
215	164
216		// save interface pointer for later
217		intf = interface;
218
	165	void am53cf96_device::device_start()
	166	{
219	167	memset(scsi_regs, 0, sizeof(scsi_regs));
220	168	memset(devices, 0, sizeof(devices));
221	169
222	170	// try to open the devices
223		for (i = 0; i < interface->scsidevs->devs_present; i++)
	171	for (int i = 0; i < scsidevs->devs_present; i++)
224	172	{
225		scsidev_device *device = machine.device<scsidev_device>( interface->scsidevs->devices[i].tag );
	173	scsidev_device *device = machine().device<scsidev_device>( scsidevs->devices[i].tag );
226	174	devices[device->GetDeviceID()] = device;
227	175	}
228	176
229		state_save_register_global_array(machine, scsi_regs);
230		state_save_register_global_array(machine, fifo);
231		state_save_register_global(machine, fptr);
232		state_save_register_global(machine, xfer_state);
233		state_save_register_global(machine, last_id);
	177	fptr = 0;
	178	xfer_state = 0;
	179
	180	save_item( NAME( scsi_regs ) );
	181	save_item( NAME( fifo ) );
	182	save_item( NAME( fptr ) );
	183	save_item( NAME( xfer_state ) );
	184	save_item( NAME( last_id ) );
	185
	186	m_transfer_timer = timer_alloc( TIMER_TRANSFER );
234	187	}
235	188
	189	void am53cf96_device::static_set_interface(device_t &device, const AM53CF96interface &interface)
	190	{
	191	am53cf96_device &am53cf96 = downcast<am53cf96_device &>(device);
	192	static_cast<AM53CF96interface &>(am53cf96) = interface;
	193	}
	194
236	195	// retrieve data from the SCSI controller
237		void am53cf96_read_data(int bytes, UINT8 *pData)
	196	void am53cf96_device::dma_read_data(int bytes, UINT8 *pData)
238	197	{
239	198	scsi_regs[REG_STATUS] |= 0x10;   // indicate DMA finished
240	199
r17439	r17440
249	208	}
250	209
251	210	// write data to the SCSI controller
252		void am53cf96_write_data(int bytes, UINT8 *pData)
	211	void am53cf96_device::dma_write_data(int bytes, UINT8 *pData)
253	212	{
254	213	//  int i;
255	214
r17439	r17440
264	223	logerror("53cf96: request for unknown device SCSI ID %d\n", last_id);
265	224	}
266	225	}
	226
	227	const device_type AM53CF96 = &device_creator<am53cf96_device>;

trunk/src/emu/machine/am53cf96.h

r17439	r17440
7	7	#define _AM53CF96_H_
8	8
9	9	#include "scsi.h"
	10	#include "scsidev.h"
10	11
11	12	struct AM53CF96interface
12	13	{
r17439	r17440
14	15	void (*irq_callback)(running_machine &machine);   /* irq callback */
15	16	};
16	17
17		extern void am53cf96_init( running_machine &machine, const struct AM53CF96interface *interface );
18		extern void am53cf96_read_data(int bytes, UINT8 *pData);
19		void am53cf96_write_data(int bytes, UINT8 *pData);
20		extern READ32_HANDLER( am53cf96_r );
21		extern WRITE32_HANDLER( am53cf96_w );
	18	#define MCFG_AM53CF96_ADD( _tag, _interface ) \
	19	MCFG_DEVICE_ADD( _tag, AM53CF96, 0 ) \
	20	am53cf96_device::static_set_interface(*device, _interface);
22	21
	22	// 53CF96 register set
	23	enum
	24	{
	25	REG_XFERCNTLOW = 0,   // read = current xfer count lo byte, write = set xfer count lo byte
	26	REG_XFERCNTMID,      // read = current xfer count mid byte, write = set xfer count mid byte
	27	REG_FIFO,      // read/write = FIFO
	28	REG_COMMAND,      // read/write = command
	29
	30	REG_STATUS,      // read = status, write = destination SCSI ID (4)
	31	REG_IRQSTATE,      // read = IRQ status, write = timeout         (5)
	32	REG_INTSTATE,      // read = internal state, write = sync xfer period (6)
	33	REG_FIFOSTATE,      // read = FIFO status, write = sync offset
	34	REG_CTRL1,      // read/write = control 1
	35	REG_CLOCKFCTR,      // clock factor (write only)
	36	REG_TESTMODE,      // test mode (write only)
	37	REG_CTRL2,      // read/write = control 2
	38	REG_CTRL3,      // read/write = control 3
	39	REG_CTRL4,      // read/write = control 4
	40	REG_XFERCNTHI,      // read = current xfer count hi byte, write = set xfer count hi byte
	41	REG_DATAALIGN      // data alignment (write only)
	42	};
	43
	44	class am53cf96_device : public device_t,
	45	public AM53CF96interface
	46	{
	47	public:
	48	// construction/destruction
	49	am53cf96_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
	50
	51	// inline configuration helpers
	52	static void static_set_interface(device_t &device, const AM53CF96interface &interface);
	53
	54	DECLARE_READ8_MEMBER(read);
	55	DECLARE_WRITE8_MEMBER(write);
	56
	57	void dma_read_data(int bytes, UINT8 *pData);
	58	void dma_write_data(int bytes, UINT8 *pData);
	59
	60	protected:
	61	// device-level overrides
	62	virtual void device_start();
	63	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
	64
	65	private:
	66	static const device_timer_id TIMER_TRANSFER = 0;
	67
	68	scsidev_device *devices[8];
	69
	70	UINT8 scsi_regs[32];
	71	UINT8 fifo[16];
	72	UINT8 fptr;
	73	UINT8 xfer_state;
	74	UINT8 last_id;
	75
	76	emu_timer* m_transfer_timer;
	77	};
	78
	79	// device type definition
	80	extern const device_type AM53CF96;
	81
23	82	#endif

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