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| r14134 Friday 7th October, 2011 at 16:06:28 UTC by Tafoid |
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| Made the interrupt priority registers reusable on the SH3, hooked up TMU priority register on the sh3 side so that the Timers actually attempt to cause exceptions. From Haze (nw) |
| [src/emu/cpu/sh4] | sh3comn.c sh3comn.h sh4.c sh4comn.c sh4comn.h |
| [src/mame/drivers] | cavesh3.c |
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