MAME SVN History

199869 Revisions

r40527 Friday 28th August, 2015 at 07:25:52 UTC by Joakim Larsson Edström
Added centronics-ish interface support for the fccpu1 board as expected by the system ROM, tested and works

[/trunk]	.gitignore
[hash]	megadriv.xml x1_cass.xml
[src/emu/bus/centronics]	printer.c
[src/emu/drivers]	emudummy.c
[src/emu/machine]	68230pit.c 68230pit.h
[src/emu/netlist]	nl_base.h nl_setup.h
[src/emu/netlist/plib]	pstring.c pstring.h
[src/emu/netlist/solver]	nld_solver.h
[src/emu/sound]	c352.c c352.h tms5110.c tms5110.h tms5220.c tms5220.h
[src/mame]	arcade.lst
[src/mame/drivers]	fcrash.c lethalj.c midxunit.c namcofl.c namconb1.c namcond1.c namcos11.c namcos12.c namcos22.c namcos23.c quantum.c
[src/mame/includes]	chihiro.h
[src/mame/machine]	xbox.c
[src/mame/video]	chihiro.c
[src/mess/drivers]	force68k.c mc1000.c
[src/osd/modules/debugger/win]	debugviewinfo.c debugwininfo.c editwininfo.c
[src/osd/windows]	input.c output.c window.c winmain.c winutil.c winutil.h

trunk/.gitignore
r249038	r249039
1	1	*~
2	2	/*
3		/*/
4		!/3rdparty/
5		!/artwork/
6		!/docs/
7		!/hash/
8		!/hlsl/
9		!/keymaps/
10		!/nl_examples/
11		!/samples/
12		!/scripts/
13		!/src/
14		!/tests/
15		!/web/
	3	!/*/
16	4	!/.gitattributes
17	5	!/.gitignore
18	6	!/.travis.yml
19	7	!/makefile
20		!/mame.doxygen
	8	!/mame.doxygen
21	9	!/*.md
	10	/cfg
	11	/diff
	12	/ini
	13	/inp
	14	/nvram
	15	/obj
	16	/roms
	17	/snap
22	18	src/regtests/chdman/temp
23	19	src/regtests/jedutil/output
24		*.pyc
		No newline at end of file
	20	/sta
	21	*.pyc
	22	/build
	23	/documentation
		No newline at end of file

trunk/hash/megadriv.xml
r249038	r249039
16204	16204	<info name="release" value="19920710"/>
16205	16205	<info name="alt_title" value="炎の闘球児ドッジ弾平"/>
16206	16206	<part name="cart" interface="megadriv_cart">
16207		<feature name="slot" value="rom_eeprom"/>
16208	16207	<dataarea name="rom" width="16" endianness="big" size="524288">
16209	16208	<rom name="mpr-14856.bin" size="524288" crc="630f07c6" sha1="ebdf20fd8aaeb3c7ec97302089b3330265118cf0" offset="0x000000"/>
16210	16209	</dataarea>
r249038	r249039
18271	18270	<info name="release" value="19941021"/>
18272	18271	<info name="alt_title" value="ロックマンメガワールド"/>
18273	18272	<part name="cart" interface="megadriv_cart">
18274		<feature name="slot" value="rom_sram"/>
18275	18273	<dataarea name="rom" width="16" endianness="big" size="2097152">
18276	18274	<rom name="rockman mega world (jpn) (alt).bin" size="2097152" crc="85c956ef" sha1="a435ac53589a29dbb655662c942daab425d3f6bd" offset="0x000000"/>
18277	18275	</dataarea>
18278		<dataarea name="sram" size="16384">
18279		</dataarea>
18280	18276	</part>
18281	18277	</software>
18282	18278
r249038	r249039
20366	20362	<info name="release" value="19911205"/>
20367	20363	<info name="alt_title" value="忍者武雷伝説"/>
20368	20364	<part name="cart" interface="megadriv_cart">
20369		<feature name="slot" value="rom_eeprom"/>
20370	20365	<dataarea name="rom" width="16" endianness="big" size="1048576">
20371	20366	<rom name="ninja burai densetsu (jpn).bin" size="1048576" crc="a8d828a0" sha1="9cc3419ca7ecaf0d106aa896ffc0266c7145fff7" offset="0x000000"/>
20372	20367	</dataarea>

trunk/hash/x1_cass.xml
r249038	r249039
12	12
13	13	<softwarelist name="x1_cass" description="Sharp X1 cassettes">
14	14
15		<software name="alamein">
16		<description>El Alamein</description>
17		<year>1983</year>
18		<publisher>ポニカ (Pony Canyon)</publisher>
19		<info name="alt_title" value="エル・アラメイン"/>
20		<info name="usage" value="In BASIC, type LOAD and then RUN"/>
21		<sharedfeat name="requirement" value="x1_flop:tapbas"/>
22		<part name="cass" interface="x1_cass">
23		<dataarea name="side1" size="12742140">
24		<rom name="alamein.wav" size="12742140" crc="04e00f60" sha1="42f3ef356fdb67ddd0fbdb57e473c23d267f9bf4" offset="0" />
25		</dataarea>
26		</part>
27		</software>
28
29	15	<software name="blckonyx" supported="no">
30	16	<description>The Black Onyx</description>
31	17	<year>1985</year>
r249038	r249039
90	76	</dataarea>
91	77	</part>
92	78	</software>
93
94		<software name="cball">
95		<description>Cannon Ball</description>
96		<year>1983</year>
97		<publisher>ハドソン (Hudson Soft)</publisher>
98		<info name="alt_title" value="キャノンボール"/>
99		<part name="cass" interface="x1_cass">
100		<dataarea name="side1" size="4857558">
101		<rom name="cball.wav" size="4857558" crc="4405cf21" sha1="769a43d97f69b5d72347ca8b72547e464b9d059b" offset="0" />
102		</dataarea>
103		</part>
104		</software>
105	79
106	80	<software name="cprowsp">
107	81	<description>Champion ProWres Special</description>
r249038	r249039
322	296	</dataarea>
323	297	</part>
324	298	</software>
325
326		<software name="machgjoe">
327		<description>Ginkou Goutou - Machinegun Joe vs. the Mafia</description>
328		<year>1983</year>
329		<publisher>ハドソン (Hudson Soft)</publisher>
330		<info name="alt_title" value="銀行強盗マシンガンジョー VS ザ・マフィア"/>
331		<part name="cass" interface="x1_cass">
332		<dataarea name="side1" size="15591932">
333		<rom name="machgjoe.wav" size="15591932" crc="3769199a" sha1="81614c317f432055f2c5fdcce51438de9fbdad7f" offset="0" />
334		</dataarea>
335		</part>
336		</software>
337	299
338	300	<software name="mappy">
339	301	<description>Mappy</description>

trunk/src/emu/bus/centronics/printer.c
r249038	r249039
99	99	output_busy(m_busy);
100	100	output_fault(1);
101	101	output_ack(1);
	102	output_select(1);
102	103	}
103	104
104	105	/*-------------------------------------------------

trunk/src/emu/drivers/emudummy.c
r249038	r249039
33	33	ROM_END
34	34
35	35
36		GAME( 1900, __dummy, 0, __dummy, 0, driver_device, 0, ROT0, "(none)", "Dummy", MA~~CHIN~~E_NO_SOUND )
	36	GAME( 1900, __dummy, 0, __dummy, 0, driver_device, 0, ROT0, "(none)", "Dummy", GAME_NO_SOUND )

trunk/src/emu/machine/68230pit.c
r249038	r249039
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/**********************************************************************
	4	*
	5	* Motorola MC68230 PI/T Parallell Interface and Timer
	6	*
	7	* Revisions
	8	* 2015-07-15 JLE initial
	9	*
	10	* Todo
	11	* - Add clock and timers
	12	* - Add all missing registers
	13	* - Add configuration
	14	**********************************************************************/
4	15
5		~~Motoro~~la MC68230 ~~PI/T Parallell Interface and T~~i~~mer~~
	16	#include "68230pit.h"
6	17
7		Revisions
8		2015-07-15 JLE initial
	18	#define LOG(x) /* x */
9	19
10		Todo
11		- Add clock and timers
12		- Add all missing registers
13		- Add configuration
14		**********************************************************************/
	20	//**************************************************************************
	21	// DEVICE TYPE DEFINITIONS
	22	//**************************************************************************
15	23
16		/*
17		Force CPU-1 init sequence
18		0801EA 0E0000 W 0000 PGCR data_w: 0000 -> 0000 & 00ff
19		0801EA 0E0002 W 0000 PSRR data_w: 0000 -> 0001 & 00ff
20		0801EA 0E0004 W FFFF PADDR data_w: 00ff -> 0002 & 00ff
21		0801EA 0E0006 W 0000 PBDDR data_w: 0000 -> 0003 & 00ff
22		0801F0 0E000C W 6060 PACR data_w: 0060 -> 0006 & 00ff
23		0801F6 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
24		0801FC 0E0000 W 3030 PGCR data_w: 0030 -> 0000 & 00ff
25		080202 0E000E W A8A8 PBCR data_w: 00a8 -> 0007 & 00ff
26		080210 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
	24	const device_type PIT68230 = &device_creator<pit68230_device>;
27	25
28		Force CPU-1 after one keypress in terminal
29		081DC0 0E000C W 6868 PACR
30		081DC8 0E000C W 6060 PACR
31		*/
	26	//-------------------------------------------------
	27	// pit68230_device - constructors
	28	//-------------------------------------------------
	29	pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 variant, const char shortname, const char *source)
	30	: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
	31	device_execute_interface (mconfig, *this)
	32	, m_icount (0)
	33	, m_write_pa (*this)
	34	, m_write_h2 (*this)
	35	{
	36	}
32	37
33	38
34		#include "emu.h"
35		#include "68230pit.h"
	39	pit68230_device::pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
	40	: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
	41	device_execute_interface (mconfig, *this)
	42	, m_icount (0)
	43	, m_write_pa (*this)
	44	, m_write_h2 (*this)
	45	{
	46	}
36	47
37		/***************************************************************************
38		IMPLEMENTATION
39		***************************************************************************/
	48	//-------------------------------------------------
	49	// device_start - device-specific startup
	50	//-------------------------------------------------
	51	void pit68230_device::device_start ()
	52	{
	53	LOG (logerror ("PIT68230 device started\n"));
	54	m_icountptr = &m_icount;
40	55
41		// device type definition
42		const device_type PIT68230 = &device_creator<pit68230_device>;
	56	// resolve callbacks
	57	m_write_pa.resolve_safe ();
	58	m_write_h2.resolve_safe ();
	59	}
43	60
44	61	//-------------------------------------------------
45		// ~~pit68230_~~device - cons~~tru~~ctor
	62	// device_reset - device-specific reset
46	63	//-------------------------------------------------
47
48		pit68230_device::pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
49		: device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__)
	64	void pit68230_device::device_reset ()
50	65	{
	66	LOG (logerror ("PIT68230 device reseted\n"));
	67	m_pgcr = 0;
	68	m_psrr = 0;
	69	m_paddr = 0;
	70	m_pbddr = 0;
	71	m_pcddr = 0;
	72	m_pacr = 0; m_write_h2 (m_pacr);
	73	m_pbcr = 0;
	74	m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
	75	m_pbdr = 0;
	76	m_psr = 0;
51	77	}
52	78
53		void pit68230_device::device_start()
	79	//-------------------------------------------------
	80	// device_timer - handler timer events
	81	//-------------------------------------------------
	82	void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32 param, void *ptr)
54	83	{
55		printf("PIT68230 device started\n");
56	84	}
57	85
58		void pit68230_device::~~device~~_reset()
	86	void pit68230_device::h1_set (UINT8 state)
59	87	{
60		printf("PIT68230 device reseted\n");
61		m_pgcr = 0;
62		m_psrr = 0;
63		m_paddr = 0;
64		m_pbddr = 0;
65		m_pcddr = 0;
66		m_pacr = 0;
67		m_pbcr = 0;
68		m_padr = 0;
69		m_pbdr = 0;
70		m_psr = 0;
	88	LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr));
	89	if (state) m_psr \|= 1; else m_psr &= ~1;
	90	LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ()));
71	91	}
72	92
73		~~WRITE8_MEMBER(~~ pit68230_device::data_w )
	93	void pit68230_device::portb_setbit (UINT8 bit, UINT8 state)
74	94	{
75		printf("data_w: %04x -> ", data);
76		switch (offset)
77		{
78		case PIT_68230_PGCR:
79		printf("PGCR");
80		m_pgcr = data;
81		break;
82		case PIT_68230_PSRR:
83		printf("PSRR");
84		m_psrr = data;
85		break;
86		case PIT_68230_PADDR:
87		printf("PADDR");
88		m_paddr = data;
89		break;
90		case PIT_68230_PBDDR:
91		printf("PBDDR");
92		m_pbddr = data;
93		break;
94		case PIT_68230_PACR:
95		printf("PACR");
96		m_pacr = data;
97		break;
98		case PIT_68230_PBCR:
99		printf("PBCR");
100		m_pbcr = data;
101		break;
102		case PIT_68230_PADR:
103		printf("PADR");
104		m_padr = data;
105		break;
106		case PIT_68230_PSR:
107		printf("PSR");
108		m_padr = data;
109		break;
110		default:
111		printf("unhandled register %02x", offset);
112		}
113		printf("\n");
	95	LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr));
	96	if (state) m_pbdr \|= (1 << bit); else m_pbdr &= ~(1 << bit);
	97	LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
114	98	}
115	99
116		READ8_MEMBER( pit68230_device::data_r )
	100	//-------------------------------------------------
	101	// execute_run -
	102	//-------------------------------------------------
	103	void pit68230_device::execute_run ()
117	104	{
118		UINT8 data = 0;
	105	do {
	106	synchronize ();
119	107
120		printf("data_r: ");
121		switch (offset)
122		{
123		case PIT_68230_PGCR:
124		printf("PGCR");
125		data = m_pgcr;
126		break;
127		case PIT_68230_PSRR:
128		printf("PSRR");
129		data = m_psrr;
130		break;
131		case PIT_68230_PADDR:
132		printf("PADDR");
133		data = m_paddr;
134		break;
135		case PIT_68230_PBDDR:
136		printf("PBDDR");
137		data = m_pbddr;
138		break;
139		case PIT_68230_PACR:
140		printf("PACR");
141		data = m_pacr;
142		break;
143		case PIT_68230_PBCR:
144		printf("PBCR");
145		data = m_pbcr;
146		break;
147		case PIT_68230_PADR:
148		printf("PADR");
149		data = m_padr;
150		break;
151		case PIT_68230_PBDR:
152		/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding register for moving data
153		to and from port B pins. The port B data direction register determines whether each pin is an input (zero)
154		or an output (one). This register is readable and writable at all times. Depending on the chosen mode/submode,
155		reading or writing may affect the double-buffered handshake mechanism. The port B data register is not affected
156		by the assertion of the RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
157		printf("PBDR");
158		data = m_pbdr;
159		// data = (m_pbdr & 0xfc) \| 1; // CPU-1 centronics interface expects to see 2 lowest bits equal 1 for printer
160		break;
161		case PIT_68230_PSR:
162		printf("PSR");
163		data = m_psr;
164		// data = m_psr \| 1; // CPU-1 centronics interface expects status to be non zero
165		break;
166		default:
167		printf("unhandled register %02x", offset);
168		data = 0;
169		}
170		printf("\n");
	108	m_icount--;
	109	} while (m_icount > 0);
	110	}
171	111
172		return data;
	112	LOG (static INT32 ow_cnt = 0);
	113	LOG (static INT32 ow_data = 0);
	114	LOG (static INT32 ow_ofs = 0);
	115
	116	WRITE8_MEMBER (pit68230_device::write){
	117	switch (offset) {
	118	case PIT_68230_PGCR:
	119	m_pgcr = data;
	120	break;
	121
	122	case PIT_68230_PSRR:
	123	m_psrr = data;
	124	break;
	125
	126	case PIT_68230_PADDR:
	127	m_paddr = data;
	128	break;
	129
	130	case PIT_68230_PBDDR:
	131	m_pbddr = data;
	132	break;
	133
	134	case PIT_68230_PACR:
	135	m_pacr = data;
	136	// callbacks
	137	/*PACR in Mode 0
	138	* 5 43 H2 Control in Submode 00 && 01
	139	* ------------------------------------
	140	* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
	141	* 1 00 Output pin - negated, H2S is always clear.
	142	* 1 01 Output pin - asserted, H2S is always clear.
	143	* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
	144	* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
	145	*
	146	* 5 43 H2 Control in Submode 1x
	147	* ------------------------------------
	148	* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
	149	* 1 X0 Output pin - negated, H2S is always cleared.
	150	* 1 X1 Output pin - asserted, H2S is always cleared.
	151	*/
	152	m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
	153	break;
	154
	155	case PIT_68230_PBCR:
	156	m_pbcr = data;
	157	break;
	158
	159	case PIT_68230_PADR:
	160	m_padr = data;
	161	// callbacks
	162	m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
	163	break;
	164
	165	case PIT_68230_PSR:
	166	m_psr = data;
	167	break;
	168
	169	default:
	170	LOG (logerror ("unhandled register %02x", offset));
	171	}
	172
	173	LOG (if (offset != ow_ofs \|\| data != ow_data \|\| ow_cnt >= 1000) {
	174	logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt);
	175	ow_cnt = 0;
	176	ow_data = data;
	177	ow_ofs = offset;
	178	logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ());
	179	}
	180	else
	181	ow_cnt++; )
173	182	}
	183
	184	LOG (static INT32 or_cnt = 0);
	185	LOG (static INT32 or_data = 0);
	186	LOG (static INT32 or_ofs = 0);
	187
	188	READ8_MEMBER (pit68230_device::read){
	189	UINT8 data = 0;
	190
	191	switch (offset) {
	192	case PIT_68230_PGCR:
	193	data = m_pgcr;
	194	break;
	195
	196	case PIT_68230_PSRR:
	197	data = m_psrr;
	198	break;
	199
	200	case PIT_68230_PADDR:
	201	data = m_paddr;
	202	break;
	203
	204	case PIT_68230_PBDDR:
	205	data = m_pbddr;
	206	break;
	207
	208	case PIT_68230_PACR:
	209	data = m_pacr;
	210	break;
	211
	212	case PIT_68230_PBCR:
	213	data = m_pbcr;
	214	break;
	215
	216	case PIT_68230_PADR:
	217	data = m_padr;
	218	break;
	219
	220	case PIT_68230_PBDR:
	221	/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
	222	* register for moving data to and from port B pins. The port B data direction
	223	* register determines whether each pin is an input (zero) or an output (one).
	224	* This register is readable and writable at all times. Depending on the chosen
	225	* mode/submode, reading or writing may affect the double-buffered handshake
	226	* mechanism. The port B data register is not affected by the assertion of the
	227	* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
	228	data = m_pbdr;
	229	break;
	230
	231	case PIT_68230_PSR:
	232	/* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about
	233	* handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake
	234	* pin, and are independent of the handshake pin sense bits in the port general control
	235	* register. Bits 3-0 are the respective status bits referred to throughout this document.
	236	* Their interpretation depends on the programmed mode/submode of the PI/T. For bits
	237	* 3-0 a one is the active or asserted state. */
	238	data = m_psr;
	239	break;
	240
	241	default:
	242	LOG (logerror ("unhandled register %02x", offset));
	243	data = 0;
	244	}
	245
	246	LOG (if (offset != or_ofs \|\| data != or_data \|\| or_cnt >= 1000) {
	247	logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt);
	248	or_cnt = 0;
	249	or_data = data;
	250	or_ofs = offset;
	251	logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ());
	252	}
	253	else
	254	or_cnt++; )
	255
	256	return data;
	257	}

trunk/src/emu/machine/68230pit.h
r249038	r249039
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/**********************************************************************
	4	*
	5	* Motorola MC68230 PI/T Parallell Interface and Timer
	6	*
	7	* _____ _____
	8	* D5 1 \|* \_/ \| 48 D4
	9	* D6 2 \| \| 47 D3
	10	* D7 3 \| \| 46 D2
	11	* PA0 4 \| \| 45 D1
	12	* PA1 5 \| \| 44 D0
	13	* PA2 6 \| \| 43 R/W*
	14	* PA3 7 \| \| 42 DTACK*
	15	* PA4 8 \| \| 41 CS*
	16	* PA5 9 \| \| 40 CLK
	17	* PA6 10 \| \| 39 RESET*
	18	* PA7 11 \| \| 38 VSS
	19	* Vcc 12 \| TS68230 \| 37 PC7/TIACK*
	20	* H1 13 \| SC87845 \| 36 PC6/PIACK*
	21	* H2 14 \| \| 35 PC5/PIRQ*
	22	* H3 15 \| \| 34 PC4/DMAREQ*
	23	* H4 16 \| \| 33 PC3/TOUT
	24	* PB0 17 \| \| 32 PC2/TIN
	25	* PB1 18 \| \| 31 PC1
	26	* PB2 19 \| \| 30 PC0
	27	* PB3 20 \| \| 29 RS1
	28	* PB4 21 \| \| 28 RS2
	29	* PB5 22 \| \| 27 RS3
	30	* PB6 23 \| \| 26 RS4
	31	* PB7 24 \|_____________\| 25 RS5
	32	*
	33	**********************************************************************/
4	34
5		Motorola MC68230 PI/T Parallell Interface and Timer
6
7		**********************************************************************/
8	35	#pragma once
9	36
10	37	#ifndef __68230PIT_H__
r249038	r249039
12	39
13	40	#include "emu.h"
14	41
	42	//**************************************************************************
	43	// INTERFACE CONFIGURATION MACROS
	44	//**************************************************************************
	45
	46	#define MCFG_PIT68230_PA_OUTPUT_CALLBACK(_write) \
	47	devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write);
	48
	49	#define MCFG_PIT68230_PB_OUTPUT_CALLBACK(_write) \
	50	devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write);
	51
	52	#define MCFG_PIT68230_H2_CALLBACK(_write) \
	53	devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write);
	54
15	55	/*-----------------------------------------------------------------------
16		Registers RS1-RS5 R/W Description
17		-------------------------------------------------------------------------*/
	56	* Registers RS1-RS5 R/W Description
	57	* -------------------------------------------------------------------------*/
18	58	#define PIT_68230_PGCR 0x00 /* RW Port General Control register */
19	59	#define PIT_68230_PSRR 0x01 /* RW Port Service Request register */
20	60	#define PIT_68230_PADDR 0x02 /* RW Port A Data Direction register */
r249038	r249039
42	82	//**************************************************************************
43	83	// TYPE DEFINITIONS
44	84	//**************************************************************************
45		class pit68230_device : public device_t
	85	class pit68230_device : public device_t, public device_execute_interface
46	86	{
47	87	public:
48		// construction/destruction
49		pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
50		DECLARE_WRITE8_MEMBER( data_w );
51		DECLARE_READ8_MEMBER( data_r );
	88	// construction/destruction
	89	pit68230_device(const machine_config &mconfig, device_type type, const char name, const char tag, device_t owner, UINT32 clock, UINT32 variant, const char shortname, const char *source);
	90	pit68230_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock);
	91	template<class _Object> static devcb_base &set_pa_wr_callback (device_t &device, _Object object)
	92	{
	93	return downcast<pit68230_device &>(device).m_write_pa.set_callback (object);
	94	}
	95	template<class _Object> static devcb_base &set_h2_wr_callback (device_t &device, _Object object)
	96	{
	97	return downcast<pit68230_device &>(device).m_write_h2.set_callback (object);
	98	}
52	99
	100	DECLARE_WRITE8_MEMBER (write);
	101	DECLARE_READ8_MEMBER (read);
	102
	103	void h1_set (UINT8 state);
	104	void portb_setbit (UINT8 bit, UINT8 state);
	105
53	106	protected:
54		// device-level overrides
55		virtual void device_start();
56		virtual void device_reset();
	107	// device-level overrides
	108	virtual void device_start ();
	109	virtual void device_reset ();
	110	virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr);
	111	virtual void execute_run ();
	112	int m_icount;
	113	devcb_write8 m_write_pa;
	114	devcb_write_line m_write_h2;
57	115
58		private:
59		UINT8 m_pgcr; // Port General Control register
60		UINT8 m_psrr; // Port Service Request register
61		UINT8 m_paddr; // Port A Data Direction register
62		UINT8 m_pbddr; // Port B Data Direction register
63		UINT8 m_pcddr; // Port C Data Direction register
64		UINT8 m_pacr; // Port A Control register
65		UINT8 m_pbcr; // Port B Control register
66		UINT8 m_padr; // Port A Data register
67		UINT8 m_pbdr; // Port B Data register
68		UINT8 m_psr; // Port Status Register
	116	// peripheral ports
	117	UINT8 m_pgcr; // Port General Control register
	118	UINT8 m_psrr; // Port Service Request register
	119	UINT8 m_paddr; // Port A Data Direction register
	120	UINT8 m_pbddr; // Port B Data Direction register
	121	UINT8 m_pcddr; // Port C Data Direction register
	122	UINT8 m_pacr; // Port A Control register
	123	UINT8 m_pbcr; // Port B Control register
	124	UINT8 m_padr; // Port A Data register
	125	UINT8 m_pbdr; // Port B Data register
	126	UINT8 m_psr; // Port Status Register
69	127	};
70	128
71
72	129	// device type definition
73	130	extern const device_type PIT68230;
74
75		#endif // __68230PIT__
	131	#endif /* __68230PIT_H__ */

trunk/src/emu/netlist/nl_base.h
r249038	r249039
1233	1233	pnamedlist_t<core_device_t *> m_started_devices;
1234	1234	#endif
1235	1235
1236		ATTR_COLD plog_base<NL_DEBUG> &log() { return m_log; }
1237	1236	ATTR_COLD const plog_base<NL_DEBUG> &log() const { return m_log; }
1238	1237
1239	1238	protected:

trunk/src/emu/netlist/nl_setup.h
r249038	r249039
198	198
199	199	void model_parse(const pstring &model, model_map_t &map);
200	200
201		plog_base<NL_DEBUG> &log() { return netlist().log(); }
202	201	const plog_base<NL_DEBUG> &log() const { return netlist().log(); }
203	202
204	203	protected:

trunk/src/emu/netlist/plib/pstring.c
r249038	r249039
14	14
15	15	#include "pstring.h"
16	16	#include "palloc.h"
17		#include "plists.h"
18	17
19	18	template<>
20	19	pstr_t pstring_t<putf8_traits>::m_zero = pstr_t(0);
r249038	r249039
306	305	// static stuff ...
307	306	// ----------------------------------------------------------------------------------------
308	307
309		/*
310		* Cached allocation of string memory
311		*
312		* This improves startup performance by 30%.
313		*/
314
315		#if 1
316
317		static pstack_t<pstr_t > stk = NULL;
318
319		static inline unsigned countleadbits(unsigned x)
320		{
321		#ifndef count_leading_zeros
322		unsigned msk;
323		unsigned ret;
324		if (x < 0x100)
325		{
326		msk = 0x80;
327		ret = 24;
328		}
329		else if (x < 0x10000)
330		{
331		msk = 0x8000;
332		ret = 16;
333		}
334		else if (x < 0x1000000)
335		{
336		msk = 0x800000;
337		ret = 8;
338		}
339		else
340		{
341		msk = 0x80000000;
342		ret = 0;
343		}
344		while ((msk & x) == 0 && ret < 31)
345		{
346		msk = msk >> 1;
347		ret++;
348		}
349		return ret;
350		#else
351		return count_leading_zeros(x);
352		#endif
353		}
354
355	308	template<typename F>
356	309	void pstring_t<F>::sfree(pstr_t *s)
357	310	{
358	311	s->m_ref_count--;
359	312	if (s->m_ref_count == 0 && s != &m_zero)
360	313	{
361		if (stk != NULL)
362		{
363		unsigned sn= ((32 - countleadbits(s->len())) + 1) / 2;
364		stk[sn].push(s);
365		}
366		else
367		pfree_array(((char *)s));
368		//_mm_free(((char *)s));
369		}
370		}
371
372		template<typename F>
373		pstr_t *pstring_t<F>::salloc(int n)
374		{
375		if (stk == NULL)
376		stk = palloc_array(pstack_t<pstr_t *>, 17);
377		pstr_t *p;
378		unsigned sn= ((32 - countleadbits(n)) + 1) / 2;
379		unsigned size = sizeof(pstr_t) + (1<<(sn * 2)) + 1;
380		if (stk[sn].empty())
381		p = (pstr_t *) palloc_array(char, size);
382		else
383		{
384		//printf("%u %u\n", sn, (unsigned) stk[sn].count());
385		p = stk[sn].pop();
386		}
387
388		// str_t p = (str_t ) _mm_malloc(size, 8);
389		p->init(n);
390		return p;
391		}
392		template<typename F>
393		void pstring_t<F>::resetmem()
394		{
395		if (stk != NULL)
396		{
397		for (unsigned i=0; i<=16; i++)
398		{
399		for (; stk[i].count() > 0; )
400		pfree_array(stk[i].pop());
401		}
402		pfree_array(stk);
403		stk = NULL;
404		}
405		}
406
407
408		#else
409		template<typename F>
410		void pstring_t<F>::sfree(pstr_t *s)
411		{
412		s->m_ref_count--;
413		if (s->m_ref_count == 0 && s != &m_zero)
414		{
415	314	pfree_array(((char *)s));
416	315	//_mm_free(((char *)s));
417	316	}
r249038	r249039
432	331	{
433	332	// Release the 0 string
434	333	}
435		#endif
436	334
437
438	335	// ----------------------------------------------------------------------------------------
439	336	// pstring ...
440	337	// ----------------------------------------------------------------------------------------

trunk/src/emu/netlist/plib/pstring.h
r249038	r249039
22	22	struct pstr_t
23	23	{
24	24	//str_t() : m_ref_count(1), m_len(0) { m_str[0] = 0; }
25		pstr_t(const ~~uns~~igned alen)
	25	pstr_t(const int alen)
26	26	{
27	27	init(alen);
28	28	}
29		void init(const ~~uns~~igned alen)
	29	void init(const int alen)
30	30	{
31	31	m_ref_count = 1;
32	32	m_len = alen;
33	33	m_str[0] = 0;
34	34	}
35	35	char *str() { return &m_str[0]; }
36		~~uns~~igned len() const { return m_len; }
	36	int len() const { return m_len; }
37	37	int m_ref_count;
38	38	private:
39		~~uns~~igned m_len;
	39	int m_len;
40	40	char m_str[1];
41	41	};
42	42
r249038	r249039
548	548	class pfmt_writer_t
549	549	{
550	550	public:
551		pfmt_writer_t() ~~: m_enabled(true)~~ { }
	551	pfmt_writer_t() { }
552	552	virtual ~pfmt_writer_t() { }
553	553
554	554	ATTR_COLD void operator ()(const char *fmt) const
555	555	{
556		if (build_enabled ~~&& m_enabled~~) vdowrite(fmt);
	556	if (build_enabled) vdowrite(fmt);
557	557	}
558	558
559	559	template<typename T1>
560	560	ATTR_COLD void operator ()(const char *fmt, const T1 &v1) const
561	561	{
562		if (build_enabled ~~&& m_enabled~~) vdowrite(pfmt(fmt)(v1));
	562	if (build_enabled) vdowrite(pfmt(fmt)(v1));
563	563	}
564	564
565	565	template<typename T1, typename T2>
566	566	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2) const
567	567	{
568		if (build_enabled ~~&& m_enabled~~) vdowrite(pfmt(fmt)(v1)(v2));
	568	if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2));
569	569	}
570	570
571	571	template<typename T1, typename T2, typename T3>
572	572	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2, const T3 &v3) const
573	573	{
574		if (build_enabled ~~&& m_enabled~~) vdowrite(pfmt(fmt)(v1)(v2)(v3));
	574	if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3));
575	575	}
576	576
577	577	template<typename T1, typename T2, typename T3, typename T4>
578	578	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2, const T3 &v3, const T4 &v4) const
579	579	{
580		if (build_enabled ~~&& m_enabled~~) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4));
	580	if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4));
581	581	}
582	582
583	583	template<typename T1, typename T2, typename T3, typename T4, typename T5>
584	584	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2, const T3 &v3, const T4 &v4, const T5 &v5) const
585	585	{
586		if (build_enabled ~~&& m_enabled~~) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4)(v5));
	586	if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4)(v5));
587	587	}
588	588
589		void set_enabled(const bool v)
590		{
591		m_enabled = v;
592		}
593
594		bool is_enabled() const { return m_enabled; }
595
596	589	protected:
597	590	virtual void vdowrite(const pstring &ls) const {}
598	591
599		private:
600		bool m_enabled;
601
602	592	};
603	593
604	594	template <plog_level L, bool build_enabled = true>

trunk/src/emu/netlist/solver/nld_solver.h
r249038	r249039
135	135	ATTR_COLD int get_net_idx(net_t *net);
136	136
137	137	inline eSolverType type() const { return m_type; }
138		plog_base<NL_DEBUG> &log() { return netlist().log(); }
	138	const plog_base<NL_DEBUG> &log() const { return netlist().log(); }
139	139
140	140	virtual void log_stats();
141	141

trunk/src/emu/sound/c352.c
r249038	r249039
13	13	Supports 8-bit linear and 8-bit muLaw samples
14	14	Output: digital, 16 bit, 4 channels
15	15	Output sample rate is the input clock / (288 * 2).
16
17		superctr: The clock divider appears to be configurable for each system.
18		Below is a list of the divider values followed by the systems that use it.
19
20		* 228: System 11.
21		* 288: System 22, Super 22, NB-1/2, ND-1, FL.
22		* 296: System 23, Super 23.
23		* 332: System 12.
24	16	*/
25	17
26	18	#include "emu.h"
r249038	r249039
476	468
477	469	void c352_device::device_start()
478	470	{
479		int i;
	471	int i, divider;
480	472	double x_max = 32752.0;
481	473	double y_max = 127.0;
482	474	double u = 10.0;
r249038	r249039
484	476	// find our direct access
485	477	m_direct = &space().direct();
486	478
487		m_sample_rate_base = clock() / m_divider;
	479	switch(m_divider)
	480	{
	481	case C352_DIVIDER_228:
	482	divider=228;
	483	break;
	484	case C352_DIVIDER_288:
	485	default:
	486	divider=288;
	487	break;
	488	case C352_DIVIDER_332:
	489	divider=332;
	490	break;
	491	}
488	492
	493	m_sample_rate_base = clock() / divider;
	494
489	495	m_stream = machine().sound().stream_alloc(*this, 0, 4, m_sample_rate_base);
490	496
491	497	// generate mulaw table for mulaw format samples

trunk/src/emu/sound/c352.h
r249038	r249039
6	6	#define __C352_H__
7	7
8	8	//**************************************************************************
	9	// CONSTANTS
	10	//**************************************************************************
	11
	12	enum
	13	{
	14	C352_DIVIDER_228 = 0,
	15	C352_DIVIDER_288 = 1,
	16	C352_DIVIDER_332 = 2
	17	};
	18
	19	//**************************************************************************
9	20	// INTERFACE CONFIGURATION MACROS
10	21	//**************************************************************************
11	22

trunk/src/emu/sound/tms5110.c
r249038	r249039
14	14
15	15	Todo:
16	16	- implement CS
	17	- implement missing commands
17	18	- TMS5110_CMD_TEST_TALK is only partially implemented
18	19
19	20	TMS5100:
r249038	r249039
211	212	{
212	213	save_item(NAME(m_variant));
213	214
	215	save_item(NAME(m_fifo));
	216	save_item(NAME(m_fifo_head));
	217	save_item(NAME(m_fifo_tail));
	218	save_item(NAME(m_fifo_count));
	219
214	220	save_item(NAME(m_PDC));
215	221	save_item(NAME(m_CTL_pins));
216	222	save_item(NAME(m_SPEN));
r249038	r249039
235	241	save_item(NAME(m_old_frame_pitch_idx));
236	242	save_item(NAME(m_old_frame_k_idx));
237	243	save_item(NAME(m_old_zpar));
238		save_item(NAME(m_old_uv_zpar));
239	244	#endif
240	245	save_item(NAME(m_current_energy));
241	246	save_item(NAME(m_current_pitch));
r249038	r249039
305	310	}
306	311	#endif
307	312
	313
308	314	/******************************************************************************************
309	315
310		~~extr~~act_bits -- extract a ~~spec~~i~~fic numb~~er of bits from the VSM
	316	FIFO_data_write -- handle bit data write to the TMS5110 (as a result of toggling M0 pin)
311	317
312	318	******************************************************************************************/
	319	void tms5110_device::FIFO_data_write(int data)
	320	{
	321	/* add this bit to the FIFO */
	322	if (m_fifo_count < FIFO_SIZE)
	323	{
	324	m_fifo[m_fifo_tail] = (data&1); /* set bit to 1 or 0 */
313	325
	326	m_fifo_tail = (m_fifo_tail + 1) % FIFO_SIZE;
	327	m_fifo_count++;
	328
	329	if (DEBUG_5110) logerror("Added bit to FIFO (size=%2d)\n", m_fifo_count);
	330	}
	331	else
	332	{
	333	if (DEBUG_5110) logerror("Ran out of room in the FIFO!\n");
	334	}
	335	}
	336
	337	/******************************************************************************************
	338
	339	extract_bits -- extract a specific number of bits from the FIFO
	340
	341	******************************************************************************************/
	342
314	343	int tms5110_device::extract_bits(int count)
315	344	{
316	345	int val = 0;
317		if (DEBUG_5110) logerror("requesting %d bits", count);
318		for (int i = 0; i < count; i++)
	346	if (DEBUG_5110) logerror("requesting %d bits from fifo: ", count);
	347	while (count--)
319	348	{
320		val = (val<<1) \| new_int_read();
321		if (DEBUG_5110) logerror("bit read: %d\n", val&1);
	349	val = (val << 1) \| (m_fifo[m_fifo_head] & 1);
	350	m_fifo_count--;
	351	m_fifo_head = (m_fifo_head + 1) % FIFO_SIZE;
322	352	}
323	353	if (DEBUG_5110) logerror("returning: %02x\n", val);
324	354	return val;
325	355	}
326	356
	357	void tms5110_device::request_bits(int no)
	358	{
	359	for (int i = 0; i < no; i++)
	360	{
	361	UINT8 data = new_int_read();
	362	if (DEBUG_5110) logerror("bit added to fifo: %d\n", data);
	363	FIFO_data_write(data);
	364	}
	365	}
327	366
328	367	void tms5110_device::perform_dummy_read()
329	368	{
r249038	r249039
350	389	int i, bitout;
351	390	INT32 this_sample;
352	391
	392	/* if we're not speaking, fill with nothingness */
	393	if (!m_TALKD)
	394	goto empty;
	395
353	396	/* loop until the buffer is full or we've stopped speaking */
354		while (size > 0)
	397	while ((size > 0) && m_TALKD)
355	398	{
356		if(m_TALKD) // speaking
	399	/* if it is the appropriate time to update the old energy/pitch indices,
	400	* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
	401	* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
	402	* which happens 4 T-cycles later), we change on the latter.
	403	* The indices are updated here ~12 PCs before the new frame is applied.
	404	*/
	405	/ TODO: the patents 4331836, 4335277, and 4419540 disagree about the timing of this /
	406	if ((m_IP == 0) && (m_PC == 0) && (m_subcycle < 2))
357	407	{
358		/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
359		* (In reality, the frame was really loaded incrementally during the entire IP=0
360		* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
361		*/
362		if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
363		{
364		// HACK for regression testing, be sure to comment out before release!
365		//m_RNG = 0x1234;
366		// end HACK
	408	m_OLDE = (m_new_frame_energy_idx == 0);
	409	m_OLDP = (m_new_frame_pitch_idx == 0);
	410	}
367	411
	412	/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
	413	* (In reality, the frame was really loaded incrementally during the entire IP=0
	414	* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
	415	*/
	416	if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
	417	{
	418	// HACK for regression testing, be sure to comment out before release!
	419	//m_RNG = 0x1234;
	420	// end HACK
	421
368	422	#ifdef PERFECT_INTERPOLATION_HACK
369		/* remember previous frame energy, pitch, and coefficients */
370		m_old_frame_energy_idx = m_new_frame_energy_idx;
371		m_old_frame_pitch_idx = m_new_frame_pitch_idx;
372		for (i = 0; i < m_coeff->num_k; i++)
373		m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
	423	/* remember previous frame energy, pitch, and coefficients */
	424	m_old_frame_energy_idx = m_new_frame_energy_idx;
	425	m_old_frame_pitch_idx = m_new_frame_pitch_idx;
	426	for (i = 0; i < m_coeff->num_k; i++)
	427	m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
374	428	#endif
375	429
376		/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[] */
377		parse_frame();
378
379		// if the new frame is unvoiced (or silenced via ZPAR), be sure to zero out the k5-k10 parameters
380		// NOTE: this is probably the bug the tms5100/tmc0280 has, pre-rev D, I think.
381		// GUESS: Pre-rev D versions start zeroing k5-k10 immediately upon new frame load regardless of interpolation inhibit
382		// I.e. ZPAR = /TALKD \|\| (PC>5&&P=0)
383		// GUESS: D and later versions only start or stop zeroing k5-k10 at the IP7->IP0 transition AFTER the frame
384		// I.e. ZPAR = /TALKD \|\| (PC>5&&OLDP)
385		#ifdef PERFECT_INTERPOLATION_HACK
386		m_old_uv_zpar = m_uv_zpar;
387		m_old_zpar = m_zpar; // unset old zpar on new frame
	430	/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[] */
	431	parse_frame();
	432	#ifdef DEBUG_PARSE_FRAME_DUMP
	433	fprintf(stderr,"\n");
388	434	#endif
389		m_zpar = 0;
390		//m_uv_zpar = (OLD_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: fixed version in tmc0280d/tms5100a/cd280x/tms5110
391		m_uv_zpar = (NEW_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: buggy version in tmc0280/tms5100
	435	/* if the new frame is unvoiced (or silenced via ZPAR), be sure to zero out the k5-k10 parameters */
	436	m_uv_zpar = NEW_FRAME_UNVOICED_FLAG \| m_zpar;
392	437
393		/* if the new frame is a stop frame, unset both TALK and SPEN (via TCON). TALKD remains active while the energy is ramping to 0. */
394		if (NEW_FRAME_STOP_FLAG == 1)
395		{
396		m_TALK = m_SPEN = 0;
397		}
	438	/* if the new frame is a stop frame, unset both TALK and SPEN. TALKD remains active while the energy is ramping to 0. */
	439	if (NEW_FRAME_STOP_FLAG == 1)
	440	{
	441	m_TALK = m_SPEN = 0;
	442	}
398	443
399		/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
400		Interpolation inhibit cases:
401		* Old frame was voiced, new is unvoiced
402		* Old frame was silence/zero energy, new has nonzero energy
403		* Old frame was unvoiced, new is voiced (note this is the case on the patent but may not be correct on the real final chip)
404		*/
405		if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
406		\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0)) /* this line needs further investigation, starwars tie fighters may sound better without it */
407		\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
408		m_inhibit = 1;
409		else // normal frame, normal interpolation
410		m_inhibit = 0;
	444	/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
	445	Interpolation inhibit cases:
	446	* Old frame was voiced, new is unvoiced
	447	* Old frame was silence/zero energy, new has nonzero energy
	448	* Old frame was unvoiced, new is voiced (note this is the case on the patent but may not be correct on the real final chip)
	449	*/
	450	if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
	451	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0)) /* this line needs further investigation, starwars tie fighters may sound better without it */
	452	\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
	453	m_inhibit = 1;
	454	else // normal frame, normal interpolation
	455	m_inhibit = 0;
411	456
412	457	#ifdef DEBUG_GENERATION
413		/* Debug info for current parsed frame */
414		fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
415		fprintf(stderr,"Processing new frame: ");
416		if (m_inhibit == 0)
417		fprintf(stderr, "Normal Frame\n");
418		else
419		fprintf(stderr,"Interpolation Inhibited\n");
420		fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
421		fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",
422		(m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)),
423		m_new_frame_energy_idx,
424		(m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)),
425		(m_coeff->ktable[0][m_new_frame_k_idx[0]] * (1-m_zpar)),
426		(m_coeff->ktable[1][m_new_frame_k_idx[1]] * (1-m_zpar)),
427		(m_coeff->ktable[2][m_new_frame_k_idx[2]] * (1-m_zpar)),
428		(m_coeff->ktable[3][m_new_frame_k_idx[3]] * (1-m_zpar)),
429		(m_coeff->ktable[4][m_new_frame_k_idx[4]] * (1-m_uv_zpar)),
430		(m_coeff->ktable[5][m_new_frame_k_idx[5]] * (1-m_uv_zpar)),
431		(m_coeff->ktable[6][m_new_frame_k_idx[6]] * (1-m_uv_zpar)),
432		(m_coeff->ktable[7][m_new_frame_k_idx[7]] * (1-m_uv_zpar)),
433		(m_coeff->ktable[8][m_new_frame_k_idx[8]] * (1-m_uv_zpar)),
434		(m_coeff->ktable[9][m_new_frame_k_idx[9]] * (1-m_uv_zpar)) );
	458	/* Debug info for current parsed frame */
	459	fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
	460	fprintf(stderr,"Processing frame: ");
	461	if (m_inhibit == 0)
	462	fprintf(stderr, "Normal Frame\n");
	463	else
	464	fprintf(stderr,"Interpolation Inhibited\n");
	465	fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
	466	fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",
	467	(m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)),
	468	m_new_frame_energy_idx,
	469	(m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)),
	470	(m_coeff->ktable[0][m_new_frame_k_idx[0]] * (1-m_zpar)),
	471	(m_coeff->ktable[1][m_new_frame_k_idx[1]] * (1-m_zpar)),
	472	(m_coeff->ktable[2][m_new_frame_k_idx[2]] * (1-m_zpar)),
	473	(m_coeff->ktable[3][m_new_frame_k_idx[3]] * (1-m_zpar)),
	474	(m_coeff->ktable[4][m_new_frame_k_idx[4]] * (1-m_uv_zpar)),
	475	(m_coeff->ktable[5][m_new_frame_k_idx[5]] * (1-m_uv_zpar)),
	476	(m_coeff->ktable[6][m_new_frame_k_idx[6]] * (1-m_uv_zpar)),
	477	(m_coeff->ktable[7][m_new_frame_k_idx[7]] * (1-m_uv_zpar)),
	478	(m_coeff->ktable[8][m_new_frame_k_idx[8]] * (1-m_uv_zpar)),
	479	(m_coeff->ktable[9][m_new_frame_k_idx[9]] * (1-m_uv_zpar)) );
435	480	#endif
436	481
	482	}
	483	else // Not a new frame, just interpolate the existing frame.
	484	{
	485	int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
	486	#ifdef PERFECT_INTERPOLATION_HACK
	487	int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
	488	//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
	489	int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
	490	//fprintf(stderr, "CS: %03d", current_sample);
	491	// reset the current energy, pitch, etc to what it was at frame start
	492	m_current_energy = (m_coeff->energytable[m_old_frame_energy_idx] * (1-m_zpar));
	493	m_current_pitch = (m_coeff->pitchtable[m_old_frame_pitch_idx] * (1-m_old_zpar));
	494	for (i = 0; i < 4; i++)
	495	m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-m_old_zpar));
	496	for (i = 4; i < m_coeff->num_k; i++)
	497	m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-m_uv_zpar));
	498	// now adjust each value to be exactly correct for each of the samples per frame
	499	if (m_IP != 0) // if we're still interpolating...
	500	{
	501	m_current_energy += ((((m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)) - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame;
	502	m_current_pitch += ((((m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)) - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame;
	503	for (i = 0; i < m_coeff->num_k; i++)
	504	m_current_k[i] += ((((m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar))) - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame;
437	505	}
438		else // ~~Not a ne~~w frame, ~~just i~~nterpolate th~~e ex~~is~~ting~~ frame.
	506	else // we're done, play this frame for 1/8 frame.
439	507	{
440		int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
441		#ifdef PERFECT_INTERPOLATION_HACK
442		int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
443		//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
444		int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
445		//fprintf(stderr, "CS: %03d", current_sample);
446		// reset the current energy, pitch, etc to what it was at frame start
447		m_current_energy = (m_coeff->energytable[m_old_frame_energy_idx] * (1-m_old_zpar));
448		m_current_pitch = (m_coeff->pitchtable[m_old_frame_pitch_idx] * (1-m_old_zpar));
	508	m_current_energy = (m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar));
	509	m_current_pitch = (m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar));
449	510	for (i = 0; i < m_coeff->num_k; i++)
450		m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-((i<4)?m_old_zpar:m_old_uv_zpar)));
451		// now adjust each value to be exactly correct for each of the samples per frame
452		if (m_IP != 0) // if we're still interpolating...
453		{
454		m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
455		m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
456		for (i = 0; i < m_coeff->num_k; i++)
457		m_current_k[i] = (m_current_k[i] + (((m_coeff->ktable[i][m_new_frame_k_idx[i]] - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame)*(1-((i<4)?m_zpar:m_uv_zpar));
458		}
459		else // we're done, play this frame for 1/8 frame.
460		{
461		m_current_energy = (m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar));
462		m_current_pitch = (m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar));
463		for (i = 0; i < m_coeff->num_k; i++)
464		m_current_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar)));
465		}
	511	m_current_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar)));
	512	}
466	513	#else
467		//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
468		if (m_subcycle == 2)
	514	//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
	515	if (m_subcycle == 2)
	516	{
	517	switch(m_PC)
469	518	{
470		switch(m_PC)
471		{
472		case 0: /* PC = 0, B cycle, write updated energy */
473		m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
474		break;
475		case 1: /* PC = 1, B cycle, write updated pitch */
476		m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
477		break;
478		case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
479		/* PC = 2 through 11, B cycle, write updated K1 through K10 */
480		m_current_k[m_PC-2] = (m_current_k[m_PC-2] + (((m_coeff->ktable[m_PC-2][m_new_frame_k_idx[m_PC-2]] - m_current_k[m_PC-2])(1-inhibit_state)) INTERP_SHIFT))(((m_PC-2)>4)?(1-m_uv_zpar):(1-m_zpar));
481		break;
482		case 12: /* PC = 12 */
483		/* we should NEVER reach this point, PC=12 doesn't have a subcycle 2 */
484		break;
485		}
	519	case 0: /* PC = 0, B cycle, write updated energy */
	520	m_current_energy += ((((m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)) - m_current_energy)*(1-inhibit_state)) INTERP_SHIFT);
	521	break;
	522	case 1: /* PC = 1, B cycle, write updated pitch */
	523	m_current_pitch += ((((m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)) - m_current_pitch)*(1-inhibit_state)) INTERP_SHIFT);
	524	break;
	525	case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
	526	/* PC = 2 through 11, B cycle, write updated K1 through K10 */
	527	m_current_k[m_PC-2] += ((((m_coeff->ktable[m_PC-2][m_new_frame_k_idx[m_PC-2]] * (1-(((m_PC-2)<4)?m_zpar:m_uv_zpar))) - m_current_k[m_PC-2])*(1-inhibit_state)) INTERP_SHIFT);
	528	break;
	529	case 12: /* PC = 12, do nothing */
	530	break;
486	531	}
	532	}
487	533	#endif
488		}
	534	}
489	535
490		// calculate the output
491		if (OLD_FRAME_UNVOICED_FLAG == 1)
492		{
493		// generate unvoiced samples here
494		if (m_RNG & 1)
495		m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
496		else
497		m_excitation_data = 0x40;
498		}
499		else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
500		{
501		// generate voiced samples here
502		/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
503		* function has a chirp/peak and then a long chain of zeroes.
504		* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
505		* and if the address reaches that point the ADDRESS incrementer is
506		* disabled, forcing all samples beyond 51d to be == 51d
507		*/
508		if (m_pitch_count >= 51)
509		m_excitation_data = (INT8)m_coeff->chirptable[51];
510		else /m_pitch_count < 51/
511		m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
512		}
	536	// calculate the output
	537	if (OLD_FRAME_UNVOICED_FLAG == 1)
	538	{
	539	// generate unvoiced samples here
	540	if (m_RNG & 1)
	541	m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
	542	else
	543	m_excitation_data = 0x40;
	544	}
	545	else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
	546	{
	547	// generate voiced samples here
	548	/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
	549	* function has a chirp/peak and then a long chain of zeroes.
	550	* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
	551	* and if the address reaches that point the ADDRESS incrementer is
	552	* disabled, forcing all samples beyond 51d to be == 51d
	553	*/
	554	if (m_pitch_count >= 51)
	555	m_excitation_data = (INT8)m_coeff->chirptable[51];
	556	else /m_pitch_count < 51/
	557	m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
	558	}
513	559
514		// Update LFSR 20 times every sample (once per T cycle), like patent shows
515		for (i=0; i<20; i++)
516		{
517		bitout = ((m_RNG >> 12) & 1) ^
518		((m_RNG >> 3) & 1) ^
519		((m_RNG >> 2) & 1) ^
520		((m_RNG >> 0) & 1);
521		m_RNG <<= 1;
522		m_RNG \|= bitout;
523		}
524		this_sample = lattice_filter(); /* execute lattice filter */
	560	// Update LFSR 20 times every sample (once per T cycle), like patent shows
	561	for (i=0; i<20; i++)
	562	{
	563	bitout = ((m_RNG >> 12) & 1) ^
	564	((m_RNG >> 3) & 1) ^
	565	((m_RNG >> 2) & 1) ^
	566	((m_RNG >> 0) & 1);
	567	m_RNG <<= 1;
	568	m_RNG \|= bitout;
	569	}
	570	this_sample = lattice_filter(); /* execute lattice filter */
525	571	#ifdef DEBUG_GENERATION_VERBOSE
526		//fprintf(stderr,"C:%01d; ",m_subcycle);
527		fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
528		//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
529		for (i=0; i<10; i++)
530		fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
531		fprintf(stderr,"Out:%06d ", this_sample);
532		//#ifdef PERFECT_INTERPOLATION_HACK
533		// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
534		//#else
535		// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
536		//#endif
537		fprintf(stderr,"\n");
	572	//fprintf(stderr,"C:%01d; ",m_subcycle);
	573	fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	574	//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	575	for (i=0; i<10; i++)
	576	fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
	577	fprintf(stderr,"Out:%06d", this_sample);
	578	fprintf(stderr,"\n");
538	579	#endif
539		/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
540		while (this_sample > 16383) this_sample -= 32768;
541		while (this_sample < -16384) this_sample += 32768;
542		if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
543		buffer[buf_count] = clip_analog(this_sample);
544		else // digital I/O pin output is 12 bits
545		{
	580	/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
	581	while (this_sample > 16383) this_sample -= 32768;
	582	while (this_sample < -16384) this_sample += 32768;
	583	if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
	584	buffer[buf_count] = clip_analog(this_sample);
	585	else // digital I/O pin output is 12 bits
	586	{
546	587	#ifdef ALLOW_4_LSB
547		// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
548		// N taps: ^ = 0x2000;
549		// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
550		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
	588	// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
	589	// N taps: ^ = 0x2000;
	590	// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
	591	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
551	592	#else
552		this_sample &= ~0xF;
553		// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
554		// N taps: ^^ ^^^ = 0x3E00;
555		// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
556		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
	593	this_sample &= ~0xF;
	594	// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
	595	// N taps: ^^ ^^^ = 0x3E00;
	596	// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
	597	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
557	598	#endif
558		}
559		// Update all counts
	599	}
	600	// Update all counts
560	601
561		m_subcycle++;
562		if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
	602	m_subcycle++;
	603	if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
	604	{
	605	/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
	606	* if INHIBIT was true during the most recent frame transition.
	607	* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
	608	* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
	609	* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
	610	* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
	611	* convenient and should make no difference in output.
	612	*/
	613	if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_zero = 1;
	614	if ((m_IP == 0)&&(m_pitch_zero==1)) m_pitch_zero = 0;
	615	#ifdef PERFECT_INTERPOLATION_HACK
	616	m_old_zpar = m_zpar;
	617	#endif
	618	m_zpar = 0; /* this gets effectively reset by resetf3, same signal which resets m_PC to 0 */
	619	if (m_IP == 7) // RESETL4
563	620	{
564		/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
565		* if INHIBIT was true during the most recent frame transition.
566		* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
567		* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
568		* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
569		* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
570		* convenient and should make no difference in output.
571		*/
572		if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_zero = 1;
573		if ((m_IP == 0)&&(m_pitch_zero==1)) m_pitch_zero = 0;
574		if (m_IP == 7) // RESETL4
575		{
576		// Latch OLDE and OLDP
577		OLD_FRAME_SILENCE_FLAG = NEW_FRAME_SILENCE_FLAG; // m_OLDE
578		OLD_FRAME_UNVOICED_FLAG = NEW_FRAME_UNVOICED_FLAG; // m_OLDP
579		/* if TALK was clear last frame, halt speech now, since TALKD (latched from TALK on new frame) just went inactive. */
	621	/* if TALK was clear last frame, halt speech now, since TALKD (latched from TALK on new frame) just went inactive. */
580	622	#ifdef DEBUG_GENERATION
581		if (m_TALK == 0)
582		fprintf(stderr,"tms5110_process: processing frame: TALKD = 0 caused by stop frame or buffer empty, halting speech.\n");
	623	if (m_TALK == 0)
	624	fprintf(stderr,"tms5110_process: processing frame: TALKD = 0 caused by stop frame or buffer empty, halting speech.\n");
583	625	#endif
584		m_TALKD = m_TALK; // TALKD is latched from TALK
585		m_TALK = m_SPEN; // TALK is latched from SPEN
586		}
587		m_subcycle = m_subc_reload;
588		m_PC = 0;
589		m_IP++;
590		m_IP&=0x7;
	626	m_TALKD = m_TALK; // TALKD is latched from TALK
	627	m_TALK = m_SPEN; // TALK is latched from SPEN
591	628	}
592		else if (m_subcycle == 3)
593		{
594		m_subcycle = m_subc_reload;
595		m_PC++;
596		}
597		m_pitch_count++;
598		if ((m_pitch_count >= m_current_pitch)\|\|(m_pitch_zero == 1)) m_pitch_count = 0;
599		m_pitch_count &= 0x1FF;
	629	m_subcycle = m_subc_reload;
	630	m_PC = 0;
	631	m_IP++;
	632	m_IP&=0x7;
600	633	}
601		else // m_~~TALKD~~ == 0
	634	else if (m_subcycle == 3)
602	635	{
603		m_subcycle++;
604		if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
	636	m_subcycle = m_subc_reload;
	637	m_PC++;
	638	}
	639	m_pitch_count++;
	640	if ((m_pitch_count >= m_current_pitch)\|\|(m_pitch_zero == 1)) m_pitch_count = 0;
	641	m_pitch_count &= 0x1FF;
	642	buf_count++;
	643	size--;
	644	}
	645
	646	empty:
	647
	648	while (size > 0)
	649	{
	650	m_subcycle++;
	651	if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
	652	{
	653	if (m_IP == 7) // RESETL4
605	654	{
606		if (m_IP == 7) // RESETL4
607		{
608		m_TALKD = m_TALK; // TALKD is latched from TALK
609		m_TALK = m_SPEN; // TALK is latched from SPEN
610		}
611		m_subcycle = m_subc_reload;
612		m_PC = 0;
613		m_IP++;
614		m_IP&=0x7;
	655	m_TALKD = m_TALK; // TALKD is latched from TALK
	656	m_TALK = m_SPEN; // TALK is latched from SPEN
615	657	}
616		else if (m_subcycle == 3)
617		{
618		m_subcycle = m_subc_reload;
619		m_PC++;
620		}
621		buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
	658	m_subcycle = m_subc_reload;
	659	m_PC = 0;
	660	m_IP++;
	661	m_IP&=0x7;
622	662	}
623		buf_count++;
624		size--;
	663	else if (m_subcycle == 3)
	664	{
	665	m_subcycle = m_subc_reload;
	666	m_PC++;
	667	}
	668	buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
	669	buf_count++;
	670	size--;
625	671	}
626	672	}
627	673
r249038	r249039
853	899	m_SPEN = 1; /* start immediately */
854	900	/* clear out variables before speaking */
855	901	m_zpar = 1; // zero all the parameters
856		m_uv_zpar = 1; // zero k4-k10 as well
857		m_OLDE = 1; // 'silence/zpar' frames are zero energy
858		m_OLDP = 1; // 'silence/zpar' frames are zero pitch
859		#ifdef PERFECT_INTERPOLATION_HACK
860		m_old_zpar = 1; // zero all the old parameters
861		m_old_uv_zpar = 1; // zero old k4-k10 as well
862		#endif
863	902	m_subc_reload = 0; // SPKSLOW means this is 0
	903	m_subcycle = m_subc_reload;
	904	m_PC = 0;
	905	m_IP = 0;
864	906	break;
865	907
866	908	case TMS5110_CMD_READ_BIT:
r249038	r249039
874	916	#ifdef DEBUG_COMMAND_DUMP
875	917	fprintf(stderr,"actually reading a bit now\n");
876	918	#endif
	919	request_bits(1);
877	920	m_CTL_buffer >>= 1;
878	921	m_CTL_buffer \|= (extract_bits(1)<<3);
879	922	m_CTL_buffer &= 0xF;
r249038	r249039
888	931	m_SPEN = 1; /* start immediately */
889	932	/* clear out variables before speaking */
890	933	m_zpar = 1; // zero all the parameters
891		m_uv_zpar = 1; // zero k4-k10 as well
892		m_OLDE = 1; // 'silence/zpar' frames are zero energy
893		m_OLDP = 1; // 'silence/zpar' frames are zero pitch
894		#ifdef PERFECT_INTERPOLATION_HACK
895		m_old_zpar = 1; // zero all the old parameters
896		m_old_uv_zpar = 1; // zero old k4-k10 as well
897		#endif
898	934	m_subc_reload = 1; // SPEAK means this is 1
	935	m_subcycle = m_subc_reload;
	936	m_PC = 0;
	937	m_IP = 0;
899	938	break;
900	939
901	940	case TMS5110_CMD_READ_BRANCH:
r249038	r249039
940	979
941	980	void tms5110_device::parse_frame()
942	981	{
943		int i, rep_flag;
	982	int bits, i, rep_flag;
	983	/ TODO: get rid of bits handling here and move into extract_bits (as in tms5220.c) /
	984	/* count the total number of bits available */
	985	bits = m_fifo_count;
944	986
	987	/* attempt to extract the energy index */
	988	bits -= m_coeff->energy_bits;
	989	if (bits < 0)
	990	{
	991	request_bits( -bits ); /* toggle M0 to receive needed bits */
	992	bits = 0;
	993	}
945	994	// attempt to extract the energy index
946	995	m_new_frame_energy_idx = extract_bits(m_coeff->energy_bits);
947	996	#ifdef DEBUG_PARSE_FRAME_DUMP
r249038	r249039
949	998	fprintf(stderr," ");
950	999	#endif
951	1000
	1001	/* if the energy index is 0 or 15, we're done
	1002
	1003	if ((indx == 0) \|\| (indx == 15))
	1004	{
	1005	if (DEBUG_5110) logerror(" (4-bit energy=%d frame)\n",m_new_energy);
	1006
	1007	// clear the k's
	1008	if (indx == 0)
	1009	{
	1010	for (i = 0; i < m_coeff->num_k; i++)
	1011	m_new_k[i] = 0;
	1012	}
	1013
	1014	// clear fifo if stop frame encountered
	1015	if (indx == 15)
	1016	{
	1017	if (DEBUG_5110) logerror(" (4-bit energy=%d STOP frame)\n",m_new_energy);
	1018	m_fifo_head = m_fifo_tail = m_fifo_count = 0;
	1019	}
	1020	return;
	1021	}*/
952	1022	// if the energy index is 0 or 15, we're done
953	1023	if ((m_new_frame_energy_idx == 0) \|\| (m_new_frame_energy_idx == 15))
954	1024	return;
955	1025
	1026
	1027	/* attempt to extract the repeat flag */
	1028	bits -= 1;
	1029	if (bits < 0)
	1030	{
	1031	request_bits( -bits ); /* toggle M0 to receive needed bits */
	1032	bits = 0;
	1033	}
956	1034	rep_flag = extract_bits(1);
957	1035	#ifdef DEBUG_PARSE_FRAME_DUMP
958	1036	printbits(rep_flag, 1);
959	1037	fprintf(stderr," ");
960	1038	#endif
961	1039
	1040	/* attempt to extract the pitch */
	1041	bits -= m_coeff->pitch_bits;
	1042	if (bits < 0)
	1043	{
	1044	request_bits( -bits ); /* toggle M0 to receive needed bits */
	1045	bits = 0;
	1046	}
962	1047	m_new_frame_pitch_idx = extract_bits(m_coeff->pitch_bits);
963	1048	#ifdef DEBUG_PARSE_FRAME_DUMP
964	1049	printbits(m_new_frame_pitch_idx,m_coeff->pitch_bits);
r249038	r249039
971	1056	// extract first 4 K coefficients
972	1057	for (i = 0; i < 4; i++)
973	1058	{
	1059	/* attempt to extract 4 K's */
	1060	bits -= m_coeff->kbits[i];
	1061	if (bits < 0)
	1062	{
	1063	request_bits( -bits ); /* toggle M0 to receive needed bits */
	1064	bits = 0;
	1065	}
974	1066	m_new_frame_k_idx[i] = extract_bits(m_coeff->kbits[i]);
975	1067	#ifdef DEBUG_PARSE_FRAME_DUMP
976	1068	printbits(m_new_frame_k_idx[i],m_coeff->kbits[i]);
r249038	r249039
988	1080	// If we got here, we need the remaining 6 K's
989	1081	for (i = 4; i < m_coeff->num_k; i++)
990	1082	{
	1083	bits -= m_coeff->kbits[i];
	1084	if (bits < 0)
	1085	{
	1086	request_bits( -bits ); /* toggle M0 to receive needed bits */
	1087	bits = 0;
	1088	}
991	1089	m_new_frame_k_idx[i] = extract_bits(m_coeff->kbits[i]);
992	1090	#ifdef DEBUG_PARSE_FRAME_DUMP
993	1091	printbits(m_new_frame_k_idx[i],m_coeff->kbits[i]);
994	1092	fprintf(stderr," ");
995	1093	#endif
996	1094	}
997		#ifdef DEBUG_PARSE_FRAME_DUMP
998		fprintf(stderr,"\n");
999		#endif
1000	1095	#ifdef VERBOSE
	1096	if (m_speak_external)
	1097	logerror("Parsed a frame successfully in FIFO - %d bits remaining\n", (m_fifo_count*8)-(m_fifo_bits_taken));
	1098	else
1001	1099	logerror("Parsed a frame successfully in ROM\n");
1002	1100	#endif
1003	1101	return;
r249038	r249039
1141	1239	void tms5110_device::device_reset()
1142	1240	{
1143	1241	m_digital_select = FORCE_DIGITAL; // assume analog output
	1242	/* initialize the FIFO */
	1243	memset(m_fifo, 0, sizeof(m_fifo));
	1244	m_fifo_head = m_fifo_tail = m_fifo_count = 0;
1144	1245
1145	1246	/* initialize the chip state */
1146	1247	m_SPEN = m_TALK = m_TALKD = 0;
r249038	r249039
1153	1254	#ifdef PERFECT_INTERPOLATION_HACK
1154	1255	m_old_frame_energy_idx = m_old_frame_pitch_idx = 0;
1155	1256	memset(m_old_frame_k_idx, 0, sizeof(m_old_frame_k_idx));
1156		m_old_zpar = ~~m_old_uv_zpar =~~ 0;
	1257	m_old_zpar = 0;
1157	1258	#endif
1158	1259	m_new_frame_energy_idx = m_current_energy = m_previous_energy = 0;
1159	1260	m_new_frame_pitch_idx = m_current_pitch = 0;
r249038	r249039
1290	1391	}
1291	1392
1292	1393
	1394
1293	1395	/******************************************************************************
1294	1396
	1397	tms5110_ready_r -- return the not ready status from the sound chip
	1398
	1399	******************************************************************************/
	1400
	1401	int tms5110_device::ready_r()
	1402	{
	1403	/* bring up to date first */
	1404	m_stream->update();
	1405	return (m_fifo_count < FIFO_SIZE-1);
	1406	}
	1407
	1408
	1409
	1410	/******************************************************************************
	1411
1295	1412	tms5110_update -- update the sound chip so that it is in sync with CPU execution
1296	1413
1297	1414	******************************************************************************/

trunk/src/emu/sound/tms5110.h
r249038	r249039
7	7
8	8	#include "emu.h"
9	9
10		/* HACK: if defined, uses impossibly perfect 'straight line' interpolation */
11		#undef PERFECT_INTERPOLATION_HACK
	10	#define FIFO_SIZE 64 // TODO: technically the tms51xx chips don't have a fifo at all
12	11
13	12	/* TMS5110 commands */
14	13	/* CTL8 CTL4 CTL2 CTL1 \| PDC's */
r249038	r249039
16	15	#define TMS5110_CMD_RESET (0) /* 0 0 0 x \| 1 */
17	16	#define TMS5110_CMD_LOAD_ADDRESS (2) /* 0 0 1 x \| 2 */
18	17	#define TMS5110_CMD_OUTPUT (4) /* 0 1 0 x \| 3 */
19		#define TMS5110_CMD_SPKSLOW (6) /* 0 1 1 x \| 1 \| Note: this command is undocumented on the datasheets, it only appears on the patents. It might not actually work properly on some of the real chips as manufactured. Acts the same as CMD_SPEAK, but makes the interpolator take t~~hree~~ A cycles whereever it would normally only take one, effectively making speech of any given word take twice as long as normal. */
	18	#define TMS5110_CMD_SPKSLOW (6) /* 0 1 1 x \| 1 \| Note: this command is undocumented on the datasheets, it only appears on the patents. It might not actually work properly on some of the real chips as manufactured. Acts the same as CMD_SPEAK, but makes the interpolator take two A cycles whereever it would normally only take one, effectively making speech of any given word take about twice as long as normal. */
20	19	#define TMS5110_CMD_READ_BIT (8) /* 1 0 0 x \| 1 */
21	20	#define TMS5110_CMD_SPEAK (10) /* 1 0 1 x \| 1 */
22	21	#define TMS5110_CMD_READ_BRANCH (12) /* 1 1 0 x \| 1 */
r249038	r249039
65	64	*/
66	65	DECLARE_READ8_MEMBER( romclk_hack_r );
67	66
	67	int ready_r();
68	68	void set_frequency(int frequency);
69	69
70	70	int _speech_rom_read_bit();
r249038	r249039
93	93	void new_int_write_addr(UINT8 addr);
94	94	UINT8 new_int_read();
95	95	void register_for_save_states();
	96	void FIFO_data_write(int data);
96	97	int extract_bits(int count);
	98	void request_bits(int no);
97	99	void perform_dummy_read();
98	100	INT32 lattice_filter();
99	101	void process(INT16 *buffer, unsigned int size);
r249038	r249039
107	109	/* coefficient tables */
108	110	const struct tms5100_coeffs *m_coeff;
109	111
	112	/* these contain data that describes the 4 bit "FIFO" */
	113	UINT8 m_fifo[FIFO_SIZE];
	114	UINT8 m_fifo_head;
	115	UINT8 m_fifo_tail;
	116	UINT8 m_fifo_count;
	117
110	118	/* these contain global status bits */
111	119	UINT8 m_PDC;
112	120	UINT8 m_CTL_pins;
r249038	r249039
154	162	UINT8 m_old_frame_pitch_idx;
155	163	UINT8 m_old_frame_k_idx[10];
156	164	UINT8 m_old_zpar;
157		UINT8 m_old_uv_zpar;
158	165
159	166	INT32 m_current_energy;
160	167	INT32 m_current_pitch;

trunk/src/emu/sound/tms5220.c
r249038	r249039
271	271	* or clip logic, even though the real hardware doesn't do this, partially verified by decap */
272	272	#undef ALLOW_4_LSB
273	273
274		/* forces m_TALK active instantly whenever m_SPEN would be activated, causing speech delay to be reduced by up to one frame time */
275		/* for some reason, this hack makes victory behave better, though it does not match the patent */
276		#define FAST_START_HACK 1
277	274
278
279	275	/* ***configuration of chip connection stuff*** */
280	276	/* must be defined; if 0, output the waveform as if it was tapped on the speaker pin as usual, if 1, output the waveform as if it was tapped on the i/o pin (volume is much lower in the latter case) */
281	277	#define FORCE_DIGITAL 0
r249038	r249039
365	361	save_item(NAME(m_fifo_count));
366	362	save_item(NAME(m_fifo_bits_taken));
367	363
368		save_item(NAME(m_previous_TALK_STATUS));
369		save_item(NAME(m_SPEN));
370		save_item(NAME(m_DDIS));
371		save_item(NAME(m_TALK));
372		save_item(NAME(m_TALKD));
	364	save_item(NAME(m_speaking_now));
	365	save_item(NAME(m_speak_external));
	366	save_item(NAME(m_talk_status));
373	367	save_item(NAME(m_buffer_low));
374	368	save_item(NAME(m_buffer_empty));
375	369	save_item(NAME(m_irq_pin));
r249038	r249039
390	384	save_item(NAME(m_current_pitch));
391	385	save_item(NAME(m_current_k));
392	386
	387	save_item(NAME(m_target_energy));
	388	save_item(NAME(m_target_pitch));
	389	save_item(NAME(m_target_k));
	390
393	391	save_item(NAME(m_previous_energy));
394	392
395	393	save_item(NAME(m_subcycle));
r249038	r249039
397	395	save_item(NAME(m_PC));
398	396	save_item(NAME(m_IP));
399	397	save_item(NAME(m_inhibit));
400		save_item(NAME(m_uv_zpar));
401		save_item(NAME(m_zpar));
402		save_item(NAME(m_pitch_zero));
403	398	save_item(NAME(m_c_variant_rate));
404	399	save_item(NAME(m_pitch_count));
405	400
r249038	r249039
470	465
471	466	void tms5220_device::data_write(int data)
472	467	{
473		int old_buffer_low = m_buffer_low;
474	468	#ifdef DEBUG_DUMP_INPUT_DATA
475	469	fprintf(stdout, "%c",data);
476	470	#endif
477		if (m_~~DDIS~~) // If we're in speak external mode
	471	if (m_speak_external) // If we're in speak external mode
478	472	{
479	473	// add this byte to the FIFO
480	474	if (m_fifo_count < FIFO_SIZE)
r249038	r249039
483	477	m_fifo_tail = (m_fifo_tail + 1) % FIFO_SIZE;
484	478	m_fifo_count++;
485	479	#ifdef DEBUG_FIFO
486		~~fprintf(std~~err,"data_write: Added byte to FIFO (current count=%2d)\n", m_fifo_count);
	480	logerror("data_write: Added byte to FIFO (current count=%2d)\n", m_fifo_count);
487	481	#endif
488	482	update_fifo_status_and_ints();
489		// if we just unset buffer low with that last write, and SPEN was zero (see circuit 251, sheet 12)
490		if ((m_SPEN == 0) && ((old_buffer_low == 1) && (m_buffer_low == 0))) // MUST HAVE EDGE DETECT
	483	if ((m_talk_status == 0) && (m_buffer_low == 0)) // we just unset buffer low with that last write, and talk status was zero...
491	484	{
492		int i;
	485	int i;
493	486	#ifdef DEBUG_FIFO
494		~~fprintf(std~~err,"data_write triggered ~~SPEN~~ to go active!\n");
	487	logerror("data_write triggered talk status to go active!\n");
495	488	#endif
496		// ...then we now have enough bytes to start talking; set zpar and clear out the new frame parameters (it will become old frame just before the first call to parse_frame() )
497		m_zpar = 1;
498		m_uv_zpar = 1; // zero k4-k10 as well
499		m_OLDE = 1; // 'silence/zpar' frames are zero energy
500		m_OLDP = 1; // 'silence/zpar' frames are zero pitch
501		#ifdef PERFECT_INTERPOLATION_HACK
502		m_old_zpar = 1; // zero all the old parameters
503		m_old_uv_zpar = 1; // zero old k4-k10 as well
504		#endif
505		m_SPEN = 1;
506		#ifdef FAST_START_HACK
507		m_TALK = 1;
508		#endif
	489	// ...then we now have enough bytes to start talking; clear out the new frame parameters (it will become old frame just before the first call to parse_frame() )
	490	// TODO: the 3 lines below (and others) are needed for victory to not fail its selftest due to a sample ending too late, may require additional investigation
	491	m_subcycle = m_subc_reload;
	492	m_PC = 0;
	493	m_IP = reload_table[m_c_variant_rate&0x3]; // is this correct? should this be always 7 instead, so that the new frame is loaded quickly?
509	494	m_new_frame_energy_idx = 0;
510	495	m_new_frame_pitch_idx = 0;
511	496	for (i = 0; i < 4; i++)
r249038	r249039
514	499	m_new_frame_k_idx[i] = 0xF;
515	500	for (i = 7; i < m_coeff->num_k; i++)
516	501	m_new_frame_k_idx[i] = 0x7;
517
	502	m_talk_status = m_speaking_now = 1;
518	503	}
519	504	}
520	505	else
521	506	{
522	507	#ifdef DEBUG_FIFO
523		~~fprintf(std~~err,"data_write: Ran out of room in the tms52xx FIFO! this should never happen!\n");
	508	logerror("data_write: Ran out of room in the tms52xx FIFO! this should never happen!\n");
524	509	// at this point, /READY should remain HIGH/inactive until the fifo has at least one byte open in it.
525	510	#endif
526	511	}
527	512
528	513
529	514	}
530		else //(! m_~~DDIS~~)
	515	else //(! m_speak_external)
531	516	// R Nabet : we parse commands at once. It is necessary for such commands as read.
532	517	process_command(data);
533	518	}
r249038	r249039
575	560	m_buffer_low = 0;
576	561
577	562	/* BE is set if neither byte 15 nor 14 of the fifo are in use; this
578		translates to having fifo_count equal to exactly 0
579		*/
	563	translates to having fifo_count equal to exactly 0 */
580	564	if (m_fifo_count == 0)
581	565	{
582	566	// generate an interrupt if necessary; if /BE was inactive and is now active, set int.
583	567	if (!m_buffer_empty)
584	568	set_interrupt_state(1);
585	569	m_buffer_empty = 1;
586		m_TALK = m_SPEN = 0; // /BE being active clears the TALK(TCON) status which in turn clears SPEN
587	570	}
588	571	else
589	572	m_buffer_empty = 0;
590	573
591		// generate an interrupt if /TS was active, and is now inactive.
592		// also, in this case, regardless if DDIS was set, unset it.
593		if (m_previous_TALK_STATUS == 1 && (TALK_STATUS == 0))
	574	/* TS is talk status and is set elsewhere in the fifo parser and in
	575	the SPEAK command handler; however, if /BE is true during speak external
	576	mode, it is immediately unset here. */
	577	if ((m_speak_external == 1) && (m_buffer_empty == 1))
594	578	{
595		#ifdef VERBOSE
596		fprintf(stderr,"Talk status WAS 1, is now 0, unsetting DDIS and firing an interrupt!\n");
597		#endif
598		set_interrupt_state(1);
599		m_DDIS = 0;
	579	// generate an interrupt: /TS was active, and is now inactive.
	580	if (m_talk_status == 1)
	581	{
	582	m_talk_status = m_speak_external = 0;
	583	set_interrupt_state(1);
	584	}
600	585	}
601		m_previous_TALK_STATUS = TALK_STATUS;
602
	586	/* Note that TS being unset will also generate an interrupt when a STOP
	587	frame is encountered; this is handled in the sample generator code and not here */
603	588	}
604	589
605	590	/**********************************************************************************************
r249038	r249039
612	597	{
613	598	int val = 0;
614	599
615		if (m_~~DDIS~~)
	600	if (m_speak_external)
616	601	{
617	602	// extract from FIFO
618	603	while (count--)
r249038	r249039
658	643	/* clear the interrupt pin on status read */
659	644	set_interrupt_state(0);
660	645	#ifdef DEBUG_PIN_READS
661		~~fprintf(std~~err,"Status read: TS=%d BL=%d BE=%d\n", ~~TALK~~_~~STATUS~~, m_buffer_low, m_buffer_empty);
	646	logerror("Status read: TS=%d BL=%d BE=%d\n", m_talk_status, m_buffer_low, m_buffer_empty);
662	647	#endif
663	648
664		return (~~TALK~~_~~STATUS~~ << 7) \| (m_buffer_low << 6) \| (m_buffer_empty << 5);
	649	return (m_talk_status << 7) \| (m_buffer_low << 6) \| (m_buffer_empty << 5);
665	650	}
666	651	}
667	652
r249038	r249039
675	660	int tms5220_device::ready_read()
676	661	{
677	662	#ifdef DEBUG_PIN_READS
678		~~fprintf(std~~err,"ready_read: ready pin read, io_ready is %d, fifo count is %d~~, DDIS(speak external) is %d~~\n", m_io_ready, m_fifo_count~~, m_DDIS~~);
	663	logerror("ready_read: ready pin read, io_ready is %d, fifo count is %d\n", m_io_ready, m_fifo_count);
679	664	#endif
680		return ((m_fifo_count < FIFO_SIZE)\|\|(!m_~~DDIS~~)) && m_io_ready;
	665	return ((m_fifo_count < FIFO_SIZE)\|\|(!m_speak_external)) && m_io_ready;
681	666	}
682	667
683	668
r249038	r249039
733	718	int tms5220_device::int_read()
734	719	{
735	720	#ifdef DEBUG_PIN_READS
736		~~fprintf(std~~err,"int_read: irq pin read, state is %d\n", m_irq_pin);
	721	logerror("int_read: irq pin read, state is %d\n", m_irq_pin);
737	722	#endif
738	723	return m_irq_pin;
739	724	}
r249038	r249039
748	733	void tms5220_device::process(INT16 *buffer, unsigned int size)
749	734	{
750	735	int buf_count=0;
751		int i, bitout;
	736	int i, bitout, zpar;
752	737	INT32 this_sample;
753	738
754		#ifdef VERBOSE
755		fprintf(stderr,"process called with size of %d; IP=%d, PC=%d, subcycle=%d, m_SPEN=%d, m_TALK=%d, m_TALKD=%d\n", size, m_IP, m_PC, m_subcycle, m_SPEN, m_TALK, m_TALKD);
756		#endif
	739	/* the following gotos are probably safe to remove */
	740	/* if we're empty and still not speaking, fill with nothingness */
	741	if (!m_speaking_now)
	742	goto empty;
757	743
	744	/* if speak external is set, but talk status is not (yet) set,
	745	wait for buffer low to clear */
	746	if (!m_talk_status && m_speak_external && m_buffer_low)
	747	goto empty;
	748
758	749	/* loop until the buffer is full or we've stopped speaking */
759		while (size > 0)
	750	while ((size > 0) && m_speaking_now)
760	751	{
761		if(m_TALKD) // speaking
	752	/* if it is the appropriate time to update the old energy/pitch indices,
	753	* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
	754	* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
	755	* which happens 4 T-cycles later), we change on the latter.
	756	* The indices are updated here ~12 PCs before the new frame is applied.
	757	*/
	758	/ TODO: the patents 4331836, 4335277, and 4419540 disagree about the timing of this /
	759	if ((m_IP == 0) && (m_PC == 0) && (m_subcycle < 2))
762	760	{
763		/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
764		* (In reality, the frame was really loaded incrementally during the entire IP=0
765		* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
766		*/
767		if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
768		{
769		// HACK for regression testing, be sure to comment out before release!
770		//m_RNG = 0x1234;
771		// end HACK
	761	m_OLDE = (m_new_frame_energy_idx == 0);
	762	m_OLDP = (m_new_frame_pitch_idx == 0);
	763	}
772	764
773		/* appropriately override the interp count if needed; this will be incremented after the frame parse! */
774		m_IP = reload_table[m_c_variant_rate&0x3];
	765	/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
	766	* (In reality, the frame was really loaded incrementally during the entire IP=0
	767	* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
	768	*/
	769	if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
	770	{
	771	// HACK for regression testing, be sure to comment out before release!
	772	//m_RNG = 0x1234;
	773	// end HACK
775	774
	775	/* appropriately override the interp count if needed; this will be incremented after the frame parse! */
	776	m_IP = reload_table[m_c_variant_rate&0x3];
	777
776	778	#ifdef PERFECT_INTERPOLATION_HACK
777		/* remember previous frame energy, pitch, and coefficients */
778		m_old_frame_energy_idx = m_new_frame_energy_idx;
779		m_old_frame_pitch_idx = m_new_frame_pitch_idx;
780		for (i = 0; i < m_coeff->num_k; i++)
781		m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
	779	/* remember previous frame energy, pitch, and coefficients */
	780	m_old_frame_energy_idx = m_new_frame_energy_idx;
	781	m_old_frame_pitch_idx = m_new_frame_pitch_idx;
	782	for (i = 0; i < m_coeff->num_k; i++)
	783	m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
782	784	#endif
783	785
784		/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[] */
785		parse_frame();
	786	/* if the talk status was clear last frame, halt speech now. */
	787	if (m_talk_status == 0)
	788	{
	789	#ifdef DEBUG_GENERATION
	790	fprintf(stderr,"tms5220_process: processing frame: talk status = 0 caused by stop frame or buffer empty, halting speech.\n");
	791	#endif
	792	if (m_speaking_now == 1) // we're done, set all coeffs to idle state but keep going for a bit...
	793	{
	794	/TODO: should index clearing be done here, or elsewhere? /
	795	m_new_frame_energy_idx = 0;
	796	m_new_frame_pitch_idx = 0;
	797	for (i = 0; i < 4; i++)
	798	m_new_frame_k_idx[i] = 0;
	799	for (i = 4; i < 7; i++)
	800	m_new_frame_k_idx[i] = 0xF;
	801	for (i = 7; i < m_coeff->num_k; i++)
	802	m_new_frame_k_idx[i] = 0x7;
	803	m_speaking_now = 2; // wait 8 extra interp periods before shutting down so we can interpolate everything to zero state
	804	}
	805	else // m_speaking_now == 2 // now we're really done.
	806	{
	807	m_speaking_now = 0; // finally halt speech
	808	goto empty;
	809	}
	810	}
786	811
787		// if the new frame is unvoiced (or silenced via ZPAR), be sure to zero out the k5-k10 parameters
788		// NOTE: this is probably the bug the tms5100/tmc0280 has, pre-rev D, I think.
789		// GUESS: Pre-rev D versions start zeroing k5-k10 immediately upon new frame load regardless of interpolation inhibit
790		// I.e. ZPAR = /TALKD \|\| (PC>5&&P=0)
791		// GUESS: D and later versions only start or stop zeroing k5-k10 at the IP7->IP0 transition AFTER the frame
792		// I.e. ZPAR = /TALKD \|\| (PC>5&&OLDP)
793		#ifdef PERFECT_INTERPOLATION_HACK
794		m_old_uv_zpar = m_uv_zpar;
795		m_old_zpar = m_zpar; // unset old zpar on new frame
	812
	813	/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[],
	814	* but only if we're not just about to end speech */
	815	if (m_speaking_now == 1) parse_frame();
	816	#ifdef DEBUG_PARSE_FRAME_DUMP
	817	fprintf(stderr,"\n");
796	818	#endif
797		m_zpar = 0;
798		//m_uv_zpar = (OLD_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: fixed version in tmc0280d/tms5100a/cd280x/tms5110
799		m_uv_zpar = (NEW_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: buggy version in tmc0280/tms5100
800	819
801		/* if the new frame is a stop frame, unset both TALK and SPEN (via TCON). TALKD remains active while the energy is ramping to 0. */
802		if (NEW_FRAME_STOP_FLAG == 1)
	820	/* if the new frame is a stop frame, set an interrupt and set talk status to 0 */
	821	/ TODO: investigate this later! /
	822	if (NEW_FRAME_STOP_FLAG == 1)
803	823	{
804		m_TALK = m_SPEN = 0;
	824	m_talk_status = m_speak_external = 0;
	825	set_interrupt_state(1);
	826	update_fifo_status_and_ints();
805	827	}
806	828
807		/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
808		Interpolation inhibit cases:
809		* Old frame was voiced, new is unvoiced
810		* Old frame was silence/zero energy, new has nonzero energy
811		* Old frame was unvoiced, new is voiced
812		* Old frame was unvoiced, new frame is silence/zero energy (unique to tms52xx)
813		*/
814		if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
815		\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
816		\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0))
817		\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 1)) )
818		m_inhibit = 1;
819		else // normal frame, normal interpolation
820		m_inhibit = 0;
	829	/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
	830	Interpolation inhibit cases:
	831	* Old frame was voiced, new is unvoiced
	832	* Old frame was silence/zero energy, new has nonzero energy
	833	* Old frame was unvoiced, new is voiced
	834	* Old frame was unvoiced, new frame is silence/zero energy (unique to tms52xx)
	835	*/
	836	if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
	837	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
	838	\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0))
	839	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 1)) )
	840	m_inhibit = 1;
	841	else // normal frame, normal interpolation
	842	m_inhibit = 0;
821	843
	844	/* load new frame targets from tables, using parsed indices */
	845	m_target_energy = m_coeff->energytable[m_new_frame_energy_idx];
	846	m_target_pitch = m_coeff->pitchtable[m_new_frame_pitch_idx];
	847	zpar = NEW_FRAME_UNVOICED_FLAG; // find out if parameters k5-k10 should be zeroed
	848	for (i = 0; i < 4; i++)
	849	m_target_k[i] = m_coeff->ktable[i][m_new_frame_k_idx[i]];
	850	for (i = 4; i < m_coeff->num_k; i++)
	851	m_target_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-zpar));
	852
822	853	#ifdef DEBUG_GENERATION
823		/* Debug info for current parsed frame */
824		fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
825		fprintf(stderr,"Processing new frame: ");
826		if (m_inhibit == 0)
827		fprintf(stderr, "Normal Frame\n");
828		else
829		fprintf(stderr,"Interpolation Inhibited\n");
830		fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
831		fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",
832		(m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)),
833		m_new_frame_energy_idx,
834		(m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)),
835		(m_coeff->ktable[0][m_new_frame_k_idx[0]] * (1-m_zpar)),
836		(m_coeff->ktable[1][m_new_frame_k_idx[1]] * (1-m_zpar)),
837		(m_coeff->ktable[2][m_new_frame_k_idx[2]] * (1-m_zpar)),
838		(m_coeff->ktable[3][m_new_frame_k_idx[3]] * (1-m_zpar)),
839		(m_coeff->ktable[4][m_new_frame_k_idx[4]] * (1-m_uv_zpar)),
840		(m_coeff->ktable[5][m_new_frame_k_idx[5]] * (1-m_uv_zpar)),
841		(m_coeff->ktable[6][m_new_frame_k_idx[6]] * (1-m_uv_zpar)),
842		(m_coeff->ktable[7][m_new_frame_k_idx[7]] * (1-m_uv_zpar)),
843		(m_coeff->ktable[8][m_new_frame_k_idx[8]] * (1-m_uv_zpar)),
844		(m_coeff->ktable[9][m_new_frame_k_idx[9]] * (1-m_uv_zpar)) );
	854	/* Debug info for current parsed frame */
	855	fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
	856	fprintf(stderr,"Processing frame: ");
	857	if (m_inhibit == 0)
	858	fprintf(stderr, "Normal Frame\n");
	859	else
	860	fprintf(stderr,"Interpolation Inhibited\n");
	861	fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
	862	fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_target_energy, m_new_frame_energy_idx, m_target_pitch, m_target_k[0], m_target_k[1], m_target_k[2], m_target_k[3], m_target_k[4], m_target_k[5], m_target_k[6], m_target_k[7], m_target_k[8], m_target_k[9]);
845	863	#endif
846	864
847		}
848		else // Not a new frame, just interpolate the existing frame.
	865	/* if TS is now 0, ramp the energy down to 0. Is this really correct to hardware? */
	866	if (m_talk_status == 0)
849	867	{
850		int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
851		#ifdef PERFECT_INTERPOLATION_HACK
852		int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
853		//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
854		int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
855		//fprintf(stderr, "CS: %03d", current_sample);
856		// reset the current energy, pitch, etc to what it was at frame start
857		m_current_energy = (m_coeff->energytable[m_old_frame_energy_idx] * (1-m_old_zpar));
858		m_current_pitch = (m_coeff->pitchtable[m_old_frame_pitch_idx] * (1-m_old_zpar));
859		for (i = 0; i < m_coeff->num_k; i++)
860		m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-((i<4)?m_old_zpar:m_old_uv_zpar)));
861		// now adjust each value to be exactly correct for each of the samples per frame
862		if (m_IP != 0) // if we're still interpolating...
863		{
864		m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
865		m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
866		for (i = 0; i < m_coeff->num_k; i++)
867		m_current_k[i] = (m_current_k[i] + (((m_coeff->ktable[i][m_new_frame_k_idx[i]] - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame)*(1-((i<4)?m_zpar:m_uv_zpar));
868		}
869		else // we're done, play this frame for 1/8 frame.
870		{
871		m_current_energy = (m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar));
872		m_current_pitch = (m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar));
873		for (i = 0; i < m_coeff->num_k; i++)
874		m_current_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar)));
875		}
876		#else
877		//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
878		if (m_subcycle == 2)
879		{
880		switch(m_PC)
881		{
882		case 0: /* PC = 0, B cycle, write updated energy */
883		m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
884		break;
885		case 1: /* PC = 1, B cycle, write updated pitch */
886		m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
887		break;
888		case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
889		/* PC = 2 through 11, B cycle, write updated K1 through K10 */
890		m_current_k[m_PC-2] = (m_current_k[m_PC-2] + (((m_coeff->ktable[m_PC-2][m_new_frame_k_idx[m_PC-2]] - m_current_k[m_PC-2])(1-inhibit_state)) INTERP_SHIFT))(((m_PC-2)>4)?(1-m_uv_zpar):(1-m_zpar));
891		break;
892		case 12: /* PC = 12 */
893		/* we should NEVER reach this point, PC=12 doesn't have a subcycle 2 */
894		break;
895		}
896		}
	868	#ifdef DEBUG_GENERATION
	869	fprintf(stderr,"Talk status is 0, forcing target energy to 0\n");
897	870	#endif
	871	m_target_energy = 0;
898	872	}
	873	}
	874	else // Not a new frame, just interpolate the existing frame.
	875	{
	876	int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
	877	#ifdef PERFECT_INTERPOLATION_HACK
	878	int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
	879	//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
	880	int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
899	881
900		// calculate the output
901		if (OLD_FRAME_UNVOICED_FLAG == 1)
	882	zpar = OLD_FRAME_UNVOICED_FLAG;
	883	//fprintf(stderr, "CS: %03d", current_sample);
	884	// reset the current energy, pitch, etc to what it was at frame start
	885	m_current_energy = m_coeff->energytable[m_old_frame_energy_idx];
	886	m_current_pitch = m_coeff->pitchtable[m_old_frame_pitch_idx];
	887	for (i = 0; i < 4; i++)
	888	m_current_k[i] = m_coeff->ktable[i][m_old_frame_k_idx[i]];
	889	for (i = 4; i < m_coeff->num_k; i++)
	890	m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-zpar));
	891	// now adjust each value to be exactly correct for each of the samples per frame
	892	if (m_IP != 0) // if we're still interpolating...
902	893	{
903		// generate unvoiced samples here
904		if (m_RNG & 1)
905		m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
906		else
907		m_excitation_data = 0x40;
	894	m_current_energy += (((m_target_energy - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame;
	895	m_current_pitch += (((m_target_pitch - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame;
	896	for (i = 0; i < m_coeff->num_k; i++)
	897	m_current_k[i] += (((m_target_k[i] - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame;
908	898	}
909		else /* ~~(OLD_FRAME_UNVOICED_FLAG~~ == 0) */
	899	else // we're done, play this frame for 1/8 frame.
910	900	{
911		// generate voiced samples here
912		/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
913		* function has a chirp/peak and then a long chain of zeroes.
914		* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
915		* and if the address reaches that point the ADDRESS incrementer is
916		* disabled, forcing all samples beyond 51d to be == 51d
917		*/
918		if (m_pitch_count >= 51)
919		m_excitation_data = (INT8)m_coeff->chirptable[51];
920		else /m_pitch_count < 51/
921		m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
	901	m_current_energy = m_target_energy;
	902	m_current_pitch = m_target_pitch;
	903	for (i = 0; i < m_coeff->num_k; i++)
	904	m_current_k[i] = m_target_k[i];
922	905	}
923
924		// Update LFSR 20 times every sample (once per T cycle), like patent shows
925		for (i=0; i<20; i++)
	906	#else
	907	//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
	908	if (m_subcycle == 2)
926	909	{
927		bitout = ((m_RNG >> 12) & 1) ^
928		((m_RNG >> 3) & 1) ^
929		((m_RNG >> 2) & 1) ^
930		((m_RNG >> 0) & 1);
931		m_RNG <<= 1;
932		m_RNG \|= bitout;
	910	switch(m_PC)
	911	{
	912	case 0: /* PC = 0, B cycle, write updated energy */
	913	m_current_energy += (((m_target_energy - m_current_energy)*(1-inhibit_state)) INTERP_SHIFT);
	914	break;
	915	case 1: /* PC = 1, B cycle, write updated pitch */
	916	m_current_pitch += (((m_target_pitch - m_current_pitch)*(1-inhibit_state)) INTERP_SHIFT);
	917	break;
	918	case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
	919	/* PC = 2 through 11, B cycle, write updated K1 through K10 */
	920	m_current_k[m_PC-2] += (((m_target_k[m_PC-2] - m_current_k[m_PC-2])*(1-inhibit_state)) INTERP_SHIFT);
	921	break;
	922	case 12: /* PC = 12, do nothing */
	923	break;
	924	}
933	925	}
934		this_sample = lattice_filter(); /* execute lattice filter */
	926	#endif
	927	}
	928
	929	// calculate the output
	930	if (OLD_FRAME_UNVOICED_FLAG == 1)
	931	{
	932	// generate unvoiced samples here
	933	if (m_RNG & 1)
	934	m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
	935	else
	936	m_excitation_data = 0x40;
	937	}
	938	else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
	939	{
	940	// generate voiced samples here
	941	/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
	942	* function has a chirp/peak and then a long chain of zeroes.
	943	* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
	944	* and if the address reaches that point the ADDRESS incrementer is
	945	* disabled, forcing all samples beyond 51d to be == 51d
	946	*/
	947	if (m_pitch_count >= 51)
	948	m_excitation_data = (INT8)m_coeff->chirptable[51];
	949	else /m_pitch_count < 51/
	950	m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
	951	}
	952
	953	// Update LFSR 20 times every sample (once per T cycle), like patent shows
	954	for (i=0; i<20; i++)
	955	{
	956	bitout = ((m_RNG >> 12) & 1) ^
	957	((m_RNG >> 3) & 1) ^
	958	((m_RNG >> 2) & 1) ^
	959	((m_RNG >> 0) & 1);
	960	m_RNG <<= 1;
	961	m_RNG \|= bitout;
	962	}
	963	this_sample = lattice_filter(); /* execute lattice filter */
935	964	#ifdef DEBUG_GENERATION_VERBOSE
936		//fprintf(stderr,"C:%01d; ",m_subcycle);
937		fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
938		//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
939		for (i=0; i<10; i++)
940		fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
941		fprintf(stderr,"Out:%06d ", this_sample);
942		//#ifdef PERFECT_INTERPOLATION_HACK
943		// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
944		//#else
945		// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
946		//#endif
947		fprintf(stderr,"\n");
	965	//fprintf(stderr,"C:%01d; ",m_subcycle);
	966	fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	967	//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	968	for (i=0; i<10; i++)
	969	fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
	970	fprintf(stderr,"Out:%06d", this_sample);
	971	fprintf(stderr,"\n");
948	972	#endif
949		/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
950		while (this_sample > 16383) this_sample -= 32768;
951		while (this_sample < -16384) this_sample += 32768;
952		if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
953		buffer[buf_count] = clip_analog(this_sample);
954		else // digital I/O pin output is 12 bits
955		{
	973	/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
	974	while (this_sample > 16383) this_sample -= 32768;
	975	while (this_sample < -16384) this_sample += 32768;
	976	if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
	977	buffer[buf_count] = clip_analog(this_sample);
	978	else // digital I/O pin output is 12 bits
	979	{
956	980	#ifdef ALLOW_4_LSB
957		// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
958		// N taps: ^ = 0x2000;
959		// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
960		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
	981	// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
	982	// N taps: ^ = 0x2000;
	983	// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
	984	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
961	985	#else
962		this_sample &= ~0xF;
963		// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
964		// N taps: ^^ ^^^ = 0x3E00;
965		// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
966		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
	986	this_sample &= ~0xF;
	987	// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
	988	// N taps: ^^ ^^^ = 0x3E00;
	989	// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
	990	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
967	991	#endif
968		}
969		// Update all counts
	992	}
	993	// Update all counts
970	994
971		m_subcycle++;
972		if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
973		{
974		/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
975		* if INHIBIT was true during the most recent frame transition.
976		* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
977		* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
978		* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
979		* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
980		* convenient and should make no difference in output.
981		*/
982		if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_zero = 1;
983		if ((m_IP == 0)&&(m_pitch_zero==1)) m_pitch_zero = 0;
984		if (m_IP == 7) // RESETL4
985		{
986		// Latch OLDE and OLDP
987		OLD_FRAME_SILENCE_FLAG = NEW_FRAME_SILENCE_FLAG; // m_OLDE
988		OLD_FRAME_UNVOICED_FLAG = NEW_FRAME_UNVOICED_FLAG; // m_OLDP
989		/* if TALK was clear last frame, halt speech now, since TALKD (latched from TALK on new frame) just went inactive. */
990		#ifdef DEBUG_GENERATION
991		fprintf(stderr,"RESETL4, about to update status: IP=%d, PC=%d, subcycle=%d, m_SPEN=%d, m_TALK=%d, m_TALKD=%d\n", m_IP, m_PC, m_subcycle, m_SPEN, m_TALK, m_TALKD);
992		#endif
993		#ifdef DEBUG_GENERATION
994		if (m_TALK == 0)
995		fprintf(stderr,"tms5220_process: processing frame: TALKD = 0 caused by stop frame or buffer empty, halting speech.\n");
996		#endif
997		m_TALKD = m_TALK; // TALKD is latched from TALK
998		update_fifo_status_and_ints(); // to trigger an interrupt if TALK_STATUS is now inactive
999		m_TALK = m_SPEN; // TALK is latched from SPEN
1000		#ifdef DEBUG_GENERATION
1001		fprintf(stderr,"RESETL4, status updated: IP=%d, PC=%d, subcycle=%d, m_SPEN=%d, m_TALK=%d, m_TALKD=%d\n", m_IP, m_PC, m_subcycle, m_SPEN, m_TALK, m_TALKD);
1002		#endif
1003		}
1004		m_subcycle = m_subc_reload;
1005		m_PC = 0;
1006		m_IP++;
1007		m_IP&=0x7;
1008		}
1009		else if (m_subcycle == 3)
1010		{
1011		m_subcycle = m_subc_reload;
1012		m_PC++;
1013		}
1014		m_pitch_count++;
1015		if ((m_pitch_count >= m_current_pitch)\|\|(m_pitch_zero == 1)) m_pitch_count = 0;
1016		m_pitch_count &= 0x1FF;
	995	m_subcycle++;
	996	if ((m_subcycle == 2) && (m_PC == 12))
	997	{
	998	/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
	999	* if INHIBIT was true during the most recent frame transition.
	1000	* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
	1001	* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
	1002	* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
	1003	* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
	1004	* convenient and should make no difference in output.
	1005	*/
	1006	if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_count = 0;
	1007	m_subcycle = m_subc_reload;
	1008	m_PC = 0;
	1009	m_IP++;
	1010	m_IP&=0x7;
1017	1011	}
1018		else // m_~~TALKD~~ == 0
	1012	else if (m_subcycle == 3)
1019	1013	{
1020		m_subcycle++;
1021		if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
1022		{
1023		if (m_IP == 7) // RESETL4
1024		{
1025		m_TALKD = m_TALK; // TALKD is latched from TALK
1026		m_TALK = m_SPEN; // TALK is latched from SPEN
1027		}
1028		m_subcycle = m_subc_reload;
1029		m_PC = 0;
1030		m_IP++;
1031		m_IP&=0x7;
1032		}
1033		else if (m_subcycle == 3)
1034		{
1035		m_subcycle = m_subc_reload;
1036		m_PC++;
1037		}
1038		buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
	1014	m_subcycle = m_subc_reload;
	1015	m_PC++;
1039	1016	}
1040		buf_count++;
1041		size--;
	1017	m_pitch_count++;
	1018	if (m_pitch_count >= m_current_pitch) m_pitch_count = 0;
	1019	m_pitch_count &= 0x1FF;
	1020	buf_count++;
	1021	size--;
1042	1022	}
	1023
	1024	empty:
	1025
	1026	while (size > 0)
	1027	{
	1028	m_subcycle++;
	1029	if ((m_subcycle == 2) && (m_PC == 12))
	1030	{
	1031	m_subcycle = m_subc_reload;
	1032	m_PC = 0;
	1033	m_IP++;
	1034	m_IP&=0x7;
	1035	}
	1036	else if (m_subcycle == 3)
	1037	{
	1038	m_subcycle = m_subc_reload;
	1039	m_PC++;
	1040	}
	1041	buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
	1042	buf_count++;
	1043	size--;
	1044	}
1043	1045	}
1044	1046
1045	1047	/**********************************************************************************************
r249038	r249039
1180	1182
1181	1183	void tms5220_device::process_command(unsigned char cmd)
1182	1184	{
1183		int i;
1184	1185	#ifdef DEBUG_COMMAND_DUMP
1185	1186	fprintf(stderr,"process_command called with parameter %02X\n",cmd);
1186	1187	#endif
r249038	r249039
1188	1189	switch (cmd & 0x70)
1189	1190	{
1190	1191	case 0x10 : /* read byte */
1191		if (~~TALK~~_~~STATUS~~ == 0) /* TALKST must be clear for RDBY */
	1192	if (m_talk_status == 0) /* TALKST must be clear for RDBY */
1192	1193	{
1193	1194	if (m_schedule_dummy_read)
1194	1195	{
r249038	r249039
1210	1211	break;
1211	1212
1212	1213	case 0x30 : /* read and branch */
1213		if (~~TALK~~_~~STATUS~~ == 0) /* TALKST must be clear for RB */
	1214	if (m_talk_status == 0) /* TALKST must be clear for RB */
1214	1215	{
1215	1216	#ifdef VERBOSE
1216		~~fprintf(std~~err,"read and branch command received\n");
	1217	logerror("read and branch command received\n");
1217	1218	#endif
1218	1219	m_RDB_flag = FALSE;
1219	1220	if (m_speechrom)
r249038	r249039
1222	1223	break;
1223	1224
1224	1225	case 0x40 : /* load address */
1225		if (~~TALK~~_~~STATUS~~ == 0) /* TALKST must be clear for LA */
	1226	if (m_talk_status == 0) /* TALKST must be clear for LA */
1226	1227	{
1227	1228	/* tms5220 data sheet says that if we load only one 4-bit nibble, it won't work.
1228	1229	This code does not care about this. */
r249038	r249039
1239	1240	if (m_speechrom)
1240	1241	m_speechrom->read(1);
1241	1242	}
1242		m_SPEN = 1;
1243		#ifdef FAST_START_HACK
1244		m_TALK = 1;
1245		#endif
1246		m_DDIS = 0;
1247		m_zpar = 1; // zero all the parameters
1248		m_uv_zpar = 1; // zero k4-k10 as well
1249		m_OLDE = 1; // 'silence/zpar' frames are zero energy
1250		m_OLDP = 1; // 'silence/zpar' frames are zero pitch
1251		#ifdef PERFECT_INTERPOLATION_HACK
1252		m_old_zpar = 1; // zero all the old parameters
1253		m_old_uv_zpar = 1; // zero old k4-k10 as well
1254		#endif
1255		// following is semi-hack but matches idle state observed on chip
	1243	m_speaking_now = 1;
	1244	m_speak_external = 0;
	1245	m_talk_status = 1; /* start immediately */
	1246	/* clear out variables before speaking */
	1247	// TODO: similar to the victory case described above, but for VSM speech
	1248	m_subcycle = m_subc_reload;
	1249	m_PC = 0;
	1250	m_IP = reload_table[m_c_variant_rate&0x3];
1256	1251	m_new_frame_energy_idx = 0;
1257	1252	m_new_frame_pitch_idx = 0;
	1253	int i;
1258	1254	for (i = 0; i < 4; i++)
1259	1255	m_new_frame_k_idx[i] = 0;
1260	1256	for (i = 4; i < 7; i++)
r249038	r249039
1264	1260	break;
1265	1261
1266	1262	case 0x60 : /* speak external */
1267		// SPKEXT going active activates SPKEE which clears the fifo
	1263	//SPKEXT going active activates SPKEE which clears the fifo
1268	1264	m_fifo_head = m_fifo_tail = m_fifo_count = m_fifo_bits_taken = 0;
1269		// SPEN is enabled when the fifo passes half full (falling edge of BL signal)
1270		m_DDIS = 1;
1271		m_zpar = 1; // zero all the parameters
1272		m_uv_zpar = 1; // zero k4-k10 as well
1273		m_OLDE = 1; // 'silence/zpar' frames are zero energy
1274		m_OLDP = 1; // 'silence/zpar' frames are zero pitch
1275		#ifdef PERFECT_INTERPOLATION_HACK
1276		m_old_zpar = 1; // zero all the old parameters
1277		m_old_uv_zpar = 1; // zero old k4-k10 as well
1278		#endif
1279		// following is semi-hack but matches idle state observed on chip
1280		m_new_frame_energy_idx = 0;
1281		m_new_frame_pitch_idx = 0;
1282		for (i = 0; i < 4; i++)
1283		m_new_frame_k_idx[i] = 0;
1284		for (i = 4; i < 7; i++)
1285		m_new_frame_k_idx[i] = 0xF;
1286		for (i = 7; i < m_coeff->num_k; i++)
1287		m_new_frame_k_idx[i] = 0x7;
	1265	m_speak_external = 1;
1288	1266	m_RDB_flag = FALSE;
1289	1267	break;
1290	1268
r249038	r249039
1330	1308	m_IP = reload_table[m_c_variant_rate&0x3];
1331	1309
1332	1310	update_fifo_status_and_ints();
1333		if (m_~~DDIS && m~~_~~buffer_emp~~ty) goto ranout;
	1311	if (!m_talk_status) goto ranout;
1334	1312
1335	1313	// attempt to extract the energy index
1336	1314	m_new_frame_energy_idx = extract_bits(m_coeff->energy_bits);
r249038	r249039
1339	1317	fprintf(stderr," ");
1340	1318	#endif
1341	1319	update_fifo_status_and_ints();
1342		if (m_~~DDIS && m~~_~~buffer_emp~~ty) goto ranout;
	1320	if (!m_talk_status) goto ranout;
1343	1321	// if the energy index is 0 or 15, we're done
1344	1322	if ((m_new_frame_energy_idx == 0) \|\| (m_new_frame_energy_idx == 15))
1345	1323	return;
r249038	r249039
1359	1337	fprintf(stderr," ");
1360	1338	#endif
1361	1339	update_fifo_status_and_ints();
1362		if (m_~~DDIS && m~~_~~buffer_emp~~ty) goto ranout;
	1340	if (!m_talk_status) goto ranout;
1363	1341	// if this is a repeat frame, just do nothing, it will reuse the old coefficients
1364	1342	if (rep_flag)
1365	1343	return;
r249038	r249039
1373	1351	fprintf(stderr," ");
1374	1352	#endif
1375	1353	update_fifo_status_and_ints();
1376		if (m_~~DDIS && m~~_~~buffer_emp~~ty) goto ranout;
	1354	if (!m_talk_status) goto ranout;
1377	1355	}
1378	1356
1379	1357	// if the pitch index was zero, we only need 4 K's...
r249038	r249039
1392	1370	fprintf(stderr," ");
1393	1371	#endif
1394	1372	update_fifo_status_and_ints();
1395		if (m_~~DDIS && m~~_~~buffer_emp~~ty) goto ranout;
	1373	if (!m_talk_status) goto ranout;
1396	1374	}
1397		#ifdef DEBUG_PARSE_FRAME_DUMP
1398		fprintf(stderr,"\n");
1399		#endif
1400	1375	#ifdef VERBOSE
1401		if (m_DDIS)
1402		fprintf(stderr,"Parsed a frame successfully in FIFO - %d bits remaining\n", (m_fifo_count*8)-(m_fifo_bits_taken));
	1376	if (m_speak_external)
	1377	logerror("Parsed a frame successfully in FIFO - %d bits remaining\n", (m_fifo_count*8)-(m_fifo_bits_taken));
1403	1378	else
1404		~~fprintf(std~~err,"Parsed a frame successfully in ROM\n");
	1379	logerror("Parsed a frame successfully in ROM\n");
1405	1380	#endif
1406	1381	return;
1407	1382
1408	1383	ranout:
1409	1384	#ifdef DEBUG_FRAME_ERRORS
1410		~~fprintf(std~~err,"Ran out of bits on a parse!\n");
	1385	logerror("Ran out of bits on a parse!\n");
1411	1386	#endif
1412	1387	return;
1413	1388	}
r249038	r249039
1422	1397	{
1423	1398	if (!TMS5220_IS_52xx) return; // bail out if not a 52xx chip, since there's no int pin
1424	1399	#ifdef DEBUG_PIN_READS
1425		~~fprintf(std~~err,"irq pin set to state %d\n", state);
	1400	logerror("irq pin set to state %d\n", state);
1426	1401	#endif
1427	1402	if (!m_irq_handler.isnull() && state != m_irq_pin)
1428	1403	m_irq_handler(!state);
r249038	r249039
1439	1414	{
1440	1415	int state = ready_read();
1441	1416	#ifdef DEBUG_PIN_READS
1442		~~fprintf(std~~err,"ready pin set to state %d\n", state);
	1417	logerror("ready pin set to state %d\n", state);
1443	1418	#endif
1444	1419	if (!m_readyq_handler.isnull() && state != m_ready_pin)
1445	1420	m_readyq_handler(!state);
r249038	r249039
1539	1514
1540	1515	/* initialize the chip state */
1541	1516	/* Note that we do not actually clear IRQ on start-up : IRQ is even raised if m_buffer_empty or m_buffer_low are 0 */
1542		m_~~SPEN = m~~_~~DDIS~~ = m_~~TALK = m~~_~~TALKD~~ = m_~~previo~~us~~_TALK_STATUS~~ = m_irq_pin = m_ready_pin = 0;
	1517	m_speaking_now = m_speak_external = m_talk_status = m_irq_pin = m_ready_pin = 0;
1543	1518	set_interrupt_state(0);
1544	1519	update_ready_state();
1545	1520	m_buffer_empty = m_buffer_low = 1;
r249038	r249039
1550	1525	#ifdef PERFECT_INTERPOLATION_HACK
1551	1526	m_old_frame_energy_idx = m_old_frame_pitch_idx = 0;
1552	1527	memset(m_old_frame_k_idx, 0, sizeof(m_old_frame_k_idx));
1553		m_old_zpar = 0;
1554	1528	#endif
1555		m_new_frame_energy_idx = m_current_energy = m_previous_energy = 0;
1556		m_new_frame_pitch_idx = m_current_pitch = 0;
1557		m_zpar = m_uv_zpar = 0;
	1529	m_new_frame_energy_idx = m_current_energy = m_target_energy = m_previous_energy = 0;
	1530	m_new_frame_pitch_idx = m_current_pitch = m_target_pitch = 0;
1558	1531	memset(m_new_frame_k_idx, 0, sizeof(m_new_frame_k_idx));
1559	1532	memset(m_current_k, 0, sizeof(m_current_k));
	1533	memset(m_target_k, 0, sizeof(m_target_k));
1560	1534
1561	1535	/* initialize the sample generators */
1562	1536	m_inhibit = 1;
r249038	r249039
1600	1574	/* Write */
1601	1575	/* bring up to date first */
1602	1576	#ifdef DEBUG_IO_READY
1603		~~fprintf(std~~err,"Serviced write: %02x\n", m_write_latch);
	1577	logerror("Serviced write: %02x\n", m_write_latch);
1604	1578	//fprintf(stderr, "Processed write data: %02X\n", m_write_latch);
1605	1579	#endif
1606	1580	m_stream->update();
r249038	r249039
1636	1610	m_true_timing = 1;
1637	1611	state &= 0x01;
1638	1612	#ifdef DEBUG_RS_WS
1639		~~fprintf(std~~err,"/RS written with data: %d\n", state);
	1613	logerror("/RS written with data: %d\n", state);
1640	1614	#endif
1641	1615	new_val = (m_rs_ws & 0x01) \| (state<<1);
1642	1616	if (new_val != m_rs_ws)
r249038	r249039
1649	1623	#ifdef DEBUG_RS_WS
1650	1624	else
1651	1625	/* illegal */
1652		~~fprintf(std~~err,"tms5220_rs_w: illegal\n");
	1626	logerror("tms5220_rs_w: illegal\n");
1653	1627	#endif
1654	1628	return;
1655	1629	}
r249038	r249039
1667	1641	{
1668	1642	/* high to low - schedule ready cycle */
1669	1643	#ifdef DEBUG_RS_WS
1670		~~fprintf(std~~err,"Scheduling ready cycle for /RS...\n");
	1644	logerror("Scheduling ready cycle for /RS...\n");
1671	1645	#endif
1672	1646	/* upon /RS being activated, /READY goes inactive after 100 nsec from data sheet, through 3 asynchronous gates on patent. This is effectively within one clock, so we immediately set io_ready to 0 and activate the callback. */
1673	1647	m_io_ready = 0;
r249038	r249039
1688	1662	m_true_timing = 1;
1689	1663	state &= 0x01;
1690	1664	#ifdef DEBUG_RS_WS
1691		~~fprintf(std~~err,"/WS written with data: %d\n", state);
	1665	logerror("/WS written with data: %d\n", state);
1692	1666	#endif
1693	1667	new_val = (m_rs_ws & 0x02) \| (state<<0);
1694	1668	if (new_val != m_rs_ws)
r249038	r249039
1701	1675	#ifdef DEBUG_RS_WS
1702	1676	else
1703	1677	/* illegal */
1704		~~fprintf(std~~err,"tms5220_ws_w: illegal\n");
	1678	logerror("tms5220_ws_w: illegal\n");
1705	1679	#endif
1706	1680	return;
1707	1681	}
r249038	r249039
1719	1693	{
1720	1694	/* high to low - schedule ready cycle */
1721	1695	#ifdef DEBUG_RS_WS
1722		~~fprintf(std~~err,"Scheduling ready cycle for /WS...\n");
	1696	logerror("Scheduling ready cycle for /WS...\n");
1723	1697	#endif
1724	1698	/* upon /WS being activated, /READY goes inactive after 100 nsec from data sheet, through 3 asynchronous gates on patent. This is effectively within one clock, so we immediately set io_ready to 0 and activate the callback. */
1725	1699	m_io_ready = 0;
r249038	r249039
1752	1726	if (space.debugger_access()) return;
1753	1727
1754	1728	#ifdef DEBUG_RS_WS
1755		~~fprintf(std~~err,"tms5220_data_w: data %02x\n", data);
	1729	logerror("tms5220_data_w: data %02x\n", data);
1756	1730	#endif
1757	1731	if (!m_true_timing)
1758	1732	{
r249038	r249039
1765	1739	/* actually in a write ? */
1766	1740	#ifdef DEBUG_RS_WS
1767	1741	if (!(m_rs_ws == 0x02))
1768		~~fprintf(std~~err,"tms5220_data_w: data written outside ws, status: %02x!\n", m_rs_ws);
	1742	logerror("tms5220_data_w: data written outside ws, status: %02x!\n", m_rs_ws);
1769	1743	#endif
1770	1744	m_write_latch = data;
1771	1745	}
r249038	r249039
1797	1771	return m_read_latch;
1798	1772	#ifdef DEBUG_RS_WS
1799	1773	else
1800		~~fprintf(std~~err,"tms5220_status_r: data read outside rs!\n");
	1774	logerror("tms5220_status_r: data read outside rs!\n");
1801	1775	#endif
1802	1776	return 0xff;
1803	1777	}

trunk/src/emu/sound/tms5220.h
r249038	r249039
105	105
106	106
107	107	/* these contain global status bits */
108		UINT8 m_previous_TALK_STATUS; /* this is the OLD value of TALK_STATUS (i.e. previous value of m_SPEN\|m_TALKD), needed for generating interrupts on a falling TALK_STATUS edge */
109		UINT8 m_SPEN; /* set on speak(or speak external and BL falling edge) command, cleared on stop command, reset command, or buffer out */
110		UINT8 m_DDIS; /* If 1, DDIS is 1, i.e. Speak External command in progress, writes go to FIFO. */
111		UINT8 m_TALK; /* set on SPEN & RESETL4(pc12->pc0 transition), cleared on stop command or reset command */
112		#define TALK_STATUS (m_SPEN\|m_TALKD)
113		UINT8 m_TALKD; /* TALK(TCON) value, latched every RESETL4 */
	108	UINT8 m_speaking_now; /* True only if actual speech is being generated right now. Is set when a speak vsm command happens OR when speak external happens and buffer low becomes nontrue; Is cleared when speech halts after the last stop frame or the last frame after talk status is otherwise cleared.*/
	109	UINT8 m_speak_external; /* If 1, DDIS is 1, i.e. Speak External command in progress, writes go to FIFO. */
	110	UINT8 m_talk_status; /* If 1, TS status bit is 1, i.e. speak or speak external is in progress and we have not encountered a stop frame yet; talk_status differs from speaking_now in that speaking_now is set as soon as a speak or speak external command is started; talk_status does NOT go active until after 8 bytes are written to the fifo on a speak external command, otherwise the two are the same. TS is cleared by 3 things: 1. when a STOP command has just been processed as a new frame in the speech stream; 2. if the fifo runs out in speak external mode; 3. on power-up/during a reset command; When it gets cleared, speak_external is also cleared, an interrupt is generated, and speaking_now will be cleared when the next frame starts. */
114	111	UINT8 m_buffer_low; /* If 1, FIFO has less than 8 bytes in it */
115	112	UINT8 m_buffer_empty; /* If 1, FIFO is empty */
116	113	UINT8 m_irq_pin; /* state of the IRQ pin (output) */
r249038	r249039
135	132	INT16 m_current_energy;
136	133	INT16 m_current_pitch;
137	134	INT16 m_current_k[10];
	135
	136	INT16 m_target_energy;
	137	INT16 m_target_pitch;
	138	INT16 m_target_k[10];
138	139	#else
139	140	UINT8 m_old_frame_energy_idx;
140	141	UINT8 m_old_frame_pitch_idx;
141	142	UINT8 m_old_frame_k_idx[10];
142		UINT8 m_old_zpar;
143		UINT8 m_old_uv_zpar;
144	143
145	144	INT32 m_current_energy;
146	145	INT32 m_current_pitch;
147	146	INT32 m_current_k[10];
	147
	148	INT32 m_target_energy;
	149	INT32 m_target_pitch;
	150	INT32 m_target_k[10];
148	151	#endif
149	152
150	153	UINT16 m_previous_energy; /* needed for lattice filter to match patent */
r249038	r249039
152	155	UINT8 m_subcycle; /* contains the current subcycle for a given PC: 0 is A' (only used on SPKSLOW mode on 51xx), 1 is A, 2 is B */
153	156	UINT8 m_subc_reload; /* contains 1 for normal speech, 0 when SPKSLOW is active */
154	157	UINT8 m_PC; /* current parameter counter (what param is being interpolated), ranges from 0 to 12 */
155		/* NOTE: the interpolation period counts 1,2,3,4,5,6,7,0 for divide by 8,8,8,4,4,2,2,1 */
	158	/* TODO/NOTE: the current interpolation period, counts 1,2,3,4,5,6,7,0 for divide by 8,8,8,4,4,2,2,1 */
156	159	UINT8 m_IP; /* the current interpolation period */
157	160	UINT8 m_inhibit; /* If 1, interpolation is inhibited until the DIV1 period */
158		UINT8 m_uv_zpar; /* If 1, zero k5 thru k10 coefficients */
159		UINT8 m_zpar; /* If 1, zero ALL parameters. */
160		UINT8 m_pitch_zero; /* circuit 412; pitch is forced to zero under certain circumstances */
161	161	UINT8 m_c_variant_rate; /* only relevant for tms5220C's multi frame rate feature; is the actual 4 bit value written on a 0x2* or 0x0* command */
162	162	UINT16 m_pitch_count; /* pitch counter; provides chirp rom address */
163	163
164	164	INT32 m_u[11];
165	165	INT32 m_x[10];
166	166
167		UINT16 m_RNG; /* the random noise generator configuration is: 1 + x + x^3 + x^4 + x^13 ~~TODO: no it isn't~~ */
	167	UINT16 m_RNG; /* the random noise generator configuration is: 1 + x + x^3 + x^4 + x^13 */
168	168	INT16 m_excitation_data;
169	169
170	170	/* R Nabet : These have been added to emulate speech Roms */

trunk/src/mame/arcade.lst
r249038	r249039
8220	8220	nbajamte3 // (c) 1994 Midway
8221	8221	nbajamten // (c) 1995 Midway
8222	8222	revx // (c) 1994 Midway
8223		revxp5 // (c) 1994 Midway
8224	8223	mk3 // (c) 1994 Midway
8225	8224	mk3r20 // (c) 1994 Midway
8226	8225	mk3r10 // (c) 1994 Midway

trunk/src/mame/drivers/fcrash.c
r249038	r249039
2958	2958
2959	2959	GAME( 1992, sf2b, sf2, sf2b, sf2mdt, cps_state, sf2b, ROT0, "bootleg", "Street Fighter II: The World Warrior (bootleg)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_SUPPORTS_SAVE ) //910204 - based on World version
2960	2960
2961		GAME( 1992, sf2m9, sf2ce, sf2m1, sf2, cps_state, ~~sf2m1~~, ROT0, "bootleg", "Street Fighter II': Champion Edition (M9, bootleg)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_SUPPORTS_SAVE ) // 920313 ETC
	2961	GAME( 1992, sf2m9, sf2ce, sf2m1, sf2, cps_state, dinopic, ROT0, "bootleg", "Street Fighter II': Champion Edition (M9, bootleg)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_SUPPORTS_SAVE ) // 920313 ETC
2962	2962
2963	2963	GAME( 1993, slampic, slammast, slampic, slammast, cps_state, dinopic, ROT0, "bootleg", "Saturday Night Slam Masters (bootleg with PIC16c57)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NO_SOUND \| MACHINE_SUPPORTS_SAVE ) // 930713 ETC
2964	2964

trunk/src/mame/drivers/lethalj.c
r249038	r249039
681	681
682	682	ROM_START( lethalj )
683	683	ROM_REGION16_LE( 0x100000, "user1", 0 ) /* 34010 code */
684		ROM_LOAD16_BYTE( "lethal_vc8_2.3.vc8", 0x000000, 0x080000, CRC(8d568e1d) SHA1(e4dd3794789f9ccd7be8374978a3336f2b79136f) ) /* Labeled as LETHAL VC8 2.3, also found labeled as VC-8 */
685		ROM_LOAD16_BYTE( "lethal_vc9_2.3.vc9", 0x000001, 0x080000, CRC(8f22add4) SHA1(e773d3ae9cf512810fc266e784d21ed115c8830c) ) /* Labeled as LETHAL VC9 2.3, also found labeled as VC-9 */
	684	ROM_LOAD16_BYTE( "vc8", 0x000000, 0x080000, CRC(8d568e1d) SHA1(e4dd3794789f9ccd7be8374978a3336f2b79136f) )
	685	ROM_LOAD16_BYTE( "vc9", 0x000001, 0x080000, CRC(8f22add4) SHA1(e773d3ae9cf512810fc266e784d21ed115c8830c) )
686	686
687	687	ROM_REGION16_LE( 0x600000, "gfx1", 0 ) /* graphics data */
688		ROM_LOAD16_BYTE( "gr1.gr1", 0x000000, 0x100000, CRC(27f7b244) SHA1(628b29c066e217e1fe54553ea3ed98f86735e262) ) /* These had non specific GRx labels, also found labeled as GR-x */
689		ROM_LOAD16_BYTE( "gr2.gr2", 0x000001, 0x100000, CRC(1f25d3ab) SHA1(bdb8a3c546cdee9a5630c47b9c5079a956e8a093) )
690		ROM_LOAD16_BYTE( "gr4.gr4", 0x200000, 0x100000, CRC(c5838b4c) SHA1(9ad03d0f316eb31fdf0ca6f65c02a27d3406d072) )
691		ROM_LOAD16_BYTE( "gr3.gr3", 0x200001, 0x100000, CRC(ba9fa057) SHA1(db6f11a8964870f04f94fef6f1b1a58168a942ad) )
692		ROM_LOAD16_BYTE( "lethal_gr6_2.3.gr6", 0x400000, 0x100000, CRC(51c99b85) SHA1(9a23bf21a73d2884b49c64a8f42c288534c79dc5) ) /* Labeled as LETHAL GR6 2.3, also found labeled as GR-6 */
693		ROM_LOAD16_BYTE( "lethal_gr5_2.3.gr5", 0x400001, 0x100000, CRC(80dda9b5) SHA1(d8a79cad112bc7d9e4ba31a950e4807581f3bf46) ) /* Labeled as LETHAL GR5 2.3, also found labeled as GR-5 */
	688	ROM_LOAD16_BYTE( "gr1", 0x000000, 0x100000, CRC(27f7b244) SHA1(628b29c066e217e1fe54553ea3ed98f86735e262) )
	689	ROM_LOAD16_BYTE( "gr2", 0x000001, 0x100000, CRC(1f25d3ab) SHA1(bdb8a3c546cdee9a5630c47b9c5079a956e8a093) )
	690	ROM_LOAD16_BYTE( "gr4", 0x200000, 0x100000, CRC(c5838b4c) SHA1(9ad03d0f316eb31fdf0ca6f65c02a27d3406d072) )
	691	ROM_LOAD16_BYTE( "gr3", 0x200001, 0x100000, CRC(ba9fa057) SHA1(db6f11a8964870f04f94fef6f1b1a58168a942ad) )
	692	ROM_LOAD16_BYTE( "gr6", 0x400000, 0x100000, CRC(51c99b85) SHA1(9a23bf21a73d2884b49c64a8f42c288534c79dc5) )
	693	ROM_LOAD16_BYTE( "gr5", 0x400001, 0x100000, CRC(80dda9b5) SHA1(d8a79cad112bc7d9e4ba31a950e4807581f3bf46) )
694	694
695	695	ROM_REGION( 0x40000, "oki1", 0 ) /* sound data */
696	696	ROM_LOAD( "sound1.u20", 0x00000, 0x40000, CRC(7d93ca66) SHA1(9e1dc0efa5d0f770c7e1f10de56fbf5620dea437) )
r249038	r249039
1007	1007	*
1008	1008	*************************************/
1009	1009
1010		GAME( 1996, lethalj, 0, lethalj, lethalj, driver_device, 0, ROT0, "The Game Room", "Lethal Justice ~~(Version 2.3)~~", 0 )
	1010	GAME( 1996, lethalj, 0, lethalj, lethalj, driver_device, 0, ROT0, "The Game Room", "Lethal Justice", 0 )
1011	1011	GAME( 1996, franticf, 0, gameroom, franticf, driver_device, 0, ROT0, "The Game Room", "Frantic Fred", MACHINE_NOT_WORKING )
1012	1012	GAME( 1997, eggventr, 0, gameroom, eggventr, driver_device, 0, ROT0, "The Game Room", "Egg Venture (Release 10)", 0 )
1013	1013	GAME( 1997, eggventr8, eggventr, gameroom, eggventr, driver_device, 0, ROT0, "The Game Room", "Egg Venture (Release 8)", 0 )

trunk/src/mame/drivers/midxunit.c
r249038	r249039
345	345	ROM_LOAD( "a-17721.u955", 0x200, 0x117, CRC(033fe902) SHA1(6efb4e519ed3c9d49fff046a679762b506b3a75b) )
346	346	ROM_END
347	347
348		ROM_START( revxp5 )
349		ROM_REGION16_LE( 0x1000000, "dcs", ROMREGION_ERASEFF ) /* sound data */
350		ROM_LOAD16_BYTE( "revx_snd.2", 0x000000, 0x80000, CRC(4ed9e803) SHA1(ba50f1beb9f2a2cf5110897209b5e9a2951ff165) )
351		ROM_LOAD16_BYTE( "revx_snd.3", 0x200000, 0x80000, CRC(af8f253b) SHA1(25a0000cab177378070f7a6e3c7378fe87fad63e) )
352		ROM_LOAD16_BYTE( "revx_snd.4", 0x400000, 0x80000, CRC(3ccce59c) SHA1(e81a31d64c64e7b1d25f178c53da3d68453c203c) )
353		ROM_LOAD16_BYTE( "revx_snd.5", 0x600000, 0x80000, CRC(a0438006) SHA1(560d216d21cb8073dbee0fd20ebe589932a9144e) )
354		ROM_LOAD16_BYTE( "revx_snd.6", 0x800000, 0x80000, CRC(b7b34f60) SHA1(3b9682c6a00fa3bdb47e69d8e8ceccc244ee55b5) )
355		ROM_LOAD16_BYTE( "revx_snd.7", 0xa00000, 0x80000, CRC(6795fd88) SHA1(7c3790730a8b99b63112c851318b1c7e4989e5e0) )
356		ROM_LOAD16_BYTE( "revx_snd.8", 0xc00000, 0x80000, CRC(793a7eb5) SHA1(4b1f81b68f95cedf1b356ef362d1eb37acc74b16) )
357		ROM_LOAD16_BYTE( "revx_snd.9", 0xe00000, 0x80000, CRC(14ddbea1) SHA1(8dba9dc5529ea77c4312ea61f825bf9062ffc6c3) )
358	348
359		ROM_REGION16_LE( 0x200000, "maincpu", 0 ) /* 34020 code */
360		ROM_LOAD32_BYTE( "revx_p5.51", 0x00000, 0x80000, CRC(f3877eee) SHA1(7a4fdce36edddd35308c107c992ce626a2c9eb8c) )
361		ROM_LOAD32_BYTE( "revx_p5.52", 0x00001, 0x80000, CRC(199a54d8) SHA1(45319437e11176d4926c00c95c372098203a32a3) )
362		ROM_LOAD32_BYTE( "revx_p5.53", 0x00002, 0x80000, CRC(fcfcf72a) SHA1(b471afb416e3d348b046b0b40f497d27b0afa470) )
363		ROM_LOAD32_BYTE( "revx_p5.54", 0x00003, 0x80000, CRC(fd684c31) SHA1(db3453792e4d9fc375297d030f0b3f9cc3cad925) )
364	349
365		ROM_REGION( 0x2000, "pic", 0 )
366		ROM_LOAD( "revx_16c57.bin", 0x0000000, 0x2000, CRC(eb8a8649) SHA1(a1e1d0b7a5e9802e8f889eb7e719259656dc8133) )
367
368		ROM_REGION( 0x1000000, "gfxrom", 0 )
369		ROM_LOAD32_BYTE( "revx.120", 0x0000000, 0x80000, CRC(523af1f0) SHA1(a67c0fd757e860fc1c1236945952a295b4d5df5a) )
370		ROM_LOAD32_BYTE( "revx.121", 0x0000001, 0x80000, CRC(78201d93) SHA1(fb0b8f887eec433f7624f387d7fb6f633ea30d7c) )
371		ROM_LOAD32_BYTE( "revx.122", 0x0000002, 0x80000, CRC(2cf36144) SHA1(22ed0eefa2c7c836811fac5f717c3f38254eabc2) )
372		ROM_LOAD32_BYTE( "revx.123", 0x0000003, 0x80000, CRC(6912e1fb) SHA1(416f0de711d80e9182ede524c568c5095b1bec61) )
373
374		ROM_LOAD32_BYTE( "revx.110", 0x0200000, 0x80000, CRC(e3f7f0af) SHA1(5877d9f488b0f4362a9482007c3ff7f4589a036f) )
375		ROM_LOAD32_BYTE( "revx.111", 0x0200001, 0x80000, CRC(49fe1a69) SHA1(9ae54b461f0524c034fbcb6fcd3fd5ccb5d7265a) )
376		ROM_LOAD32_BYTE( "revx.112", 0x0200002, 0x80000, CRC(7e3ba175) SHA1(dd2fe90988b544f67dbe6151282fd80d49631388) )
377		ROM_LOAD32_BYTE( "revx.113", 0x0200003, 0x80000, CRC(c0817583) SHA1(2f866e5888e212b245984344950d0e1fb8957a73) )
378
379		ROM_LOAD32_BYTE( "revx.101", 0x0400000, 0x80000, CRC(5a08272a) SHA1(17da3c9d71114f5fdbf50281a942be3da3b6f564) )
380		ROM_LOAD32_BYTE( "revx.102", 0x0400001, 0x80000, CRC(11d567d2) SHA1(7ebe6fd39a0335e1fdda150d2dc86c3eaab17b2e) )
381		ROM_LOAD32_BYTE( "revx.103", 0x0400002, 0x80000, CRC(d338e63b) SHA1(0a038217542667b3a01ecbcad824ee18c084f293) )
382		ROM_LOAD32_BYTE( "revx.104", 0x0400003, 0x80000, CRC(f7b701ee) SHA1(0fc5886e5857326bee7272d5d482a878cbcea83c) )
383
384		ROM_LOAD32_BYTE( "revx.91", 0x0600000, 0x80000, CRC(52a63713) SHA1(dcc0ff3596bd5d273a8d4fd33b0b9b9d588d8354) )
385		ROM_LOAD32_BYTE( "revx.92", 0x0600001, 0x80000, CRC(fae3621b) SHA1(715d41ea789c0c724baa5bd90f6f0f06b9cb1c64) )
386		ROM_LOAD32_BYTE( "revx.93", 0x0600002, 0x80000, CRC(7065cf95) SHA1(6c5888da099e51c4b1c592721c5027c899cf52e3) )
387		ROM_LOAD32_BYTE( "revx.94", 0x0600003, 0x80000, CRC(600d5b98) SHA1(6aef98c91f87390c0759fe71a272a3ccadd71066) )
388
389		ROM_LOAD32_BYTE( "revx.81", 0x0800000, 0x80000, CRC(729eacb1) SHA1(d130162ae22b99c84abfbe014c4e23e20afb757f) )
390		ROM_LOAD32_BYTE( "revx.82", 0x0800001, 0x80000, CRC(19acb904) SHA1(516059b516bc5b1669c9eb085e0cdcdee520dff0) )
391		ROM_LOAD32_BYTE( "revx.83", 0x0800002, 0x80000, CRC(0e223456) SHA1(1eedbd667f4a214533d1c22ca5312ecf2d4a3ab4) )
392		ROM_LOAD32_BYTE( "revx.84", 0x0800003, 0x80000, CRC(d3de0192) SHA1(2d22c5bac07a7411f326691167c7c70eba4b371f) )
393
394		ROM_LOAD32_BYTE( "revx.71", 0x0a00000, 0x80000, CRC(2b29fddb) SHA1(57b71e5c18b56bf58216e690fdefa6d30d88d34a) )
395		ROM_LOAD32_BYTE( "revx.72", 0x0a00001, 0x80000, CRC(2680281b) SHA1(d1ae0701d20166a00d8733d9d12246c140a5fb96) )
396		ROM_LOAD32_BYTE( "revx.73", 0x0a00002, 0x80000, CRC(420bde4d) SHA1(0f010cdeddb59631a5420dddfc142c50c2a1e65a) )
397		ROM_LOAD32_BYTE( "revx.74", 0x0a00003, 0x80000, CRC(26627410) SHA1(a612121554549afff5c8e8c54774ca7b0220eda8) )
398
399		ROM_LOAD32_BYTE( "revx.63", 0x0c00000, 0x80000, CRC(3066e3f3) SHA1(25548923db111bd6c6cff44bfb63cb9eb2ef0b53) )
400		ROM_LOAD32_BYTE( "revx.64", 0x0c00001, 0x80000, CRC(c33f5309) SHA1(6bb333f563ea66c4c862ffd5fb91fb5e1b919fe8) )
401		ROM_LOAD32_BYTE( "revx.65", 0x0c00002, 0x80000, CRC(6eee3e71) SHA1(0ef22732e0e2bb5207559decd43f90d1e338ad7b) )
402		ROM_LOAD32_BYTE( "revx.66", 0x0c00003, 0x80000, CRC(b43d6fff) SHA1(87584e7aeea9d52a43023d40c359591ff6342e84) )
403
404		ROM_LOAD32_BYTE( "revx_p5.51", 0xe00000, 0x80000, CRC(f3877eee) SHA1(7a4fdce36edddd35308c107c992ce626a2c9eb8c) )
405		ROM_LOAD32_BYTE( "revx_p5.52", 0xe00001, 0x80000, CRC(199a54d8) SHA1(45319437e11176d4926c00c95c372098203a32a3) )
406		ROM_LOAD32_BYTE( "revx_p5.53", 0xe00002, 0x80000, CRC(fcfcf72a) SHA1(b471afb416e3d348b046b0b40f497d27b0afa470) )
407		ROM_LOAD32_BYTE( "revx_p5.54", 0xe00003, 0x80000, CRC(fd684c31) SHA1(db3453792e4d9fc375297d030f0b3f9cc3cad925) )
408
409		ROM_REGION( 0x400, "plds", 0 )
410		ROM_LOAD( "a-17722.u1", 0x000, 0x117, CRC(054de7a3) SHA1(bb7abaec50ed704c03b44d5d54296898f7c80d38) )
411		ROM_LOAD( "a-17721.u955", 0x200, 0x117, CRC(033fe902) SHA1(6efb4e519ed3c9d49fff046a679762b506b3a75b) )
412		ROM_END
413
414
415
416	350	/*************************************
417	351	*
418	352	* Game drivers
419	353	*
420	354	*************************************/
421	355
422		GAME( 1994, revx, 0, midxunit, revx, midxunit_state, revx, ROT0, "Midway", "Revolution X (rev 1.0 6/16/94)", MACHINE_SUPPORTS_SAVE )
423		GAME( 1994, revxp5, revx, midxunit, revx, midxunit_state, revx, ROT0, "Midway", "Revolution X (prototype, rev 5.0 5/23/94)", MACHINE_SUPPORTS_SAVE )
	356	GAME( 1994, revx, 0, midxunit, revx, midxunit_state, revx, ROT0, "Midway", "Revolution X (Rev. 1.0 6/16/94)", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/namcofl.c
r249038	r249039
610	610	MCFG_VIDEO_START_OVERRIDE(namcofl_state,namcofl)
611	611
612	612	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
613		MCFG_C352_ADD("c352", 48384000/2, 288)
	613	MCFG_C352_ADD("c352", 48384000/2, C352_DIVIDER_288)
614	614	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
615	615	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
616	616	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namconb1.c
r249038	r249039
1126	1126	MCFG_VIDEO_START_OVERRIDE(namconb1_state,namconb1)
1127	1127
1128	1128	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1129		MCFG_C352_ADD("c352", MASTER_CLOCK/2, 288)
	1129	MCFG_C352_ADD("c352", MASTER_CLOCK/2, C352_DIVIDER_288)
1130	1130	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
1131	1131	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
1132	1132	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249038	r249039
1163	1163	MCFG_VIDEO_START_OVERRIDE(namconb1_state,namconb2)
1164	1164
1165	1165	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1166		MCFG_C352_ADD("c352", MASTER_CLOCK/2, 288)
	1166	MCFG_C352_ADD("c352", MASTER_CLOCK/2, C352_DIVIDER_288)
1167	1167	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
1168	1168	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
1169	1169	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcond1.c
r249038	r249039
307	307	/* sound hardware */
308	308	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
309	309
310		MCFG_C352_ADD("c352", XTAL_49_152MHz/2, 288)
	310	MCFG_C352_ADD("c352", XTAL_49_152MHz/2, C352_DIVIDER_288)
311	311	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
312	312	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
313	313	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos11.c
r249038	r249039
571	571
572	572	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
573	573
574		MCFG_C352_ADD("c352", 20013200, 228)
	574	MCFG_C352_ADD("c352", 20013200, C352_DIVIDER_228)
575	575	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
576	576	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
577	577	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos12.c
r249038	r249039
1622	1622	/* sound hardware */
1623	1623	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
1624	1624
1625		MCFG_C352_ADD("c352", 29168000, 332)
	1625	MCFG_C352_ADD("c352", 29168000, C352_DIVIDER_332)
1626	1626	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
1627	1627	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
1628	1628	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos22.c
r249038	r249039
3781	3781	/* sound hardware */
3782	3782	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3783	3783
3784		MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, 288)
	3784	MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, C352_DIVIDER_288)
3785	3785	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3786	3786	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3787	3787	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249038	r249039
3830	3830	/* sound hardware */
3831	3831	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3832	3832
3833		MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, 288)
	3833	MCFG_C352_ADD("c352", SS22_MASTER_CLOCK/2, C352_DIVIDER_288)
3834	3834	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3835	3835	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3836	3836	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/namcos23.c
r249038	r249039
1247	1247	#define JVSCLOCK (XTAL_14_7456MHz)
1248	1248	#define H8CLOCK (16737350) /* from 2061 */
1249	1249	#define BUSCLOCK (167373502) / 33MHz CPU bus clock / input */
1250		#define C352CLOCK (25992000) /* measured at 25.992MHz from 2061 pin 9 */
1251		#define C352DIV (296)
	1250	#define C352CLOCK (25992000) /* measured at 25.992MHz from 2061 pin 9 (System 12 uses a divider of 332) */
1252	1251	#define VSYNC1 (59.8824)
1253	1252	#define VSYNC2 (59.915)
1254	1253	#define HSYNC (16666150)
r249038	r249039
3321	3320	/* sound hardware */
3322	3321	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3323	3322
3324		MCFG_C352_ADD("c352", C352CLOCK, C352DIV)
	3323	MCFG_C352_ADD("c352", C352CLOCK, C352_DIVIDER_332)
3325	3324	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3326	3325	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3327	3326	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249038	r249039
3390	3389	/* sound hardware */
3391	3390	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3392	3391
3393		MCFG_C352_ADD("c352", C352CLOCK, C352DIV)
	3392	MCFG_C352_ADD("c352", C352CLOCK, C352_DIVIDER_332)
3394	3393	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3395	3394	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3396	3395	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)
r249038	r249039
3470	3469	/* sound hardware */
3471	3470	MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
3472	3471
3473		MCFG_C352_ADD("c352", C352CLOCK, C352DIV)
	3472	MCFG_C352_ADD("c352", C352CLOCK, C352_DIVIDER_332)
3474	3473	MCFG_SOUND_ROUTE(0, "rspeaker", 1.00)
3475	3474	MCFG_SOUND_ROUTE(1, "lspeaker", 1.00)
3476	3475	MCFG_SOUND_ROUTE(2, "rspeaker", 1.00)

trunk/src/mame/drivers/quantum.c
r249038	r249039
334	334	/* AVG PROM */
335	335	ROM_REGION( 0x100, "user1", 0 )
336	336	ROM_LOAD( "136002-125.6h", 0x0000, 0x0100, BAD_DUMP CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
337
338		ROM_REGION( 0x200, "plds", 0 )
339		ROM_LOAD( "137290-001.1b", 0x0000, 0x0117, CRC(938a4598) SHA1(e5b6ddb1b4bb5546d3a0da5d00ce7c57a9e8e769) ) // GAL16V8
340	337	ROM_END
341	338
342	339
r249038	r249039
355	352	/* AVG PROM */
356	353	ROM_REGION( 0x100, "user1", 0 )
357	354	ROM_LOAD( "136002-125.6h", 0x0000, 0x0100, BAD_DUMP CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
358
359		ROM_REGION( 0x200, "plds", 0 )
360		ROM_LOAD( "137290-001.1b", 0x0000, 0x0117, CRC(938a4598) SHA1(e5b6ddb1b4bb5546d3a0da5d00ce7c57a9e8e769) ) // GAL16V8
361	355	ROM_END
362	356
363	357
r249038	r249039
376	370	/* AVG PROM */
377	371	ROM_REGION( 0x100, "user1", 0 )
378	372	ROM_LOAD( "136002-125.6h", 0x0000, 0x0100, BAD_DUMP CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
379
380		ROM_REGION( 0x200, "plds", 0 )
381		ROM_LOAD( "137290-001.1b", 0x0000, 0x0117, CRC(938a4598) SHA1(e5b6ddb1b4bb5546d3a0da5d00ce7c57a9e8e769) ) // GAL16V8
382	373	ROM_END
383	374
384	375

trunk/src/mame/includes/chihiro.h
r249038	r249039
185	185	memset(pfifo, 0, sizeof(pfifo));
186	186	memset(pcrtc, 0, sizeof(pcrtc));
187	187	memset(pmc, 0, sizeof(pmc));
188		memset(pgraph, 0, sizeof(pgraph));
189	188	memset(ramin, 0, sizeof(ramin));
190	189	computedilated();
191	190	objectdata = &(object_data_alloc());
r249038	r249039
195	194	enabled_vertex_attributes = 0;
196	195	indexesleft_count = 0;
197	196	vertex_pipeline = 4;
198		color_mask = 0xffffffff;
199	197	alpha_test_enabled = false;
200	198	alpha_reference = 0;
201	199	alpha_func = nv2a_renderer::ALWAYS;
r249038	r249039
240	238	}
241	239	DECLARE_READ32_MEMBER(geforce_r);
242	240	DECLARE_WRITE32_MEMBER(geforce_w);
243		void vblank_callback(screen_device &screen, bool state);
	241	bool vblank_callback(screen_device &screen, bool state);
244	242	UINT32 screen_update_callback(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
245		bool update_interrupts();
246		void set_interrupt_device(pic8259_device *device);
247	243
248	244	void render_texture_simple(INT32 scanline, const extent_t &extent, const nvidia_object_data &extradata, int threadid);
249	245	void render_color(INT32 scanline, const extent_t &extent, const nvidia_object_data &extradata, int threadid);
r249038	r249039
307	303	UINT32 pfifo[0x2000 / 4];
308	304	UINT32 pcrtc[0x1000 / 4];
309	305	UINT32 pmc[0x1000 / 4];
310		UINT32 pgraph[0x2000 / 4];
311	306	UINT32 ramin[0x100000 / 4];
312	307	UINT32 dma_offset[2];
313	308	UINT32 dma_size[2];
314	309	UINT8 *basemempointer;
315		pic8259_device *interruptdevice;
316	310	rectangle limits_rendertarget;
317	311	UINT32 pitch_rendertarget;
318	312	UINT32 pitch_depthbuffer;
r249038	r249039
447	441	int used;
448	442	osd_lock *lock;
449	443	} combiner;
450		UINT32 color_mask;
451	444	bool alpha_test_enabled;
452	445	int alpha_func;
453	446	int alpha_reference;

trunk/src/mame/machine/xbox.c
r249038	r249039
465	465
466	466	void xbox_base_state::vblank_callback(screen_device &screen, bool state)
467	467	{
468		nvidia_nv2a->vblank_callback(screen, state);
	468	if (nvidia_nv2a->vblank_callback(screen, state))
	469	xbox_base_devs.pic8259_1->ir3_w(1); // IRQ 3
	470	else
	471	xbox_base_devs.pic8259_1->ir3_w(0); // IRQ 3
469	472	}
470	473
471	474	UINT32 xbox_base_state::screen_update_callback(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
r249038	r249039
1457	1460	if (machine().debug_flags & DEBUG_FLAG_ENABLED)
1458	1461	debug_console_register_command(machine(), "xbox", CMDFLAG_NONE, 0, 1, 4, xbox_debug_commands);
1459	1462	memset(&ohcist, 0, sizeof(ohcist));
1460		// PIC challenge handshake data
1461		pic16lc_buffer[0x1c] = 0x0c;
1462		pic16lc_buffer[0x1d] = 0x0d;
1463		pic16lc_buffer[0x1e] = 0x0e;
1464		pic16lc_buffer[0x1f] = 0x0f;
1465	1463	#ifdef USB_ENABLED
1466	1464	ohcist.hc_regs[HcRevision] = 0x10;
1467	1465	ohcist.hc_regs[HcFmInterval] = 0x2edf;
r249038	r249039
1485	1483	save_item(NAME(smbusst.rw));
1486	1484	save_item(NAME(smbusst.words));
1487	1485	save_item(NAME(pic16lc_buffer));
1488		nvidia_nv2a->set_interrupt_device(xbox_base_devs.pic8259_1);
1489	1486	nvidia_nv2a->start(&m_maincpu->space());
1490	1487	nvidia_nv2a->savestate_items();
1491	1488	}

trunk/src/mame/video/chihiro.c
r249038	r249039
3	3	#include "emu.h"
4	4	#include "video/poly.h"
5	5	#include "bitmap.h"
6		#include "machine/pic8259.h"
7	6	#include "includes/chihiro.h"
8	7
9	8	//#define LOG_NV2A
r249038	r249039
946	945	UINT32 nv2a_renderer::geforce_object_offset(UINT32 handle)
947	946	{
948	947	UINT32 h = ((((handle >> 11) ^ handle) >> 11) ^ handle) & 0x7ff;
949		UINT32 o = (pfifo[0x210 / 4] & 0x1ff) << 8; // ~~0x1ff is n~~o~~t ce~~r~~tain~~
	948	UINT32 o = (pfifo[0x210 / 4] & 0x1f) << 8; // or 12 ?
950	949	UINT32 e = o + h * 8; // at 0xfd000000+0x00700000
951	950	UINT32 w;
952	951
953		if (ramin[e / 4] != handle) {
954		// this should never happen
955		for (UINT32 aa = o / 4; aa < (sizeof(ramin) / 4); aa = aa + 2) {
956		if (ramin[aa] == handle) {
957		e = aa * 4;
958		}
959		}
960		}
	952	if (ramin[e / 4] != handle)
	953	e = 0;
961	954	w = ramin[e / 4 + 1];
962		return (w & 0xffff) * 0x10; ~~// 0xffff is not certain~~
	955	return (w & 0xffff) * 0x10;
963	956	}
964	957
965	958	void nv2a_renderer::geforce_read_dma_object(UINT32 handle, UINT32 &offset, UINT32 &size)
r249038	r249039
1253	1246	addr = rendertarget + (dilated0[dilate_rendertarget][x] + dilated1[dilate_rendertarget][y]);
1254	1247	else // type_rendertarget == LINEAR*/
1255	1248	addr = rendertarget + (pitch_rendertarget / 4)*y + x;
1256		fbcolor = 0;
1257		if (color_mask != 0)
1258		fbcolor = *addr;
	1249	fbcolor = *addr;
1259	1250	daddr=depthbuffer + (pitch_depthbuffer / 4)*y + x;
1260	1251	deptsten = *daddr;
1261	1252	c[3] = color >> 24;
r249038	r249039
1781	1772	break;
1782	1773	}
1783	1774	}
1784		if (color_mask != 0) {
1785		UINT32 fbcolor_tmp;
1786
1787		fbcolor_tmp = (c[3] << 24) \| (c[2] << 16) \| (c[1] << 8) \| c[0];
1788		*addr = (fbcolor & ~color_mask) \| (fbcolor_tmp & color_mask);
1789		}
	1775	fbcolor = (c[3] << 24) \| (c[2] << 16) \| (c[1] << 8) \| c[0];
	1776	*addr = fbcolor;
1790	1777	if (depth_write_enabled)
1791	1778	dep = depth;
1792	1779	deptsten = (dep << 8) \| sten;
r249038	r249039
2246	2233	maddress = method * 4;
2247	2234	data = space.read_dword(address);
2248	2235	channel[chanel][subchannel].object.method[method] = data;
2249		#ifdef LOG_NV2A
2250		printf("A:%08X MTHD:%08X D:%08X\n\r",address,maddress,data);
2251		#endif
2252	2236	if (maddress == 0x17fc) {
2253	2237	indexesleft_count = 0;
2254	2238	indexesleft_first = 0;
r249038	r249039
2286	2270	}
2287	2271	wait();
2288	2272	}
2289		else if (type == nv2a_renderer::TRIANGLE_FAN) {
2290		vertex_nv vert[3];
2291		vertex_t xy[3];
2292
2293		read_vertices_0x1810(space, vert, offset, 2);
2294		convert_vertices_poly(vert, xy, 2);
2295		count = count - 2;
2296		offset = offset + 2;
2297		for (n = 0; n <= count; n++) {
2298		read_vertices_0x1810(space, vert + (((n + 1) & 1) + 1), offset + n, 1);
2299		convert_vertices_poly(vert + (((n + 1) & 1) + 1), xy + (((n + 1) & 1) + 1), 1);
2300		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, xy[0], xy[(~(n + 1) & 1) + 1], xy[((n + 1) & 1) + 1]);
2301		}
2302		wait();
2303		}
2304	2273	else if (type == nv2a_renderer::TRIANGLE_STRIP) {
2305	2274	vertex_nv vert[4];
2306	2275	vertex_t xy[4];
r249038	r249039
2342	2311	// each dword after 1800 contains two 16 bit index values to select the vartices
2343	2312	// each dword after 1808 contains a 32 bit index value to select the vartices
2344	2313	type = channel[chanel][subchannel].object.method[0x17fc / 4];
	2314	#ifdef LOG_NV2A
	2315	printf("vertex %d %d %d\n\r", type, offset, count);
	2316	#endif
2345	2317	if (type == nv2a_renderer::QUADS) {
2346	2318	while (1) {
2347	2319	vertex_nv vert[4];
r249038	r249039
2360	2332	render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, xy); // 4 rgba, 4 texture units 2 uv
2361	2333	}
2362	2334	}
2363		else if (type == nv2a_renderer::TRIANGLE_FAN) {
2364		if ((countlen * mult + indexesleft_count) >= 3) {
2365		vertex_nv vert[3];
2366		vertex_t xy[3];
2367		int c, count;
2368
2369		if (mult == 1)
2370		c = read_vertices_0x1808(space, vert, address, 2);
2371		else
2372		c = read_vertices_0x1800(space, vert, address, 2);
2373		convert_vertices_poly(vert, xy, 2);
2374		address = address + c * 4;
2375		countlen = countlen - c;
2376		count = countlen * mult + indexesleft_count;
2377		for (n = 1; n <= count; n++) {
2378		if (mult == 1)
2379		c = read_vertices_0x1808(space, vert + ((n & 1) + 1), address, 1);
2380		else
2381		c = read_vertices_0x1800(space, vert + ((n & 1) + 1), address, 1);
2382
2383		convert_vertices_poly(vert + ((n & 1) + 1), xy + ((n & 1) + 1), 1);
2384		address = address + c * 4;
2385		countlen = countlen - c;
2386		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, xy[0], xy[(~n & 1) + 1], xy[(n & 1) + 1]);
2387		}
2388		wait();
2389		}
2390		}
2391	2335	else if (type == nv2a_renderer::TRIANGLES) {
2392	2336	while (1) {
2393	2337	vertex_nv vert[3];
r249038	r249039
2502	2446	}
2503	2447	wait();
2504	2448	}
2505		else if (type == nv2a_renderer::TRIANGLES) {
2506		while (countlen > 0) {
2507		vertex_nv vert[3];
2508		vertex_t xy[3];
2509		int c;
2510
2511		c = read_vertices_0x1818(space, vert, address, 3);
2512		convert_vertices_poly(vert, xy, 3);
2513		countlen = countlen - c;
2514		if (countlen < 0) {
2515		logerror("Method 0x1818 missing %d words to draw a complete primitive\n", -countlen);
2516		countlen = 0;
2517		break;
2518		}
2519		address = address + c * 3;
2520		render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, xy[0], xy[1], xy[2]); // 4 rgba, 4 texture units 2 uv
2521		}
2522		}
2523	2449	else if (type == nv2a_renderer::TRIANGLE_STRIP) {
2524	2450	vertex_nv vert[4];
2525	2451	vertex_t xy[4];
r249038	r249039
2687	2613	// clear colors
2688	2614	UINT32 color = channel[chanel][subchannel].object.method[0x1d90 / 4];
2689	2615	bm.fill(color);
2690		#ifdef LOG_NV2A
2691		printf("clearscreen\n\r");
2692		#endif
	2616	//printf("clearscreen\n\r");
2693	2617	}
2694	2618	if ((data & 0x03) == 3) {
2695	2619	bitmap_rgb32 bm(depthbuffer, (limits_rendertarget.right() + 1) * m, (limits_rendertarget.bottom() + 1) * m, pitch_rendertarget / 4); // why *2 ?
r249038	r249039
2725	2649	dilate_rendertarget = dilatechose[(log2width_rendertarget << 4) + log2height_rendertarget];
2726	2650	}
2727	2651	if (maddress == 0x020c) {
	2652	// line size ?
2728	2653	pitch_rendertarget=data & 0xffff;
2729	2654	pitch_depthbuffer=(data >> 16) & 0xffff;
2730		#ifdef LOG_NV2A
2731		printf("Pitch color %04X zbuffer %04X\n\r",pitch_rendertarget,pitch_depthbuffer);
2732		#endif
	2655	//printf("Pitch color %04X zbuffer %04X\n\r",pitch_rendertarget,pitch_depthbuffer);
2733	2656	countlen--;
2734	2657	}
2735	2658	if (maddress == 0x0100) {
2736		countlen--;
2737		if (data != 0) {
2738		pgraph[0x704 / 4] = 0x100;
2739		pgraph[0x708 / 4] = data;
2740		pgraph[0x100 / 4] \|= 1;
2741		pgraph[0x108 / 4] \|= 1;
2742		if (update_interrupts() == true)
2743		interruptdevice->ir3_w(1); // IRQ 3
2744		else
2745		interruptdevice->ir3_w(0); // IRQ 3
2746		return 2;
	2659	// just temporarily
	2660	if ((data & 0x1f) == 1) {
	2661	data = data >> 5;
	2662	data = data & 0x0ffffff0;
	2663	displayedtarget = (UINT32 *)direct_access_ptr(data);
2747	2664	}
2748		else
2749		return 0;
2750	2665	}
2751	2666	if (maddress == 0x0130) {
2752	2667	countlen--;
r249038	r249039
2755	2670	else
2756	2671	return 0;
2757	2672	}
2758		if (maddress == 0x1d8c) {
2759		countlen--;
2760		// it is used to specify the clear value for the depth buffer (zbuffer)
2761		// but also as a parameter for interrupt routines
2762		pgraph[0x1a88 / 4] = data;
2763		}
2764		if (maddress == 0x1d90) {
2765		countlen--;
2766		// it is used to specify the clear value for the color buffer
2767		// but also as a parameter for interrupt routines
2768		pgraph[0x186c / 4] = data;
2769		}
2770	2673	if (maddress == 0x0210) {
2771	2674	// framebuffer offset ?
2772	2675	rendertarget = (UINT32 *)direct_access_ptr(data);
2773		#ifdef LOG_NV2A
2774		printf("Render target at %08X\n\r", data);
2775		#endif
	2676	//printf("Render target at %08X\n\r",data);
2776	2677	countlen--;
2777	2678	}
2778	2679	if (maddress == 0x0214) {
2779	2680	// zbuffer offset ?
2780	2681	depthbuffer = (UINT32 *)direct_access_ptr(data);
2781		#ifdef LOG_NV2A
2782		printf("Depth buffer at %08X\n\r",data);
2783		#endif
	2682	//printf("Depth buffer at %08X\n\r",data);
2784	2683	if ((data == 0) \|\| (data > 0x7ffffffc))
2785	2684	depth_write_enabled = false;
2786	2685	else if (channel[chanel][subchannel].object.method[0x035c / 4] != 0)
r249038	r249039
2810	2709	if (maddress == 0x0354) {
2811	2710	depth_function = data;
2812	2711	}
2813		if (maddress == 0x0358) {
2814		//color_mask = data;
2815		if (data & 0x000000ff)
2816		data \|= 0x000000ff;
2817		if (data & 0x0000ff00)
2818		data \|= 0x0000ff00;
2819		if (data & 0x00ff0000)
2820		data \|= 0x00ff0000;
2821		if (data & 0xff000000)
2822		data \|= 0xff000000;
2823		color_mask = data;
2824		}
2825	2712	if (maddress == 0x035c) {
2826	2713	UINT32 g = channel[chanel][subchannel].object.method[0x0214 / 4];
2827	2714	depth_write_enabled = data != 0;
r249038	r249039
3761	3648	combiner.function_Aop3 = MAX(MIN((combiner.function_Aop3 + biasa) * scalea, 1.0f), -1.0f);
3762	3649	}
3763	3650
3764		void nv2a_renderer::vblank_callback(screen_device &screen, bool state)
	3651	bool nv2a_renderer::vblank_callback(screen_device &screen, bool state)
3765	3652	{
3766		#ifdef LOG_NV2A
3767		printf("vblank_callback\n\r");
3768		#endif
3769		if ((state == true) && (puller_waiting == 1)) {
3770		puller_waiting = 0;
3771		puller_timer_work(NULL, 0);
3772		}
3773		if (state == true) {
	3653	//printf("vblank_callback\n\r");
	3654	if (state == true)
3774	3655	pcrtc[0x100 / 4] \|= 1;
3775		pcrtc[0x808 / 4] \|= 0x10000;
3776		}
3777		else {
3778		pcrtc[0x100 / 4] &= ~1;
3779		pcrtc[0x808 / 4] &= ~0x10000;
3780		}
3781		if (update_interrupts() == true)
3782		interruptdevice->ir3_w(1); // IRQ 3
3783	3656	else
3784		interruptdevice->ir3_w(0); // IRQ 3
3785		}
3786
3787		bool nv2a_renderer::update_interrupts()
3788		{
	3657	pcrtc[0x100 / 4] &= ~1;
3789	3658	if (pcrtc[0x100 / 4] & pcrtc[0x140 / 4])
3790	3659	pmc[0x100 / 4] \|= 0x1000000;
3791	3660	else
3792	3661	pmc[0x100 / 4] &= ~0x1000000;
3793		if (pgraph[0x100 / 4] & pgraph[0x140 / 4])
3794		pmc[0x100 / 4] \|= 0x1000;
3795		else
3796		pmc[0x100 / 4] &= ~0x1000;
3797		if (((pmc[0x100 / 4] & 0x7fffffff) && (pmc[0x140 / 4] & 1)) \|\| ((pmc[0x100 / 4] & 0x80000000) && (pmc[0x140 / 4] & 2))) {
	3662	if ((state == true) && (puller_waiting == 1)) {
	3663	puller_waiting = 0;
	3664	puller_timer_work(NULL, 0);
	3665	}
	3666	if ((pmc[0x100 / 4] != 0) && (pmc[0x140 / 4] != 0)) {
3798	3667	// send interrupt
3799	3668	return true;
3800	3669	}
r249038	r249039
3823	3692	int countlen;
3824	3693	int ret;
3825	3694	address_space *space = puller_space;
3826		#ifdef LOG_NV2A
3827		UINT32 subch;
3828		#endif
3829	3695
3830	3696	chanel = puller_channel;
3831	3697	subchannel = puller_subchannel;
r249038	r249039
3882	3748	}
3883	3749	if (ret != 0) {
3884	3750	puller_timer->enable(false);
3885		puller_waiting = ~~ret~~;
	3751	puller_waiting = 1;
3886	3752	return;
3887	3753	}
3888	3754	}
r249038	r249039
3981	3847	//logerror("NV_2A: read PRAMIN[%06X] value %08X\n",offset*4-0x00700000,ret);
3982	3848	}
3983	3849	else if ((offset >= 0x00400000 / 4) && (offset < 0x00402000 / 4)) {
3984		ret = pgraph[offset - 0x00400000 / 4];
3985	3850	//logerror("NV_2A: read PGRAPH[%06X] value %08X\n",offset*4-0x00400000,ret);
3986	3851	}
3987	3852	else if ((offset >= 0x00600000 / 4) && (offset < 0x00601000 / 4)) {
r249038	r249039
4005	3870	//logerror("NV_2A: read channel[%02X,%d,%04X]=%08X\n",chanel,subchannel,suboffset*4,ret);
4006	3871	return ret;
4007	3872	}
	3873	else
	3874	{
	3875	/* nothing */
	3876	}
4008	3877	//logerror("NV_2A: read at %08X mask %08X value %08X\n",0xfd000000+offset*4,mem_mask,ret);
4009	3878	return ret;
4010	3879	}
4011	3880
4012	3881	WRITE32_MEMBER(nv2a_renderer::geforce_w)
4013	3882	{
4014		UINT32 old;
4015		bool update_int;
4016
4017		update_int = false;
4018	3883	if ((offset >= 0x00101000 / 4) && (offset < 0x00102000 / 4)) {
4019	3884	//logerror("NV_2A: write STRAPS[%06X] mask %08X value %08X\n",offset*4-0x00101000,mem_mask,data);
4020	3885	}
r249038	r249039
4033	3898	//logerror("NV_2A: write PRAMIN[%06X]=%08X\n",offset*4-0x00700000,data & mem_mask);
4034	3899	}
4035	3900	else if ((offset >= 0x00400000 / 4) && (offset < 0x00402000 / 4)) {
4036		int e = offset - 0x00400000 / 4;
4037		if (e >= (sizeof(pgraph) / sizeof(UINT32)))
4038		return;
4039		old = pgraph[e];
4040		COMBINE_DATA(pgraph + e);
4041		if (e == 0x100 / 4) {
4042		pgraph[e] = old & ~data;
4043		if (data & 1)
4044		pgraph[0x108 / 4] = 0;
4045		update_int = true;
4046		}
4047		if (e == 0x140 / 4)
4048		update_int = true;
4049		if (e == 0x720 / 4) {
4050		if ((data & 1) && (puller_waiting == 2)) {
4051		puller_waiting = 0;
4052		puller_timer->enable();
4053		puller_timer->adjust(attotime::zero);
4054		}
4055		}
4056		if ((e >= 0x900 / 4) && (e < 0xa00 / 4))
4057		pgraph[e] = 0;
4058	3901	//logerror("NV_2A: write PGRAPH[%06X]=%08X\n",offset*4-0x00400000,data & mem_mask);
4059	3902	}
4060	3903	else if ((offset >= 0x00600000 / 4) && (offset < 0x00601000 / 4)) {
4061	3904	int e = offset - 0x00600000 / 4;
4062	3905	if (e >= (sizeof(pcrtc) / sizeof(UINT32)))
4063	3906	return;
4064		old = pcrtc[e];
4065	3907	COMBINE_DATA(pcrtc + e);
4066		if (e == 0x100 / 4) {
4067		pcrtc[e] = old & ~data;
4068		update_int = true;
4069		}
4070		if (e == 0x140 / 4)
4071		update_int = true;
4072	3908	if (e == 0x800 / 4) {
4073		displayedtarget = (UINT32 *)direct_access_ptr(pcrtc[e]);
4074		#ifdef LOG_NV2A
4075		printf("crtc buffer %08X\n\r", data);
4076		#endif
	3909	displayedtarget = (UINT32 *)direct_access_ptr(data);
	3910	//printf("crtc buffer %08X\n\r", data);
4077	3911	}
4078	3912	//logerror("NV_2A: write PCRTC[%06X]=%08X\n",offset*4-0x00600000,data & mem_mask);
4079	3913	}
r249038	r249039
4088	3922	// 32 channels size 0x10000 each, 8 subchannels per channel size 0x2000 each
4089	3923	int chanel, subchannel, suboffset;
4090	3924	//int method, count, handle, objclass;
	3925	#ifdef LOG_NV2A
	3926	int subch;
	3927	#endif
4091	3928
4092	3929	suboffset = offset - 0x00800000 / 4;
4093	3930	chanel = (suboffset >> (16 - 2)) & 31;
r249038	r249039
4122	3959	}
4123	3960	//else
4124	3961	// logerror("NV_2A: write at %08X mask %08X value %08X\n",0xfd000000+offset*4,mem_mask,data);
4125		if (update_int == true) {
4126		if (update_interrupts() == true)
4127		interruptdevice->ir3_w(1); // IRQ 3
4128		else
4129		interruptdevice->ir3_w(0); // IRQ 3
4130		}
4131	3962	}
4132	3963
4133	3964	void nv2a_renderer::savestate_items()
r249038	r249039
4140	3971	puller_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nv2a_renderer::puller_timer_work), this), (void *)"NV2A Puller Timer");
4141	3972	puller_timer->enable(false);
4142	3973	}
4143
4144		void nv2a_renderer::set_interrupt_device(pic8259_device *device)
4145		{
4146		interruptdevice = device;
4147		}

trunk/src/mess/drivers/force68k.c
r249038	r249039
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Joakim Larsson Edstr??m
3	3	/***************************************************************************
	4	*
	5	* Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
	6	*
	7	* 13/06/2015
	8	*
	9	* The info found on the links below is for a later revisions of the board I have
	10	* but it is somewhat compatible so I got the system ROM up and running in terminal.
	11	* My CPU-1 board has proms from 1983 and the PCB has no rev markings so probably
	12	* the original or a very early design. The board real estate differs from the later
	13	* CPU-1:s I found pictures of but has the same main chips and functions.
	14	*
	15	* http://bitsavers.trailing-edge.com/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
	16	* http://www.artisantg.com/info/P_wUovN.pdf
	17	*
	18	* Some info from those documents:
	19	*
	20	* Address Map
	21	* ----------------------------------------------------------
	22	* Address Range Description
	23	* ----------------------------------------------------------
	24	* 000 000 - 000 007 Initialisation vectors from system EPROM
	25	* 000 008 - 01F FFF Dynamic RAM on CPU-1 B
	26	* 000 008 - 07F FFF Dynamic RAM on CPU-1 D
	27	* 080 008 - 09F FFF SYSTEM EPROM Area
	28	* OAO 000 - OBF FFF USER EPROMArea
	29	* 0C0 041 - 0C0 043 ACIA (P3) Host
	30	* 0C0 080 - 0C0 082 ACIA (P4) Terminal
	31	* 0C0 101 - 0C0 103 ACIA (P5) Remote device (eg serial printer)
	32	* 0C0 401 - 0C0 42F RTC
	33	* OEO 001 - 0E0 035 PI/T (eg centronics printer)
	34	* OEO 200 - 0E0 2FF FPU
	35	* OEO 300 - 0E0 300 Reset Off
	36	* OEO 380 - 0E0 380 Reset On
	37	* 100 000 - FEF FFF VMEbus addresses (A24)
	38	* FFO 000 - FFF FFF VMEbus Short I/O (A16)
	39	* ----------------------------------------------------------
	40	*
	41	* Interrupt sources
	42	* ----------------------------------------------------------
	43	* Description Device Lvl IRQ VME board
	44	* /Board Vector Address
	45	* ----------------------------------------------------------
	46	* On board Sources
	47	* ABORT Switch 7 31
	48	* Real Time Clock (RTC) 58167A 6 30
	49	* Parallel/Timer (PI/T) 68230 5 29
	50	* Terminal ACIA 6850 4 28
	51	* Remote ACIA 6850 3 27
	52	* Host ACIA 6850 2 26
	53	* ACFAIL, SYSFAIL VME 5 29
	54	* Off board Sources (other VME boards)
	55	* 6 Port Serial I/O board SIO 4 64-75 0xb00000
	56	* 8 Port Serial I/O board ISIO 4 76-83 0x960000
	57	* Disk Controller WFC 3 119 0xb01000
	58	* SCSI Controller ISCSI 4 119 0xa00000
	59	* Slot 1 Controller Board ASCU 7 31 0xb02000
	60	* ----------------------------------------------------------
	61	*
	62	* 10. The VMEbus
	63	* ---------------
	64	* The implemented VMEbus Interface includes 24 address, 16 data,
	65	* 6 address modifier and the asynchronous control signals.
	66	* A single level bus arbiter is provided to build multi master
	67	* systems. In addition to the bus arbiter, a separate slave bus
	68	* arbitration allows selection of the arbitration level (0-3).
	69	*
	70	* The address modifier range .,Short 110 Access« can be selected
	71	* via a jumper for variable system generation. The 7 interrupt
	72	* request levels of the VMEbus are fully supported from the
	73	* SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
	74	* enabled/disabled via a jumper field.
	75	*
	76	* Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
	77	* SYSFAIL and SYSCLK signal (16 MHz).
	78	*
	79	* TODO:
	80	* - Finish 3 x ACIA6850, host and remote interface left, terminal works
	81	* - Finish 1 x 68230 Motorola, Parallel Interface / Timer as required by ROM
	82	* - Configure PIT to the Centronics device printer interface as
	83	* supported by ROM (DONE)
	84	* - Add 1 x Abort Switch
	85	* - Add 1 x Reset Switch
	86	* - Add 1 x Halt LED
	87	* - Add a jumper field device as supported by PCB
	88	* - Add configurable serial connector between ACIA:s and
	89	* - Real terminal emulator, ie rs232 "socket"
	90	* - Debug console
	91	* - Add VME bus driver
	92	*
	93	****************************************************************************/
4	94
5		Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
6
7		13/06/2015
8
9		The info found on the links below is for a later revisions of the board I have
10		but I hope it is somewhat compatible so I can get it up and running at least.
11		My CPU-1 board has proms from 1983 and no rev markings so probably the original.
12
13		http://bitsavers.trailing-edge.com/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
14		http://www.artisantg.com/info/P_wUovN.pdf
15
16		Some info from those documents:
17
18		Address Map
19		----------------------------------------------------------
20		Address Range Description
21		----------------------------------------------------------
22		000 000 - 000 007 Initialisation vectors from system EPROM
23		000 008 - 01F FFF Dynamic RAM on CPU-1 B
24		000 008 - 07F FFF Dynamic RAM on CPU-1 D
25		080 008 - 09F FFF SYSTEM EPROM Area
26		OAO 000 - OBF FFF USER EPROMArea
27		0C0 041 - 0C0 043 ACIA (P3) Host
28		0C0 080 - 0C0 082 ACIA (P4) Terminal
29		0C0 101 - 0C0 103 ACIA (P5) Remote device (eg serial printer)
30		0C0 401 - 0C0 42F RTC
31		OEO 001 - 0E0 035 PI/T (eg centronics printer)
32		OEO 200 - 0E0 2FF FPU
33		OEO 300 - 0E0 300 Reset Off
34		OEO 380 - 0E0 380 Reset On
35		100 000 - FEF FFF VMEbus addresses (A24)
36		FFO 000 - FFF FFF VMEbus Short I/O (A16)
37		----------------------------------------------------------
38
39		Interrupt sources
40		----------------------------------------------------------
41		Description Device Lvl IRQ VME board
42		/Board Vector Address
43		----------------------------------------------------------
44		On board Sources
45		ABORT Switch 7 31
46		Real Time Clock (RTC) 58167A 6 30
47		Parallel/Timer (PI/T) 68230 5 29
48		Terminal ACIA 6850 4 28
49		Remote ACIA 6850 3 27
50		Host ACIA 6850 2 26
51		ACFAIL, SYSFAIL VME 5 29
52		Off board Sources (other VME boards)
53		6 Port Serial I/O board SIO 4 64-75 0xb00000
54		8 Port Serial I/O board ISIO 4 76-83 0x960000
55		Disk Controller WFC 3 119 0xb01000
56		SCSI Controller ISCSI 4 119 0xa00000
57		Slot 1 Controller Board ASCU 7 31 0xb02000
58		----------------------------------------------------------
59
60		10. The VMEbus
61		---------------
62		The implemented VMEbus Interface includes 24 address, 16 data,
63		6 address modifier and the asynchronous control signals.
64		A single level bus arbiter is provided to build multi master
65		systems. In addition to the bus arbiter, a separate slave bus
66		arbitration allows selection of the arbitration level (0-3).
67
68		The address modifier range .,Short 110 Access?? can be selected
69		via a jumper for variable system generation. The 7 interrupt
70		request levels of the VMEbus are fully supported from the
71		SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
72		enabled/disabled via a jumper field.
73
74		Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
75		SYSFAIL and SYSCLK signal (16 MHz).
76
77
78		TODO:
79		- Finish 2 x ACIA6850, host and remote interface left, terminal works
80		- Finish 1 x 68230 Motorola, Parallel Interface / Timer
81		- Connect Port B to a Centronics printer interface
82		- Add 1 x Abort Switch
83		- Add configurable serial connector between ACIA:s and
84		- Real terminal emulator, ie rs232 "socket"
85		- Debug console
86		- Add VME bus driver
87
88		****************************************************************************/
89
90	95	#include "emu.h"
91	96	#include "bus/rs232/rs232.h"
92	97	#include "cpu/m68000/m68000.h"
r249038	r249039
94	99	#include "machine/68230pit.h"
95	100	#include "machine/6850acia.h"
96	101	#include "machine/clock.h"
	102	#include "bus/centronics/ctronics.h"
97	103
	104	#define LOG(x) /* x */
	105
98	106	#define BAUDGEN_CLOCK XTAL_1_8432MHz
99	107	/*
100		The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
101		Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
102		that I could find on the CPU-1 board. Here how I calculated the clock for
103		the factory settings. No need to add selectors until terminal.c supports
104		configurable baudrates. Fortunality CPU-1 was shipped with 9600N8!
105
106		From the documents:
107
108		3 RS232C interfaces, strap selectable baud rate from 110-9600 or 600-19200 baud
109
110		Default Jumper Settings of B7:
111		--------------------------------
112		GND 10 - 11 RSA input on 14411
113		F1 on 14411 1 - 20 Baud selector of the terminal port
114		F1 on 14411 3 - 18 Baud selector of the host port
115		F1 on 14411 5 - 16 Baud selector of the remote port
116
117		The RSB input on the 14411 is kept high always so RSA=0, RSB=1 and a 1.8432MHz crystal
118		generates 153600 on the F1 output pin which by default strapping is connected to all
119		three 6850 acias on the board. These can be strapped separatelly to speedup downloads.
120
121		The selectable outputs from 14411, F1-F16:
122		X16 RSA=0,RSB=1: 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 3200, 2153.3, 1758.8, 1200, 921600, 1843000
123		X64 RSA=1,RSB=1: 614400, 460800, 307200, 230400, 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 921600, 1843000
124
125		However, the datasheet says baudrate is strapable for 110-9600 but the output is 153600
126		so the system rom MUST setup the acia to divide by 16 to generate the correct baudrate.
127
128		*/
	108	* The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
	109	* Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
	110	* that I could find on the CPU-1 board. Here how I calculated the clock for
	111	* the factory settings. No need to add selectors until terminal.c supports
	112	* configurable baudrates. Fortunality CPU-1 was shipped with 9600N8!
	113	*
	114	* From the documents:
	115	*
	116	* 3 RS232C interfaces, strap selectable baud rate from 110-9600 or 600-19200 baud
	117	*
	118	* Default Jumper Settings of B7:
	119	* --------------------------------
	120	* GND 10 - 11 RSA input on 14411
	121	* F1 on 14411 1 - 20 Baud selector of the terminal port
	122	* F1 on 14411 3 - 18 Baud selector of the host port
	123	* F1 on 14411 5 - 16 Baud selector of the remote port
	124	*
	125	* The RSB input on the 14411 is kept high always so RSA=0, RSB=1 and a 1.8432MHz crystal
	126	* generates 153600 on the F1 output pin which by default strapping is connected to all
	127	* three 6850 acias on the board. These can be strapped separatelly to speedup downloads.
	128	*
	129	* The selectable outputs from 14411, F1-F16:
	130	* X16 RSA=0,RSB=1: 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 3200, 2153.3, 1758.8, 1200, 921600, 1843000
	131	* X64 RSA=1,RSB=1: 614400, 460800, 307200, 230400, 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 921600, 1843000
	132	*
	133	* However, the datasheet says baudrate is strapable for 110-9600 but the output is 153600
	134	* so the system rom MUST setup the acia to divide by 16 to generate the correct baudrate.
	135	*
	136	*/
129	137	#define ACIA_CLOCK (BAUDGEN_CLOCK / 12)
130	138
131	139	class force68k_state : public driver_device
132	140	{
133	141	public:
134		force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
135		driver_device(mconfig, type, tag),
136		// m_rtc(*this, "rtc")
137		m_maincpu(*this, "maincpu"),
138		m_rtc(*this, "rtc"),
139		m_pit(*this, "pit"),
140		m_aciahost(*this, "aciahost"),
141		m_aciaterm(*this, "aciaterm"),
142		m_aciaremt(*this, "aciaremt")
143		{
144		}
	142	force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
	143	driver_device (mconfig, type, tag),
	144	m_maincpu (*this, "maincpu"),
	145	m_rtc (*this, "rtc"),
	146	m_pit (*this, "pit"),
	147	m_aciahost (*this, "aciahost"),
	148	m_aciaterm (*this, "aciaterm"),
	149	m_aciaremt (*this, "aciaremt"),
	150	m_centronics (*this, "centronics")
	151	, m_centronics_ack (0)
	152	, m_centronics_busy (0)
	153	, m_centronics_perror (0)
	154	, m_centronics_select (0)
	155	{
	156	}
145	157
146		DECLARE_READ16_MEMBER(bootvect_r);
147		virtual void machine_start();
148		DECLARE_WRITE_LINE_MEMBER(write_aciahost_clock);
149		DECLARE_WRITE_LINE_MEMBER(write_aciaterm_clock);
150		DECLARE_WRITE_LINE_MEMBER(write_aciaremt_clock);
	158	DECLARE_READ16_MEMBER (bootvect_r);
	159	virtual void machine_start ();
	160	// clocks
	161	DECLARE_WRITE_LINE_MEMBER (write_aciahost_clock);
	162	DECLARE_WRITE_LINE_MEMBER (write_aciaterm_clock);
	163	DECLARE_WRITE_LINE_MEMBER (write_aciaremt_clock);
	164	// centronics printer interface
	165	DECLARE_WRITE_LINE_MEMBER (centronics_ack_w);
	166	DECLARE_WRITE_LINE_MEMBER (centronics_busy_w);
	167	DECLARE_WRITE_LINE_MEMBER (centronics_perror_w);
	168	DECLARE_WRITE_LINE_MEMBER (centronics_select_w);
151	169
	170	protected:
	171
152	172	private:
153		required_device<cpu_device> m_maincpu;
154		required_device<mm58167_device> m_rtc;
155		required_device<pit68230_device> m_pit;
156		required_device<acia6850_device> m_aciahost;
157		required_device<acia6850_device> m_aciaterm;
158		required_device<acia6850_device> m_aciaremt;
	173	required_device<cpu_device> m_maincpu;
	174	required_device<mm58167_device> m_rtc;
	175	required_device<pit68230_device> m_pit;
	176	required_device<acia6850_device> m_aciahost;
	177	required_device<acia6850_device> m_aciaterm;
	178	required_device<acia6850_device> m_aciaremt;
	179	optional_device<centronics_device> m_centronics;
159	180
160		// Pointer to System ROMs needed by bootvect_r
161		UINT16 *m_sysrom;
	181	INT32 m_centronics_ack;
	182	INT32 m_centronics_busy;
	183	INT32 m_centronics_perror;
	184	INT32 m_centronics_select;
	185
	186	// Pointer to System ROMs needed by bootvect_r
	187	UINT16 *m_sysrom;
162	188	};
163	189
164		static ADDRESS_MAP_START(force68k_mem, AS_PROGRAM, 16, force68k_state)
165		ADDRESS_MAP_UNMAP_HIGH
166		AM_RANGE(0x000000, 0x000007) AM_ROM AM_READ(bootvect_r) /* Vectors mapped from System EPROM */
167		AM_RANGE(0x000008, 0x01ffff) AM_RAM /* DRAM */
168		AM_RANGE(0x080000, 0x09ffff) AM_ROM /* System EPROM Area */
169		// AM_RANGE(0x0a0000, 0x0bffff) AM_ROM /* User EPROM Area */
170		AM_RANGE(0x0c0040, 0x0c0041) AM_DEVREADWRITE8("aciahost", acia6850_device, status_r, control_w, 0x00ff)
171		AM_RANGE(0x0c0042, 0x0c0043) AM_DEVREADWRITE8("aciahost", acia6850_device, data_r, data_w, 0x00ff)
172		AM_RANGE(0x0c0080, 0x0c0081) AM_DEVREADWRITE8("aciaterm", acia6850_device, status_r, control_w, 0xff00)
173		AM_RANGE(0x0c0082, 0x0c0083) AM_DEVREADWRITE8("aciaterm", acia6850_device, data_r, data_w, 0xff00)
174		AM_RANGE(0x0c0100, 0x0c0101) AM_DEVREADWRITE8("aciaremt", acia6850_device, status_r, control_w, 0x00ff)
175		AM_RANGE(0x0c0102, 0x0c0103) AM_DEVREADWRITE8("aciaremt", acia6850_device, data_r, data_w, 0x00ff)
176		AM_RANGE(0x0c0400, 0x0c042f) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
177		AM_RANGE(0x0e0000, 0x0e0035) AM_DEVREADWRITE8("pit", pit68230_device, data_r, data_w, 0x00ff)
	190	static ADDRESS_MAP_START (force68k_mem, AS_PROGRAM, 16, force68k_state)
	191	ADDRESS_MAP_UNMAP_HIGH
	192	AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
	193	AM_RANGE (0x000008, 0x01ffff) AM_RAM /* DRAM */
	194	AM_RANGE (0x080000, 0x09ffff) AM_ROM /* System EPROM Area */
	195	// AM_RANGE(0x0a0000, 0x0bffff) AM_ROM /* User EPROM Area */
	196	AM_RANGE (0x0c0040, 0x0c0041) AM_DEVREADWRITE8 ("aciahost", acia6850_device, status_r, control_w, 0x00ff)
	197	AM_RANGE (0x0c0042, 0x0c0043) AM_DEVREADWRITE8 ("aciahost", acia6850_device, data_r, data_w, 0x00ff)
	198	AM_RANGE (0x0c0080, 0x0c0081) AM_DEVREADWRITE8 ("aciaterm", acia6850_device, status_r, control_w, 0xff00)
	199	AM_RANGE (0x0c0082, 0x0c0083) AM_DEVREADWRITE8 ("aciaterm", acia6850_device, data_r, data_w, 0xff00)
	200	AM_RANGE (0x0c0100, 0x0c0101) AM_DEVREADWRITE8 ("aciaremt", acia6850_device, status_r, control_w, 0x00ff)
	201	AM_RANGE (0x0c0102, 0x0c0103) AM_DEVREADWRITE8 ("aciaremt", acia6850_device, data_r, data_w, 0x00ff)
	202	AM_RANGE (0x0c0400, 0x0c042f) AM_DEVREADWRITE8 ("rtc", mm58167_device, read, write, 0x00ff)
	203	AM_RANGE (0x0e0000, 0x0e0035) AM_DEVREADWRITE8 ("pit", pit68230_device, read, write, 0x00ff)
178	204	// AM_RANGE(0x0e0200, 0x0e0380) AM_READWRITE(fpu_r, fpu_w) /* optional FPCP 68881 FPU interface */
179	205	// AM_RANGE(0x100000, 0xfeffff) /* VMEbus Rev B addresses (24 bits) */
180	206	// AM_RANGE(0xff0000, 0xffffff) /* VMEbus Rev B addresses (16 bits) */
181	207	ADDRESS_MAP_END
182	208
183	209	/* Input ports */
184		static INPUT_PORTS_START( force68k )
	210	static INPUT_PORTS_START (force68k)
185	211	INPUT_PORTS_END
186	212
187		void force68k_state::machine_start()
	213	/*
	214	* Centronics support
	215	*
	216	* The system ROMs has support for a parallel printer interface but the signals are just routed to row A
	217	* of the VME P2 connector so no on board Centronics connector is available but assumed to be added on a
	218	* separate I/O board. After some detective work I found that the ROM works as follows:
	219	*
	220	* The 'PA' (Printer Attach) command issues a <cr> on Port A and sends a strobe on H2 it then loops over
	221	* the select signal, bit 0 on Port B, and the ack signal on HS1, both to be non zero. The support is really
	222	* flawed as the strobe signal goes high instead of low ( this might assume an inverting driver on the
	223	* P2 board ) and the busy signal is not checked at all. Or I might have assumed it all wrong, but it now
	224	* works with the generic centronics printer driver. Need the printer board documentation to improve further.
	225	*
	226	* When the 'PA' command is successful everything printed to screen is mirrored on the printer. Use the
	227	* 'NOPA' command to stop mirroring. I had no printer ROMs so could not test it with a "real" printer.
	228	*
	229	* Force CPU-1 init sequence for MC68230 PIT
	230	* -----------------------------------------
	231	* 0801E6 0E0000 W 00 -> PGCR Mode 0 (uni8), H34 dis, H12 dis, H1234 HZ
	232	* 0801E6 0E0002 W 00 -> PSRR PC4, PC5, H1S>H2S>H3S>H4S
	233	* 0801E6 0E0004 W FF -> PADDR Port A all Outputs
	234	* 0801E6 0E0006 W 00 -> PBDDR Port B all Inputs
	235	* 0801EA 0E000C W 60 -> PACR Port A Mode 01, pin def, dbfr H1 data rec, H2 status/int, H2 output neg, H2S clrd
	236	* 0801F0 0E000E W A0 -> PBCR Port B mode 1x, H4 output neg, H4S clrd, H3 int dis, H3 edg input, H3S set by assrt edg
	237	* 0801F6 0E0000 W 30 -> PGCR H34 enable, H12enable
	238	* 0801FC 0E000E W A8 -> PBCR +H4 asserted
	239	* 08020A 0E000E W A0 -> PBCR +H4 negated
	240	*
	241	* Upon PA (Printer Attach) command enabling the Centronics printer mode
	242	* ---------------------------------------------------------------------
	243	* 081DB4 0E0011 W D0 -> PADR Data to Port A
	244	* 081DB8 0E000D W 68 -> PACR H2 output asserted Centronics Strobe
	245	* 081DC0 0E000D W 60 -> PACR H2 output negated
	246	* 081DD0 0E0013 R 00 <- PBDR Port B polled for 01 (data) & 03 (mask)
	247	*
	248	*/
	249
	250	/* Centronics ACK handler
	251	* The centronics ack signal is expected by the ROM to arrive at H1 input line
	252	*/
	253	WRITE_LINE_MEMBER (force68k_state::centronics_ack_w)
188	254	{
189		m_sysrom = (UINT16*)(memregion("maincpu")->base() + 0x080000);
	255	LOG (logerror ("centronics_ack_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
	256	m_centronics_ack = state;
	257	m_pit->h1_set (state);
190	258	}
191	259
192		READ16_MEMBER(force68k_state::bootvect_r)
193		{
194		return m_sysrom[offset];
	260	/* Centronics BUSY handler
	261	* The centronics busy signal is not used by the ROM driver afaik
	262	*/
	263	WRITE_LINE_MEMBER (force68k_state::centronics_busy_w){
	264	LOG (logerror ("centronics_busy_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
	265	m_centronics_busy = state;
195	266	}
196	267
197		WRITE_LINE_MEMBER(force68k_state::write_aciahost_clock)
198		{
199		m_aciahost->write_txc(state);
200		m_aciahost->write_rxc(state);
	268	/* Centronics PERROR handler
	269	* The centronics perror signal is not used by the ROM driver afaik
	270	*/
	271	WRITE_LINE_MEMBER (force68k_state::centronics_perror_w){
	272	LOG (logerror ("centronics_perror_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
	273	m_centronics_perror = state;
201	274	}
202	275
203		WRITE_LINE_MEMBER(force68k_state::write_aciaterm_clock)
204		{
205		m_aciaterm->write_txc(state);
206		m_aciaterm->write_rxc(state);
	276	/* Centronics SELECT handler
	277	* The centronics select signal is expected by the ROM on Port B bit 0
	278	*/
	279	WRITE_LINE_MEMBER (force68k_state::centronics_select_w){
	280	LOG (logerror ("centronics_select_w(%d) %lld\n", state, m_maincpu->total_cycles ()));
	281	m_centronics_select = state;
	282	m_pit->portb_setbit (0, state);
207	283	}
208	284
209		WRITE_LINE_MEMBER(force68k_state::write_aciaremt_clock)
	285	/* Start it up */
	286	void force68k_state::machine_start ()
210	287	{
211		m_aciaremt->write_txc(state);
212		m_aciaremt->write_rxc(state);
	288	LOG (logerror ("machine_start\n"));
	289
	290	save_item (NAME (m_centronics_busy));
	291	save_item (NAME (m_centronics_ack));
	292	save_item (NAME (m_centronics_select));
	293	save_item (NAME (m_centronics_perror));
	294
	295	/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
	296	m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x080000);
213	297	}
214	298
215		static MACHINE_CONFIG_START( fccpu1, force68k_state )
216		/* basic machine hardware */
217		MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz / 2)
218		MCFG_CPU_PROGRAM_MAP(force68k_mem)
	299	/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
	300	READ16_MEMBER (force68k_state::bootvect_r){
	301	return m_sysrom [offset];
	302	}
219	303
220		/* P3/Host Port config */
221		MCFG_DEVICE_ADD("aciahost", ACIA6850, 0)
222		MCFG_DEVICE_ADD("aciahost_clock", CLOCK, ACIA_CLOCK)
223		MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciahost_clock))
	304	/*
	305	* Serial port clock sources can all be driven by different outputs of the 14411
	306	*/
	307	WRITE_LINE_MEMBER (force68k_state::write_aciahost_clock){
	308	m_aciahost->write_txc (state);
	309	m_aciahost->write_rxc (state);
	310	}
224	311
225		/* P4/Terminal Port config */
226		MCFG_DEVICE_ADD("aciaterm", ACIA6850, 0)
	312	WRITE_LINE_MEMBER (force68k_state::write_aciaterm_clock){
	313	m_aciaterm->write_txc (state);
	314	m_aciaterm->write_rxc (state);
	315	}
227	316
228		MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
229		MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
	317	WRITE_LINE_MEMBER (force68k_state::write_aciaremt_clock){
	318	m_aciaremt->write_txc (state);
	319	m_aciaremt->write_rxc (state);
	320	}
230	321
231		MCFG_RS232_PORT_ADD("rs232trm", default_rs232_devices, "terminal")
232		MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_rxd))
233		MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_cts))
	322	/*
	323	* Machine configuration
	324	*/
	325	static MACHINE_CONFIG_START (fccpu1, force68k_state)
	326	/* basic machine hardware */
	327	MCFG_CPU_ADD ("maincpu", M68000, XTAL_16MHz / 2)
	328	MCFG_CPU_PROGRAM_MAP (force68k_mem)
234	329
235		MCFG_DEVICE_ADD("aciaterm_clock", CLOCK, ACIA_CLOCK)
236		MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
	330	/* P3/Host Port config */
	331	MCFG_DEVICE_ADD ("aciahost", ACIA6850, 0)
	332	MCFG_DEVICE_ADD ("aciahost_clock", CLOCK, ACIA_CLOCK)
	333	MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (force68k_state, write_aciahost_clock))
237	334
238		/* P5/Remote Port config */
239		MCFG_DEVICE_ADD("aciaremt", ACIA6850, 0)
	335	/* P4/Terminal Port config */
	336	MCFG_DEVICE_ADD ("aciaterm", ACIA6850, 0)
240	337
241		#define PRINTER 0
242		#if PRINTER
243		MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232rmt", rs232_port_device, write_txd))
244		MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232rmt", rs232_port_device, write_rts))
	338	MCFG_ACIA6850_TXD_HANDLER (DEVWRITELINE ("rs232trm", rs232_port_device, write_txd))
	339	MCFG_ACIA6850_RTS_HANDLER (DEVWRITELINE ("rs232trm", rs232_port_device, write_rts))
245	340
246		MCFG_RS232_PORT_ADD("rs232rmt", default_rs232_devices, "printer")
247		MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_rxd))
248		MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_cts))
249		#endif
	341	MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
	342	MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("aciaterm", acia6850_device, write_rxd))
	343	MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("aciaterm", acia6850_device, write_cts))
250	344
251		MCFG_DEVICE_ADD("aciaremt_clock", CLOCK, ACIA_CLOCK)
252		MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
	345	MCFG_DEVICE_ADD ("aciaterm_clock", CLOCK, ACIA_CLOCK)
	346	MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (force68k_state, write_aciaterm_clock))
253	347
254		/* RTC Real Time Clock device */
255		MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz)
	348	/* P5/Remote Port config */
	349	MCFG_DEVICE_ADD ("aciaremt", ACIA6850, 0)
256	350
257		/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
258		MCFG_DEVICE_ADD("pit", PIT68230, XTAL_16MHz / 2)
	351	MCFG_DEVICE_ADD ("aciaremt_clock", CLOCK, ACIA_CLOCK)
	352	MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (force68k_state, write_aciaterm_clock))
259	353
260		MACHINE_CONFIG_END
	354	/* RTC Real Time Clock device */
	355	MCFG_DEVICE_ADD ("rtc", MM58167, XTAL_32_768kHz)
261	356
262		#if 0
	357	/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
	358	MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_16MHz / 2)
	359	MCFG_PIT68230_PA_OUTPUT_CALLBACK (DEVWRITE8 ("cent_data_out", output_latch_device, write))
	360	MCFG_PIT68230_H2_CALLBACK (DEVWRITELINE ("centronics", centronics_device, write_strobe))
263	361
264		static MACHINE_CONFIG_START( fccpu6, force68k_state )
265		MCFG_CPU_ADD("maincpu", M68000, XTAL_8MHz) /* Jumper B10 Mode B */
266		MCFG_CPU_PROGRAM_MAP(force68k_mem)
	362	// centronics
	363	MCFG_CENTRONICS_ADD ("centronics", centronics_devices, "printer")
	364	MCFG_CENTRONICS_ACK_HANDLER (WRITELINE (force68k_state, centronics_ack_w))
	365	MCFG_CENTRONICS_BUSY_HANDLER (WRITELINE (force68k_state, centronics_busy_w))
	366	MCFG_CENTRONICS_PERROR_HANDLER (WRITELINE (force68k_state, centronics_perror_w))
	367	MCFG_CENTRONICS_SELECT_HANDLER (WRITELINE (force68k_state, centronics_select_w))
	368	MCFG_CENTRONICS_OUTPUT_LATCH_ADD ("cent_data_out", "centronics")
267	369	MACHINE_CONFIG_END
268	370
269		static MACHINE_CONFIG_START( fccpu6a, force68k_state )
270		MCFG_CPU_ADD("maincpu", M68000, XTAL_12_5MHz) /* Jumper B10 Mode A */
271		MCFG_CPU_PROGRAM_MAP(force68k_mem)
	371	#if 0 /*
	372	* CPU-6 family is device and adressmap compatible with CPU-1 but with additions
	373	* such as an optional 68881 FPU
	374	*/
	375	static MACHINE_CONFIG_START (fccpu6, force68k_state)
	376	MCFG_CPU_ADD ("maincpu", M68000, XTAL_8MHz) /* Jumper B10 Mode B */
	377	MCFG_CPU_PROGRAM_MAP (force68k_mem)
272	378	MACHINE_CONFIG_END
273	379
274		static MACHINE_CONFIG_START( fccpu6v, force68k_state )
275		MCFG_CPU_ADD("maincpu", M68010, XTAL_8MHz) /* Jumper B10 Mode B */
276		MCFG_CPU_PROGRAM_MAP(force68k_mem)
	380	static MACHINE_CONFIG_START (fccpu6a, force68k_state)
	381	MCFG_CPU_ADD ("maincpu", M68000, XTAL_12_5MHz) /* Jumper B10 Mode A */
	382	MCFG_CPU_PROGRAM_MAP (force68k_mem)
277	383	MACHINE_CONFIG_END
278	384
279		static MACHINE_CONFIG_START( fccpu6va, force68k_state )
280		MCFG_CPU_ADD("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
281		MCFG_CPU_PROGRAM_MAP(force68k_mem)
	385	static MACHINE_CONFIG_START (fccpu6v, force68k_state)
	386	MCFG_CPU_ADD ("maincpu", M68010, XTAL_8MHz) /* Jumper B10 Mode B */
	387	MCFG_CPU_PROGRAM_MAP (force68k_mem)
282	388	MACHINE_CONFIG_END
283	389
284		static MACHINE_CONFIG_START( fccpu6vb, force68k_state )
285		MCFG_CPU_ADD("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
286		MCFG_CPU_PROGRAM_MAP(force68k_mem)
	390	static MACHINE_CONFIG_START (fccpu6va, force68k_state)
	391	MCFG_CPU_ADD ("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
	392	MCFG_CPU_PROGRAM_MAP (force68k_mem)
287	393	MACHINE_CONFIG_END
	394
	395	static MACHINE_CONFIG_START (fccpu6vb, force68k_state)
	396	MCFG_CPU_ADD ("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
	397	MCFG_CPU_PROGRAM_MAP (force68k_mem)
	398	MACHINE_CONFIG_END
288	399	#endif
289	400
290	401	/* ROM definitions */
291		ROM_START( fccpu1 )
292		ROM_REGION(0x1000000, "maincpu", 0)
	402	ROM_START (fccpu1)
	403	ROM_REGION (0x1000000, "maincpu", 0)
293	404
294		ROM_LOAD16_BYTE( "fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC(3ac6f08f) SHA1(502f6547b508d8732bd68bbbb2402d8c30fefc3b) )
295		ROM_LOAD16_BYTE( "fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC(035315fb) SHA1(90dc44d9c25d28428233e6846da6edce2d69e440) )
296		/* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
297		from a CPU-1 board so some features might be missing or different)
298		---------------------------------------------------------------------------
299		BF <address1> <address2> <data> <CR> Block Fill memory - from addr1 through addr2 with data
300		BM <address1> <address2> <address 3> <CR> Block Move - move from addr1 through addr2to addr3
301		BR [<address> [; <count>] ... ] <CR> Set/display Breakpoint
302		BS <address1> <address2> <data> <CR> Block Search - search addr1 through addr2 for data
303		BT <address1> <address2> <CR> Block Test of memory
304		DC <expression> <CR> Data Conversion
305		DF <CR> Display Formatted registers
306		DU [n] <address1> <address2>[<string>] <CR> Dump memory to object file
307		GO [<address] <CR> Execute program
308		GD [<address] <CR> Go Direct
309		GT <address> <CR> Exec prog: temporary breakpoint
310		HE<CR> Help; display monitor commands
311		LO [n] [;<options] <CR> Load Object file
312		MD <address> [<count?? <CR> Memory Display
313		MM <address> [<data?? [;<options?? <CR> Memory Modify
314		MS <address> <data1 > <data2> < ... <CR> Memory Set - starting at addr with data 1. data 2 ...
315		NOBR [<address> ... ] <CR> Remove Breakpoint
316		NOPA <CR> Printer Detach (Centronics on PIT/P2)
317		OF <CR> Offset
318		PA <CR> Printer Attach (Centronics on PIT/P2)
319		PF[n] <CR> Set/display Port Format
320		RM <CR> Register Modify
321		TM [<exit character?? <CR> Transparent Mode
322		TR [<count] <CR> Trace
323		TT <address> <CR> Trace: temporary breakpoint
324		VE [n] [<string] <CR> Verify memory/object file
325		----------------------------------------------------------------------------
326		.AO - .A7 [<expression] <CR> Display/set address register
327		.00 - .07 [<expression] <CR> Display/set data register
328		.RO - .R6 [<expression] <CR> Display/set offset register
329		.PC [<expression] <CR> Display/set program counter
330		.SR [<expression] <CR> Display/set status register
331		.SS [<expression] <CR> Display/set supervisor stack
332		.US [<expression] <CR> Display/set user stack
333		----------------------------------------------------------------------------
334		MD <address> [<count>]; D1 <CR> Disassemble memory location
335		MM <address>; DI <CR> Disassemble/Assemble memory location
336		----------------------------------------------------------------------------
337		*/
	405	ROM_LOAD16_BYTE ("fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC (3ac6f08f) SHA1 (502f6547b508d8732bd68bbbb2402d8c30fefc3b))
	406	ROM_LOAD16_BYTE ("fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC (035315fb) SHA1 (90dc44d9c25d28428233e6846da6edce2d69e440))
	407
	408	/*
	409	* System ROM terminal commands
	410	*
	411	* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
	412	* from a CPU-1 board so some features might be missing or different)
	413	* ---------------------------------------------------------------------------
	414	* BF <address1> <address2> <data> <CR> Block Fill memory - from addr1 through addr2 with data
	415	* BM <address1> <address2> <address 3> <CR> Block Move - move from addr1 through addr2to addr3
	416	* BR [<address> [; <count>] ... ] <CR> Set/display Breakpoint
	417	* BS <address1> <address2> <data> <CR> Block Search - search addr1 through addr2 for data
	418	* BT <address1> <address2> <CR> Block Test of memory
	419	* DC <expression> <CR> Data Conversion
	420	* DF <CR> Display Formatted registers
	421	* DU [n] <address1> <address2>[<string>] <CR> Dump memory to object file
	422	* GO [<address] <CR> Execute program
	423	* GD [<address] <CR> Go Direct
	424	* GT <address> <CR> Exec prog: temporary breakpoint
	425	* HE<CR> Help; display monitor commands
	426	* LO [n] [;<options] <CR> Load Object file
	427	* MD <address> [<count» <CR> Memory Display
	428	* MM <address> [<data» [;<options» <CR> Memory Modify
	429	* MS <address> <data1 > <data2> < ... <CR> Memory Set - starting at addr with data 1. data 2 ...
	430	* NOBR [<address> ... ] <CR> Remove Breakpoint
	431	* NOPA <CR> Printer Detach (Centronics on PIT/P2)
	432	* OF <CR> Offset
	433	* PA <CR> Printer Attach (Centronics on PIT/P2)
	434	* PF[n] <CR> Set/display Port Format
	435	* RM <CR> Register Modify
	436	* TM [<exit character» <CR> Transparent Mode
	437	* TR [<count] <CR> Trace
	438	* TT <address> <CR> Trace: temporary breakpoint
	439	* VE [n] [<string] <CR> Verify memory/object file
	440	* ----------------------------------------------------------------------------
	441	* .AO - .A7 [<expression] <CR> Display/set address register
	442	* .00 - .07 [<expression] <CR> Display/set data register
	443	* .RO - .R6 [<expression] <CR> Display/set offset register
	444	* .PC [<expression] <CR> Display/set program counter
	445	* .SR [<expression] <CR> Display/set status register
	446	* .SS [<expression] <CR> Display/set supervisor stack
	447	* .US [<expression] <CR> Display/set user stack
	448	* ----------------------------------------------------------------------------
	449	* MD <address> [<count>]; D1 <CR> Disassemble memory location
	450	* MM <address>; DI <CR> Disassemble/Assemble memory location
	451	* ----------------------------------------------------------------------------
	452	*/
338	453	ROM_END
339	454
	455	/*
	456	* CPU-6 ROMs were generally based om VMEPROM which contained the PDOS RTOS from Eyring Research.
	457	* I don't have these but if anyone can dump them and send to me I can verify that they work as expected.
	458	*/
340	459	#if 0
341		ROM_START( fccpu6 )
342		ROM_REGION(0x1000000, "maincpu", 0)
	460	ROM_START (fccpu6)
	461	ROM_REGION (0x1000000, "maincpu", 0)
343	462	ROM_END
344	463
345		ROM_START( fccpu6a )
346		ROM_REGION(0x1000000, "maincpu", 0)
	464	ROM_START (fccpu6a)
	465	ROM_REGION (0x1000000, "maincpu", 0)
347	466	ROM_END
348	467
349		ROM_START( fccpu6v )
350		ROM_REGION(0x1000000, "maincpu", 0)
	468	ROM_START (fccpu6v)
	469	ROM_REGION (0x1000000, "maincpu", 0)
351	470	ROM_END
352	471
353		ROM_START( fccpu6va )
354		ROM_REGION(0x1000000, "maincpu", 0)
	472	ROM_START (fccpu6va)
	473	ROM_REGION (0x1000000, "maincpu", 0)
355	474	ROM_END
356	475
357		ROM_START( fccpu6vb )
358		ROM_REGION(0x1000000, "maincpu", 0)
	476	ROM_START (fccpu6vb)
	477	ROM_REGION (0x1000000, "maincpu", 0)
359	478	ROM_END
360	479	#endif
361	480

trunk/src/mess/drivers/mc1000.c
r249038	r249039
378	378	+---------------o V+
379	379	\| \| \|
380	380	+-+ \| \|
381		\| \|390K \| \|
	381	\| \|309K \| \|
382	382	\| \|R17 \|8 \|4
383	383	+-+ +-------+
384	384	\| 7\| \|3
r249038	r249039
390	390	\| \| \| \| 555 \|
391	391	+-+ \| \| \|
392	392	\| \| 6\| \|5
393		------\| \|---+
	393	----?-\| \|---+
394	394	\| \| \| \|
395	395	---C30 +-------+ ---C29
396		---10n \|1 ---10n
	396	---103 \|1 ---103
397	397	_\|_ _\|_ _\|_
398	398	/// /// ///
399	399
400	400	Calculated properties:
401	401
402	402	* 99.74489795918367 Duty Cycle Percentage
403		* 367.34693~~87755~~102 Frequency in Hertz
	403	* 368.1126130105722 Frequency in Hertz
404	404	* 0.00000693 Seconds Low
405		* 0.00270963 Seconds High
	405	* 0.0027096299999999998 Seconds High
406	406
407	407	*/
408	408
409		#define MC1000_NE555_FREQ (367) /* Hz */
	409	#define MC1000_NE555_FREQ (368) /* Hz */
410	410	#define MC1000_NE555_DUTY_CYCLE (99.745) /* % */
411	411
412	412	TIMER_DEVICE_CALLBACK_MEMBER(mc1000_state::ne555_tick)

trunk/src/osd/modules/debugger/win/debugviewinfo.c
r249038	r249039
15	15
16	16	#include "strconv.h"
17	17
18		#include "winutil.h"
19	18
20
21	19	// debugger view styles
22	20	#define DEBUG_VIEW_STYLE WS_CHILD \| WS_VISIBLE \| WS_CLIPCHILDREN
23	21	#define DEBUG_VIEW_STYLE_EX 0
r249038	r249039
50	48
51	49	// create the child view
52	50	m_wnd = CreateWindowEx(DEBUG_VIEW_STYLE_EX, TEXT("MAMEDebugView"), NULL, DEBUG_VIEW_STYLE,
53		0, 0, 100, 100, parent, NULL, GetModuleHandle~~Uni~~(), this);
	51	0, 0, 100, 100, parent, NULL, GetModuleHandle(NULL), this);
54	52	if (m_wnd == NULL)
55	53	goto cleanup;
56	54
57	55	// create the scroll bars
58	56	m_hscroll = CreateWindowEx(HSCROLL_STYLE_EX, TEXT("SCROLLBAR"), NULL, HSCROLL_STYLE,
59		0, 0, 100, CW_USEDEFAULT, m_wnd, NULL, GetModuleHandle~~Uni~~(), this);
	57	0, 0, 100, CW_USEDEFAULT, m_wnd, NULL, GetModuleHandle(NULL), this);
60	58	m_vscroll = CreateWindowEx(VSCROLL_STYLE_EX, TEXT("SCROLLBAR"), NULL, VSCROLL_STYLE,
61		0, 0, CW_USEDEFAULT, 100, m_wnd, NULL, GetModuleHandle~~Uni~~(), this);
	59	0, 0, CW_USEDEFAULT, 100, m_wnd, NULL, GetModuleHandle(NULL), this);
62	60	if ((m_hscroll == NULL) \|\| (m_vscroll == NULL))
63	61	goto cleanup;
64	62
r249038	r249039
256	254	{
257	255	// create a combo box
258	256	HWND const result = CreateWindowEx(COMBO_BOX_STYLE_EX, TEXT("COMBOBOX"), NULL, COMBO_BOX_STYLE,
259		0, 0, 100, 1000, parent, NULL, GetModuleHandle~~Uni~~(), NULL);
	257	0, 0, 100, 1000, parent, NULL, GetModuleHandle(NULL), NULL);
260	258	SetWindowLongPtr(result, GWLP_USERDATA, userdata);
261	259	SendMessage(result, WM_SETFONT, (WPARAM)metrics().debug_font(), (LPARAM)FALSE);
262	260
r249038	r249039
791	789
792	790	// initialize the description of the window class
793	791	wc.lpszClassName = TEXT("MAMEDebugView");
794		wc.hInstance = GetModuleHandle~~Uni~~();
	792	wc.hInstance = GetModuleHandle(NULL);
795	793	wc.lpfnWndProc = &debugview_info::static_view_proc;
796	794	wc.hCursor = LoadCursor(NULL, IDC_ARROW);
797	795	wc.hIcon = LoadIcon(wc.hInstance, MAKEINTRESOURCE(2));
r249038	r249039
800	798	wc.style = 0;
801	799	wc.cbClsExtra = 0;
802	800	wc.cbWndExtra = 0;
803
804		UnregisterClass(wc.lpszClassName, wc.hInstance);
805	801
806	802	// register the class; fail if we can't
807	803	if (!RegisterClass(&wc))

trunk/src/osd/modules/debugger/win/debugwininfo.c
r249038	r249039
17	17	#include "window.h"
18	18	#include "winutf8.h"
19	19
20		#include "winutil.h"
21	20
22
23	21	bool debugwin_info::s_window_class_registered = false;
24	22
25	23
r249038	r249039
38	36	register_window_class();
39	37
40	38	m_wnd = win_create_window_ex_utf8(DEBUG_WINDOW_STYLE_EX, "MAMEDebugWindow", title, DEBUG_WINDOW_STYLE,
41		0, 0, 100, 100, win_window_list->m_hwnd, create_standard_menubar(), GetModuleHandle~~Uni~~(), this);
	39	0, 0, 100, 100, win_window_list->m_hwnd, create_standard_menubar(), GetModuleHandle(NULL), this);
42	40	if (m_wnd == NULL)
43	41	return;
44	42
r249038	r249039
582	580
583	581	// initialize the description of the window class
584	582	wc.lpszClassName = TEXT("MAMEDebugWindow");
585		wc.hInstance = GetModuleHandle~~Uni~~();
	583	wc.hInstance = GetModuleHandle(NULL);
586	584	wc.lpfnWndProc = &debugwin_info::static_window_proc;
587	585	wc.hCursor = LoadCursor(NULL, IDC_ARROW);
588	586	wc.hIcon = LoadIcon(wc.hInstance, MAKEINTRESOURCE(2));
r249038	r249039
591	589	wc.style = 0;
592	590	wc.cbClsExtra = 0;
593	591	wc.cbWndExtra = 0;
594
595		UnregisterClass(wc.lpszClassName, wc.hInstance);
596	592
597	593	// register the class; fail if we can't
598	594	if (!RegisterClass(&wc))

trunk/src/osd/modules/debugger/win/editwininfo.c
r249038	r249039
13	13
14	14	#include "strconv.h"
15	15
16		#include "winutil.h"
17	16
18
19	17	// edit box styles
20	18	#define EDIT_BOX_STYLE WS_CHILD \| WS_VISIBLE \| ES_AUTOHSCROLL
21	19	#define EDIT_BOX_STYLE_EX 0
r249038	r249039
34	32
35	33	// create an edit box and override its key handling
36	34	m_editwnd = CreateWindowEx(EDIT_BOX_STYLE_EX, TEXT("EDIT"), NULL, EDIT_BOX_STYLE,
37		0, 0, 100, 100, window(), NULL, GetModuleHandle~~Uni~~(), NULL);
	35	0, 0, 100, 100, window(), NULL, GetModuleHandle(NULL), NULL);
38	36	m_original_editproc = (WNDPROC)(FPTR)GetWindowLongPtr(m_editwnd, GWLP_WNDPROC);
39	37	SetWindowLongPtr(m_editwnd, GWLP_USERDATA, (LONG_PTR)this);
40	38	SetWindowLongPtr(m_editwnd, GWLP_WNDPROC, (LONG_PTR)&editwin_info::static_edit_proc);

trunk/src/osd/windows/input.c
r249038	r249039
38	38	#include "strconv.h"
39	39	#include "config.h"
40	40
41		#include "winutil.h"
42
43	41	//============================================================
44	42	// PARAMETERS
45	43	//============================================================
r249038	r249039
1119	1117	int didevtype_joystick = DI8DEVCLASS_GAMECTRL;
1120	1118
1121	1119	dinput_version = DIRECTINPUT_VERSION;
1122		result = DirectInput8Create(GetModuleHandle~~Uni~~(), dinput_version, IID_IDirectInput8, (void **)&dinput, NULL);
	1120	result = DirectInput8Create(GetModuleHandle(NULL), dinput_version, IID_IDirectInput8, (void **)&dinput, NULL);
1123	1121	if (result != DI_OK)
1124	1122	{
1125	1123	dinput_version = 0;
r249038	r249039
1132	1130
1133	1131	// first attempt to initialize DirectInput at the current version
1134	1132	dinput_version = DIRECTINPUT_VERSION;
1135		result = DirectInputCreate(GetModuleHandle~~Uni~~(), dinput_version, &dinput, NULL);
	1133	result = DirectInputCreate(GetModuleHandle(NULL), dinput_version, &dinput, NULL);
1136	1134	if (result != DI_OK)
1137	1135	{
1138	1136	// if that fails, try version 5
1139	1137	dinput_version = 0x0500;
1140		result = DirectInputCreate(GetModuleHandle~~Uni~~(), dinput_version, &dinput, NULL);
	1138	result = DirectInputCreate(GetModuleHandle(NULL), dinput_version, &dinput, NULL);
1141	1139	if (result != DI_OK)
1142	1140	{
1143	1141	// if that fails, try version 3
1144	1142	dinput_version = 0x0300;
1145		result = DirectInputCreate(GetModuleHandle~~Uni~~(), dinput_version, &dinput, NULL);
	1143	result = DirectInputCreate(GetModuleHandle(NULL), dinput_version, &dinput, NULL);
1146	1144	if (result != DI_OK)
1147	1145	{
1148	1146	dinput_version = 0;

trunk/src/osd/windows/output.c
r249038	r249039
17	17	// MAMEOS headers
18	18	#include "output.h"
19	19
20		#include "winutil.h"
21	20
22	21
23
24	22	//============================================================
25	23	// CONSTANTS
26	24	//============================================================
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103	101	1, 1,
104	102	NULL,
105	103	NULL,
106		GetModuleHandle~~Uni~~(),
	104	GetModuleHandle(NULL),
107	105	NULL);
108	106	assert(output_hwnd != NULL);
109	107
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169	167
170	168	// initialize the description of the window class
171	169	wc.lpszClassName = OUTPUT_WINDOW_CLASS;
172		wc.hInstance = GetModuleHandle~~Uni~~();
	170	wc.hInstance = GetModuleHandle(NULL);
173	171	wc.lpfnWndProc = output_window_proc;
174
175		UnregisterClass(wc.lpszClassName, wc.hInstance);
176	172
177	173	// register the class; fail if we can't
178	174	if (!RegisterClass(&wc))

trunk/src/osd/windows/window.c
r249038	r249039
35	35	#include "config.h"
36	36	#include "winutf8.h"
37	37
38		#include "winutil.h"
39
40	38	extern int drawnone_init(running_machine &machine, osd_draw_callbacks *callbacks);
41	39	extern int drawgdi_init(running_machine &machine, osd_draw_callbacks *callbacks);
42	40	extern int drawdd_init(running_machine &machine, osd_draw_callbacks *callbacks);
r249038	r249039
887	885
888	886	// initialize the description of the window class
889	887	wc.lpszClassName = TEXT("MAME");
890		wc.hInstance = GetModuleHandle~~Uni~~();
	888	wc.hInstance = GetModuleHandle(NULL);
891	889	wc.lpfnWndProc = winwindow_video_window_proc_ui;
892	890	wc.hCursor = LoadCursor(NULL, IDC_ARROW);
893	891	wc.hIcon = LoadIcon(wc.hInstance, MAKEINTRESOURCE(2));
894
895		UnregisterClass(wc.lpszClassName, wc.hInstance);
896	892
897	893	// register the class; fail if we can't
898	894	if (!RegisterClass(&wc))
r249038	r249039
1195	1191	monitorbounds.left() + 100, monitorbounds.top() + 100,
1196	1192	NULL,//(win_window_list != NULL) ? win_window_list->m_hwnd : NULL,
1197	1193	menu,
1198		GetModuleHandle~~Uni~~(),
	1194	GetModuleHandle(NULL),
1199	1195	NULL);
1200	1196	if (m_hwnd == NULL)
1201	1197	return 1;

trunk/src/osd/windows/winmain.c
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1321	1321	dynamic_bind<PIMAGE_NT_HEADERS (WINAPI *)(PVOID)> image_nt_header(TEXT("dbghelp.dll"), "ImageNtHeader");
1322	1322
1323	1323	// start with the image base
1324		PVOID base = reinterpret_cast<PVOID>(GetModuleHandle~~Uni~~());
	1324	PVOID base = reinterpret_cast<PVOID>(GetModuleHandle(NULL));
1325	1325	assert(base != NULL);
1326	1326
1327	1327	// make sure we have the functions we need

trunk/src/osd/windows/winutil.c
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92	92	is_first_time = FALSE;
93	93
94	94	// get the current module
95		module = GetModuleHandle~~Uni~~();
	95	module = GetModuleHandle(NULL);
96	96	if (!module)
97	97	return FALSE;
98	98	image_ptr = (BYTE*) module;
r249038	r249039
122	122	}
123	123	return is_gui_frontend;
124	124	}
125
126		//-------------------------------------------------
127		// Universal way to get module handle
128		//-------------------------------------------------
129
130		HMODULE WINAPI GetModuleHandleUni()
131		{
132		MEMORY_BASIC_INFORMATION mbi;
133		VirtualQuery((LPCVOID)GetModuleHandleUni, &mbi, sizeof(mbi));
134		return (HMODULE)mbi.AllocationBase;
135		}

trunk/src/osd/windows/winutil.h
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15	15	file_error win_error_to_file_error(DWORD error);
16	16	osd_dir_entry_type win_attributes_to_entry_type(DWORD attributes);
17	17	BOOL win_is_gui_application(void);
18		HMODULE WINAPI GetModuleHandleUni();
19	18
20	19	#endif // __WINUTIL__

https://github.com/mamedev/mame/commit/cab1a4046714dc7ebf052676f11dc97ba3defe50

199869 Revisions