MAME SVN History

199869 Revisions

r40514 Friday 28th August, 2015 at 16:54:57 UTC by R. Belmont
Merge pull request #289 from DrMefistO/master Fixed GetModuleHandle to be universal.

[/trunk]	.gitignore
[hash]	gameking.xml
[scripts/target/mame]	arcade.lua
[src]	version.c
[src/emu]	attotime.h emuopts.c screen.h
[src/emu/bus/c64]	c128_partner.c c128_partner.h
[src/emu/bus/msx_cart]	fs_sr022.c
[src/emu/bus/ti99_peb]	hfdc.c hfdc.h
[src/emu/cpu/h8]	h8_timer16.c
[src/emu/cpu/pdp8]	pdp8.c
[src/emu/cpu/tms32082]	mp_ops.c tms32082.c
[src/emu/cpu/ucom4]	ucom4.c
[src/emu/drivers]	emudummy.c
[src/emu/machine]	i8251.c i8251.h intelfsh.c tms6100.c
[src/emu/netlist]	nl_base.c nl_base.h nl_setup.h
[src/emu/netlist/plib]	pconfig.h pstream.c pstring.c pstring.h
[src/emu/netlist/prg]	nltool.c nlwav.c
[src/emu/netlist/solver]	nld_ms_direct.h nld_ms_direct_lu.h nld_solver.h
[src/emu/sound]	rf5c400.c tms5110.c tms5110.h tms5220.c tms5220.h
[src/mame]	arcade.lst mess.lst
[src/mame/audio]	targ.c
[src/mame/drivers]	ajax.c aliens.c blockhl.c chexx.c* chqflag.c cobra.c crimfght.c deco32.c ~~faceoffh.c~~ fcrash.c firebeat.c gunsmoke.c joystand.c kaneko16.c konendev.c lethalj.c megasys1.c midxunit.c minivadr.c namcos10.c namcos12.c naomi.c norautp.c pacman.c quantum.c rollext.c royalmah.c seattle.c simpsons.c spcforce.c thedealr.c toaplan2.c vegas.c xyonix.c
[src/mame/includes]	chihiro.h gaelco2.h hng64.h rocnrope.h xbox.h
[src/mame/layout]	aquastge.lay chexx.lay*
[src/mame/machine]	dc-ctrl.c iteagle_fpga.c ns10crypt.c ns10crypt.h pgmcrypt.c xbox.c
[src/mame/video]	bottom9.c chihiro.c k052109.h k057714.c macrossp.c midzeus.c
[src/mess/drivers]	apple2.c hh_hmcs40.c hh_tms1k.c hh_ucom4.c hp64k.c hp_ipc.c ngen.c tispeak.c xbox.c
[src/mess/includes]	aussiebyte.h thomson.h
[src/mess/machine]	coco.c
[src/mess/video]	aussiebyte.c

trunk/.gitignore
r249025	r249026
1	1	*~
2	2	/*
3		!/*/
	3	/*/
	4	!/3rdparty/
	5	!/artwork/
	6	!/docs/
	7	!/hash/
	8	!/hlsl/
	9	!/keymaps/
	10	!/nl_examples/
	11	!/samples/
	12	!/scripts/
	13	!/src/
	14	!/tests/
	15	!/web/
4	16	!/.gitattributes
5	17	!/.gitignore
6	18	!/.travis.yml
7	19	!/makefile
8		!/mame.doxygen
	20	!/mame.doxygen
9	21	!/*.md
10		/cfg
11		/diff
12		/ini
13		/inp
14		/nvram
15		/obj
16		/roms
17		/snap
18	22	src/regtests/chdman/temp
19	23	src/regtests/jedutil/output
20		/sta
21		*.pyc
22		/build
23		/documentation
		No newline at end of file
	24	*.pyc
		No newline at end of file

trunk/hash/gameking.xml
r249025	r249026
227	227	</software>
228	228
229	229	<!-- Same hashes as trojanl, why is there a new entry?
230		<software name="trojanla" cloneof="trojanl" supported="no">
231		<description>Trojan Legend (Alt Revision)</description>
232		<year>200?</year>
233		<publisher>TimeTop</publisher>
234		<part name="cart" interface="gameking_cart">
235		<dataarea name="rom" size="131072">
236		<rom name="trojan legend (alt).bin" size="131072" crc="b832db4f" sha1="5a152bfb2ba2150cff9dc66729ceadc0b47d4f17" offset="0x00000" />
237		</dataarea>
238		</part>
239		</software>
	230	<software name="trojanla" cloneof="trojanl" supported="no">
	231	<description>Trojan Legend (Alt Revision)</description>
	232	<year>200?</year>
	233	<publisher>TimeTop</publisher>
	234	<part name="cart" interface="gameking_cart">
	235	<dataarea name="rom" size="131072">
	236	<rom name="trojan legend (alt).bin" size="131072" crc="b832db4f" sha1="5a152bfb2ba2150cff9dc66729ceadc0b47d4f17" offset="0x00000" />
	237	</dataarea>
	238	</part>
	239	</software>
240	240	-->
241	241
242	242

trunk/scripts/target/mame/arcade.lua
r249025	r249026
3332	3332	MAME_DIR .. "src/mame/machine/cdicdic.c",
3333	3333	MAME_DIR .. "src/mame/drivers/cesclass.c",
3334	3334	MAME_DIR .. "src/mame/drivers/chance32.c",
	3335	MAME_DIR .. "src/mame/drivers/chexx.c",
3335	3336	MAME_DIR .. "src/mame/drivers/chicago.c",
3336	3337	MAME_DIR .. "src/mame/drivers/chsuper.c",
3337	3338	MAME_DIR .. "src/mame/drivers/cidelsa.c",
r249025	r249026
3378	3379	MAME_DIR .. "src/mame/video/esripsys.c",
3379	3380	MAME_DIR .. "src/mame/drivers/ettrivia.c",
3380	3381	MAME_DIR .. "src/mame/drivers/extrema.c",
3381		MAME_DIR .. "src/mame/drivers/faceoffh.c",
3382	3382	MAME_DIR .. "src/mame/drivers/fireball.c",
3383	3383	MAME_DIR .. "src/mame/drivers/flipjack.c",
3384	3384	MAME_DIR .. "src/mame/drivers/flower.c",

trunk/src/emu/attotime.h
r249025	r249026
121	121
122	122	void normalize()
123	123	{
124		while (m_attoseconds >= ATTOSECONDS_PER_SECOND)
125		{
126		m_seconds++;
127		m_attoseconds -= ATTOSECONDS_PER_SECOND;
128		}
	124	while (m_attoseconds >= ATTOSECONDS_PER_SECOND)
	125	{
	126	m_seconds++;
	127	m_attoseconds -= ATTOSECONDS_PER_SECOND;
	128	}
129	129	}
130	130
131	131	attoseconds_t attoseconds() const { return m_attoseconds; }

trunk/src/emu/bus/c64/c128_partner.c
r249025	r249026
2	2	// copyright-holders:Curt Coder
3	3	/**********************************************************************
4	4
5		Timeworks PARTNER 128 cartridge emulation
	5	Timeworks PARTNER 128 cartridge emulation
6	6
7	7	**********************************************************************/
8	8
9	9	/*
10	10
11		PCB Layout
12		----------
	11	PCB Layout
	12	----------
13	13
14		\|---------------\|
15		\|LS74 SW * \|
16		\|LS09 LS273\|
17		\|LS139 RAM \|
18		\|LS133 \|
19		\| LS240 \|
20		\|LS33 ROM \|
21		\|LS09 \|
22		\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|
	14	\|---------------\|
	15	\|LS74 SW * \|
	16	\|LS09 LS273\|
	17	\|LS139 RAM \|
	18	\|LS133 \|
	19	\| LS240 \|
	20	\|LS33 ROM \|
	21	\|LS09 \|
	22	\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|
23	23
24		ROM - Toshiba TMM24128AP 16Kx8 EPROM (blank label)
25		RAM - Sony CXK5864PN-15L 8Kx8 SRAM
26		SW - push button switch
27		* - solder point for joystick port dongle
	24	ROM - Toshiba TMM24128AP 16Kx8 EPROM (blank label)
	25	RAM - Sony CXK5864PN-15L 8Kx8 SRAM
	26	SW - push button switch
	27	* - solder point for joystick port dongle
28	28
29	29	*/
30	30
r249025	r249026
193	193	{
194	194	/*
195	195
196		bit description
	196	bit description
197	197
198		0 RAM A7
199		1 RAM A8
200		2 RAM A9
201		3 RAM A10
202		4 RAM A11
203		5 RAM A12
204		6 LS74 1Cd,2Cd
205		7 N/C
	198	0 RAM A7
	199	1 RAM A8
	200	2 RAM A9
	201	3 RAM A10
	202	4 RAM A11
	203	5 RAM A12
	204	6 LS74 1Cd,2Cd
	205	7 N/C
206	206
207	207	*/
208	208

trunk/src/emu/bus/c64/c128_partner.h
r249025	r249026
24	24	// ======================> partner128_t
25	25
26	26	class partner128_t : public device_t,
27		public device_c64_expansion_card_interface
28		//public device_vcs_control_port_interface
	27	public device_c64_expansion_card_interface
	28	//public device_vcs_control_port_interface
29	29	{
30	30	public:
31	31	// construction/destruction

trunk/src/emu/bus/msx_cart/fs_sr022.c
r249025	r249026
69	69	break;
70	70	}
71	71	}
72

trunk/src/emu/bus/ti99_peb/hfdc.c
r249025	r249026
350	350
351	351	7 6 5 4 3 2 1 0
352	352	+-----+-----+-----+-----+-----+-----+-----+-----+
353		\| 0 \| 0 \| 0 \| 0 \| 0 \| MON \| DIP \| IRQ \|
	353	\| 0 \| 0 \| 0 \| 0 \| WAIT\| MON*\| DIP \| IRQ \|
354	354	+-----+-----+-----+-----+-----+-----+-----+-----+
355	355
356		MON = Motor on
	356	WAIT = Wait for WDS1 to become ready
	357	MON* = Motor on
357	358	DIP = DMA in progress
358	359	IRQ = Interrupt request
359	360	---
r249025	r249026
375	376	reply = 0;
376	377	if (m_irq == ASSERT_LINE) reply \|= 0x01;
377	378	if (m_dip == ASSERT_LINE) reply \|= 0x02;
378		if (m_motor_running) reply \|= 0x04;
	379	if (!m_motor_running) reply \|= 0x04;
	380	if (m_wait_for_hd1) reply \|= 0x08;
379	381	}
380	382	*value = reply;
381	383	}
r249025	r249026
888	890	}
889	891
890	892	m_cru_base = ioport("CRUHFDC")->read();
	893	m_wait_for_hd1 = ioport("WAITHD1")->read();
891	894
892	895	// Resetting values
893	896	m_rom_page = 0;
r249025	r249026
956	959	the drives 1 to 4 are renamed to DSK5-DSK8 (see [1] p. 7).
957	960	*/
958	961	INPUT_PORTS_START( ti99_hfdc )
	962	PORT_START( "WAITHD1" )
	963	PORT_DIPNAME( 0x01, 0x00, "HFDC Wait for HD1" )
	964	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
	965	PORT_DIPSETTING( 0x01, DEF_STR( On ) )
	966
959	967	PORT_START( "CRUHFDC" )
960	968	PORT_DIPNAME( 0x1f00, 0x1100, "HFDC CRU base" )
961	969	PORT_DIPSETTING( 0x1000, "1000" )

trunk/src/emu/bus/ti99_peb/hfdc.h
r249025	r249026
142	142	// DMA in progress
143	143	bool m_dma_in_progress;
144	144
	145	// Wait for HD. This was an addition in later cards.
	146	bool m_wait_for_hd1;
	147
145	148	// Device Service Routine ROM (firmware)
146	149	UINT8* m_dsrrom;
147	150

trunk/src/emu/cpu/h8/h8_timer16.c
r249025	r249026
164	164	{
165	165	intc = owner()->siblingdevice<h8_intc_device>(intc_tag);
166	166	channel_active = false;
167		c~~lock_typ~~e ~~= DIV~~_1;
	167	device_reset();
168	168
169	169	save_item(NAME(tgr_clearing));
170	170	save_item(NAME(tcr));

trunk/src/emu/cpu/pdp8/pdp8.c
r249025	r249026
12	12
13	13	CPU_DISASSEMBLE( pdp8 );
14	14
15		#define OP ((op >> 011) & 07)
	15	#define OP ((op >> 011) & 07)
16	16
17		#define MR_IND ((op >> 010) & 01)
18		#define MR_PAGE ((op >> 07) & 01)
19		#define MR_ADDR (op & 0177)
	17	#define MR_IND ((op >> 010) & 01)
	18	#define MR_PAGE ((op >> 07) & 01)
	19	#define MR_ADDR (op & 0177)
20	20
21		#define IOT_DEVICE ((op >> 03) & 077)
22		#define IOT_IOP1 (op & 01)
23		#define IOT_IOP2 ((op >> 01) & 01)
24		#define IOT_IOP4 ((op >> 02) & 01)
	21	#define IOT_DEVICE ((op >> 03) & 077)
	22	#define IOT_IOP1 (op & 01)
	23	#define IOT_IOP2 ((op >> 01) & 01)
	24	#define IOT_IOP4 ((op >> 02) & 01)
25	25
26		#define OPR_GROUP ((op >> 010) & 01)
27		#define OPR_CLA ((op >> 07) & 01)
28		#define OPR_CLL ((op >> 06) & 01)
29		#define OPR_CMA ((op >> 05) & 01)
30		#define OPR_CML ((op >> 04) & 01)
31		#define OPR_ROR ((op >> 03) & 01)
32		#define OPR_ROL ((op >> 02) & 01)
33		#define OPR_ROT2 ((op >> 01) & 01)
34		#define OPR_IAC (op & 01)
	26	#define OPR_GROUP ((op >> 010) & 01)
	27	#define OPR_CLA ((op >> 07) & 01)
	28	#define OPR_CLL ((op >> 06) & 01)
	29	#define OPR_CMA ((op >> 05) & 01)
	30	#define OPR_CML ((op >> 04) & 01)
	31	#define OPR_ROR ((op >> 03) & 01)
	32	#define OPR_ROL ((op >> 02) & 01)
	33	#define OPR_ROT2 ((op >> 01) & 01)
	34	#define OPR_IAC (op & 01)
35	35
36		#define OPR_SMA OPR_CLL
37		#define OPR_SZA OPR_CMA
38		#define OPR_SNL OPR_CML
39		#define OPR_REVSKIP OPR_ROR
40		#define OPR_OSR OPR_ROL
41		#define OPR_HLT OPR_ROT2
	36	#define OPR_SMA OPR_CLL
	37	#define OPR_SZA OPR_CMA
	38	#define OPR_SNL OPR_CML
	39	#define OPR_REVSKIP OPR_ROR
	40	#define OPR_OSR OPR_ROL
	41	#define OPR_HLT OPR_ROT2
42	42
43		#define OPR_GROUP_MASK 0401
44		#define OPR_GROUP1_VAL 0000
45		#define OPR_GROUP2_VAL 0400
	43	#define OPR_GROUP_MASK 0401
	44	#define OPR_GROUP1_VAL 0000
	45	#define OPR_GROUP2_VAL 0400
46	46
47	47	const device_type PDP8CPU = &device_creator<pdp8_device>;
48	48

trunk/src/emu/cpu/tms32082/mp_ops.c
r249025	r249026
465	465	break;
466	466	}
467	467
468		case 0x12: // and.tf
	468	case 0x12: // and.tf
469	469	{
470	470	int rd = OP_RD();
471	471	int rs = OP_RS();
r249025	r249026
692	692	break;
693	693	}
694	694
695		case 0x45: // jsr.a
	695	case 0x45: // jsr.a
696	696	{
697	697	int link = OP_LINK();
698	698	int base = OP_BASE();
r249025	r249026
929	929	UINT32 compmask = endmask & shiftmask;
930	930
931	931	UINT32 res = 0;
932		if (r) // right
	932	if (r) // right
933	933	{
934	934	res = ROTATE_R(source, rot) & compmask;
935	935	res = SIGN_EXTEND(res, rot);
936	936	}
937		else // left
	937	else // left
938	938	{
939	939	res = ROTATE_L(source, rot) & compmask;
940	940	}
r249025	r249026
1022	1022	}
1023	1023
1024	1024	case 0x3a:
1025		case 0x3b: // or.ft
	1025	case 0x3b: // or.ft
1026	1026	{
1027	1027	int rd = OP_RD();
1028	1028	int rs = OP_RS();

trunk/src/emu/cpu/tms32082/tms32082.c
r249025	r249026
298	298
299	299	for (int i=0; i < num; i++)
300	300	{
301		printf("Entry %d:\n", i);
302		for (int k=0; k < 6; k++)
303		{
304		for (int l=0; l < 4; l++)
305		{
306		UINT32 dd = m_program->read_dword(ra);
307		ra += 4;
	301	printf("Entry %d:\n", i);
	302	for (int k=0; k < 6; k++)
	303	{
	304	for (int l=0; l < 4; l++)
	305	{
	306	UINT32 dd = m_program->read_dword(ra);
	307	ra += 4;
308	308
309		printf("%08X(%f) ", dd, u2f(dd));
310		}
311		printf("\n");
312		}
313		printf("\n");
	309	printf("%08X(%f) ", dd, u2f(dd));
	310	}
	311	printf("\n");
	312	}
	313	printf("\n");
314	314	}
315	315	*/
316	316
317	317	UINT32 ra = 0x1000280;
318
	318
319	319	int oldnum = m_program->read_dword(0x600ffffc);
320	320	UINT32 rb = 0x60000000 + (oldnum * 0x60);
321	321
r249025	r249026
367	367	case 0xa: // PPERROR
368	368	return 0xe0000;
369	369
370		case 0xe: // TCOUNT
	370	case 0xe: // TCOUNT
371	371	return m_tcount;
372	372
373	373	case 0x4000: // IN0P
r249025	r249026
413	413	printf("IE = %08X\n", data);
414	414	break;
415	415
416		case 0xe: // TCOUNT
	416	case 0xe: // TCOUNT
417	417	m_tcount = data;
418	418	break;
419	419

trunk/src/emu/cpu/ucom4/ucom4.c
r249025	r249026
268	268	UINT8 upd557l_cpu_device::input_r(int index)
269	269	{
270	270	index &= 0xf;
271
	271
272	272	if (index == NEC_UCOM4_PORTB)
273	273	logerror("%s read from unknown port %c at $%03X\n", tag(), 'A' + index, m_prev_pc);
274	274	else
275	275	return ucom4_cpu_device::input_r(index);
276
	276
277	277	return 0;
278	278	}
279	279

trunk/src/emu/drivers/emudummy.c
r249025	r249026
33	33	ROM_END
34	34
35	35
36		GAME( 1900, __dummy, 0, __dummy, 0, driver_device, 0, ROT0, "(none)", "Dummy", GAME_NO_SOUND )
	36	GAME( 1900, __dummy, 0, __dummy, 0, driver_device, 0, ROT0, "(none)", "Dummy", MACHINE_NO_SOUND )

trunk/src/emu/emuopts.c
r249025	r249026
595	595	m_sleep = bool_value(OPTION_SLEEP);
596	596	m_refresh_speed = bool_value(OPTION_REFRESHSPEED);
597	597	}
598

trunk/src/emu/machine/i8251.c
r249025	r249026
692	692	{
693	693	m_tx_data = data;
694	694
695		LOG(("data_w %02x\n" , data));
	695	LOG(("data_w %02x\n" , data));
696	696	// printf("i8251 transmit char: %02x\n",data);
697	697
698	698	/* writing clears */
r249025	r249026
714	714
715	715	void i8251_device::receive_character(UINT8 ch)
716	716	{
717
718	717	m_rx_data = ch;
719	718
720	719	/* char has not been read and another has arrived! */
r249025	r249026
735	734
736	735	READ8_MEMBER(i8251_device::data_r)
737	736	{
738		LOG(("read data: %02x, STATUS=%02x\n",m_rx_data,m_status));
	737	LOG(("read data: %02x, STATUS=%02x\n",m_rx_data,m_status));
739	738	/* reading clears */
740	739	m_status &= ~I8251_STATUS_RX_READY;
741	740

trunk/src/emu/machine/i8251.h
r249025	r249026
133	133
134	134	/* data being received */
135	135	UINT8 m_rx_data;
136		UINT8 m_tx_data;
	136	UINT8 m_tx_data;
137	137	bool m_tx_busy;
138	138	bool m_disable_tx_pending;
139	139	};

trunk/src/emu/machine/intelfsh.c
r249025	r249026
425	425	: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F080 Flash", tag, owner, clock, FLASH_AMD_29F080, "amd_29f080", __FILE__) { }
426	426
427	427	amd_29f400t_device::amd_29f400t_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
428		: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F400 Flash", tag, owner, clock, FLASH_AMD_29F400T, "amd_29f400t", __FILE__) { }
	428	: intelfsh8_device(mconfig, AMD_29F400T, "AMD 29F400 Flash", tag, owner, clock, FLASH_AMD_29F400T, "amd_29f400t", __FILE__) { }
429	429
430	430	amd_29f800t_device::amd_29f800t_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
431		: intelfsh8_device(mconfig, AMD_29F080, "AMD 29F800 Flash", tag, owner, clock, FLASH_AMD_29F080, "amd_29f800t", __FILE__) { }
	431	: intelfsh8_device(mconfig, AMD_29F800T, "AMD 29F800 Flash", tag, owner, clock, FLASH_AMD_29F800T, "amd_29f800t", __FILE__) { }
432	432
433	433	amd_29lv200t_device::amd_29lv200t_device(const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
434	434	: intelfsh8_device(mconfig, AMD_29LV200T, "AMD 29LV200T Flash", tag, owner, clock, FLASH_AMD_29LV200T, "amd_29lv200t", __FILE__) { }

trunk/src/emu/machine/tms6100.c
r249025	r249026
211	211	/* read bit at address */
212	212	if (m_variant == TMS6110_IS_M58819)
213	213	{
214		m_data = (m_rom[m_address >> 3] >> (7-(m_address & 0x07))) & 1;
	214	m_data = (m_rom[m_address >> 3] >> (7-(m_address & 0x07))) & 1;
215	215	}
216	216	else // m_variant == (TMS6110_IS_TMS6100 \|\| TMS6110_IS_TMS6125)
217	217	{

trunk/src/emu/netlist/nl_base.c
r249025	r249026
19	19
20	20	namespace netlist
21	21	{
22
23	22	// ----------------------------------------------------------------------------------------
24	23	// logic_family_ttl_t
25	24	// ----------------------------------------------------------------------------------------

trunk/src/emu/netlist/nl_base.h
r249025	r249026
1233	1233	pnamedlist_t<core_device_t *> m_started_devices;
1234	1234	#endif
1235	1235
	1236	ATTR_COLD plog_base<NL_DEBUG> &log() { return m_log; }
1236	1237	ATTR_COLD const plog_base<NL_DEBUG> &log() const { return m_log; }
1237	1238
1238	1239	protected:
1239	1240
1240	1241	// any derived netlist must override vlog inherited from plog_base
1241		// virtual void vlog(const plog_level &l, const pstring &ls) = 0;
	1242	// virtual void vlog(const plog_level &l, const pstring &ls) = 0;
1242	1243
1243	1244	/* from netlist_object */
1244	1245	virtual void reset();
r249025	r249026
1256	1257
1257	1258	netlist_time m_time;
1258	1259	bool m_use_deactivate;
1259		queue_t m_queue;
	1260	queue_t m_queue;
1260	1261
1261	1262
1262	1263	devices::NETLIB_NAME(mainclock) * m_mainclock;

trunk/src/emu/netlist/nl_setup.h
r249025	r249026
198	198
199	199	void model_parse(const pstring &model, model_map_t &map);
200	200
	201	plog_base<NL_DEBUG> &log() { return netlist().log(); }
201	202	const plog_base<NL_DEBUG> &log() const { return netlist().log(); }
202	203
203	204	protected:

trunk/src/emu/netlist/plib/pconfig.h
r249025	r249026
101	101	#define ATTR_HOT __attribute__((hot))
102	102	#define ATTR_COLD __attribute__((cold))
103	103
104		#define RESTRICT __restrict__
	104	#define RESTRICT __restrict__
105	105	#define EXPECTED(x) (x)
106	106	#define UNEXPECTED(x) (x)
107	107	#define ATTR_PRINTF(x,y) __attribute__((format(printf, x, y)))

trunk/src/emu/netlist/plib/pstream.c
r249025	r249026
264	264	{
265	265	return m_pos;
266	266	}
267

trunk/src/emu/netlist/plib/pstring.c
r249025	r249026
14	14
15	15	#include "pstring.h"
16	16	#include "palloc.h"
	17	#include "plists.h"
17	18
18	19	template<>
19	20	pstr_t pstring_t<putf8_traits>::m_zero = pstr_t(0);
r249025	r249026
305	306	// static stuff ...
306	307	// ----------------------------------------------------------------------------------------
307	308
	309	/*
	310	* Cached allocation of string memory
	311	*
	312	* This improves startup performance by 30%.
	313	*/
	314
	315	#if 1
	316
	317	static pstack_t<pstr_t > stk = NULL;
	318
	319	static inline unsigned countleadbits(unsigned x)
	320	{
	321	#ifndef count_leading_zeros
	322	unsigned msk;
	323	unsigned ret;
	324	if (x < 0x100)
	325	{
	326	msk = 0x80;
	327	ret = 24;
	328	}
	329	else if (x < 0x10000)
	330	{
	331	msk = 0x8000;
	332	ret = 16;
	333	}
	334	else if (x < 0x1000000)
	335	{
	336	msk = 0x800000;
	337	ret = 8;
	338	}
	339	else
	340	{
	341	msk = 0x80000000;
	342	ret = 0;
	343	}
	344	while ((msk & x) == 0 && ret < 31)
	345	{
	346	msk = msk >> 1;
	347	ret++;
	348	}
	349	return ret;
	350	#else
	351	return count_leading_zeros(x);
	352	#endif
	353	}
	354
308	355	template<typename F>
309	356	void pstring_t<F>::sfree(pstr_t *s)
310	357	{
311	358	s->m_ref_count--;
312	359	if (s->m_ref_count == 0 && s != &m_zero)
313	360	{
	361	if (stk != NULL)
	362	{
	363	unsigned sn= ((32 - countleadbits(s->len())) + 1) / 2;
	364	stk[sn].push(s);
	365	}
	366	else
	367	pfree_array(((char *)s));
	368	//_mm_free(((char *)s));
	369	}
	370	}
	371
	372	template<typename F>
	373	pstr_t *pstring_t<F>::salloc(int n)
	374	{
	375	if (stk == NULL)
	376	stk = palloc_array(pstack_t<pstr_t *>, 17);
	377	pstr_t *p;
	378	unsigned sn= ((32 - countleadbits(n)) + 1) / 2;
	379	unsigned size = sizeof(pstr_t) + (1<<(sn * 2)) + 1;
	380	if (stk[sn].empty())
	381	p = (pstr_t *) palloc_array(char, size);
	382	else
	383	{
	384	//printf("%u %u\n", sn, (unsigned) stk[sn].count());
	385	p = stk[sn].pop();
	386	}
	387
	388	// str_t p = (str_t ) _mm_malloc(size, 8);
	389	p->init(n);
	390	return p;
	391	}
	392	template<typename F>
	393	void pstring_t<F>::resetmem()
	394	{
	395	if (stk != NULL)
	396	{
	397	for (unsigned i=0; i<=16; i++)
	398	{
	399	for (; stk[i].count() > 0; )
	400	pfree_array(stk[i].pop());
	401	}
	402	pfree_array(stk);
	403	stk = NULL;
	404	}
	405	}
	406
	407
	408	#else
	409	template<typename F>
	410	void pstring_t<F>::sfree(pstr_t *s)
	411	{
	412	s->m_ref_count--;
	413	if (s->m_ref_count == 0 && s != &m_zero)
	414	{
314	415	pfree_array(((char *)s));
315	416	//_mm_free(((char *)s));
316	417	}
r249025	r249026
331	432	{
332	433	// Release the 0 string
333	434	}
	435	#endif
334	436
	437
335	438	// ----------------------------------------------------------------------------------------
336	439	// pstring ...
337	440	// ----------------------------------------------------------------------------------------
r249025	r249026
600	703
601	704	template struct pstring_t<pu8_traits>;
602	705	template struct pstring_t<putf8_traits>;
603

trunk/src/emu/netlist/plib/pstring.h
r249025	r249026
22	22	struct pstr_t
23	23	{
24	24	//str_t() : m_ref_count(1), m_len(0) { m_str[0] = 0; }
25		pstr_t(const int alen)
	25	pstr_t(const unsigned alen)
26	26	{
27	27	init(alen);
28	28	}
29		void init(const int alen)
	29	void init(const unsigned alen)
30	30	{
31	31	m_ref_count = 1;
32	32	m_len = alen;
33	33	m_str[0] = 0;
34	34	}
35	35	char *str() { return &m_str[0]; }
36		int len() const { return m_len; }
	36	unsigned len() const { return m_len; }
37	37	int m_ref_count;
38	38	private:
39		int m_len;
	39	unsigned m_len;
40	40	char m_str[1];
41	41	};
42	42
r249025	r249026
241	241	return 2;
242	242	else if (c < 0x10000)
243	243	return 3;
244		else /* U+10000 U+1FFFFF */
	244	else /* U+10000 U+1FFFFF */
245	245	return 4; /* no checks */
246	246	}
247	247	static code_t code(const mem_t *p)
r249025	r249026
276	276	m[1] = 0x80 \| ((c>>6) & 0x3f);
277	277	m[2] = 0x80 \| (c & 0x3f);
278	278	}
279		else /* U+10000 U+1FFFFF */
	279	else /* U+10000 U+1FFFFF */
280	280	{
281	281	m[0] = 0xF0 \| (c >> 18);
282	282	m[1] = 0x80 \| ((c>>12) & 0x3f);
r249025	r249026
548	548	class pfmt_writer_t
549	549	{
550	550	public:
551		pfmt_writer_t() { }
	551	pfmt_writer_t() : m_enabled(true) { }
552	552	virtual ~pfmt_writer_t() { }
553	553
554	554	ATTR_COLD void operator ()(const char *fmt) const
555	555	{
556		if (build_enabled) vdowrite(fmt);
	556	if (build_enabled && m_enabled) vdowrite(fmt);
557	557	}
558	558
559	559	template<typename T1>
560	560	ATTR_COLD void operator ()(const char *fmt, const T1 &v1) const
561	561	{
562		if (build_enabled) vdowrite(pfmt(fmt)(v1));
	562	if (build_enabled && m_enabled) vdowrite(pfmt(fmt)(v1));
563	563	}
564	564
565	565	template<typename T1, typename T2>
566	566	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2) const
567	567	{
568		if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2));
	568	if (build_enabled && m_enabled) vdowrite(pfmt(fmt)(v1)(v2));
569	569	}
570	570
571	571	template<typename T1, typename T2, typename T3>
572	572	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2, const T3 &v3) const
573	573	{
574		if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3));
	574	if (build_enabled && m_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3));
575	575	}
576	576
577	577	template<typename T1, typename T2, typename T3, typename T4>
578	578	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2, const T3 &v3, const T4 &v4) const
579	579	{
580		if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4));
	580	if (build_enabled && m_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4));
581	581	}
582	582
583	583	template<typename T1, typename T2, typename T3, typename T4, typename T5>
584	584	ATTR_COLD void operator ()(const char *fmt, const T1 &v1, const T2 &v2, const T3 &v3, const T4 &v4, const T5 &v5) const
585	585	{
586		if (build_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4)(v5));
	586	if (build_enabled && m_enabled) vdowrite(pfmt(fmt)(v1)(v2)(v3)(v4)(v5));
587	587	}
588	588
	589	void set_enabled(const bool v)
	590	{
	591	m_enabled = v;
	592	}
	593
	594	bool is_enabled() const { return m_enabled; }
	595
589	596	protected:
590	597	virtual void vdowrite(const pstring &ls) const {}
591	598
	599	private:
	600	bool m_enabled;
	601
592	602	};
593	603
594	604	template <plog_level L, bool build_enabled = true>
r249025	r249026
622	632
623	633	plog_base(plog_dispatch_intf *proxy)
624	634	: debug(proxy),
625		info(proxy),
626		verbose(proxy),
627		warning(proxy),
628		error(proxy),
629		fatal(proxy)
	635	info(proxy),
	636	verbose(proxy),
	637	warning(proxy),
	638	error(proxy),
	639	fatal(proxy)
630	640	{}
631	641	virtual ~plog_base() {};
632	642

trunk/src/emu/netlist/prg/nltool.c
r249025	r249026
30	30
31	31	#include <ctime>
32	32
33		#define osd_ticks_t clock_t
	33	#define osd_ticks_t clock_t
34	34
35	35	inline osd_ticks_t osd_ticks_per_second() { return CLOCKS_PER_SEC; }
36	36
r249025	r249026
98	98	public:
99	99	tool_options_t() :
100	100	poptions(),
101		opt_ttr ("t", "time_to_run", 1.0, "time to run the emulation (seconds)", this),
	101	opt_ttr ("t", "time_to_run", 1.0, "time to run the emulation (seconds)", this),
102	102	opt_name("n", "name", "", "netlist in file to run; default is first one", this),
103	103	opt_logs("l", "logs", "", "colon separated list of terminals to log", this),
104	104	opt_file("f", "file", "-", "file to process (default is stdin)", this),
105	105	opt_type("y", "type", "spice", "spice:eagle", "type of file to be converted: spice,eagle", this),
106		opt_cmd ("c", "cmd", "run", "run\|convert\|listdevices", this),
	106	opt_cmd ("c", "cmd", "run", "run\|convert\|listdevices", this),
107	107	opt_inp( "i", "input", "", "input file to process (default is none)", this),
108	108	opt_verb("v", "verbose", "be verbose - this produces lots of output", this),
109	109	opt_quiet("q", "quiet", "be quiet - no warnings", this),
r249025	r249026
113	113	poption_double opt_ttr;
114	114	poption_str opt_name;
115	115	poption_str opt_logs;
116		poption_str opt_file;
	116	poption_str opt_file;
117	117	poption_str_limit opt_type;
118	118	poption_str opt_cmd;
119	119	poption_str opt_inp;

trunk/src/emu/netlist/prg/nlwav.c
r249025	r249026
49	49	public:
50	50	wav_t(postream &strm, unsigned sr) : m_f(strm)
51	51	{
52		// m_f = strm;
	52	// m_f = strm;
53	53	initialize(sr);
54	54	m_f.write(&m_fh, sizeof(m_fh));
55	55	m_f.write(&m_fmt, sizeof(m_fmt));

trunk/src/emu/netlist/solver/nld_ms_direct.h
r249025	r249026
488	488	// ii=-1
489	489
490	490	//for (int i=0; i < kN; i++)
491		// x[i] = m_RHS[i];
	491	// x[i] = m_RHS[i];
492	492
493	493	for (int i=0; i < kN; i++)
494	494	{

trunk/src/emu/netlist/solver/nld_ms_direct_lu.h
r249025	r249026
429	429	template <unsigned m_N, unsigned _storage_N>
430	430	ATTR_HOT void matrix_solver_direct_t<m_N, _storage_N>::LE_solve()
431	431	{
432
433	432	const unsigned kN = N();
434	433
435	434	ATTR_UNUSED int imax;
r249025	r249026
501	500	indx[j]=imax;
502	501	#endif
503	502	//if (m_A[j][j] == 0.0)
504		// m_A[j][j] = 1e-20;
	503	// m_A[j][j] = 1e-20;
505	504	double dum = 1.0 / A(j,j);
506	505	for (int i = j+1; i < kN; i++)
507	506	A(i,j) *= dum;
r249025	r249026
521	520	// ii=-1
522	521
523	522	//for (int i=0; i < kN; i++)
524		// x[i] = m_RHS[i];
	523	// x[i] = m_RHS[i];
525	524
526	525	for (int i=0; i < kN; i++)
527	526	{

trunk/src/emu/netlist/solver/nld_solver.h
r249025	r249026
135	135	ATTR_COLD int get_net_idx(net_t *net);
136	136
137	137	inline eSolverType type() const { return m_type; }
138		~~const~~ plog_base<NL_DEBUG> &log() ~~const~~ { return netlist().log(); }
	138	plog_base<NL_DEBUG> &log() { return netlist().log(); }
139	139
140	140	virtual void log_stats();
141	141

trunk/src/emu/screen.h
r249025	r249026
287	287	INT32 m_last_partial_scan; // scanline of last partial update
288	288	bitmap_argb32 m_screen_overlay_bitmap; // screen overlay bitmap
289	289	UINT32 m_unique_id; // unique id for this screen_device
290		rgb_t m_color; // render color
291		UINT8 m_brightness; // global brightness
	290	rgb_t m_color; // render color
	291	UINT8 m_brightness; // global brightness
292	292
293	293	// screen timing
294	294	attoseconds_t m_frame_period; // attoseconds per frame

trunk/src/emu/sound/rf5c400.c
r249025	r249026
413	413	case 0x08: // relative to env attack (channel no)
414	414	case 0x09: // relative to env attack (0x0c00/ 0x1c00)
415	415
416		case 0x11: // ? counter for 0x13?
	416	case 0x11: // ? counter for 0x13?
417	417	{
418	418	break;
419	419	}
420		case 0x13: // ? bujutsu writes sample data here
	420	case 0x13: // ? bujutsu writes sample data here
421	421	{
422	422	break;
423	423	}
424	424
425		case 0x14: // ? related to 0x11/0x13 ?
	425	case 0x14: // ? related to 0x11/0x13 ?
426	426	break;
427	427
428	428	case 0x21: // reverb(character).w

trunk/src/emu/sound/tms5110.c
r249025	r249026
14	14
15	15	Todo:
16	16	- implement CS
17		- implement missing commands
18	17	- TMS5110_CMD_TEST_TALK is only partially implemented
19	18
20	19	TMS5100:
r249025	r249026
212	211	{
213	212	save_item(NAME(m_variant));
214	213
215		save_item(NAME(m_fifo));
216		save_item(NAME(m_fifo_head));
217		save_item(NAME(m_fifo_tail));
218		save_item(NAME(m_fifo_count));
219
220	214	save_item(NAME(m_PDC));
221	215	save_item(NAME(m_CTL_pins));
222	216	save_item(NAME(m_SPEN));
r249025	r249026
240	234	save_item(NAME(m_old_frame_energy_idx));
241	235	save_item(NAME(m_old_frame_pitch_idx));
242	236	save_item(NAME(m_old_frame_k_idx));
	237	save_item(NAME(m_old_zpar));
	238	save_item(NAME(m_old_uv_zpar));
243	239	#endif
244	240	save_item(NAME(m_current_energy));
245	241	save_item(NAME(m_current_pitch));
r249025	r249026
309	305	}
310	306	#endif
311	307
312
313	308	/******************************************************************************************
314	309
315		~~FIFO_da~~ta_write -- ~~handl~~e bit data write to t~~he TMS5110 (a~~s a r~~esult~~ of t~~oggling~~ M~~0 pin)~~
	310	extract_bits -- extract a specific number of bits from the VSM
316	311
317	312	******************************************************************************************/
318		void tms5110_device::FIFO_data_write(int data)
319		{
320		/* add this bit to the FIFO */
321		if (m_fifo_count < FIFO_SIZE)
322		{
323		m_fifo[m_fifo_tail] = (data&1); /* set bit to 1 or 0 */
324	313
325		m_fifo_tail = (m_fifo_tail + 1) % FIFO_SIZE;
326		m_fifo_count++;
327
328		if (DEBUG_5110) logerror("Added bit to FIFO (size=%2d)\n", m_fifo_count);
329		}
330		else
331		{
332		if (DEBUG_5110) logerror("Ran out of room in the FIFO!\n");
333		}
334		}
335
336		/******************************************************************************************
337
338		extract_bits -- extract a specific number of bits from the FIFO
339
340		******************************************************************************************/
341
342	314	int tms5110_device::extract_bits(int count)
343	315	{
344	316	int val = 0;
345		if (DEBUG_5110) logerror("requesting %d bits from fifo: ", count);
346		while (count--)
	317	if (DEBUG_5110) logerror("requesting %d bits", count);
	318	for (int i = 0; i < count; i++)
347	319	{
348		val = (val << 1) \| (m_fifo[m_fifo_head] & 1);
349		m_fifo_count--;
350		m_fifo_head = (m_fifo_head + 1) % FIFO_SIZE;
	320	val = (val<<1) \| new_int_read();
	321	if (DEBUG_5110) logerror("bit read: %d\n", val&1);
351	322	}
352	323	if (DEBUG_5110) logerror("returning: %02x\n", val);
353	324	return val;
354	325	}
355	326
356		void tms5110_device::request_bits(int no)
357		{
358		for (int i = 0; i < no; i++)
359		{
360		UINT8 data = new_int_read();
361		if (DEBUG_5110) logerror("bit added to fifo: %d\n", data);
362		FIFO_data_write(data);
363		}
364		}
365	327
366	328	void tms5110_device::perform_dummy_read()
367	329	{
r249025	r249026
388	350	int i, bitout;
389	351	INT32 this_sample;
390	352
391		/* if we're not speaking, fill with nothingness */
392		if (!m_TALKD)
393		goto empty;
394
395	353	/* loop until the buffer is full or we've stopped speaking */
396		while ((size > 0~~) && m_TALKD~~)
	354	while (size > 0)
397	355	{
398		/* if it is the appropriate time to update the old energy/pitch indices,
399		* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
400		* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
401		* which happens 4 T-cycles later), we change on the latter.
402		* The indices are updated here ~12 PCs before the new frame is applied.
403		*/
404		/ TODO: the patents 4331836, 4335277, and 4419540 disagree about the timing of this /
405		if ((m_IP == 0) && (m_PC == 0) && (m_subcycle < 2))
	356	if(m_TALKD) // speaking
406	357	{
407		m_OLDE = (m_new_frame_energy_idx == 0);
408		m_OLDP = (m_new_frame_pitch_idx == 0);
409		}
	358	/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
	359	* (In reality, the frame was really loaded incrementally during the entire IP=0
	360	* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
	361	*/
	362	if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
	363	{
	364	// HACK for regression testing, be sure to comment out before release!
	365	//m_RNG = 0x1234;
	366	// end HACK
410	367
411		/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
412		* (In reality, the frame was really loaded incrementally during the entire IP=0
413		* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
414		*/
415		if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
416		{
417		// HACK for regression testing, be sure to comment out before release!
418		//m_RNG = 0x1234;
419		// end HACK
420
421	368	#ifdef PERFECT_INTERPOLATION_HACK
422		/* remember previous frame energy, pitch, and coefficients */
423		m_old_frame_energy_idx = m_new_frame_energy_idx;
424		m_old_frame_pitch_idx = m_new_frame_pitch_idx;
425		for (i = 0; i < m_coeff->num_k; i++)
426		m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
	369	/* remember previous frame energy, pitch, and coefficients */
	370	m_old_frame_energy_idx = m_new_frame_energy_idx;
	371	m_old_frame_pitch_idx = m_new_frame_pitch_idx;
	372	for (i = 0; i < m_coeff->num_k; i++)
	373	m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
427	374	#endif
428	375
429		/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[] */
430		parse_frame();
431		#ifdef DEBUG_PARSE_FRAME_DUMP
432		fprintf(stderr,"\n");
	376	/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[] */
	377	parse_frame();
	378
	379	// if the new frame is unvoiced (or silenced via ZPAR), be sure to zero out the k5-k10 parameters
	380	// NOTE: this is probably the bug the tms5100/tmc0280 has, pre-rev D, I think.
	381	// GUESS: Pre-rev D versions start zeroing k5-k10 immediately upon new frame load regardless of interpolation inhibit
	382	// I.e. ZPAR = /TALKD \|\| (PC>5&&P=0)
	383	// GUESS: D and later versions only start or stop zeroing k5-k10 at the IP7->IP0 transition AFTER the frame
	384	// I.e. ZPAR = /TALKD \|\| (PC>5&&OLDP)
	385	#ifdef PERFECT_INTERPOLATION_HACK
	386	m_old_uv_zpar = m_uv_zpar;
	387	m_old_zpar = m_zpar; // unset old zpar on new frame
433	388	#endif
434		/* if the new frame is unvoiced (or silenced via ZPAR), be sure to zero out the k5-k10 parameters */
435		m_uv_zpar = NEW_FRAME_UNVOICED_FLAG \| m_zpar;
	389	m_zpar = 0;
	390	//m_uv_zpar = (OLD_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: fixed version in tmc0280d/tms5100a/cd280x/tms5110
	391	m_uv_zpar = (NEW_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: buggy version in tmc0280/tms5100
436	392
437		/* if the new frame is a stop frame, unset both TALK and SPEN. TALKD remains active while the energy is ramping to 0. */
438		if (NEW_FRAME_STOP_FLAG == 1)
439		{
440		m_TALK = m_SPEN = 0;
441		}
	393	/* if the new frame is a stop frame, unset both TALK and SPEN (via TCON). TALKD remains active while the energy is ramping to 0. */
	394	if (NEW_FRAME_STOP_FLAG == 1)
	395	{
	396	m_TALK = m_SPEN = 0;
	397	}
442	398
443		/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
444		Interpolation inhibit cases:
445		* Old frame was voiced, new is unvoiced
446		* Old frame was silence/zero energy, new has nonzero energy
447		* Old frame was unvoiced, new is voiced (note this is the case on the patent but may not be correct on the real final chip)
448		*/
449		if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
450		\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0)) /* this line needs further investigation, starwars tie fighters may sound better without it */
451		\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
452		m_inhibit = 1;
453		else // normal frame, normal interpolation
454		m_inhibit = 0;
	399	/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
	400	Interpolation inhibit cases:
	401	* Old frame was voiced, new is unvoiced
	402	* Old frame was silence/zero energy, new has nonzero energy
	403	* Old frame was unvoiced, new is voiced (note this is the case on the patent but may not be correct on the real final chip)
	404	*/
	405	if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
	406	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0)) /* this line needs further investigation, starwars tie fighters may sound better without it */
	407	\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0)) )
	408	m_inhibit = 1;
	409	else // normal frame, normal interpolation
	410	m_inhibit = 0;
455	411
456	412	#ifdef DEBUG_GENERATION
457		/* Debug info for current parsed frame */
458		fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
459		fprintf(stderr,"Processing frame: ");
460		if (m_inhibit == 0)
461		fprintf(stderr, "Normal Frame\n");
462		else
463		fprintf(stderr,"Interpolation Inhibited\n");
464		fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
465		fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",
466		(m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)),
467		m_new_frame_energy_idx,
468		(m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)),
469		(m_coeff->ktable[0][m_new_frame_k_idx[0]] * (1-m_zpar)),
470		(m_coeff->ktable[1][m_new_frame_k_idx[1]] * (1-m_zpar)),
471		(m_coeff->ktable[2][m_new_frame_k_idx[2]] * (1-m_zpar)),
472		(m_coeff->ktable[3][m_new_frame_k_idx[3]] * (1-m_zpar)),
473		(m_coeff->ktable[4][m_new_frame_k_idx[4]] * (1-m_uv_zpar)),
474		(m_coeff->ktable[5][m_new_frame_k_idx[5]] * (1-m_uv_zpar)),
475		(m_coeff->ktable[6][m_new_frame_k_idx[6]] * (1-m_uv_zpar)),
476		(m_coeff->ktable[7][m_new_frame_k_idx[7]] * (1-m_uv_zpar)),
477		(m_coeff->ktable[8][m_new_frame_k_idx[8]] * (1-m_uv_zpar)),
478		(m_coeff->ktable[9][m_new_frame_k_idx[9]] * (1-m_uv_zpar)) );
	413	/* Debug info for current parsed frame */
	414	fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
	415	fprintf(stderr,"Processing new frame: ");
	416	if (m_inhibit == 0)
	417	fprintf(stderr, "Normal Frame\n");
	418	else
	419	fprintf(stderr,"Interpolation Inhibited\n");
	420	fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
	421	fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",
	422	(m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)),
	423	m_new_frame_energy_idx,
	424	(m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)),
	425	(m_coeff->ktable[0][m_new_frame_k_idx[0]] * (1-m_zpar)),
	426	(m_coeff->ktable[1][m_new_frame_k_idx[1]] * (1-m_zpar)),
	427	(m_coeff->ktable[2][m_new_frame_k_idx[2]] * (1-m_zpar)),
	428	(m_coeff->ktable[3][m_new_frame_k_idx[3]] * (1-m_zpar)),
	429	(m_coeff->ktable[4][m_new_frame_k_idx[4]] * (1-m_uv_zpar)),
	430	(m_coeff->ktable[5][m_new_frame_k_idx[5]] * (1-m_uv_zpar)),
	431	(m_coeff->ktable[6][m_new_frame_k_idx[6]] * (1-m_uv_zpar)),
	432	(m_coeff->ktable[7][m_new_frame_k_idx[7]] * (1-m_uv_zpar)),
	433	(m_coeff->ktable[8][m_new_frame_k_idx[8]] * (1-m_uv_zpar)),
	434	(m_coeff->ktable[9][m_new_frame_k_idx[9]] * (1-m_uv_zpar)) );
479	435	#endif
480	436
481		}
482		else // Not a new frame, just interpolate the existing frame.
483		{
484		int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
485		#ifdef PERFECT_INTERPOLATION_HACK
486		int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
487		//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
488		int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
489		//fprintf(stderr, "CS: %03d", current_sample);
490		// reset the current energy, pitch, etc to what it was at frame start
491		m_current_energy = (m_coeff->energytable[m_old_frame_energy_idx] * (1-m_zpar));
492		m_current_pitch = (m_coeff->pitchtable[m_old_frame_pitch_idx] * (1-m_old_zpar));
493		for (i = 0; i < 4; i++)
494		m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-m_old_zpar));
495		for (i = 4; i < m_coeff->num_k; i++)
496		m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-m_uv_zpar));
497		// now adjust each value to be exactly correct for each of the samples per frame
498		if (m_IP != 0) // if we're still interpolating...
499		{
500		m_current_energy += ((((m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)) - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame;
501		m_current_pitch += ((((m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)) - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame;
502		for (i = 0; i < m_coeff->num_k; i++)
503		m_current_k[i] += ((((m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar))) - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame;
504	437	}
505		else // we're done, play th~~is fram~~e ~~for 1/8~~ frame.
	438	else // Not a new frame, just interpolate the existing frame.
506	439	{
507		m_current_energy = (m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar));
508		m_current_pitch = (m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar));
	440	int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
	441	#ifdef PERFECT_INTERPOLATION_HACK
	442	int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
	443	//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
	444	int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
	445	//fprintf(stderr, "CS: %03d", current_sample);
	446	// reset the current energy, pitch, etc to what it was at frame start
	447	m_current_energy = (m_coeff->energytable[m_old_frame_energy_idx] * (1-m_old_zpar));
	448	m_current_pitch = (m_coeff->pitchtable[m_old_frame_pitch_idx] * (1-m_old_zpar));
509	449	for (i = 0; i < m_coeff->num_k; i++)
510		m_current_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar)));
511		}
	450	m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-((i<4)?m_old_zpar:m_old_uv_zpar)));
	451	// now adjust each value to be exactly correct for each of the samples per frame
	452	if (m_IP != 0) // if we're still interpolating...
	453	{
	454	m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
	455	m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
	456	for (i = 0; i < m_coeff->num_k; i++)
	457	m_current_k[i] = (m_current_k[i] + (((m_coeff->ktable[i][m_new_frame_k_idx[i]] - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame)*(1-((i<4)?m_zpar:m_uv_zpar));
	458	}
	459	else // we're done, play this frame for 1/8 frame.
	460	{
	461	m_current_energy = (m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar));
	462	m_current_pitch = (m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar));
	463	for (i = 0; i < m_coeff->num_k; i++)
	464	m_current_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar)));
	465	}
512	466	#else
513		//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
514		if (m_subcycle == 2)
515		{
516		switch(m_PC)
	467	//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
	468	if (m_subcycle == 2)
517	469	{
518		case 0: /* PC = 0, B cycle, write updated energy */
519		m_current_energy += ((((m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)) - m_current_energy)*(1-inhibit_state)) INTERP_SHIFT);
520		break;
521		case 1: /* PC = 1, B cycle, write updated pitch */
522		m_current_pitch += ((((m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)) - m_current_pitch)*(1-inhibit_state)) INTERP_SHIFT);
523		break;
524		case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
525		/* PC = 2 through 11, B cycle, write updated K1 through K10 */
526		m_current_k[m_PC-2] += ((((m_coeff->ktable[m_PC-2][m_new_frame_k_idx[m_PC-2]] * (1-(((m_PC-2)<4)?m_zpar:m_uv_zpar))) - m_current_k[m_PC-2])*(1-inhibit_state)) INTERP_SHIFT);
527		break;
528		case 12: /* PC = 12, do nothing */
529		break;
	470	switch(m_PC)
	471	{
	472	case 0: /* PC = 0, B cycle, write updated energy */
	473	m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
	474	break;
	475	case 1: /* PC = 1, B cycle, write updated pitch */
	476	m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
	477	break;
	478	case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
	479	/* PC = 2 through 11, B cycle, write updated K1 through K10 */
	480	m_current_k[m_PC-2] = (m_current_k[m_PC-2] + (((m_coeff->ktable[m_PC-2][m_new_frame_k_idx[m_PC-2]] - m_current_k[m_PC-2])(1-inhibit_state)) INTERP_SHIFT))(((m_PC-2)>4)?(1-m_uv_zpar):(1-m_zpar));
	481	break;
	482	case 12: /* PC = 12 */
	483	/* we should NEVER reach this point, PC=12 doesn't have a subcycle 2 */
	484	break;
	485	}
530	486	}
531		}
532	487	#endif
533		}
	488	}
534	489
535		// calculate the output
536		if (OLD_FRAME_UNVOICED_FLAG == 1)
537		{
538		// generate unvoiced samples here
539		if (m_RNG & 1)
540		m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
541		else
542		m_excitation_data = 0x40;
543		}
544		else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
545		{
546		// generate voiced samples here
547		/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
548		* function has a chirp/peak and then a long chain of zeroes.
549		* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
550		* and if the address reaches that point the ADDRESS incrementer is
551		* disabled, forcing all samples beyond 51d to be == 51d
552		*/
553		if (m_pitch_count >= 51)
554		m_excitation_data = (INT8)m_coeff->chirptable[51];
555		else /m_pitch_count < 51/
556		m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
557		}
	490	// calculate the output
	491	if (OLD_FRAME_UNVOICED_FLAG == 1)
	492	{
	493	// generate unvoiced samples here
	494	if (m_RNG & 1)
	495	m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
	496	else
	497	m_excitation_data = 0x40;
	498	}
	499	else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
	500	{
	501	// generate voiced samples here
	502	/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
	503	* function has a chirp/peak and then a long chain of zeroes.
	504	* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
	505	* and if the address reaches that point the ADDRESS incrementer is
	506	* disabled, forcing all samples beyond 51d to be == 51d
	507	*/
	508	if (m_pitch_count >= 51)
	509	m_excitation_data = (INT8)m_coeff->chirptable[51];
	510	else /m_pitch_count < 51/
	511	m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
	512	}
558	513
559		// Update LFSR 20 times every sample (once per T cycle), like patent shows
560		for (i=0; i<20; i++)
561		{
562		bitout = ((m_RNG >> 12) & 1) ^
563		((m_RNG >> 3) & 1) ^
564		((m_RNG >> 2) & 1) ^
565		((m_RNG >> 0) & 1);
566		m_RNG <<= 1;
567		m_RNG \|= bitout;
568		}
569		this_sample = lattice_filter(); /* execute lattice filter */
	514	// Update LFSR 20 times every sample (once per T cycle), like patent shows
	515	for (i=0; i<20; i++)
	516	{
	517	bitout = ((m_RNG >> 12) & 1) ^
	518	((m_RNG >> 3) & 1) ^
	519	((m_RNG >> 2) & 1) ^
	520	((m_RNG >> 0) & 1);
	521	m_RNG <<= 1;
	522	m_RNG \|= bitout;
	523	}
	524	this_sample = lattice_filter(); /* execute lattice filter */
570	525	#ifdef DEBUG_GENERATION_VERBOSE
571		//fprintf(stderr,"C:%01d; ",m_subcycle);
572		fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
573		//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
574		for (i=0; i<10; i++)
575		fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
576		fprintf(stderr,"Out:%06d", this_sample);
577		fprintf(stderr,"\n");
	526	//fprintf(stderr,"C:%01d; ",m_subcycle);
	527	fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	528	//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	529	for (i=0; i<10; i++)
	530	fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
	531	fprintf(stderr,"Out:%06d ", this_sample);
	532	//#ifdef PERFECT_INTERPOLATION_HACK
	533	// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
	534	//#else
	535	// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
	536	//#endif
	537	fprintf(stderr,"\n");
578	538	#endif
579		/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
580		while (this_sample > 16383) this_sample -= 32768;
581		while (this_sample < -16384) this_sample += 32768;
582		if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
583		buffer[buf_count] = clip_analog(this_sample);
584		else // digital I/O pin output is 12 bits
585		{
	539	/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
	540	while (this_sample > 16383) this_sample -= 32768;
	541	while (this_sample < -16384) this_sample += 32768;
	542	if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
	543	buffer[buf_count] = clip_analog(this_sample);
	544	else // digital I/O pin output is 12 bits
	545	{
586	546	#ifdef ALLOW_4_LSB
587		// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
588		// N taps: ^ = 0x2000;
589		// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
590		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
	547	// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
	548	// N taps: ^ = 0x2000;
	549	// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
	550	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
591	551	#else
592		this_sample &= ~0xF;
593		// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
594		// N taps: ^^ ^^^ = 0x3E00;
595		// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
596		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
	552	this_sample &= ~0xF;
	553	// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
	554	// N taps: ^^ ^^^ = 0x3E00;
	555	// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
	556	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
597	557	#endif
598		}
599		// Update all counts
	558	}
	559	// Update all counts
600	560
601		m_subcycle++;
602		if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
603		{
604		/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
605		* if INHIBIT was true during the most recent frame transition.
606		* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
607		* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
608		* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
609		* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
610		* convenient and should make no difference in output.
611		*/
612		if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_zero = 1;
613		if ((m_IP == 0)&&(m_pitch_zero==1)) m_pitch_zero = 0;
614		#ifdef PERFECT_INTERPOLATION_HACK
615		m_old_zpar = m_zpar;
616		#endif
617		m_zpar = 0; /* this gets effectively reset by resetf3, same signal which resets m_PC to 0 */
618		if (m_IP == 7) // RESETL4
	561	m_subcycle++;
	562	if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
619	563	{
620		/* if TALK was clear last frame, halt speech now, since TALKD (latched from TALK on new frame) just went inactive. */
	564	/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
	565	* if INHIBIT was true during the most recent frame transition.
	566	* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
	567	* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
	568	* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
	569	* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
	570	* convenient and should make no difference in output.
	571	*/
	572	if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_zero = 1;
	573	if ((m_IP == 0)&&(m_pitch_zero==1)) m_pitch_zero = 0;
	574	if (m_IP == 7) // RESETL4
	575	{
	576	// Latch OLDE and OLDP
	577	OLD_FRAME_SILENCE_FLAG = NEW_FRAME_SILENCE_FLAG; // m_OLDE
	578	OLD_FRAME_UNVOICED_FLAG = NEW_FRAME_UNVOICED_FLAG; // m_OLDP
	579	/* if TALK was clear last frame, halt speech now, since TALKD (latched from TALK on new frame) just went inactive. */
621	580	#ifdef DEBUG_GENERATION
622		if (m_TALK == 0)
623		fprintf(stderr,"tms5110_process: processing frame: TALKD = 0 caused by stop frame or buffer empty, halting speech.\n");
	581	if (m_TALK == 0)
	582	fprintf(stderr,"tms5110_process: processing frame: TALKD = 0 caused by stop frame or buffer empty, halting speech.\n");
624	583	#endif
625		m_TALKD = m_TALK; // TALKD is latched from TALK
626		m_TALK = m_SPEN; // TALK is latched from SPEN
	584	m_TALKD = m_TALK; // TALKD is latched from TALK
	585	m_TALK = m_SPEN; // TALK is latched from SPEN
	586	}
	587	m_subcycle = m_subc_reload;
	588	m_PC = 0;
	589	m_IP++;
	590	m_IP&=0x7;
627	591	}
628		m_subcycle = m_subc_reload;
629		m_PC = 0;
630		m_IP++;
631		m_IP&=0x7;
	592	else if (m_subcycle == 3)
	593	{
	594	m_subcycle = m_subc_reload;
	595	m_PC++;
	596	}
	597	m_pitch_count++;
	598	if ((m_pitch_count >= m_current_pitch)\|\|(m_pitch_zero == 1)) m_pitch_count = 0;
	599	m_pitch_count &= 0x1FF;
632	600	}
633		else if (m_~~subcycle~~ == 3)
	601	else // m_TALKD == 0
634	602	{
635		m_subcycle = m_subc_reload;
636		m_PC++;
637		}
638		m_pitch_count++;
639		if ((m_pitch_count >= m_current_pitch)\|\|(m_pitch_zero == 1)) m_pitch_count = 0;
640		m_pitch_count &= 0x1FF;
641		buf_count++;
642		size--;
643		}
644
645		empty:
646
647		while (size > 0)
648		{
649		m_subcycle++;
650		if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
651		{
652		if (m_IP == 7) // RESETL4
	603	m_subcycle++;
	604	if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
653	605	{
654		m_TALKD = m_TALK; // TALKD is latched from TALK
655		m_TALK = m_SPEN; // TALK is latched from SPEN
	606	if (m_IP == 7) // RESETL4
	607	{
	608	m_TALKD = m_TALK; // TALKD is latched from TALK
	609	m_TALK = m_SPEN; // TALK is latched from SPEN
	610	}
	611	m_subcycle = m_subc_reload;
	612	m_PC = 0;
	613	m_IP++;
	614	m_IP&=0x7;
656	615	}
657		m_subcycle = m_subc_reload;
658		m_PC = 0;
659		m_IP++;
660		m_IP&=0x7;
	616	else if (m_subcycle == 3)
	617	{
	618	m_subcycle = m_subc_reload;
	619	m_PC++;
	620	}
	621	buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
661	622	}
662		else if (m_subcycle == 3)
663		{
664		m_subcycle = m_subc_reload;
665		m_PC++;
666		}
667		buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
668		buf_count++;
669		size--;
	623	buf_count++;
	624	size--;
670	625	}
671	626	}
672	627
r249025	r249026
898	853	m_SPEN = 1; /* start immediately */
899	854	/* clear out variables before speaking */
900	855	m_zpar = 1; // zero all the parameters
	856	m_uv_zpar = 1; // zero k4-k10 as well
	857	m_OLDE = 1; // 'silence/zpar' frames are zero energy
	858	m_OLDP = 1; // 'silence/zpar' frames are zero pitch
	859	#ifdef PERFECT_INTERPOLATION_HACK
	860	m_old_zpar = 1; // zero all the old parameters
	861	m_old_uv_zpar = 1; // zero old k4-k10 as well
	862	#endif
901	863	m_subc_reload = 0; // SPKSLOW means this is 0
902		m_subcycle = m_subc_reload;
903		m_PC = 0;
904		m_IP = 0;
905	864	break;
906	865
907	866	case TMS5110_CMD_READ_BIT:
r249025	r249026
915	874	#ifdef DEBUG_COMMAND_DUMP
916	875	fprintf(stderr,"actually reading a bit now\n");
917	876	#endif
918		request_bits(1);
919	877	m_CTL_buffer >>= 1;
920	878	m_CTL_buffer \|= (extract_bits(1)<<3);
921	879	m_CTL_buffer &= 0xF;
r249025	r249026
930	888	m_SPEN = 1; /* start immediately */
931	889	/* clear out variables before speaking */
932	890	m_zpar = 1; // zero all the parameters
	891	m_uv_zpar = 1; // zero k4-k10 as well
	892	m_OLDE = 1; // 'silence/zpar' frames are zero energy
	893	m_OLDP = 1; // 'silence/zpar' frames are zero pitch
	894	#ifdef PERFECT_INTERPOLATION_HACK
	895	m_old_zpar = 1; // zero all the old parameters
	896	m_old_uv_zpar = 1; // zero old k4-k10 as well
	897	#endif
933	898	m_subc_reload = 1; // SPEAK means this is 1
934		m_subcycle = m_subc_reload;
935		m_PC = 0;
936		m_IP = 0;
937	899	break;
938	900
939	901	case TMS5110_CMD_READ_BRANCH:
r249025	r249026
978	940
979	941	void tms5110_device::parse_frame()
980	942	{
981		int bits, i, rep_flag;
982		/ TODO: get rid of bits handling here and move into extract_bits (as in tms5220.c) /
983		/* count the total number of bits available */
984		bits = m_fifo_count;
	943	int i, rep_flag;
985	944
986		/* attempt to extract the energy index */
987		bits -= m_coeff->energy_bits;
988		if (bits < 0)
989		{
990		request_bits( -bits ); /* toggle M0 to receive needed bits */
991		bits = 0;
992		}
993	945	// attempt to extract the energy index
994	946	m_new_frame_energy_idx = extract_bits(m_coeff->energy_bits);
995	947	#ifdef DEBUG_PARSE_FRAME_DUMP
r249025	r249026
997	949	fprintf(stderr," ");
998	950	#endif
999	951
1000		/* if the energy index is 0 or 15, we're done
1001
1002		if ((indx == 0) \|\| (indx == 15))
1003		{
1004		if (DEBUG_5110) logerror(" (4-bit energy=%d frame)\n",m_new_energy);
1005
1006		// clear the k's
1007		if (indx == 0)
1008		{
1009		for (i = 0; i < m_coeff->num_k; i++)
1010		m_new_k[i] = 0;
1011		}
1012
1013		// clear fifo if stop frame encountered
1014		if (indx == 15)
1015		{
1016		if (DEBUG_5110) logerror(" (4-bit energy=%d STOP frame)\n",m_new_energy);
1017		m_fifo_head = m_fifo_tail = m_fifo_count = 0;
1018		}
1019		return;
1020		}*/
1021	952	// if the energy index is 0 or 15, we're done
1022	953	if ((m_new_frame_energy_idx == 0) \|\| (m_new_frame_energy_idx == 15))
1023	954	return;
1024	955
1025
1026		/* attempt to extract the repeat flag */
1027		bits -= 1;
1028		if (bits < 0)
1029		{
1030		request_bits( -bits ); /* toggle M0 to receive needed bits */
1031		bits = 0;
1032		}
1033	956	rep_flag = extract_bits(1);
1034	957	#ifdef DEBUG_PARSE_FRAME_DUMP
1035	958	printbits(rep_flag, 1);
1036	959	fprintf(stderr," ");
1037	960	#endif
1038	961
1039		/* attempt to extract the pitch */
1040		bits -= m_coeff->pitch_bits;
1041		if (bits < 0)
1042		{
1043		request_bits( -bits ); /* toggle M0 to receive needed bits */
1044		bits = 0;
1045		}
1046	962	m_new_frame_pitch_idx = extract_bits(m_coeff->pitch_bits);
1047	963	#ifdef DEBUG_PARSE_FRAME_DUMP
1048	964	printbits(m_new_frame_pitch_idx,m_coeff->pitch_bits);
r249025	r249026
1055	971	// extract first 4 K coefficients
1056	972	for (i = 0; i < 4; i++)
1057	973	{
1058		/* attempt to extract 4 K's */
1059		bits -= m_coeff->kbits[i];
1060		if (bits < 0)
1061		{
1062		request_bits( -bits ); /* toggle M0 to receive needed bits */
1063		bits = 0;
1064		}
1065	974	m_new_frame_k_idx[i] = extract_bits(m_coeff->kbits[i]);
1066	975	#ifdef DEBUG_PARSE_FRAME_DUMP
1067	976	printbits(m_new_frame_k_idx[i],m_coeff->kbits[i]);
r249025	r249026
1079	988	// If we got here, we need the remaining 6 K's
1080	989	for (i = 4; i < m_coeff->num_k; i++)
1081	990	{
1082		bits -= m_coeff->kbits[i];
1083		if (bits < 0)
1084		{
1085		request_bits( -bits ); /* toggle M0 to receive needed bits */
1086		bits = 0;
1087		}
1088	991	m_new_frame_k_idx[i] = extract_bits(m_coeff->kbits[i]);
1089	992	#ifdef DEBUG_PARSE_FRAME_DUMP
1090	993	printbits(m_new_frame_k_idx[i],m_coeff->kbits[i]);
1091	994	fprintf(stderr," ");
1092	995	#endif
1093	996	}
	997	#ifdef DEBUG_PARSE_FRAME_DUMP
	998	fprintf(stderr,"\n");
	999	#endif
1094	1000	#ifdef VERBOSE
1095		if (m_speak_external)
1096		logerror("Parsed a frame successfully in FIFO - %d bits remaining\n", (m_fifo_count*8)-(m_fifo_bits_taken));
1097		else
1098	1001	logerror("Parsed a frame successfully in ROM\n");
1099	1002	#endif
1100	1003	return;
r249025	r249026
1238	1141	void tms5110_device::device_reset()
1239	1142	{
1240	1143	m_digital_select = FORCE_DIGITAL; // assume analog output
1241		/* initialize the FIFO */
1242		memset(m_fifo, 0, sizeof(m_fifo));
1243		m_fifo_head = m_fifo_tail = m_fifo_count = 0;
1244	1144
1245	1145	/* initialize the chip state */
1246	1146	m_SPEN = m_TALK = m_TALKD = 0;
r249025	r249026
1253	1153	#ifdef PERFECT_INTERPOLATION_HACK
1254	1154	m_old_frame_energy_idx = m_old_frame_pitch_idx = 0;
1255	1155	memset(m_old_frame_k_idx, 0, sizeof(m_old_frame_k_idx));
1256		m_old_zpar = 0;
	1156	m_old_zpar = m_old_uv_zpar = 0;
1257	1157	#endif
1258	1158	m_new_frame_energy_idx = m_current_energy = m_previous_energy = 0;
1259	1159	m_new_frame_pitch_idx = m_current_pitch = 0;
r249025	r249026
1390	1290	}
1391	1291
1392	1292
1393
1394	1293	/******************************************************************************
1395	1294
1396		tms5110_ready_r -- return the not ready status from the sound chip
1397
1398		******************************************************************************/
1399
1400		int tms5110_device::ready_r()
1401		{
1402		/* bring up to date first */
1403		m_stream->update();
1404		return (m_fifo_count < FIFO_SIZE-1);
1405		}
1406
1407
1408
1409		/******************************************************************************
1410
1411	1295	tms5110_update -- update the sound chip so that it is in sync with CPU execution
1412	1296
1413	1297	******************************************************************************/

trunk/src/emu/sound/tms5110.h
r249025	r249026
7	7
8	8	#include "emu.h"
9	9
10		#define FIFO_SIZE 64 // TODO: technically the tms51xx chips don't have a fifo at all
	10	/* HACK: if defined, uses impossibly perfect 'straight line' interpolation */
	11	#undef PERFECT_INTERPOLATION_HACK
11	12
12	13	/* TMS5110 commands */
13	14	/* CTL8 CTL4 CTL2 CTL1 \| PDC's */
r249025	r249026
15	16	#define TMS5110_CMD_RESET (0) /* 0 0 0 x \| 1 */
16	17	#define TMS5110_CMD_LOAD_ADDRESS (2) /* 0 0 1 x \| 2 */
17	18	#define TMS5110_CMD_OUTPUT (4) /* 0 1 0 x \| 3 */
18		#define TMS5110_CMD_SPKSLOW (6) /* 0 1 1 x \| 1 \| Note: this command is undocumented on the datasheets, it only appears on the patents. It might not actually work properly on some of the real chips as manufactured. Acts the same as CMD_SPEAK, but makes the interpolator take two A cycles whereever it would normally only take one, effectively making speech of any given word take ~~about~~ twice as long as normal. */
	19	#define TMS5110_CMD_SPKSLOW (6) /* 0 1 1 x \| 1 \| Note: this command is undocumented on the datasheets, it only appears on the patents. It might not actually work properly on some of the real chips as manufactured. Acts the same as CMD_SPEAK, but makes the interpolator take three A cycles whereever it would normally only take one, effectively making speech of any given word take twice as long as normal. */
19	20	#define TMS5110_CMD_READ_BIT (8) /* 1 0 0 x \| 1 */
20	21	#define TMS5110_CMD_SPEAK (10) /* 1 0 1 x \| 1 */
21	22	#define TMS5110_CMD_READ_BRANCH (12) /* 1 1 0 x \| 1 */
r249025	r249026
64	65	*/
65	66	DECLARE_READ8_MEMBER( romclk_hack_r );
66	67
67		int ready_r();
68	68	void set_frequency(int frequency);
69	69
70	70	int _speech_rom_read_bit();
r249025	r249026
93	93	void new_int_write_addr(UINT8 addr);
94	94	UINT8 new_int_read();
95	95	void register_for_save_states();
96		void FIFO_data_write(int data);
97	96	int extract_bits(int count);
98		void request_bits(int no);
99	97	void perform_dummy_read();
100	98	INT32 lattice_filter();
101	99	void process(INT16 *buffer, unsigned int size);
r249025	r249026
109	107	/* coefficient tables */
110	108	const struct tms5100_coeffs *m_coeff;
111	109
112		/* these contain data that describes the 4 bit "FIFO" */
113		UINT8 m_fifo[FIFO_SIZE];
114		UINT8 m_fifo_head;
115		UINT8 m_fifo_tail;
116		UINT8 m_fifo_count;
117
118	110	/* these contain global status bits */
119	111	UINT8 m_PDC;
120	112	UINT8 m_CTL_pins;
r249025	r249026
162	154	UINT8 m_old_frame_pitch_idx;
163	155	UINT8 m_old_frame_k_idx[10];
164	156	UINT8 m_old_zpar;
	157	UINT8 m_old_uv_zpar;
165	158
166	159	INT32 m_current_energy;
167	160	INT32 m_current_pitch;

trunk/src/emu/sound/tms5220.c
r249025	r249026
271	271	* or clip logic, even though the real hardware doesn't do this, partially verified by decap */
272	272	#undef ALLOW_4_LSB
273	273
	274	/* forces m_TALK active instantly whenever m_SPEN would be activated, causing speech delay to be reduced by up to one frame time */
	275	/* for some reason, this hack makes victory behave better, though it does not match the patent */
	276	#define FAST_START_HACK 1
274	277
	278
275	279	/* ***configuration of chip connection stuff*** */
276	280	/* must be defined; if 0, output the waveform as if it was tapped on the speaker pin as usual, if 1, output the waveform as if it was tapped on the i/o pin (volume is much lower in the latter case) */
277	281	#define FORCE_DIGITAL 0
r249025	r249026
361	365	save_item(NAME(m_fifo_count));
362	366	save_item(NAME(m_fifo_bits_taken));
363	367
364		save_item(NAME(m_speaking_now));
365		save_item(NAME(m_speak_external));
366		save_item(NAME(m_talk_status));
	368	save_item(NAME(m_previous_TALK_STATUS));
	369	save_item(NAME(m_SPEN));
	370	save_item(NAME(m_DDIS));
	371	save_item(NAME(m_TALK));
	372	save_item(NAME(m_TALKD));
367	373	save_item(NAME(m_buffer_low));
368	374	save_item(NAME(m_buffer_empty));
369	375	save_item(NAME(m_irq_pin));
r249025	r249026
384	390	save_item(NAME(m_current_pitch));
385	391	save_item(NAME(m_current_k));
386	392
387		save_item(NAME(m_target_energy));
388		save_item(NAME(m_target_pitch));
389		save_item(NAME(m_target_k));
390
391	393	save_item(NAME(m_previous_energy));
392	394
393	395	save_item(NAME(m_subcycle));
r249025	r249026
395	397	save_item(NAME(m_PC));
396	398	save_item(NAME(m_IP));
397	399	save_item(NAME(m_inhibit));
	400	save_item(NAME(m_uv_zpar));
	401	save_item(NAME(m_zpar));
	402	save_item(NAME(m_pitch_zero));
398	403	save_item(NAME(m_c_variant_rate));
399	404	save_item(NAME(m_pitch_count));
400	405
r249025	r249026
465	470
466	471	void tms5220_device::data_write(int data)
467	472	{
	473	int old_buffer_low = m_buffer_low;
468	474	#ifdef DEBUG_DUMP_INPUT_DATA
469	475	fprintf(stdout, "%c",data);
470	476	#endif
471		if (m_~~speak_external~~) // If we're in speak external mode
	477	if (m_DDIS) // If we're in speak external mode
472	478	{
473	479	// add this byte to the FIFO
474	480	if (m_fifo_count < FIFO_SIZE)
r249025	r249026
477	483	m_fifo_tail = (m_fifo_tail + 1) % FIFO_SIZE;
478	484	m_fifo_count++;
479	485	#ifdef DEBUG_FIFO
480		~~log~~err~~or(~~"data_write: Added byte to FIFO (current count=%2d)\n", m_fifo_count);
	486	fprintf(stderr,"data_write: Added byte to FIFO (current count=%2d)\n", m_fifo_count);
481	487	#endif
482	488	update_fifo_status_and_ints();
483		if ((m_talk_status == 0) && (m_buffer_low == 0)) // we just unset buffer low with that last write, and talk status was zero...
	489	// if we just unset buffer low with that last write, and SPEN was zero (see circuit 251, sheet 12)
	490	if ((m_SPEN == 0) && ((old_buffer_low == 1) && (m_buffer_low == 0))) // MUST HAVE EDGE DETECT
484	491	{
485		int i;
	492	int i;
486	493	#ifdef DEBUG_FIFO
487		~~log~~err~~or(~~"data_write triggered ~~talk status~~ to go active!\n");
	494	fprintf(stderr,"data_write triggered SPEN to go active!\n");
488	495	#endif
489		// ...then we now have enough bytes to start talking; clear out the new frame parameters (it will become old frame just before the first call to parse_frame() )
490		// TODO: the 3 lines below (and others) are needed for victory to not fail its selftest due to a sample ending too late, may require additional investigation
491		m_subcycle = m_subc_reload;
492		m_PC = 0;
493		m_IP = reload_table[m_c_variant_rate&0x3]; // is this correct? should this be always 7 instead, so that the new frame is loaded quickly?
	496	// ...then we now have enough bytes to start talking; set zpar and clear out the new frame parameters (it will become old frame just before the first call to parse_frame() )
	497	m_zpar = 1;
	498	m_uv_zpar = 1; // zero k4-k10 as well
	499	m_OLDE = 1; // 'silence/zpar' frames are zero energy
	500	m_OLDP = 1; // 'silence/zpar' frames are zero pitch
	501	#ifdef PERFECT_INTERPOLATION_HACK
	502	m_old_zpar = 1; // zero all the old parameters
	503	m_old_uv_zpar = 1; // zero old k4-k10 as well
	504	#endif
	505	m_SPEN = 1;
	506	#ifdef FAST_START_HACK
	507	m_TALK = 1;
	508	#endif
494	509	m_new_frame_energy_idx = 0;
495	510	m_new_frame_pitch_idx = 0;
496	511	for (i = 0; i < 4; i++)
r249025	r249026
499	514	m_new_frame_k_idx[i] = 0xF;
500	515	for (i = 7; i < m_coeff->num_k; i++)
501	516	m_new_frame_k_idx[i] = 0x7;
502		~~m_talk_status = m_speaking_now = 1;~~
	517
503	518	}
504	519	}
505	520	else
506	521	{
507	522	#ifdef DEBUG_FIFO
508		~~log~~err~~or(~~"data_write: Ran out of room in the tms52xx FIFO! this should never happen!\n");
	523	fprintf(stderr,"data_write: Ran out of room in the tms52xx FIFO! this should never happen!\n");
509	524	// at this point, /READY should remain HIGH/inactive until the fifo has at least one byte open in it.
510	525	#endif
511	526	}
512	527
513	528
514	529	}
515		else //(! m_~~speak_external~~)
	530	else //(! m_DDIS)
516	531	// R Nabet : we parse commands at once. It is necessary for such commands as read.
517	532	process_command(data);
518	533	}
r249025	r249026
560	575	m_buffer_low = 0;
561	576
562	577	/* BE is set if neither byte 15 nor 14 of the fifo are in use; this
563		translates to having fifo_count equal to exactly 0 */
	578	translates to having fifo_count equal to exactly 0
	579	*/
564	580	if (m_fifo_count == 0)
565	581	{
566	582	// generate an interrupt if necessary; if /BE was inactive and is now active, set int.
567	583	if (!m_buffer_empty)
568	584	set_interrupt_state(1);
569	585	m_buffer_empty = 1;
	586	m_TALK = m_SPEN = 0; // /BE being active clears the TALK(TCON) status which in turn clears SPEN
570	587	}
571	588	else
572	589	m_buffer_empty = 0;
573	590
574		/* TS is talk status and is set elsewhere in the fifo parser and in
575		the SPEAK command handler; however, if /BE is true during speak external
576		mode, it is immediately unset here. */
577		if ((m_speak_external == 1) && (m_buffer_empty == 1))
	591	// generate an interrupt if /TS was active, and is now inactive.
	592	// also, in this case, regardless if DDIS was set, unset it.
	593	if (m_previous_TALK_STATUS == 1 && (TALK_STATUS == 0))
578	594	{
579		// generate an interrupt: /TS was active, and is now inactive.
580		if (m_talk_status == 1)
581		{
582		m_talk_status = m_speak_external = 0;
583		set_interrupt_state(1);
584		}
	595	#ifdef VERBOSE
	596	fprintf(stderr,"Talk status WAS 1, is now 0, unsetting DDIS and firing an interrupt!\n");
	597	#endif
	598	set_interrupt_state(1);
	599	m_DDIS = 0;
585	600	}
586		/* Note that TS being unset will also generate an interrupt when a STOP
587		frame is encountered; this is handled in the sample generator code and not here */
	601	m_previous_TALK_STATUS = TALK_STATUS;
	602
588	603	}
589	604
590	605	/**********************************************************************************************
r249025	r249026
597	612	{
598	613	int val = 0;
599	614
600		if (m_~~speak_external~~)
	615	if (m_DDIS)
601	616	{
602	617	// extract from FIFO
603	618	while (count--)
r249025	r249026
643	658	/* clear the interrupt pin on status read */
644	659	set_interrupt_state(0);
645	660	#ifdef DEBUG_PIN_READS
646		~~log~~err~~or(~~"Status read: TS=%d BL=%d BE=%d\n", m_~~talk_status~~, m_buffer_low, m_buffer_empty);
	661	fprintf(stderr,"Status read: TS=%d BL=%d BE=%d\n", TALK_STATUS, m_buffer_low, m_buffer_empty);
647	662	#endif
648	663
649		return (m_~~talk_status~~ << 7) \| (m_buffer_low << 6) \| (m_buffer_empty << 5);
	664	return (TALK_STATUS << 7) \| (m_buffer_low << 6) \| (m_buffer_empty << 5);
650	665	}
651	666	}
652	667
r249025	r249026
660	675	int tms5220_device::ready_read()
661	676	{
662	677	#ifdef DEBUG_PIN_READS
663		~~log~~err~~or(~~"ready_read: ready pin read, io_ready is %d, fifo count is %d\n", m_io_ready, m_fifo_count);
	678	fprintf(stderr,"ready_read: ready pin read, io_ready is %d, fifo count is %d, DDIS(speak external) is %d\n", m_io_ready, m_fifo_count, m_DDIS);
664	679	#endif
665		return ((m_fifo_count < FIFO_SIZE)\|\|(!m_~~speak_external~~)) && m_io_ready;
	680	return ((m_fifo_count < FIFO_SIZE)\|\|(!m_DDIS)) && m_io_ready;
666	681	}
667	682
668	683
r249025	r249026
718	733	int tms5220_device::int_read()
719	734	{
720	735	#ifdef DEBUG_PIN_READS
721		~~log~~err~~or(~~"int_read: irq pin read, state is %d\n", m_irq_pin);
	736	fprintf(stderr,"int_read: irq pin read, state is %d\n", m_irq_pin);
722	737	#endif
723	738	return m_irq_pin;
724	739	}
r249025	r249026
733	748	void tms5220_device::process(INT16 *buffer, unsigned int size)
734	749	{
735	750	int buf_count=0;
736		int i, bitout~~, zpar~~;
	751	int i, bitout;
737	752	INT32 this_sample;
738	753
739		/* the following gotos are probably safe to remove */
740		/* if we're empty and still not speaking, fill with nothingness */
741		if (!m_speaking_now)
742		goto empty;
	754	#ifdef VERBOSE
	755	fprintf(stderr,"process called with size of %d; IP=%d, PC=%d, subcycle=%d, m_SPEN=%d, m_TALK=%d, m_TALKD=%d\n", size, m_IP, m_PC, m_subcycle, m_SPEN, m_TALK, m_TALKD);
	756	#endif
743	757
744		/* if speak external is set, but talk status is not (yet) set,
745		wait for buffer low to clear */
746		if (!m_talk_status && m_speak_external && m_buffer_low)
747		goto empty;
748
749	758	/* loop until the buffer is full or we've stopped speaking */
750		while ((size > 0~~) && m_speaking_now~~)
	759	while (size > 0)
751	760	{
752		/* if it is the appropriate time to update the old energy/pitch indices,
753		* i.e. when IP=7, PC=12, T=17, subcycle=2, do so. Since IP=7 PC=12 T=17
754		* is JUST BEFORE the transition to IP=0 PC=0 T=0 sybcycle=(0 or 1),
755		* which happens 4 T-cycles later), we change on the latter.
756		* The indices are updated here ~12 PCs before the new frame is applied.
757		*/
758		/ TODO: the patents 4331836, 4335277, and 4419540 disagree about the timing of this /
759		if ((m_IP == 0) && (m_PC == 0) && (m_subcycle < 2))
	761	if(m_TALKD) // speaking
760	762	{
761		m_OLDE = (m_new_frame_energy_idx == 0);
762		m_OLDP = (m_new_frame_pitch_idx == 0);
763		}
	763	/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
	764	* (In reality, the frame was really loaded incrementally during the entire IP=0
	765	* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
	766	*/
	767	if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
	768	{
	769	// HACK for regression testing, be sure to comment out before release!
	770	//m_RNG = 0x1234;
	771	// end HACK
764	772
765		/* if we're ready for a new frame to be applied, i.e. when IP=0, PC=12, Sub=1
766		* (In reality, the frame was really loaded incrementally during the entire IP=0
767		* PC=x time period, but it doesn't affect anything until IP=0 PC=12 happens)
768		*/
769		if ((m_IP == 0) && (m_PC == 12) && (m_subcycle == 1))
770		{
771		// HACK for regression testing, be sure to comment out before release!
772		//m_RNG = 0x1234;
773		// end HACK
	773	/* appropriately override the interp count if needed; this will be incremented after the frame parse! */
	774	m_IP = reload_table[m_c_variant_rate&0x3];
774	775
775		/* appropriately override the interp count if needed; this will be incremented after the frame parse! */
776		m_IP = reload_table[m_c_variant_rate&0x3];
777
778	776	#ifdef PERFECT_INTERPOLATION_HACK
779		/* remember previous frame energy, pitch, and coefficients */
780		m_old_frame_energy_idx = m_new_frame_energy_idx;
781		m_old_frame_pitch_idx = m_new_frame_pitch_idx;
782		for (i = 0; i < m_coeff->num_k; i++)
783		m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
	777	/* remember previous frame energy, pitch, and coefficients */
	778	m_old_frame_energy_idx = m_new_frame_energy_idx;
	779	m_old_frame_pitch_idx = m_new_frame_pitch_idx;
	780	for (i = 0; i < m_coeff->num_k; i++)
	781	m_old_frame_k_idx[i] = m_new_frame_k_idx[i];
784	782	#endif
785	783
786		/* if the talk status was clear last frame, halt speech now. */
787		if (m_talk_status == 0)
788		{
789		#ifdef DEBUG_GENERATION
790		fprintf(stderr,"tms5220_process: processing frame: talk status = 0 caused by stop frame or buffer empty, halting speech.\n");
791		#endif
792		if (m_speaking_now == 1) // we're done, set all coeffs to idle state but keep going for a bit...
793		{
794		/TODO: should index clearing be done here, or elsewhere? /
795		m_new_frame_energy_idx = 0;
796		m_new_frame_pitch_idx = 0;
797		for (i = 0; i < 4; i++)
798		m_new_frame_k_idx[i] = 0;
799		for (i = 4; i < 7; i++)
800		m_new_frame_k_idx[i] = 0xF;
801		for (i = 7; i < m_coeff->num_k; i++)
802		m_new_frame_k_idx[i] = 0x7;
803		m_speaking_now = 2; // wait 8 extra interp periods before shutting down so we can interpolate everything to zero state
804		}
805		else // m_speaking_now == 2 // now we're really done.
806		{
807		m_speaking_now = 0; // finally halt speech
808		goto empty;
809		}
810		}
	784	/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[] */
	785	parse_frame();
811	786
812
813		/* Parse a new frame into the new_target_energy, new_target_pitch and new_target_k[],
814		* but only if we're not just about to end speech */
815		if (m_speaking_now == 1) parse_frame();
816		#ifdef DEBUG_PARSE_FRAME_DUMP
817		fprintf(stderr,"\n");
	787	// if the new frame is unvoiced (or silenced via ZPAR), be sure to zero out the k5-k10 parameters
	788	// NOTE: this is probably the bug the tms5100/tmc0280 has, pre-rev D, I think.
	789	// GUESS: Pre-rev D versions start zeroing k5-k10 immediately upon new frame load regardless of interpolation inhibit
	790	// I.e. ZPAR = /TALKD \|\| (PC>5&&P=0)
	791	// GUESS: D and later versions only start or stop zeroing k5-k10 at the IP7->IP0 transition AFTER the frame
	792	// I.e. ZPAR = /TALKD \|\| (PC>5&&OLDP)
	793	#ifdef PERFECT_INTERPOLATION_HACK
	794	m_old_uv_zpar = m_uv_zpar;
	795	m_old_zpar = m_zpar; // unset old zpar on new frame
818	796	#endif
	797	m_zpar = 0;
	798	//m_uv_zpar = (OLD_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: fixed version in tmc0280d/tms5100a/cd280x/tms5110
	799	m_uv_zpar = (NEW_FRAME_UNVOICED_FLAG\|\|m_zpar); // GUESS: buggy version in tmc0280/tms5100
819	800
820		/* if the new frame is a stop frame, set an interrupt and set talk status to 0 */
821		/ TODO: investigate this later! /
822		if (NEW_FRAME_STOP_FLAG == 1)
	801	/* if the new frame is a stop frame, unset both TALK and SPEN (via TCON). TALKD remains active while the energy is ramping to 0. */
	802	if (NEW_FRAME_STOP_FLAG == 1)
823	803	{
824		m_talk_status = m_speak_external = 0;
825		set_interrupt_state(1);
826		update_fifo_status_and_ints();
	804	m_TALK = m_SPEN = 0;
827	805	}
828	806
829		/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
830		Interpolation inhibit cases:
831		* Old frame was voiced, new is unvoiced
832		* Old frame was silence/zero energy, new has nonzero energy
833		* Old frame was unvoiced, new is voiced
834		* Old frame was unvoiced, new frame is silence/zero energy (unique to tms52xx)
835		*/
836		if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
837		\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
838		\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0))
839		\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 1)) )
840		m_inhibit = 1;
841		else // normal frame, normal interpolation
842		m_inhibit = 0;
	807	/* in all cases where interpolation would be inhibited, set the inhibit flag; otherwise clear it.
	808	Interpolation inhibit cases:
	809	* Old frame was voiced, new is unvoiced
	810	* Old frame was silence/zero energy, new has nonzero energy
	811	* Old frame was unvoiced, new is voiced
	812	* Old frame was unvoiced, new frame is silence/zero energy (unique to tms52xx)
	813	*/
	814	if ( ((OLD_FRAME_UNVOICED_FLAG == 0) && (NEW_FRAME_UNVOICED_FLAG == 1))
	815	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_UNVOICED_FLAG == 0))
	816	\|\| ((OLD_FRAME_SILENCE_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 0))
	817	\|\| ((OLD_FRAME_UNVOICED_FLAG == 1) && (NEW_FRAME_SILENCE_FLAG == 1)) )
	818	m_inhibit = 1;
	819	else // normal frame, normal interpolation
	820	m_inhibit = 0;
843	821
844		/* load new frame targets from tables, using parsed indices */
845		m_target_energy = m_coeff->energytable[m_new_frame_energy_idx];
846		m_target_pitch = m_coeff->pitchtable[m_new_frame_pitch_idx];
847		zpar = NEW_FRAME_UNVOICED_FLAG; // find out if parameters k5-k10 should be zeroed
848		for (i = 0; i < 4; i++)
849		m_target_k[i] = m_coeff->ktable[i][m_new_frame_k_idx[i]];
850		for (i = 4; i < m_coeff->num_k; i++)
851		m_target_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-zpar));
852
853	822	#ifdef DEBUG_GENERATION
854		/* Debug info for current parsed frame */
855		fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
856		fprintf(stderr,"Processing frame: ");
857		if (m_inhibit == 0)
858		fprintf(stderr, "Normal Frame\n");
859		else
860		fprintf(stderr,"Interpolation Inhibited\n");
861		fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
862		fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_target_energy, m_new_frame_energy_idx, m_target_pitch, m_target_k[0], m_target_k[1], m_target_k[2], m_target_k[3], m_target_k[4], m_target_k[5], m_target_k[6], m_target_k[7], m_target_k[8], m_target_k[9]);
	823	/* Debug info for current parsed frame */
	824	fprintf(stderr, "OLDE: %d; OLDP: %d; ", m_OLDE, m_OLDP);
	825	fprintf(stderr,"Processing new frame: ");
	826	if (m_inhibit == 0)
	827	fprintf(stderr, "Normal Frame\n");
	828	else
	829	fprintf(stderr,"Interpolation Inhibited\n");
	830	fprintf(stderr,"*** current Energy, Pitch and Ks = %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",m_current_energy, m_current_pitch, m_current_k[0], m_current_k[1], m_current_k[2], m_current_k[3], m_current_k[4], m_current_k[5], m_current_k[6], m_current_k[7], m_current_k[8], m_current_k[9]);
	831	fprintf(stderr,"*** target Energy(idx), Pitch, and Ks = %04d(%x),%04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d, %04d\n",
	832	(m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar)),
	833	m_new_frame_energy_idx,
	834	(m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar)),
	835	(m_coeff->ktable[0][m_new_frame_k_idx[0]] * (1-m_zpar)),
	836	(m_coeff->ktable[1][m_new_frame_k_idx[1]] * (1-m_zpar)),
	837	(m_coeff->ktable[2][m_new_frame_k_idx[2]] * (1-m_zpar)),
	838	(m_coeff->ktable[3][m_new_frame_k_idx[3]] * (1-m_zpar)),
	839	(m_coeff->ktable[4][m_new_frame_k_idx[4]] * (1-m_uv_zpar)),
	840	(m_coeff->ktable[5][m_new_frame_k_idx[5]] * (1-m_uv_zpar)),
	841	(m_coeff->ktable[6][m_new_frame_k_idx[6]] * (1-m_uv_zpar)),
	842	(m_coeff->ktable[7][m_new_frame_k_idx[7]] * (1-m_uv_zpar)),
	843	(m_coeff->ktable[8][m_new_frame_k_idx[8]] * (1-m_uv_zpar)),
	844	(m_coeff->ktable[9][m_new_frame_k_idx[9]] * (1-m_uv_zpar)) );
863	845	#endif
864	846
865		/* if TS is now 0, ramp the energy down to 0. Is this really correct to hardware? */
866		if (m_talk_status == 0)
	847	}
	848	else // Not a new frame, just interpolate the existing frame.
867	849	{
868		#ifdef DEBUG_GENERATION
869		fprintf(stderr,"Talk status is 0, forcing target energy to 0\n");
	850	int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
	851	#ifdef PERFECT_INTERPOLATION_HACK
	852	int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
	853	//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
	854	int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
	855	//fprintf(stderr, "CS: %03d", current_sample);
	856	// reset the current energy, pitch, etc to what it was at frame start
	857	m_current_energy = (m_coeff->energytable[m_old_frame_energy_idx] * (1-m_old_zpar));
	858	m_current_pitch = (m_coeff->pitchtable[m_old_frame_pitch_idx] * (1-m_old_zpar));
	859	for (i = 0; i < m_coeff->num_k; i++)
	860	m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-((i<4)?m_old_zpar:m_old_uv_zpar)));
	861	// now adjust each value to be exactly correct for each of the samples per frame
	862	if (m_IP != 0) // if we're still interpolating...
	863	{
	864	m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
	865	m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame)*(1-m_zpar);
	866	for (i = 0; i < m_coeff->num_k; i++)
	867	m_current_k[i] = (m_current_k[i] + (((m_coeff->ktable[i][m_new_frame_k_idx[i]] - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame)*(1-((i<4)?m_zpar:m_uv_zpar));
	868	}
	869	else // we're done, play this frame for 1/8 frame.
	870	{
	871	m_current_energy = (m_coeff->energytable[m_new_frame_energy_idx] * (1-m_zpar));
	872	m_current_pitch = (m_coeff->pitchtable[m_new_frame_pitch_idx] * (1-m_zpar));
	873	for (i = 0; i < m_coeff->num_k; i++)
	874	m_current_k[i] = (m_coeff->ktable[i][m_new_frame_k_idx[i]] * (1-((i<4)?m_zpar:m_uv_zpar)));
	875	}
	876	#else
	877	//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
	878	if (m_subcycle == 2)
	879	{
	880	switch(m_PC)
	881	{
	882	case 0: /* PC = 0, B cycle, write updated energy */
	883	m_current_energy = (m_current_energy + (((m_coeff->energytable[m_new_frame_energy_idx] - m_current_energy)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
	884	break;
	885	case 1: /* PC = 1, B cycle, write updated pitch */
	886	m_current_pitch = (m_current_pitch + (((m_coeff->pitchtable[m_new_frame_pitch_idx] - m_current_pitch)(1-inhibit_state)) INTERP_SHIFT))(1-m_zpar);
	887	break;
	888	case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
	889	/* PC = 2 through 11, B cycle, write updated K1 through K10 */
	890	m_current_k[m_PC-2] = (m_current_k[m_PC-2] + (((m_coeff->ktable[m_PC-2][m_new_frame_k_idx[m_PC-2]] - m_current_k[m_PC-2])(1-inhibit_state)) INTERP_SHIFT))(((m_PC-2)>4)?(1-m_uv_zpar):(1-m_zpar));
	891	break;
	892	case 12: /* PC = 12 */
	893	/* we should NEVER reach this point, PC=12 doesn't have a subcycle 2 */
	894	break;
	895	}
	896	}
870	897	#endif
871		m_target_energy = 0;
872	898	}
873		}
874		else // Not a new frame, just interpolate the existing frame.
875		{
876		int inhibit_state = ((m_inhibit==1)&&(m_IP != 0)); // disable inhibit when reaching the last interp period, but don't overwrite the m_inhibit value
877		#ifdef PERFECT_INTERPOLATION_HACK
878		int samples_per_frame = m_subc_reload?175:266; // either (13 A cycles + 12 B cycles) * 7 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 7 interps for SPKSLOW
879		//int samples_per_frame = m_subc_reload?200:304; // either (13 A cycles + 12 B cycles) * 8 interps for normal SPEAK/SPKEXT, or (132 A cycles + 12 B cycles) 8 interps for SPKSLOW
880		int current_sample = (m_subcycle - m_subc_reload)+(m_PC(3-m_subc_reload))+((m_subc_reload?25:38)((m_IP-1)&7));
881	899
882		zpar = OLD_FRAME_UNVOICED_FLAG;
883		//fprintf(stderr, "CS: %03d", current_sample);
884		// reset the current energy, pitch, etc to what it was at frame start
885		m_current_energy = m_coeff->energytable[m_old_frame_energy_idx];
886		m_current_pitch = m_coeff->pitchtable[m_old_frame_pitch_idx];
887		for (i = 0; i < 4; i++)
888		m_current_k[i] = m_coeff->ktable[i][m_old_frame_k_idx[i]];
889		for (i = 4; i < m_coeff->num_k; i++)
890		m_current_k[i] = (m_coeff->ktable[i][m_old_frame_k_idx[i]] * (1-zpar));
891		// now adjust each value to be exactly correct for each of the samples per frame
892		if (m_IP != 0) // if we're still interpolating...
	900	// calculate the output
	901	if (OLD_FRAME_UNVOICED_FLAG == 1)
893	902	{
894		m_current_energy += (((m_target_energy - m_current_energy)(1-inhibit_state))current_sample)/samples_per_frame;
895		m_current_pitch += (((m_target_pitch - m_current_pitch)(1-inhibit_state))current_sample)/samples_per_frame;
896		for (i = 0; i < m_coeff->num_k; i++)
897		m_current_k[i] += (((m_target_k[i] - m_current_k[i])(1-inhibit_state))current_sample)/samples_per_frame;
	903	// generate unvoiced samples here
	904	if (m_RNG & 1)
	905	m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
	906	else
	907	m_excitation_data = 0x40;
898	908	}
899		else // ~~we're~~ ~~done,~~ ~~play~~ ~~this frame for 1~~/~~8 frame.~~
	909	else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
900	910	{
901		m_current_energy = m_target_energy;
902		m_current_pitch = m_target_pitch;
903		for (i = 0; i < m_coeff->num_k; i++)
904		m_current_k[i] = m_target_k[i];
	911	// generate voiced samples here
	912	/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
	913	* function has a chirp/peak and then a long chain of zeroes.
	914	* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
	915	* and if the address reaches that point the ADDRESS incrementer is
	916	* disabled, forcing all samples beyond 51d to be == 51d
	917	*/
	918	if (m_pitch_count >= 51)
	919	m_excitation_data = (INT8)m_coeff->chirptable[51];
	920	else /m_pitch_count < 51/
	921	m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
905	922	}
906		#else
907		//Updates to parameters only happen on subcycle '2' (B cycle) of PCs.
908		if (m_subcycle == 2)
	923
	924	// Update LFSR 20 times every sample (once per T cycle), like patent shows
	925	for (i=0; i<20; i++)
909	926	{
910		switch(m_PC)
911		{
912		case 0: /* PC = 0, B cycle, write updated energy */
913		m_current_energy += (((m_target_energy - m_current_energy)*(1-inhibit_state)) INTERP_SHIFT);
914		break;
915		case 1: /* PC = 1, B cycle, write updated pitch */
916		m_current_pitch += (((m_target_pitch - m_current_pitch)*(1-inhibit_state)) INTERP_SHIFT);
917		break;
918		case 2: case 3: case 4: case 5: case 6: case 7: case 8: case 9: case 10: case 11:
919		/* PC = 2 through 11, B cycle, write updated K1 through K10 */
920		m_current_k[m_PC-2] += (((m_target_k[m_PC-2] - m_current_k[m_PC-2])*(1-inhibit_state)) INTERP_SHIFT);
921		break;
922		case 12: /* PC = 12, do nothing */
923		break;
924		}
	927	bitout = ((m_RNG >> 12) & 1) ^
	928	((m_RNG >> 3) & 1) ^
	929	((m_RNG >> 2) & 1) ^
	930	((m_RNG >> 0) & 1);
	931	m_RNG <<= 1;
	932	m_RNG \|= bitout;
925	933	}
926		#endif
927		}
928
929		// calculate the output
930		if (OLD_FRAME_UNVOICED_FLAG == 1)
931		{
932		// generate unvoiced samples here
933		if (m_RNG & 1)
934		m_excitation_data = ~0x3F; /* according to the patent it is (either + or -) half of the maximum value in the chirp table, so either 01000000(0x40) or 11000000(0xC0)*/
935		else
936		m_excitation_data = 0x40;
937		}
938		else /* (OLD_FRAME_UNVOICED_FLAG == 0) */
939		{
940		// generate voiced samples here
941		/* US patent 4331836 Figure 14B shows, and logic would hold, that a pitch based chirp
942		* function has a chirp/peak and then a long chain of zeroes.
943		* The last entry of the chirp rom is at address 0b110011 (51d), the 52nd sample,
944		* and if the address reaches that point the ADDRESS incrementer is
945		* disabled, forcing all samples beyond 51d to be == 51d
946		*/
947		if (m_pitch_count >= 51)
948		m_excitation_data = (INT8)m_coeff->chirptable[51];
949		else /m_pitch_count < 51/
950		m_excitation_data = (INT8)m_coeff->chirptable[m_pitch_count];
951		}
952
953		// Update LFSR 20 times every sample (once per T cycle), like patent shows
954		for (i=0; i<20; i++)
955		{
956		bitout = ((m_RNG >> 12) & 1) ^
957		((m_RNG >> 3) & 1) ^
958		((m_RNG >> 2) & 1) ^
959		((m_RNG >> 0) & 1);
960		m_RNG <<= 1;
961		m_RNG \|= bitout;
962		}
963		this_sample = lattice_filter(); /* execute lattice filter */
	934	this_sample = lattice_filter(); /* execute lattice filter */
964	935	#ifdef DEBUG_GENERATION_VERBOSE
965		//fprintf(stderr,"C:%01d; ",m_subcycle);
966		fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
967		//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
968		for (i=0; i<10; i++)
969		fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
970		fprintf(stderr,"Out:%06d", this_sample);
971		fprintf(stderr,"\n");
	936	//fprintf(stderr,"C:%01d; ",m_subcycle);
	937	fprintf(stderr,"IP:%01d PC:%02d X:%04d E:%03d P:%03d Pc:%03d ",m_IP, m_PC, m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	938	//fprintf(stderr,"X:%04d E:%03d P:%03d Pc:%03d ", m_excitation_data, m_current_energy, m_current_pitch, m_pitch_count);
	939	for (i=0; i<10; i++)
	940	fprintf(stderr,"K%d:%04d ", i+1, m_current_k[i]);
	941	fprintf(stderr,"Out:%06d ", this_sample);
	942	//#ifdef PERFECT_INTERPOLATION_HACK
	943	// fprintf(stderr,"%d%d%d%d",m_old_zpar,m_zpar,m_old_uv_zpar,m_uv_zpar);
	944	//#else
	945	// fprintf(stderr,"x%dx%d",m_zpar,m_uv_zpar);
	946	//#endif
	947	fprintf(stderr,"\n");
972	948	#endif
973		/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
974		while (this_sample > 16383) this_sample -= 32768;
975		while (this_sample < -16384) this_sample += 32768;
976		if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
977		buffer[buf_count] = clip_analog(this_sample);
978		else // digital I/O pin output is 12 bits
979		{
	949	/* next, force result to 14 bits (since its possible that the addition at the final (k1) stage of the lattice overflowed) */
	950	while (this_sample > 16383) this_sample -= 32768;
	951	while (this_sample < -16384) this_sample += 32768;
	952	if (m_digital_select == 0) // analog SPK pin output is only 8 bits, with clipping
	953	buffer[buf_count] = clip_analog(this_sample);
	954	else // digital I/O pin output is 12 bits
	955	{
980	956	#ifdef ALLOW_4_LSB
981		// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
982		// N taps: ^ = 0x2000;
983		// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
984		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
	957	// input: ssss ssss ssss ssss ssnn nnnn nnnn nnnn
	958	// N taps: ^ = 0x2000;
	959	// output: ssss ssss ssss ssss snnn nnnn nnnn nnnN
	960	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x2000)>>13);
985	961	#else
986		this_sample &= ~0xF;
987		// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
988		// N taps: ^^ ^^^ = 0x3E00;
989		// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
990		buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
	962	this_sample &= ~0xF;
	963	// input: ssss ssss ssss ssss ssnn nnnn nnnn 0000
	964	// N taps: ^^ ^^^ = 0x3E00;
	965	// output: ssss ssss ssss ssss snnn nnnn nnnN NNNN
	966	buffer[buf_count] = (this_sample<<1)\|((this_sample&0x3E00)>>9);
991	967	#endif
992		}
993		// Update all counts
	968	}
	969	// Update all counts
994	970
995		m_subcycle++;
996		if ((m_subcycle == 2) && (m_PC == 12))
997		{
998		/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
999		* if INHIBIT was true during the most recent frame transition.
1000		* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
1001		* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
1002		* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
1003		* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
1004		* convenient and should make no difference in output.
1005		*/
1006		if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_count = 0;
1007		m_subcycle = m_subc_reload;
1008		m_PC = 0;
1009		m_IP++;
1010		m_IP&=0x7;
	971	m_subcycle++;
	972	if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
	973	{
	974	/* Circuit 412 in the patent acts a reset, resetting the pitch counter to 0
	975	* if INHIBIT was true during the most recent frame transition.
	976	* The exact time this occurs is betwen IP=7, PC=12 sub=0, T=t12
	977	* and m_IP = 0, PC=0 sub=0, T=t12, a period of exactly 20 cycles,
	978	* which overlaps the time OLDE and OLDP are updated at IP=7 PC=12 T17
	979	* (and hence INHIBIT itself 2 t-cycles later). We do it here because it is
	980	* convenient and should make no difference in output.
	981	*/
	982	if ((m_IP == 7)&&(m_inhibit==1)) m_pitch_zero = 1;
	983	if ((m_IP == 0)&&(m_pitch_zero==1)) m_pitch_zero = 0;
	984	if (m_IP == 7) // RESETL4
	985	{
	986	// Latch OLDE and OLDP
	987	OLD_FRAME_SILENCE_FLAG = NEW_FRAME_SILENCE_FLAG; // m_OLDE
	988	OLD_FRAME_UNVOICED_FLAG = NEW_FRAME_UNVOICED_FLAG; // m_OLDP
	989	/* if TALK was clear last frame, halt speech now, since TALKD (latched from TALK on new frame) just went inactive. */
	990	#ifdef DEBUG_GENERATION
	991	fprintf(stderr,"RESETL4, about to update status: IP=%d, PC=%d, subcycle=%d, m_SPEN=%d, m_TALK=%d, m_TALKD=%d\n", m_IP, m_PC, m_subcycle, m_SPEN, m_TALK, m_TALKD);
	992	#endif
	993	#ifdef DEBUG_GENERATION
	994	if (m_TALK == 0)
	995	fprintf(stderr,"tms5220_process: processing frame: TALKD = 0 caused by stop frame or buffer empty, halting speech.\n");
	996	#endif
	997	m_TALKD = m_TALK; // TALKD is latched from TALK
	998	update_fifo_status_and_ints(); // to trigger an interrupt if TALK_STATUS is now inactive
	999	m_TALK = m_SPEN; // TALK is latched from SPEN
	1000	#ifdef DEBUG_GENERATION
	1001	fprintf(stderr,"RESETL4, status updated: IP=%d, PC=%d, subcycle=%d, m_SPEN=%d, m_TALK=%d, m_TALKD=%d\n", m_IP, m_PC, m_subcycle, m_SPEN, m_TALK, m_TALKD);
	1002	#endif
	1003	}
	1004	m_subcycle = m_subc_reload;
	1005	m_PC = 0;
	1006	m_IP++;
	1007	m_IP&=0x7;
	1008	}
	1009	else if (m_subcycle == 3)
	1010	{
	1011	m_subcycle = m_subc_reload;
	1012	m_PC++;
	1013	}
	1014	m_pitch_count++;
	1015	if ((m_pitch_count >= m_current_pitch)\|\|(m_pitch_zero == 1)) m_pitch_count = 0;
	1016	m_pitch_count &= 0x1FF;
1011	1017	}
1012		else if (m_~~subcycle~~ == 3)
	1018	else // m_TALKD == 0
1013	1019	{
1014		m_subcycle = m_subc_reload;
1015		m_PC++;
	1020	m_subcycle++;
	1021	if ((m_subcycle == 2) && (m_PC == 12)) // RESETF3
	1022	{
	1023	if (m_IP == 7) // RESETL4
	1024	{
	1025	m_TALKD = m_TALK; // TALKD is latched from TALK
	1026	m_TALK = m_SPEN; // TALK is latched from SPEN
	1027	}
	1028	m_subcycle = m_subc_reload;
	1029	m_PC = 0;
	1030	m_IP++;
	1031	m_IP&=0x7;
	1032	}
	1033	else if (m_subcycle == 3)
	1034	{
	1035	m_subcycle = m_subc_reload;
	1036	m_PC++;
	1037	}
	1038	buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
1016	1039	}
1017		m_pitch_count++;
1018		if (m_pitch_count >= m_current_pitch) m_pitch_count = 0;
1019		m_pitch_count &= 0x1FF;
1020		buf_count++;
1021		size--;
	1040	buf_count++;
	1041	size--;
1022	1042	}
1023
1024		empty:
1025
1026		while (size > 0)
1027		{
1028		m_subcycle++;
1029		if ((m_subcycle == 2) && (m_PC == 12))
1030		{
1031		m_subcycle = m_subc_reload;
1032		m_PC = 0;
1033		m_IP++;
1034		m_IP&=0x7;
1035		}
1036		else if (m_subcycle == 3)
1037		{
1038		m_subcycle = m_subc_reload;
1039		m_PC++;
1040		}
1041		buffer[buf_count] = -1; /* should be just -1; actual chip outputs -1 every idle sample; (cf note in data sheet, p 10, table 4) */
1042		buf_count++;
1043		size--;
1044		}
1045	1043	}
1046	1044
1047	1045	/**********************************************************************************************
r249025	r249026
1182	1180
1183	1181	void tms5220_device::process_command(unsigned char cmd)
1184	1182	{
	1183	int i;
1185	1184	#ifdef DEBUG_COMMAND_DUMP
1186	1185	fprintf(stderr,"process_command called with parameter %02X\n",cmd);
1187	1186	#endif
r249025	r249026
1189	1188	switch (cmd & 0x70)
1190	1189	{
1191	1190	case 0x10 : /* read byte */
1192		if (m_~~talk_status~~ == 0) /* TALKST must be clear for RDBY */
	1191	if (TALK_STATUS == 0) /* TALKST must be clear for RDBY */
1193	1192	{
1194	1193	if (m_schedule_dummy_read)
1195	1194	{
r249025	r249026
1211	1210	break;
1212	1211
1213	1212	case 0x30 : /* read and branch */
1214		if (m_~~talk_status~~ == 0) /* TALKST must be clear for RB */
	1213	if (TALK_STATUS == 0) /* TALKST must be clear for RB */
1215	1214	{
1216	1215	#ifdef VERBOSE
1217		~~log~~err~~or(~~"read and branch command received\n");
	1216	fprintf(stderr,"read and branch command received\n");
1218	1217	#endif
1219	1218	m_RDB_flag = FALSE;
1220	1219	if (m_speechrom)
r249025	r249026
1223	1222	break;
1224	1223
1225	1224	case 0x40 : /* load address */
1226		if (m_~~talk_status~~ == 0) /* TALKST must be clear for LA */
	1225	if (TALK_STATUS == 0) /* TALKST must be clear for LA */
1227	1226	{
1228	1227	/* tms5220 data sheet says that if we load only one 4-bit nibble, it won't work.
1229	1228	This code does not care about this. */
r249025	r249026
1240	1239	if (m_speechrom)
1241	1240	m_speechrom->read(1);
1242	1241	}
1243		m_speaking_now = 1;
1244		m_speak_external = 0;
1245		m_talk_status = 1; /* start immediately */
1246		/* clear out variables before speaking */
1247		// TODO: similar to the victory case described above, but for VSM speech
1248		m_subcycle = m_subc_reload;
1249		m_PC = 0;
1250		m_IP = reload_table[m_c_variant_rate&0x3];
	1242	m_SPEN = 1;
	1243	#ifdef FAST_START_HACK
	1244	m_TALK = 1;
	1245	#endif
	1246	m_DDIS = 0;
	1247	m_zpar = 1; // zero all the parameters
	1248	m_uv_zpar = 1; // zero k4-k10 as well
	1249	m_OLDE = 1; // 'silence/zpar' frames are zero energy
	1250	m_OLDP = 1; // 'silence/zpar' frames are zero pitch
	1251	#ifdef PERFECT_INTERPOLATION_HACK
	1252	m_old_zpar = 1; // zero all the old parameters
	1253	m_old_uv_zpar = 1; // zero old k4-k10 as well
	1254	#endif
	1255	// following is semi-hack but matches idle state observed on chip
1251	1256	m_new_frame_energy_idx = 0;
1252	1257	m_new_frame_pitch_idx = 0;
1253		int i;
1254	1258	for (i = 0; i < 4; i++)
1255	1259	m_new_frame_k_idx[i] = 0;
1256	1260	for (i = 4; i < 7; i++)
r249025	r249026
1260	1264	break;
1261	1265
1262	1266	case 0x60 : /* speak external */
1263		//SPKEXT going active activates SPKEE which clears the fifo
	1267	// SPKEXT going active activates SPKEE which clears the fifo
1264	1268	m_fifo_head = m_fifo_tail = m_fifo_count = m_fifo_bits_taken = 0;
1265		m_speak_external = 1;
	1269	// SPEN is enabled when the fifo passes half full (falling edge of BL signal)
	1270	m_DDIS = 1;
	1271	m_zpar = 1; // zero all the parameters
	1272	m_uv_zpar = 1; // zero k4-k10 as well
	1273	m_OLDE = 1; // 'silence/zpar' frames are zero energy
	1274	m_OLDP = 1; // 'silence/zpar' frames are zero pitch
	1275	#ifdef PERFECT_INTERPOLATION_HACK
	1276	m_old_zpar = 1; // zero all the old parameters
	1277	m_old_uv_zpar = 1; // zero old k4-k10 as well
	1278	#endif
	1279	// following is semi-hack but matches idle state observed on chip
	1280	m_new_frame_energy_idx = 0;
	1281	m_new_frame_pitch_idx = 0;
	1282	for (i = 0; i < 4; i++)
	1283	m_new_frame_k_idx[i] = 0;
	1284	for (i = 4; i < 7; i++)
	1285	m_new_frame_k_idx[i] = 0xF;
	1286	for (i = 7; i < m_coeff->num_k; i++)
	1287	m_new_frame_k_idx[i] = 0x7;
1266	1288	m_RDB_flag = FALSE;
1267	1289	break;
1268	1290
r249025	r249026
1308	1330	m_IP = reload_table[m_c_variant_rate&0x3];
1309	1331
1310	1332	update_fifo_status_and_ints();
1311		if (!m_~~talk~~_~~stat~~us) goto ranout;
	1333	if (m_DDIS && m_buffer_empty) goto ranout;
1312	1334
1313	1335	// attempt to extract the energy index
1314	1336	m_new_frame_energy_idx = extract_bits(m_coeff->energy_bits);
r249025	r249026
1317	1339	fprintf(stderr," ");
1318	1340	#endif
1319	1341	update_fifo_status_and_ints();
1320		if (!m_~~talk~~_~~stat~~us) goto ranout;
	1342	if (m_DDIS && m_buffer_empty) goto ranout;
1321	1343	// if the energy index is 0 or 15, we're done
1322	1344	if ((m_new_frame_energy_idx == 0) \|\| (m_new_frame_energy_idx == 15))
1323	1345	return;
r249025	r249026
1337	1359	fprintf(stderr," ");
1338	1360	#endif
1339	1361	update_fifo_status_and_ints();
1340		if (!m_~~talk~~_~~stat~~us) goto ranout;
	1362	if (m_DDIS && m_buffer_empty) goto ranout;
1341	1363	// if this is a repeat frame, just do nothing, it will reuse the old coefficients
1342	1364	if (rep_flag)
1343	1365	return;
r249025	r249026
1351	1373	fprintf(stderr," ");
1352	1374	#endif
1353	1375	update_fifo_status_and_ints();
1354		if (!m_~~talk~~_~~stat~~us) goto ranout;
	1376	if (m_DDIS && m_buffer_empty) goto ranout;
1355	1377	}
1356	1378
1357	1379	// if the pitch index was zero, we only need 4 K's...
r249025	r249026
1370	1392	fprintf(stderr," ");
1371	1393	#endif
1372	1394	update_fifo_status_and_ints();
1373		if (!m_~~talk~~_~~stat~~us) goto ranout;
	1395	if (m_DDIS && m_buffer_empty) goto ranout;
1374	1396	}
	1397	#ifdef DEBUG_PARSE_FRAME_DUMP
	1398	fprintf(stderr,"\n");
	1399	#endif
1375	1400	#ifdef VERBOSE
1376		if (m_speak_external)
1377		logerror("Parsed a frame successfully in FIFO - %d bits remaining\n", (m_fifo_count*8)-(m_fifo_bits_taken));
	1401	if (m_DDIS)
	1402	fprintf(stderr,"Parsed a frame successfully in FIFO - %d bits remaining\n", (m_fifo_count*8)-(m_fifo_bits_taken));
1378	1403	else
1379		~~log~~err~~or(~~"Parsed a frame successfully in ROM\n");
	1404	fprintf(stderr,"Parsed a frame successfully in ROM\n");
1380	1405	#endif
1381	1406	return;
1382	1407
1383	1408	ranout:
1384	1409	#ifdef DEBUG_FRAME_ERRORS
1385		~~log~~err~~or(~~"Ran out of bits on a parse!\n");
	1410	fprintf(stderr,"Ran out of bits on a parse!\n");
1386	1411	#endif
1387	1412	return;
1388	1413	}
r249025	r249026
1397	1422	{
1398	1423	if (!TMS5220_IS_52xx) return; // bail out if not a 52xx chip, since there's no int pin
1399	1424	#ifdef DEBUG_PIN_READS
1400		~~log~~err~~or(~~"irq pin set to state %d\n", state);
	1425	fprintf(stderr,"irq pin set to state %d\n", state);
1401	1426	#endif
1402	1427	if (!m_irq_handler.isnull() && state != m_irq_pin)
1403	1428	m_irq_handler(!state);
r249025	r249026
1414	1439	{
1415	1440	int state = ready_read();
1416	1441	#ifdef DEBUG_PIN_READS
1417		~~log~~err~~or(~~"ready pin set to state %d\n", state);
	1442	fprintf(stderr,"ready pin set to state %d\n", state);
1418	1443	#endif
1419	1444	if (!m_readyq_handler.isnull() && state != m_ready_pin)
1420	1445	m_readyq_handler(!state);
r249025	r249026
1514	1539
1515	1540	/* initialize the chip state */
1516	1541	/* Note that we do not actually clear IRQ on start-up : IRQ is even raised if m_buffer_empty or m_buffer_low are 0 */
1517		m_~~speaking~~_~~now~~ = m_~~speak~~_~~external~~ = m_~~talk_stat~~us = m_irq_pin = m_ready_pin = 0;
	1542	m_SPEN = m_DDIS = m_TALK = m_TALKD = m_previous_TALK_STATUS = m_irq_pin = m_ready_pin = 0;
1518	1543	set_interrupt_state(0);
1519	1544	update_ready_state();
1520	1545	m_buffer_empty = m_buffer_low = 1;
r249025	r249026
1525	1550	#ifdef PERFECT_INTERPOLATION_HACK
1526	1551	m_old_frame_energy_idx = m_old_frame_pitch_idx = 0;
1527	1552	memset(m_old_frame_k_idx, 0, sizeof(m_old_frame_k_idx));
	1553	m_old_zpar = 0;
1528	1554	#endif
1529		m_new_frame_energy_idx = m_current_energy = m_target_energy = m_previous_energy = 0;
1530		m_new_frame_pitch_idx = m_current_pitch = m_target_pitch = 0;
	1555	m_new_frame_energy_idx = m_current_energy = m_previous_energy = 0;
	1556	m_new_frame_pitch_idx = m_current_pitch = 0;
	1557	m_zpar = m_uv_zpar = 0;
1531	1558	memset(m_new_frame_k_idx, 0, sizeof(m_new_frame_k_idx));
1532	1559	memset(m_current_k, 0, sizeof(m_current_k));
1533		memset(m_target_k, 0, sizeof(m_target_k));
1534	1560
1535	1561	/* initialize the sample generators */
1536	1562	m_inhibit = 1;
r249025	r249026
1574	1600	/* Write */
1575	1601	/* bring up to date first */
1576	1602	#ifdef DEBUG_IO_READY
1577		~~log~~err~~or(~~"Serviced write: %02x\n", m_write_latch);
	1603	fprintf(stderr,"Serviced write: %02x\n", m_write_latch);
1578	1604	//fprintf(stderr, "Processed write data: %02X\n", m_write_latch);
1579	1605	#endif
1580	1606	m_stream->update();
r249025	r249026
1610	1636	m_true_timing = 1;
1611	1637	state &= 0x01;
1612	1638	#ifdef DEBUG_RS_WS
1613		~~log~~err~~or(~~"/RS written with data: %d\n", state);
	1639	fprintf(stderr,"/RS written with data: %d\n", state);
1614	1640	#endif
1615	1641	new_val = (m_rs_ws & 0x01) \| (state<<1);
1616	1642	if (new_val != m_rs_ws)
r249025	r249026
1623	1649	#ifdef DEBUG_RS_WS
1624	1650	else
1625	1651	/* illegal */
1626		~~log~~err~~or(~~"tms5220_rs_w: illegal\n");
	1652	fprintf(stderr,"tms5220_rs_w: illegal\n");
1627	1653	#endif
1628	1654	return;
1629	1655	}
r249025	r249026
1641	1667	{
1642	1668	/* high to low - schedule ready cycle */
1643	1669	#ifdef DEBUG_RS_WS
1644		~~log~~err~~or(~~"Scheduling ready cycle for /RS...\n");
	1670	fprintf(stderr,"Scheduling ready cycle for /RS...\n");
1645	1671	#endif
1646	1672	/* upon /RS being activated, /READY goes inactive after 100 nsec from data sheet, through 3 asynchronous gates on patent. This is effectively within one clock, so we immediately set io_ready to 0 and activate the callback. */
1647	1673	m_io_ready = 0;
r249025	r249026
1662	1688	m_true_timing = 1;
1663	1689	state &= 0x01;
1664	1690	#ifdef DEBUG_RS_WS
1665		~~log~~err~~or(~~"/WS written with data: %d\n", state);
	1691	fprintf(stderr,"/WS written with data: %d\n", state);
1666	1692	#endif
1667	1693	new_val = (m_rs_ws & 0x02) \| (state<<0);
1668	1694	if (new_val != m_rs_ws)
r249025	r249026
1675	1701	#ifdef DEBUG_RS_WS
1676	1702	else
1677	1703	/* illegal */
1678		~~log~~err~~or(~~"tms5220_ws_w: illegal\n");
	1704	fprintf(stderr,"tms5220_ws_w: illegal\n");
1679	1705	#endif
1680	1706	return;
1681	1707	}
r249025	r249026
1693	1719	{
1694	1720	/* high to low - schedule ready cycle */
1695	1721	#ifdef DEBUG_RS_WS
1696		~~log~~err~~or(~~"Scheduling ready cycle for /WS...\n");
	1722	fprintf(stderr,"Scheduling ready cycle for /WS...\n");
1697	1723	#endif
1698	1724	/* upon /WS being activated, /READY goes inactive after 100 nsec from data sheet, through 3 asynchronous gates on patent. This is effectively within one clock, so we immediately set io_ready to 0 and activate the callback. */
1699	1725	m_io_ready = 0;
r249025	r249026
1726	1752	if (space.debugger_access()) return;
1727	1753
1728	1754	#ifdef DEBUG_RS_WS
1729		~~log~~err~~or(~~"tms5220_data_w: data %02x\n", data);
	1755	fprintf(stderr,"tms5220_data_w: data %02x\n", data);
1730	1756	#endif
1731	1757	if (!m_true_timing)
1732	1758	{
r249025	r249026
1739	1765	/* actually in a write ? */
1740	1766	#ifdef DEBUG_RS_WS
1741	1767	if (!(m_rs_ws == 0x02))
1742		~~log~~err~~or(~~"tms5220_data_w: data written outside ws, status: %02x!\n", m_rs_ws);
	1768	fprintf(stderr,"tms5220_data_w: data written outside ws, status: %02x!\n", m_rs_ws);
1743	1769	#endif
1744	1770	m_write_latch = data;
1745	1771	}
r249025	r249026
1771	1797	return m_read_latch;
1772	1798	#ifdef DEBUG_RS_WS
1773	1799	else
1774		~~log~~err~~or(~~"tms5220_status_r: data read outside rs!\n");
	1800	fprintf(stderr,"tms5220_status_r: data read outside rs!\n");
1775	1801	#endif
1776	1802	return 0xff;
1777	1803	}

trunk/src/emu/sound/tms5220.h
r249025	r249026
105	105
106	106
107	107	/* these contain global status bits */
108		UINT8 m_speaking_now; /* True only if actual speech is being generated right now. Is set when a speak vsm command happens OR when speak external happens and buffer low becomes nontrue; Is cleared when speech halts after the last stop frame or the last frame after talk status is otherwise cleared.*/
109		UINT8 m_speak_external; /* If 1, DDIS is 1, i.e. Speak External command in progress, writes go to FIFO. */
110		UINT8 m_talk_status; /* If 1, TS status bit is 1, i.e. speak or speak external is in progress and we have not encountered a stop frame yet; talk_status differs from speaking_now in that speaking_now is set as soon as a speak or speak external command is started; talk_status does NOT go active until after 8 bytes are written to the fifo on a speak external command, otherwise the two are the same. TS is cleared by 3 things: 1. when a STOP command has just been processed as a new frame in the speech stream; 2. if the fifo runs out in speak external mode; 3. on power-up/during a reset command; When it gets cleared, speak_external is also cleared, an interrupt is generated, and speaking_now will be cleared when the next frame starts. */
	108	UINT8 m_previous_TALK_STATUS; /* this is the OLD value of TALK_STATUS (i.e. previous value of m_SPEN\|m_TALKD), needed for generating interrupts on a falling TALK_STATUS edge */
	109	UINT8 m_SPEN; /* set on speak(or speak external and BL falling edge) command, cleared on stop command, reset command, or buffer out */
	110	UINT8 m_DDIS; /* If 1, DDIS is 1, i.e. Speak External command in progress, writes go to FIFO. */
	111	UINT8 m_TALK; /* set on SPEN & RESETL4(pc12->pc0 transition), cleared on stop command or reset command */
	112	#define TALK_STATUS (m_SPEN\|m_TALKD)
	113	UINT8 m_TALKD; /* TALK(TCON) value, latched every RESETL4 */
111	114	UINT8 m_buffer_low; /* If 1, FIFO has less than 8 bytes in it */
112	115	UINT8 m_buffer_empty; /* If 1, FIFO is empty */
113	116	UINT8 m_irq_pin; /* state of the IRQ pin (output) */
r249025	r249026
132	135	INT16 m_current_energy;
133	136	INT16 m_current_pitch;
134	137	INT16 m_current_k[10];
135
136		INT16 m_target_energy;
137		INT16 m_target_pitch;
138		INT16 m_target_k[10];
139	138	#else
140	139	UINT8 m_old_frame_energy_idx;
141	140	UINT8 m_old_frame_pitch_idx;
142	141	UINT8 m_old_frame_k_idx[10];
	142	UINT8 m_old_zpar;
	143	UINT8 m_old_uv_zpar;
143	144
144	145	INT32 m_current_energy;
145	146	INT32 m_current_pitch;
146	147	INT32 m_current_k[10];
147
148		INT32 m_target_energy;
149		INT32 m_target_pitch;
150		INT32 m_target_k[10];
151	148	#endif
152	149
153	150	UINT16 m_previous_energy; /* needed for lattice filter to match patent */
r249025	r249026
155	152	UINT8 m_subcycle; /* contains the current subcycle for a given PC: 0 is A' (only used on SPKSLOW mode on 51xx), 1 is A, 2 is B */
156	153	UINT8 m_subc_reload; /* contains 1 for normal speech, 0 when SPKSLOW is active */
157	154	UINT8 m_PC; /* current parameter counter (what param is being interpolated), ranges from 0 to 12 */
158		/* ~~TODO/~~NOTE: the ~~current~~ interpolation period, counts 1,2,3,4,5,6,7,0 for divide by 8,8,8,4,4,2,2,1 */
	155	/* NOTE: the interpolation period counts 1,2,3,4,5,6,7,0 for divide by 8,8,8,4,4,2,2,1 */
159	156	UINT8 m_IP; /* the current interpolation period */
160	157	UINT8 m_inhibit; /* If 1, interpolation is inhibited until the DIV1 period */
	158	UINT8 m_uv_zpar; /* If 1, zero k5 thru k10 coefficients */
	159	UINT8 m_zpar; /* If 1, zero ALL parameters. */
	160	UINT8 m_pitch_zero; /* circuit 412; pitch is forced to zero under certain circumstances */
161	161	UINT8 m_c_variant_rate; /* only relevant for tms5220C's multi frame rate feature; is the actual 4 bit value written on a 0x2* or 0x0* command */
162	162	UINT16 m_pitch_count; /* pitch counter; provides chirp rom address */
163	163
164	164	INT32 m_u[11];
165	165	INT32 m_x[10];
166	166
167		UINT16 m_RNG; /* the random noise generator configuration is: 1 + x + x^3 + x^4 + x^13 */
	167	UINT16 m_RNG; /* the random noise generator configuration is: 1 + x + x^3 + x^4 + x^13 TODO: no it isn't */
168	168	INT16 m_excitation_data;
169	169
170	170	/* R Nabet : These have been added to emulate speech Roms */

trunk/src/mame/arcade.lst
r249025	r249026
336	336	mimonkey // (c) 1982 Universal Video Games (US Copyright Office info - http://cocatalog.loc.gov)
337	337	mimonsco // (c) 1982 bootleg
338	338	mimonscr // (c) 1982 bootleg
339		mimonscra // (c) 1982 bootleg
	339	mimonscra // (c) 1982 bootleg
340	340	scobra // GX316 (c) 1981 Konami
341	341	scobras // GX316 (c) 1981 Stern
342	342	scobrase // GX316 (c) 1981 Sega
r249025	r249026
3040	3040	avengers // 2/1987 (c) 1987 (US)
3041	3041	avengers2 // 2/1987 (c) 1987 (US)
3042	3042	buraiken // 2/1987 (c) 1987 (Japan)
3043		buraikenb // 2/1987 (c) 1987 (Japan)
	3043	buraikenb // 2/1987 (c) 1987 (Japan)
3044	3044	bionicc // 3/1987 (c) 1987 (Euro)
3045	3045	bionicc1 // 3/1987 (c) 1987 (US)
3046	3046	bionicc2 // 3/1987 (c) 1987 (US)
r249025	r249026
3514	3514	sfa3 // 04/09/1998 (c) 1998 (USA)
3515	3515	sfa3u // 04/09/1998 (c) 1998 (USA)
3516	3516	sfa3ur1 // 29/06/1998 (c) 1998 (USA)
3517		sfa3us // 16/06/1998 (c) 1998 (USA)
	3517	sfa3us // 16/06/1998 (c) 1998 (USA)
3518	3518	sfa3h // 04/09/1998 (c) 1998 (Hispanic)
3519	3519	sfa3hr1 // 29/06/1998 (c) 1998 (Hispanic)
3520	3520	sfa3b // 29/06/1998 (c) 1998 (Brazil)
r249025	r249026
3845	3845	soulclbrub // 1998.?? Soul Calibur (US, SOC13/VER.B)
3846	3846	soulclbrjb // 1998.?? Soul Calibur (Japan, SOC11/VER.B)
3847	3847	soulclbrja // 1998.?? Soul Calibur (Japan, SOC11/VER.A2)
3848		technodr // 1998.07 Techno Drive
	3848	technodr // 1998.07 Techno Drive
3849	3849	mdhorse // 1998.11 Derby Quiz My Dream Horse (Japan, MDH1/VER.A2)
3850	3850	// 1998.12 Attack Pla Rail
3851	3851	tenkomor // 1998.?? Tenkomori Shooting (Asia, TKM2/VER.A1)
r249025	r249026
8220	8220	nbajamte3 // (c) 1994 Midway
8221	8221	nbajamten // (c) 1995 Midway
8222	8222	revx // (c) 1994 Midway
	8223	revxp5 // (c) 1994 Midway
8223	8224	mk3 // (c) 1994 Midway
8224	8225	mk3r20 // (c) 1994 Midway
8225	8226	mk3r10 // (c) 1994 Midway
r249025	r249026
9535	9536	spcforce // (c) 1980 Venture Line
9536	9537	spcforc2 // bootleg
9537	9538	meteor // (c) 1981 Venture Line
9538		meteors // (c) 1981 Amusement World
	9539	meteors // (c) 1981 Amusement World
9539	9540	looping // (c) 1982 Video Games GmbH
9540	9541	loopingv // (c) 1982 Video Games GmbH (Venture Line license)
9541	9542	loopingva // (c) 1982 Video Games GmbH (Venture Line license)
r249025	r249026
32184	32185	alinvade
32185	32186
32186	32187	joystand // 1997 Yuvo
32187		faceoffh // 1993 SoftLogic / Entertainment Enterprises
	32188	chexx83 // 1983 ICE
	32189	faceoffh // 1983 SoftLogic / Entertainment Enterprises

trunk/src/mame/audio/targ.c
r249025	r249026
36	36	void exidy_state::adjust_sample(UINT8 freq)
37	37	{
38	38	m_tone_freq = freq;
39
	39
40	40	if (!m_samples->playing(3))
41	41	{
42	42	m_samples->set_volume(3, 0);
43	43	m_samples->start_raw(3, sine_wave, 32, 1000, true);
44	44	}
45
	45
46	46	if ((m_tone_freq == 0xff) \|\| (m_tone_freq == 0x00))
47	47	m_samples->set_volume(3, 0);
48	48	else

trunk/src/mame/drivers/ajax.c
r249025	r249026
182	182	MCFG_SCREEN_ADD("screen", RASTER)
183	183	MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/3, 528, 112, 400, 256, 16, 240)
184	184	// 6MHz dotclock is more realistic, however needs drawing updates. replace when ready
185		// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
	185	// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
186	186	MCFG_SCREEN_UPDATE_DRIVER(ajax_state, screen_update_ajax)
187	187	MCFG_SCREEN_PALETTE("palette")
188	188

trunk/src/mame/drivers/aliens.c
r249025	r249026
209	209	MCFG_SCREEN_ADD("screen", RASTER)
210	210	MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/3, 528, 112, 400, 256, 16, 240) // measured 59.17
211	211	// 6MHz dotclock is more realistic, however needs drawing updates. replace when ready
212		// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
	212	// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
213	213	MCFG_SCREEN_UPDATE_DRIVER(aliens_state, screen_update_aliens)
214	214	MCFG_SCREEN_PALETTE("palette")
215	215

trunk/src/mame/drivers/blockhl.c
r249025	r249026
7	7	Original driver by Nicola Salmoria
8	8
9	9	Notes:
10		- To advance to the next screen in service mode, press P1 and P2 start
11		simultaneously
	10	- To advance to the next screen in service mode, press P1 and P2 start
	11	simultaneously
12	12
13		Todo:
14		- How is the sound irq cleared (currently using HOLD_LINE)?
15		- Do bit 2 and 7 of the bankswitch port have any meaning?
16		- Verify raw screen parameters
	13	Todo:
	14	- How is the sound irq cleared (currently using HOLD_LINE)?
	15	- Do bit 2 and 7 of the bankswitch port have any meaning?
	16	- Verify raw screen parameters
17	17
18	18	*******************************************************************************/
19	19
r249025	r249026
285	285	MCFG_SCREEN_ADD("screen", RASTER)
286	286	MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/3, 528, 112, 400, 256, 16, 240)
287	287	// 6MHz dotclock is more realistic, however needs drawing updates. replace when ready
288		// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
	288	// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
289	289	MCFG_SCREEN_UPDATE_DRIVER(blockhl_state, screen_update_blockhl)
290	290	MCFG_SCREEN_PALETTE("palette")
291	291
r249025	r249026
318	318	//**************************************************************************
319	319
320	320	ROM_START( blockhl )
321		ROM_REGION( 0x10000, "maincpu", 0 ) // code + banked roms
	321	ROM_REGION( 0x10000, "maincpu", 0 ) // code + banked roms
322	322	ROM_LOAD( "973l02.e21", 0x00000, 0x10000, CRC(e14f849a) SHA1(d44cf178cc98998b72ed32c6e20b6ebdf1f97579) )
323	323
324		ROM_REGION( 0x08000, "audiocpu", 0 ) // 32k for the sound CPU
	324	ROM_REGION( 0x08000, "audiocpu", 0 ) // 32k for the sound CPU
325	325	ROM_LOAD( "973d01.g6", 0x00000, 0x08000, CRC(eeee9d92) SHA1(6c6c324b1f6f4fba0aa12e0d1fc5dbab133ef669) )
326	326
327		ROM_REGION( 0x20000, "k052109", 0 ) // tiles
	327	ROM_REGION( 0x20000, "k052109", 0 ) // tiles
328	328	ROM_LOAD32_BYTE( "973f07.k15", 0x00000, 0x08000, CRC(1a8cd9b4) SHA1(7cb7944d24ac51fa6b610542d9dec68697cacf0f) )
329	329	ROM_LOAD32_BYTE( "973f08.k18", 0x00001, 0x08000, CRC(952b51a6) SHA1(017575738d444b688b137cad5611638d53be84f2) )
330	330	ROM_LOAD32_BYTE( "973f09.k20", 0x00002, 0x08000, CRC(77841594) SHA1(e1bfdc5bb598d865868d578ef7faba8078becd7a) )
331	331	ROM_LOAD32_BYTE( "973f10.k23", 0x00003, 0x08000, CRC(09039fab) SHA1(a9dea17aacf4484d21ef3b16470263447b51b6b5) )
332	332
333		ROM_REGION( 0x20000, "k051960", 0 ) // sprites
	333	ROM_REGION( 0x20000, "k051960", 0 ) // sprites
334	334	ROM_LOAD32_BYTE( "973f06.k12", 0x00000, 0x08000, CRC(51acfdb6) SHA1(94d243f341b490684f5297d95d4835bd522ece35) )
335	335	ROM_LOAD32_BYTE( "973f05.k9", 0x00001, 0x08000, CRC(4cfea298) SHA1(4772b5b99f5fd8174d8884bd84173512e1edabf4) )
336	336	ROM_LOAD32_BYTE( "973f04.k7", 0x00002, 0x08000, CRC(69ca41bd) SHA1(9b0b1c888efd2f2d5525f14778e18fb4a7353eb6) )
337	337	ROM_LOAD32_BYTE( "973f03.k4", 0x00003, 0x08000, CRC(21e98472) SHA1(8c697d369a1f57be0825c33b4e9107ce1b02a130) )
338	338
339		ROM_REGION( 0x0100, "priority", 0 ) // priority encoder (not used)
	339	ROM_REGION( 0x0100, "priority", 0 ) // priority encoder (not used)
340	340	ROM_LOAD( "973a11.h10", 0x0000, 0x0100, CRC(46d28fe9) SHA1(9d0811a928c8907785ef483bfbee5445506b3ec8) )
341	341	ROM_END
342	342
343	343	ROM_START( quarth )
344		ROM_REGION( 0x10000, "maincpu", 0 ) // code + banked roms
	344	ROM_REGION( 0x10000, "maincpu", 0 ) // code + banked roms
345	345	ROM_LOAD( "973j02.e21", 0x00000, 0x10000, CRC(27a90118) SHA1(51309385b93db29b9277d14252166c4ea1746303) )
346	346
347		ROM_REGION( 0x08000, "audiocpu", 0 ) // 32k for the sound CPU
	347	ROM_REGION( 0x08000, "audiocpu", 0 ) // 32k for the sound CPU
348	348	ROM_LOAD( "973d01.g6", 0x00000, 0x08000, CRC(eeee9d92) SHA1(6c6c324b1f6f4fba0aa12e0d1fc5dbab133ef669) )
349	349
350		ROM_REGION( 0x20000, "k052109", 0 ) // tiles
	350	ROM_REGION( 0x20000, "k052109", 0 ) // tiles
351	351	ROM_LOAD32_BYTE( "973e07.k15", 0x00000, 0x08000, CRC(0bd6b0f8) SHA1(6c59cf637354fe2df424eaa89feb9c1bc1f66a92) )
352	352	ROM_LOAD32_BYTE( "973e08.k18", 0x00001, 0x08000, CRC(104d0d5f) SHA1(595698911513113d01e5b565f5b073d1bd033d3f) )
353	353	ROM_LOAD32_BYTE( "973e09.k20", 0x00002, 0x08000, CRC(bd3a6f24) SHA1(eb45db3a6a52bb2b25df8c2dace877e59b4130a6) )
354	354	ROM_LOAD32_BYTE( "973e10.k23", 0x00003, 0x08000, CRC(cf5e4b86) SHA1(43348753894c1763b26dbfc70245dac92048db8f) )
355	355
356		ROM_REGION( 0x20000, "k051960", 0 ) // sprites
	356	ROM_REGION( 0x20000, "k051960", 0 ) // sprites
357	357	ROM_LOAD32_BYTE( "973e06.k12", 0x00000, 0x08000, CRC(0d58af85) SHA1(2efd661d614fb305a14cfe1aa4fb17714f215d4f) )
358	358	ROM_LOAD32_BYTE( "973e05.k9", 0x00001, 0x08000, CRC(15d822cb) SHA1(70ecad5e0a461df0da6e6eb23f43a7b643297f0d) )
359	359	ROM_LOAD32_BYTE( "973e04.k7", 0x00002, 0x08000, CRC(d70f4a2c) SHA1(25f835a17bacf2b8debb2eb8a3cff90cab3f402a) )
360	360	ROM_LOAD32_BYTE( "973e03.k4", 0x00003, 0x08000, CRC(2c5a4b4b) SHA1(e2991dd78b9cd96cf93ebd6de0d4e060d346ab9c) )
361	361
362		ROM_REGION( 0x0100, "priority", 0 ) // priority encoder (not used)
	362	ROM_REGION( 0x0100, "priority", 0 ) // priority encoder (not used)
363	363	ROM_LOAD( "973a11.h10", 0x0000, 0x0100, CRC(46d28fe9) SHA1(9d0811a928c8907785ef483bfbee5445506b3ec8) )
364	364	ROM_END
365	365

trunk/src/mame/drivers/chexx.c
r0	r249026
	1	// license:BSD-3-Clause
	2	// copyright-holders:Luca Elia
	3	/***************************************************************************
	4
	5	Electro-mechanical bubble hockey games:
	6
	7	- Chexx (1983 version) by ICE
	8	http://www.pinrepair.com/arcade/chexx.htm
	9
	10	- Face-Off, an illegal? copy of Chexx
	11	http://valker.us/gameroom/SegaFaceOff.htm
	12	https://casetext.com/case/innovative-concepts-in-ent-v-entertainment-enter
	13
	14	(Some sources indicate these may have been copied from a earlier Sega game called Face-Off)
	15
	16	***************************************************************************/
	17
	18	#include "emu.h"
	19	#include "cpu/m6502/m6502.h"
	20	#include "sound/ay8910.h"
	21	#include "sound/digitalk.h"
	22	#include "machine/6522via.h"
	23	#include "chexx.lh"
	24
	25	#define MAIN_CLOCK XTAL_4MHz
	26
	27	class chexx_state : public driver_device
	28	{
	29	public:
	30	chexx_state(const machine_config &mconfig, device_type type, const char *tag)
	31	: driver_device(mconfig, type, tag),
	32	m_maincpu(*this, "maincpu"),
	33	m_via(*this, "via6522"),
	34	m_digitalker(*this, "digitalker"),
	35	m_aysnd(*this, "aysnd")
	36	{
	37	}
	38
	39	// devices
	40	required_device<cpu_device> m_maincpu;
	41	required_device<via6522_device> m_via;
	42	required_device<digitalker_device> m_digitalker;
	43	optional_device<ay8910_device> m_aysnd; // only faceoffh
	44
	45	// vars
	46	UINT8 m_port_a, m_port_b;
	47	UINT8 m_bank;
	48	UINT32 m_shift;
	49	UINT8 m_lamp;
	50	UINT8 m_ay_cmd, m_ay_data;
	51
	52	// callbacks
	53	TIMER_DEVICE_CALLBACK_MEMBER(update);
	54
	55	// handlers
	56	DECLARE_READ8_MEMBER(via_a_in);
	57	DECLARE_READ8_MEMBER(via_b_in);
	58
	59	DECLARE_WRITE8_MEMBER(via_a_out);
	60	DECLARE_WRITE8_MEMBER(via_b_out);
	61
	62	DECLARE_WRITE_LINE_MEMBER(via_ca2_out);
	63	DECLARE_WRITE_LINE_MEMBER(via_cb1_out);
	64	DECLARE_WRITE_LINE_MEMBER(via_cb2_out);
	65	DECLARE_WRITE_LINE_MEMBER(via_irq_out);
	66
	67	DECLARE_READ8_MEMBER(input_r);
	68
	69	DECLARE_WRITE8_MEMBER(ay_w);
	70	DECLARE_WRITE8_MEMBER(lamp_w);
	71
	72	// digitalker
	73	void digitalker_set_bank(UINT8 bank);
	74
	75	// driver_device overrides
	76	virtual void machine_start();
	77	virtual void machine_reset();
	78	};
	79
	80
	81	// VIA
	82
	83	READ8_MEMBER(chexx_state::via_a_in)
	84	{
	85	UINT8 ret = 0;
	86	logerror("%s: VIA read A: %02X\n", machine().describe_context(), ret);
	87	return ret;
	88	}
	89	READ8_MEMBER(chexx_state::via_b_in)
	90	{
	91	UINT8 ret = 0;
	92	logerror("%s: VIA read B: %02X\n", machine().describe_context(), ret);
	93	return ret;
	94	}
	95
	96	WRITE8_MEMBER(chexx_state::via_a_out)
	97	{
	98	m_port_a = data; // multiplexer
	99
	100	m_digitalker->digitalker_data_w(space, 0, data, 0);
	101
	102	// logerror("%s: VIA write A = %02X\n", machine().describe_context(), data);
	103	}
	104	WRITE8_MEMBER(chexx_state::via_b_out)
	105	{
	106	m_port_b = data;
	107
	108	digitalker_set_bank(data & 3);
	109	m_digitalker->set_output_gain(0, BIT(data,2) ? 1.0f : 0.0f); // bit 2 controls the Digitalker output
	110	coin_counter_w(machine(), 0, BIT(~data,3));
	111	// bit 4 is EJECT
	112	// bit 7 is related to speaker out
	113
	114	// logerror("%s: VIA write B = %02X\n", machine().describe_context(), data);
	115	}
	116
	117	WRITE_LINE_MEMBER(chexx_state::via_ca2_out)
	118	{
	119	m_digitalker->digitalker_0_cms_w(CLEAR_LINE);
	120	m_digitalker->digitalker_0_cs_w(CLEAR_LINE);
	121	m_digitalker->digitalker_0_wr_w(state ? ASSERT_LINE : CLEAR_LINE);
	122
	123	// logerror("%s: VIA write CA2 = %02X\n", machine().describe_context(), state);
	124	}
	125	WRITE_LINE_MEMBER(chexx_state::via_cb1_out)
	126	{
	127	// logerror("%s: VIA write CB1 = %02X\n", machine().describe_context(), state);
	128	}
	129	WRITE_LINE_MEMBER(chexx_state::via_cb2_out)
	130	{
	131	m_shift = ((m_shift << 1) & 0xffffff) \| state;
	132
	133	// 7segs (score)
	134	static const UINT8 patterns[16] = { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7c, 0x07, 0x7f, 0x67, 0, 0, 0, 0, 0, 0 }; // 4511
	135
	136	output_set_digit_value(0, patterns[(m_shift >> (16+4)) & 0xf]);
	137	output_set_digit_value(1, patterns[(m_shift >> (16+0)) & 0xf]);
	138
	139	output_set_digit_value(2, patterns[(m_shift >> (8+4)) & 0xf]);
	140	output_set_digit_value(3, patterns[(m_shift >> (8+0)) & 0xf]);
	141
	142	// Leds (period being played)
	143	output_set_led_value(0, BIT(m_shift,2));
	144	output_set_led_value(1, BIT(m_shift,1));
	145	output_set_led_value(2, BIT(m_shift,0));
	146
	147	// logerror("%s: VIA write CB2 = %02X\n", machine().describe_context(), state);
	148	}
	149	WRITE_LINE_MEMBER(chexx_state::via_irq_out)
	150	{
	151	m_maincpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
	152	// logerror("%s: VIA write IRQ = %02X\n", machine().describe_context(), state);
	153	}
	154
	155	READ8_MEMBER(chexx_state::input_r)
	156	{
	157	UINT8 ret = ioport("DSW")->read(); // bits 0-3
	158	UINT8 inp = ioport("INPUT")->read(); // bit 7 (multiplexed)
	159
	160	for (int i = 0; i < 8; ++i)
	161	if ( ((~m_port_a) & (1 << i)) && ((~inp) & (1 << i)) )
	162	ret &= 0x7f;
	163
	164	return ret;
	165	}
	166
	167	// Chexx Memory Map
	168
	169	static ADDRESS_MAP_START( chexx83_map, AS_PROGRAM, 8, chexx_state )
	170	AM_RANGE(0x0000, 0x007f) AM_RAM AM_MIRROR(0x100) // 6810 - 128 x 8 static RAM
	171	AM_RANGE(0x4000, 0x400f) AM_DEVREADWRITE("via6522", via6522_device, read, write)
	172	AM_RANGE(0x8000, 0x8000) AM_READ(input_r)
	173	AM_RANGE(0xf800, 0xffff) AM_ROM AM_REGION("maincpu", 0)
	174	ADDRESS_MAP_END
	175
	176	// Face-Off Memory Map
	177
	178	WRITE8_MEMBER(chexx_state::lamp_w)
	179	{
	180	m_lamp = data;
	181	output_set_lamp_value(0, BIT(m_lamp,0));
	182	output_set_lamp_value(1, BIT(m_lamp,1));
	183	}
	184
	185	WRITE8_MEMBER(chexx_state::ay_w)
	186	{
	187	if (offset)
	188	{
	189	m_ay_data = data;
	190	return;
	191	}
	192
	193	if (m_ay_cmd == 0x00 && data == 0x03)
	194	{
	195	m_aysnd->address_w(space, offset, m_ay_data, mem_mask);
	196	// logerror("%s: AY addr = %02X\n", machine().describe_context(), m_ay_data);
	197	}
	198	else if (m_ay_cmd == 0x00 && data == 0x02)
	199	{
	200	m_aysnd->data_w(space, offset, m_ay_data, mem_mask);
	201	// logerror("%s: AY data = %02X\n", machine().describe_context(), m_ay_data);
	202	}
	203	m_ay_cmd = data;
	204	}
	205
	206	static ADDRESS_MAP_START( faceoffh_map, AS_PROGRAM, 8, chexx_state )
	207	AM_RANGE(0x0000, 0x007f) AM_RAM AM_MIRROR(0x100) // M58725P - 2KB
	208	AM_RANGE(0x4000, 0x400f) AM_DEVREADWRITE("via6522", via6522_device, read, write)
	209	AM_RANGE(0x8000, 0x8000) AM_READ(input_r)
	210	AM_RANGE(0xa000, 0xa001) AM_WRITE(ay_w)
	211	AM_RANGE(0xc000, 0xc000) AM_WRITE(lamp_w)
	212	AM_RANGE(0xf000, 0xffff) AM_ROM AM_REGION("maincpu", 0)
	213	ADDRESS_MAP_END
	214
	215	// Inputs
	216
	217	static INPUT_PORTS_START( chexx83 )
	218	PORT_START("COIN")
	219	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1) // play anthem
	220	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(1) // play anthem
	221
	222	PORT_START("INPUT")
	223	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("P1 Goal Sensor")
	224	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("P2 Goal Sensor")
	225	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 ) PORT_NAME("Puck Near Goal Sensors") // play "ohh" sample
	226	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P1 Boo Button") // stop anthem, play "boo" sample, eject puck
	227	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("P2 Boo Button") // stop anthem, play "boo" sample, eject puck
	228	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Puck Eject Ready Sensor")
	229	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
	230	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
	231
	232	PORT_START("DSW")
	233	PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
	234	PORT_DIPSETTING( 0x03, DEF_STR( 4C_1C ) )
	235	PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
	236	PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
	237	PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
	238	PORT_DIPNAME( 0x0c, 0x00, "Game Duration (mins)" ) PORT_DIPLOCATION("SW1:3,4")
	239	PORT_DIPSETTING( 0x00, "2" ) // 40
	240	PORT_DIPSETTING( 0x04, "3" ) // 60
	241	PORT_DIPSETTING( 0x08, "4" ) // 80
	242	PORT_DIPSETTING( 0x0c, "5" ) // 100
	243	PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
	244	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) // multiplexed inputs
	245	INPUT_PORTS_END
	246
	247	// Machine
	248
	249	void chexx_state::machine_start()
	250	{
	251	}
	252
	253	void chexx_state::digitalker_set_bank(UINT8 bank)
	254	{
	255	if (m_bank != bank)
	256	{
	257	UINT8 *src = memregion("samples")->base();
	258	UINT8 *dst = memregion("digitalker")->base();
	259
	260	memcpy(dst, src + bank * 0x4000, 0x4000);
	261
	262	m_bank = bank;
	263	}
	264	}
	265
	266	void chexx_state::machine_reset()
	267	{
	268	m_bank = -1;
	269	digitalker_set_bank(0);
	270	}
	271
	272	TIMER_DEVICE_CALLBACK_MEMBER(chexx_state::update)
	273	{
	274	// NMI on coin-in
	275	UINT8 coin = (~ioport("COIN")->read()) & 0x03;
	276	m_maincpu->set_input_line(INPUT_LINE_NMI, coin ? ASSERT_LINE : CLEAR_LINE);
	277
	278	// VIA CA1 connected to Digitalker INTR line
	279	m_via->write_ca1(m_digitalker->digitalker_0_intr_r());
	280
	281	#if 0
	282	// Play the digitalker samples (it's not hooked up correctly yet)
	283	static UINT8 sample = 0, bank = 0;
	284
	285	if (machine().input().code_pressed_once(KEYCODE_Q))
	286	--bank;
	287	if (machine().input().code_pressed_once(KEYCODE_W))
	288	++bank;
	289	bank %= 3;
	290	digitalker_set_bank(bank);
	291
	292	if (machine().input().code_pressed_once(KEYCODE_A))
	293	--sample;
	294	if (machine().input().code_pressed_once(KEYCODE_S))
	295	++sample;
	296
	297	if (machine().input().code_pressed_once(KEYCODE_Z))
	298	{
	299	m_digitalker->digitalker_0_cms_w(CLEAR_LINE);
	300	m_digitalker->digitalker_0_cs_w(CLEAR_LINE);
	301
	302	address_space &space = m_maincpu->space(AS_PROGRAM);
	303	m_digitalker->digitalker_data_w(space, 0, sample, 0);
	304
	305	m_digitalker->digitalker_0_wr_w(ASSERT_LINE);
	306	m_digitalker->digitalker_0_wr_w(CLEAR_LINE);
	307	m_digitalker->digitalker_0_wr_w(ASSERT_LINE);
	308	}
	309	#endif
	310	}
	311
	312	static MACHINE_CONFIG_START( chexx83, chexx_state )
	313
	314	// basic machine hardware
	315	MCFG_CPU_ADD("maincpu", M6502, MAIN_CLOCK/2)
	316	MCFG_CPU_PROGRAM_MAP(chexx83_map)
	317	MCFG_TIMER_DRIVER_ADD_PERIODIC("update", chexx_state, update, attotime::from_hz(60))
	318
	319	// via
	320	MCFG_DEVICE_ADD("via6522", VIA6522, MAIN_CLOCK/4)
	321
	322	MCFG_VIA6522_READPA_HANDLER(READ8(chexx_state, via_a_in))
	323	MCFG_VIA6522_READPB_HANDLER(READ8(chexx_state, via_b_in))
	324
	325	MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(chexx_state, via_a_out))
	326	MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(chexx_state, via_b_out))
	327
	328	MCFG_VIA6522_CA2_HANDLER(WRITELINE(chexx_state, via_ca2_out))
	329	MCFG_VIA6522_CB1_HANDLER(WRITELINE(chexx_state, via_cb1_out))
	330	MCFG_VIA6522_CB2_HANDLER(WRITELINE(chexx_state, via_cb2_out))
	331	MCFG_VIA6522_IRQ_HANDLER(WRITELINE(chexx_state, via_irq_out))
	332
	333	// Layout
	334	MCFG_DEFAULT_LAYOUT(layout_chexx)
	335
	336	// sound hardware
	337	MCFG_SPEAKER_STANDARD_MONO("mono")
	338	MCFG_DIGITALKER_ADD("digitalker", MAIN_CLOCK)
	339	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.16)
	340	MACHINE_CONFIG_END
	341
	342	static MACHINE_CONFIG_DERIVED( faceoffh, chexx83 )
	343	MCFG_CPU_MODIFY("maincpu")
	344	MCFG_CPU_PROGRAM_MAP(faceoffh_map)
	345
	346	MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/2)
	347	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
	348	MACHINE_CONFIG_END
	349
	350	// ROMs
	351
	352	/***************************************************************************
	353
	354	Chexx Hockey (1983 version 1.1)
	355
	356	The "long and skinny" Moog CPU board used a 6502 for the processor,
	357	a 6522 for the PIA, a 6810 static RAM, eight 52164 64k bit sound ROM chips,
	358	a 40 pin 54104 sound chip, and a single 2716 CPU EPROM
	359
	360	***************************************************************************/
	361
	362	ROM_START( chexx83 )
	363	ROM_REGION( 0x0800, "maincpu", 0 )
	364	ROM_LOAD( "chexx83.u4", 0x0000, 0x0800, CRC(a34abac1) SHA1(75a31670eb6d1b62ba984f0bac7c6e6067f6ae87) )
	365
	366	ROM_REGION( 0x4000, "digitalker", ROMREGION_ERASE00 )
	367	// bank switched (from samples region)
	368
	369	ROM_REGION( 0x10000, "samples", ROMREGION_ERASE00 )
	370	ROM_LOAD( "chexx83.u12", 0x0000, 0x2000, NO_DUMP )
	371	ROM_LOAD( "chexx83.u13", 0x2000, 0x2000, NO_DUMP )
	372	ROM_LOAD( "chexx83.u14", 0x4000, 0x2000, NO_DUMP )
	373	ROM_LOAD( "chexx83.u15", 0x6000, 0x2000, NO_DUMP )
	374	ROM_LOAD( "chexx83.u16", 0x8000, 0x2000, NO_DUMP )
	375	ROM_LOAD( "chexx83.u17", 0xa000, 0x2000, NO_DUMP )
	376	ROM_LOAD( "chexx83.u18", 0xc000, 0x2000, NO_DUMP )
	377	ROM_LOAD( "chexx83.u19", 0xe000, 0x2000, NO_DUMP )
	378	ROM_END
	379
	380	/***************************************************************************
	381
	382	Face-Off PCB?
	383
	384	Entertainment Enterprises Ltd. 1983 (sticker)
	385	Serial No. 025402 (sticker)
	386	MADE IN JAPAN (etched)
	387
	388	CPU: R6502P
	389	RAM: M58725P (2KB)
	390	I/O: R6522P (VIA)
	391	Samples: Digitalker (MM54104)
	392	Music: AY-3-8910
	393	Misc: XTAL 4MHz, DSW4, 42-pin connector
	394
	395	***************************************************************************/
	396
	397	ROM_START( faceoffh )
	398	ROM_REGION( 0x1000, "maincpu", 0 )
	399	// "Copyright (c) 1983 SoftLogic JAPAN"
	400	ROM_LOAD( "1.5d", 0x0000, 0x1000, CRC(6ab050be) SHA1(ebecae855e22e9c3c46bdee51f84fd5352bf191a) )
	401
	402	ROM_REGION( 0x4000, "digitalker", ROMREGION_ERASE00 )
	403	// bank switched (from samples region)
	404
	405	ROM_REGION( 0x10000, "samples", 0 )
	406	ROM_LOAD( "9.2a", 0x0000, 0x2000, CRC(059b3725) SHA1(5837bee1ef34ce19a3101b851ca55029776e4b3e) ) // digitalker header
	407	ROM_LOAD( "8.2b", 0x2000, 0x2000, CRC(679da4e1) SHA1(01a5b9dd132c1b0de97c153d7de226f5bf357338) )
	408
	409	ROM_LOAD( "7.2c", 0x4000, 0x2000, CRC(f8461b33) SHA1(717a8842e0ce9ba94dd59504a324bede4844e389) ) // digitalker header
	410	ROM_LOAD( "6.2d", 0x6000, 0x2000, CRC(156c91e0) SHA1(6017d4b5609b214a6e66dcd76493a7d1442c04d4) )
	411
	412	ROM_LOAD( "5.3a", 0x8000, 0x2000, CRC(19904604) SHA1(633c211a9a822cdf597a6f3c221ae9c8d6482e82) ) // digitalker header
	413	ROM_LOAD( "4.3b", 0xa000, 0x2000, CRC(c3386d51) SHA1(7882e88db55ba914be81075e4b2d76e246c34d3b) )
	414
	415	ROM_FILL( 0xc000, 0x2000, 0xff ) // unpopulated
	416	ROM_FILL( 0xe000, 0x2000, 0xff ) // unpopulated
	417	ROM_END
	418
	419	GAME( 1983, chexx83, 0, chexx83, chexx83, driver_device, 0, ROT270, "ICE", "Chexx (EM Bubble Hockey, 1983 1.1)", MACHINE_NOT_WORKING \| MACHINE_MECHANICAL \| MACHINE_NO_SOUND )
	420	GAME( 1983, faceoffh, chexx83, faceoffh, chexx83, driver_device, 0, ROT270, "SoftLogic (Entertainment Enterprises, Ltd. license)", "Face-Off (EM Bubble Hockey)", MACHINE_NOT_WORKING \| MACHINE_MECHANICAL \| MACHINE_IMPERFECT_SOUND )

trunk/src/mame/drivers/chqflag.c
r249025	r249026
306	306	MCFG_SCREEN_ADD("screen", RASTER)
307	307	MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/3, 528, 96, 400, 256, 16, 240) // measured Vsync 59.17hz Hsync 15.13 / 15.19khz
308	308	// 6MHz dotclock is more realistic, however needs drawing updates. replace when ready
309		// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
	309	// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
310	310	MCFG_SCREEN_UPDATE_DRIVER(chqflag_state, screen_update_chqflag)
311	311	MCFG_SCREEN_PALETTE("palette")
312	312

trunk/src/mame/drivers/cobra.c
r249025	r249026
1581	1581	{
1582	1582	// install HD patches for bujutsu
1583	1583	if (strcmp(space.machine().system().name, "bujutsu") == 0)
1584		{
	1584	{
1585	1585	UINT32 main_ram = (UINT32)(UINT64*)m_main_ram;
1586	1586	UINT32 sub_ram = (UINT32)m_sub_ram;
1587	1587	UINT32 gfx_ram = (UINT32)(UINT64*)m_gfx_ram0;
1588	1588
1589		main_ram[(0x0005ac^4) / 4] = 0x60000000; // skip IRQ fail
1590		main_ram[(0x001ec4^4) / 4] = 0x60000000; // waiting for IRQ?
1591		main_ram[(0x001f00^4) / 4] = 0x60000000; // waiting for IRQ?
1592
1593		sub_ram[0x568 / 4] = 0x60000000; // skip IRQ fail
	1589	main_ram[(0x0005ac^4) / 4] = 0x60000000; // skip IRQ fail
	1590	main_ram[(0x001ec4^4) / 4] = 0x60000000; // waiting for IRQ?
	1591	main_ram[(0x001f00^4) / 4] = 0x60000000; // waiting for IRQ?
1594	1592
1595		gfx_ram[(0x38632c^4) / 4] = 0x38600000; // skip check_one_scene()
	1593	sub_ram[0x568 / 4] = 0x60000000; // skip IRQ fail
	1594
	1595	gfx_ram[(0x38632c^4) / 4] = 0x38600000; // skip check_one_scene()
1596	1596	}
1597	1597	}
1598	1598

trunk/src/mame/drivers/crimfght.c
r249025	r249026
302	302	MCFG_SCREEN_ADD("screen", RASTER)
303	303	MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/3, 528, 96, 416, 256, 16, 240) // measured 59.17
304	304	// 6MHz dotclock is more realistic, however needs drawing updates. replace when ready
305		// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
	305	// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
306	306	MCFG_SCREEN_UPDATE_DRIVER(crimfght_state, screen_update_crimfght)
307	307	MCFG_SCREEN_PALETTE("palette")
308	308

trunk/src/mame/drivers/deco32.c
r249025	r249026
2036	2036	MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.35)
2037	2037	MACHINE_CONFIG_END
2038	2038
2039		static MACHINE_CONFIG_DERIVED( fghthistz, fghthsta )
	2039	static MACHINE_CONFIG_DERIVED( fghthistz, fghthsta )
2040	2040	MCFG_DEVICE_REMOVE("audiocpu")
2041	2041
2042	2042	MCFG_CPU_ADD("audiocpu", Z80, 32220000/9)

trunk/src/mame/drivers/faceoffh.c
r249025	r249026
1		// license:BSD-3-Clause
2		// copyright-holders:Luca Elia
3		/***************************************************************************
4
5		Sound board for an unknown game. Most probably a bubble hockey EM game
6		titled "Face-Off", an illegal? copy of Chexx Hockey by ICE. See here:
7
8		http://valker.us/gameroom/SegaFaceOff.htm
9		https://casetext.com/case/innovative-concepts-in-ent-v-entertainment-enter
10		http://www.pinrepair.com/arcade/chexx.htm
11
12		"Copyright (c) 1983 SoftLogic JAPAN" in the program rom.
13
14		The same PCB, with serial 025707, is allegedly for "Vampire" (prototype).
15
16		PCB:
17
18		Entertainment Enterprises Ltd. 1983 (sticker)
19		Serial No. 025402 (sticker)
20		MADE IN JAPAN (etched)
21
22		CPU: R6502P
23		RAM: M58725P (2KB)
24		I/O: R6522P (VIA)
25		Speech: Digitalker
26		Sound: AY-3-8910
27		Misc: XTAL 4MHz, DSW4, 42-pin connector
28
29		***************************************************************************/
30
31		#include "emu.h"
32		#include "cpu/m6502/m6502.h"
33		#include "sound/ay8910.h"
34		#include "sound/digitalk.h"
35		#include "machine/6522via.h"
36
37		#define MAIN_CLOCK XTAL_4MHz
38
39		class faceoffh_state : public driver_device
40		{
41		public:
42		faceoffh_state(const machine_config &mconfig, device_type type, const char *tag)
43		: driver_device(mconfig, type, tag),
44		m_audiocpu(*this, "audiocpu"),
45		m_digitalker(*this, "digitalker"),
46		m_aysnd(*this, "aysnd")
47		{
48		}
49
50		// devices
51		required_device<cpu_device> m_audiocpu;
52		required_device<digitalker_device> m_digitalker;
53		required_device<ay8910_device> m_aysnd;
54
55		// vars
56		UINT8 m_ay_cmd, m_ay_data;
57		UINT8 m_port_a, m_port_b;
58		UINT8 m_coin;
59		UINT8 m_bank;
60		UINT32 m_shift;
61
62		// screen updates
63		UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
64
65		// handlers
66		DECLARE_READ8_MEMBER(via_a_in);
67		DECLARE_READ8_MEMBER(via_b_in);
68
69		DECLARE_WRITE8_MEMBER(via_a_out);
70		DECLARE_WRITE8_MEMBER(via_b_out);
71
72		DECLARE_WRITE_LINE_MEMBER(via_ca2_out);
73		DECLARE_WRITE_LINE_MEMBER(via_cb1_out);
74		DECLARE_WRITE_LINE_MEMBER(via_cb2_out);
75		DECLARE_WRITE_LINE_MEMBER(via_irq_out);
76
77		DECLARE_WRITE8_MEMBER(faceoffh_ay_w);
78		DECLARE_READ8_MEMBER(faceoffh_coin_r);
79		DECLARE_WRITE8_MEMBER(faceoffh_coin_w);
80
81		// digitalker
82		void digitalker_set_bank(UINT8 bank);
83
84		// driver_device overrides
85		virtual void machine_start();
86		virtual void machine_reset();
87
88		virtual void video_start();
89		};
90
91
92		// VIA
93
94		READ8_MEMBER(faceoffh_state::via_a_in)
95		{
96		UINT8 ret = 0;
97		logerror("%s: VIA read A: %02X\n", machine().describe_context(), ret);
98		return ret;
99		}
100		READ8_MEMBER(faceoffh_state::via_b_in)
101		{
102		UINT8 ret = 0;
103		logerror("%s: VIA read B: %02X\n", machine().describe_context(), ret);
104		return ret;
105		}
106
107		WRITE8_MEMBER(faceoffh_state::via_a_out)
108		{
109		m_port_a = data; // multiplexer
110		// logerror("%s: VIA write A = %02X\n", machine().describe_context(), data);
111		}
112		WRITE8_MEMBER(faceoffh_state::via_b_out)
113		{
114		m_port_b = data;
115		// logerror("%s: VIA write B = %02X\n", machine().describe_context(), data);
116		}
117
118		WRITE_LINE_MEMBER(faceoffh_state::via_ca2_out)
119		{
120		// logerror("%s: VIA write CA2 = %02X\n", machine().describe_context(), state);
121		}
122		WRITE_LINE_MEMBER(faceoffh_state::via_cb1_out)
123		{
124		// logerror("%s: VIA write CB1 = %02X\n", machine().describe_context(), state);
125		}
126		WRITE_LINE_MEMBER(faceoffh_state::via_cb2_out)
127		{
128		m_shift = ((m_shift << 1) & 0xffffff) \| state;
129		// logerror("%s: VIA write CB2 = %02X\n", machine().describe_context(), state);
130		}
131		WRITE_LINE_MEMBER(faceoffh_state::via_irq_out)
132		{
133		m_audiocpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE);
134		// logerror("%s: VIA write IRQ = %02X\n", machine().describe_context(), state);
135		}
136
137		// Video
138
139		void faceoffh_state::video_start()
140		{
141		}
142
143		UINT32 faceoffh_state::screen_update( screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect )
144		{
145		// NMI on coin-in?
146		UINT8 coin = (~ioport("INPUTS")->read()) & 0x03;
147		m_audiocpu->set_input_line(INPUT_LINE_NMI, coin ? ASSERT_LINE : CLEAR_LINE);
148
149		// Play the digitalker samples (it's not hooked up yet)
150		static UINT8 sample = 0, bank = 0;
151
152		if (screen.machine().input().code_pressed_once(KEYCODE_Q))
153		--bank;
154		if (screen.machine().input().code_pressed_once(KEYCODE_W))
155		++bank;
156		bank %= 3;
157		digitalker_set_bank(bank);
158
159		if (screen.machine().input().code_pressed_once(KEYCODE_A))
160		--sample;
161		if (screen.machine().input().code_pressed_once(KEYCODE_S))
162		++sample;
163
164		if (screen.machine().input().code_pressed_once(KEYCODE_Z))
165		{
166		m_digitalker->digitalker_0_cms_w(CLEAR_LINE);
167		m_digitalker->digitalker_0_cs_w(CLEAR_LINE);
168
169		address_space &space = m_audiocpu->space(AS_PROGRAM);
170		m_digitalker->digitalker_data_w(space, 0, sample, 0xff);
171
172		m_digitalker->digitalker_0_wr_w(ASSERT_LINE);
173		m_digitalker->digitalker_0_wr_w(CLEAR_LINE);
174		m_digitalker->digitalker_0_wr_w(ASSERT_LINE);
175		}
176
177		popmessage("COIN: %02X VIAB: %02X\nCOUNT: %02X %02X LEDS: %02X\nSAMPLE: %02X (B%X)",
178		m_coin, m_port_b,
179		(m_shift >> 16) & 0xff, (m_shift >> 8) & 0xff, (m_shift >> 0) & 0xff, // 2 x 7-seg, 3 leds
180		sample, bank
181		);
182		return 0;
183		}
184
185		// Sound
186
187		#if 0
188		READ8_MEMBER(scramble_state::faceoffh_digitalker_intr_r)
189		{
190		return m_digitalker->digitalker_0_intr_r();
191		}
192
193		WRITE8_MEMBER(scramble_state::faceoffh_digitalker_control_w)
194		{
195		m_digitalker->digitalker_0_cs_w (data & 1 ? ASSERT_LINE : CLEAR_LINE);
196		m_digitalker->digitalker_0_cms_w(data & 2 ? ASSERT_LINE : CLEAR_LINE);
197		m_digitalker->digitalker_0_wr_w (data & 4 ? ASSERT_LINE : CLEAR_LINE);
198		}
199		#endif
200
201		WRITE8_MEMBER(faceoffh_state::faceoffh_ay_w)
202		{
203		if (offset)
204		{
205		m_ay_data = data;
206		return;
207		}
208
209		if (m_ay_cmd == 0x00 && data == 0x03)
210		{
211		m_aysnd->address_w(space, offset, m_ay_data, mem_mask);
212		// logerror("%s: AY addr = %02X\n", machine().describe_context(), m_ay_data);
213		}
214		else if (m_ay_cmd == 0x00 && data == 0x02)
215		{
216		m_aysnd->data_w(space, offset, m_ay_data, mem_mask);
217		// logerror("%s: AY data = %02X\n", machine().describe_context(), m_ay_data);
218		}
219		m_ay_cmd = data;
220		}
221
222		// Memory Map
223
224		READ8_MEMBER(faceoffh_state::faceoffh_coin_r)
225		{
226		UINT8 ret = ioport("DSW")->read(); // bits 0-3
227		UINT8 inp = ioport("INPUTS")->read(); // bit 7 (multiplexed)
228
229		for (int i = 0; i < 8; ++i)
230		if ( ((~m_port_a) & (1 << i)) && ((~inp) & (1 << i)) )
231		ret &= 0x7f;
232
233		return ret;
234		}
235
236		WRITE8_MEMBER(faceoffh_state::faceoffh_coin_w)
237		{
238		m_coin = data;
239		// coin_counter_w(machine(), 0, data & 0x01);
240		// coin_counter_w(machine(), 1, data & 0x02);
241		coin_lockout_w(machine(), 0, data & 0x01);
242		coin_lockout_w(machine(), 1, data & 0x02);
243		}
244
245		//M58725P - 2KB
246		static ADDRESS_MAP_START( faceoffh_map, AS_PROGRAM, 8, faceoffh_state )
247		AM_RANGE(0x0000, 0x00ff) AM_RAM
248		AM_RANGE(0x0100, 0x01ff) AM_RAM
249
250		AM_RANGE(0x4000, 0x400f) AM_DEVREADWRITE("via6522", via6522_device, read, write)
251
252		AM_RANGE(0x8000, 0x8000) AM_READ(faceoffh_coin_r)
253
254		AM_RANGE(0xa000, 0xa001) AM_WRITE(faceoffh_ay_w)
255
256		AM_RANGE(0xc000, 0xc000) AM_WRITE(faceoffh_coin_w)
257
258		AM_RANGE(0xf000, 0xffff) AM_ROM AM_REGION("audiocpu", 0)
259		ADDRESS_MAP_END
260
261		// Inputs
262
263		static INPUT_PORTS_START( faceoffh )
264		PORT_START("INPUTS")
265		PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(1) // coin 1 (start music)
266		PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(1) // coin 2 (start music)
267		PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 ) // ?
268		PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) // (stop music)
269		PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) // (stop music)
270		PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) // ?
271		PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON4 )
272		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON5 )
273
274		PORT_START("DSW")
275		PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW1:1,2")
276		PORT_DIPSETTING( 0x03, DEF_STR( 4C_1C ) )
277		PORT_DIPSETTING( 0x02, DEF_STR( 3C_1C ) )
278		PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
279		PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
280		PORT_DIPNAME( 0x0c, 0x00, "Game Duration (mins)" ) PORT_DIPLOCATION("SW1:3,4")
281		PORT_DIPSETTING( 0x00, "2" ) // 40
282		PORT_DIPSETTING( 0x04, "3" ) // 60
283		PORT_DIPSETTING( 0x08, "4" ) // 80
284		PORT_DIPSETTING( 0x0c, "5" ) // 100
285		PORT_BIT( 0x70, IP_ACTIVE_LOW, IPT_UNKNOWN )
286		PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SPECIAL ) // multiplexed inputs
287		INPUT_PORTS_END
288
289		// Machine
290
291		void faceoffh_state::machine_start()
292		{
293		}
294
295		void faceoffh_state::digitalker_set_bank(UINT8 bank)
296		{
297		if (m_bank != bank)
298		{
299		UINT8 *src = memregion("samples")->base();
300		UINT8 *dst = memregion("digitalker")->base();
301
302		memcpy(dst, src + bank * 0x4000, 0x4000);
303
304		m_bank = bank;
305		}
306		}
307
308		void faceoffh_state::machine_reset()
309		{
310		m_bank = -1;
311		digitalker_set_bank(0);
312		}
313
314		static MACHINE_CONFIG_START( faceoffh, faceoffh_state )
315
316		// basic machine hardware
317		MCFG_CPU_ADD("audiocpu", M6502, MAIN_CLOCK/2)
318		MCFG_CPU_PROGRAM_MAP(faceoffh_map)
319		// MCFG_CPU_VBLANK_INT_DRIVER("screen", faceoffh_state, irq0_line_hold)
320		// MCFG_CPU_VBLANK_INT_DRIVER("screen", faceoffh_state, nmi_line_pulse)
321
322		// via
323		MCFG_DEVICE_ADD("via6522", VIA6522, MAIN_CLOCK/4)
324
325		MCFG_VIA6522_READPA_HANDLER(READ8(faceoffh_state,via_a_in))
326		MCFG_VIA6522_READPB_HANDLER(READ8(faceoffh_state,via_b_in))
327
328		MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(faceoffh_state, via_a_out))
329		MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(faceoffh_state, via_b_out))
330
331		MCFG_VIA6522_CA2_HANDLER(WRITELINE(faceoffh_state, via_ca2_out))
332		MCFG_VIA6522_CB1_HANDLER(WRITELINE(faceoffh_state, via_cb1_out))
333		MCFG_VIA6522_CB2_HANDLER(WRITELINE(faceoffh_state, via_cb2_out))
334		MCFG_VIA6522_IRQ_HANDLER(WRITELINE(faceoffh_state, via_irq_out)/DEVWRITELINE("audiocpu", m6502_device, write_irq4)/)
335
336		// video hardware
337		MCFG_SCREEN_ADD("screen", RASTER)
338		MCFG_SCREEN_REFRESH_RATE(60)
339		MCFG_SCREEN_UPDATE_DRIVER(faceoffh_state, screen_update)
340		MCFG_SCREEN_SIZE(256, 256)
341		MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 256-1)
342		MCFG_SCREEN_PALETTE("palette")
343
344		MCFG_PALETTE_ADD("palette", 16)
345
346		// sound hardware
347		MCFG_SPEAKER_STANDARD_MONO("mono")
348		MCFG_SOUND_ADD("aysnd", AY8910, MAIN_CLOCK/2)
349		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
350
351		MCFG_DIGITALKER_ADD("digitalker", MAIN_CLOCK)
352		MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.16)
353		MACHINE_CONFIG_END
354
355		// ROMs
356
357		ROM_START( faceoffh )
358		ROM_REGION( 0x1000, "audiocpu", 0 )
359		ROM_LOAD( "1.5d", 0x0000, 0x1000, CRC(6ab050be) SHA1(ebecae855e22e9c3c46bdee51f84fd5352bf191a) )
360
361		ROM_REGION( 0x4000, "digitalker", ROMREGION_ERASE00 )
362		// bank switched (from samples region)
363
364		ROM_REGION( 0xc000, "samples", 0 )
365		ROM_LOAD( "9.2a", 0x0000, 0x2000, CRC(059b3725) SHA1(5837bee1ef34ce19a3101b851ca55029776e4b3e) ) // digitalker header
366		ROM_LOAD( "8.2b", 0x2000, 0x2000, CRC(679da4e1) SHA1(01a5b9dd132c1b0de97c153d7de226f5bf357338) )
367
368		ROM_LOAD( "7.2c", 0x4000, 0x2000, CRC(f8461b33) SHA1(717a8842e0ce9ba94dd59504a324bede4844e389) ) // digitalker header
369		ROM_LOAD( "6.2d", 0x6000, 0x2000, CRC(156c91e0) SHA1(6017d4b5609b214a6e66dcd76493a7d1442c04d4) )
370
371		ROM_LOAD( "5.3a", 0x8000, 0x2000, CRC(19904604) SHA1(633c211a9a822cdf597a6f3c221ae9c8d6482e82) ) // digitalker header
372		ROM_LOAD( "4.3b", 0xa000, 0x2000, CRC(c3386d51) SHA1(7882e88db55ba914be81075e4b2d76e246c34d3b) )
373		ROM_END
374
375		GAME( 1983, faceoffh, 0, faceoffh, faceoffh, driver_device, 0, ROT270, "SoftLogic (Entertainment Enterprises, Ltd. license)", "Face-Off (EM Bubble Hockey)", MACHINE_IS_SKELETON_MECHANICAL \| MACHINE_IMPERFECT_SOUND )

trunk/src/mame/drivers/fcrash.c
r249025	r249026
2958	2958
2959	2959	GAME( 1992, sf2b, sf2, sf2b, sf2mdt, cps_state, sf2b, ROT0, "bootleg", "Street Fighter II: The World Warrior (bootleg)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_SUPPORTS_SAVE ) //910204 - based on World version
2960	2960
2961		GAME( 1992, sf2m9, sf2ce, sf2m1, sf2, cps_state, ~~dinopic~~, ROT0, "bootleg", "Street Fighter II': Champion Edition (M9, bootleg)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_SUPPORTS_SAVE ) // 920313 ETC
	2961	GAME( 1992, sf2m9, sf2ce, sf2m1, sf2, cps_state, sf2m1, ROT0, "bootleg", "Street Fighter II': Champion Edition (M9, bootleg)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_SUPPORTS_SAVE ) // 920313 ETC
2962	2962
2963	2963	GAME( 1993, slampic, slammast, slampic, slammast, cps_state, dinopic, ROT0, "bootleg", "Saturday Night Slam Masters (bootleg with PIC16c57)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_NO_SOUND \| MACHINE_SUPPORTS_SAVE ) // 930713 ETC
2964	2964

trunk/src/mame/drivers/firebeat.c
r249025	r249026
1064	1064	AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read_cs0, write_cs0)
1065	1065	AM_RANGE(0x340000, 0x34000f) AM_DEVREADWRITE("spu_ata", ata_interface_device, read_cs1, write_cs1)
1066	1066	AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rf5c400", rf5c400_device, rf5c400_r, rf5c400_w)
1067		AM_RANGE(0x800000, 0x83ffff) AM_RAM // SDRAM
1068		AM_RANGE(0xfc0000, 0xffffff) AM_RAM // SDRAM
	1067	AM_RANGE(0x800000, 0x83ffff) AM_RAM // SDRAM
	1068	AM_RANGE(0xfc0000, 0xffffff) AM_RAM // SDRAM
1069	1069	ADDRESS_MAP_END
1070	1070
1071	1071	/*****************************************************************************/

trunk/src/mame/drivers/gunsmoke.c
r249025	r249026
538	538	ROM_LOAD( "gsr_03a.9n", 0x00000, 0x8000, CRC(2f6e6ad7) SHA1(e9e4a367c240a35a1ba2eeaec9458996f7926f16) ) /* Code 0000-7fff */
539	539	ROM_LOAD( "gs04.10n", 0x10000, 0x8000, CRC(8d4b423f) SHA1(149274c2ed1526ca1f419fdf8a24059ff138f7f2) ) /* Paged code */
540	540	ROM_LOAD( "gs05.12n", 0x18000, 0x8000, CRC(2b5667fb) SHA1(5b689bca1e76d803b4cae22feaa7744fa528e93f) ) /* Paged code */
541
	541
542	542	ROM_REGION( 0x10000, "audiocpu", 0 )
543	543	ROM_LOAD( "gs02.14h", 0x00000, 0x8000, CRC(cd7a2c38) SHA1(c76c471f694b76015370f0eacf5350e652f526ff) )
544	544

trunk/src/mame/drivers/joystand.c
r249025	r249026
338	338	m_bg2_tmap->set_scrolly(0, m_scroll[1]);
339	339
340	340	draw_bg15_tilemap();
341
	341
342	342	bitmap.fill(m_palette->black_pen(), cliprect);
343		if (layers_ctrl & 4) copybitmap_trans(bitmap, m_bg15_bitmap[0], 0, 0, 1, 0, cliprect, BG15_TRANSPARENT);
344		if (layers_ctrl & 8) copybitmap_trans(bitmap, m_bg15_bitmap[1], 0, 0, 0, 0, cliprect, BG15_TRANSPARENT);
345		if (layers_ctrl & 1) m_bg1_tmap->draw(screen, bitmap, cliprect, 0, 0);
346		if (layers_ctrl & 2) m_bg2_tmap->draw(screen, bitmap, cliprect, 0, 0);
	343	if (layers_ctrl & 4) copybitmap_trans(bitmap, m_bg15_bitmap[0], 0, 0, 1, 0, cliprect, BG15_TRANSPARENT);
	344	if (layers_ctrl & 8) copybitmap_trans(bitmap, m_bg15_bitmap[1], 0, 0, 0, 0, cliprect, BG15_TRANSPARENT);
	345	if (layers_ctrl & 1) m_bg1_tmap->draw(screen, bitmap, cliprect, 0, 0);
	346	if (layers_ctrl & 2) m_bg2_tmap->draw(screen, bitmap, cliprect, 0, 0);
347	347
348	348	popmessage("S0: %04X S1: %04X EN: %04X OUT: %04X", m_scroll[0], m_scroll[1], m_enable[0], m_outputs[0]);
349	349	return 0;
r249025	r249026
394	394	COMBINE_DATA(&m_outputs[0]);
395	395	if (ACCESSING_BITS_8_15)
396	396	{
397		coin_counter_w(machine(), 0, BIT(data, 0)); // coin counter 1
398		coin_counter_w(machine(), 1, BIT(data, 1)); // coin counter 2
	397	coin_counter_w(machine(), 0, BIT(data, 0)); // coin counter 1
	398	coin_counter_w(machine(), 1, BIT(data, 1)); // coin counter 2
399	399
400		output_set_value("blocker", BIT(data, 2));
401		output_set_value("error_lamp", BIT(data, 3)); // counter error
402		output_set_value("photo_lamp", BIT(data, 4)); // during photo
	400	output_set_value("blocker", BIT(data, 2));
	401	output_set_value("error_lamp", BIT(data, 3)); // counter error
	402	output_set_value("photo_lamp", BIT(data, 4)); // during photo
403	403	}
404	404	if (ACCESSING_BITS_8_15)
405	405	{
406		output_set_value("ok_button_led", BIT(data, 8));
407		output_set_value("cancel_button_led", BIT(data, 9));
	406	output_set_value("ok_button_led", BIT(data, 8));
	407	output_set_value("cancel_button_led", BIT(data, 9));
408	408	}
409	409	}
410	410
r249025	r249026
449	449	AM_RANGE(0x200010, 0x200011) AM_READ_PORT("IN0") // r/w
450	450	AM_RANGE(0x200012, 0x200013) AM_RAM_WRITE(outputs_w) AM_SHARE("outputs") // r/w
451	451	AM_RANGE(0x200014, 0x200015) AM_READWRITE(fpga_r, oki_bank_w) // r/w
452		// AM_RANGE(0x200016, 0x200017) // write $9190 at boot
	452	// AM_RANGE(0x200016, 0x200017) // write $9190 at boot
453	453
454	454	AM_RANGE(0x400000, 0x47ffff) AM_RAM_WRITE(bg15_0_w) AM_SHARE("bg15_0_ram") // r5g5b5 200x200 pixel-based
455	455	AM_RANGE(0x480000, 0x4fffff) AM_RAM // more rgb layers? (writes at offset 0)
r249025	r249026
464	464	AM_RANGE(0x60c00c, 0x60c00d) AM_RAM AM_SHARE("enable") // write
465	465
466	466	AM_RANGE(0x800000, 0xdfffff) AM_READWRITE(cart_r, cart_w) // r/w (cart flash)
467		// AM_RANGE(0xe00080, 0xe00081) // write (bit 0 = cart? bit 1 = ? bit 3 = ?)
	467	// AM_RANGE(0xe00080, 0xe00081) // write (bit 0 = cart? bit 1 = ? bit 3 = ?)
468	468	AM_RANGE(0xe00000, 0xe00001) AM_READ(e00000_r) // copy slot
469	469	AM_RANGE(0xe00020, 0xe00021) AM_READ(e00020_r) // master slot
470	470
r249025	r249026
478	478	// Cart status:
479	479	// mask 0x1000 -> cart flash addressing (0 = sequential, 1 = interleaved even/odd)
480	480	// mask 0x6000 == 0 -> cart present?
481		// mask 0x8000 -> cart ready?
	481	// mask 0x8000 -> cart ready?
482	482
483	483	PORT_START("MASTER")
484	484	PORT_CONFNAME( 0x1000, 0x1000, "Master Flash Addressing" )
r249025	r249026
559	559
560	560	void joystand_state::machine_start()
561	561	{
562		m_cart_flash[0] = m_cart_u11; m_cart_flash[1] = m_cart_u5;
563		m_cart_flash[2] = m_cart_u12; m_cart_flash[3] = m_cart_u6;
564		m_cart_flash[4] = m_cart_u9; m_cart_flash[5] = m_cart_u3;
565		m_cart_flash[6] = m_cart_u10; m_cart_flash[7] = m_cart_u4;
566		m_cart_flash[8] = m_cart_u7; m_cart_flash[9] = m_cart_u1;
567		m_cart_flash[10] = m_cart_u8; m_cart_flash[11] = m_cart_u2;
	562	m_cart_flash[0] = m_cart_u11; m_cart_flash[1] = m_cart_u5;
	563	m_cart_flash[2] = m_cart_u12; m_cart_flash[3] = m_cart_u6;
	564	m_cart_flash[4] = m_cart_u9; m_cart_flash[5] = m_cart_u3;
	565	m_cart_flash[6] = m_cart_u10; m_cart_flash[7] = m_cart_u4;
	566	m_cart_flash[8] = m_cart_u7; m_cart_flash[9] = m_cart_u1;
	567	m_cart_flash[10] = m_cart_u8; m_cart_flash[11] = m_cart_u2;
568	568	}
569	569
570	570	void joystand_state::machine_reset()

trunk/src/mame/drivers/kaneko16.c
r249025	r249026
36	36	94 Great 1000 Miles Rally Z09AF-005 TBSOP01 MCU protection (EEPROM handling etc.)
37	37	Bonk's Adventure Z09AF-003 TBSOP01 MCU protection (EEPROM handling, 68k code snippet, data)
38	38	Blood Warrior Z09AF-005 TBSOP01 MCU protection (EEPROM handling etc.)
39		Pack'n Bang Bang BW-002 (prototype)
	39	Pack'n Bang Bang BW-002 (prototype)
40	40	95 Great 1000 Miles Rally 2 M201F00138 TBSOP02 MCU protection (EEPROM handling etc.)
41	41	----------------------------------------------------------------------------------------
42	42
r249025	r249026
1505	1505	PORT_DIPSETTING( 0x20, DEF_STR( 1C_5C ) )
1506	1506	PORT_DIPSETTING( 0x00, DEF_STR( 1C_6C ) )
1507	1507
1508		PORT_START("DSW2")
	1508	PORT_START("DSW2")
1509	1509	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
1510	1510	PORT_DIPSETTING( 0x02, DEF_STR( Easy ) )
1511	1511	PORT_DIPSETTING( 0x03, DEF_STR( Normal ) )

trunk/src/mame/drivers/konendev.c
r249025	r249026
84	84
85	85	if (ACCESSING_BITS_24_31)
86	86	{
87		r \|= 0x11000000; // MCU2 version
	87	r \|= 0x11000000; // MCU2 version
88	88	}
89	89	if (ACCESSING_BITS_16_23)
90	90	{
r249025	r249026
92	92	}
93	93	if (ACCESSING_BITS_8_15)
94	94	{
95		r &= ~0x4000; // MCU2 presence
96		r &= ~0x2000; // IFU2 presence
97		r &= ~0x1000; // FMU2 presence
	95	r &= ~0x4000; // MCU2 presence
	96	r &= ~0x2000; // IFU2 presence
	97	r &= ~0x1000; // FMU2 presence
98	98	}
99	99	if (ACCESSING_BITS_0_7)
100	100	{
101		r \|= 0x40; // logic door
102		r \|= 0x04; // battery 1 status
103		r \|= 0x10; // battery 2 status
	101	r \|= 0x40; // logic door
	102	r \|= 0x04; // battery 1 status
	103	r \|= 0x10; // battery 2 status
104	104	}
105	105
106	106	return r;
r249025	r249026
112	112
113	113	if (ACCESSING_BITS_0_7)
114	114	{
115		r \|= 0x11; // IFU2 version
	115	r \|= 0x11; // IFU2 version
116	116	}
117	117
118	118	return r;
r249025	r249026
151	151	AM_RANGE(0x78800004, 0x78800007) AM_READ(unk_78800004_r)
152	152	AM_RANGE(0x78a00000, 0x78a0001f) AM_READ(unk_78a00000_r)
153	153	AM_RANGE(0x78e00000, 0x78e00003) AM_READ(unk_78e00000_r)
154		// AM_RANGE(0x78000000, 0x78000003) AM_READNOP
155		// AM_RANGE(0x78100000, 0x7810001b) AM_RAM
156		// AM_RANGE(0x78a00014, 0x78a00017) AM_WRITENOP
	154	// AM_RANGE(0x78000000, 0x78000003) AM_READNOP
	155	// AM_RANGE(0x78100000, 0x7810001b) AM_RAM
	156	// AM_RANGE(0x78a00014, 0x78a00017) AM_WRITENOP
157	157	AM_RANGE(0x79000000, 0x79000003) AM_DEVWRITE("gcu", k057714_device, fifo_w)
158	158	AM_RANGE(0x79800000, 0x798000ff) AM_DEVREADWRITE("gcu", k057714_device, read, write)
159	159	AM_RANGE(0x7a000000, 0x7a01ffff) AM_RAM AM_SHARE("nvram0")
r249025	r249026
218	218	ROM_LOAD( "enl5r211.fmu.bin", 0x0000, 0x1800000, CRC(592c3c7f) SHA1(119b3c6223d656981c399c399d7edccfdbb50dc7) )
219	219
220	220	ROM_REGION32_BE( 0x100, "eeprom", 0 )
221		ROM_LOAD( "93c56.u98", 0x00, 0x100, CRC(b2521a6a) SHA1(f44711545bee7e9c772a3dc23b79f0ea8059ec50) ) // empty eeprom with Konami header
	221	ROM_LOAD( "93c56.u98", 0x00, 0x100, CRC(b2521a6a) SHA1(f44711545bee7e9c772a3dc23b79f0ea8059ec50) ) // empty eeprom with Konami header
222	222	ROM_END
223	223
224	224
r249025	r249026
348	348	ROM_REGION32_BE( 0x1800000, "flash", ROMREGION_ERASE00 )
349	349
350	350	ROM_REGION32_BE( 0x100, "eeprom", 0 )
351		ROM_LOAD( "93c56.u98", 0x00, 0x100, CRC(b2521a6a) SHA1(f44711545bee7e9c772a3dc23b79f0ea8059ec50) ) // empty eeprom with Konami header
	351	ROM_LOAD( "93c56.u98", 0x00, 0x100, CRC(b2521a6a) SHA1(f44711545bee7e9c772a3dc23b79f0ea8059ec50) ) // empty eeprom with Konami header
352	352	ROM_END
353	353
354	354	DRIVER_INIT_MEMBER(konendev_state,konendev)
r249025	r249026
358	358	DRIVER_INIT_MEMBER(konendev_state,enchlamp)
359	359	{
360	360	UINT32 rom = (UINT32)memregion("program")->base();
361		rom[0x24/4] = 0x00002743; // patch flash checksum for now
	361	rom[0x24/4] = 0x00002743; // patch flash checksum for now
362	362
363		rom[0] = 0xd43eb930; // new checksum for program rom
	363	rom[0] = 0xd43eb930; // new checksum for program rom
364	364	}
365	365
366	366	// has a flash dump?

trunk/src/mame/drivers/lethalj.c
r249025	r249026
681	681
682	682	ROM_START( lethalj )
683	683	ROM_REGION16_LE( 0x100000, "user1", 0 ) /* 34010 code */
684		ROM_LOAD16_BYTE( "vc8", 0x000000, 0x080000, CRC(8d568e1d) SHA1(e4dd3794789f9ccd7be8374978a3336f2b79136f) )
685		ROM_LOAD16_BYTE( "vc9", 0x000001, 0x080000, CRC(8f22add4) SHA1(e773d3ae9cf512810fc266e784d21ed115c8830c) )
	684	ROM_LOAD16_BYTE( "lethal_vc8_2.3.vc8", 0x000000, 0x080000, CRC(8d568e1d) SHA1(e4dd3794789f9ccd7be8374978a3336f2b79136f) ) /* Labeled as LETHAL VC8 2.3, also found labeled as VC-8 */
	685	ROM_LOAD16_BYTE( "lethal_vc9_2.3.vc9", 0x000001, 0x080000, CRC(8f22add4) SHA1(e773d3ae9cf512810fc266e784d21ed115c8830c) ) /* Labeled as LETHAL VC9 2.3, also found labeled as VC-9 */
686	686
687	687	ROM_REGION16_LE( 0x600000, "gfx1", 0 ) /* graphics data */
688		ROM_LOAD16_BYTE( "gr1", 0x000000, 0x100000, CRC(27f7b244) SHA1(628b29c066e217e1fe54553ea3ed98f86735e262) )
689		ROM_LOAD16_BYTE( "gr2", 0x000001, 0x100000, CRC(1f25d3ab) SHA1(bdb8a3c546cdee9a5630c47b9c5079a956e8a093) )
690		ROM_LOAD16_BYTE( "gr4", 0x200000, 0x100000, CRC(c5838b4c) SHA1(9ad03d0f316eb31fdf0ca6f65c02a27d3406d072) )
691		ROM_LOAD16_BYTE( "gr3", 0x200001, 0x100000, CRC(ba9fa057) SHA1(db6f11a8964870f04f94fef6f1b1a58168a942ad) )
692		ROM_LOAD16_BYTE( "gr6", 0x400000, 0x100000, CRC(51c99b85) SHA1(9a23bf21a73d2884b49c64a8f42c288534c79dc5) )
693		ROM_LOAD16_BYTE( "gr5", 0x400001, 0x100000, CRC(80dda9b5) SHA1(d8a79cad112bc7d9e4ba31a950e4807581f3bf46) )
	688	ROM_LOAD16_BYTE( "gr1.gr1", 0x000000, 0x100000, CRC(27f7b244) SHA1(628b29c066e217e1fe54553ea3ed98f86735e262) ) /* These had non specific GRx labels, also found labeled as GR-x */
	689	ROM_LOAD16_BYTE( "gr2.gr2", 0x000001, 0x100000, CRC(1f25d3ab) SHA1(bdb8a3c546cdee9a5630c47b9c5079a956e8a093) )
	690	ROM_LOAD16_BYTE( "gr4.gr4", 0x200000, 0x100000, CRC(c5838b4c) SHA1(9ad03d0f316eb31fdf0ca6f65c02a27d3406d072) )
	691	ROM_LOAD16_BYTE( "gr3.gr3", 0x200001, 0x100000, CRC(ba9fa057) SHA1(db6f11a8964870f04f94fef6f1b1a58168a942ad) )
	692	ROM_LOAD16_BYTE( "lethal_gr6_2.3.gr6", 0x400000, 0x100000, CRC(51c99b85) SHA1(9a23bf21a73d2884b49c64a8f42c288534c79dc5) ) /* Labeled as LETHAL GR6 2.3, also found labeled as GR-6 */
	693	ROM_LOAD16_BYTE( "lethal_gr5_2.3.gr5", 0x400001, 0x100000, CRC(80dda9b5) SHA1(d8a79cad112bc7d9e4ba31a950e4807581f3bf46) ) /* Labeled as LETHAL GR5 2.3, also found labeled as GR-5 */
694	694
695	695	ROM_REGION( 0x40000, "oki1", 0 ) /* sound data */
696	696	ROM_LOAD( "sound1.u20", 0x00000, 0x40000, CRC(7d93ca66) SHA1(9e1dc0efa5d0f770c7e1f10de56fbf5620dea437) )
r249025	r249026
1007	1007	*
1008	1008	*************************************/
1009	1009
1010		GAME( 1996, lethalj, 0, lethalj, lethalj, driver_device, 0, ROT0, "The Game Room", "Lethal Justice", 0 )
	1010	GAME( 1996, lethalj, 0, lethalj, lethalj, driver_device, 0, ROT0, "The Game Room", "Lethal Justice (Version 2.3)", 0 )
1011	1011	GAME( 1996, franticf, 0, gameroom, franticf, driver_device, 0, ROT0, "The Game Room", "Frantic Fred", MACHINE_NOT_WORKING )
1012	1012	GAME( 1997, eggventr, 0, gameroom, eggventr, driver_device, 0, ROT0, "The Game Room", "Egg Venture (Release 10)", 0 )
1013	1013	GAME( 1997, eggventr8, eggventr, gameroom, eggventr, driver_device, 0, ROT0, "The Game Room", "Egg Venture (Release 8)", 0 )

trunk/src/mame/drivers/megasys1.c
r249025	r249026
3591	3591
3592	3592	Bootleg version of Saint Dragon. Two PCBs connected by two flat cables.
3593	3593	Sound section can host two oki chips (and roms) but only one is populated.
3594		No ASICs just logic chips.
	3594	No ASICs just logic chips.
3595	3595
3596	3596	- ROMs A-19 and A-20 are fitted 'piggy backed' with one pin
3597	3597	from A-20 bent out and wired to a nearby TTL.

trunk/src/mame/drivers/midxunit.c
r249025	r249026
345	345	ROM_LOAD( "a-17721.u955", 0x200, 0x117, CRC(033fe902) SHA1(6efb4e519ed3c9d49fff046a679762b506b3a75b) )
346	346	ROM_END
347	347
	348	ROM_START( revxp5 )
	349	ROM_REGION16_LE( 0x1000000, "dcs", ROMREGION_ERASEFF ) /* sound data */
	350	ROM_LOAD16_BYTE( "revx_snd.2", 0x000000, 0x80000, CRC(4ed9e803) SHA1(ba50f1beb9f2a2cf5110897209b5e9a2951ff165) )
	351	ROM_LOAD16_BYTE( "revx_snd.3", 0x200000, 0x80000, CRC(af8f253b) SHA1(25a0000cab177378070f7a6e3c7378fe87fad63e) )
	352	ROM_LOAD16_BYTE( "revx_snd.4", 0x400000, 0x80000, CRC(3ccce59c) SHA1(e81a31d64c64e7b1d25f178c53da3d68453c203c) )
	353	ROM_LOAD16_BYTE( "revx_snd.5", 0x600000, 0x80000, CRC(a0438006) SHA1(560d216d21cb8073dbee0fd20ebe589932a9144e) )
	354	ROM_LOAD16_BYTE( "revx_snd.6", 0x800000, 0x80000, CRC(b7b34f60) SHA1(3b9682c6a00fa3bdb47e69d8e8ceccc244ee55b5) )
	355	ROM_LOAD16_BYTE( "revx_snd.7", 0xa00000, 0x80000, CRC(6795fd88) SHA1(7c3790730a8b99b63112c851318b1c7e4989e5e0) )
	356	ROM_LOAD16_BYTE( "revx_snd.8", 0xc00000, 0x80000, CRC(793a7eb5) SHA1(4b1f81b68f95cedf1b356ef362d1eb37acc74b16) )
	357	ROM_LOAD16_BYTE( "revx_snd.9", 0xe00000, 0x80000, CRC(14ddbea1) SHA1(8dba9dc5529ea77c4312ea61f825bf9062ffc6c3) )
348	358
	359	ROM_REGION16_LE( 0x200000, "maincpu", 0 ) /* 34020 code */
	360	ROM_LOAD32_BYTE( "revx_p5.51", 0x00000, 0x80000, CRC(f3877eee) SHA1(7a4fdce36edddd35308c107c992ce626a2c9eb8c) )
	361	ROM_LOAD32_BYTE( "revx_p5.52", 0x00001, 0x80000, CRC(199a54d8) SHA1(45319437e11176d4926c00c95c372098203a32a3) )
	362	ROM_LOAD32_BYTE( "revx_p5.53", 0x00002, 0x80000, CRC(fcfcf72a) SHA1(b471afb416e3d348b046b0b40f497d27b0afa470) )
	363	ROM_LOAD32_BYTE( "revx_p5.54", 0x00003, 0x80000, CRC(fd684c31) SHA1(db3453792e4d9fc375297d030f0b3f9cc3cad925) )
349	364
	365	ROM_REGION( 0x2000, "pic", 0 )
	366	ROM_LOAD( "revx_16c57.bin", 0x0000000, 0x2000, CRC(eb8a8649) SHA1(a1e1d0b7a5e9802e8f889eb7e719259656dc8133) )
	367
	368	ROM_REGION( 0x1000000, "gfxrom", 0 )
	369	ROM_LOAD32_BYTE( "revx.120", 0x0000000, 0x80000, CRC(523af1f0) SHA1(a67c0fd757e860fc1c1236945952a295b4d5df5a) )
	370	ROM_LOAD32_BYTE( "revx.121", 0x0000001, 0x80000, CRC(78201d93) SHA1(fb0b8f887eec433f7624f387d7fb6f633ea30d7c) )
	371	ROM_LOAD32_BYTE( "revx.122", 0x0000002, 0x80000, CRC(2cf36144) SHA1(22ed0eefa2c7c836811fac5f717c3f38254eabc2) )
	372	ROM_LOAD32_BYTE( "revx.123", 0x0000003, 0x80000, CRC(6912e1fb) SHA1(416f0de711d80e9182ede524c568c5095b1bec61) )
	373
	374	ROM_LOAD32_BYTE( "revx.110", 0x0200000, 0x80000, CRC(e3f7f0af) SHA1(5877d9f488b0f4362a9482007c3ff7f4589a036f) )
	375	ROM_LOAD32_BYTE( "revx.111", 0x0200001, 0x80000, CRC(49fe1a69) SHA1(9ae54b461f0524c034fbcb6fcd3fd5ccb5d7265a) )
	376	ROM_LOAD32_BYTE( "revx.112", 0x0200002, 0x80000, CRC(7e3ba175) SHA1(dd2fe90988b544f67dbe6151282fd80d49631388) )
	377	ROM_LOAD32_BYTE( "revx.113", 0x0200003, 0x80000, CRC(c0817583) SHA1(2f866e5888e212b245984344950d0e1fb8957a73) )
	378
	379	ROM_LOAD32_BYTE( "revx.101", 0x0400000, 0x80000, CRC(5a08272a) SHA1(17da3c9d71114f5fdbf50281a942be3da3b6f564) )
	380	ROM_LOAD32_BYTE( "revx.102", 0x0400001, 0x80000, CRC(11d567d2) SHA1(7ebe6fd39a0335e1fdda150d2dc86c3eaab17b2e) )
	381	ROM_LOAD32_BYTE( "revx.103", 0x0400002, 0x80000, CRC(d338e63b) SHA1(0a038217542667b3a01ecbcad824ee18c084f293) )
	382	ROM_LOAD32_BYTE( "revx.104", 0x0400003, 0x80000, CRC(f7b701ee) SHA1(0fc5886e5857326bee7272d5d482a878cbcea83c) )
	383
	384	ROM_LOAD32_BYTE( "revx.91", 0x0600000, 0x80000, CRC(52a63713) SHA1(dcc0ff3596bd5d273a8d4fd33b0b9b9d588d8354) )
	385	ROM_LOAD32_BYTE( "revx.92", 0x0600001, 0x80000, CRC(fae3621b) SHA1(715d41ea789c0c724baa5bd90f6f0f06b9cb1c64) )
	386	ROM_LOAD32_BYTE( "revx.93", 0x0600002, 0x80000, CRC(7065cf95) SHA1(6c5888da099e51c4b1c592721c5027c899cf52e3) )
	387	ROM_LOAD32_BYTE( "revx.94", 0x0600003, 0x80000, CRC(600d5b98) SHA1(6aef98c91f87390c0759fe71a272a3ccadd71066) )
	388
	389	ROM_LOAD32_BYTE( "revx.81", 0x0800000, 0x80000, CRC(729eacb1) SHA1(d130162ae22b99c84abfbe014c4e23e20afb757f) )
	390	ROM_LOAD32_BYTE( "revx.82", 0x0800001, 0x80000, CRC(19acb904) SHA1(516059b516bc5b1669c9eb085e0cdcdee520dff0) )
	391	ROM_LOAD32_BYTE( "revx.83", 0x0800002, 0x80000, CRC(0e223456) SHA1(1eedbd667f4a214533d1c22ca5312ecf2d4a3ab4) )
	392	ROM_LOAD32_BYTE( "revx.84", 0x0800003, 0x80000, CRC(d3de0192) SHA1(2d22c5bac07a7411f326691167c7c70eba4b371f) )
	393
	394	ROM_LOAD32_BYTE( "revx.71", 0x0a00000, 0x80000, CRC(2b29fddb) SHA1(57b71e5c18b56bf58216e690fdefa6d30d88d34a) )
	395	ROM_LOAD32_BYTE( "revx.72", 0x0a00001, 0x80000, CRC(2680281b) SHA1(d1ae0701d20166a00d8733d9d12246c140a5fb96) )
	396	ROM_LOAD32_BYTE( "revx.73", 0x0a00002, 0x80000, CRC(420bde4d) SHA1(0f010cdeddb59631a5420dddfc142c50c2a1e65a) )
	397	ROM_LOAD32_BYTE( "revx.74", 0x0a00003, 0x80000, CRC(26627410) SHA1(a612121554549afff5c8e8c54774ca7b0220eda8) )
	398
	399	ROM_LOAD32_BYTE( "revx.63", 0x0c00000, 0x80000, CRC(3066e3f3) SHA1(25548923db111bd6c6cff44bfb63cb9eb2ef0b53) )
	400	ROM_LOAD32_BYTE( "revx.64", 0x0c00001, 0x80000, CRC(c33f5309) SHA1(6bb333f563ea66c4c862ffd5fb91fb5e1b919fe8) )
	401	ROM_LOAD32_BYTE( "revx.65", 0x0c00002, 0x80000, CRC(6eee3e71) SHA1(0ef22732e0e2bb5207559decd43f90d1e338ad7b) )
	402	ROM_LOAD32_BYTE( "revx.66", 0x0c00003, 0x80000, CRC(b43d6fff) SHA1(87584e7aeea9d52a43023d40c359591ff6342e84) )
	403
	404	ROM_LOAD32_BYTE( "revx_p5.51", 0xe00000, 0x80000, CRC(f3877eee) SHA1(7a4fdce36edddd35308c107c992ce626a2c9eb8c) )
	405	ROM_LOAD32_BYTE( "revx_p5.52", 0xe00001, 0x80000, CRC(199a54d8) SHA1(45319437e11176d4926c00c95c372098203a32a3) )
	406	ROM_LOAD32_BYTE( "revx_p5.53", 0xe00002, 0x80000, CRC(fcfcf72a) SHA1(b471afb416e3d348b046b0b40f497d27b0afa470) )
	407	ROM_LOAD32_BYTE( "revx_p5.54", 0xe00003, 0x80000, CRC(fd684c31) SHA1(db3453792e4d9fc375297d030f0b3f9cc3cad925) )
	408
	409	ROM_REGION( 0x400, "plds", 0 )
	410	ROM_LOAD( "a-17722.u1", 0x000, 0x117, CRC(054de7a3) SHA1(bb7abaec50ed704c03b44d5d54296898f7c80d38) )
	411	ROM_LOAD( "a-17721.u955", 0x200, 0x117, CRC(033fe902) SHA1(6efb4e519ed3c9d49fff046a679762b506b3a75b) )
	412	ROM_END
	413
	414
	415
350	416	/*************************************
351	417	*
352	418	* Game drivers
353	419	*
354	420	*************************************/
355	421
356		GAME( 1994, revx, 0, midxunit, revx, midxunit_state, revx, ROT0, "Midway", "Revolution X (Rev. 1.0 6/16/94)", MACHINE_SUPPORTS_SAVE )
	422	GAME( 1994, revx, 0, midxunit, revx, midxunit_state, revx, ROT0, "Midway", "Revolution X (rev 1.0 6/16/94)", MACHINE_SUPPORTS_SAVE )
	423	GAME( 1994, revxp5, revx, midxunit, revx, midxunit_state, revx, ROT0, "Midway", "Revolution X (prototype, rev 5.0 5/23/94)", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/minivadr.c
r249025	r249026
31	31	Z80 - Clock 4MHz [24/6]
32	32	6116 - 2Kbx8 SRAM
33	33	D26_01.IC7 - 27C64 8Kbx8 EPROM
34
	34
35	35	***************************************************************************/
36	36
37	37	#include "emu.h"

trunk/src/mame/drivers/namcos10.c
r249025	r249026
474	474	READ16_MEMBER(namcos10_state::i2c_clock_r)
475	475	{
476	476	UINT16 res = i2c_dev_clock & i2c_host_clock & 1;
477		// logerror("i2c_clock_r %d (%x)\n", res, space.device().safe_pc());
	477	// logerror("i2c_clock_r %d (%x)\n", res, space.device().safe_pc());
478	478	return res;
479	479	}
480	480
r249025	r249026
482	482	WRITE16_MEMBER(namcos10_state::i2c_clock_w)
483	483	{
484	484	COMBINE_DATA(&i2c_host_clock);
485		// logerror("i2c_clock_w %d (%x)\n", data, space.device().safe_pc());
	485	// logerror("i2c_clock_w %d (%x)\n", data, space.device().safe_pc());
486	486	i2c_update();
487	487	}
488	488
489	489	READ16_MEMBER(namcos10_state::i2c_data_r)
490	490	{
491	491	UINT16 res = i2c_dev_data & i2c_host_data & 1;
492		// logerror("i2c_data_r %d (%x)\n", res, space.device().safe_pc());
	492	// logerror("i2c_data_r %d (%x)\n", res, space.device().safe_pc());
493	493	return res;
494	494	}
495	495
r249025	r249026
497	497	WRITE16_MEMBER(namcos10_state::i2c_data_w)
498	498	{
499	499	COMBINE_DATA(&i2c_host_data);
500		// logerror("i2c_data_w %d (%x)\n", data, space.device().safe_pc());
	500	// logerror("i2c_data_w %d (%x)\n", data, space.device().safe_pc());
501	501	i2c_update();
502	502	}
503	503
r249025	r249026
524	524	i2cp_mode = I2CP_IDLE;
525	525	} else if(clock && !i2c_prev_clock) {
526	526	i2c_byte \|= (data << i2c_bit);
527		// logerror("i2c_byte = %02x (%d)\n", i2c_byte, i2c_bit);
	527	// logerror("i2c_byte = %02x (%d)\n", i2c_byte, i2c_bit);
528	528	i2c_bit--;
529	529	if(i2c_bit < 0) {
530	530	i2cp_mode = I2CP_RECIEVE_ACK_1;
r249025	r249026
536	536	break;
537	537	case I2CP_RECIEVE_ACK_1:
538	538	if(clock && !i2c_prev_clock) {
539		// logerror("i2c ack on\n");
	539	// logerror("i2c ack on\n");
540	540	i2cp_mode = I2CP_RECIEVE_ACK_0;
541	541	}
542	542	break;
543	543	case I2CP_RECIEVE_ACK_0:
544	544	if(!clock && i2c_prev_clock) {
545		// logerror("i2c ack off\n");
	545	// logerror("i2c ack off\n");
546	546	i2c_dev_data = 1;
547	547	data = i2c_host_data & 1;
548	548	i2c_byte = 0;
r249025	r249026
574	574	printf("crypto_switch_w: %04x\n", data);
575	575	if (decrypter == 0)
576	576	return;
577
	577
578	578	if (BIT(data, 15) != 0)
579	579	decrypter->activate(data & 0xf);
580	580	else
r249025	r249026
628	628
629	629	// logerror("read %08x = %04x\n", nand_address*2, data);
630	630	// printf("read %08x = %04x\n", nand_address*2, data);
631
632	631
	632
633	633	/* printf( "data<-%08x (%08x)\n", data, nand_address ); */
634	634	nand_address++;
635	635
636	636	if (decrypter == 0)
637	637	return data;
638
	638
639	639	if (decrypter->is_active())
640	640	return decrypter->decrypt(data);
641	641	else

trunk/src/mame/drivers/namcos12.c
r249025	r249026
1878	1878	PORT_BIT( 0x7eff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1879	1879
1880	1880	PORT_START("IN23")
1881		PORT_BIT(0x0800, IP_ACTIVE_LOW, IPT_COIN1 ) // coin switch
	1881	PORT_BIT(0x0800, IP_ACTIVE_LOW, IPT_COIN1 ) // coin switch
1882	1882	PORT_BIT(0xf7ff, IP_ACTIVE_LOW, IPT_UNKNOWN )
1883	1883
1884	1884	PORT_START("SERVICE")
r249025	r249026
3000	3000	GAME( 1998, ehrgeizja, ehrgeiz, coh700, namcos12, namcos12_state, namcos12, ROT0, "Square / Namco", "Ehrgeiz (Japan, EG1/VER.A)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND ) /* KC021 */
3001	3001	GAME( 1998, mdhorse, 0, coh700, namcos12, namcos12_state, namcos12, ROT0, "MOSS / Namco", "Derby Quiz My Dream Horse (Japan, MDH1/VER.A2)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) /* KC035 */
3002	3002	GAME( 1998, sws98, 0, coh700, namcos12, namcos12_state, namcos12, ROT0, "Namco", "Super World Stadium '98 (Japan, SS81/VER.A)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND ) /* KC0?? */
3003		GAME( 1998, technodr, 0, technodr, technodr, namcos12_state, namcos12, ROT0, "Namco", "Techno Drive (Japan, TD2/VER.B)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) /* KC056 */
	3003	GAME( 1998, technodr, 0, technodr, technodr, namcos12_state, namcos12, ROT0, "Namco", "Techno Drive (Japan, TD2/VER.B)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND \| MACHINE_NOT_WORKING ) /* KC056 */
3004	3004	GAME( 1998, tenkomor, 0, coh700, namcos12, namcos12_state, namcos12, ROT90,"Namco", "Tenkomori Shooting (Asia, TKM2/VER.A1)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND ) /* KC036 */
3005	3005	GAME( 1998, tenkomorja,tenkomor, coh700, namcos12, namcos12_state, namcos12, ROT90,"Namco", "Tenkomori Shooting (Japan, TKM1/VER.A1)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND ) /* KC036 */
3006	3006	GAME( 1998, fgtlayer, 0, coh700, namcos12, namcos12_state, namcos12, ROT0, "Arika / Namco", "Fighting Layer (Japan, FTL1/VER.A)", MACHINE_IMPERFECT_GRAPHICS \| MACHINE_IMPERFECT_SOUND ) /* KC037 */

trunk/src/mame/drivers/naomi.c
r249025	r249026
1001	1001	\|--------------------\|
1002	1002	Notes:
1003	1003	This is the I/O board used in Dynamic Golf, Out Trigger, Shootout Pool,
1004		Shootout Pool Prize, Kick'4'Cash, Crackin' DJ 1&2
	1004	Shootout Pool Prize, Kick'4'Cash, Crackin' DJ 1&2
1005	1005	for the trackballs and other rotary type game controls.
1006	1006	It must be daisy-chained to the normal I/O board with a USB cable.
1007	1007
r249025	r249026
5091	5091	NAOMI_BIOS
5092	5092	NAOMI_DEFAULT_EEPROM
5093	5093
5094		ROM_REGION( 0x10000, "io_board", 0)
	5094	ROM_REGION( 0x10000, "io_board", 0)
5095	5095	ROM_LOAD("epr-22084.ic3", 0x0000, 0x10000, CRC(18cf58bb) SHA1(1494f8215231929e41bbe2a133658d01882fbb0f) )
5096	5096
5097	5097	ROM_REGION( 0xa000000, "rom_board", ROMREGION_ERASEFF)

trunk/src/mame/drivers/norautp.c
r249025	r249026
3437	3437	*/
3438	3438
3439	3439	ROM_START( pkii_dm )
3440		ROM_REGION( 0x10000, "maincpu", 0 ) // no stack, call's RET go to PC=0
3441		ROM_LOAD( "12.u12", 0x0000, 0x1000, CRC(048e70d8) SHA1(f0eb16ba68455638de2ce68f51f305a13d0df287) )
3442		ROM_LOAD( "13.u18", 0x1000, 0x1000, CRC(06cf6789) SHA1(587d883c399348b518e3be4d1dc2581824055328) )
	3440	ROM_REGION( 0x10000, "maincpu", 0 ) // no stack, call's RET go to PC=0
	3441	ROM_LOAD( "12.u12", 0x0000, 0x1000, CRC(048e70d8) SHA1(f0eb16ba68455638de2ce68f51f305a13d0df287) )
	3442	ROM_LOAD( "13.u18", 0x1000, 0x1000, CRC(06cf6789) SHA1(587d883c399348b518e3be4d1dc2581824055328) )
3443	3443
3444		ROM_REGION( 0x1000, "gfx", 0 )
3445		ROM_FILL( 0x0000, 0x0800, 0xff )
3446		ROM_LOAD( "cgw-f506.u31", 0x0800, 0x0800, CRC(412fc492) SHA1(094ea0ffd0c22274cfe164f07c009ffe022331fd) )
	3444	ROM_REGION( 0x1000, "gfx", 0 )
	3445	ROM_FILL( 0x0000, 0x0800, 0xff )
	3446	ROM_LOAD( "cgw-f506.u31", 0x0800, 0x0800, CRC(412fc492) SHA1(094ea0ffd0c22274cfe164f07c009ffe022331fd) )
3447	3447
3448		ROM_REGION( 0x0200, "proms", 0 )
3449		ROM_LOAD( "63s141n.u51", 0x0000, 0x0100, CRC(88302127) SHA1(aed1273974917673405f1234ab64e6f8b3856c34) )
	3448	ROM_REGION( 0x0200, "proms", 0 )
	3449	ROM_LOAD( "63s141n.u51", 0x0000, 0x0100, CRC(88302127) SHA1(aed1273974917673405f1234ab64e6f8b3856c34) )
3450	3450	ROM_END
3451	3451
3452	3452

trunk/src/mame/drivers/pacman.c
r249025	r249026
6913	6913	GAME( 1981, maketrax, crush, pacmanp, maketrax, pacman_state, maketrax, ROT270, "Alpha Denshi Co. / Kural (Williams license)", "Make Trax (US set 1)", MACHINE_SUPPORTS_SAVE )
6914	6914	GAME( 1981, maketrxb, crush, pacmanp, maketrax, pacman_state, maketrax, ROT270, "Alpha Denshi Co. / Kural (Williams license)", "Make Trax (US set 2)", MACHINE_SUPPORTS_SAVE )
6915	6915	GAME( 1981, korosuke, crush, pacmanp, korosuke, pacman_state, korosuke, ROT90, "Alpha Denshi Co. / Kural Electric, Ltd.", "Korosuke Roller (Japan)", MACHINE_SUPPORTS_SAVE )
6916		GAME( 1981, crushrlf, crush, pacman, maketrax, driver_device, 0, ROT90, "bootleg", "Crush Roller (Famaresa PCB)", MACHINE_SUPPORTS_SAVE )
	6916	GAME( 1981, crushrlf, crush, pacman, maketrax, driver_device, 0, ROT90, "bootleg", "Crush Roller (Famaresa PCB)", MACHINE_SUPPORTS_SAVE )
6917	6917	GAME( 1981, crushbl, crush, pacman, maketrax, driver_device, 0, ROT90, "bootleg", "Crush Roller (bootleg set 1)", MACHINE_SUPPORTS_SAVE )
6918	6918	GAME( 1981, crushbl2, crush, pacmanp, mbrush, pacman_state, maketrax, ROT90, "bootleg", "Crush Roller (bootleg set 2)", MACHINE_SUPPORTS_SAVE )
6919	6919	GAME( 1981, crushbl3, crush, pacmanp, mbrush, pacman_state, maketrax, ROT90, "bootleg", "Crush Roller (bootleg set 3)", MACHINE_SUPPORTS_SAVE )

trunk/src/mame/drivers/quantum.c
r249025	r249026
334	334	/* AVG PROM */
335	335	ROM_REGION( 0x100, "user1", 0 )
336	336	ROM_LOAD( "136002-125.6h", 0x0000, 0x0100, BAD_DUMP CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
	337
	338	ROM_REGION( 0x200, "plds", 0 )
	339	ROM_LOAD( "137290-001.1b", 0x0000, 0x0117, CRC(938a4598) SHA1(e5b6ddb1b4bb5546d3a0da5d00ce7c57a9e8e769) ) // GAL16V8
337	340	ROM_END
338	341
339	342
r249025	r249026
352	355	/* AVG PROM */
353	356	ROM_REGION( 0x100, "user1", 0 )
354	357	ROM_LOAD( "136002-125.6h", 0x0000, 0x0100, BAD_DUMP CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
	358
	359	ROM_REGION( 0x200, "plds", 0 )
	360	ROM_LOAD( "137290-001.1b", 0x0000, 0x0117, CRC(938a4598) SHA1(e5b6ddb1b4bb5546d3a0da5d00ce7c57a9e8e769) ) // GAL16V8
355	361	ROM_END
356	362
357	363
r249025	r249026
370	376	/* AVG PROM */
371	377	ROM_REGION( 0x100, "user1", 0 )
372	378	ROM_LOAD( "136002-125.6h", 0x0000, 0x0100, BAD_DUMP CRC(5903af03) SHA1(24bc0366f394ad0ec486919212e38be0f08d0239) )
	379
	380	ROM_REGION( 0x200, "plds", 0 )
	381	ROM_LOAD( "137290-001.1b", 0x0000, 0x0117, CRC(938a4598) SHA1(e5b6ddb1b4bb5546d3a0da5d00ce7c57a9e8e769) ) // GAL16V8
373	382	ROM_END
374	383
375	384

trunk/src/mame/drivers/rollext.c
r249025	r249026
1	1	// license:BSD-3-Clause
2	2	// copyright-holders:Ville Linde
3	3	/*
4		Rolling Extreme
5		Gaelco, 1999
	4	Rolling Extreme
	5	Gaelco, 1999
6	6
7		PCB Layout
8		----------
	7	PCB Layout
	8	----------
9	9
10	10	REF.991015
11	11	\|--------------------------------------------------\|
r249025	r249026
39	39
40	40	/*
41	41
42		MP Interrupts:
	42	MP Interrupts:
43	43
44		External Interrupt 1: 0x4003ef78
45		External Interrupt 2: -
46		External Interrupt 3: 0x40041d30
47		Memory Fault: 0x40043ae8
	44	External Interrupt 1: 0x4003ef78
	45	External Interrupt 2: -
	46	External Interrupt 3: 0x40041d30
	47	Memory Fault: 0x40043ae8
48	48
49		PP0 Interrupts:
50		Task: 0x400010a0 / 0x400001a0
	49	PP0 Interrupts:
	50	Task: 0x400010a0 / 0x400001a0
51	51
52		PP1 Interrupts:
53		Task: 0x4004c6e8
	52	PP1 Interrupts:
	53	Task: 0x4004c6e8
54	54
55	55
56		Memory locations:
	56	Memory locations:
57	57
58		[0x00000084] PP0 busy flag?
59		[0x00000090] PP0 fifo write pointer?
60		[0x00000094] PP0 fifo read pointer?
61		[0x00000320] 2000000-TCOUNT in XINT3 handler
62		[0x01010668] copied from (word)0xb0000004 in XINT3 handler
	58	[0x00000084] PP0 busy flag?
	59	[0x00000090] PP0 fifo write pointer?
	60	[0x00000094] PP0 fifo read pointer?
	61	[0x00000320] 2000000-TCOUNT in XINT3 handler
	62	[0x01010668] copied from (word)0xb0000004 in XINT3 handler
63	63
64	64
65		Texture ROM decode:
	65	Texture ROM decode:
66	66
67		{ic45} {ic47} {ic58} {ic60}
68		[2,0][0,0] [2,1][0,1] [3,0][1,0] [3,1][1,1]
	67	{ic45} {ic47} {ic58} {ic60}
	68	[2,0][0,0] [2,1][0,1] [3,0][1,0] [3,1][1,1]
69	69
70	70	*/
71	71
r249025	r249026
231	231	y[j] = (int)((u2f(iy) / 2.0f) + 192.0f);
232	232	}
233	233
234
	234
235	235	draw_line(bitmap, cliprect, x[0], y[0], x[1], y[1]);
236	236	draw_line(bitmap, cliprect, x[1], y[1], x[2], y[2]);
237	237	draw_line(bitmap, cliprect, x[3], y[3], x[2], y[2]);
238	238	draw_line(bitmap, cliprect, x[0], y[0], x[3], y[3]);
239
	239
240	240	}
241	241
242	242	m_disp_ram[0xffffc/4] = 0;
r249025	r249026
250	250	{
251	251	switch (offset)
252	252	{
253		case 0: // ??
	253	case 0: // ??
254	254	{
255	255	UINT32 data = 0x20200;
256	256
r249025	r249026
276	276	{
277	277	switch (offset)
278	278	{
279		case 0: // ??
	279	case 0: // ??
280	280	return 0xffff;
281		case 1: // ??
	281	case 1: // ??
282	282	return 0;
283	283	}
284	284
r249025	r249026
290	290	static ADDRESS_MAP_START(memmap, AS_PROGRAM, 32, rollext_state)
291	291	AM_RANGE(0x40000000, 0x40ffffff) AM_RAM AM_SHARE("main_ram")
292	292	AM_RANGE(0x60000000, 0x600fffff) AM_RAM AM_SHARE("disp_ram")
293		AM_RANGE(0x80000000, 0x8000ffff) AM_RAM AM_SHARE("palette_ram")
294		AM_RANGE(0x90000000, 0x9007ffff) AM_RAM AM_SHARE("texture_mask")
	293	AM_RANGE(0x80000000, 0x8000ffff) AM_RAM AM_SHARE("palette_ram")
	294	AM_RANGE(0x90000000, 0x9007ffff) AM_RAM AM_SHARE("texture_mask")
295	295	AM_RANGE(0xa0000000, 0xa00000ff) AM_READWRITE(a0000000_r, a0000000_w)
296	296	AM_RANGE(0xb0000000, 0xb0000007) AM_READ(b0000000_r)
297	297	AM_RANGE(0xc0000000, 0xc03fffff) AM_ROM AM_REGION("rom1", 0)
r249025	r249026
355	355	ROM_REGION32_BE(0x400000, "rom1", 0)
356	356	ROM_LOAD32_DWORD("roe.ic38", 0x000000, 0x400000, CRC(d9bcfb7c) SHA1(eda9870881732d4dc7cdacb65c6d40af3451dc9d))
357	357
358		ROM_REGION32_BE(0x2000000, "texture", 0) // Texture ROMs
	358	ROM_REGION32_BE(0x2000000, "texture", 0) // Texture ROMs
359	359	ROM_LOAD32_BYTE("roe.ic45", 0x000000, 0x800000, CRC(0f7fe365) SHA1(ed50fd2b76840eac6ce394a0c748109f615b775a))
360	360	ROM_LOAD32_BYTE("roe.ic47", 0x000001, 0x800000, CRC(44d7ccee) SHA1(2fec682396e4cca704bd1237016acec0e7b4b428))
361	361	ROM_LOAD32_BYTE("roe.ic58", 0x000002, 0x800000, CRC(67ad4561) SHA1(56f41b4ebd827fec49902f377c5ed054c02d9e6c))
r249025	r249026
363	363	ROM_END
364	364
365	365
366		GAME( 1999, rollext, 0, rollext, rollext, rollext_state, rollext, ROT0, "Gaelco", "ROLLing eX.tre.me", MACHINE_NOT_WORKING \| MACHINE_NO_SOUND )
		No newline at end of file
	366	GAME( 1999, rollext, 0, rollext, rollext, rollext_state, rollext, ROT0, "Gaelco", "ROLLing eX.tre.me", MACHINE_NOT_WORKING \| MACHINE_NO_SOUND )

trunk/src/mame/drivers/royalmah.c
r249025	r249026
3612	3612	ROM_LOAD( "s2.bin", 0x14000, 0x4000, CRC(fed42e7c) SHA1(31136dff07bd1883dc2d107823ba83a34abf003d) )
3613	3613
3614	3614	ROM_REGION( 0x0020, "proms", 0 )
3615		ROM_LOAD( "18s030n.6k", 0x0000, 0x0020, ~~NO_DUMP~~ )
	3615	ROM_LOAD( "18s030n.6k", 0x0000, 0x0020, CRC(c074c0f0) SHA1(b62519d1496ea366b0ea8ed657bd758ce93875ec) )
3616	3616	ROM_END
3617	3617
3618	3618	ROM_START( janputer )
r249025	r249026
4910	4910	GAME( 1981?, openmj, royalmj, royalmah, royalmah, driver_device, 0, ROT0, "Sapporo Mechanic", "Open Mahjong [BET] (Japan)", 0 )
4911	4911	GAME( 1982, royalmah, royalmj, royalmah, royalmah, driver_device, 0, ROT0, "bootleg", "Royal Mahjong (Falcon bootleg, v1.01)", 0 )
4912	4912	GAME( 1983, janyoup2, royalmj, ippatsu, janyoup2, driver_device, 0, ROT0, "Cosmo Denshi", "Janyou Part II (ver 7.03, July 1 1983)",0 )
4913		GAME( 1985, tahjong, royalmj, tahjong, tahjong, driver_device, 0, ROT0, "Bally Pond / Nasco", "Tahjong Yakitori (ver. 2-1)", ~~MACHINE_WRONG_COLORS~~ ) // 1985 Jun. 17
	4913	GAME( 1985, tahjong, royalmj, tahjong, tahjong, driver_device, 0, ROT0, "Bally Pond / Nasco", "Tahjong Yakitori (ver. 2-1)", 0 ) // 1985 Jun. 17
4914	4914	GAME( 1981, janputer, 0, royalmah, royalmah, driver_device, 0, ROT0, "bootleg (Public Software Ltd. / Mes)", "New Double Bet Mahjong (bootleg of Janputer)", 0 ) // the original Janputer (Sanritsu) is not yet dumped
4915	4915	GAME( 1984, janoh, 0, royalmah, royalmah, driver_device, 0, ROT0, "Toaplan", "Jan Oh (set 1)", MACHINE_NOT_WORKING )
4916	4916	GAME( 1984, janoha, janoh, janoh, royalmah, driver_device, 0, ROT0, "Toaplan", "Jan Oh (set 2)", MACHINE_NOT_WORKING ) // this one is complete?

trunk/src/mame/drivers/seattle.c
r249025	r249026
2756	2756	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version L1.2 (10/8/96) */
2757	2757	ROM_LOAD( "wg3dh_12.u32", 0x000000, 0x80000, CRC(15e4cea2) SHA1(72c0db7dc53ce645ba27a5311b5ce803ad39f131) )
2758	2758
2759		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2759	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2760	2760
2761	2761	DISK_REGION( "ide:0:hdd:image" ) /* Hard Drive Version 1.3 (Guts 10/15/96, Main 10/15/96) */
2762	2762	DISK_IMAGE( "wg3dh", 0, SHA1(4fc6f25d7f043d9bcf8743aa8df1d9be3cbc375b) )
r249025	r249026
2770	2770	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.0ce 7/2/97 */
2771	2771	ROM_LOAD( "mace10ce.u32", 0x000000, 0x80000, CRC(7a50b37e) SHA1(33788835f84a9443566c80bee9f20a1691490c6d) )
2772	2772
2773		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2773	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2774	2774
2775	2775	DISK_REGION( "ide:0:hdd:image" ) /* Hard Drive Version 1.0B 6/10/97 (Guts 7/2/97, Main 7/2/97) */
2776	2776	DISK_IMAGE( "mace", 0, SHA1(96ec8d3ff5dd894e21aa81403bcdbeba44bb97ea) )
r249025	r249026
2784	2784	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version ??? 5/7/97 */
2785	2785	ROM_LOAD( "maceboot.u32", 0x000000, 0x80000, CRC(effe3ebc) SHA1(7af3ca3580d6276ffa7ab8b4c57274e15ee6bcbb) )
2786	2786
2787		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2787	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2788	2788
2789	2789	DISK_REGION( "ide:0:hdd:image" ) /* Hard Drive Version 1.0a (Guts 6/9/97, Main 5/12/97) */
2790	2790	DISK_IMAGE( "macea", 0, BAD_DUMP SHA1(9bd4a60627915d71932cab24f89c48ea21f4c1cb) )
r249025	r249026
2798	2798	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version L1.0 */
2799	2799	ROM_LOAD( "hdboot.u32", 0x000000, 0x80000, CRC(39a35f1b) SHA1(c46d83448399205d38e6e41dd56abbc362254254) )
2800	2800
2801		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2801	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2802	2802
2803	2803	ROM_REGION32_LE( 0x200000, "cageboot", 0 ) /* TMS320C31 boot ROM Version L1.0 */
2804	2804	ROM_LOAD32_BYTE( "sndboot.u69", 0x000000, 0x080000, CRC(7e52cdc7) SHA1(f735063e19d2ca672cef6d761a2a47df272e8c59) )
r249025	r249026
2818	2818	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code */
2819	2819	ROM_LOAD( "boot.bin", 0x000000, 0x080000, CRC(0555b3cf) SHA1(a48abd6d06a26f4f9b6c52d8c0af6095b6be57fd) )
2820	2820
2821		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2821	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2822	2822
2823	2823	ROM_REGION32_LE( 0x200000, "cageboot", 0 ) /* TMS320C31 boot ROM */
2824	2824	ROM_LOAD32_BYTE( "audboot.bin", 0x000000, 0x080000, CRC(c70c060d) SHA1(dd014bd13efdf5adc5450836bd4650351abefc46) )
r249025	r249026
2838	2838	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.2 (2/18/98) */
2839	2839	ROM_LOAD( "caspd1_2.u32", 0x000000, 0x80000, CRC(0a235e4e) SHA1(b352f10fad786260b58bd344b5002b6ea7aaf76d) )
2840	2840
2841		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2841	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2842	2842
2843	2843	DISK_REGION( "ide:0:hdd:image" ) /* Release version 2.1a (4/17/98) (Guts 1.25 4/17/98, Main 4/17/98) */
2844	2844	DISK_IMAGE( "calspeed", 0, SHA1(08d411c591d4b8bbdd6437ea80d01c4cec8516f8) )
r249025	r249026
2851	2851	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.2 (2/18/98) */
2852	2852	ROM_LOAD( "caspd1_2.u32", 0x000000, 0x80000, CRC(0a235e4e) SHA1(b352f10fad786260b58bd344b5002b6ea7aaf76d) )
2853	2853
2854		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2854	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2855	2855
2856	2856	DISK_REGION( "ide:0:hdd:image" ) /* Release version 1.0r8a (4/10/98) (Guts 4/10/98, Main 4/10/98) */
2857	2857	DISK_IMAGE( "cs_10r8a", 0, SHA1(ba4e7589740e0647938c81c5082bb71d8826bad4) )
r249025	r249026
2864	2864	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.2 (2/18/98) */
2865	2865	ROM_LOAD( "caspd1_2.u32", 0x000000, 0x80000, CRC(0a235e4e) SHA1(b352f10fad786260b58bd344b5002b6ea7aaf76d) )
2866	2866
2867		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2867	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2868	2868
2869	2869	DISK_REGION( "ide:0:hdd:image" ) /* Release version 1.0r7a (3/4/98) (Guts 3/3/98, Main 1/19/98) */
2870	2870	DISK_IMAGE( "calspeda", 0, SHA1(6b1c3a7530195ef7309b06a651b01c8b3ece92c6) )
r249025	r249026
2881	2881	ROM_REGION32_LE( 0x80000, "user1", 0 )
2882	2882	ROM_LOAD( "vtrxboot.bin", 0x000000, 0x80000, CRC(ee487a6c) SHA1(fb9efda85047cf615f24f7276a9af9fd542f3354) )
2883	2883
2884		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2884	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2885	2885
2886	2886	DISK_REGION( "ide:0:hdd:image" )
2887	2887	DISK_IMAGE( "vaportrx", 0, SHA1(fe53ca7643d2ed2745086abb7f2243c69678cab1) )
r249025	r249026
2895	2895	ROM_REGION32_LE( 0x80000, "user1", 0 )
2896	2896	ROM_LOAD( "vtrxboot.bin", 0x000000, 0x80000, CRC(ee487a6c) SHA1(fb9efda85047cf615f24f7276a9af9fd542f3354) )
2897	2897
2898		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2898	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2899	2899
2900	2900	DISK_REGION( "ide:0:hdd:image" ) /* Guts: Apr 10 1998 11:03:14 Main: Apr 10 1998 11:27:44 */
2901	2901	DISK_IMAGE( "vaportrp", 0, SHA1(6c86637c442ebd6994eee8c0ae0dce343c35dbe9) )
r249025	r249026
2909	2909	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
2910	2910	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
2911	2911
2912		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2912	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2913	2913
2914	2914	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Seattle System Boot ROM Version 0.1i Apr 14 1997 14:52:53 */
2915	2915	ROM_LOAD( "biofreak.u32", 0x000000, 0x80000, CRC(cefa00bb) SHA1(7e171610ede1e8a448fb8d175f9cb9e7d549de28) )
r249025	r249026
2923	2923	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
2924	2924	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
2925	2925
2926		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2926	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2927	2927
2928	2928	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.2 */
2929	2929	ROM_LOAD( "blitz1_2.u32", 0x000000, 0x80000, CRC(38dbecf5) SHA1(7dd5a5b3baf83a7f8f877ff4cd3f5e8b5201b36f) )
r249025	r249026
2937	2937	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
2938	2938	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
2939	2939
2940		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2940	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2941	2941
2942	2942	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.1 */
2943	2943	ROM_LOAD( "blitz1_1.u32", 0x000000, 0x80000, CRC(8163ce02) SHA1(89b432d8879052f6c5534ee49599f667f50a010f) )
r249025	r249026
2951	2951	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
2952	2952	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
2953	2953
2954		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2954	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2955	2955
2956	2956	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.0 */
2957	2957	ROM_LOAD( "bltz9910.u32", 0x000000, 0x80000, CRC(777119b2) SHA1(40d255181c2f3a787919c339e83593fd506779a5) )
r249025	r249026
2970	2970	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF ) // to use this rom run with -bios up130 and go into TEST mode to update.
2971	2971	ROM_SYSTEM_BIOS( 0, "noupdate", "No Update Rom" )
2972	2972	ROM_SYSTEM_BIOS( 1, "up130", "Update to 1.30" )
2973		ROMX_LOAD( "rev.-1.3.u33", 0x000000, 0x100000, CRC(0a0fde5a) SHA1(1edb671c66819f634a9f1daa35331a99b2bda01a), ROM_BIOS(2) )
	2973	ROMX_LOAD( "rev.-1.3.u33", 0x000000, 0x100000, CRC(0a0fde5a) SHA1(1edb671c66819f634a9f1daa35331a99b2bda01a), ROM_BIOS(2) )
2974	2974
2975	2975	DISK_REGION( "ide:0:hdd:image" ) /* Hard Drive Version 1.30 */
2976	2976	DISK_IMAGE( "blitz99a", 0, SHA1(43f834727ce01d7a63b482fc28cbf292477fc6f2) )
r249025	r249026
2981	2981	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
2982	2982	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
2983	2983
2984		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2984	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2985	2985
2986	2986	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Code Version 1.4 */
2987	2987	ROM_LOAD( "bltz2k14.u32", 0x000000, 0x80000, CRC(ac4f0051) SHA1(b8125c17370db7bfd9b783230b4ef3d5b22a2025) )
r249025	r249026
2995	2995	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
2996	2996	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
2997	2997
2998		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	2998	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2999	2999
3000	3000	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Rom Version 1.9 */
3001	3001	ROM_LOAD( "carnevil1_9.u32", 0x000000, 0x80000, CRC(82c07f2e) SHA1(fa51c58022ce251c53bad12fc6ffadb35adb8162) )
r249025	r249026
3009	3009	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
3010	3010	ROM_LOAD16_BYTE( "sound102.u95", 0x000000, 0x8000, CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
3011	3011
3012		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	3012	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
3013	3013
3014	3014	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Rom Version 1.9 */
3015	3015	ROM_LOAD( "carnevil1_9.u32", 0x000000, 0x80000, CRC(82c07f2e) SHA1(fa51c58022ce251c53bad12fc6ffadb35adb8162) )
r249025	r249026
3023	3023	ROM_REGION16_LE( 0x10000, "dcs", 0 ) /* ADSP-2115 data Version 1.02 */
3024	3024	ROM_LOAD16_BYTE( "seattle.snd", 0x000000, 0x8000, BAD_DUMP CRC(bec7d3ae) SHA1(db80aa4a645804a4574b07b9f34dec6b6b64190d) )
3025	3025
3026		ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
	3026	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
3027	3027
3028	3028	ROM_REGION32_LE( 0x80000, "user1", 0 ) /* Boot Rom Version 9. */
3029	3029	ROM_LOAD( "hyprdrve.u32", 0x000000, 0x80000, CRC(3e18cb80) SHA1(b18cc4253090ee1d65d72a7ec0c426ed08c4f238) )

trunk/src/mame/drivers/simpsons.c
r249025	r249026
346	346	MCFG_SCREEN_ADD("screen", RASTER)
347	347	MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/3, 528, 112, 400, 256, 16, 240)
348	348	// 6MHz dotclock is more realistic, however needs drawing updates. replace when ready
349		// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
	349	// MCFG_SCREEN_RAW_PARAMS(XTAL_24MHz/4, 396, hbend, hbstart, 256, 16, 240)
350	350	MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_AFTER_VBLANK)
351	351	MCFG_SCREEN_UPDATE_DRIVER(simpsons_state, screen_update_simpsons)
352	352	MCFG_SCREEN_PALETTE("palette")

trunk/src/mame/drivers/spcforce.c
r249025	r249026
272	272
273	273	INTERRUPT_GEN_MEMBER(spcforce_state::vblank_irq)
274	274	{
275
276	275	if(m_irq_mask)
277	276	device.execute().set_input_line(3, HOLD_LINE);
278	277	}

trunk/src/mame/drivers/thedealr.c
r249025	r249026
10	10	P0-040A PCB:
11	11
12	12	R65C02P2 x 2
13		X0-009 (Intel 8742 MCU?)
	13	X0-009 (Intel 8742 MCU)
14	14
15	15	X1-001
16	16	X1-002
r249025	r249026
110	110
111	111	/***************************************************************************
112	112
113		IOX (i8742 MCU?) Simulation
	113	IOX (i8742 MCU) Simulation
114	114
115	115	***************************************************************************/
116	116
r249025	r249026
574	574	ROM_REGION( 0x10000, "subcpu", 0 )
575	575	ROM_LOAD( "xb3_002", 0x00000, 0x10000, CRC(53a37fa4) SHA1(2adfea2dd08f298cda885bc72606d03f8af886a0) )
576	576
	577	// To do: hook up
	578	ROM_REGION( 0x0800, "iocpu", 0 )
	579	ROM_LOAD( "x0-009", 0x0000, 0x0800, CRC(e8b86d5a) SHA1(ad12e8f4411c30cd691792c6b0b3429db786d8b5) )
	580
577	581	ROM_REGION( 0x100000, "gfx1", 0 )
578	582	ROM_LOAD( "xb0-002-w45.u42", 0x00000, 0x80000, CRC(41ec6a57) SHA1(d3f0508d5f4054fd2b0ee5227325a95fd1272aad) )
579	583	ROM_LOAD( "xb0-001-w44.u41", 0x80000, 0x80000, CRC(bdaca555) SHA1(5ae1dc1514993fd804a101182735d5fb6815f720) )

trunk/src/mame/drivers/toaplan2.c
r249025	r249026
1897	1897	PORT_CONFSETTING( 0x0040, DEF_STR( Hong_Kong ) )
1898	1898	PORT_CONFSETTING( 0x0050, DEF_STR( Taiwan ) )
1899	1899	PORT_CONFSETTING( 0x0060, DEF_STR( Southeast_Asia ) )
1900		PORT_CONFSETTING( 0x0070, DEF_STR( Unused ) )
1901		PORT_CONFSETTING( 0x0080, DEF_STR( Japan ) ) // no Taito license
	1900	PORT_CONFSETTING( 0x0070, DEF_STR( Unused ) )
	1901	PORT_CONFSETTING( 0x0080, DEF_STR( Japan ) ) // no Taito license
1902	1902	PORT_CONFSETTING( 0x0090, DEF_STR( Unused ) )
1903	1903	PORT_CONFSETTING( 0x00a0, DEF_STR( Unused ) )
1904		PORT_CONFSETTING( 0x00b0, DEF_STR( Korea ) )
1905		PORT_CONFSETTING( 0x00c0, DEF_STR( Hong_Kong ))
1906		PORT_CONFSETTING( 0x00d0, DEF_STR( Taiwan ))
1907		PORT_CONFSETTING( 0x00e0, DEF_STR( Southeast_Asia ))
1908		PORT_CONFSETTING( 0x00f0, DEF_STR( Unused ) )
	1904	PORT_CONFSETTING( 0x00b0, DEF_STR( Korea ) )
	1905	PORT_CONFSETTING( 0x00c0, DEF_STR( Hong_Kong ))
	1906	PORT_CONFSETTING( 0x00d0, DEF_STR( Taiwan ))
	1907	PORT_CONFSETTING( 0x00e0, DEF_STR( Southeast_Asia ))
	1908	PORT_CONFSETTING( 0x00f0, DEF_STR( Unused ) )
1909	1909	INPUT_PORTS_END
1910	1910
1911	1911	static INPUT_PORTS_START( kbash2 )

trunk/src/mame/drivers/vegas.c
r249025	r249026
2454	2454	*
2455	2455	*************************************/
2456	2456
2457		// there is a socket next to the main bios roms for updates, this is what the update region is.
	2457	// there is a socket next to the main bios roms for updates, this is what the update region is.
2458	2458
2459	2459
2460	2460	ROM_START( gauntleg )
r249025	r249026
2475	2475	ROM_REGION32_LE( 0x80000, "user1", 0 )
2476	2476	ROM_LOAD( "legend13.bin", 0x000000, 0x80000, CRC(34674c5f) SHA1(92ec1779f3ab32944cbd953b6e1889503a57794b) ) // EPROM Boot code. Version: Sep 25 1998 18:34:43 / 1.3 Sep 25 1998 18:33:45
2477	2477	ROM_LOAD( "legend14.bin", 0x000000, 0x80000, CRC(66869402) SHA1(bf470e0b9198b80f8baf8b9432a7e1df8c7d18ca) ) // EPROM Boot code. Version: Oct 30 1998 17:48:21 / 1.4 Oct 30 1998 17:44:29
2478
	2478
2479	2479	ROM_REGION32_LE( 0x100000, "update", ROMREGION_ERASEFF )
2480	2480	ROM_SYSTEM_BIOS( 0, "noupdate", "No Update Rom" )
2481	2481
2482	2482	ROM_SYSTEM_BIOS( 1, "up16_1", "Disk Update 1.2 to 1.6 Step 1 of 3" )
2483		ROMX_LOAD("12to16.1.bin", 0x000000, 0x100000, CRC(253c6bf2) SHA1(5e129576afe2bc4c638242e010735655d269a747), ROM_BIOS(2))
	2483	ROMX_LOAD("12to16.1.bin", 0x000000, 0x100000, CRC(253c6bf2) SHA1(5e129576afe2bc4c638242e010735655d269a747), ROM_BIOS(2))
2484	2484	ROM_SYSTEM_BIOS( 2, "up16_2", "Disk Update 1.2 to 1.6 Step 2 of 3" )
2485		ROMX_LOAD("12to16.2.bin", 0x000000, 0x100000, CRC(15b1fe78) SHA1(532c4937b55befcc3a8cb25b0282d63e206fba47), ROM_BIOS(3))
	2485	ROMX_LOAD("12to16.2.bin", 0x000000, 0x100000, CRC(15b1fe78) SHA1(532c4937b55befcc3a8cb25b0282d63e206fba47), ROM_BIOS(3))
2486	2486	ROM_SYSTEM_BIOS( 3, "up16_3", "Disk Update 1.2 to 1.6 Step 3 of 3" )
2487		ROMX_LOAD("12to16.3.bin", 0x000000, 0x100000, CRC(1027e54f) SHA1(a841f5cc5b022ddfaf70c97a64d1582f0a2ca70e), ROM_BIOS(4))
	2487	ROMX_LOAD("12to16.3.bin", 0x000000, 0x100000, CRC(1027e54f) SHA1(a841f5cc5b022ddfaf70c97a64d1582f0a2ca70e), ROM_BIOS(4))
2488	2488
2489	2489
2490	2490

trunk/src/mame/drivers/xyonix.c
r249025	r249026
274	274	/* GAME drivers **************************************************************/
275	275
276	276	GAME( 1989, xyonix, 0, xyonix, xyonix, driver_device, 0, ROT0, "Philko", "Xyonix", MACHINE_SUPPORTS_SAVE )
277

trunk/src/mame/includes/chihiro.h
r249025	r249026
185	185	memset(pfifo, 0, sizeof(pfifo));
186	186	memset(pcrtc, 0, sizeof(pcrtc));
187	187	memset(pmc, 0, sizeof(pmc));
	188	memset(pgraph, 0, sizeof(pgraph));
188	189	memset(ramin, 0, sizeof(ramin));
189	190	computedilated();
190	191	objectdata = &(object_data_alloc());
r249025	r249026
194	195	enabled_vertex_attributes = 0;
195	196	indexesleft_count = 0;
196	197	vertex_pipeline = 4;
	198	color_mask = 0xffffffff;
197	199	alpha_test_enabled = false;
198	200	alpha_reference = 0;
199	201	alpha_func = nv2a_renderer::ALWAYS;
r249025	r249026
238	240	}
239	241	DECLARE_READ32_MEMBER(geforce_r);
240	242	DECLARE_WRITE32_MEMBER(geforce_w);
241		bool vblank_callback(screen_device &screen, bool state);
	243	void vblank_callback(screen_device &screen, bool state);
242	244	UINT32 screen_update_callback(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
	245	bool update_interrupts();
	246	void set_interrupt_device(pic8259_device *device);
243	247
244	248	void render_texture_simple(INT32 scanline, const extent_t &extent, const nvidia_object_data &extradata, int threadid);
245	249	void render_color(INT32 scanline, const extent_t &extent, const nvidia_object_data &extradata, int threadid);
r249025	r249026
303	307	UINT32 pfifo[0x2000 / 4];
304	308	UINT32 pcrtc[0x1000 / 4];
305	309	UINT32 pmc[0x1000 / 4];
	310	UINT32 pgraph[0x2000 / 4];
306	311	UINT32 ramin[0x100000 / 4];
307	312	UINT32 dma_offset[2];
308	313	UINT32 dma_size[2];
309	314	UINT8 *basemempointer;
	315	pic8259_device *interruptdevice;
310	316	rectangle limits_rendertarget;
311	317	UINT32 pitch_rendertarget;
312	318	UINT32 pitch_depthbuffer;
r249025	r249026
441	447	int used;
442	448	osd_lock *lock;
443	449	} combiner;
	450	UINT32 color_mask;
444	451	bool alpha_test_enabled;
445	452	int alpha_func;
446	453	int alpha_reference;

trunk/src/mame/includes/gaelco2.h
r249025	r249026
107	107	DECLARE_WRITE16_MEMBER(wrally2_adc_cs);
108	108	DECLARE_CUSTOM_INPUT_MEMBER(wrally2_analog_bit_r);
109	109	};
110

trunk/src/mame/includes/hng64.h
r249025	r249026
125	125	m_com_ram(*this, "com_ram"),
126	126	m_gfxdecode(*this, "gfxdecode"),
127	127	m_screen(*this, "screen"),
128		m_palette(*this, "palette") { }
	128	m_palette(*this, "palette") { }
129	129
130	130	required_device<mips3_device> m_maincpu;
131	131	required_device<v53a_device> m_audiocpu;

trunk/src/mame/includes/rocnrope.h
r249025	r249026
27	27
28	28	tilemap_t *m_bg_tilemap;
29	29	UINT8 m_irq_mask;
30
	30
31	31	DECLARE_WRITE8_MEMBER(rocnrope_interrupt_vector_w);
32	32	DECLARE_WRITE8_MEMBER(irq_mask_w);
33	33	DECLARE_WRITE8_MEMBER(rocnrope_videoram_w);

trunk/src/mame/includes/xbox.h
r249025	r249026
318	318
319	319	ADDRESS_MAP_EXTERN(xbox_base_map, 32);
320	320	ADDRESS_MAP_EXTERN(xbox_base_map_io, 32);
321		MACHINE_CONFIG_EXTERN(xbox_base);
		No newline at end of file
	321	MACHINE_CONFIG_EXTERN(xbox_base);

trunk/src/mame/layout/aquastge.lay
r249025	r249026
1	1	<?xml version="1.0"?>
2	2	<mamelayout version="2">
3
	3
4	4	<!-- exact ratio unknown, could be wider -->
5	5	<view name="Dual Wide Screens">
6	6	<screen index="0">

trunk/src/mame/layout/chexx.lay
r0	r249026
	1	<?xml version="1.0"?>
	2	<mamelayout version="2">
	3
	4	<!-- 7segs -->
	5	<element name="digit">
	6	<led7seg>
	7	<color red="1.0" green="0.0" blue="0.0"/>
	8	</led7seg>
	9	</element>
	10
	11	<!-- Led -->
	12	<element name="led" defstate="0">
	13	<rect>
	14	<bounds x="0" y="0" width="1.5" height="1.0"/>
	15	<color red="1.0" green="0.96" blue="0.94"/>
	16	</rect>
	17	<rect state="0">
	18	<bounds x="0.05" y="0.05" width="1.4" height="0.9"/>
	19	<color red="0.5" green="0.0" blue="0.0"/>
	20	</rect>
	21	<rect state="1">
	22	<bounds x="0.05" y="0.05" width="1.4" height="0.9"/>
	23	<color red="1.0" green="0.0" blue="0.0"/>
	24	</rect>
	25	</element>
	26
	27	<!-- Lamp -->
	28	<element name="lamp" defstate="0">
	29	<disk state="0">
	30	<color red="0.2" green="0.0" blue="0.0"/>
	31	</disk>
	32	<disk state="1">
	33	<color red="1.0" green="0.0" blue="0.0"/>
	34	</disk>
	35	</element>
	36
	37	<view name="Score Board (No Artwork)">
	38	<!-- P1 score -->
	39	<backdrop name="digit0" element="digit">
	40	<bounds x="0" y="0" width="1" height="2"/>
	41	</backdrop>
	42	<backdrop name="digit1" element="digit">
	43	<bounds x="1" y="0" width="1" height="2"/>
	44	</backdrop>
	45
	46	<!-- P1 goal lamp -->
	47	<backdrop name="lamp0" element="lamp">
	48	<bounds x="0.75" y="-0.5" width="0.5" height="0.5"/>
	49	</backdrop>
	50
	51	<!-- Period being played -->
	52	<backdrop name="led0" element="led">
	53	<bounds x="3.0" y="-0.33" width="0.5" height="0.33"/>
	54	</backdrop>
	55	<backdrop name="led1" element="led">
	56	<bounds x="3.5" y="-0.33" width="0.5" height="0.33"/>
	57	</backdrop>
	58	<backdrop name="led2" element="led">
	59	<bounds x="4.0" y="-0.33" width="0.5" height="0.33"/>
	60	</backdrop>
	61
	62	<!-- P2 score -->
	63	<backdrop name="digit2" element="digit">
	64	<bounds x="5.5" y="0" width="1" height="2"/>
	65	</backdrop>
	66	<backdrop name="digit3" element="digit">
	67	<bounds x="6.5" y="0" width="1" height="2"/>
	68	</backdrop>
	69
	70	<!-- P2 goal lamp -->
	71	<backdrop name="lamp1" element="lamp">
	72	<bounds x="6.25" y="-0.5" width="0.5" height="0.5"/>
	73	</backdrop>
	74	</view>
	75	</mamelayout>

trunk/src/mame/machine/dc-ctrl.c
r249025	r249026
119	119	port[i] = ioport(port_tag[i]);
120	120	}
121	121	}
122

trunk/src/mame/machine/iteagle_fpga.c
r249025	r249026
146	146	m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) \| ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
147	147	}
148	148	if (0 && LOG_FPGA)
149		logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X other %02X%02X%02X\n", machine().describe_context(),
	149	logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X other %02X%02X%02X\n", machine().describe_context(),
150	150	data, m_seq, m_fpga_regs[offset]&0xff, m_seq_rem2, m_seq_rem1, val1);
151	151	}
152	152
r249025	r249026
731	731	{
732	732	UINT32 result = m_ide->read_cs0(space, offset, mem_mask);
733	733	if (offset==0x4/4 && ACCESSING_BITS_24_31) {
734		if (m_irq_num!=-1 && m_irq_status==1) {
	734	if (m_irq_num!=-1 && m_irq_status==1) {
735	735	m_irq_status = 0;
736	736	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
737	737	if (LOG_IDE)
r249025	r249026
746	746	{
747	747	m_ide->write_cs0(space, offset, data, mem_mask);
748	748	if (offset==0x4/4 && ACCESSING_BITS_24_31) {
749		if (m_irq_num!=-1 && m_irq_status==1) {
	749	if (m_irq_num!=-1 && m_irq_status==1) {
750	750	m_irq_status = 0;
751	751	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
752	752	if (LOG_IDE)
r249025	r249026
783	783	{
784	784	UINT32 result = m_ide2->read_cs0(space, offset, mem_mask);
785	785	if (offset==0x4/4 && ACCESSING_BITS_24_31) {
786		if (m_irq_num!=-1 && m_irq_status==1) {
	786	if (m_irq_num!=-1 && m_irq_status==1) {
787	787	m_irq_status = 0;
788	788	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
789	789	if (LOG_IDE_CTRL)
r249025	r249026
798	798	{
799	799	m_ide2->write_cs0(space, offset, data, mem_mask);
800	800	if (offset==0x4/4 && ACCESSING_BITS_24_31) {
801		if (m_irq_num!=-1 && m_irq_status==1) {
	801	if (m_irq_num!=-1 && m_irq_status==1) {
802	802	m_irq_status = 0;
803	803	m_cpu->set_input_line(m_irq_num, CLEAR_LINE);
804	804	if (LOG_IDE_CTRL)

trunk/src/mame/machine/ns10crypt.c
r249025	r249026
8	8
9	9	The decryption used by type-2 System10 PCBs (MEM-N) acts on 16-bit words and is
10	10	designed to operate in a serial way: once the decryption is triggered, every
11		word is XORed with a mask calculated over data taken from the previous words
	11	word is XORed with a mask calculated over data taken from the previous words
12	12	(both encrypted and decrypted). Type-1 PCBs seem to use a similar
13	13	scheme, probably involving the word address too and a bitswap, but his relation
14	14	to what is described here needs further investigation.
r249025	r249026
17	17	game (8E), and it's always stored spanning an integer number of NAND blocks
18	18	(the K9F2808U0B is organized in blocks of 16 KiB, each containing 32 pages of
19	19	0x200 bytes). Usually the first part of the encrypted data is stored at about the end
20		of the ROM, with all the blocks in that area processed in reverse order (first the
	20	of the ROM, with all the blocks in that area processed in reverse order (first the
21	21	one nearest the end, then the second nearest, etc); the second part goes immediately
22		after it from a logic perspective, but it's, usually, physically located at the area
	22	after it from a logic perspective, but it's, usually, physically located at the area
23	23	starting at 0x28000 in the ROM. However, in at least a couple of games, there are
24	24	out-of-order blocks (details below). Games, after
25	25	some bootup code has been executed, will copy the encrypted content from
26	26	the NANDs to RAM, moment at which the decryption is triggered. Physical locations
27		of the encrypted programs in the first NAND, together with the RAM region where
	27	of the encrypted programs in the first NAND, together with the RAM region where
28	28	they are loaded, are summarized in the following table ( ' indicating processing
29	29	in reverse order of the constituting blocks) :
30	30
r249025	r249026
44	44
45	45	Both knpuzzle & gjspace present a NAND block which is out of order with respect
46	46	to the normal layout; besides, that block is physically located immediately before
47		the end-of-ROM region, in what maybe is an attempt to hinder the
	47	the end-of-ROM region, in what maybe is an attempt to hinder the
48	48	recognition/reconstruction of the encrypted data.
49	49
50	50	Most games do a single decryption run, so the process is only initialized once;
51	51	however, at least three of them (gamshara, mrdrilrg & panikuru) do reinitialize the
52		internal state of the decrypted several times. As of 2015-08-19, only gamshara shows signs
	52	internal state of the decrypted several times. As of 2015-08-19, only gamshara shows signs
53	53	of doing it by writing to the triggering register; how the others two are triggering the
54	54	reinitializations is still unclear. gamshara does a reinitialization every 5 NAND blocks
55	55	(16 times in total); mrdrilrg does the second one after 0x38000 bytes and then subsequent
r249025	r249026
60	60	calculated by using linear equations over GF(2) taking as input data the bits from
61	61	previously processed words; however, one nonlinear calculation is performed
62	62	per word processed, and that calculation typically affect just one bit (the only
63		known exception is mrdrilrg, where the same nonlinear terms are
64		affecting two of them). Till now, all the formulae seem to depend only on the
	63	known exception is mrdrilrg, where the same nonlinear terms are
	64	affecting two of them). Till now, all the formulae seem to depend only on the
65	65	previous 3 words, and the first mask after a (re-)initialization is always zero, so
66		chances are the mask bits are calculated one word in advance, having access to the
	66	chances are the mask bits are calculated one word in advance, having access to the
67	67	current encrypted and decrypted words plus two further words in each sequence, maybe stored
68	68	in 32 bits registers. All the nonlinear terms reverse-engineered till now are of the form
69	69	A x B, where A and B are linear formulae; thus, as everything else in the schema involves
r249025	r249026
104	104	A) The linear relations are creating lots of identities involving the bits
105	105	from the sequence; they could be exploited to simplify the equations (but
106	106	only when the implementation be stable, to avoid duplicating work).
107		B) It's possible that some of those calculations are being stored and then
	107	B) It's possible that some of those calculations are being stored and then
108	108	used as another input bits for subsequent masks. Determining that (supposed)
109	109	bits and factoring out them would simplify the expressions, in case they
110	110	really exist.
r249025	r249026
123	123
124	124	// this could perfectly be part of the per-game logic; by now, only gamshara seems to use it, so we keep it global
125	125	const int ns10_decrypter_device::initSbox[16] = {0,12,13,6,2,4,9,8,11,1,7,15,10,5,14,3};
126
	126
127	127	ns10_decrypter_device::ns10_decrypter_device(device_type type, const ns10_crypto_logic &logic, const machine_config &mconfig, const char tag, device_t owner, UINT32 clock)
128	128	: device_t(mconfig, type, "Namco System 10 Decrypter", tag, owner, clock, "ns10_crypto", __FILE__)
129	129	, _active(false)
r249025	r249026
155	155	_previous_cipherwords ^= cipherword;
156	156	_previous_plainwords <<= 16;
157	157	_previous_plainwords ^= plainword;
158
	158
159	159	_mask = 0;
160	160	for (int j = 15; j >= 0; --j)
161	161	{
r249025	r249026
220	220	// static UINT16 panikuru_nonlinear_calc(UINT64 previous_cipherwords, UINT64 previous_plainwords, const gf2_reducer& reducer)
221	221	// {
222	222	// return ((reducer.gf2_reduce(0x0000000088300281ull & previous_cipherwords) ^ reducer.gf2_reduce(0x0000000004600281ull & previous_plainwords))
223		// & (reducer.gf2_reduce(0x0000a13140090000ull & previous_cipherwords) ^ reducer.gf2_reduce(0x0000806240090000ull & previous_plainwords))) << 2;
	223	// & (reducer.gf2_reduce(0x0000a13140090000ull & previous_cipherwords) ^ reducer.gf2_reduce(0x0000806240090000ull & previous_plainwords))) << 2;
224	224	// }
225	225
226	226	static UINT16 chocovdr_nonlinear_calc(UINT64 previous_cipherwords, UINT64 previous_plainwords, const gf2_reducer& reducer)

trunk/src/mame/machine/ns10crypt.h
r249025	r249026
16	16	class ns10_decrypter_device : public device_t
17	17	{
18	18	public:
19		// this encodes the decryption logic, which varies per game
	19	// this encodes the decryption logic, which varies per game
20	20	// and is probably hard-coded into the CPLD
21	21	struct ns10_crypto_logic
22	22	{

trunk/src/mame/machine/pgmcrypt.c
r249025	r249026
1526	1526	}
1527	1527	}
1528	1528
	1529	static const UINT8 fruitpar_tab[0x100] = {
	1530	0xe9, 0x0b, 0x95, 0x7e, 0x0d, 0x7d, 0x5c, 0x1e, 0x81, 0x0e, 0xa6, 0xd4, 0x8e, 0x90, 0xd8, 0x54,
	1531	0x27, 0x65, 0x51, 0x08, 0x1c, 0xa0, 0x3b, 0x51, 0x83, 0x60, 0x93, 0x02, 0x64, 0x69, 0x77, 0x1a,
	1532	0xa4, 0x03, 0xb0, 0xc2, 0x34, 0x18, 0x80, 0x87, 0x7a, 0x88, 0xad, 0xd9, 0xff, 0xd0, 0xce, 0xc4,
	1533	0x5b, 0xdc, 0xd5, 0xed, 0x5e, 0x29, 0xdd, 0xcf, 0x80, 0x1f, 0x36, 0x38, 0x8b, 0xae, 0xae, 0xfe,
	1534	0x87, 0x27, 0x22, 0x07, 0xe6, 0x5d, 0x46, 0x79, 0xf1, 0xfc, 0xb1, 0x3d, 0x72, 0x29, 0x2c, 0xba,
	1535	0xa3, 0x5b, 0x3c, 0xcf, 0x57, 0x79, 0xed, 0x12, 0x67, 0x34, 0xe1, 0x48, 0x5f, 0xa7, 0x9a, 0x24,
	1536	0x6a, 0x2e, 0x04, 0x44, 0x7b, 0x84, 0x46, 0x6a, 0xbd, 0x20, 0xca, 0xf7, 0x3e, 0xd1, 0x8b, 0xad,
	1537	0xd7, 0x98, 0x9e, 0xa6, 0x5e, 0xc6, 0x04, 0x90, 0x0f, 0x57, 0xae, 0x2b, 0x38, 0x8d, 0xd2, 0x0c,
	1538	0x25, 0xd1, 0x6d, 0x73, 0x4b, 0xc6, 0x19, 0xd3, 0xb8, 0xae, 0x11, 0x01, 0xba, 0x02, 0x82, 0x17,
	1539	0xcf, 0x4d, 0x14, 0x6a, 0xcd, 0x4a, 0xb9, 0xc1, 0x52, 0x3e, 0xb5, 0xd8, 0x6f, 0x98, 0xee, 0x16,
	1540	0x90, 0xc6, 0x76, 0x8a, 0xaf, 0x5a, 0x56, 0x2b, 0xb9, 0x5e, 0x9e, 0x51, 0x40, 0xf4, 0xaa, 0x6e,
	1541	0x63, 0x32, 0xb6, 0x12, 0xfb, 0x3c, 0xa5, 0x1f, 0x07, 0xa3, 0x0d, 0x49, 0x5a, 0xfe, 0x88, 0xd1,
	1542	0x83, 0xc7, 0x37, 0x82, 0xfd, 0x78, 0x97, 0xec, 0x98, 0xe6, 0x88, 0xe0, 0x27, 0xde, 0x9a, 0x2c,
	1543	0x6b, 0xfd, 0x9b, 0x98, 0x40, 0xd5, 0x5f, 0x20, 0x06, 0x3e, 0xcf, 0x74, 0x52, 0xf9, 0x35, 0xae,
	1544	0xd6, 0x8c, 0xc7, 0x53, 0x8e, 0x59, 0x71, 0x8c, 0x2d, 0x00, 0xe7, 0xa5, 0xc7, 0xf8, 0xeb, 0xc7,
	1545	0xbf, 0x68, 0xdc, 0xf2, 0xf4, 0x4c, 0x80, 0x3e, 0x27, 0xc5, 0x13, 0x52, 0xb0, 0xc0, 0x90, 0x2d
	1546	};
	1547
1529	1548	void fruitpar_decrypt(running_machine &machine)
1530	1549	{
1531		// TODO
	1550	int i;
	1551	UINT16 src = (UINT16 ) machine.root_device().memregion("user1")->base();
	1552
	1553	int rom_size = 0x80000;
	1554
	1555	// not 100% verified
	1556	for(i=0; i<rom_size/2; i++)
	1557	{
	1558	UINT16 x = src[i];
	1559
	1560	IGS27_CRYPT1
	1561	// IGS27_CRYPT2
	1562	// IGS27_CRYPT3
	1563	IGS27_CRYPT4_ALT
	1564	IGS27_CRYPT5
	1565	IGS27_CRYPT6_ALT
	1566	IGS27_CRYPT7
	1567	IGS27_CRYPT8
	1568
	1569	x ^= fruitpar_tab[(i>> 1) & 0xff] << 8;
	1570
	1571	src[i] = x;
	1572	}
1532	1573	}

trunk/src/mame/machine/xbox.c
r249025	r249026
465	465
466	466	void xbox_base_state::vblank_callback(screen_device &screen, bool state)
467	467	{
468		if (nvidia_nv2a->vblank_callback(screen, state))
469		xbox_base_devs.pic8259_1->ir3_w(1); // IRQ 3
470		else
471		xbox_base_devs.pic8259_1->ir3_w(0); // IRQ 3
	468	nvidia_nv2a->vblank_callback(screen, state);
472	469	}
473	470
474	471	UINT32 xbox_base_state::screen_update_callback(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
r249025	r249026
1460	1457	if (machine().debug_flags & DEBUG_FLAG_ENABLED)
1461	1458	debug_console_register_command(machine(), "xbox", CMDFLAG_NONE, 0, 1, 4, xbox_debug_commands);
1462	1459	memset(&ohcist, 0, sizeof(ohcist));
	1460	// PIC challenge handshake data
	1461	pic16lc_buffer[0x1c] = 0x0c;
	1462	pic16lc_buffer[0x1d] = 0x0d;
	1463	pic16lc_buffer[0x1e] = 0x0e;
	1464	pic16lc_buffer[0x1f] = 0x0f;
1463	1465	#ifdef USB_ENABLED
1464	1466	ohcist.hc_regs[HcRevision] = 0x10;
1465	1467	ohcist.hc_regs[HcFmInterval] = 0x2edf;
r249025	r249026
1483	1485	save_item(NAME(smbusst.rw));
1484	1486	save_item(NAME(smbusst.words));
1485	1487	save_item(NAME(pic16lc_buffer));
	1488	nvidia_nv2a->set_interrupt_device(xbox_base_devs.pic8259_1);
1486	1489	nvidia_nv2a->start(&m_maincpu->space());
1487	1490	nvidia_nv2a->savestate_items();
1488	1491	}

trunk/src/mame/mess.lst
r249025	r249026
99	99	32xe
100	100	32xj
101	101	32x_scd // 1994 Sega Sega CD (USA w/32X addon)
102		segapm // 1996 Sega Picture Magic (32x type hardware)
	102	segapm // 1996 Sega Picture Magic (32x type hardware)
103	103
104	104	saturnjp // 1994 Sega Saturn (Japan)
105	105	saturn // 1995 Sega Saturn (USA)
r249025	r249026
2729	2729	tvgame
2730	2730	aussieby
2731	2731	hp_ipc
2732

trunk/src/mame/video/bottom9.c
r249025	r249026
34	34	*priority = 0;
35	35	if ( color & 0x10) priority \|= GFX_PMASK_1;
36	36	if (~color & 0x20) priority \|= GFX_PMASK_2;
37
	37
38	38	color = sprite_colorbase + (color & 0x0f);
39	39	}
40	40

trunk/src/mame/video/chihiro.c
r249025	r249026
3	3	#include "emu.h"
4	4	#include "video/poly.h"
5	5	#include "bitmap.h"
	6	#include "machine/pic8259.h"
6	7	#include "includes/chihiro.h"
7	8
8	9	//#define LOG_NV2A
r249025	r249026
945	946	UINT32 nv2a_renderer::geforce_object_offset(UINT32 handle)
946	947	{
947	948	UINT32 h = ((((handle >> 11) ^ handle) >> 11) ^ handle) & 0x7ff;
948		UINT32 o = (pfifo[0x210 / 4] & 0x1f) << 8; // or 12 ?
	949	UINT32 o = (pfifo[0x210 / 4] & 0x1ff) << 8; // 0x1ff is not certain
949	950	UINT32 e = o + h * 8; // at 0xfd000000+0x00700000
950	951	UINT32 w;
951	952
952		if (ramin[e / 4] != handle)
953		e = 0;
	953	if (ramin[e / 4] != handle) {
	954	// this should never happen
	955	for (UINT32 aa = o / 4; aa < (sizeof(ramin) / 4); aa = aa + 2) {
	956	if (ramin[aa] == handle) {
	957	e = aa * 4;
	958	}
	959	}
	960	}
954	961	w = ramin[e / 4 + 1];
955		return (w & 0xffff) * 0x10;
	962	return (w & 0xffff) * 0x10; // 0xffff is not certain
956	963	}
957	964
958	965	void nv2a_renderer::geforce_read_dma_object(UINT32 handle, UINT32 &offset, UINT32 &size)
r249025	r249026
1246	1253	addr = rendertarget + (dilated0[dilate_rendertarget][x] + dilated1[dilate_rendertarget][y]);
1247	1254	else // type_rendertarget == LINEAR*/
1248	1255	addr = rendertarget + (pitch_rendertarget / 4)*y + x;
1249		fbcolor = *addr;
	1256	fbcolor = 0;
	1257	if (color_mask != 0)
	1258	fbcolor = *addr;
1250	1259	daddr=depthbuffer + (pitch_depthbuffer / 4)*y + x;
1251	1260	deptsten = *daddr;
1252	1261	c[3] = color >> 24;
r249025	r249026
1772	1781	break;
1773	1782	}
1774	1783	}
1775		fbcolor = (c[3] << 24) \| (c[2] << 16) \| (c[1] << 8) \| c[0];
1776		*addr = fbcolor;
	1784	if (color_mask != 0) {
	1785	UINT32 fbcolor_tmp;
	1786
	1787	fbcolor_tmp = (c[3] << 24) \| (c[2] << 16) \| (c[1] << 8) \| c[0];
	1788	*addr = (fbcolor & ~color_mask) \| (fbcolor_tmp & color_mask);
	1789	}
1777	1790	if (depth_write_enabled)
1778	1791	dep = depth;
1779	1792	deptsten = (dep << 8) \| sten;
r249025	r249026
2233	2246	maddress = method * 4;
2234	2247	data = space.read_dword(address);
2235	2248	channel[chanel][subchannel].object.method[method] = data;
	2249	#ifdef LOG_NV2A
	2250	printf("A:%08X MTHD:%08X D:%08X\n\r",address,maddress,data);
	2251	#endif
2236	2252	if (maddress == 0x17fc) {
2237	2253	indexesleft_count = 0;
2238	2254	indexesleft_first = 0;
r249025	r249026
2270	2286	}
2271	2287	wait();
2272	2288	}
	2289	else if (type == nv2a_renderer::TRIANGLE_FAN) {
	2290	vertex_nv vert[3];
	2291	vertex_t xy[3];
	2292
	2293	read_vertices_0x1810(space, vert, offset, 2);
	2294	convert_vertices_poly(vert, xy, 2);
	2295	count = count - 2;
	2296	offset = offset + 2;
	2297	for (n = 0; n <= count; n++) {
	2298	read_vertices_0x1810(space, vert + (((n + 1) & 1) + 1), offset + n, 1);
	2299	convert_vertices_poly(vert + (((n + 1) & 1) + 1), xy + (((n + 1) & 1) + 1), 1);
	2300	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, xy[0], xy[(~(n + 1) & 1) + 1], xy[((n + 1) & 1) + 1]);
	2301	}
	2302	wait();
	2303	}
2273	2304	else if (type == nv2a_renderer::TRIANGLE_STRIP) {
2274	2305	vertex_nv vert[4];
2275	2306	vertex_t xy[4];
r249025	r249026
2311	2342	// each dword after 1800 contains two 16 bit index values to select the vartices
2312	2343	// each dword after 1808 contains a 32 bit index value to select the vartices
2313	2344	type = channel[chanel][subchannel].object.method[0x17fc / 4];
2314		#ifdef LOG_NV2A
2315		printf("vertex %d %d %d\n\r", type, offset, count);
2316		#endif
2317	2345	if (type == nv2a_renderer::QUADS) {
2318	2346	while (1) {
2319	2347	vertex_nv vert[4];
r249025	r249026
2332	2360	render_polygon<4>(limits_rendertarget, renderspans, 4 + 4 * 2, xy); // 4 rgba, 4 texture units 2 uv
2333	2361	}
2334	2362	}
	2363	else if (type == nv2a_renderer::TRIANGLE_FAN) {
	2364	if ((countlen * mult + indexesleft_count) >= 3) {
	2365	vertex_nv vert[3];
	2366	vertex_t xy[3];
	2367	int c, count;
	2368
	2369	if (mult == 1)
	2370	c = read_vertices_0x1808(space, vert, address, 2);
	2371	else
	2372	c = read_vertices_0x1800(space, vert, address, 2);
	2373	convert_vertices_poly(vert, xy, 2);
	2374	address = address + c * 4;
	2375	countlen = countlen - c;
	2376	count = countlen * mult + indexesleft_count;
	2377	for (n = 1; n <= count; n++) {
	2378	if (mult == 1)
	2379	c = read_vertices_0x1808(space, vert + ((n & 1) + 1), address, 1);
	2380	else
	2381	c = read_vertices_0x1800(space, vert + ((n & 1) + 1), address, 1);
	2382
	2383	convert_vertices_poly(vert + ((n & 1) + 1), xy + ((n & 1) + 1), 1);
	2384	address = address + c * 4;
	2385	countlen = countlen - c;
	2386	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, xy[0], xy[(~n & 1) + 1], xy[(n & 1) + 1]);
	2387	}
	2388	wait();
	2389	}
	2390	}
2335	2391	else if (type == nv2a_renderer::TRIANGLES) {
2336	2392	while (1) {
2337	2393	vertex_nv vert[3];
r249025	r249026
2446	2502	}
2447	2503	wait();
2448	2504	}
	2505	else if (type == nv2a_renderer::TRIANGLES) {
	2506	while (countlen > 0) {
	2507	vertex_nv vert[3];
	2508	vertex_t xy[3];
	2509	int c;
	2510
	2511	c = read_vertices_0x1818(space, vert, address, 3);
	2512	convert_vertices_poly(vert, xy, 3);
	2513	countlen = countlen - c;
	2514	if (countlen < 0) {
	2515	logerror("Method 0x1818 missing %d words to draw a complete primitive\n", -countlen);
	2516	countlen = 0;
	2517	break;
	2518	}
	2519	address = address + c * 3;
	2520	render_triangle(limits_rendertarget, renderspans, 4 + 4 * 2, xy[0], xy[1], xy[2]); // 4 rgba, 4 texture units 2 uv
	2521	}
	2522	}
2449	2523	else if (type == nv2a_renderer::TRIANGLE_STRIP) {
2450	2524	vertex_nv vert[4];
2451	2525	vertex_t xy[4];
r249025	r249026
2613	2687	// clear colors
2614	2688	UINT32 color = channel[chanel][subchannel].object.method[0x1d90 / 4];
2615	2689	bm.fill(color);
2616		//printf("clearscreen\n\r");
	2690	#ifdef LOG_NV2A
	2691	printf("clearscreen\n\r");
	2692	#endif
2617	2693	}
2618	2694	if ((data & 0x03) == 3) {
2619	2695	bitmap_rgb32 bm(depthbuffer, (limits_rendertarget.right() + 1) * m, (limits_rendertarget.bottom() + 1) * m, pitch_rendertarget / 4); // why *2 ?
r249025	r249026
2649	2725	dilate_rendertarget = dilatechose[(log2width_rendertarget << 4) + log2height_rendertarget];
2650	2726	}
2651	2727	if (maddress == 0x020c) {
2652		// line size ?
2653	2728	pitch_rendertarget=data & 0xffff;
2654	2729	pitch_depthbuffer=(data >> 16) & 0xffff;
2655		//printf("Pitch color %04X zbuffer %04X\n\r",pitch_rendertarget,pitch_depthbuffer);
	2730	#ifdef LOG_NV2A
	2731	printf("Pitch color %04X zbuffer %04X\n\r",pitch_rendertarget,pitch_depthbuffer);
	2732	#endif
2656	2733	countlen--;
2657	2734	}
2658	2735	if (maddress == 0x0100) {
2659		// just temporarily
2660		if ((data & 0x1f) == 1) {
2661		data = data >> 5;
2662		data = data & 0x0ffffff0;
2663		displayedtarget = (UINT32 *)direct_access_ptr(data);
	2736	countlen--;
	2737	if (data != 0) {
	2738	pgraph[0x704 / 4] = 0x100;
	2739	pgraph[0x708 / 4] = data;
	2740	pgraph[0x100 / 4] \|= 1;
	2741	pgraph[0x108 / 4] \|= 1;
	2742	if (update_interrupts() == true)
	2743	interruptdevice->ir3_w(1); // IRQ 3
	2744	else
	2745	interruptdevice->ir3_w(0); // IRQ 3
	2746	return 2;
2664	2747	}
	2748	else
	2749	return 0;
2665	2750	}
2666	2751	if (maddress == 0x0130) {
2667	2752	countlen--;
r249025	r249026
2670	2755	else
2671	2756	return 0;
2672	2757	}
	2758	if (maddress == 0x1d8c) {
	2759	countlen--;
	2760	// it is used to specify the clear value for the depth buffer (zbuffer)
	2761	// but also as a parameter for interrupt routines
	2762	pgraph[0x1a88 / 4] = data;
	2763	}
	2764	if (maddress == 0x1d90) {
	2765	countlen--;
	2766	// it is used to specify the clear value for the color buffer
	2767	// but also as a parameter for interrupt routines
	2768	pgraph[0x186c / 4] = data;
	2769	}
2673	2770	if (maddress == 0x0210) {
2674	2771	// framebuffer offset ?
2675	2772	rendertarget = (UINT32 *)direct_access_ptr(data);
2676		//printf("Render target at %08X\n\r",data);
	2773	#ifdef LOG_NV2A
	2774	printf("Render target at %08X\n\r", data);
	2775	#endif
2677	2776	countlen--;
2678	2777	}
2679	2778	if (maddress == 0x0214) {
2680	2779	// zbuffer offset ?
2681	2780	depthbuffer = (UINT32 *)direct_access_ptr(data);
2682		//printf("Depth buffer at %08X\n\r",data);
	2781	#ifdef LOG_NV2A
	2782	printf("Depth buffer at %08X\n\r",data);
	2783	#endif
2683	2784	if ((data == 0) \|\| (data > 0x7ffffffc))
2684	2785	depth_write_enabled = false;
2685	2786	else if (channel[chanel][subchannel].object.method[0x035c / 4] != 0)
r249025	r249026
2709	2810	if (maddress == 0x0354) {
2710	2811	depth_function = data;
2711	2812	}
	2813	if (maddress == 0x0358) {
	2814	//color_mask = data;
	2815	if (data & 0x000000ff)
	2816	data \|= 0x000000ff;
	2817	if (data & 0x0000ff00)
	2818	data \|= 0x0000ff00;
	2819	if (data & 0x00ff0000)
	2820	data \|= 0x00ff0000;
	2821	if (data & 0xff000000)
	2822	data \|= 0xff000000;
	2823	color_mask = data;
	2824	}
2712	2825	if (maddress == 0x035c) {
2713	2826	UINT32 g = channel[chanel][subchannel].object.method[0x0214 / 4];
2714	2827	depth_write_enabled = data != 0;
r249025	r249026
3648	3761	combiner.function_Aop3 = MAX(MIN((combiner.function_Aop3 + biasa) * scalea, 1.0f), -1.0f);
3649	3762	}
3650	3763
3651		bool nv2a_renderer::vblank_callback(screen_device &screen, bool state)
	3764	void nv2a_renderer::vblank_callback(screen_device &screen, bool state)
3652	3765	{
3653		//printf("vblank_callback\n\r");
3654		if (state == true)
	3766	#ifdef LOG_NV2A
	3767	printf("vblank_callback\n\r");
	3768	#endif
	3769	if ((state == true) && (puller_waiting == 1)) {
	3770	puller_waiting = 0;
	3771	puller_timer_work(NULL, 0);
	3772	}
	3773	if (state == true) {
3655	3774	pcrtc[0x100 / 4] \|= 1;
	3775	pcrtc[0x808 / 4] \|= 0x10000;
	3776	}
	3777	else {
	3778	pcrtc[0x100 / 4] &= ~1;
	3779	pcrtc[0x808 / 4] &= ~0x10000;
	3780	}
	3781	if (update_interrupts() == true)
	3782	interruptdevice->ir3_w(1); // IRQ 3
3656	3783	else
3657		pcrtc[0x100 / 4] &= ~1;
	3784	interruptdevice->ir3_w(0); // IRQ 3
	3785	}
	3786
	3787	bool nv2a_renderer::update_interrupts()
	3788	{
3658	3789	if (pcrtc[0x100 / 4] & pcrtc[0x140 / 4])
3659	3790	pmc[0x100 / 4] \|= 0x1000000;
3660	3791	else
3661	3792	pmc[0x100 / 4] &= ~0x1000000;
3662		if ((state == true) && (puller_waiting == 1)) {
3663		puller_waiting = 0;
3664		puller_timer_work(NULL, 0);
3665		}
3666		if ((pmc[0x100 / 4] != 0) && (pmc[0x140 / 4] != 0)) {
	3793	if (pgraph[0x100 / 4] & pgraph[0x140 / 4])
	3794	pmc[0x100 / 4] \|= 0x1000;
	3795	else
	3796	pmc[0x100 / 4] &= ~0x1000;
	3797	if (((pmc[0x100 / 4] & 0x7fffffff) && (pmc[0x140 / 4] & 1)) \|\| ((pmc[0x100 / 4] & 0x80000000) && (pmc[0x140 / 4] & 2))) {
3667	3798	// send interrupt
3668	3799	return true;
3669	3800	}
r249025	r249026
3692	3823	int countlen;
3693	3824	int ret;
3694	3825	address_space *space = puller_space;
	3826	#ifdef LOG_NV2A
	3827	UINT32 subch;
	3828	#endif
3695	3829
3696	3830	chanel = puller_channel;
3697	3831	subchannel = puller_subchannel;
r249025	r249026
3748	3882	}
3749	3883	if (ret != 0) {
3750	3884	puller_timer->enable(false);
3751		puller_waiting = 1;
	3885	puller_waiting = ret;
3752	3886	return;
3753	3887	}
3754	3888	}
r249025	r249026
3847	3981	//logerror("NV_2A: read PRAMIN[%06X] value %08X\n",offset*4-0x00700000,ret);
3848	3982	}
3849	3983	else if ((offset >= 0x00400000 / 4) && (offset < 0x00402000 / 4)) {
	3984	ret = pgraph[offset - 0x00400000 / 4];
3850	3985	//logerror("NV_2A: read PGRAPH[%06X] value %08X\n",offset*4-0x00400000,ret);
3851	3986	}
3852	3987	else if ((offset >= 0x00600000 / 4) && (offset < 0x00601000 / 4)) {
r249025	r249026
3870	4005	//logerror("NV_2A: read channel[%02X,%d,%04X]=%08X\n",chanel,subchannel,suboffset*4,ret);
3871	4006	return ret;
3872	4007	}
3873		else
3874		{
3875		/* nothing */
3876		}
3877	4008	//logerror("NV_2A: read at %08X mask %08X value %08X\n",0xfd000000+offset*4,mem_mask,ret);
3878	4009	return ret;
3879	4010	}
3880	4011
3881	4012	WRITE32_MEMBER(nv2a_renderer::geforce_w)
3882	4013	{
	4014	UINT32 old;
	4015	bool update_int;
	4016
	4017	update_int = false;
3883	4018	if ((offset >= 0x00101000 / 4) && (offset < 0x00102000 / 4)) {
3884	4019	//logerror("NV_2A: write STRAPS[%06X] mask %08X value %08X\n",offset*4-0x00101000,mem_mask,data);
3885	4020	}
r249025	r249026
3898	4033	//logerror("NV_2A: write PRAMIN[%06X]=%08X\n",offset*4-0x00700000,data & mem_mask);
3899	4034	}
3900	4035	else if ((offset >= 0x00400000 / 4) && (offset < 0x00402000 / 4)) {
	4036	int e = offset - 0x00400000 / 4;
	4037	if (e >= (sizeof(pgraph) / sizeof(UINT32)))
	4038	return;
	4039	old = pgraph[e];
	4040	COMBINE_DATA(pgraph + e);
	4041	if (e == 0x100 / 4) {
	4042	pgraph[e] = old & ~data;
	4043	if (data & 1)
	4044	pgraph[0x108 / 4] = 0;
	4045	update_int = true;
	4046	}
	4047	if (e == 0x140 / 4)
	4048	update_int = true;
	4049	if (e == 0x720 / 4) {
	4050	if ((data & 1) && (puller_waiting == 2)) {
	4051	puller_waiting = 0;
	4052	puller_timer->enable();
	4053	puller_timer->adjust(attotime::zero);
	4054	}
	4055	}
	4056	if ((e >= 0x900 / 4) && (e < 0xa00 / 4))
	4057	pgraph[e] = 0;
3901	4058	//logerror("NV_2A: write PGRAPH[%06X]=%08X\n",offset*4-0x00400000,data & mem_mask);
3902	4059	}
3903	4060	else if ((offset >= 0x00600000 / 4) && (offset < 0x00601000 / 4)) {
3904	4061	int e = offset - 0x00600000 / 4;
3905	4062	if (e >= (sizeof(pcrtc) / sizeof(UINT32)))
3906	4063	return;
	4064	old = pcrtc[e];
3907	4065	COMBINE_DATA(pcrtc + e);
	4066	if (e == 0x100 / 4) {
	4067	pcrtc[e] = old & ~data;
	4068	update_int = true;
	4069	}
	4070	if (e == 0x140 / 4)
	4071	update_int = true;
3908	4072	if (e == 0x800 / 4) {
3909		displayedtarget = (UINT32 *)direct_access_ptr(data);
3910		//printf("crtc buffer %08X\n\r", data);
	4073	displayedtarget = (UINT32 *)direct_access_ptr(pcrtc[e]);
	4074	#ifdef LOG_NV2A
	4075	printf("crtc buffer %08X\n\r", data);
	4076	#endif
3911	4077	}
3912	4078	//logerror("NV_2A: write PCRTC[%06X]=%08X\n",offset*4-0x00600000,data & mem_mask);
3913	4079	}
r249025	r249026
3922	4088	// 32 channels size 0x10000 each, 8 subchannels per channel size 0x2000 each
3923	4089	int chanel, subchannel, suboffset;
3924	4090	//int method, count, handle, objclass;
3925		#ifdef LOG_NV2A
3926		int subch;
3927		#endif
3928	4091
3929	4092	suboffset = offset - 0x00800000 / 4;
3930	4093	chanel = (suboffset >> (16 - 2)) & 31;
r249025	r249026
3959	4122	}
3960	4123	//else
3961	4124	// logerror("NV_2A: write at %08X mask %08X value %08X\n",0xfd000000+offset*4,mem_mask,data);
	4125	if (update_int == true) {
	4126	if (update_interrupts() == true)
	4127	interruptdevice->ir3_w(1); // IRQ 3
	4128	else
	4129	interruptdevice->ir3_w(0); // IRQ 3
	4130	}
3962	4131	}
3963	4132
3964	4133	void nv2a_renderer::savestate_items()
r249025	r249026
3971	4140	puller_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(nv2a_renderer::puller_timer_work), this), (void *)"NV2A Puller Timer");
3972	4141	puller_timer->enable(false);
3973	4142	}
	4143
	4144	void nv2a_renderer::set_interrupt_device(pic8259_device *device)
	4145	{
	4146	interruptdevice = device;
	4147	}

trunk/src/mame/video/k052109.h
r249025	r249026
20	20	devcb = &k052109_device::set_irq_handler(*device, DEVCB_##_devcb);
21	21
22	22
23		class k052109_device : public device_t, public device_gfx_interface
	23	class k052109_device : public device_t, public device_gfx_interface
24	24	{
25	25	static const gfx_layout charlayout;
26	26	static const gfx_layout charlayout_ram;

trunk/src/mame/video/k057714.c
r249025	r249026
116	116	case 0x18: // ?
117	117	break;
118	118
119		case 0x1c: // set to 1 on "media bus" access
	119	case 0x1c: // set to 1 on "media bus" access
120	120	if ((data >> 16) == 1)
121	121	{
122	122	m_ext_fifo_count = 0;
r249025	r249026
278	278	{
279	279	if (ACCESSING_BITS_16_31)
280	280	{
281		if (m_ext_fifo_count != 0) // first access is a dummy write
	281	if (m_ext_fifo_count != 0) // first access is a dummy write
282	282	{
283	283	int count = m_ext_fifo_count - 1;
284	284	UINT32 addr = (((m_ext_fifo_addr >> 10) + m_ext_fifo_line) * 1024) + count;

trunk/src/mame/video/macrossp.c
r249025	r249026
238	238	if(pri <= 1) primask \|= GFX_PMASK_2;
239	239	if(pri <= 2) primask \|= GFX_PMASK_4;
240	240	if(pri <= 3) primask \|= GFX_PMASK_8;
241
	241
242	242	switch (source[0] & 0x0000c000)
243	243	{
244	244	case 0x00008000:
r249025	r249026
265	265	if(flipy) {
266	266	yoffst = (high * yzoom * 16);
267	267	ymin = high;
268		ymax = -1;
	268	ymax = -1;
269	269	yinc = -1;
270	270	}
271
	271
272	272	int xmin = 0;
273	273	int xmax = wide+1;
274	274	int xinc = 1;
r249025	r249026
288	288	{
289	289	int fudged_xzoom = xzoom<<8;
290	290	int fudged_yzoom = yzoom<<8;
291
	291
292	292	/* cover seams as don't know exactly how many pixels on target will cover, and can't specify fractional offsets to start */
293	293	if(xzoom < 0x100) fudged_xzoom += 0x600;
294	294	if(yzoom < 0x100) fudged_yzoom += 0x600;
295
	295
296	296	gfx->prio_zoom_alpha(bitmap,cliprect,tileno+loopno,col,
297		flipx,flipy,xpos+(xoffset>>8),ypos+(yoffset>>8),
298		fudged_xzoom,fudged_yzoom,
299		screen.priority(),primask,0,alpha);
	297	flipx,flipy,xpos+(xoffset>>8),ypos+(yoffset>>8),
	298	fudged_xzoom,fudged_yzoom,
	299	screen.priority(),primask,0,alpha);
300	300
301	301	xoffset += ((xzoom16) xinc);
302	302	loopno++;
r249025	r249026
357	357	starty -= (240/2) * (incy - 0x10000);
358	358
359	359	// previous logic, which gives mostly comparable results, vr[1] is now unused
360		// startx = (vr[1] & 0x0000ffff) << 16;
361		// starty = (vr[1] & 0xffff0000) >> 0;
362		// startx -= (368/2) * incx;
363		// starty -= (240/2) * incy;
	360	// startx = (vr[1] & 0x0000ffff) << 16;
	361	// starty = (vr[1] & 0xffff0000) >> 0;
	362	// startx -= (368/2) * incx;
	363	// starty -= (240/2) * incy;
364	364
365	365	tm->draw_roz(screen, bitmap, cliprect,
366	366	startx,starty,incx,0,0,incy,
r249025	r249026
415	415	if(lay_debug && !machine().input().code_pressed(lay_keys[pri]))
416	416	continue;
417	417	#endif
418
	418
419	419	if(!backgrounds)
420	420	continue;
421
	421
422	422	for (int y=0; y<240; y++) {
423	423	clip.min_y = clip.max_y = y;
424
	424
425	425	/* quizmoon map requires that layer 2 be drawn over layer 3 when same pri */
426	426	for(int layer = 2; layer >= 0; layer--) {
427	427	if(layerpri[layer] == pri) {
r249025	r249026
439	439
440	440	if(sprites) draw_sprites(screen, bitmap, cliprect);
441	441
442
	442
443	443	#if 0
444	444	popmessage ("scra - %08x %08x %08x\nscrb - %08x %08x %08x\nscrc - %08x %08x %08x",
445	445	m_scra_videoregs[0]&0xffffffff, // yyyyxxxx

trunk/src/mame/video/midzeus.c
r249025	r249026
27	27	#define WAVERAM1_WIDTH 512
28	28	#define WAVERAM1_HEIGHT 512
29	29
30		#define BLEND_OPAQUE1 0x00000000
31		#define BLEND_OPAQUE2 0x4b23cb00
32		#define BLEND_OPAQUE3 0x4b23dd00
33		#define BLEND_OPAQUE4 0x00004800
34		#define BLEND_OPAQUE5 0xdd23dd00
35		#define BLEND_ADD1 0x40b68800
36		#define BLEND_ADD2 0xc9b78800
37		#define BLEND_MUL1 0x4093c800
	30	#define BLEND_OPAQUE1 0x00000000
	31	#define BLEND_OPAQUE2 0x4b23cb00
	32	#define BLEND_OPAQUE3 0x4b23dd00
	33	#define BLEND_OPAQUE4 0x00004800
	34	#define BLEND_OPAQUE5 0xdd23dd00
	35	#define BLEND_ADD1 0x40b68800
	36	#define BLEND_ADD2 0xc9b78800
	37	#define BLEND_MUL1 0x4093c800
38	38
39	39
40	40	/*************************************
r249025	r249026
45	45
46	46	struct mz_poly_extra_data
47	47	{
48		const void * palbase;
49		const void * texbase;
50		UINT16 solidcolor;
51		UINT16 voffset;
52		INT16 zoffset;
53		UINT16 transcolor;
54		UINT16 texwidth;
55		UINT16 color;
56		UINT32 alpha;
57		UINT32 ctrl_word;
58		bool blend_enable;
59		bool depth_test_enable;
60		bool depth_write_enable;
61		UINT32 blend;
62		UINT8 (get_texel)(const void , int, int, int);
	48	const void * palbase;
	49	const void * texbase;
	50	UINT16 solidcolor;
	51	UINT16 voffset;
	52	INT16 zoffset;
	53	UINT16 transcolor;
	54	UINT16 texwidth;
	55	UINT16 color;
	56	UINT32 alpha;
	57	UINT32 ctrl_word;
	58	bool blend_enable;
	59	bool depth_test_enable;
	60	bool depth_write_enable;
	61	UINT32 blend;
	62	UINT8 (get_texel)(const void , int, int, int);
63	63	};
64	64
65	65
r249025	r249026
1180	1180	{
1181	1181	logerror("\t\t(%f,%f,%f) UV:(%02X,%02X) UV_SCALE:(%02X,%02X) (%03X,%03X,%03X) dot=%08X\n",
1182	1182	(double) vert[i].x * (1.0 / 65536.0), (double) vert[i].y * (1.0 / 65536.0), (double) vert[i].p[0] * (1.0 / 65536.0),
1183		(iuvz >> 16) & 0xff, (iuvz >> 24) & 0xff,
	1183	(iuvz >> 16) & 0xff, (iuvz >> 24) & 0xff,
1184	1184	(int)(vert[i].p[1] / 256.0f), (int)(vert[i].p[2] / 256.0f),
1185	1185	(databuffer[10 + i] >> 20) & 0x3ff, (databuffer[10 + i] >> 10) & 0x3ff, (databuffer[10 + i] >> 0) & 0x3ff,
1186	1186	0);

trunk/src/mess/drivers/apple2.c
r249025	r249026
377	377	if (m_video->m_mix)
378	378	{
379	379	m_video->hgr_update(screen, bitmap, cliprect, 0, 159);
380		if (!strcmp(machine().system().name, "ivelultr"))
	380	if (!strcmp(machine().system().name, "ivelultr"))
381	381	{
382	382	m_video->text_update_ultr(screen, bitmap, cliprect, 160, 191);
383	383	}
r249025	r249026
396	396	if (m_video->m_mix)
397	397	{
398	398	m_video->lores_update(screen, bitmap, cliprect, 0, 159);
399		if (!strcmp(machine().system().name, "ivelultr"))
	399	if (!strcmp(machine().system().name, "ivelultr"))
400	400	{
401	401	m_video->text_update_ultr(screen, bitmap, cliprect, 160, 191);
402	402	}
r249025	r249026
413	413	}
414	414	else
415	415	{
416		if (!strcmp(machine().system().name, "ivelultr"))
	416	if (!strcmp(machine().system().name, "ivelultr"))
417	417	{
418	418	m_video->text_update_ultr(screen, bitmap, cliprect, 0, 191);
419	419	}

trunk/src/mess/drivers/hh_hmcs40.c
r249025	r249026
1718	1718	* PCB label Kaken Corp. PT-460
1719	1719	* Hitachi QFP HD38820A88 MCU(main), HD38820A89(audio)
1720	1720	* cyan/red VFD display
1721
	1721
1722	1722	This is a memory game, the difference is instead of pictures, the player
1723	1723	needs to match sound effects. It has an extra MCU for sound. The case is
1724	1724	shaped like a glossy black pyramid. Star Trek fans will recognize it as
r249025	r249026
1758	1758	{
1759	1759	// D7: sound reset (to audiocpu reset line)
1760	1760	m_audiocpu->set_input_line(INPUT_LINE_RESET, (data & 0x80) ? ASSERT_LINE : CLEAR_LINE);
1761
	1761
1762	1762	// D9: sound start (to audiocpu INT0)
1763	1763	m_audiocpu->set_input_line(0, (data & 0x200) ? ASSERT_LINE : CLEAR_LINE);
1764
	1764
1765	1765	// D10,D15: input mux
1766	1766	m_inp_mux = (data >> 10 & 1) \| (data >> 14 & 2);
1767
	1767
1768	1768	// D0-D5: vfd matrix grid
1769	1769	m_grid = data & 0x3f;
1770	1770	display_matrix(12, 6, m_plate, m_grid);
r249025	r249026
1795	1795	{
1796	1796	// D0: speaker out
1797	1797	m_speaker->level_w(data & 1);
1798
	1798
1799	1799	// D1: sound ack (to maincpu INT0)
1800	1800	m_maincpu->set_input_line(0, (data & 2) ? ASSERT_LINE : CLEAR_LINE);
1801	1801	}

trunk/src/mess/drivers/hh_tms1k.c
r249025	r249026
235	235	}
236	236
237	237	memcpy(m_display_cache, active_state, sizeof(m_display_cache));
238
	238
239	239	// output optional power led
240	240	if (m_power_led != m_power_on)
241	241	{

trunk/src/mess/drivers/hh_ucom4.c
r249025	r249026
969	969	Castle Toy Tactix
970	970	* NEC uCOM-43 MCU, labeled D557LC 512
971	971	* 16 LEDs behind buttons
972
	972
973	973	Tactix is similar to Merlin, for 1 or 2 players. In 2-player mode, simply
974	974	don't press the Comp Turn button. The four included minigames are:
975	975	1: Capture (reversi)
r249025	r249026
1194	1194	known releases:
1195	1195	- USA: Electronic Football (aka Pro-Bowl Football)
1196	1196	- Japan: American Football
1197
	1197
1198	1198	note: MAME external artwork is not needed for this game
1199	1199
1200	1200	***************************************************************************/

trunk/src/mess/drivers/hp64k.c
r249025	r249026
216	216
217	217	DECLARE_READ16_MEMBER(hp64k_usart_r);
218	218	DECLARE_WRITE16_MEMBER(hp64k_usart_w);
219		DECLARE_WRITE_LINE_MEMBER(hp64k_rxrdy_w);
220		DECLARE_WRITE_LINE_MEMBER(hp64k_txrdy_w);
221		DECLARE_WRITE_LINE_MEMBER(hp64k_txd_w);
222		DECLARE_WRITE_LINE_MEMBER(hp64k_dtr_w);
223		DECLARE_WRITE_LINE_MEMBER(hp64k_rts_w);
	219	DECLARE_WRITE_LINE_MEMBER(hp64k_rxrdy_w);
	220	DECLARE_WRITE_LINE_MEMBER(hp64k_txrdy_w);
	221	DECLARE_WRITE_LINE_MEMBER(hp64k_txd_w);
	222	DECLARE_WRITE_LINE_MEMBER(hp64k_dtr_w);
	223	DECLARE_WRITE_LINE_MEMBER(hp64k_rts_w);
224	224	DECLARE_WRITE16_MEMBER(hp64k_loopback_w);
225		void hp64k_update_loopback(void);
226		DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_rxd_w);
227		DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_dcd_w);
228		DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_cts_w);
229
	225	void hp64k_update_loopback(void);
	226	DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_rxd_w);
	227	DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_dcd_w);
	228	DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_cts_w);
	229
230	230	DECLARE_WRITE16_MEMBER(hp64k_beep_w);
231	231	TIMER_DEVICE_CALLBACK_MEMBER(hp64k_beeper_off);
232	232
233		DECLARE_WRITE_LINE_MEMBER(hp64k_baud_clk_w);
	233	DECLARE_WRITE_LINE_MEMBER(hp64k_baud_clk_w);
234	234	private:
235	235	required_device<hp_5061_3011_cpu_device> m_cpu;
236	236	required_device<i8275_device> m_crtc;
r249025	r249026
248	248	required_ioport m_rs232_sw;
249	249	required_device<beep_device> m_beeper;
250	250	required_device<timer_device> m_beep_timer;
251		required_device<clock_device> m_baud_rate;
252		required_ioport m_s5_sw;
253		required_device<i8251_device> m_uart;
254		required_device<rs232_port_device> m_rs232;
	251	required_device<clock_device> m_baud_rate;
	252	required_ioport m_s5_sw;
	253	required_device<i8251_device> m_uart;
	254	required_device<rs232_port_device> m_rs232;
255	255
256	256	// Character generator
257	257	const UINT8 *m_chargen;
r249025	r249026
302	302	floppy_state_t m_floppy_if_state;
303	303	floppy_image_device *m_current_floppy;
304	304
305		// RS232 I/F
306		bool m_16x_clk;
307		bool m_baud_clk;
308		UINT8 m_16x_div;
309		bool m_loopback;
310		bool m_txd_state;
311		bool m_dtr_state;
312		bool m_rts_state;
	305	// RS232 I/F
	306	bool m_16x_clk;
	307	bool m_baud_clk;
	308	UINT8 m_16x_div;
	309	bool m_loopback;
	310	bool m_txd_state;
	311	bool m_dtr_state;
	312	bool m_rts_state;
313	313	};
314	314
315	315	static ADDRESS_MAP_START(cpu_mem_map , AS_PROGRAM , 16 , hp64k_state)
r249025	r249026
329	329	// PA = 4, IC = [0..3]
330	330	// Floppy I/F
331	331	AM_RANGE(HP_MAKE_IOADDR(4 , 0) , HP_MAKE_IOADDR(4 , 3)) AM_READWRITE(hp64k_flp_r , hp64k_flp_w)
332		// PA = 5, IC = [0..3]
333		// Write to USART
334		AM_RANGE(HP_MAKE_IOADDR(5 , 0) , HP_MAKE_IOADDR(5 , 3)) AM_WRITE(hp64k_usart_w)
	332	// PA = 5, IC = [0..3]
	333	// Write to USART
	334	AM_RANGE(HP_MAKE_IOADDR(5 , 0) , HP_MAKE_IOADDR(5 , 3)) AM_WRITE(hp64k_usart_w)
335	335	// PA = 6, IC = [0..3]
336	336	// Read from USART
337	337	AM_RANGE(HP_MAKE_IOADDR(6 , 0) , HP_MAKE_IOADDR(6 , 3)) AM_READ(hp64k_usart_r)
338	338	// PA = 7, IC = 2
339	339	// Rear-panel switches and loopback relay control
340		AM_RANGE(HP_MAKE_IOADDR(7 , 2) , HP_MAKE_IOADDR(7 , 2)) AM_READWRITE(hp64k_rear_sw_r , hp64k_loopback_w)
	340	AM_RANGE(HP_MAKE_IOADDR(7 , 2) , HP_MAKE_IOADDR(7 , 2)) AM_READWRITE(hp64k_rear_sw_r , hp64k_loopback_w)
341	341	// PA = 9, IC = [0..3]
342	342	// Beeper control & interrupt status read
343	343	AM_RANGE(HP_MAKE_IOADDR(9 , 0) , HP_MAKE_IOADDR(9 , 3)) AM_WRITE(hp64k_beep_w)
r249025	r249026
366	366	m_rear_panel_sw(*this , "rear_sw"),
367	367	m_rs232_sw(*this , "rs232_sw"),
368	368	m_beeper(*this , "beeper"),
369		m_beep_timer(*this , "beep_timer"),
370		m_baud_rate(*this , "baud_rate"),
371		m_s5_sw(*this , "s5_sw"),
372		m_uart(*this , "uart"),
373		m_rs232(*this , "rs232")
	369	m_beep_timer(*this , "beep_timer"),
	370	m_baud_rate(*this , "baud_rate"),
	371	m_s5_sw(*this , "s5_sw"),
	372	m_uart(*this , "uart"),
	373	m_rs232(*this , "rs232")
374	374	{
375	375	}
376	376
r249025	r249026
387	387
388	388	// Divisors of K1135 baud rate generator
389	389	static unsigned baud_rate_divisors[] = {
390		6336,
391		4224,
392		2880,
393		2355,
394		2112,
395		1056,
396		528,
397		264,
398		176,
399		158,
400		132,
401		88,
402		66,
403		44,
404		33,
405		16
	390	6336,
	391	4224,
	392	2880,
	393	2355,
	394	2112,
	395	1056,
	396	528,
	397	264,
	398	176,
	399	158,
	400	132,
	401	88,
	402	66,
	403	44,
	404	33,
	405	16
406	406	};
407	407
408	408	void hp64k_state::machine_reset()
r249025	r249026
428	428	m_floppy0_wpt = false;
429	429	m_floppy1_wpt = false;
430	430	m_beeper->set_state(0);
431		m_baud_rate->set_unscaled_clock(BAUD_RATE_GEN_CLOCK / baud_rate_divisors[ (m_s5_sw->read() >> 1) & 0xf ]);
432		m_16x_clk = (m_rs232_sw->read() & 0x02) != 0;
433		m_loopback = false;
434		m_txd_state = true;
435		m_dtr_state = true;
436		m_rts_state = true;
437
	431	m_baud_rate->set_unscaled_clock(BAUD_RATE_GEN_CLOCK / baud_rate_divisors[ (m_s5_sw->read() >> 1) & 0xf ]);
	432	m_16x_clk = (m_rs232_sw->read() & 0x02) != 0;
	433	m_loopback = false;
	434	m_txd_state = true;
	435	m_dtr_state = true;
	436	m_rts_state = true;
	437
438	438	}
439	439
440	440	UINT8 hp64k_state::hp64k_crtc_filter(UINT8 data)
r249025	r249026
958	958
959	959	READ16_MEMBER(hp64k_state::hp64k_usart_r)
960	960	{
961		UINT16 tmp;
	961	UINT16 tmp;
962	962
963		if ((offset & 1) == 0) {
964		tmp = m_uart->status_r(space , 0);
965		} else {
966		tmp = m_uart->data_r(space , 0);
967		}
968
	963	if ((offset & 1) == 0) {
	964	tmp = m_uart->status_r(space , 0);
	965	} else {
	966	tmp = m_uart->data_r(space , 0);
	967	}
	968
969	969	// bit 8 == bit 7 rear panel switches (modem/terminal) ???
970	970
971		tmp \|= (m_rs232_sw->read() << 8);
	971	tmp \|= (m_rs232_sw->read() << 8);
972	972
973		if (BIT(m_rear_panel_sw->read() , 7)) {
974		BIT_SET(tmp , 8);
975		}
976
	973	if (BIT(m_rear_panel_sw->read() , 7)) {
	974	BIT_SET(tmp , 8);
	975	}
	976
977	977	return tmp;
978	978	}
979	979
980	980	WRITE16_MEMBER(hp64k_state::hp64k_usart_w)
981	981	{
982		if ((offset & 1) == 0) {
983		m_uart->control_w(space , 0 , (UINT8)(data & 0xff));
984		} else {
985		m_uart->data_w(space , 0 , (UINT8)(data & 0xff));
986		}
	982	if ((offset & 1) == 0) {
	983	m_uart->control_w(space , 0 , (UINT8)(data & 0xff));
	984	} else {
	985	m_uart->data_w(space , 0 , (UINT8)(data & 0xff));
	986	}
987	987	}
988	988
989	989	WRITE_LINE_MEMBER(hp64k_state::hp64k_rxrdy_w)
990	990	{
991		if (state) {
992		BIT_SET(m_irl_pending , 6);
993		} else {
994		BIT_CLR(m_irl_pending , 6);
995		}
	991	if (state) {
	992	BIT_SET(m_irl_pending , 6);
	993	} else {
	994	BIT_CLR(m_irl_pending , 6);
	995	}
996	996
997		hp64k_update_irl();
	997	hp64k_update_irl();
998	998	}
999	999
1000	1000	WRITE_LINE_MEMBER(hp64k_state::hp64k_txrdy_w)
1001	1001	{
1002		if (state) {
1003		BIT_SET(m_irl_pending , 5);
1004		} else {
1005		BIT_CLR(m_irl_pending , 5);
1006		}
	1002	if (state) {
	1003	BIT_SET(m_irl_pending , 5);
	1004	} else {
	1005	BIT_CLR(m_irl_pending , 5);
	1006	}
1007	1007
1008		hp64k_update_irl();
	1008	hp64k_update_irl();
1009	1009	}
1010	1010
1011	1011	WRITE_LINE_MEMBER(hp64k_state::hp64k_txd_w)
1012	1012	{
1013		m_txd_state = state;
1014		if (m_loopback) {
1015		m_uart->write_rxd(state);
1016		}
1017		m_rs232->write_txd(state);
	1013	m_txd_state = state;
	1014	if (m_loopback) {
	1015	m_uart->write_rxd(state);
	1016	}
	1017	m_rs232->write_txd(state);
1018	1018	}
1019	1019
1020	1020	WRITE_LINE_MEMBER(hp64k_state::hp64k_dtr_w)
1021	1021	{
1022		m_dtr_state = state;
1023		if (m_loopback) {
1024		m_uart->write_dsr(state);
1025		}
1026		m_rs232->write_dtr(state);
	1022	m_dtr_state = state;
	1023	if (m_loopback) {
	1024	m_uart->write_dsr(state);
	1025	}
	1026	m_rs232->write_dtr(state);
1027	1027	}
1028	1028
1029	1029	WRITE_LINE_MEMBER(hp64k_state::hp64k_rts_w)
1030	1030	{
1031		if (BIT(m_s5_sw->read() , 0)) {
1032		// Full duplex, RTS/ = 0
1033		state = 0;
1034		}
1035		m_rts_state = state;
1036		if (m_loopback) {
1037		m_uart->write_cts(state);
1038		}
1039		m_rs232->write_rts(state);
	1031	if (BIT(m_s5_sw->read() , 0)) {
	1032	// Full duplex, RTS/ = 0
	1033	state = 0;
	1034	}
	1035	m_rts_state = state;
	1036	if (m_loopback) {
	1037	m_uart->write_cts(state);
	1038	}
	1039	m_rs232->write_rts(state);
1040	1040	}
1041	1041
1042	1042	WRITE16_MEMBER(hp64k_state::hp64k_loopback_w)
1043	1043	{
1044		m_loopback = BIT(data , 11);
1045		hp64k_update_loopback();
	1044	m_loopback = BIT(data , 11);
	1045	hp64k_update_loopback();
1046	1046	}
1047	1047
1048	1048	void hp64k_state::hp64k_update_loopback(void)
1049	1049	{
1050		if (m_loopback) {
1051		m_uart->write_rxd(m_txd_state);
1052		m_uart->write_dsr(m_dtr_state);
1053		m_uart->write_cts(m_rts_state);
1054		} else {
1055		m_uart->write_rxd(m_rs232->rxd_r());
1056		m_uart->write_dsr(m_rs232->dcd_r());
1057		m_uart->write_cts(m_rs232->cts_r());
1058		}
	1050	if (m_loopback) {
	1051	m_uart->write_rxd(m_txd_state);
	1052	m_uart->write_dsr(m_dtr_state);
	1053	m_uart->write_cts(m_rts_state);
	1054	} else {
	1055	m_uart->write_rxd(m_rs232->rxd_r());
	1056	m_uart->write_dsr(m_rs232->dcd_r());
	1057	m_uart->write_cts(m_rs232->cts_r());
	1058	}
1059	1059	}
1060	1060
1061	1061	WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_rxd_w)
1062	1062	{
1063		if (!m_loopback) {
1064		m_uart->write_rxd(state);
1065		}
	1063	if (!m_loopback) {
	1064	m_uart->write_rxd(state);
	1065	}
1066	1066	}
1067	1067
1068	1068	WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_dcd_w)
1069	1069	{
1070		if (!m_loopback) {
1071		m_uart->write_dsr(state);
1072		}
	1070	if (!m_loopback) {
	1071	m_uart->write_dsr(state);
	1072	}
1073	1073	}
1074	1074
1075	1075	WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_cts_w)
1076	1076	{
1077		if (!m_loopback) {
1078		m_uart->write_cts(state);
1079		}
	1077	if (!m_loopback) {
	1078	m_uart->write_cts(state);
	1079	}
1080	1080	}
1081	1081
1082	1082	WRITE16_MEMBER(hp64k_state::hp64k_beep_w)
r249025	r249026
1095	1095
1096	1096	WRITE_LINE_MEMBER(hp64k_state::hp64k_baud_clk_w)
1097	1097	{
1098		if (!m_16x_clk) {
1099		if (state && !m_baud_clk) {
1100		m_16x_div++;
1101		}
1102		m_baud_clk = !!state;
1103		state = BIT(m_16x_div , 3);
1104		}
1105		m_uart->write_txc(state);
1106		m_uart->write_rxc(state);
	1098	if (!m_16x_clk) {
	1099	if (state && !m_baud_clk) {
	1100	m_16x_div++;
	1101	}
	1102	m_baud_clk = !!state;
	1103	state = BIT(m_16x_div , 3);
	1104	}
	1105	m_uart->write_txc(state);
	1106	m_uart->write_rxc(state);
1107	1107	}
1108	1108
1109	1109	static INPUT_PORTS_START(hp64k)
r249025	r249026
1321	1321	PORT_DIPSETTING(0x00 , "1x")
1322	1322	PORT_DIPSETTING(0x02 , "16x")
1323	1323
1324		PORT_START("s5_sw")
1325		PORT_DIPNAME(0x01 , 0x00 , "Duplex")
1326		PORT_DIPLOCATION("S5 IO:!1")
1327		PORT_DIPSETTING(0x00 , "Half duplex")
1328		PORT_DIPSETTING(0x01 , "Full duplex")
1329		PORT_DIPNAME(0x1e , 0x00 , "Baud rate")
1330		PORT_DIPLOCATION("S5 IO:!5,!4,!3,!2")
1331		PORT_DIPSETTING(0x00 , "50")
1332		PORT_DIPSETTING(0x02 , "75")
1333		PORT_DIPSETTING(0x04 , "110")
1334		PORT_DIPSETTING(0x06 , "134.5")
1335		PORT_DIPSETTING(0x08 , "150")
1336		PORT_DIPSETTING(0x0a , "300")
1337		PORT_DIPSETTING(0x0c , "600")
1338		PORT_DIPSETTING(0x0e , "1200")
1339		PORT_DIPSETTING(0x10 , "1800")
1340		PORT_DIPSETTING(0x12 , "2000")
1341		PORT_DIPSETTING(0x14 , "2400")
1342		PORT_DIPSETTING(0x16 , "3600")
1343		PORT_DIPSETTING(0x18 , "4800")
1344		PORT_DIPSETTING(0x1a , "7200")
1345		PORT_DIPSETTING(0x1c , "9600")
1346		PORT_DIPSETTING(0x1e , "19200")
	1324	PORT_START("s5_sw")
	1325	PORT_DIPNAME(0x01 , 0x00 , "Duplex")
	1326	PORT_DIPLOCATION("S5 IO:!1")
	1327	PORT_DIPSETTING(0x00 , "Half duplex")
	1328	PORT_DIPSETTING(0x01 , "Full duplex")
	1329	PORT_DIPNAME(0x1e , 0x00 , "Baud rate")
	1330	PORT_DIPLOCATION("S5 IO:!5,!4,!3,!2")
	1331	PORT_DIPSETTING(0x00 , "50")
	1332	PORT_DIPSETTING(0x02 , "75")
	1333	PORT_DIPSETTING(0x04 , "110")
	1334	PORT_DIPSETTING(0x06 , "134.5")
	1335	PORT_DIPSETTING(0x08 , "150")
	1336	PORT_DIPSETTING(0x0a , "300")
	1337	PORT_DIPSETTING(0x0c , "600")
	1338	PORT_DIPSETTING(0x0e , "1200")
	1339	PORT_DIPSETTING(0x10 , "1800")
	1340	PORT_DIPSETTING(0x12 , "2000")
	1341	PORT_DIPSETTING(0x14 , "2400")
	1342	PORT_DIPSETTING(0x16 , "3600")
	1343	PORT_DIPSETTING(0x18 , "4800")
	1344	PORT_DIPSETTING(0x1a , "7200")
	1345	PORT_DIPSETTING(0x1c , "9600")
	1346	PORT_DIPSETTING(0x1e , "19200")
1347	1347
1348	1348	INPUT_PORTS_END
1349	1349
r249025	r249026
1366	1366
1367	1367	// Clock = 25 MHz / 9 * (112/114)
1368	1368	MCFG_DEVICE_ADD("crtc" , I8275 , 2729045)
1369		MCFG_VIDEO_SET_SCREEN("screen")
	1369	MCFG_VIDEO_SET_SCREEN("screen")
1370	1370	MCFG_I8275_CHARACTER_WIDTH(9)
1371	1371	MCFG_I8275_DRAW_CHARACTER_CALLBACK_OWNER(hp64k_state , crtc_display_pixels)
1372	1372	MCFG_I8275_DRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_crtc_drq_w))
r249025	r249026
1375	1375	MCFG_SCREEN_ADD("screen" , RASTER)
1376	1376	MCFG_SCREEN_UPDATE_DEVICE("crtc" , i8275_device , screen_update)
1377	1377	MCFG_SCREEN_REFRESH_RATE(60)
1378		MCFG_SCREEN_SIZE(720 , 390)
	1378	MCFG_SCREEN_SIZE(720 , 390)
1379	1379	MCFG_PALETTE_ADD_MONOCHROME_GREEN_HIGHLIGHT("palette")
1380	1380
1381		MCFG_FD1791_ADD("fdc" , XTAL_4MHz / 4)
	1381	MCFG_FD1791_ADD("fdc" , XTAL_4MHz / 4)
1382	1382	MCFG_WD_FDC_FORCE_READY
1383	1383	MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_flp_intrq_w))
1384	1384	MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(hp64k_state , hp64k_flp_drq_w))
r249025	r249026
1410	1410
1411	1411	MCFG_TIMER_DRIVER_ADD("beep_timer" , hp64k_state , hp64k_beeper_off);
1412	1412
1413		MCFG_DEVICE_ADD("baud_rate" , CLOCK , 0)
1414		MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(hp64k_state , hp64k_baud_clk_w));
	1413	MCFG_DEVICE_ADD("baud_rate" , CLOCK , 0)
	1414	MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(hp64k_state , hp64k_baud_clk_w));
1415	1415
1416		MCFG_DEVICE_ADD("uart" , I8251 , 0)
1417		MCFG_I8251_RXRDY_HANDLER(WRITELINE(hp64k_state , hp64k_rxrdy_w));
1418		MCFG_I8251_TXRDY_HANDLER(WRITELINE(hp64k_state , hp64k_txrdy_w));
1419		MCFG_I8251_TXD_HANDLER(WRITELINE(hp64k_state , hp64k_txd_w));
1420		MCFG_I8251_DTR_HANDLER(WRITELINE(hp64k_state , hp64k_dtr_w));
1421		MCFG_I8251_RTS_HANDLER(WRITELINE(hp64k_state , hp64k_rts_w));
	1416	MCFG_DEVICE_ADD("uart" , I8251 , 0)
	1417	MCFG_I8251_RXRDY_HANDLER(WRITELINE(hp64k_state , hp64k_rxrdy_w));
	1418	MCFG_I8251_TXRDY_HANDLER(WRITELINE(hp64k_state , hp64k_txrdy_w));
	1419	MCFG_I8251_TXD_HANDLER(WRITELINE(hp64k_state , hp64k_txd_w));
	1420	MCFG_I8251_DTR_HANDLER(WRITELINE(hp64k_state , hp64k_dtr_w));
	1421	MCFG_I8251_RTS_HANDLER(WRITELINE(hp64k_state , hp64k_rts_w));
1422	1422
1423		MCFG_RS232_PORT_ADD("rs232" , default_rs232_devices , NULL)
1424		MCFG_RS232_RXD_HANDLER(WRITELINE(hp64k_state , hp64k_rs232_rxd_w))
1425		MCFG_RS232_DCD_HANDLER(WRITELINE(hp64k_state , hp64k_rs232_dcd_w))
1426		MCFG_RS232_CTS_HANDLER(WRITELINE(hp64k_state , hp64k_rs232_cts_w))
1427
	1423	MCFG_RS232_PORT_ADD("rs232" , default_rs232_devices , NULL)
	1424	MCFG_RS232_RXD_HANDLER(WRITELINE(hp64k_state , hp64k_rs232_rxd_w))
	1425	MCFG_RS232_DCD_HANDLER(WRITELINE(hp64k_state , hp64k_rs232_dcd_w))
	1426	MCFG_RS232_CTS_HANDLER(WRITELINE(hp64k_state , hp64k_rs232_cts_w))
	1427
1428	1428	MACHINE_CONFIG_END
1429	1429
1430	1430	ROM_START(hp64k)

trunk/src/mess/drivers/hp_ipc.c
r249025	r249026
356	356
357	357
358	358	COMP(1985, hp_ipc, 0, 0, hp_ipc, hp_ipc, driver_device, 0, "HP", "Integral Personal Computer", MACHINE_IS_SKELETON)
359

trunk/src/mess/drivers/ngen.c
r249025	r249026
744	744	MC6845_UPDATE_ROW( ngen_state::crtc_update_row )
745	745	{
746	746	UINT16 addr = ma;
747
	747
748	748	for(int x=0;x<bitmap.width();x+=9)
749	749	{
750	750	UINT8 ch = m_vram.read16(addr++) & 0xff;
r249025	r249026
893	893
894	894	static ADDRESS_MAP_START( ngen386_io, AS_IO, 32, ngen_state )
895	895	AM_RANGE(0x0000, 0x0003) AM_READWRITE16(xbus_r, xbus_w, 0x0000ffff)
896		// AM_RANGE(0xf800, 0xfeff) AM_READWRITE16(peripheral_r, peripheral_w,0xffffffff)
	896	// AM_RANGE(0xf800, 0xfeff) AM_READWRITE16(peripheral_r, peripheral_w,0xffffffff)
897	897	AM_RANGE(0xfd08, 0xfd0b) AM_READWRITE16(b38_crtc_r, b38_crtc_w,0xffffffff)
898	898	AM_RANGE(0xfd0c, 0xfd0f) AM_READWRITE16(b38_keyboard_r, b38_keyboard_w,0xffffffff)
899	899	ADDRESS_MAP_END

trunk/src/mess/drivers/tispeak.c
r249025	r249026
9	9	These devices, mostly edu-toys, are based around an MCU(TMS0270/TMS1100),
10	10	TMS51xx speech, and VSM ROM(s). Newer devices, such as Speak & Music,
11	11	are based around the TMP50C40 and belong in another driver, probably.
12
	12
13	13	note: except for tntell, MAME external artwork is not required. But it
14	14	is objectively a large improvement.
15	15
r249025	r249026
430	430	void tispeak_state::init_cartridge()
431	431	{
432	432	m_overlay = 0;
433
	433
434	434	if (m_cart != NULL && m_cart->exists())
435	435	{
436	436	std::string region_tag;
r249025	r249026
558	558	{
559	559	// R10: CD2802 PDC pin
560	560	m_tms5100->pdc_w(data >> 10);
561
	561
562	562	// R9: power-off request, on falling edge
563	563	if ((m_r >> 9 & 1) && !(data >> 9 & 1))
564	564	snspell_power_off();
r249025	r249026
578	578	{
579	579	// multiplexed inputs (and K2 from on-button)
580	580	UINT8 k = m_inp_matrix[9]->read() \| read_inputs(9);
581
	581
582	582	// K4: CD2802 CTL1
583	583	if (m_tms5100->ctl_r(space, 0) & 1)
584	584	k \|= 4;
r249025	r249026
586	586	// K8: overlay code from R5,O4-O7
587	587	if (((m_r >> 1 & 0x10) \| (m_o >> 4 & 0xf)) & m_overlay)
588	588	k \|= 8;
589
	589
590	590	return k;
591	591	}
592	592
r249025	r249026
596	596	// which one is active(if any). If it matches with the internal ROM or
597	597	// external module, the game continues.
598	598	// 00 for none, 1F for diagnostics, see comment section above for a list
599
	599
600	600	// try to get overlay code from artwork file(in decimal), otherwise pick the
601	601	// one that was selected in machine configuration
602	602	m_overlay = output_get_value("overlay_code") & 0x1f;
603	603	if (m_overlay == 0)
604	604	m_overlay = m_inp_matrix[10]->read();
605
	605
606	606	for (int i = 0; i < 5; i++)
607	607	output_set_indexed_value("ol", i+1, m_overlay >> i & 1);
608	608	}
r249025	r249026
1252	1252	ROM_LOAD( "tms1100_cd8012_micro.pla", 0, 867, CRC(46d936c8) SHA1(b0aad486a90a5dec7fd2fb07caa503be771f91c8) )
1253	1253	ROM_REGION( 365, "maincpu:opla", 0 )
1254	1254	ROM_LOAD( "tms1100_cd8012_output.pla", 0, 365, CRC(5ada9306) SHA1(a4140118dd535af45a691832530d55cd86a23510) )
1255
	1255
1256	1256	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF ) // 4000-7fff = space reserved for cartridge
1257	1257	ROM_LOAD( "cd2610.vsm", 0x0000, 0x1000, CRC(6db34e5a) SHA1(10fa5db20fdcba68034058e7194f35c90b9844e6) )
1258	1258	ROM_END
r249025	r249026
1265	1265	ROM_LOAD( "tms1100_cd8012_micro.pla", 0, 867, CRC(46d936c8) SHA1(b0aad486a90a5dec7fd2fb07caa503be771f91c8) )
1266	1266	ROM_REGION( 365, "maincpu:opla", 0 )
1267	1267	ROM_LOAD( "tms1100_cd8012_output.pla", 0, 365, CRC(5ada9306) SHA1(a4140118dd535af45a691832530d55cd86a23510) )
1268
	1268
1269	1269	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF ) // 4000-7fff = space reserved for cartridge
1270	1270	ROM_LOAD( "cd62170.vsm", 0x0000, 0x4000, CRC(6dc9d072) SHA1(9d2c9ff57c4f8fe69768666ffa41fcac649279ef) )
1271	1271	ROM_END
r249025	r249026
1278	1278	ROM_LOAD( "tms1100_cd8012_micro.pla", 0, 867, CRC(46d936c8) SHA1(b0aad486a90a5dec7fd2fb07caa503be771f91c8) )
1279	1279	ROM_REGION( 365, "maincpu:opla", 0 )
1280	1280	ROM_LOAD( "tms1100_cd8012_output.pla", 0, 365, CRC(5ada9306) SHA1(a4140118dd535af45a691832530d55cd86a23510) )
1281
	1281
1282	1282	ROM_REGION( 0x8000, "tms6100", ROMREGION_ERASEFF ) // 4000-7fff = space reserved for cartridge
1283	1283	ROM_LOAD( "cd62171.vsm", 0x0000, 0x4000, CRC(cc26f7d1) SHA1(2b03e37b3bf3cbeca36980acfc45246dac706b83) )
1284	1284	ROM_END

trunk/src/mess/drivers/xbox.c
r249025	r249026
130	130	}
131	131
132	132	/*static const struct {
133		const char *game_name;
134		struct {
135		UINT32 address;
136		UINT8 write_byte;
137		} modify[16];
	133	const char *game_name;
	134	struct {
	135	UINT32 address;
	136	UINT8 write_byte;
	137	} modify[16];
138	138	} hacks[] = { { "chihiro",{ { 0x6a79f, 0x01 },{ 0x6a7a0, 0x00 },{ 0x6b575, 0x00 },{ 0x6b576, 0x00 },{ 0x6b5af, 0x75 },{ 0x6b78a, 0x75 },{ 0x6b7ca, 0x00 },{ 0x6b7b8, 0x00 },{ 0x8f5b2, 0x75 },{ 0x79a9e, 0x74 },{ 0x79b80, 0x74 },{ 0x79b97, 0x74 },{ 0, 0 } } },
139	139	{ "outr2",{ { 0x12e4cf, 0x01 },{ 0x12e4d0, 0x00 },{ 0x4793e, 0x01 },{ 0x4793f, 0x00 },{ 0x47aa3, 0x01 },{ 0x47aa4, 0x00 },{ 0x14f2b6, 0x84 },{ 0x14f2d1, 0x75 },{ 0x8732f, 0x7d },{ 0x87384, 0x7d },{ 0x87388, 0xeb },{ 0, 0 } } } };*/
140	140
r249025	r249026
150	150	p = -1;
151	151	if (p >= 0) {
152	152	/*for (int a = 0; a < 16; a++) {
153		if (hacks[p].modify[a].address == 0)
154		break;
155		m_maincpu->space(0).write_byte(hacks[p].modify[a].address, hacks[p].modify[a].write_byte);
	153	if (hacks[p].modify[a].address == 0)
	154	break;
	155	m_maincpu->space(0).write_byte(hacks[p].modify[a].address, hacks[p].modify[a].write_byte);
156	156	}*/
157	157	}
158	158	usbhack_counter++;
r249025	r249026
164	164	xbox_devs.ide = machine().device<bus_master_ide_controller_device>("ide");
165	165	usbhack_index = -1;
166	166	/*for (int a = 1; a < 2; a++)
167		if (strcmp(machine().basename(), hacks[a].game_name) == 0) {
168		usbhack_index = a;
169		break;
170		}*/
	167	if (strcmp(machine().basename(), hacks[a].game_name) == 0) {
	168	usbhack_index = a;
	169	break;
	170	}*/
171	171	usbhack_counter = 0;
172	172	// savestates
173	173	save_item(NAME(usbhack_counter));

trunk/src/mess/includes/aussiebyte.h
r249025	r249026
124	124	required_device<speaker_sound_device> m_speaker;
125	125	required_device<votrax_sc01_device> m_votrax;
126	126	};
127

trunk/src/mess/includes/thomson.h
r249025	r249026
390	390	optional_memory_bank m_rambank;
391	391	required_memory_bank m_flopbank;
392	392	required_memory_bank m_basebank;
393		required_memory_bank m_syslobank;
	393	required_memory_bank m_syslobank;
394	394	optional_memory_bank m_syshibank;
395	395	optional_memory_bank m_datalobank;
396	396	optional_memory_bank m_datahibank;

trunk/src/mess/machine/coco.c
r249025	r249026
705	705	*/
706	706	if ((status & SOUNDMUX_ENABLE) != 0)
707	707	{
708		m_analog_audio_level = dac_sound + cassette_sound + cart_sound;
	708	m_analog_audio_level = dac_sound + cassette_sound + cart_sound;
709	709	}
710	710
711	711	m_dac->write_unsigned8(single_bit_sound + m_analog_audio_level);

trunk/src/mess/video/aussiebyte.c
r249025	r249026
70	70	MC6845_ON_UPDATE_ADDR_CHANGED( aussiebyte_state::crtc_update_addr )
71	71	{
72	72	/* not sure what goes in here - parameters passed are device, address, strobe */
73		// m_video_address = address;// & 0x7ff;
	73	// m_video_address = address;// & 0x7ff;
74	74	}
75	75
76	76	WRITE8_MEMBER( aussiebyte_state::address_w )
r249025	r249026
147	147	gfx = m_p_chargen[((ac_chr & 0x7f)<<4) \| ac_ra];
148	148	break;
149	149	}
150
	150
151	151	if (BIT(ac_attr, 3) & (ac_ra == 11)) // underline
152	152	gfx = 0xff;
153	153	if (BIT(ac_attr, 2) & ((ac_ra == 5) \| (ac_ra == 6))) // strike-through
r249025	r249026
194	194	*p++ = palette[BIT(gfx, 0)];
195	195	}
196	196	}
197

trunk/src/version.c
r249025	r249026
8	8
9	9	***************************************************************************/
10	10
11		#define BARE_BUILD_VERSION "0.164"
	11	#define BARE_BUILD_VERSION "0.165"
12	12
13	13	extern const char bare_build_version[];
14	14	extern const char build_version[];

https://github.com/mamedev/mame/commit/7cec959bf8a6ecb9ae72ed171257050bcc845e36

199869 Revisions