trunk/src/mess/drivers/dsb46.c
| r24596 | r24597 | |
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| 30 | 30 | , m_terminal(*this, TERMINAL_TAG) |
| 31 | 31 | { } |
| 32 | 32 | |
| 33 | | required_device<cpu_device> m_maincpu; |
| 34 | | required_device<generic_terminal_device> m_terminal; |
| 35 | 33 | DECLARE_READ8_MEMBER(port00_r); |
| 36 | 34 | DECLARE_READ8_MEMBER(port01_r); |
| 37 | 35 | DECLARE_WRITE8_MEMBER(kbd_put); |
| 36 | DECLARE_WRITE8_MEMBER(port1a_w); |
| 37 | DECLARE_DRIVER_INIT(dsb46); |
| 38 | DECLARE_MACHINE_RESET(dsb46); |
| 39 | private: |
| 38 | 40 | UINT8 m_term_data; |
| 41 | required_device<cpu_device> m_maincpu; |
| 42 | required_device<generic_terminal_device> m_terminal; |
| 39 | 43 | }; |
| 40 | 44 | |
| 41 | 45 | static ADDRESS_MAP_START( dsb46_mem, AS_PROGRAM, 8, dsb46_state ) |
| 42 | | AM_RANGE(0x0000, 0x07ff) AM_ROM AM_REGION("maincpu", 0) |
| 46 | AM_RANGE(0x0000, 0x07ff) AM_READ_BANK("read") AM_WRITE_BANK("write") |
| 43 | 47 | AM_RANGE(0x0800, 0xffff) AM_RAM |
| 44 | 48 | ADDRESS_MAP_END |
| 45 | 49 | |
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| 47 | 51 | ADDRESS_MAP_GLOBAL_MASK(0xff) |
| 48 | 52 | AM_RANGE(0x00, 0x00) AM_READ(port00_r) AM_DEVWRITE(TERMINAL_TAG, generic_terminal_device, write) |
| 49 | 53 | AM_RANGE(0x01, 0x01) AM_READ(port01_r) |
| 50 | | // port 1a bankswitch between rom and ram |
| 54 | AM_RANGE(0x1a, 0x1a) AM_WRITE(port1a_w) |
| 51 | 55 | ADDRESS_MAP_END |
| 52 | 56 | |
| 53 | 57 | static INPUT_PORTS_START( dsb46 ) |
| 54 | 58 | INPUT_PORTS_END |
| 55 | 59 | |
| 60 | DRIVER_INIT_MEMBER(dsb46_state, dsb46) |
| 61 | { |
| 62 | UINT8 *RAM = memregion("maincpu")->base(); |
| 63 | membank("read")->configure_entry(0, &RAM[0x10000]); |
| 64 | membank("read")->configure_entry(1, &RAM[0x00000]); |
| 65 | membank("write")->configure_entry(0, &RAM[0x00000]); |
| 66 | } |
| 67 | |
| 68 | MACHINE_RESET_MEMBER( dsb46_state,dsb46 ) |
| 69 | { |
| 70 | membank("read")->set_entry(0); |
| 71 | membank("write")->set_entry(0); |
| 72 | m_term_data = 0; |
| 73 | m_maincpu->reset(); |
| 74 | } |
| 75 | |
| 76 | WRITE8_MEMBER( dsb46_state::port1a_w ) |
| 77 | { |
| 78 | membank("read")->set_entry(data & 1); |
| 79 | } |
| 80 | |
| 56 | 81 | READ8_MEMBER( dsb46_state::port01_r ) |
| 57 | 82 | { |
| 58 | 83 | return (m_term_data) ? 5 : 4; |
| r24596 | r24597 | |
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| 80 | 105 | MCFG_CPU_ADD("maincpu", Z80, 4000000) |
| 81 | 106 | MCFG_CPU_PROGRAM_MAP(dsb46_mem) |
| 82 | 107 | MCFG_CPU_IO_MAP(dsb46_io) |
| 108 | MCFG_MACHINE_RESET_OVERRIDE(dsb46_state, dsb46) |
| 83 | 109 | |
| 84 | 110 | /* video hardware */ |
| 85 | 111 | MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf) |
| 86 | 112 | MACHINE_CONFIG_END |
| 87 | 113 | |
| 88 | 114 | ROM_START( dsb46 ) |
| 89 | | ROM_REGION( 0x800, "maincpu", 0 ) |
| 90 | | ROM_LOAD( "1538a.bin", 0x000, 0x800, CRC(65b3e26e) SHA1(afe1f03f266b7d13fdb1f1bc6762df5e0aa5c764) ) |
| 115 | ROM_REGION( 0x10800, "maincpu", 0 ) |
| 116 | ROM_LOAD( "1538a.bin", 0x10000, 0x800, CRC(65b3e26e) SHA1(afe1f03f266b7d13fdb1f1bc6762df5e0aa5c764) ) |
| 91 | 117 | |
| 92 | 118 | ROM_REGION( 0x4000, "ades", 0 ) |
| 93 | 119 | ROM_LOAD( "ades.bin", 0x0000, 0x4000, CRC(d374abf0) SHA1(331f51a2bb81375aeffbe63c1ebc1d7cd779b9c3) ) |
| 94 | 120 | ROM_END |
| 95 | 121 | |
| 96 | | COMP( 198?, dsb46, 0, 0, dsb46, dsb46, driver_device, 0, "Davidge", "DSB-4/6", GAME_NOT_WORKING | GAME_NO_SOUND_HW ) |
| 122 | COMP( 198?, dsb46, 0, 0, dsb46, dsb46, dsb46_state, dsb46, "Davidge", "DSB-4/6", GAME_NOT_WORKING | GAME_NO_SOUND_HW ) |